]> Git Repo - qemu.git/blame - vl.h
Fix rfi instruction: do not depend on current execution mode
[qemu.git] / vl.h
CommitLineData
fc01f7e7
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1/*
2 * QEMU System Emulator header
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24#ifndef VL_H
25#define VL_H
26
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27/* we put basic includes here to avoid repeating them in device drivers */
28#include <stdlib.h>
29#include <stdio.h>
30#include <stdarg.h>
31#include <string.h>
32#include <inttypes.h>
85571bc7 33#include <limits.h>
8a7ddc38 34#include <time.h>
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35#include <ctype.h>
36#include <errno.h>
37#include <unistd.h>
38#include <fcntl.h>
7d3505c5 39#include <sys/stat.h>
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40
41#ifndef O_LARGEFILE
42#define O_LARGEFILE 0
43#endif
40c3bac3
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44#ifndef O_BINARY
45#define O_BINARY 0
46#endif
67b915a5 47
71c2fd5c
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48#ifndef ENOMEDIUM
49#define ENOMEDIUM ENODEV
50#endif
2e9671da 51
67b915a5 52#ifdef _WIN32
a18e524a 53#include <windows.h>
ac62f715 54#define fsync _commit
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55#define lseek _lseeki64
56#define ENOTSUP 4096
beac80cd
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57extern int qemu_ftruncate64(int, int64_t);
58#define ftruncate qemu_ftruncate64
59
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60
61static inline char *realpath(const char *path, char *resolved_path)
62{
63 _fullpath(resolved_path, path, _MAX_PATH);
64 return resolved_path;
65}
ec3757de
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66
67#define PRId64 "I64d"
26a76461
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68#define PRIx64 "I64x"
69#define PRIu64 "I64u"
70#define PRIo64 "I64o"
67b915a5 71#endif
8a7ddc38 72
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73#ifdef QEMU_TOOL
74
75/* we use QEMU_TOOL in the command line tools which do not depend on
76 the target CPU type */
77#include "config-host.h"
78#include <setjmp.h>
79#include "osdep.h"
80#include "bswap.h"
81
82#else
83
4f209290 84#include "audio/audio.h"
16f62432
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85#include "cpu.h"
86
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87#endif /* !defined(QEMU_TOOL) */
88
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89#ifndef glue
90#define xglue(x, y) x ## y
91#define glue(x, y) xglue(x, y)
92#define stringify(s) tostring(s)
93#define tostring(s) #s
94#endif
95
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96#ifndef MIN
97#define MIN(a, b) (((a) < (b)) ? (a) : (b))
98#endif
99#ifndef MAX
100#define MAX(a, b) (((a) > (b)) ? (a) : (b))
101#endif
102
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103/* cutils.c */
104void pstrcpy(char *buf, int buf_size, const char *str);
105char *pstrcat(char *buf, int buf_size, const char *s);
106int strstart(const char *str, const char *val, const char **ptr);
107int stristart(const char *str, const char *val, const char **ptr);
108
33e3963e 109/* vl.c */
80cabfad 110uint64_t muldiv64(uint64_t a, uint32_t b, uint32_t c);
313aa567 111
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112void hw_error(const char *fmt, ...);
113
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114extern const char *bios_dir;
115
8a7ddc38 116extern int vm_running;
c35734b2 117extern const char *qemu_name;
8a7ddc38 118
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119typedef struct vm_change_state_entry VMChangeStateEntry;
120typedef void VMChangeStateHandler(void *opaque, int running);
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121typedef void VMStopHandler(void *opaque, int reason);
122
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123VMChangeStateEntry *qemu_add_vm_change_state_handler(VMChangeStateHandler *cb,
124 void *opaque);
125void qemu_del_vm_change_state_handler(VMChangeStateEntry *e);
126
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127int qemu_add_vm_stop_handler(VMStopHandler *cb, void *opaque);
128void qemu_del_vm_stop_handler(VMStopHandler *cb, void *opaque);
129
130void vm_start(void);
131void vm_stop(int reason);
132
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133typedef void QEMUResetHandler(void *opaque);
134
135void qemu_register_reset(QEMUResetHandler *func, void *opaque);
136void qemu_system_reset_request(void);
137void qemu_system_shutdown_request(void);
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138void qemu_system_powerdown_request(void);
139#if !defined(TARGET_SPARC)
140// Please implement a power failure function to signal the OS
141#define qemu_system_powerdown() do{}while(0)
142#else
143void qemu_system_powerdown(void);
144#endif
bb0c6722 145
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146void main_loop_wait(int timeout);
147
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148extern int ram_size;
149extern int bios_size;
ee22c2f7 150extern int rtc_utc;
1f04275e 151extern int cirrus_vga_enabled;
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152extern int graphic_width;
153extern int graphic_height;
154extern int graphic_depth;
3d11d0eb 155extern const char *keyboard_layout;
d993e026 156extern int kqemu_allowed;
a09db21f 157extern int win2k_install_hack;
bb36d470 158extern int usb_enabled;
6a00d601 159extern int smp_cpus;
667accab 160extern int no_quit;
8e71621f 161extern int semihosting_enabled;
3c07f8e8 162extern int autostart;
47d5d01a 163extern const char *bootp_filename;
0ced6589 164
9ae02555
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165#define MAX_OPTION_ROMS 16
166extern const char *option_rom[MAX_OPTION_ROMS];
167extern int nb_option_roms;
168
0ced6589 169/* XXX: make it dynamic */
970ac5a3 170#define MAX_BIOS_SIZE (4 * 1024 * 1024)
75956cf0 171#if defined (TARGET_PPC) || defined (TARGET_SPARC64)
d5295253 172#define BIOS_SIZE ((512 + 32) * 1024)
6af0bf9c 173#elif defined(TARGET_MIPS)
567daa49 174#define BIOS_SIZE (4 * 1024 * 1024)
0ced6589 175#endif
aaaa7df6 176
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177/* keyboard/mouse support */
178
179#define MOUSE_EVENT_LBUTTON 0x01
180#define MOUSE_EVENT_RBUTTON 0x02
181#define MOUSE_EVENT_MBUTTON 0x04
182
183typedef void QEMUPutKBDEvent(void *opaque, int keycode);
184typedef void QEMUPutMouseEvent(void *opaque, int dx, int dy, int dz, int buttons_state);
185
455204eb
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186typedef struct QEMUPutMouseEntry {
187 QEMUPutMouseEvent *qemu_put_mouse_event;
188 void *qemu_put_mouse_event_opaque;
189 int qemu_put_mouse_event_absolute;
190 char *qemu_put_mouse_event_name;
191
192 /* used internally by qemu for handling mice */
193 struct QEMUPutMouseEntry *next;
194} QEMUPutMouseEntry;
195
63066f4f 196void qemu_add_kbd_event_handler(QEMUPutKBDEvent *func, void *opaque);
455204eb
TS
197QEMUPutMouseEntry *qemu_add_mouse_event_handler(QEMUPutMouseEvent *func,
198 void *opaque, int absolute,
199 const char *name);
200void qemu_remove_mouse_event_handler(QEMUPutMouseEntry *entry);
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201
202void kbd_put_keycode(int keycode);
203void kbd_mouse_event(int dx, int dy, int dz, int buttons_state);
09b26c5e 204int kbd_mouse_is_absolute(void);
63066f4f 205
455204eb
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206void do_info_mice(void);
207void do_mouse_set(int index);
208
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209/* keysym is a unicode code except for special keys (see QEMU_KEY_xxx
210 constants) */
211#define QEMU_KEY_ESC1(c) ((c) | 0xe100)
212#define QEMU_KEY_BACKSPACE 0x007f
213#define QEMU_KEY_UP QEMU_KEY_ESC1('A')
214#define QEMU_KEY_DOWN QEMU_KEY_ESC1('B')
215#define QEMU_KEY_RIGHT QEMU_KEY_ESC1('C')
216#define QEMU_KEY_LEFT QEMU_KEY_ESC1('D')
217#define QEMU_KEY_HOME QEMU_KEY_ESC1(1)
218#define QEMU_KEY_END QEMU_KEY_ESC1(4)
219#define QEMU_KEY_PAGEUP QEMU_KEY_ESC1(5)
220#define QEMU_KEY_PAGEDOWN QEMU_KEY_ESC1(6)
221#define QEMU_KEY_DELETE QEMU_KEY_ESC1(3)
222
223#define QEMU_KEY_CTRL_UP 0xe400
224#define QEMU_KEY_CTRL_DOWN 0xe401
225#define QEMU_KEY_CTRL_LEFT 0xe402
226#define QEMU_KEY_CTRL_RIGHT 0xe403
227#define QEMU_KEY_CTRL_HOME 0xe404
228#define QEMU_KEY_CTRL_END 0xe405
229#define QEMU_KEY_CTRL_PAGEUP 0xe406
230#define QEMU_KEY_CTRL_PAGEDOWN 0xe407
231
232void kbd_put_keysym(int keysym);
233
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234/* async I/O support */
235
236typedef void IOReadHandler(void *opaque, const uint8_t *buf, int size);
237typedef int IOCanRWHandler(void *opaque);
7c9d8e07 238typedef void IOHandler(void *opaque);
c20709aa 239
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240int qemu_set_fd_handler2(int fd,
241 IOCanRWHandler *fd_read_poll,
242 IOHandler *fd_read,
243 IOHandler *fd_write,
244 void *opaque);
245int qemu_set_fd_handler(int fd,
246 IOHandler *fd_read,
247 IOHandler *fd_write,
248 void *opaque);
c20709aa 249
f331110f
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250/* Polling handling */
251
252/* return TRUE if no sleep should be done afterwards */
253typedef int PollingFunc(void *opaque);
254
255int qemu_add_polling_cb(PollingFunc *func, void *opaque);
256void qemu_del_polling_cb(PollingFunc *func, void *opaque);
257
a18e524a
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258#ifdef _WIN32
259/* Wait objects handling */
260typedef void WaitObjectFunc(void *opaque);
261
262int qemu_add_wait_object(HANDLE handle, WaitObjectFunc *func, void *opaque);
263void qemu_del_wait_object(HANDLE handle, WaitObjectFunc *func, void *opaque);
264#endif
265
86e94dea
TS
266typedef struct QEMUBH QEMUBH;
267
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268/* character device */
269
270#define CHR_EVENT_BREAK 0 /* serial break char */
ea2384d3 271#define CHR_EVENT_FOCUS 1 /* focus to this terminal (modal input needed) */
86e94dea 272#define CHR_EVENT_RESET 2 /* new connection established */
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273
274
275#define CHR_IOCTL_SERIAL_SET_PARAMS 1
276typedef struct {
277 int speed;
278 int parity;
279 int data_bits;
280 int stop_bits;
281} QEMUSerialSetParams;
282
283#define CHR_IOCTL_SERIAL_SET_BREAK 2
284
285#define CHR_IOCTL_PP_READ_DATA 3
286#define CHR_IOCTL_PP_WRITE_DATA 4
287#define CHR_IOCTL_PP_READ_CONTROL 5
288#define CHR_IOCTL_PP_WRITE_CONTROL 6
289#define CHR_IOCTL_PP_READ_STATUS 7
5867c88a
TS
290#define CHR_IOCTL_PP_EPP_READ_ADDR 8
291#define CHR_IOCTL_PP_EPP_READ 9
292#define CHR_IOCTL_PP_EPP_WRITE_ADDR 10
293#define CHR_IOCTL_PP_EPP_WRITE 11
2122c51a 294
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295typedef void IOEventHandler(void *opaque, int event);
296
297typedef struct CharDriverState {
298 int (*chr_write)(struct CharDriverState *s, const uint8_t *buf, int len);
e5b0bc44 299 void (*chr_update_read_handler)(struct CharDriverState *s);
2122c51a 300 int (*chr_ioctl)(struct CharDriverState *s, int cmd, void *arg);
82c643ff 301 IOEventHandler *chr_event;
e5b0bc44
PB
302 IOCanRWHandler *chr_can_read;
303 IOReadHandler *chr_read;
304 void *handler_opaque;
eb45f5fe 305 void (*chr_send_event)(struct CharDriverState *chr, int event);
f331110f 306 void (*chr_close)(struct CharDriverState *chr);
82c643ff 307 void *opaque;
20d8a3ed 308 int focus;
86e94dea 309 QEMUBH *bh;
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310} CharDriverState;
311
5856de80 312CharDriverState *qemu_chr_open(const char *filename);
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313void qemu_chr_printf(CharDriverState *s, const char *fmt, ...);
314int qemu_chr_write(CharDriverState *s, const uint8_t *buf, int len);
ea2384d3 315void qemu_chr_send_event(CharDriverState *s, int event);
e5b0bc44
PB
316void qemu_chr_add_handlers(CharDriverState *s,
317 IOCanRWHandler *fd_can_read,
318 IOReadHandler *fd_read,
319 IOEventHandler *fd_event,
320 void *opaque);
2122c51a 321int qemu_chr_ioctl(CharDriverState *s, int cmd, void *arg);
86e94dea 322void qemu_chr_reset(CharDriverState *s);
e5b0bc44
PB
323int qemu_chr_can_read(CharDriverState *s);
324void qemu_chr_read(CharDriverState *s, uint8_t *buf, int len);
f8d179e3 325
82c643ff
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326/* consoles */
327
328typedef struct DisplayState DisplayState;
329typedef struct TextConsole TextConsole;
330
95219897
PB
331typedef void (*vga_hw_update_ptr)(void *);
332typedef void (*vga_hw_invalidate_ptr)(void *);
333typedef void (*vga_hw_screen_dump_ptr)(void *, const char *);
334
335TextConsole *graphic_console_init(DisplayState *ds, vga_hw_update_ptr update,
336 vga_hw_invalidate_ptr invalidate,
337 vga_hw_screen_dump_ptr screen_dump,
338 void *opaque);
339void vga_hw_update(void);
340void vga_hw_invalidate(void);
341void vga_hw_screen_dump(const char *filename);
342
343int is_graphic_console(void);
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344CharDriverState *text_console_init(DisplayState *ds);
345void console_select(unsigned int index);
346
8d11df9e
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347/* serial ports */
348
349#define MAX_SERIAL_PORTS 4
350
351extern CharDriverState *serial_hds[MAX_SERIAL_PORTS];
352
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353/* parallel ports */
354
355#define MAX_PARALLEL_PORTS 3
356
357extern CharDriverState *parallel_hds[MAX_PARALLEL_PORTS];
358
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359struct ParallelIOArg {
360 void *buffer;
361 int count;
362};
363
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364/* VLANs support */
365
366typedef struct VLANClientState VLANClientState;
367
368struct VLANClientState {
369 IOReadHandler *fd_read;
d861b05e
PB
370 /* Packets may still be sent if this returns zero. It's used to
371 rate-limit the slirp code. */
372 IOCanRWHandler *fd_can_read;
7c9d8e07
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373 void *opaque;
374 struct VLANClientState *next;
375 struct VLANState *vlan;
376 char info_str[256];
377};
378
379typedef struct VLANState {
380 int id;
381 VLANClientState *first_client;
382 struct VLANState *next;
383} VLANState;
384
385VLANState *qemu_find_vlan(int id);
386VLANClientState *qemu_new_vlan_client(VLANState *vlan,
d861b05e
PB
387 IOReadHandler *fd_read,
388 IOCanRWHandler *fd_can_read,
389 void *opaque);
390int qemu_can_send_packet(VLANClientState *vc);
7c9d8e07 391void qemu_send_packet(VLANClientState *vc, const uint8_t *buf, int size);
d861b05e 392void qemu_handler_true(void *opaque);
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393
394void do_info_network(void);
395
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396/* TAP win32 */
397int tap_win32_init(VLANState *vlan, const char *ifname);
7fb843f8 398
7c9d8e07 399/* NIC info */
c4b1fcc0
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400
401#define MAX_NICS 8
402
7c9d8e07 403typedef struct NICInfo {
c4b1fcc0 404 uint8_t macaddr[6];
a41b2ff2 405 const char *model;
7c9d8e07
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406 VLANState *vlan;
407} NICInfo;
c4b1fcc0
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408
409extern int nb_nics;
7c9d8e07 410extern NICInfo nd_table[MAX_NICS];
8a7ddc38
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411
412/* timers */
413
414typedef struct QEMUClock QEMUClock;
415typedef struct QEMUTimer QEMUTimer;
416typedef void QEMUTimerCB(void *opaque);
417
418/* The real time clock should be used only for stuff which does not
419 change the virtual machine state, as it is run even if the virtual
69b91039 420 machine is stopped. The real time clock has a frequency of 1000
8a7ddc38
FB
421 Hz. */
422extern QEMUClock *rt_clock;
423
e80cfcfc 424/* The virtual clock is only run during the emulation. It is stopped
8a7ddc38
FB
425 when the virtual machine is stopped. Virtual timers use a high
426 precision clock, usually cpu cycles (use ticks_per_sec). */
427extern QEMUClock *vm_clock;
428
429int64_t qemu_get_clock(QEMUClock *clock);
430
431QEMUTimer *qemu_new_timer(QEMUClock *clock, QEMUTimerCB *cb, void *opaque);
432void qemu_free_timer(QEMUTimer *ts);
433void qemu_del_timer(QEMUTimer *ts);
434void qemu_mod_timer(QEMUTimer *ts, int64_t expire_time);
435int qemu_timer_pending(QEMUTimer *ts);
436
437extern int64_t ticks_per_sec;
438extern int pit_min_timer_count;
439
1dce7c3c 440int64_t cpu_get_ticks(void);
8a7ddc38
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441void cpu_enable_ticks(void);
442void cpu_disable_ticks(void);
443
444/* VM Load/Save */
445
faea38e7 446typedef struct QEMUFile QEMUFile;
8a7ddc38 447
faea38e7
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448QEMUFile *qemu_fopen(const char *filename, const char *mode);
449void qemu_fflush(QEMUFile *f);
450void qemu_fclose(QEMUFile *f);
8a7ddc38
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451void qemu_put_buffer(QEMUFile *f, const uint8_t *buf, int size);
452void qemu_put_byte(QEMUFile *f, int v);
453void qemu_put_be16(QEMUFile *f, unsigned int v);
454void qemu_put_be32(QEMUFile *f, unsigned int v);
455void qemu_put_be64(QEMUFile *f, uint64_t v);
456int qemu_get_buffer(QEMUFile *f, uint8_t *buf, int size);
457int qemu_get_byte(QEMUFile *f);
458unsigned int qemu_get_be16(QEMUFile *f);
459unsigned int qemu_get_be32(QEMUFile *f);
460uint64_t qemu_get_be64(QEMUFile *f);
461
462static inline void qemu_put_be64s(QEMUFile *f, const uint64_t *pv)
463{
464 qemu_put_be64(f, *pv);
465}
466
467static inline void qemu_put_be32s(QEMUFile *f, const uint32_t *pv)
468{
469 qemu_put_be32(f, *pv);
470}
471
472static inline void qemu_put_be16s(QEMUFile *f, const uint16_t *pv)
473{
474 qemu_put_be16(f, *pv);
475}
476
477static inline void qemu_put_8s(QEMUFile *f, const uint8_t *pv)
478{
479 qemu_put_byte(f, *pv);
480}
481
482static inline void qemu_get_be64s(QEMUFile *f, uint64_t *pv)
483{
484 *pv = qemu_get_be64(f);
485}
486
487static inline void qemu_get_be32s(QEMUFile *f, uint32_t *pv)
488{
489 *pv = qemu_get_be32(f);
490}
491
492static inline void qemu_get_be16s(QEMUFile *f, uint16_t *pv)
493{
494 *pv = qemu_get_be16(f);
495}
496
497static inline void qemu_get_8s(QEMUFile *f, uint8_t *pv)
498{
499 *pv = qemu_get_byte(f);
500}
501
c27004ec
FB
502#if TARGET_LONG_BITS == 64
503#define qemu_put_betl qemu_put_be64
504#define qemu_get_betl qemu_get_be64
505#define qemu_put_betls qemu_put_be64s
506#define qemu_get_betls qemu_get_be64s
507#else
508#define qemu_put_betl qemu_put_be32
509#define qemu_get_betl qemu_get_be32
510#define qemu_put_betls qemu_put_be32s
511#define qemu_get_betls qemu_get_be32s
512#endif
513
8a7ddc38
FB
514int64_t qemu_ftell(QEMUFile *f);
515int64_t qemu_fseek(QEMUFile *f, int64_t pos, int whence);
516
517typedef void SaveStateHandler(QEMUFile *f, void *opaque);
518typedef int LoadStateHandler(QEMUFile *f, void *opaque, int version_id);
519
8a7ddc38
FB
520int register_savevm(const char *idstr,
521 int instance_id,
522 int version_id,
523 SaveStateHandler *save_state,
524 LoadStateHandler *load_state,
525 void *opaque);
526void qemu_get_timer(QEMUFile *f, QEMUTimer *ts);
527void qemu_put_timer(QEMUFile *f, QEMUTimer *ts);
c4b1fcc0 528
6a00d601
FB
529void cpu_save(QEMUFile *f, void *opaque);
530int cpu_load(QEMUFile *f, void *opaque, int version_id);
531
faea38e7
FB
532void do_savevm(const char *name);
533void do_loadvm(const char *name);
534void do_delvm(const char *name);
535void do_info_snapshots(void);
536
83f64091 537/* bottom halves */
83f64091
FB
538typedef void QEMUBHFunc(void *opaque);
539
540QEMUBH *qemu_bh_new(QEMUBHFunc *cb, void *opaque);
541void qemu_bh_schedule(QEMUBH *bh);
542void qemu_bh_cancel(QEMUBH *bh);
543void qemu_bh_delete(QEMUBH *bh);
6eb5733a 544int qemu_bh_poll(void);
83f64091 545
fc01f7e7
FB
546/* block.c */
547typedef struct BlockDriverState BlockDriverState;
ea2384d3
FB
548typedef struct BlockDriver BlockDriver;
549
550extern BlockDriver bdrv_raw;
19cb3738 551extern BlockDriver bdrv_host_device;
ea2384d3
FB
552extern BlockDriver bdrv_cow;
553extern BlockDriver bdrv_qcow;
554extern BlockDriver bdrv_vmdk;
3c56521b 555extern BlockDriver bdrv_cloop;
585d0ed9 556extern BlockDriver bdrv_dmg;
a8753c34 557extern BlockDriver bdrv_bochs;
6a0f9e82 558extern BlockDriver bdrv_vpc;
de167e41 559extern BlockDriver bdrv_vvfat;
faea38e7
FB
560extern BlockDriver bdrv_qcow2;
561
562typedef struct BlockDriverInfo {
563 /* in bytes, 0 if irrelevant */
564 int cluster_size;
565 /* offset at which the VM state can be saved (0 if not possible) */
566 int64_t vm_state_offset;
567} BlockDriverInfo;
568
569typedef struct QEMUSnapshotInfo {
570 char id_str[128]; /* unique snapshot id */
571 /* the following fields are informative. They are not needed for
572 the consistency of the snapshot */
573 char name[256]; /* user choosen name */
574 uint32_t vm_state_size; /* VM state info size */
575 uint32_t date_sec; /* UTC date of the snapshot */
576 uint32_t date_nsec;
577 uint64_t vm_clock_nsec; /* VM clock relative to boot */
578} QEMUSnapshotInfo;
ea2384d3 579
83f64091
FB
580#define BDRV_O_RDONLY 0x0000
581#define BDRV_O_RDWR 0x0002
582#define BDRV_O_ACCESS 0x0003
583#define BDRV_O_CREAT 0x0004 /* create an empty file */
584#define BDRV_O_SNAPSHOT 0x0008 /* open the file read only and save writes in a snapshot */
585#define BDRV_O_FILE 0x0010 /* open as a raw file (do not try to
586 use a disk image format on top of
587 it (default for
588 bdrv_file_open()) */
589
ea2384d3
FB
590void bdrv_init(void);
591BlockDriver *bdrv_find_format(const char *format_name);
592int bdrv_create(BlockDriver *drv,
593 const char *filename, int64_t size_in_sectors,
594 const char *backing_file, int flags);
c4b1fcc0
FB
595BlockDriverState *bdrv_new(const char *device_name);
596void bdrv_delete(BlockDriverState *bs);
83f64091
FB
597int bdrv_file_open(BlockDriverState **pbs, const char *filename, int flags);
598int bdrv_open(BlockDriverState *bs, const char *filename, int flags);
599int bdrv_open2(BlockDriverState *bs, const char *filename, int flags,
ea2384d3 600 BlockDriver *drv);
fc01f7e7
FB
601void bdrv_close(BlockDriverState *bs);
602int bdrv_read(BlockDriverState *bs, int64_t sector_num,
603 uint8_t *buf, int nb_sectors);
604int bdrv_write(BlockDriverState *bs, int64_t sector_num,
605 const uint8_t *buf, int nb_sectors);
83f64091
FB
606int bdrv_pread(BlockDriverState *bs, int64_t offset,
607 void *buf, int count);
608int bdrv_pwrite(BlockDriverState *bs, int64_t offset,
609 const void *buf, int count);
610int bdrv_truncate(BlockDriverState *bs, int64_t offset);
611int64_t bdrv_getlength(BlockDriverState *bs);
fc01f7e7 612void bdrv_get_geometry(BlockDriverState *bs, int64_t *nb_sectors_ptr);
33e3963e 613int bdrv_commit(BlockDriverState *bs);
77fef8c1 614void bdrv_set_boot_sector(BlockDriverState *bs, const uint8_t *data, int size);
83f64091
FB
615/* async block I/O */
616typedef struct BlockDriverAIOCB BlockDriverAIOCB;
617typedef void BlockDriverCompletionFunc(void *opaque, int ret);
618
ce1a14dc
PB
619BlockDriverAIOCB *bdrv_aio_read(BlockDriverState *bs, int64_t sector_num,
620 uint8_t *buf, int nb_sectors,
621 BlockDriverCompletionFunc *cb, void *opaque);
622BlockDriverAIOCB *bdrv_aio_write(BlockDriverState *bs, int64_t sector_num,
623 const uint8_t *buf, int nb_sectors,
624 BlockDriverCompletionFunc *cb, void *opaque);
83f64091 625void bdrv_aio_cancel(BlockDriverAIOCB *acb);
83f64091
FB
626
627void qemu_aio_init(void);
628void qemu_aio_poll(void);
6192bc37 629void qemu_aio_flush(void);
83f64091
FB
630void qemu_aio_wait_start(void);
631void qemu_aio_wait(void);
632void qemu_aio_wait_end(void);
633
7a6cba61
PB
634/* Ensure contents are flushed to disk. */
635void bdrv_flush(BlockDriverState *bs);
33e3963e 636
c4b1fcc0
FB
637#define BDRV_TYPE_HD 0
638#define BDRV_TYPE_CDROM 1
639#define BDRV_TYPE_FLOPPY 2
4dbb0f50
TS
640#define BIOS_ATA_TRANSLATION_AUTO 0
641#define BIOS_ATA_TRANSLATION_NONE 1
642#define BIOS_ATA_TRANSLATION_LBA 2
643#define BIOS_ATA_TRANSLATION_LARGE 3
644#define BIOS_ATA_TRANSLATION_RECHS 4
c4b1fcc0
FB
645
646void bdrv_set_geometry_hint(BlockDriverState *bs,
647 int cyls, int heads, int secs);
648void bdrv_set_type_hint(BlockDriverState *bs, int type);
46d4767d 649void bdrv_set_translation_hint(BlockDriverState *bs, int translation);
c4b1fcc0
FB
650void bdrv_get_geometry_hint(BlockDriverState *bs,
651 int *pcyls, int *pheads, int *psecs);
652int bdrv_get_type_hint(BlockDriverState *bs);
46d4767d 653int bdrv_get_translation_hint(BlockDriverState *bs);
c4b1fcc0
FB
654int bdrv_is_removable(BlockDriverState *bs);
655int bdrv_is_read_only(BlockDriverState *bs);
656int bdrv_is_inserted(BlockDriverState *bs);
19cb3738 657int bdrv_media_changed(BlockDriverState *bs);
c4b1fcc0
FB
658int bdrv_is_locked(BlockDriverState *bs);
659void bdrv_set_locked(BlockDriverState *bs, int locked);
19cb3738 660void bdrv_eject(BlockDriverState *bs, int eject_flag);
c4b1fcc0
FB
661void bdrv_set_change_cb(BlockDriverState *bs,
662 void (*change_cb)(void *opaque), void *opaque);
ea2384d3 663void bdrv_get_format(BlockDriverState *bs, char *buf, int buf_size);
c4b1fcc0
FB
664void bdrv_info(void);
665BlockDriverState *bdrv_find(const char *name);
82c643ff 666void bdrv_iterate(void (*it)(void *opaque, const char *name), void *opaque);
ea2384d3
FB
667int bdrv_is_encrypted(BlockDriverState *bs);
668int bdrv_set_key(BlockDriverState *bs, const char *key);
669void bdrv_iterate_format(void (*it)(void *opaque, const char *name),
670 void *opaque);
671const char *bdrv_get_device_name(BlockDriverState *bs);
faea38e7
FB
672int bdrv_write_compressed(BlockDriverState *bs, int64_t sector_num,
673 const uint8_t *buf, int nb_sectors);
674int bdrv_get_info(BlockDriverState *bs, BlockDriverInfo *bdi);
c4b1fcc0 675
83f64091
FB
676void bdrv_get_backing_filename(BlockDriverState *bs,
677 char *filename, int filename_size);
faea38e7
FB
678int bdrv_snapshot_create(BlockDriverState *bs,
679 QEMUSnapshotInfo *sn_info);
680int bdrv_snapshot_goto(BlockDriverState *bs,
681 const char *snapshot_id);
682int bdrv_snapshot_delete(BlockDriverState *bs, const char *snapshot_id);
683int bdrv_snapshot_list(BlockDriverState *bs,
684 QEMUSnapshotInfo **psn_info);
685char *bdrv_snapshot_dump(char *buf, int buf_size, QEMUSnapshotInfo *sn);
686
687char *get_human_readable_size(char *buf, int buf_size, int64_t size);
83f64091
FB
688int path_is_absolute(const char *path);
689void path_combine(char *dest, int dest_size,
690 const char *base_path,
691 const char *filename);
ea2384d3
FB
692
693#ifndef QEMU_TOOL
54fa5af5
FB
694
695typedef void QEMUMachineInitFunc(int ram_size, int vga_ram_size,
696 int boot_device,
697 DisplayState *ds, const char **fd_filename, int snapshot,
698 const char *kernel_filename, const char *kernel_cmdline,
94fc95cd 699 const char *initrd_filename, const char *cpu_model);
54fa5af5
FB
700
701typedef struct QEMUMachine {
702 const char *name;
703 const char *desc;
704 QEMUMachineInitFunc *init;
705 struct QEMUMachine *next;
706} QEMUMachine;
707
708int qemu_register_machine(QEMUMachine *m);
709
710typedef void SetIRQFunc(void *opaque, int irq_num, int level);
3de388f6 711typedef void IRQRequestFunc(void *opaque, int level);
54fa5af5 712
94fc95cd
JM
713#if defined(TARGET_PPC)
714void ppc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
715#endif
716
33d68b5f
TS
717#if defined(TARGET_MIPS)
718void mips_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
719#endif
720
26aa7d72
FB
721/* ISA bus */
722
723extern target_phys_addr_t isa_mem_base;
724
725typedef void (IOPortWriteFunc)(void *opaque, uint32_t address, uint32_t data);
726typedef uint32_t (IOPortReadFunc)(void *opaque, uint32_t address);
727
728int register_ioport_read(int start, int length, int size,
729 IOPortReadFunc *func, void *opaque);
730int register_ioport_write(int start, int length, int size,
731 IOPortWriteFunc *func, void *opaque);
69b91039
FB
732void isa_unassign_ioport(int start, int length);
733
aef445bd
PB
734void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size);
735
69b91039
FB
736/* PCI bus */
737
69b91039
FB
738extern target_phys_addr_t pci_mem_base;
739
46e50e9d 740typedef struct PCIBus PCIBus;
69b91039
FB
741typedef struct PCIDevice PCIDevice;
742
743typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
744 uint32_t address, uint32_t data, int len);
745typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
746 uint32_t address, int len);
747typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
748 uint32_t addr, uint32_t size, int type);
749
750#define PCI_ADDRESS_SPACE_MEM 0x00
751#define PCI_ADDRESS_SPACE_IO 0x01
752#define PCI_ADDRESS_SPACE_MEM_PREFETCH 0x08
753
754typedef struct PCIIORegion {
5768f5ac 755 uint32_t addr; /* current PCI mapping address. -1 means not mapped */
69b91039
FB
756 uint32_t size;
757 uint8_t type;
758 PCIMapIORegionFunc *map_func;
759} PCIIORegion;
760
8a8696a3
FB
761#define PCI_ROM_SLOT 6
762#define PCI_NUM_REGIONS 7
502a5395
PB
763
764#define PCI_DEVICES_MAX 64
765
766#define PCI_VENDOR_ID 0x00 /* 16 bits */
767#define PCI_DEVICE_ID 0x02 /* 16 bits */
768#define PCI_COMMAND 0x04 /* 16 bits */
769#define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
770#define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
771#define PCI_CLASS_DEVICE 0x0a /* Device class */
772#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
773#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
774#define PCI_MIN_GNT 0x3e /* 8 bits */
775#define PCI_MAX_LAT 0x3f /* 8 bits */
776
69b91039
FB
777struct PCIDevice {
778 /* PCI config space */
779 uint8_t config[256];
780
781 /* the following fields are read only */
46e50e9d 782 PCIBus *bus;
69b91039
FB
783 int devfn;
784 char name[64];
8a8696a3 785 PCIIORegion io_regions[PCI_NUM_REGIONS];
69b91039
FB
786
787 /* do not access the following fields */
788 PCIConfigReadFunc *config_read;
789 PCIConfigWriteFunc *config_write;
502a5395 790 /* ??? This is a PC-specific hack, and should be removed. */
5768f5ac 791 int irq_index;
d2b59317
PB
792
793 /* Current IRQ levels. Used internally by the generic PCI code. */
794 int irq_state[4];
69b91039
FB
795};
796
46e50e9d
FB
797PCIDevice *pci_register_device(PCIBus *bus, const char *name,
798 int instance_size, int devfn,
69b91039
FB
799 PCIConfigReadFunc *config_read,
800 PCIConfigWriteFunc *config_write);
801
802void pci_register_io_region(PCIDevice *pci_dev, int region_num,
803 uint32_t size, int type,
804 PCIMapIORegionFunc *map_func);
805
5768f5ac
FB
806void pci_set_irq(PCIDevice *pci_dev, int irq_num, int level);
807
808uint32_t pci_default_read_config(PCIDevice *d,
809 uint32_t address, int len);
810void pci_default_write_config(PCIDevice *d,
811 uint32_t address, uint32_t val, int len);
89b6b508
FB
812void pci_device_save(PCIDevice *s, QEMUFile *f);
813int pci_device_load(PCIDevice *s, QEMUFile *f);
5768f5ac 814
d2b59317
PB
815typedef void (*pci_set_irq_fn)(void *pic, int irq_num, int level);
816typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
817PCIBus *pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
80b3ada7 818 void *pic, int devfn_min, int nirq);
502a5395 819
abcebc7e 820void pci_nic_init(PCIBus *bus, NICInfo *nd, int devfn);
502a5395
PB
821void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len);
822uint32_t pci_data_read(void *opaque, uint32_t addr, int len);
823int pci_bus_num(PCIBus *s);
80b3ada7 824void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d));
9995c51f 825
5768f5ac 826void pci_info(void);
80b3ada7
PB
827PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint32_t id,
828 pci_map_irq_fn map_irq, const char *name);
26aa7d72 829
502a5395 830/* prep_pci.c */
46e50e9d 831PCIBus *pci_prep_init(void);
77d4bc34 832
502a5395
PB
833/* grackle_pci.c */
834PCIBus *pci_grackle_init(uint32_t base, void *pic);
835
836/* unin_pci.c */
837PCIBus *pci_pmac_init(void *pic);
838
839/* apb_pci.c */
840PCIBus *pci_apb_init(target_ulong special_base, target_ulong mem_base,
841 void *pic);
842
e69954b9 843PCIBus *pci_vpb_init(void *pic, int irq, int realview);
502a5395
PB
844
845/* piix_pci.c */
f00fc47c
FB
846PCIBus *i440fx_init(PCIDevice **pi440fx_state);
847void i440fx_set_smm(PCIDevice *d, int val);
8f1c91d8 848int piix3_init(PCIBus *bus, int devfn);
f00fc47c 849void i440fx_init_memory_mappings(PCIDevice *d);
a41b2ff2 850
5856de80
TS
851int piix4_init(PCIBus *bus, int devfn);
852
28b9b5af
FB
853/* openpic.c */
854typedef struct openpic_t openpic_t;
47103572
JM
855enum {
856 OPENPIC_EVT_INT = 0, /* IRQ */
857 OPENPIC_EVT_CINT, /* critical IRQ */
858 OPENPIC_EVT_MCK, /* Machine check event */
859 OPENPIC_EVT_DEBUG, /* Inconditional debug event */
860 OPENPIC_EVT_RESET, /* Core reset event */
861};
54fa5af5 862void openpic_set_irq(void *opaque, int n_IRQ, int level);
47103572
JM
863openpic_t *openpic_init (PCIBus *bus, SetIRQFunc *set_irq,
864 int *pmem_index, int nb_cpus, CPUPPCState **envp);
28b9b5af 865
54fa5af5
FB
866/* heathrow_pic.c */
867typedef struct HeathrowPICS HeathrowPICS;
868void heathrow_pic_set_irq(void *opaque, int num, int level);
869HeathrowPICS *heathrow_pic_init(int *pmem_index);
870
fde7d5bd
TS
871/* gt64xxx.c */
872PCIBus *pci_gt64120_init(void *pic);
873
6a36d84e
FB
874#ifdef HAS_AUDIO
875struct soundhw {
876 const char *name;
877 const char *descr;
878 int enabled;
879 int isa;
880 union {
881 int (*init_isa) (AudioState *s);
882 int (*init_pci) (PCIBus *bus, AudioState *s);
883 } init;
884};
885
886extern struct soundhw soundhw[];
887#endif
888
313aa567
FB
889/* vga.c */
890
74a14f22 891#define VGA_RAM_SIZE (8192 * 1024)
313aa567 892
82c643ff 893struct DisplayState {
313aa567
FB
894 uint8_t *data;
895 int linesize;
896 int depth;
d3079cd2 897 int bgr; /* BGR color order instead of RGB. Only valid for depth == 32 */
82c643ff
FB
898 int width;
899 int height;
24236869
FB
900 void *opaque;
901
313aa567
FB
902 void (*dpy_update)(struct DisplayState *s, int x, int y, int w, int h);
903 void (*dpy_resize)(struct DisplayState *s, int w, int h);
904 void (*dpy_refresh)(struct DisplayState *s);
24236869 905 void (*dpy_copy)(struct DisplayState *s, int src_x, int src_y, int dst_x, int dst_y, int w, int h);
82c643ff 906};
313aa567
FB
907
908static inline void dpy_update(DisplayState *s, int x, int y, int w, int h)
909{
910 s->dpy_update(s, x, y, w, h);
911}
912
913static inline void dpy_resize(DisplayState *s, int w, int h)
914{
915 s->dpy_resize(s, w, h);
916}
917
89b6b508
FB
918int isa_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
919 unsigned long vga_ram_offset, int vga_ram_size);
920int pci_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
921 unsigned long vga_ram_offset, int vga_ram_size,
922 unsigned long vga_bios_offset, int vga_bios_size);
313aa567 923
d6bfa22f 924/* cirrus_vga.c */
46e50e9d 925void pci_cirrus_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
d6bfa22f 926 unsigned long vga_ram_offset, int vga_ram_size);
d6bfa22f
FB
927void isa_cirrus_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
928 unsigned long vga_ram_offset, int vga_ram_size);
929
313aa567 930/* sdl.c */
43523e93 931void sdl_display_init(DisplayState *ds, int full_screen, int no_frame);
313aa567 932
da4dbf74
FB
933/* cocoa.m */
934void cocoa_display_init(DisplayState *ds, int full_screen);
935
24236869 936/* vnc.c */
73fc9742 937void vnc_display_init(DisplayState *ds, const char *display);
a9ce8590 938void do_info_vnc(void);
24236869 939
6070dd07
TS
940/* x_keymap.c */
941extern uint8_t _translate_keycode(const int key);
942
5391d806
FB
943/* ide.c */
944#define MAX_DISKS 4
945
faea38e7 946extern BlockDriverState *bs_table[MAX_DISKS + 1];
5391d806 947
69b91039
FB
948void isa_ide_init(int iobase, int iobase2, int irq,
949 BlockDriverState *hd0, BlockDriverState *hd1);
54fa5af5
FB
950void pci_cmd646_ide_init(PCIBus *bus, BlockDriverState **hd_table,
951 int secondary_ide_enabled);
502a5395 952void pci_piix3_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn);
28b9b5af 953int pmac_ide_init (BlockDriverState **hd_table,
54fa5af5 954 SetIRQFunc *set_irq, void *irq_opaque, int irq);
5391d806 955
2e5d83bb
PB
956/* cdrom.c */
957int cdrom_read_toc(int nb_sectors, uint8_t *buf, int msf, int start_track);
958int cdrom_read_toc_raw(int nb_sectors, uint8_t *buf, int msf, int session_num);
959
9542611a
TS
960/* ds1225y.c */
961typedef struct ds1225y_t ds1225y_t;
962ds1225y_t *ds1225y_init(target_ulong mem_base, const char *filename);
963
1d14ffa9 964/* es1370.c */
c0fe3827 965int es1370_init (PCIBus *bus, AudioState *s);
1d14ffa9 966
fb065187 967/* sb16.c */
c0fe3827 968int SB16_init (AudioState *s);
fb065187
FB
969
970/* adlib.c */
c0fe3827 971int Adlib_init (AudioState *s);
fb065187
FB
972
973/* gus.c */
c0fe3827 974int GUS_init (AudioState *s);
27503323
FB
975
976/* dma.c */
85571bc7 977typedef int (*DMA_transfer_handler) (void *opaque, int nchan, int pos, int size);
27503323 978int DMA_get_channel_mode (int nchan);
85571bc7
FB
979int DMA_read_memory (int nchan, void *buf, int pos, int size);
980int DMA_write_memory (int nchan, void *buf, int pos, int size);
27503323
FB
981void DMA_hold_DREQ (int nchan);
982void DMA_release_DREQ (int nchan);
16f62432 983void DMA_schedule(int nchan);
27503323 984void DMA_run (void);
28b9b5af 985void DMA_init (int high_page_enable);
27503323 986void DMA_register_channel (int nchan,
85571bc7
FB
987 DMA_transfer_handler transfer_handler,
988 void *opaque);
7138fcfb
FB
989/* fdc.c */
990#define MAX_FD 2
991extern BlockDriverState *fd_table[MAX_FD];
992
baca51fa
FB
993typedef struct fdctrl_t fdctrl_t;
994
995fdctrl_t *fdctrl_init (int irq_lvl, int dma_chann, int mem_mapped,
996 uint32_t io_base,
997 BlockDriverState **fds);
998int fdctrl_get_drive_type(fdctrl_t *fdctrl, int drive_num);
7138fcfb 999
80cabfad
FB
1000/* ne2000.c */
1001
7c9d8e07 1002void isa_ne2000_init(int base, int irq, NICInfo *nd);
abcebc7e 1003void pci_ne2000_init(PCIBus *bus, NICInfo *nd, int devfn);
80cabfad 1004
a41b2ff2
PB
1005/* rtl8139.c */
1006
abcebc7e 1007void pci_rtl8139_init(PCIBus *bus, NICInfo *nd, int devfn);
a41b2ff2 1008
e3c2613f
FB
1009/* pcnet.c */
1010
abcebc7e 1011void pci_pcnet_init(PCIBus *bus, NICInfo *nd, int devfn);
67e999be
FB
1012void pcnet_h_reset(void *opaque);
1013void *lance_init(NICInfo *nd, uint32_t leaddr, void *dma_opaque);
1014
548df2ac
TS
1015/* vmmouse.c */
1016void *vmmouse_init(void *m);
e3c2613f 1017
80cabfad
FB
1018/* pckbd.c */
1019
80cabfad
FB
1020void kbd_init(void);
1021
1022/* mc146818rtc.c */
1023
8a7ddc38 1024typedef struct RTCState RTCState;
80cabfad 1025
8a7ddc38
FB
1026RTCState *rtc_init(int base, int irq);
1027void rtc_set_memory(RTCState *s, int addr, int val);
1028void rtc_set_date(RTCState *s, const struct tm *tm);
80cabfad
FB
1029
1030/* serial.c */
1031
c4b1fcc0 1032typedef struct SerialState SerialState;
e5d13e2f
FB
1033SerialState *serial_init(SetIRQFunc *set_irq, void *opaque,
1034 int base, int irq, CharDriverState *chr);
1035SerialState *serial_mm_init (SetIRQFunc *set_irq, void *opaque,
1036 target_ulong base, int it_shift,
1037 int irq, CharDriverState *chr);
80cabfad 1038
6508fe59
FB
1039/* parallel.c */
1040
1041typedef struct ParallelState ParallelState;
1042ParallelState *parallel_init(int base, int irq, CharDriverState *chr);
1043
80cabfad
FB
1044/* i8259.c */
1045
3de388f6
FB
1046typedef struct PicState2 PicState2;
1047extern PicState2 *isa_pic;
80cabfad 1048void pic_set_irq(int irq, int level);
54fa5af5 1049void pic_set_irq_new(void *opaque, int irq, int level);
3de388f6 1050PicState2 *pic_init(IRQRequestFunc *irq_request, void *irq_request_opaque);
d592d303
FB
1051void pic_set_alt_irq_func(PicState2 *s, SetIRQFunc *alt_irq_func,
1052 void *alt_irq_opaque);
3de388f6
FB
1053int pic_read_irq(PicState2 *s);
1054void pic_update_irq(PicState2 *s);
1055uint32_t pic_intack_read(PicState2 *s);
c20709aa 1056void pic_info(void);
4a0fb71e 1057void irq_info(void);
80cabfad 1058
c27004ec 1059/* APIC */
d592d303
FB
1060typedef struct IOAPICState IOAPICState;
1061
c27004ec
FB
1062int apic_init(CPUState *env);
1063int apic_get_interrupt(CPUState *env);
d592d303
FB
1064IOAPICState *ioapic_init(void);
1065void ioapic_set_irq(void *opaque, int vector, int level);
c27004ec 1066
80cabfad
FB
1067/* i8254.c */
1068
1069#define PIT_FREQ 1193182
1070
ec844b96
FB
1071typedef struct PITState PITState;
1072
1073PITState *pit_init(int base, int irq);
1074void pit_set_gate(PITState *pit, int channel, int val);
1075int pit_get_gate(PITState *pit, int channel);
fd06c375
FB
1076int pit_get_initial_count(PITState *pit, int channel);
1077int pit_get_mode(PITState *pit, int channel);
ec844b96 1078int pit_get_out(PITState *pit, int channel, int64_t current_time);
80cabfad 1079
fd06c375
FB
1080/* pcspk.c */
1081void pcspk_init(PITState *);
1082int pcspk_audio_init(AudioState *);
1083
3fffc223
TS
1084#include "hw/smbus.h"
1085
6515b203
FB
1086/* acpi.c */
1087extern int acpi_enabled;
502a5395 1088void piix4_pm_init(PCIBus *bus, int devfn);
3fffc223 1089void piix4_smbus_register_device(SMBusDevice *dev, uint8_t addr);
6515b203
FB
1090void acpi_bios_init(void);
1091
3fffc223
TS
1092/* smbus_eeprom.c */
1093SMBusDevice *smbus_eeprom_device_init(uint8_t addr, uint8_t *buf);
1094
80cabfad 1095/* pc.c */
54fa5af5 1096extern QEMUMachine pc_machine;
3dbbdc25 1097extern QEMUMachine isapc_machine;
52ca8d6a 1098extern int fd_bootchk;
80cabfad 1099
6a00d601
FB
1100void ioport_set_a20(int enable);
1101int ioport_get_a20(void);
1102
26aa7d72 1103/* ppc.c */
54fa5af5
FB
1104extern QEMUMachine prep_machine;
1105extern QEMUMachine core99_machine;
1106extern QEMUMachine heathrow_machine;
1107
6af0bf9c
FB
1108/* mips_r4k.c */
1109extern QEMUMachine mips_machine;
1110
5856de80
TS
1111/* mips_malta.c */
1112extern QEMUMachine mips_malta_machine;
1113
4de9b249
TS
1114/* mips_int */
1115extern void cpu_mips_irq_request(void *opaque, int irq, int level);
1116
e16fe40c
TS
1117/* mips_timer.c */
1118extern void cpu_mips_clock_init(CPUState *);
1119extern void cpu_mips_irqctrl_init (void);
1120
27c7ca7e
FB
1121/* shix.c */
1122extern QEMUMachine shix_machine;
1123
8cc43fef 1124#ifdef TARGET_PPC
47103572
JM
1125/* PowerPC hardware exceptions management helpers */
1126void ppc_set_irq (void *opaque, int n_IRQ, int level);
1127void ppc_openpic_irq (void *opaque, int n_IRQ, int level);
1128int ppc_hw_interrupt (CPUState *env);
8cc43fef
FB
1129ppc_tb_t *cpu_ppc_tb_init (CPUState *env, uint32_t freq);
1130#endif
64201201 1131void PREP_debug_write (void *opaque, uint32_t addr, uint32_t val);
77d4bc34
FB
1132
1133extern CPUWriteMemoryFunc *PPC_io_write[];
1134extern CPUReadMemoryFunc *PPC_io_read[];
54fa5af5 1135void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val);
26aa7d72 1136
e95c8d51 1137/* sun4m.c */
54fa5af5 1138extern QEMUMachine sun4m_machine;
ba3c64fb 1139void pic_set_irq_cpu(int irq, int level, unsigned int cpu);
e95c8d51
FB
1140
1141/* iommu.c */
e80cfcfc 1142void *iommu_init(uint32_t addr);
67e999be 1143void sparc_iommu_memory_rw(void *opaque, target_phys_addr_t addr,
a917d384 1144 uint8_t *buf, int len, int is_write);
67e999be
FB
1145static inline void sparc_iommu_memory_read(void *opaque,
1146 target_phys_addr_t addr,
1147 uint8_t *buf, int len)
1148{
1149 sparc_iommu_memory_rw(opaque, addr, buf, len, 0);
1150}
e95c8d51 1151
67e999be
FB
1152static inline void sparc_iommu_memory_write(void *opaque,
1153 target_phys_addr_t addr,
1154 uint8_t *buf, int len)
1155{
1156 sparc_iommu_memory_rw(opaque, addr, buf, len, 1);
1157}
e95c8d51
FB
1158
1159/* tcx.c */
95219897 1160void tcx_init(DisplayState *ds, uint32_t addr, uint8_t *vram_base,
6f7e9aec 1161 unsigned long vram_offset, int vram_size, int width, int height);
e80cfcfc
FB
1162
1163/* slavio_intctl.c */
1164void *slavio_intctl_init();
ba3c64fb 1165void slavio_intctl_set_cpu(void *opaque, unsigned int cpu, CPUState *env);
e80cfcfc
FB
1166void slavio_pic_info(void *opaque);
1167void slavio_irq_info(void *opaque);
1168void slavio_pic_set_irq(void *opaque, int irq, int level);
ba3c64fb 1169void slavio_pic_set_irq_cpu(void *opaque, int irq, int level, unsigned int cpu);
e95c8d51 1170
5fe141fd
FB
1171/* loader.c */
1172int get_image_size(const char *filename);
1173int load_image(const char *filename, uint8_t *addr);
9ee3c029 1174int load_elf(const char *filename, int64_t virt_to_phys_addend, uint64_t *pentry);
e80cfcfc 1175int load_aout(const char *filename, uint8_t *addr);
1c7b3754 1176int load_uboot(const char *filename, target_ulong *ep, int *is_linux);
e80cfcfc
FB
1177
1178/* slavio_timer.c */
ba3c64fb 1179void slavio_timer_init(uint32_t addr, int irq, int mode, unsigned int cpu);
8d5f07fa 1180
e80cfcfc
FB
1181/* slavio_serial.c */
1182SerialState *slavio_serial_init(int base, int irq, CharDriverState *chr1, CharDriverState *chr2);
1183void slavio_serial_ms_kbd_init(int base, int irq);
e95c8d51 1184
3475187d
FB
1185/* slavio_misc.c */
1186void *slavio_misc_init(uint32_t base, int irq);
1187void slavio_set_power_fail(void *opaque, int power_failing);
1188
6f7e9aec 1189/* esp.c */
fa1fb14c 1190void esp_scsi_attach(void *opaque, BlockDriverState *bd, int id);
67e999be
FB
1191void *esp_init(BlockDriverState **bd, uint32_t espaddr, void *dma_opaque);
1192void esp_reset(void *opaque);
1193
1194/* sparc32_dma.c */
1195void *sparc32_dma_init(uint32_t daddr, int espirq, int leirq, void *iommu,
1196 void *intctl);
1197void ledma_set_irq(void *opaque, int isr);
9b94dc32
FB
1198void ledma_memory_read(void *opaque, target_phys_addr_t addr,
1199 uint8_t *buf, int len, int do_bswap);
1200void ledma_memory_write(void *opaque, target_phys_addr_t addr,
1201 uint8_t *buf, int len, int do_bswap);
67e999be
FB
1202void espdma_raise_irq(void *opaque);
1203void espdma_clear_irq(void *opaque);
1204void espdma_memory_read(void *opaque, uint8_t *buf, int len);
1205void espdma_memory_write(void *opaque, uint8_t *buf, int len);
1206void sparc32_dma_set_reset_data(void *opaque, void *esp_opaque,
1207 void *lance_opaque);
6f7e9aec 1208
b8174937
FB
1209/* cs4231.c */
1210void cs_init(target_phys_addr_t base, int irq, void *intctl);
1211
3475187d
FB
1212/* sun4u.c */
1213extern QEMUMachine sun4u_machine;
1214
64201201
FB
1215/* NVRAM helpers */
1216#include "hw/m48t59.h"
1217
1218void NVRAM_set_byte (m48t59_t *nvram, uint32_t addr, uint8_t value);
1219uint8_t NVRAM_get_byte (m48t59_t *nvram, uint32_t addr);
1220void NVRAM_set_word (m48t59_t *nvram, uint32_t addr, uint16_t value);
1221uint16_t NVRAM_get_word (m48t59_t *nvram, uint32_t addr);
1222void NVRAM_set_lword (m48t59_t *nvram, uint32_t addr, uint32_t value);
1223uint32_t NVRAM_get_lword (m48t59_t *nvram, uint32_t addr);
1224void NVRAM_set_string (m48t59_t *nvram, uint32_t addr,
1225 const unsigned char *str, uint32_t max);
1226int NVRAM_get_string (m48t59_t *nvram, uint8_t *dst, uint16_t addr, int max);
1227void NVRAM_set_crc (m48t59_t *nvram, uint32_t addr,
1228 uint32_t start, uint32_t count);
1229int PPC_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size,
1230 const unsigned char *arch,
1231 uint32_t RAM_size, int boot_device,
1232 uint32_t kernel_image, uint32_t kernel_size,
28b9b5af 1233 const char *cmdline,
64201201 1234 uint32_t initrd_image, uint32_t initrd_size,
28b9b5af
FB
1235 uint32_t NVRAM_image,
1236 int width, int height, int depth);
64201201 1237
63066f4f
FB
1238/* adb.c */
1239
1240#define MAX_ADB_DEVICES 16
1241
e2733d20 1242#define ADB_MAX_OUT_LEN 16
63066f4f 1243
e2733d20 1244typedef struct ADBDevice ADBDevice;
63066f4f 1245
e2733d20
FB
1246/* buf = NULL means polling */
1247typedef int ADBDeviceRequest(ADBDevice *d, uint8_t *buf_out,
1248 const uint8_t *buf, int len);
12c28fed
FB
1249typedef int ADBDeviceReset(ADBDevice *d);
1250
63066f4f
FB
1251struct ADBDevice {
1252 struct ADBBusState *bus;
1253 int devaddr;
1254 int handler;
e2733d20 1255 ADBDeviceRequest *devreq;
12c28fed 1256 ADBDeviceReset *devreset;
63066f4f
FB
1257 void *opaque;
1258};
1259
1260typedef struct ADBBusState {
1261 ADBDevice devices[MAX_ADB_DEVICES];
1262 int nb_devices;
e2733d20 1263 int poll_index;
63066f4f
FB
1264} ADBBusState;
1265
e2733d20
FB
1266int adb_request(ADBBusState *s, uint8_t *buf_out,
1267 const uint8_t *buf, int len);
1268int adb_poll(ADBBusState *s, uint8_t *buf_out);
63066f4f
FB
1269
1270ADBDevice *adb_register_device(ADBBusState *s, int devaddr,
e2733d20 1271 ADBDeviceRequest *devreq,
12c28fed 1272 ADBDeviceReset *devreset,
63066f4f
FB
1273 void *opaque);
1274void adb_kbd_init(ADBBusState *bus);
1275void adb_mouse_init(ADBBusState *bus);
1276
1277/* cuda.c */
1278
1279extern ADBBusState adb_bus;
54fa5af5 1280int cuda_init(SetIRQFunc *set_irq, void *irq_opaque, int irq);
63066f4f 1281
bb36d470
FB
1282#include "hw/usb.h"
1283
a594cfbf
FB
1284/* usb ports of the VM */
1285
0d92ed30
PB
1286void qemu_register_usb_port(USBPort *port, void *opaque, int index,
1287 usb_attachfn attach);
a594cfbf 1288
0d92ed30 1289#define VM_USB_HUB_SIZE 8
a594cfbf
FB
1290
1291void do_usb_add(const char *devname);
1292void do_usb_del(const char *devname);
1293void usb_info(void);
1294
2e5d83bb 1295/* scsi-disk.c */
4d611c9a
PB
1296enum scsi_reason {
1297 SCSI_REASON_DONE, /* Command complete. */
1298 SCSI_REASON_DATA /* Transfer complete, more data required. */
1299};
1300
2e5d83bb 1301typedef struct SCSIDevice SCSIDevice;
a917d384
PB
1302typedef void (*scsi_completionfn)(void *opaque, int reason, uint32_t tag,
1303 uint32_t arg);
2e5d83bb
PB
1304
1305SCSIDevice *scsi_disk_init(BlockDriverState *bdrv,
a917d384 1306 int tcq,
2e5d83bb
PB
1307 scsi_completionfn completion,
1308 void *opaque);
1309void scsi_disk_destroy(SCSIDevice *s);
1310
0fc5c15a 1311int32_t scsi_send_command(SCSIDevice *s, uint32_t tag, uint8_t *buf, int lun);
4d611c9a
PB
1312/* SCSI data transfers are asynchrnonous. However, unlike the block IO
1313 layer the completion routine may be called directly by
1314 scsi_{read,write}_data. */
a917d384
PB
1315void scsi_read_data(SCSIDevice *s, uint32_t tag);
1316int scsi_write_data(SCSIDevice *s, uint32_t tag);
1317void scsi_cancel_io(SCSIDevice *s, uint32_t tag);
1318uint8_t *scsi_get_buf(SCSIDevice *s, uint32_t tag);
2e5d83bb 1319
7d8406be
PB
1320/* lsi53c895a.c */
1321void lsi_scsi_attach(void *opaque, BlockDriverState *bd, int id);
1322void *lsi_scsi_init(PCIBus *bus, int devfn);
1323
b5ff1b31 1324/* integratorcp.c */
3371d272 1325extern QEMUMachine integratorcp_machine;
b5ff1b31 1326
cdbdb648
PB
1327/* versatilepb.c */
1328extern QEMUMachine versatilepb_machine;
16406950 1329extern QEMUMachine versatileab_machine;
cdbdb648 1330
e69954b9
PB
1331/* realview.c */
1332extern QEMUMachine realview_machine;
1333
daa57963
FB
1334/* ps2.c */
1335void *ps2_kbd_init(void (*update_irq)(void *, int), void *update_arg);
1336void *ps2_mouse_init(void (*update_irq)(void *, int), void *update_arg);
1337void ps2_write_mouse(void *, int val);
1338void ps2_write_keyboard(void *, int val);
1339uint32_t ps2_read_data(void *);
1340void ps2_queue(void *, int b);
f94f5d71 1341void ps2_keyboard_set_translation(void *opaque, int mode);
548df2ac 1342void ps2_mouse_fake_event(void *opaque);
daa57963 1343
80337b66
FB
1344/* smc91c111.c */
1345void smc91c111_init(NICInfo *, uint32_t, void *, int);
1346
bdd5003a 1347/* pl110.c */
95219897 1348void *pl110_init(DisplayState *ds, uint32_t base, void *pic, int irq, int);
bdd5003a 1349
cdbdb648
PB
1350/* pl011.c */
1351void pl011_init(uint32_t base, void *pic, int irq, CharDriverState *chr);
1352
1353/* pl050.c */
1354void pl050_init(uint32_t base, void *pic, int irq, int is_mouse);
1355
1356/* pl080.c */
e69954b9 1357void *pl080_init(uint32_t base, void *pic, int irq, int nchannels);
cdbdb648
PB
1358
1359/* pl190.c */
1360void *pl190_init(uint32_t base, void *parent, int irq, int fiq);
1361
1362/* arm-timer.c */
1363void sp804_init(uint32_t base, void *pic, int irq);
1364void icp_pit_init(uint32_t base, void *pic, int irq);
1365
e69954b9
PB
1366/* arm_sysctl.c */
1367void arm_sysctl_init(uint32_t base, uint32_t sys_id);
1368
1369/* arm_gic.c */
1370void *arm_gic_init(uint32_t base, void *parent, int parent_irq);
1371
16406950
PB
1372/* arm_boot.c */
1373
daf90626 1374void arm_load_kernel(CPUState *env, int ram_size, const char *kernel_filename,
16406950
PB
1375 const char *kernel_cmdline, const char *initrd_filename,
1376 int board_id);
1377
27c7ca7e
FB
1378/* sh7750.c */
1379struct SH7750State;
1380
008a8818 1381struct SH7750State *sh7750_init(CPUState * cpu);
27c7ca7e
FB
1382
1383typedef struct {
1384 /* The callback will be triggered if any of the designated lines change */
1385 uint16_t portamask_trigger;
1386 uint16_t portbmask_trigger;
1387 /* Return 0 if no action was taken */
1388 int (*port_change_cb) (uint16_t porta, uint16_t portb,
1389 uint16_t * periph_pdtra,
1390 uint16_t * periph_portdira,
1391 uint16_t * periph_pdtrb,
1392 uint16_t * periph_portdirb);
1393} sh7750_io_device;
1394
1395int sh7750_register_io_device(struct SH7750State *s,
1396 sh7750_io_device * device);
1397/* tc58128.c */
1398int tc58128_init(struct SH7750State *s, char *zone1, char *zone2);
1399
29133e9a
FB
1400/* NOR flash devices */
1401typedef struct pflash_t pflash_t;
1402
1403pflash_t *pflash_register (target_ulong base, ram_addr_t off,
1404 BlockDriverState *bs,
1405 target_ulong sector_len, int nb_blocs, int width,
1406 uint16_t id0, uint16_t id1,
1407 uint16_t id2, uint16_t id3);
1408
4046d913
PB
1409#include "gdbstub.h"
1410
ea2384d3
FB
1411#endif /* defined(QEMU_TOOL) */
1412
c4b1fcc0 1413/* monitor.c */
82c643ff 1414void monitor_init(CharDriverState *hd, int show_banner);
ea2384d3
FB
1415void term_puts(const char *str);
1416void term_vprintf(const char *fmt, va_list ap);
40c3bac3 1417void term_printf(const char *fmt, ...) __attribute__ ((__format__ (__printf__, 1, 2)));
fef30743 1418void term_print_filename(const char *filename);
c4b1fcc0
FB
1419void term_flush(void);
1420void term_print_help(void);
ea2384d3
FB
1421void monitor_readline(const char *prompt, int is_password,
1422 char *buf, int buf_size);
1423
1424/* readline.c */
1425typedef void ReadLineFunc(void *opaque, const char *str);
1426
1427extern int completion_index;
1428void add_completion(const char *str);
1429void readline_handle_byte(int ch);
1430void readline_find_completion(const char *cmdline);
1431const char *readline_get_history(unsigned int index);
1432void readline_start(const char *prompt, int is_password,
1433 ReadLineFunc *readline_func, void *opaque);
c4b1fcc0 1434
5e6ad6f9
FB
1435void kqemu_record_dump(void);
1436
fc01f7e7 1437#endif /* VL_H */
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