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Merge remote-tracking branch 'remotes/kraxel/tags/pull-chardev-1' into staging
[qemu.git] / hw / display / qxl.c
CommitLineData
a19cbfb3
GH		 1/*
2 * Copyright (C) 2010 Red Hat, Inc.
3 *
4 * written by Yaniv Kamay, Izik Eidus, Gerd Hoffmann
5 * maintained by Gerd Hoffmann <[email protected]>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 or
10 * (at your option) version 3 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, see <http://www.gnu.org/licenses/>.
19 */
20
a639ab04 21#include <zlib.h>
3761abb1 22#include <stdint.h>
a639ab04 23
a19cbfb3 24#include "qemu-common.h"
1de7afc9
PB		 25#include "qemu/timer.h"
26#include "qemu/queue.h"
5444e768 27#include "qemu/atomic.h"
83c9089e 28#include "monitor/monitor.h"
9c17d615 29#include "sysemu/sysemu.h"
c480bb7d 30#include "trace.h"
a19cbfb3 31
47b43a1f 32#include "qxl.h"
a19cbfb3 33
0b81c478
AL		 34/*
35 * NOTE: SPICE_RING_PROD_ITEM accesses memory on the pci bar and as
36 * such can be changed by the guest, so to avoid a guest trigerrable
0a530548 37 * abort we just qxl_set_guest_bug and set the return to NULL. Still
0b81c478
AL		 38 * it may happen as a result of emulator bug as well.
39 */
a19cbfb3 40#undef SPICE_RING_PROD_ITEM
0b81c478 41#define SPICE_RING_PROD_ITEM(qxl, r, ret) { \
a19cbfb3 42 uint32_t prod = (r)->prod & SPICE_RING_INDEX_MASK(r); \
bc5f92e5 43 if (prod >= ARRAY_SIZE((r)->items)) { \
0a530548 44 qxl_set_guest_bug(qxl, "SPICE_RING_PROD_ITEM indices mismatch " \
bc5f92e5 45 "%u >= %zu", prod, ARRAY_SIZE((r)->items)); \
0b81c478
AL		 46 ret = NULL; \
47 } else { \
bc5f92e5 48 ret = &(r)->items[prod].el; \
a19cbfb3 49 } \
a19cbfb3
GH		 50 }
51
52#undef SPICE_RING_CONS_ITEM
0b81c478 53#define SPICE_RING_CONS_ITEM(qxl, r, ret) { \
a19cbfb3 54 uint32_t cons = (r)->cons & SPICE_RING_INDEX_MASK(r); \
bc5f92e5 55 if (cons >= ARRAY_SIZE((r)->items)) { \
0a530548 56 qxl_set_guest_bug(qxl, "SPICE_RING_CONS_ITEM indices mismatch " \
bc5f92e5 57 "%u >= %zu", cons, ARRAY_SIZE((r)->items)); \
0b81c478
AL		 58 ret = NULL; \
59 } else { \
bc5f92e5 60 ret = &(r)->items[cons].el; \
a19cbfb3 61 } \
a19cbfb3
GH		 62 }
63
64#undef ALIGN
65#define ALIGN(a, b) (((a) + ((b) - 1)) & ~((b) - 1))
66
67#define PIXEL_SIZE 0.2936875 //1280x1024 is 14.8" x 11.9"
68
69#define QXL_MODE(_x, _y, _b, _o) \
70 { .x_res = _x, \
71 .y_res = _y, \
72 .bits = _b, \
73 .stride = (_x) * (_b) / 8, \
74 .x_mili = PIXEL_SIZE * (_x), \
75 .y_mili = PIXEL_SIZE * (_y), \
76 .orientation = _o, \
77 }
78
79#define QXL_MODE_16_32(x_res, y_res, orientation) \
80 QXL_MODE(x_res, y_res, 16, orientation), \
81 QXL_MODE(x_res, y_res, 32, orientation)
82
83#define QXL_MODE_EX(x_res, y_res) \
84 QXL_MODE_16_32(x_res, y_res, 0), \
038c1879 85 QXL_MODE_16_32(x_res, y_res, 1)
a19cbfb3
GH		 86
87static QXLMode qxl_modes[] = {
88 QXL_MODE_EX(640, 480),
89 QXL_MODE_EX(800, 480),
90 QXL_MODE_EX(800, 600),
91 QXL_MODE_EX(832, 624),
92 QXL_MODE_EX(960, 640),
93 QXL_MODE_EX(1024, 600),
94 QXL_MODE_EX(1024, 768),
95 QXL_MODE_EX(1152, 864),
96 QXL_MODE_EX(1152, 870),
97 QXL_MODE_EX(1280, 720),
98 QXL_MODE_EX(1280, 760),
99 QXL_MODE_EX(1280, 768),
100 QXL_MODE_EX(1280, 800),
101 QXL_MODE_EX(1280, 960),
102 QXL_MODE_EX(1280, 1024),
103 QXL_MODE_EX(1360, 768),
104 QXL_MODE_EX(1366, 768),
105 QXL_MODE_EX(1400, 1050),
106 QXL_MODE_EX(1440, 900),
107 QXL_MODE_EX(1600, 900),
108 QXL_MODE_EX(1600, 1200),
109 QXL_MODE_EX(1680, 1050),
110 QXL_MODE_EX(1920, 1080),
a19cbfb3
GH		 111 /* these modes need more than 8 MB video memory */
112 QXL_MODE_EX(1920, 1200),
113 QXL_MODE_EX(1920, 1440),
5c74fb27 114 QXL_MODE_EX(2000, 2000),
a19cbfb3 115 QXL_MODE_EX(2048, 1536),
5c74fb27 116 QXL_MODE_EX(2048, 2048),
a19cbfb3
GH		 117 QXL_MODE_EX(2560, 1440),
118 QXL_MODE_EX(2560, 1600),
a19cbfb3
GH		 119 /* these modes need more than 16 MB video memory */
120 QXL_MODE_EX(2560, 2048),
121 QXL_MODE_EX(2800, 2100),
122 QXL_MODE_EX(3200, 2400),
d4bcb199
GH		 123 QXL_MODE_EX(3840, 2160), /* 4k mainstream */
124 QXL_MODE_EX(4096, 2160), /* 4k */
125 QXL_MODE_EX(7680, 4320), /* 8k mainstream */
126 QXL_MODE_EX(8192, 4320), /* 8k */
a19cbfb3
GH		 127};
128
a19cbfb3 129static void qxl_send_events(PCIQXLDevice *d, uint32_t events);
5ff4e36c 130static int qxl_destroy_primary(PCIQXLDevice *d, qxl_async_io async);
a19cbfb3
GH		 131static void qxl_reset_memslots(PCIQXLDevice *d);
132static void qxl_reset_surfaces(PCIQXLDevice *d);
133static void qxl_ring_set_dirty(PCIQXLDevice *qxl);
134
0a530548 135void qxl_set_guest_bug(PCIQXLDevice *qxl, const char *msg, ...)
2bce0400 136{
917ae08c 137 trace_qxl_set_guest_bug(qxl->id);
2bce0400 138 qxl_send_events(qxl, QXL_INTERRUPT_ERROR);
087e6a42 139 qxl->guest_bug = 1;
2bce0400 140 if (qxl->guestdebug) {
7635392c
AL		 141 va_list ap;
142 va_start(ap, msg);
143 fprintf(stderr, "qxl-%d: guest bug: ", qxl->id);
144 vfprintf(stderr, msg, ap);
145 fprintf(stderr, "\n");
146 va_end(ap);
2bce0400
GH		 147 }
148}
149
087e6a42
AL		 150static void qxl_clear_guest_bug(PCIQXLDevice *qxl)
151{
152 qxl->guest_bug = 0;
153}
aee32bf3
GH		 154
155void qxl_spice_update_area(PCIQXLDevice *qxl, uint32_t surface_id,
156 struct QXLRect *area, struct QXLRect *dirty_rects,
157 uint32_t num_dirty_rects,
5ff4e36c 158 uint32_t clear_dirty_region,
2e1a98c9 159 qxl_async_io async, struct QXLCookie *cookie)
aee32bf3 160{
c480bb7d
AL		 161 trace_qxl_spice_update_area(qxl->id, surface_id, area->left, area->right,
162 area->top, area->bottom);
163 trace_qxl_spice_update_area_rest(qxl->id, num_dirty_rects,
164 clear_dirty_region);
5ff4e36c 165 if (async == QXL_SYNC) {
26defe81 166 spice_qxl_update_area(&qxl->ssd.qxl, surface_id, area,
5ff4e36c
AL		 167 dirty_rects, num_dirty_rects, clear_dirty_region);
168 } else {
2e1a98c9 169 assert(cookie != NULL);
5ff4e36c 170 spice_qxl_update_area_async(&qxl->ssd.qxl, surface_id, area,
5dba0d45 171 clear_dirty_region, (uintptr_t)cookie);
5ff4e36c 172 }
aee32bf3
GH		 173}
174
5ff4e36c
AL		 175static void qxl_spice_destroy_surface_wait_complete(PCIQXLDevice *qxl,
176 uint32_t id)
aee32bf3 177{
c480bb7d 178 trace_qxl_spice_destroy_surface_wait_complete(qxl->id, id);
14898cf6 179 qemu_mutex_lock(&qxl->track_lock);
14898cf6
GH		 180 qxl->guest_surfaces.cmds[id] = 0;
181 qxl->guest_surfaces.count--;
182 qemu_mutex_unlock(&qxl->track_lock);
aee32bf3
GH		 183}
184
5ff4e36c
AL		 185static void qxl_spice_destroy_surface_wait(PCIQXLDevice *qxl, uint32_t id,
186 qxl_async_io async)
187{
2e1a98c9
AL		 188 QXLCookie *cookie;
189
c480bb7d 190 trace_qxl_spice_destroy_surface_wait(qxl->id, id, async);
5ff4e36c 191 if (async) {
2e1a98c9
AL		 192 cookie = qxl_cookie_new(QXL_COOKIE_TYPE_IO,
193 QXL_IO_DESTROY_SURFACE_ASYNC);
194 cookie->u.surface_id = id;
5dba0d45 195 spice_qxl_destroy_surface_async(&qxl->ssd.qxl, id, (uintptr_t)cookie);
5ff4e36c 196 } else {
26defe81 197 spice_qxl_destroy_surface_wait(&qxl->ssd.qxl, id);
753b8b0d 198 qxl_spice_destroy_surface_wait_complete(qxl, id);
5ff4e36c
AL		 199 }
200}
201
3e16b9c5
AL		 202static void qxl_spice_flush_surfaces_async(PCIQXLDevice *qxl)
203{
c480bb7d
AL		 204 trace_qxl_spice_flush_surfaces_async(qxl->id, qxl->guest_surfaces.count,
205 qxl->num_free_res);
2e1a98c9 206 spice_qxl_flush_surfaces_async(&qxl->ssd.qxl,
5dba0d45
PM		 207 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO,
208 QXL_IO_FLUSH_SURFACES_ASYNC));
3e16b9c5 209}
3e16b9c5 210
aee32bf3
GH		 211void qxl_spice_loadvm_commands(PCIQXLDevice *qxl, struct QXLCommandExt *ext,
212 uint32_t count)
213{
c480bb7d 214 trace_qxl_spice_loadvm_commands(qxl->id, ext, count);
26defe81 215 spice_qxl_loadvm_commands(&qxl->ssd.qxl, ext, count);
aee32bf3
GH		 216}
217
218void qxl_spice_oom(PCIQXLDevice *qxl)
219{
c480bb7d 220 trace_qxl_spice_oom(qxl->id);
26defe81 221 spice_qxl_oom(&qxl->ssd.qxl);
aee32bf3
GH		 222}
223
224void qxl_spice_reset_memslots(PCIQXLDevice *qxl)
225{
c480bb7d 226 trace_qxl_spice_reset_memslots(qxl->id);
26defe81 227 spice_qxl_reset_memslots(&qxl->ssd.qxl);
aee32bf3
GH		 228}
229
5ff4e36c 230static void qxl_spice_destroy_surfaces_complete(PCIQXLDevice *qxl)
aee32bf3 231{
c480bb7d 232 trace_qxl_spice_destroy_surfaces_complete(qxl->id);
14898cf6 233 qemu_mutex_lock(&qxl->track_lock);
ddd8fdc7 234 memset(qxl->guest_surfaces.cmds, 0,
8bb9f51c 235 sizeof(qxl->guest_surfaces.cmds[0]) * qxl->ssd.num_surfaces);
14898cf6
GH		 236 qxl->guest_surfaces.count = 0;
237 qemu_mutex_unlock(&qxl->track_lock);
aee32bf3
GH		 238}
239
5ff4e36c
AL		 240static void qxl_spice_destroy_surfaces(PCIQXLDevice *qxl, qxl_async_io async)
241{
c480bb7d 242 trace_qxl_spice_destroy_surfaces(qxl->id, async);
5ff4e36c 243 if (async) {
2e1a98c9 244 spice_qxl_destroy_surfaces_async(&qxl->ssd.qxl,
5dba0d45
PM		 245 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO,
246 QXL_IO_DESTROY_ALL_SURFACES_ASYNC));
5ff4e36c 247 } else {
26defe81 248 spice_qxl_destroy_surfaces(&qxl->ssd.qxl);
5ff4e36c
AL		 249 qxl_spice_destroy_surfaces_complete(qxl);
250 }
251}
252
020af1c4
AL		 253static void qxl_spice_monitors_config_async(PCIQXLDevice *qxl, int replay)
254{
255 trace_qxl_spice_monitors_config(qxl->id);
020af1c4
AL		 256 if (replay) {
257 /*
258 * don't use QXL_COOKIE_TYPE_IO:
259 * - we are not running yet (post_load), we will assert
260 * in send_events
261 * - this is not a guest io, but a reply, so async_io isn't set.
262 */
263 spice_qxl_monitors_config_async(&qxl->ssd.qxl,
264 qxl->guest_monitors_config,
265 MEMSLOT_GROUP_GUEST,
266 (uintptr_t)qxl_cookie_new(
267 QXL_COOKIE_TYPE_POST_LOAD_MONITORS_CONFIG,
268 0));
269 } else {
270 qxl->guest_monitors_config = qxl->ram->monitors_config;
271 spice_qxl_monitors_config_async(&qxl->ssd.qxl,
272 qxl->ram->monitors_config,
273 MEMSLOT_GROUP_GUEST,
274 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO,
275 QXL_IO_MONITORS_CONFIG_ASYNC));
276 }
020af1c4
AL		 277}
278
aee32bf3
GH		 279void qxl_spice_reset_image_cache(PCIQXLDevice *qxl)
280{
c480bb7d 281 trace_qxl_spice_reset_image_cache(qxl->id);
26defe81 282 spice_qxl_reset_image_cache(&qxl->ssd.qxl);
aee32bf3
GH		 283}
284
285void qxl_spice_reset_cursor(PCIQXLDevice *qxl)
286{
c480bb7d 287 trace_qxl_spice_reset_cursor(qxl->id);
26defe81 288 spice_qxl_reset_cursor(&qxl->ssd.qxl);
30f6da66
YH		 289 qemu_mutex_lock(&qxl->track_lock);
290 qxl->guest_cursor = 0;
291 qemu_mutex_unlock(&qxl->track_lock);
958c2bce
GH		 292 if (qxl->ssd.cursor) {
293 cursor_put(qxl->ssd.cursor);
294 }
295 qxl->ssd.cursor = cursor_builtin_hidden();
aee32bf3
GH		 296}
297
298
a19cbfb3
GH		 299static inline uint32_t msb_mask(uint32_t val)
300{
301 uint32_t mask;
302
303 do {
304 mask = ~(val - 1) & val;
305 val &= ~mask;
306 } while (mask < val);
307
308 return mask;
309}
310
311static ram_addr_t qxl_rom_size(void)
312{
038c1879
AL		 313 uint32_t required_rom_size = sizeof(QXLRom) + sizeof(QXLModes) +
314 sizeof(qxl_modes);
315 uint32_t rom_size = 8192; /* two pages */
13d1fd44 316
60b3b2a5 317 QEMU_BUILD_BUG_ON(required_rom_size > rom_size);
a19cbfb3
GH		 318 return rom_size;
319}
320
321static void init_qxl_rom(PCIQXLDevice *d)
322{
b1950430 323 QXLRom *rom = memory_region_get_ram_ptr(&d->rom_bar);
a19cbfb3
GH		 324 QXLModes *modes = (QXLModes *)(rom + 1);
325 uint32_t ram_header_size;
326 uint32_t surface0_area_size;
327 uint32_t num_pages;
13d1fd44
AL		 328 uint32_t fb;
329 int i, n;
a19cbfb3
GH		 330
331 memset(rom, 0, d->rom_size);
332
333 rom->magic = cpu_to_le32(QXL_ROM_MAGIC);
334 rom->id = cpu_to_le32(d->id);
335 rom->log_level = cpu_to_le32(d->guestdebug);
336 rom->modes_offset = cpu_to_le32(sizeof(QXLRom));
337
338 rom->slot_gen_bits = MEMSLOT_GENERATION_BITS;
339 rom->slot_id_bits = MEMSLOT_SLOT_BITS;
340 rom->slots_start = 1;
341 rom->slots_end = NUM_MEMSLOTS - 1;
ddd8fdc7 342 rom->n_surfaces = cpu_to_le32(d->ssd.num_surfaces);
a19cbfb3 343
13d1fd44 344 for (i = 0, n = 0; i < ARRAY_SIZE(qxl_modes); i++) {
a19cbfb3 345 fb = qxl_modes[i].y_res * qxl_modes[i].stride;
13d1fd44
AL		 346 if (fb > d->vgamem_size) {
347 continue;
a19cbfb3 348 }
13d1fd44
AL		 349 modes->modes[n].id = cpu_to_le32(i);
350 modes->modes[n].x_res = cpu_to_le32(qxl_modes[i].x_res);
351 modes->modes[n].y_res = cpu_to_le32(qxl_modes[i].y_res);
352 modes->modes[n].bits = cpu_to_le32(qxl_modes[i].bits);
353 modes->modes[n].stride = cpu_to_le32(qxl_modes[i].stride);
354 modes->modes[n].x_mili = cpu_to_le32(qxl_modes[i].x_mili);
355 modes->modes[n].y_mili = cpu_to_le32(qxl_modes[i].y_mili);
356 modes->modes[n].orientation = cpu_to_le32(qxl_modes[i].orientation);
357 n++;
358 }
359 modes->n_modes = cpu_to_le32(n);
a19cbfb3
GH		 360
361 ram_header_size = ALIGN(sizeof(QXLRam), 4096);
13d1fd44 362 surface0_area_size = ALIGN(d->vgamem_size, 4096);
a19cbfb3
GH		 363 num_pages = d->vga.vram_size;
364 num_pages -= ram_header_size;
365 num_pages -= surface0_area_size;
9efc2d8d 366 num_pages = num_pages / QXL_PAGE_SIZE;
a19cbfb3
GH		 367
368 rom->draw_area_offset = cpu_to_le32(0);
369 rom->surface0_area_size = cpu_to_le32(surface0_area_size);
370 rom->pages_offset = cpu_to_le32(surface0_area_size);
371 rom->num_pages = cpu_to_le32(num_pages);
372 rom->ram_header_offset = cpu_to_le32(d->vga.vram_size - ram_header_size);
373
374 d->shadow_rom = *rom;
375 d->rom = rom;
376 d->modes = modes;
377}
378
379static void init_qxl_ram(PCIQXLDevice *d)
380{
381 uint8_t *buf;
382 uint64_t *item;
383
384 buf = d->vga.vram_ptr;
385 d->ram = (QXLRam *)(buf + le32_to_cpu(d->shadow_rom.ram_header_offset));
386 d->ram->magic = cpu_to_le32(QXL_RAM_MAGIC);
387 d->ram->int_pending = cpu_to_le32(0);
388 d->ram->int_mask = cpu_to_le32(0);
9f0f352d 389 d->ram->update_surface = 0;
329f97fc 390 d->ram->monitors_config = 0;
a19cbfb3
GH		 391 SPICE_RING_INIT(&d->ram->cmd_ring);
392 SPICE_RING_INIT(&d->ram->cursor_ring);
393 SPICE_RING_INIT(&d->ram->release_ring);
0b81c478
AL		 394 SPICE_RING_PROD_ITEM(d, &d->ram->release_ring, item);
395 assert(item);
a19cbfb3
GH		 396 *item = 0;
397 qxl_ring_set_dirty(d);
398}
399
400/* can be called from spice server thread context */
b1950430 401static void qxl_set_dirty(MemoryRegion *mr, ram_addr_t addr, ram_addr_t end)
a19cbfb3 402{
fd4aa979 403 memory_region_set_dirty(mr, addr, end - addr);
a19cbfb3
GH		 404}
405
406static void qxl_rom_set_dirty(PCIQXLDevice *qxl)
407{
b1950430 408 qxl_set_dirty(&qxl->rom_bar, 0, qxl->rom_size);
a19cbfb3
GH		 409}
410
411/* called from spice server thread context only */
412static void qxl_ram_set_dirty(PCIQXLDevice *qxl, void *ptr)
413{
a19cbfb3
GH		 414 void *base = qxl->vga.vram_ptr;
415 intptr_t offset;
416
417 offset = ptr - base;
a19cbfb3 418 assert(offset < qxl->vga.vram_size);
b0297b4a 419 qxl_set_dirty(&qxl->vga.vram, offset, offset + 3);
a19cbfb3
GH		 420}
421
422/* can be called from spice server thread context */
423static void qxl_ring_set_dirty(PCIQXLDevice *qxl)
424{
b1950430
AK		 425 ram_addr_t addr = qxl->shadow_rom.ram_header_offset;
426 ram_addr_t end = qxl->vga.vram_size;
427 qxl_set_dirty(&qxl->vga.vram, addr, end);
a19cbfb3
GH		 428}
429
430/*
431 * keep track of some command state, for savevm/loadvm.
432 * called from spice server thread context only
433 */
fae2afb1 434static int qxl_track_command(PCIQXLDevice *qxl, struct QXLCommandExt *ext)
a19cbfb3
GH		 435{
436 switch (le32_to_cpu(ext->cmd.type)) {
437 case QXL_CMD_SURFACE:
438 {
439 QXLSurfaceCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id);
fae2afb1
AL		 440
441 if (!cmd) {
442 return 1;
443 }
a19cbfb3 444 uint32_t id = le32_to_cpu(cmd->surface_id);
47eddfbf 445
ddd8fdc7 446 if (id >= qxl->ssd.num_surfaces) {
0a530548 447 qxl_set_guest_bug(qxl, "QXL_CMD_SURFACE id %d >= %d", id,
ddd8fdc7 448 qxl->ssd.num_surfaces);
47eddfbf
AL		 449 return 1;
450 }
48f4ba67
AL		 451 if (cmd->type == QXL_SURFACE_CMD_CREATE &&
452 (cmd->u.surface_create.stride & 0x03) != 0) {
453 qxl_set_guest_bug(qxl, "QXL_CMD_SURFACE stride = %d %% 4 != 0\n",
454 cmd->u.surface_create.stride);
455 return 1;
456 }
14898cf6 457 qemu_mutex_lock(&qxl->track_lock);
a19cbfb3
GH		 458 if (cmd->type == QXL_SURFACE_CMD_CREATE) {
459 qxl->guest_surfaces.cmds[id] = ext->cmd.data;
460 qxl->guest_surfaces.count++;
461 if (qxl->guest_surfaces.max < qxl->guest_surfaces.count)
462 qxl->guest_surfaces.max = qxl->guest_surfaces.count;
463 }
464 if (cmd->type == QXL_SURFACE_CMD_DESTROY) {
465 qxl->guest_surfaces.cmds[id] = 0;
466 qxl->guest_surfaces.count--;
467 }
14898cf6 468 qemu_mutex_unlock(&qxl->track_lock);
a19cbfb3
GH		 469 break;
470 }
471 case QXL_CMD_CURSOR:
472 {
473 QXLCursorCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id);
fae2afb1
AL		 474
475 if (!cmd) {
476 return 1;
477 }
a19cbfb3 478 if (cmd->type == QXL_CURSOR_SET) {
30f6da66 479 qemu_mutex_lock(&qxl->track_lock);
a19cbfb3 480 qxl->guest_cursor = ext->cmd.data;
30f6da66 481 qemu_mutex_unlock(&qxl->track_lock);
a19cbfb3
GH		 482 }
483 break;
484 }
485 }
fae2afb1 486 return 0;
a19cbfb3
GH		 487}
488
489/* spice display interface callbacks */
490
491static void interface_attach_worker(QXLInstance *sin, QXLWorker *qxl_worker)
492{
493 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
494
c480bb7d 495 trace_qxl_interface_attach_worker(qxl->id);
a19cbfb3
GH		 496 qxl->ssd.worker = qxl_worker;
497}
498
499static void interface_set_compression_level(QXLInstance *sin, int level)
500{
501 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
502
c480bb7d 503 trace_qxl_interface_set_compression_level(qxl->id, level);
a19cbfb3
GH		 504 qxl->shadow_rom.compression_level = cpu_to_le32(level);
505 qxl->rom->compression_level = cpu_to_le32(level);
506 qxl_rom_set_dirty(qxl);
507}
508
509static void interface_set_mm_time(QXLInstance *sin, uint32_t mm_time)
510{
511 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
512
c480bb7d 513 trace_qxl_interface_set_mm_time(qxl->id, mm_time);
a19cbfb3
GH		 514 qxl->shadow_rom.mm_clock = cpu_to_le32(mm_time);
515 qxl->rom->mm_clock = cpu_to_le32(mm_time);
516 qxl_rom_set_dirty(qxl);
517}
518
519static void interface_get_init_info(QXLInstance *sin, QXLDevInitInfo *info)
520{
521 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
522
c480bb7d 523 trace_qxl_interface_get_init_info(qxl->id);
a19cbfb3
GH		 524 info->memslot_gen_bits = MEMSLOT_GENERATION_BITS;
525 info->memslot_id_bits = MEMSLOT_SLOT_BITS;
526 info->num_memslots = NUM_MEMSLOTS;
527 info->num_memslots_groups = NUM_MEMSLOTS_GROUPS;
528 info->internal_groupslot_id = 0;
9efc2d8d
GH		 529 info->qxl_ram_size =
530 le32_to_cpu(qxl->shadow_rom.num_pages) << QXL_PAGE_BITS;
ddd8fdc7 531 info->n_surfaces = qxl->ssd.num_surfaces;
a19cbfb3
GH		 532}
533
5b77870c
AL		 534static const char *qxl_mode_to_string(int mode)
535{
536 switch (mode) {
537 case QXL_MODE_COMPAT:
538 return "compat";
539 case QXL_MODE_NATIVE:
540 return "native";
541 case QXL_MODE_UNDEFINED:
542 return "undefined";
543 case QXL_MODE_VGA:
544 return "vga";
545 }
546 return "INVALID";
547}
548
8b92e298
AL		 549static const char *io_port_to_string(uint32_t io_port)
550{
551 if (io_port >= QXL_IO_RANGE_SIZE) {
552 return "out of range";
553 }
554 static const char *io_port_to_string[QXL_IO_RANGE_SIZE + 1] = {
555 [QXL_IO_NOTIFY_CMD] = "QXL_IO_NOTIFY_CMD",
556 [QXL_IO_NOTIFY_CURSOR] = "QXL_IO_NOTIFY_CURSOR",
557 [QXL_IO_UPDATE_AREA] = "QXL_IO_UPDATE_AREA",
558 [QXL_IO_UPDATE_IRQ] = "QXL_IO_UPDATE_IRQ",
559 [QXL_IO_NOTIFY_OOM] = "QXL_IO_NOTIFY_OOM",
560 [QXL_IO_RESET] = "QXL_IO_RESET",
561 [QXL_IO_SET_MODE] = "QXL_IO_SET_MODE",
562 [QXL_IO_LOG] = "QXL_IO_LOG",
563 [QXL_IO_MEMSLOT_ADD] = "QXL_IO_MEMSLOT_ADD",
564 [QXL_IO_MEMSLOT_DEL] = "QXL_IO_MEMSLOT_DEL",
565 [QXL_IO_DETACH_PRIMARY] = "QXL_IO_DETACH_PRIMARY",
566 [QXL_IO_ATTACH_PRIMARY] = "QXL_IO_ATTACH_PRIMARY",
567 [QXL_IO_CREATE_PRIMARY] = "QXL_IO_CREATE_PRIMARY",
568 [QXL_IO_DESTROY_PRIMARY] = "QXL_IO_DESTROY_PRIMARY",
569 [QXL_IO_DESTROY_SURFACE_WAIT] = "QXL_IO_DESTROY_SURFACE_WAIT",
570 [QXL_IO_DESTROY_ALL_SURFACES] = "QXL_IO_DESTROY_ALL_SURFACES",
8b92e298
AL		 571 [QXL_IO_UPDATE_AREA_ASYNC] = "QXL_IO_UPDATE_AREA_ASYNC",
572 [QXL_IO_MEMSLOT_ADD_ASYNC] = "QXL_IO_MEMSLOT_ADD_ASYNC",
573 [QXL_IO_CREATE_PRIMARY_ASYNC] = "QXL_IO_CREATE_PRIMARY_ASYNC",
574 [QXL_IO_DESTROY_PRIMARY_ASYNC] = "QXL_IO_DESTROY_PRIMARY_ASYNC",
575 [QXL_IO_DESTROY_SURFACE_ASYNC] = "QXL_IO_DESTROY_SURFACE_ASYNC",
576 [QXL_IO_DESTROY_ALL_SURFACES_ASYNC]
577 = "QXL_IO_DESTROY_ALL_SURFACES_ASYNC",
578 [QXL_IO_FLUSH_SURFACES_ASYNC] = "QXL_IO_FLUSH_SURFACES_ASYNC",
579 [QXL_IO_FLUSH_RELEASE] = "QXL_IO_FLUSH_RELEASE",
020af1c4 580 [QXL_IO_MONITORS_CONFIG_ASYNC] = "QXL_IO_MONITORS_CONFIG_ASYNC",
8b92e298
AL		 581 };
582 return io_port_to_string[io_port];
583}
584
a19cbfb3
GH		 585/* called from spice server thread context only */
586static int interface_get_command(QXLInstance *sin, struct QXLCommandExt *ext)
587{
588 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
589 SimpleSpiceUpdate *update;
590 QXLCommandRing *ring;
591 QXLCommand *cmd;
e0c64d08 592 int notify, ret;
a19cbfb3 593
c480bb7d
AL		 594 trace_qxl_ring_command_check(qxl->id, qxl_mode_to_string(qxl->mode));
595
a19cbfb3
GH		 596 switch (qxl->mode) {
597 case QXL_MODE_VGA:
e0c64d08
GH		 598 ret = false;
599 qemu_mutex_lock(&qxl->ssd.lock);
b1af98ba
GH		 600 update = QTAILQ_FIRST(&qxl->ssd.updates);
601 if (update != NULL) {
602 QTAILQ_REMOVE(&qxl->ssd.updates, update, next);
e0c64d08
GH		 603 *ext = update->ext;
604 ret = true;
a19cbfb3 605 }
e0c64d08 606 qemu_mutex_unlock(&qxl->ssd.lock);
212496c9 607 if (ret) {
c480bb7d 608 trace_qxl_ring_command_get(qxl->id, qxl_mode_to_string(qxl->mode));
212496c9
AL		 609 qxl_log_command(qxl, "vga", ext);
610 }
e0c64d08 611 return ret;
a19cbfb3
GH		 612 case QXL_MODE_COMPAT:
613 case QXL_MODE_NATIVE:
614 case QXL_MODE_UNDEFINED:
a19cbfb3 615 ring = &qxl->ram->cmd_ring;
087e6a42 616 if (qxl->guest_bug || SPICE_RING_IS_EMPTY(ring)) {
a19cbfb3
GH		 617 return false;
618 }
0b81c478
AL		 619 SPICE_RING_CONS_ITEM(qxl, ring, cmd);
620 if (!cmd) {
621 return false;
622 }
a19cbfb3
GH		 623 ext->cmd = *cmd;
624 ext->group_id = MEMSLOT_GROUP_GUEST;
625 ext->flags = qxl->cmdflags;
626 SPICE_RING_POP(ring, notify);
627 qxl_ring_set_dirty(qxl);
628 if (notify) {
629 qxl_send_events(qxl, QXL_INTERRUPT_DISPLAY);
630 }
631 qxl->guest_primary.commands++;
632 qxl_track_command(qxl, ext);
633 qxl_log_command(qxl, "cmd", ext);
0b81c478 634 trace_qxl_ring_command_get(qxl->id, qxl_mode_to_string(qxl->mode));
a19cbfb3
GH		 635 return true;
636 default:
637 return false;
638 }
639}
640
641/* called from spice server thread context only */
642static int interface_req_cmd_notification(QXLInstance *sin)
643{
644 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
645 int wait = 1;
646
c480bb7d 647 trace_qxl_ring_command_req_notification(qxl->id);
a19cbfb3
GH		 648 switch (qxl->mode) {
649 case QXL_MODE_COMPAT:
650 case QXL_MODE_NATIVE:
651 case QXL_MODE_UNDEFINED:
652 SPICE_RING_CONS_WAIT(&qxl->ram->cmd_ring, wait);
653 qxl_ring_set_dirty(qxl);
654 break;
655 default:
656 /* nothing */
657 break;
658 }
659 return wait;
660}
661
662/* called from spice server thread context only */
663static inline void qxl_push_free_res(PCIQXLDevice *d, int flush)
664{
665 QXLReleaseRing *ring = &d->ram->release_ring;
666 uint64_t *item;
667 int notify;
668
669#define QXL_FREE_BUNCH_SIZE 32
670
671 if (ring->prod - ring->cons + 1 == ring->num_items) {
672 /* ring full -- can't push */
673 return;
674 }
675 if (!flush && d->oom_running) {
676 /* collect everything from oom handler before pushing */
677 return;
678 }
679 if (!flush && d->num_free_res < QXL_FREE_BUNCH_SIZE) {
680 /* collect a bit more before pushing */
681 return;
682 }
683
684 SPICE_RING_PUSH(ring, notify);
c480bb7d
AL		 685 trace_qxl_ring_res_push(d->id, qxl_mode_to_string(d->mode),
686 d->guest_surfaces.count, d->num_free_res,
687 d->last_release, notify ? "yes" : "no");
688 trace_qxl_ring_res_push_rest(d->id, ring->prod - ring->cons,
689 ring->num_items, ring->prod, ring->cons);
a19cbfb3
GH		 690 if (notify) {
691 qxl_send_events(d, QXL_INTERRUPT_DISPLAY);
692 }
0b81c478
AL		 693 SPICE_RING_PROD_ITEM(d, ring, item);
694 if (!item) {
695 return;
696 }
a19cbfb3
GH		 697 *item = 0;
698 d->num_free_res = 0;
699 d->last_release = NULL;
700 qxl_ring_set_dirty(d);
701}
702
703/* called from spice server thread context only */
704static void interface_release_resource(QXLInstance *sin,
705 struct QXLReleaseInfoExt ext)
706{
707 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
708 QXLReleaseRing *ring;
709 uint64_t *item, id;
710
711 if (ext.group_id == MEMSLOT_GROUP_HOST) {
712 /* host group -> vga mode update request */
f4a8a424 713 qemu_spice_destroy_update(&qxl->ssd, (void *)(intptr_t)ext.info->id);
a19cbfb3
GH		 714 return;
715 }
716
717 /*
718 * ext->info points into guest-visible memory
719 * pci bar 0, $command.release_info
720 */
721 ring = &qxl->ram->release_ring;
0b81c478
AL		 722 SPICE_RING_PROD_ITEM(qxl, ring, item);
723 if (!item) {
724 return;
725 }
a19cbfb3
GH		 726 if (*item == 0) {
727 /* stick head into the ring */
728 id = ext.info->id;
729 ext.info->next = 0;
730 qxl_ram_set_dirty(qxl, &ext.info->next);
731 *item = id;
732 qxl_ring_set_dirty(qxl);
733 } else {
734 /* append item to the list */
735 qxl->last_release->next = ext.info->id;
736 qxl_ram_set_dirty(qxl, &qxl->last_release->next);
737 ext.info->next = 0;
738 qxl_ram_set_dirty(qxl, &ext.info->next);
739 }
740 qxl->last_release = ext.info;
741 qxl->num_free_res++;
c480bb7d 742 trace_qxl_ring_res_put(qxl->id, qxl->num_free_res);
a19cbfb3
GH		 743 qxl_push_free_res(qxl, 0);
744}
745
746/* called from spice server thread context only */
747static int interface_get_cursor_command(QXLInstance *sin, struct QXLCommandExt *ext)
748{
749 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
750 QXLCursorRing *ring;
751 QXLCommand *cmd;
752 int notify;
753
c480bb7d
AL		 754 trace_qxl_ring_cursor_check(qxl->id, qxl_mode_to_string(qxl->mode));
755
a19cbfb3
GH		 756 switch (qxl->mode) {
757 case QXL_MODE_COMPAT:
758 case QXL_MODE_NATIVE:
759 case QXL_MODE_UNDEFINED:
760 ring = &qxl->ram->cursor_ring;
761 if (SPICE_RING_IS_EMPTY(ring)) {
762 return false;
763 }
0b81c478
AL		 764 SPICE_RING_CONS_ITEM(qxl, ring, cmd);
765 if (!cmd) {
766 return false;
767 }
a19cbfb3
GH		 768 ext->cmd = *cmd;
769 ext->group_id = MEMSLOT_GROUP_GUEST;
770 ext->flags = qxl->cmdflags;
771 SPICE_RING_POP(ring, notify);
772 qxl_ring_set_dirty(qxl);
773 if (notify) {
774 qxl_send_events(qxl, QXL_INTERRUPT_CURSOR);
775 }
776 qxl->guest_primary.commands++;
777 qxl_track_command(qxl, ext);
778 qxl_log_command(qxl, "csr", ext);
779 if (qxl->id == 0) {
780 qxl_render_cursor(qxl, ext);
781 }
c480bb7d 782 trace_qxl_ring_cursor_get(qxl->id, qxl_mode_to_string(qxl->mode));
a19cbfb3
GH		 783 return true;
784 default:
785 return false;
786 }
787}
788
789/* called from spice server thread context only */
790static int interface_req_cursor_notification(QXLInstance *sin)
791{
792 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
793 int wait = 1;
794
c480bb7d 795 trace_qxl_ring_cursor_req_notification(qxl->id);
a19cbfb3
GH		 796 switch (qxl->mode) {
797 case QXL_MODE_COMPAT:
798 case QXL_MODE_NATIVE:
799 case QXL_MODE_UNDEFINED:
800 SPICE_RING_CONS_WAIT(&qxl->ram->cursor_ring, wait);
801 qxl_ring_set_dirty(qxl);
802 break;
803 default:
804 /* nothing */
805 break;
806 }
807 return wait;
808}
809
810/* called from spice server thread context */
811static void interface_notify_update(QXLInstance *sin, uint32_t update_id)
812{
baeae407
AL		 813 /*
814 * Called by spice-server as a result of a QXL_CMD_UPDATE which is not in
815 * use by xf86-video-qxl and is defined out in the qxl windows driver.
816 * Probably was at some earlier version that is prior to git start (2009),
817 * and is still guest trigerrable.
818 */
819 fprintf(stderr, "%s: deprecated\n", __func__);
a19cbfb3
GH		 820}
821
822/* called from spice server thread context only */
823static int interface_flush_resources(QXLInstance *sin)
824{
825 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
826 int ret;
827
a19cbfb3
GH		 828 ret = qxl->num_free_res;
829 if (ret) {
830 qxl_push_free_res(qxl, 1);
831 }
832 return ret;
833}
834
5ff4e36c
AL		 835static void qxl_create_guest_primary_complete(PCIQXLDevice *d);
836
5ff4e36c 837/* called from spice server thread context only */
2e1a98c9 838static void interface_async_complete_io(PCIQXLDevice *qxl, QXLCookie *cookie)
5ff4e36c 839{
5ff4e36c
AL		 840 uint32_t current_async;
841
842 qemu_mutex_lock(&qxl->async_lock);
843 current_async = qxl->current_async;
844 qxl->current_async = QXL_UNDEFINED_IO;
845 qemu_mutex_unlock(&qxl->async_lock);
846
c480bb7d 847 trace_qxl_interface_async_complete_io(qxl->id, current_async, cookie);
2e1a98c9
AL		 848 if (!cookie) {
849 fprintf(stderr, "qxl: %s: error, cookie is NULL\n", __func__);
850 return;
851 }
852 if (cookie && current_async != cookie->io) {
853 fprintf(stderr,
2fce7edf
AL		 854 "qxl: %s: error: current_async = %d != %"
855 PRId64 " = cookie->io\n", __func__, current_async, cookie->io);
2e1a98c9 856 }
5ff4e36c 857 switch (current_async) {
81fb6f15
AL		 858 case QXL_IO_MEMSLOT_ADD_ASYNC:
859 case QXL_IO_DESTROY_PRIMARY_ASYNC:
860 case QXL_IO_UPDATE_AREA_ASYNC:
861 case QXL_IO_FLUSH_SURFACES_ASYNC:
020af1c4 862 case QXL_IO_MONITORS_CONFIG_ASYNC:
81fb6f15 863 break;
5ff4e36c
AL		 864 case QXL_IO_CREATE_PRIMARY_ASYNC:
865 qxl_create_guest_primary_complete(qxl);
866 break;
867 case QXL_IO_DESTROY_ALL_SURFACES_ASYNC:
868 qxl_spice_destroy_surfaces_complete(qxl);
869 break;
870 case QXL_IO_DESTROY_SURFACE_ASYNC:
2e1a98c9 871 qxl_spice_destroy_surface_wait_complete(qxl, cookie->u.surface_id);
5ff4e36c 872 break;
81fb6f15
AL		 873 default:
874 fprintf(stderr, "qxl: %s: unexpected current_async %d\n", __func__,
875 current_async);
5ff4e36c
AL		 876 }
877 qxl_send_events(qxl, QXL_INTERRUPT_IO_CMD);
878}
879
81fb6f15
AL		 880/* called from spice server thread context only */
881static void interface_update_area_complete(QXLInstance *sin,
882 uint32_t surface_id,
883 QXLRect *dirty, uint32_t num_updated_rects)
884{
885 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
886 int i;
887 int qxl_i;
888
889 qemu_mutex_lock(&qxl->ssd.lock);
890 if (surface_id != 0 || !qxl->render_update_cookie_num) {
891 qemu_mutex_unlock(&qxl->ssd.lock);
892 return;
893 }
c480bb7d
AL		 894 trace_qxl_interface_update_area_complete(qxl->id, surface_id, dirty->left,
895 dirty->right, dirty->top, dirty->bottom);
896 trace_qxl_interface_update_area_complete_rest(qxl->id, num_updated_rects);
81fb6f15
AL		 897 if (qxl->num_dirty_rects + num_updated_rects > QXL_NUM_DIRTY_RECTS) {
898 /*
899 * overflow - treat this as a full update. Not expected to be common.
900 */
c480bb7d
AL		 901 trace_qxl_interface_update_area_complete_overflow(qxl->id,
902 QXL_NUM_DIRTY_RECTS);
81fb6f15
AL		 903 qxl->guest_primary.resized = 1;
904 }
905 if (qxl->guest_primary.resized) {
906 /*
907 * Don't bother copying or scheduling the bh since we will flip
908 * the whole area anyway on completion of the update_area async call
909 */
910 qemu_mutex_unlock(&qxl->ssd.lock);
911 return;
912 }
913 qxl_i = qxl->num_dirty_rects;
914 for (i = 0; i < num_updated_rects; i++) {
915 qxl->dirty[qxl_i++] = dirty[i];
916 }
917 qxl->num_dirty_rects += num_updated_rects;
c480bb7d
AL		 918 trace_qxl_interface_update_area_complete_schedule_bh(qxl->id,
919 qxl->num_dirty_rects);
81fb6f15
AL		 920 qemu_bh_schedule(qxl->update_area_bh);
921 qemu_mutex_unlock(&qxl->ssd.lock);
922}
923
2e1a98c9
AL		 924/* called from spice server thread context only */
925static void interface_async_complete(QXLInstance *sin, uint64_t cookie_token)
926{
927 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
5dba0d45 928 QXLCookie *cookie = (QXLCookie *)(uintptr_t)cookie_token;
2e1a98c9
AL		 929
930 switch (cookie->type) {
931 case QXL_COOKIE_TYPE_IO:
932 interface_async_complete_io(qxl, cookie);
81fb6f15
AL		 933 g_free(cookie);
934 break;
935 case QXL_COOKIE_TYPE_RENDER_UPDATE_AREA:
936 qxl_render_update_area_done(qxl, cookie);
2e1a98c9 937 break;
020af1c4
AL		 938 case QXL_COOKIE_TYPE_POST_LOAD_MONITORS_CONFIG:
939 break;
2e1a98c9
AL		 940 default:
941 fprintf(stderr, "qxl: %s: unexpected cookie type %d\n",
942 __func__, cookie->type);
81fb6f15 943 g_free(cookie);
2e1a98c9 944 }
2e1a98c9
AL		 945}
946
c10018d6
SSP		 947/* called from spice server thread context only */
948static void interface_set_client_capabilities(QXLInstance *sin,
949 uint8_t client_present,
950 uint8_t caps[58])
951{
952 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
953
e0ac6097
AL		 954 if (qxl->revision < 4) {
955 trace_qxl_set_client_capabilities_unsupported_by_revision(qxl->id,
956 qxl->revision);
957 return;
958 }
959
ab902981
HG		 960 if (runstate_check(RUN_STATE_INMIGRATE) ||
961 runstate_check(RUN_STATE_POSTMIGRATE)) {
962 return;
963 }
964
c10018d6 965 qxl->shadow_rom.client_present = client_present;
08688af0
MA		 966 memcpy(qxl->shadow_rom.client_capabilities, caps,
967 sizeof(qxl->shadow_rom.client_capabilities));
c10018d6 968 qxl->rom->client_present = client_present;
08688af0
MA		 969 memcpy(qxl->rom->client_capabilities, caps,
970 sizeof(qxl->rom->client_capabilities));
c10018d6
SSP		 971 qxl_rom_set_dirty(qxl);
972
973 qxl_send_events(qxl, QXL_INTERRUPT_CLIENT);
974}
975
a639ab04
AL		 976static uint32_t qxl_crc32(const uint8_t *p, unsigned len)
977{
978 /*
979 * zlib xors the seed with 0xffffffff, and xors the result
980 * again with 0xffffffff; Both are not done with linux's crc32,
981 * which we want to be compatible with, so undo that.
982 */
983 return crc32(0xffffffff, p, len) ^ 0xffffffff;
984}
985
986/* called from main context only */
987static int interface_client_monitors_config(QXLInstance *sin,
988 VDAgentMonitorsConfig *monitors_config)
989{
990 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
991 QXLRom *rom = memory_region_get_ram_ptr(&qxl->rom_bar);
992 int i;
993
e0ac6097
AL		 994 if (qxl->revision < 4) {
995 trace_qxl_client_monitors_config_unsupported_by_device(qxl->id,
996 qxl->revision);
997 return 0;
998 }
a639ab04
AL		 999 /*
1000 * Older windows drivers set int_mask to 0 when their ISR is called,
1001 * then later set it to ~0. So it doesn't relate to the actual interrupts
1002 * handled. However, they are old, so clearly they don't support this
1003 * interrupt
1004 */
1005 if (qxl->ram->int_mask == 0 || qxl->ram->int_mask == ~0 ||
1006 !(qxl->ram->int_mask & QXL_INTERRUPT_CLIENT_MONITORS_CONFIG)) {
1007 trace_qxl_client_monitors_config_unsupported_by_guest(qxl->id,
1008 qxl->ram->int_mask,
1009 monitors_config);
1010 return 0;
1011 }
1012 if (!monitors_config) {
1013 return 1;
1014 }
1015 memset(&rom->client_monitors_config, 0,
1016 sizeof(rom->client_monitors_config));
1017 rom->client_monitors_config.count = monitors_config->num_of_monitors;
1018 /* monitors_config->flags ignored */
1019 if (rom->client_monitors_config.count >=
1020 ARRAY_SIZE(rom->client_monitors_config.heads)) {
1021 trace_qxl_client_monitors_config_capped(qxl->id,
1022 monitors_config->num_of_monitors,
1023 ARRAY_SIZE(rom->client_monitors_config.heads));
1024 rom->client_monitors_config.count =
1025 ARRAY_SIZE(rom->client_monitors_config.heads);
1026 }
1027 for (i = 0 ; i < rom->client_monitors_config.count ; ++i) {
1028 VDAgentMonConfig *monitor = &monitors_config->monitors[i];
1029 QXLURect *rect = &rom->client_monitors_config.heads[i];
1030 /* monitor->depth ignored */
1031 rect->left = monitor->x;
1032 rect->top = monitor->y;
1033 rect->right = monitor->x + monitor->width;
1034 rect->bottom = monitor->y + monitor->height;
1035 }
1036 rom->client_monitors_config_crc = qxl_crc32(
1037 (const uint8_t *)&rom->client_monitors_config,
1038 sizeof(rom->client_monitors_config));
1039 trace_qxl_client_monitors_config_crc(qxl->id,
1040 sizeof(rom->client_monitors_config),
1041 rom->client_monitors_config_crc);
1042
1043 trace_qxl_interrupt_client_monitors_config(qxl->id,
1044 rom->client_monitors_config.count,
1045 rom->client_monitors_config.heads);
1046 qxl_send_events(qxl, QXL_INTERRUPT_CLIENT_MONITORS_CONFIG);
1047 return 1;
1048}
a639ab04 1049
a19cbfb3
GH		 1050static const QXLInterface qxl_interface = {
1051 .base.type = SPICE_INTERFACE_QXL,
1052 .base.description = "qxl gpu",
1053 .base.major_version = SPICE_INTERFACE_QXL_MAJOR,
1054 .base.minor_version = SPICE_INTERFACE_QXL_MINOR,
1055
1056 .attache_worker = interface_attach_worker,
1057 .set_compression_level = interface_set_compression_level,
1058 .set_mm_time = interface_set_mm_time,
1059 .get_init_info = interface_get_init_info,
1060
1061 /* the callbacks below are called from spice server thread context */
1062 .get_command = interface_get_command,
1063 .req_cmd_notification = interface_req_cmd_notification,
1064 .release_resource = interface_release_resource,
1065 .get_cursor_command = interface_get_cursor_command,
1066 .req_cursor_notification = interface_req_cursor_notification,
1067 .notify_update = interface_notify_update,
1068 .flush_resources = interface_flush_resources,
5ff4e36c 1069 .async_complete = interface_async_complete,
81fb6f15 1070 .update_area_complete = interface_update_area_complete,
c10018d6 1071 .set_client_capabilities = interface_set_client_capabilities,
a639ab04 1072 .client_monitors_config = interface_client_monitors_config,
a19cbfb3
GH		 1073};
1074
1075static void qxl_enter_vga_mode(PCIQXLDevice *d)
1076{
1077 if (d->mode == QXL_MODE_VGA) {
1078 return;
1079 }
c480bb7d 1080 trace_qxl_enter_vga_mode(d->id);
0a2b5e3a
HG		 1081#if SPICE_SERVER_VERSION >= 0x000c03 /* release 0.12.3 */
1082 spice_qxl_driver_unload(&d->ssd.qxl);
1083#endif
a19cbfb3
GH		 1084 qemu_spice_create_host_primary(&d->ssd);
1085 d->mode = QXL_MODE_VGA;
0f7bfd81 1086 vga_dirty_log_start(&d->vga);
1dbfa005 1087 graphic_hw_update(d->vga.con);
a19cbfb3
GH		 1088}
1089
1090static void qxl_exit_vga_mode(PCIQXLDevice *d)
1091{
1092 if (d->mode != QXL_MODE_VGA) {
1093 return;
1094 }
c480bb7d 1095 trace_qxl_exit_vga_mode(d->id);
0f7bfd81 1096 vga_dirty_log_stop(&d->vga);
5ff4e36c 1097 qxl_destroy_primary(d, QXL_SYNC);
a19cbfb3
GH		 1098}
1099
40010aea 1100static void qxl_update_irq(PCIQXLDevice *d)
a19cbfb3
GH		 1101{
1102 uint32_t pending = le32_to_cpu(d->ram->int_pending);
1103 uint32_t mask = le32_to_cpu(d->ram->int_mask);
1104 int level = !!(pending & mask);
9e64f8a3 1105 pci_set_irq(&d->pci, level);
a19cbfb3
GH		 1106 qxl_ring_set_dirty(d);
1107}
1108
a19cbfb3
GH		 1109static void qxl_check_state(PCIQXLDevice *d)
1110{
1111 QXLRam *ram = d->ram;
71d388d4 1112 int spice_display_running = qemu_spice_display_is_running(&d->ssd);
a19cbfb3 1113
71d388d4
YH		 1114 assert(!spice_display_running || SPICE_RING_IS_EMPTY(&ram->cmd_ring));
1115 assert(!spice_display_running || SPICE_RING_IS_EMPTY(&ram->cursor_ring));
a19cbfb3
GH		 1116}
1117
1118static void qxl_reset_state(PCIQXLDevice *d)
1119{
a19cbfb3
GH		 1120 QXLRom *rom = d->rom;
1121
be48e995 1122 qxl_check_state(d);
a19cbfb3
GH		 1123 d->shadow_rom.update_id = cpu_to_le32(0);
1124 *rom = d->shadow_rom;
1125 qxl_rom_set_dirty(d);
1126 init_qxl_ram(d);
1127 d->num_free_res = 0;
1128 d->last_release = NULL;
1129 memset(&d->ssd.dirty, 0, sizeof(d->ssd.dirty));
f06b8521 1130 qxl_update_irq(d);
a19cbfb3
GH		 1131}
1132
1133static void qxl_soft_reset(PCIQXLDevice *d)
1134{
c480bb7d 1135 trace_qxl_soft_reset(d->id);
a19cbfb3 1136 qxl_check_state(d);
087e6a42 1137 qxl_clear_guest_bug(d);
a5f68c22 1138 d->current_async = QXL_UNDEFINED_IO;
a19cbfb3
GH		 1139
1140 if (d->id == 0) {
1141 qxl_enter_vga_mode(d);
1142 } else {
1143 d->mode = QXL_MODE_UNDEFINED;
1144 }
1145}
1146
1147static void qxl_hard_reset(PCIQXLDevice *d, int loadvm)
1148{
75c70e37
GH		 1149 bool startstop = qemu_spice_display_is_running(&d->ssd);
1150
c480bb7d 1151 trace_qxl_hard_reset(d->id, loadvm);
a19cbfb3 1152
75c70e37
GH		 1153 if (startstop) {
1154 qemu_spice_display_stop();
1155 }
1156
aee32bf3
GH		 1157 qxl_spice_reset_cursor(d);
1158 qxl_spice_reset_image_cache(d);
a19cbfb3
GH		 1159 qxl_reset_surfaces(d);
1160 qxl_reset_memslots(d);
1161
1162 /* pre loadvm reset must not touch QXLRam. This lives in
1163 * device memory, is migrated together with RAM and thus
1164 * already loaded at this point */
1165 if (!loadvm) {
1166 qxl_reset_state(d);
1167 }
1168 qemu_spice_create_host_memslot(&d->ssd);
1169 qxl_soft_reset(d);
75c70e37
GH		 1170
1171 if (startstop) {
1172 qemu_spice_display_start();
1173 }
a19cbfb3
GH		 1174}
1175
1176static void qxl_reset_handler(DeviceState *dev)
1177{
1178 PCIQXLDevice *d = DO_UPCAST(PCIQXLDevice, pci.qdev, dev);
c480bb7d 1179
a19cbfb3
GH		 1180 qxl_hard_reset(d, 0);
1181}
1182
1183static void qxl_vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
1184{
1185 VGACommonState *vga = opaque;
1186 PCIQXLDevice *qxl = container_of(vga, PCIQXLDevice, vga);
1187
c480bb7d 1188 trace_qxl_io_write_vga(qxl->id, qxl_mode_to_string(qxl->mode), addr, val);
a19cbfb3 1189 if (qxl->mode != QXL_MODE_VGA) {
5ff4e36c 1190 qxl_destroy_primary(qxl, QXL_SYNC);
a19cbfb3
GH		 1191 qxl_soft_reset(qxl);
1192 }
1193 vga_ioport_write(opaque, addr, val);
1194}
1195
f67ab77a
GH		 1196static const MemoryRegionPortio qxl_vga_portio_list[] = {
1197 { 0x04, 2, 1, .read = vga_ioport_read,
1198 .write = qxl_vga_ioport_write }, /* 3b4 */
1199 { 0x0a, 1, 1, .read = vga_ioport_read,
1200 .write = qxl_vga_ioport_write }, /* 3ba */
1201 { 0x10, 16, 1, .read = vga_ioport_read,
1202 .write = qxl_vga_ioport_write }, /* 3c0 */
1203 { 0x24, 2, 1, .read = vga_ioport_read,
1204 .write = qxl_vga_ioport_write }, /* 3d4 */
1205 { 0x2a, 1, 1, .read = vga_ioport_read,
1206 .write = qxl_vga_ioport_write }, /* 3da */
1207 PORTIO_END_OF_LIST(),
1208};
1209
e954ea28
AL		 1210static int qxl_add_memslot(PCIQXLDevice *d, uint32_t slot_id, uint64_t delta,
1211 qxl_async_io async)
a19cbfb3
GH		 1212{
1213 static const int regions[] = {
1214 QXL_RAM_RANGE_INDEX,
1215 QXL_VRAM_RANGE_INDEX,
6f2b175a 1216 QXL_VRAM64_RANGE_INDEX,
a19cbfb3
GH		 1217 };
1218 uint64_t guest_start;
1219 uint64_t guest_end;
1220 int pci_region;
1221 pcibus_t pci_start;
1222 pcibus_t pci_end;
1223 intptr_t virt_start;
1224 QXLDevMemSlot memslot;
1225 int i;
1226
1227 guest_start = le64_to_cpu(d->guest_slots[slot_id].slot.mem_start);
1228 guest_end = le64_to_cpu(d->guest_slots[slot_id].slot.mem_end);
1229
c480bb7d 1230 trace_qxl_memslot_add_guest(d->id, slot_id, guest_start, guest_end);
a19cbfb3 1231
e954ea28 1232 if (slot_id >= NUM_MEMSLOTS) {
0a530548 1233 qxl_set_guest_bug(d, "%s: slot_id >= NUM_MEMSLOTS %d >= %d", __func__,
e954ea28
AL		 1234 slot_id, NUM_MEMSLOTS);
1235 return 1;
1236 }
1237 if (guest_start > guest_end) {
0a530548 1238 qxl_set_guest_bug(d, "%s: guest_start > guest_end 0x%" PRIx64
e954ea28
AL		 1239 " > 0x%" PRIx64, __func__, guest_start, guest_end);
1240 return 1;
1241 }
a19cbfb3
GH		 1242
1243 for (i = 0; i < ARRAY_SIZE(regions); i++) {
1244 pci_region = regions[i];
1245 pci_start = d->pci.io_regions[pci_region].addr;
1246 pci_end = pci_start + d->pci.io_regions[pci_region].size;
1247 /* mapped? */
1248 if (pci_start == -1) {
1249 continue;
1250 }
1251 /* start address in range ? */
1252 if (guest_start < pci_start || guest_start > pci_end) {
1253 continue;
1254 }
1255 /* end address in range ? */
1256 if (guest_end > pci_end) {
1257 continue;
1258 }
1259 /* passed */
1260 break;
1261 }
e954ea28 1262 if (i == ARRAY_SIZE(regions)) {
0a530548 1263 qxl_set_guest_bug(d, "%s: finished loop without match", __func__);
e954ea28
AL		 1264 return 1;
1265 }
a19cbfb3
GH		 1266
1267 switch (pci_region) {
1268 case QXL_RAM_RANGE_INDEX:
b1950430 1269 virt_start = (intptr_t)memory_region_get_ram_ptr(&d->vga.vram);
a19cbfb3
GH		 1270 break;
1271 case QXL_VRAM_RANGE_INDEX:
6f2b175a 1272 case 4 /* vram 64bit */:
b1950430 1273 virt_start = (intptr_t)memory_region_get_ram_ptr(&d->vram_bar);
a19cbfb3
GH		 1274 break;
1275 default:
1276 /* should not happen */
0a530548 1277 qxl_set_guest_bug(d, "%s: pci_region = %d", __func__, pci_region);
e954ea28 1278 return 1;
a19cbfb3
GH		 1279 }
1280
1281 memslot.slot_id = slot_id;
1282 memslot.slot_group_id = MEMSLOT_GROUP_GUEST; /* guest group */
1283 memslot.virt_start = virt_start + (guest_start - pci_start);
1284 memslot.virt_end = virt_start + (guest_end - pci_start);
1285 memslot.addr_delta = memslot.virt_start - delta;
1286 memslot.generation = d->rom->slot_generation = 0;
1287 qxl_rom_set_dirty(d);
1288
5ff4e36c 1289 qemu_spice_add_memslot(&d->ssd, &memslot, async);
a19cbfb3
GH		 1290 d->guest_slots[slot_id].ptr = (void*)memslot.virt_start;
1291 d->guest_slots[slot_id].size = memslot.virt_end - memslot.virt_start;
1292 d->guest_slots[slot_id].delta = delta;
1293 d->guest_slots[slot_id].active = 1;
e954ea28 1294 return 0;
a19cbfb3
GH		 1295}
1296
1297static void qxl_del_memslot(PCIQXLDevice *d, uint32_t slot_id)
1298{
5c59d118 1299 qemu_spice_del_memslot(&d->ssd, MEMSLOT_GROUP_HOST, slot_id);
a19cbfb3
GH		 1300 d->guest_slots[slot_id].active = 0;
1301}
1302
1303static void qxl_reset_memslots(PCIQXLDevice *d)
1304{
aee32bf3 1305 qxl_spice_reset_memslots(d);
a19cbfb3
GH		 1306 memset(&d->guest_slots, 0, sizeof(d->guest_slots));
1307}
1308
1309static void qxl_reset_surfaces(PCIQXLDevice *d)
1310{
c480bb7d 1311 trace_qxl_reset_surfaces(d->id);
a19cbfb3 1312 d->mode = QXL_MODE_UNDEFINED;
5ff4e36c 1313 qxl_spice_destroy_surfaces(d, QXL_SYNC);
a19cbfb3
GH		 1314}
1315
e25139b3 1316/* can be also called from spice server thread context */
a19cbfb3
GH		 1317void *qxl_phys2virt(PCIQXLDevice *qxl, QXLPHYSICAL pqxl, int group_id)
1318{
1319 uint64_t phys = le64_to_cpu(pqxl);
1320 uint32_t slot = (phys >> (64 - 8)) & 0xff;
1321 uint64_t offset = phys & 0xffffffffffff;
1322
1323 switch (group_id) {
1324 case MEMSLOT_GROUP_HOST:
f4a8a424 1325 return (void *)(intptr_t)offset;
a19cbfb3 1326 case MEMSLOT_GROUP_GUEST:
4b635c59 1327 if (slot >= NUM_MEMSLOTS) {
0a530548
AL		 1328 qxl_set_guest_bug(qxl, "slot too large %d >= %d", slot,
1329 NUM_MEMSLOTS);
4b635c59
AL		 1330 return NULL;
1331 }
1332 if (!qxl->guest_slots[slot].active) {
0a530548 1333 qxl_set_guest_bug(qxl, "inactive slot %d\n", slot);
4b635c59
AL		 1334 return NULL;
1335 }
1336 if (offset < qxl->guest_slots[slot].delta) {
0a530548
AL		 1337 qxl_set_guest_bug(qxl,
1338 "slot %d offset %"PRIu64" < delta %"PRIu64"\n",
4b635c59
AL		 1339 slot, offset, qxl->guest_slots[slot].delta);
1340 return NULL;
1341 }
a19cbfb3 1342 offset -= qxl->guest_slots[slot].delta;
4b635c59 1343 if (offset > qxl->guest_slots[slot].size) {
0a530548
AL		 1344 qxl_set_guest_bug(qxl,
1345 "slot %d offset %"PRIu64" > size %"PRIu64"\n",
4b635c59
AL		 1346 slot, offset, qxl->guest_slots[slot].size);
1347 return NULL;
1348 }
a19cbfb3 1349 return qxl->guest_slots[slot].ptr + offset;
a19cbfb3 1350 }
4b635c59 1351 return NULL;
a19cbfb3
GH		 1352}
1353
5ff4e36c
AL		 1354static void qxl_create_guest_primary_complete(PCIQXLDevice *qxl)
1355{
1356 /* for local rendering */
1357 qxl_render_resize(qxl);
1358}
1359
1360static void qxl_create_guest_primary(PCIQXLDevice *qxl, int loadvm,
1361 qxl_async_io async)
a19cbfb3
GH		 1362{
1363 QXLDevSurfaceCreate surface;
1364 QXLSurfaceCreate *sc = &qxl->guest_primary.surface;
3761abb1 1365 uint32_t requested_height = le32_to_cpu(sc->height);
13d1fd44
AL		 1366 int requested_stride = le32_to_cpu(sc->stride);
1367
3761abb1
AL		 1368 if (requested_stride == INT32_MIN ||
1369 abs(requested_stride) * (uint64_t)requested_height
1370 > qxl->vgamem_size) {
1371 qxl_set_guest_bug(qxl, "%s: requested primary larger than framebuffer"
1372 " stride %d x height %" PRIu32 " > %" PRIu32,
1373 __func__, requested_stride, requested_height,
1374 qxl->vgamem_size);
13d1fd44
AL		 1375 return;
1376 }
a19cbfb3 1377
ddf9f4b7 1378 if (qxl->mode == QXL_MODE_NATIVE) {
0a530548 1379 qxl_set_guest_bug(qxl, "%s: nop since already in QXL_MODE_NATIVE",
ddf9f4b7
AL		 1380 __func__);
1381 }
a19cbfb3
GH		 1382 qxl_exit_vga_mode(qxl);
1383
a19cbfb3
GH		 1384 surface.format = le32_to_cpu(sc->format);
1385 surface.height = le32_to_cpu(sc->height);
1386 surface.mem = le64_to_cpu(sc->mem);
1387 surface.position = le32_to_cpu(sc->position);
1388 surface.stride = le32_to_cpu(sc->stride);
1389 surface.width = le32_to_cpu(sc->width);
1390 surface.type = le32_to_cpu(sc->type);
1391 surface.flags = le32_to_cpu(sc->flags);
c480bb7d
AL		 1392 trace_qxl_create_guest_primary(qxl->id, sc->width, sc->height, sc->mem,
1393 sc->format, sc->position);
1394 trace_qxl_create_guest_primary_rest(qxl->id, sc->stride, sc->type,
1395 sc->flags);
a19cbfb3 1396
48f4ba67
AL		 1397 if ((surface.stride & 0x3) != 0) {
1398 qxl_set_guest_bug(qxl, "primary surface stride = %d %% 4 != 0",
1399 surface.stride);
1400 return;
1401 }
1402
a19cbfb3
GH		 1403 surface.mouse_mode = true;
1404 surface.group_id = MEMSLOT_GROUP_GUEST;
1405 if (loadvm) {
1406 surface.flags |= QXL_SURF_FLAG_KEEP_DATA;
1407 }
1408
1409 qxl->mode = QXL_MODE_NATIVE;
1410 qxl->cmdflags = 0;
5ff4e36c 1411 qemu_spice_create_primary_surface(&qxl->ssd, 0, &surface, async);
a19cbfb3 1412
5ff4e36c
AL		 1413 if (async == QXL_SYNC) {
1414 qxl_create_guest_primary_complete(qxl);
1415 }
a19cbfb3
GH		 1416}
1417
5ff4e36c
AL		 1418/* return 1 if surface destoy was initiated (in QXL_ASYNC case) or
1419 * done (in QXL_SYNC case), 0 otherwise. */
1420static int qxl_destroy_primary(PCIQXLDevice *d, qxl_async_io async)
a19cbfb3
GH		 1421{
1422 if (d->mode == QXL_MODE_UNDEFINED) {
5ff4e36c 1423 return 0;
a19cbfb3 1424 }
c480bb7d 1425 trace_qxl_destroy_primary(d->id);
a19cbfb3 1426 d->mode = QXL_MODE_UNDEFINED;
5ff4e36c 1427 qemu_spice_destroy_primary_surface(&d->ssd, 0, async);
30f6da66 1428 qxl_spice_reset_cursor(d);
5ff4e36c 1429 return 1;
a19cbfb3
GH		 1430}
1431
9c70434f 1432static void qxl_set_mode(PCIQXLDevice *d, unsigned int modenr, int loadvm)
a19cbfb3
GH		 1433{
1434 pcibus_t start = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr;
1435 pcibus_t end = d->pci.io_regions[QXL_RAM_RANGE_INDEX].size + start;
1436 QXLMode *mode = d->modes->modes + modenr;
1437 uint64_t devmem = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr;
1438 QXLMemSlot slot = {
1439 .mem_start = start,
1440 .mem_end = end
1441 };
9c70434f
GH		 1442
1443 if (modenr >= d->modes->n_modes) {
1444 qxl_set_guest_bug(d, "mode number out of range");
1445 return;
1446 }
1447
a19cbfb3
GH		 1448 QXLSurfaceCreate surface = {
1449 .width = mode->x_res,
1450 .height = mode->y_res,
1451 .stride = -mode->x_res * 4,
1452 .format = SPICE_SURFACE_FMT_32_xRGB,
1453 .flags = loadvm ? QXL_SURF_FLAG_KEEP_DATA : 0,
1454 .mouse_mode = true,
1455 .mem = devmem + d->shadow_rom.draw_area_offset,
1456 };
1457
c480bb7d
AL		 1458 trace_qxl_set_mode(d->id, modenr, mode->x_res, mode->y_res, mode->bits,
1459 devmem);
a19cbfb3
GH		 1460 if (!loadvm) {
1461 qxl_hard_reset(d, 0);
1462 }
1463
1464 d->guest_slots[0].slot = slot;
e954ea28 1465 assert(qxl_add_memslot(d, 0, devmem, QXL_SYNC) == 0);
a19cbfb3
GH		 1466
1467 d->guest_primary.surface = surface;
5ff4e36c 1468 qxl_create_guest_primary(d, 0, QXL_SYNC);
a19cbfb3
GH		 1469
1470 d->mode = QXL_MODE_COMPAT;
1471 d->cmdflags = QXL_COMMAND_FLAG_COMPAT;
a19cbfb3
GH		 1472 if (mode->bits == 16) {
1473 d->cmdflags |= QXL_COMMAND_FLAG_COMPAT_16BPP;
1474 }
a19cbfb3
GH		 1475 d->shadow_rom.mode = cpu_to_le32(modenr);
1476 d->rom->mode = cpu_to_le32(modenr);
1477 qxl_rom_set_dirty(d);
1478}
1479
a8170e5e 1480static void ioport_write(void *opaque, hwaddr addr,
b1950430 1481 uint64_t val, unsigned size)
a19cbfb3
GH		 1482{
1483 PCIQXLDevice *d = opaque;
b1950430 1484 uint32_t io_port = addr;
5ff4e36c 1485 qxl_async_io async = QXL_SYNC;
5ff4e36c 1486 uint32_t orig_io_port = io_port;
a19cbfb3 1487
d96aafca 1488 if (d->guest_bug && io_port != QXL_IO_RESET) {
087e6a42
AL		 1489 return;
1490 }
1491
020af1c4 1492 if (d->revision <= QXL_REVISION_STABLE_V10 &&
ffe01e59 1493 io_port > QXL_IO_FLUSH_RELEASE) {
020af1c4
AL		 1494 qxl_set_guest_bug(d, "unsupported io %d for revision %d\n",
1495 io_port, d->revision);
1496 return;
1497 }
1498
a19cbfb3
GH		 1499 switch (io_port) {
1500 case QXL_IO_RESET:
1501 case QXL_IO_SET_MODE:
1502 case QXL_IO_MEMSLOT_ADD:
1503 case QXL_IO_MEMSLOT_DEL:
1504 case QXL_IO_CREATE_PRIMARY:
81144d1a 1505 case QXL_IO_UPDATE_IRQ:
a3d14054 1506 case QXL_IO_LOG:
5ff4e36c
AL		 1507 case QXL_IO_MEMSLOT_ADD_ASYNC:
1508 case QXL_IO_CREATE_PRIMARY_ASYNC:
a19cbfb3
GH		 1509 break;
1510 default:
e21a298a 1511 if (d->mode != QXL_MODE_VGA) {
a19cbfb3 1512 break;
e21a298a 1513 }
c480bb7d 1514 trace_qxl_io_unexpected_vga_mode(d->id,
917ae08c 1515 addr, val, io_port_to_string(io_port));
5ff4e36c
AL		 1516 /* be nice to buggy guest drivers */
1517 if (io_port >= QXL_IO_UPDATE_AREA_ASYNC &&
020af1c4 1518 io_port < QXL_IO_RANGE_SIZE) {
5ff4e36c
AL		 1519 qxl_send_events(d, QXL_INTERRUPT_IO_CMD);
1520 }
a19cbfb3
GH		 1521 return;
1522 }
1523
5ff4e36c
AL		 1524 /* we change the io_port to avoid ifdeffery in the main switch */
1525 orig_io_port = io_port;
1526 switch (io_port) {
1527 case QXL_IO_UPDATE_AREA_ASYNC:
1528 io_port = QXL_IO_UPDATE_AREA;
1529 goto async_common;
1530 case QXL_IO_MEMSLOT_ADD_ASYNC:
1531 io_port = QXL_IO_MEMSLOT_ADD;
1532 goto async_common;
1533 case QXL_IO_CREATE_PRIMARY_ASYNC:
1534 io_port = QXL_IO_CREATE_PRIMARY;
1535 goto async_common;
1536 case QXL_IO_DESTROY_PRIMARY_ASYNC:
1537 io_port = QXL_IO_DESTROY_PRIMARY;
1538 goto async_common;
1539 case QXL_IO_DESTROY_SURFACE_ASYNC:
1540 io_port = QXL_IO_DESTROY_SURFACE_WAIT;
1541 goto async_common;
1542 case QXL_IO_DESTROY_ALL_SURFACES_ASYNC:
1543 io_port = QXL_IO_DESTROY_ALL_SURFACES;
3e16b9c5
AL		 1544 goto async_common;
1545 case QXL_IO_FLUSH_SURFACES_ASYNC:
020af1c4 1546 case QXL_IO_MONITORS_CONFIG_ASYNC:
5ff4e36c
AL		 1547async_common:
1548 async = QXL_ASYNC;
1549 qemu_mutex_lock(&d->async_lock);
1550 if (d->current_async != QXL_UNDEFINED_IO) {
0a530548 1551 qxl_set_guest_bug(d, "%d async started before last (%d) complete",
5ff4e36c
AL		 1552 io_port, d->current_async);
1553 qemu_mutex_unlock(&d->async_lock);
1554 return;
1555 }
1556 d->current_async = orig_io_port;
1557 qemu_mutex_unlock(&d->async_lock);
5ff4e36c
AL		 1558 break;
1559 default:
1560 break;
1561 }
18b20385
GH		 1562 trace_qxl_io_write(d->id, qxl_mode_to_string(d->mode),
1563 addr, io_port_to_string(addr),
1564 val, size, async);
5ff4e36c 1565
a19cbfb3
GH		 1566 switch (io_port) {
1567 case QXL_IO_UPDATE_AREA:
1568 {
81fb6f15 1569 QXLCookie *cookie = NULL;
a19cbfb3 1570 QXLRect update = d->ram->update_area;
81fb6f15 1571
ddd8fdc7 1572 if (d->ram->update_surface > d->ssd.num_surfaces) {
511b13e2
AL		 1573 qxl_set_guest_bug(d, "QXL_IO_UPDATE_AREA: invalid surface id %d\n",
1574 d->ram->update_surface);
36a03e0b 1575 break;
511b13e2 1576 }
36a03e0b
MT		 1577 if (update.left >= update.right || update.top >= update.bottom ||
1578 update.left < 0 || update.top < 0) {
511b13e2
AL		 1579 qxl_set_guest_bug(d,
1580 "QXL_IO_UPDATE_AREA: invalid area (%ux%u)x(%ux%u)\n",
1581 update.left, update.top, update.right, update.bottom);
ccc2960d
DH		 1582 break;
1583 }
81fb6f15
AL		 1584 if (async == QXL_ASYNC) {
1585 cookie = qxl_cookie_new(QXL_COOKIE_TYPE_IO,
1586 QXL_IO_UPDATE_AREA_ASYNC);
1587 cookie->u.area = update;
1588 }
aee32bf3 1589 qxl_spice_update_area(d, d->ram->update_surface,
81fb6f15
AL		 1590 cookie ? &cookie->u.area : &update,
1591 NULL, 0, 0, async, cookie);
a19cbfb3
GH		 1592 break;
1593 }
1594 case QXL_IO_NOTIFY_CMD:
5c59d118 1595 qemu_spice_wakeup(&d->ssd);
a19cbfb3
GH		 1596 break;
1597 case QXL_IO_NOTIFY_CURSOR:
5c59d118 1598 qemu_spice_wakeup(&d->ssd);
a19cbfb3
GH		 1599 break;
1600 case QXL_IO_UPDATE_IRQ:
40010aea 1601 qxl_update_irq(d);
a19cbfb3
GH		 1602 break;
1603 case QXL_IO_NOTIFY_OOM:
a19cbfb3
GH		 1604 if (!SPICE_RING_IS_EMPTY(&d->ram->release_ring)) {
1605 break;
1606 }
1607 d->oom_running = 1;
aee32bf3 1608 qxl_spice_oom(d);
a19cbfb3
GH		 1609 d->oom_running = 0;
1610 break;
1611 case QXL_IO_SET_MODE:
a19cbfb3
GH		 1612 qxl_set_mode(d, val, 0);
1613 break;
1614 case QXL_IO_LOG:
1a1bc085 1615 trace_qxl_io_log(d->id, d->ram->log_buf);
a19cbfb3 1616 if (d->guestdebug) {
a680f7e7 1617 fprintf(stderr, "qxl/guest-%d: %" PRId64 ": %s", d->id,
bc72ad67 1618 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), d->ram->log_buf);
a19cbfb3
GH		 1619 }
1620 break;
1621 case QXL_IO_RESET:
a19cbfb3
GH		 1622 qxl_hard_reset(d, 0);
1623 break;
1624 case QXL_IO_MEMSLOT_ADD:
2bce0400 1625 if (val >= NUM_MEMSLOTS) {
0a530548 1626 qxl_set_guest_bug(d, "QXL_IO_MEMSLOT_ADD: val out of range");
2bce0400
GH		 1627 break;
1628 }
1629 if (d->guest_slots[val].active) {
0a530548
AL		 1630 qxl_set_guest_bug(d,
1631 "QXL_IO_MEMSLOT_ADD: memory slot already active");
2bce0400
GH		 1632 break;
1633 }
a19cbfb3 1634 d->guest_slots[val].slot = d->ram->mem_slot;
5ff4e36c 1635 qxl_add_memslot(d, val, 0, async);
a19cbfb3
GH		 1636 break;
1637 case QXL_IO_MEMSLOT_DEL:
2bce0400 1638 if (val >= NUM_MEMSLOTS) {
0a530548 1639 qxl_set_guest_bug(d, "QXL_IO_MEMSLOT_DEL: val out of range");
2bce0400
GH		 1640 break;
1641 }
a19cbfb3
GH		 1642 qxl_del_memslot(d, val);
1643 break;
1644 case QXL_IO_CREATE_PRIMARY:
2bce0400 1645 if (val != 0) {
0a530548 1646 qxl_set_guest_bug(d, "QXL_IO_CREATE_PRIMARY (async=%d): val != 0",
5ff4e36c
AL		 1647 async);
1648 goto cancel_async;
2bce0400 1649 }
a19cbfb3 1650 d->guest_primary.surface = d->ram->create_surface;
5ff4e36c 1651 qxl_create_guest_primary(d, 0, async);
a19cbfb3
GH		 1652 break;
1653 case QXL_IO_DESTROY_PRIMARY:
2bce0400 1654 if (val != 0) {
0a530548 1655 qxl_set_guest_bug(d, "QXL_IO_DESTROY_PRIMARY (async=%d): val != 0",
5ff4e36c
AL		 1656 async);
1657 goto cancel_async;
1658 }
5ff4e36c 1659 if (!qxl_destroy_primary(d, async)) {
c480bb7d
AL		 1660 trace_qxl_io_destroy_primary_ignored(d->id,
1661 qxl_mode_to_string(d->mode));
5ff4e36c 1662 goto cancel_async;
2bce0400 1663 }
a19cbfb3
GH		 1664 break;
1665 case QXL_IO_DESTROY_SURFACE_WAIT:
ddd8fdc7 1666 if (val >= d->ssd.num_surfaces) {
0a530548 1667 qxl_set_guest_bug(d, "QXL_IO_DESTROY_SURFACE (async=%d):"
5f8daf2e 1668 "%" PRIu64 " >= NUM_SURFACES", async, val);
5ff4e36c
AL		 1669 goto cancel_async;
1670 }
1671 qxl_spice_destroy_surface_wait(d, val, async);
a19cbfb3 1672 break;
3e16b9c5
AL		 1673 case QXL_IO_FLUSH_RELEASE: {
1674 QXLReleaseRing *ring = &d->ram->release_ring;
1675 if (ring->prod - ring->cons + 1 == ring->num_items) {
1676 fprintf(stderr,
1677 "ERROR: no flush, full release ring [p%d,%dc]\n",
1678 ring->prod, ring->cons);
1679 }
1680 qxl_push_free_res(d, 1 /* flush */);
3e16b9c5
AL		 1681 break;
1682 }
1683 case QXL_IO_FLUSH_SURFACES_ASYNC:
3e16b9c5
AL		 1684 qxl_spice_flush_surfaces_async(d);
1685 break;
a19cbfb3 1686 case QXL_IO_DESTROY_ALL_SURFACES:
5ff4e36c
AL		 1687 d->mode = QXL_MODE_UNDEFINED;
1688 qxl_spice_destroy_surfaces(d, async);
a19cbfb3 1689 break;
020af1c4
AL		 1690 case QXL_IO_MONITORS_CONFIG_ASYNC:
1691 qxl_spice_monitors_config_async(d, 0);
1692 break;
a19cbfb3 1693 default:
0a530548 1694 qxl_set_guest_bug(d, "%s: unexpected ioport=0x%x\n", __func__, io_port);
a19cbfb3 1695 }
5ff4e36c
AL		 1696 return;
1697cancel_async:
5ff4e36c
AL		 1698 if (async) {
1699 qxl_send_events(d, QXL_INTERRUPT_IO_CMD);
1700 qemu_mutex_lock(&d->async_lock);
1701 d->current_async = QXL_UNDEFINED_IO;
1702 qemu_mutex_unlock(&d->async_lock);
1703 }
a19cbfb3
GH		 1704}
1705
a8170e5e 1706static uint64_t ioport_read(void *opaque, hwaddr addr,
b1950430 1707 unsigned size)
a19cbfb3 1708{
917ae08c 1709 PCIQXLDevice *qxl = opaque;
a19cbfb3 1710
917ae08c 1711 trace_qxl_io_read_unexpected(qxl->id);
a19cbfb3
GH		 1712 return 0xff;
1713}
1714
b1950430
AK		 1715static const MemoryRegionOps qxl_io_ops = {
1716 .read = ioport_read,
1717 .write = ioport_write,
1718 .valid = {
1719 .min_access_size = 1,
1720 .max_access_size = 1,
1721 },
1722};
a19cbfb3 1723
4a46c99c 1724static void qxl_update_irq_bh(void *opaque)
a19cbfb3
GH		 1725{
1726 PCIQXLDevice *d = opaque;
40010aea 1727 qxl_update_irq(d);
a19cbfb3
GH		 1728}
1729
a19cbfb3
GH		 1730static void qxl_send_events(PCIQXLDevice *d, uint32_t events)
1731{
1732 uint32_t old_pending;
1733 uint32_t le_events = cpu_to_le32(events);
1734
917ae08c 1735 trace_qxl_send_events(d->id, events);
511aefb0
AL		 1736 if (!qemu_spice_display_is_running(&d->ssd)) {
1737 /* spice-server tracks guest running state and should not do this */
1738 fprintf(stderr, "%s: spice-server bug: guest stopped, ignoring\n",
1739 __func__);
1740 trace_qxl_send_events_vm_stopped(d->id, events);
1741 return;
1742 }
5444e768 1743 old_pending = atomic_fetch_or(&d->ram->int_pending, le_events);
a19cbfb3
GH		 1744 if ((old_pending & le_events) == le_events) {
1745 return;
1746 }
4a46c99c 1747 qemu_bh_schedule(d->update_irq);
a19cbfb3
GH		 1748}
1749
1750/* graphics console */
1751
1752static void qxl_hw_update(void *opaque)
1753{
1754 PCIQXLDevice *qxl = opaque;
1755 VGACommonState *vga = &qxl->vga;
1756
1757 switch (qxl->mode) {
1758 case QXL_MODE_VGA:
380cd056 1759 vga->hw_ops->gfx_update(vga);
a19cbfb3
GH		 1760 break;
1761 case QXL_MODE_COMPAT:
1762 case QXL_MODE_NATIVE:
1763 qxl_render_update(qxl);
1764 break;
1765 default:
1766 break;
1767 }
1768}
1769
1770static void qxl_hw_invalidate(void *opaque)
1771{
1772 PCIQXLDevice *qxl = opaque;
1773 VGACommonState *vga = &qxl->vga;
1774
bfe528b9
GH		 1775 if (qxl->mode == QXL_MODE_VGA) {
1776 vga->hw_ops->invalidate(vga);
1777 return;
1778 }
a19cbfb3
GH		 1779}
1780
a19cbfb3
GH		 1781static void qxl_hw_text_update(void *opaque, console_ch_t *chardata)
1782{
1783 PCIQXLDevice *qxl = opaque;
1784 VGACommonState *vga = &qxl->vga;
1785
1786 if (qxl->mode == QXL_MODE_VGA) {
380cd056 1787 vga->hw_ops->text_update(vga, chardata);
a19cbfb3
GH		 1788 return;
1789 }
1790}
1791
e25139b3
YH		 1792static void qxl_dirty_surfaces(PCIQXLDevice *qxl)
1793{
c5825ac6 1794 uintptr_t vram_start;
e25139b3
YH		 1795 int i;
1796
2aa9e85c 1797 if (qxl->mode != QXL_MODE_NATIVE && qxl->mode != QXL_MODE_COMPAT) {
e25139b3
YH		 1798 return;
1799 }
1800
1801 /* dirty the primary surface */
1802 qxl_set_dirty(&qxl->vga.vram, qxl->shadow_rom.draw_area_offset,
1803 qxl->shadow_rom.surface0_area_size);
1804
c5825ac6 1805 vram_start = (uintptr_t)memory_region_get_ram_ptr(&qxl->vram_bar);
e25139b3
YH		 1806
1807 /* dirty the off-screen surfaces */
ddd8fdc7 1808 for (i = 0; i < qxl->ssd.num_surfaces; i++) {
e25139b3
YH		 1809 QXLSurfaceCmd *cmd;
1810 intptr_t surface_offset;
1811 int surface_size;
1812
1813 if (qxl->guest_surfaces.cmds[i] == 0) {
1814 continue;
1815 }
1816
1817 cmd = qxl_phys2virt(qxl, qxl->guest_surfaces.cmds[i],
1818 MEMSLOT_GROUP_GUEST);
fae2afb1 1819 assert(cmd);
e25139b3
YH		 1820 assert(cmd->type == QXL_SURFACE_CMD_CREATE);
1821 surface_offset = (intptr_t)qxl_phys2virt(qxl,
1822 cmd->u.surface_create.data,
1823 MEMSLOT_GROUP_GUEST);
fae2afb1 1824 assert(surface_offset);
e25139b3
YH		 1825 surface_offset -= vram_start;
1826 surface_size = cmd->u.surface_create.height *
1827 abs(cmd->u.surface_create.stride);
c480bb7d 1828 trace_qxl_surfaces_dirty(qxl->id, i, (int)surface_offset, surface_size);
e25139b3
YH		 1829 qxl_set_dirty(&qxl->vram_bar, surface_offset, surface_size);
1830 }
1831}
1832
1dfb4dd9
LC		 1833static void qxl_vm_change_state_handler(void *opaque, int running,
1834 RunState state)
a19cbfb3
GH		 1835{
1836 PCIQXLDevice *qxl = opaque;
a19cbfb3 1837
efbf2950
YH		 1838 if (running) {
1839 /*
1840 * if qxl_send_events was called from spice server context before
40010aea 1841 * migration ended, qxl_update_irq for these events might not have been
efbf2950
YH		 1842 * called
1843 */
40010aea 1844 qxl_update_irq(qxl);
e25139b3
YH		 1845 } else {
1846 /* make sure surfaces are saved before migration */
1847 qxl_dirty_surfaces(qxl);
a19cbfb3
GH		 1848 }
1849}
1850
1851/* display change listener */
1852
7c20b4a3 1853static void display_update(DisplayChangeListener *dcl,
7c20b4a3 1854 int x, int y, int w, int h)
a19cbfb3 1855{
c6c06853
GH		 1856 PCIQXLDevice *qxl = container_of(dcl, PCIQXLDevice, ssd.dcl);
1857
1858 if (qxl->mode == QXL_MODE_VGA) {
1859 qemu_spice_display_update(&qxl->ssd, x, y, w, h);
a19cbfb3
GH		 1860 }
1861}
1862
c12aeb86 1863static void display_switch(DisplayChangeListener *dcl,
c12aeb86 1864 struct DisplaySurface *surface)
a19cbfb3 1865{
c6c06853
GH		 1866 PCIQXLDevice *qxl = container_of(dcl, PCIQXLDevice, ssd.dcl);
1867
71874c17 1868 qxl->ssd.ds = surface;
c6c06853 1869 if (qxl->mode == QXL_MODE_VGA) {
c12aeb86 1870 qemu_spice_display_switch(&qxl->ssd, surface);
a19cbfb3
GH		 1871 }
1872}
1873
bc2ed970 1874static void display_refresh(DisplayChangeListener *dcl)
a19cbfb3 1875{
c6c06853
GH		 1876 PCIQXLDevice *qxl = container_of(dcl, PCIQXLDevice, ssd.dcl);
1877
1878 if (qxl->mode == QXL_MODE_VGA) {
1879 qemu_spice_display_refresh(&qxl->ssd);
bb5a8cd5 1880 } else {
c6c06853
GH		 1881 qemu_mutex_lock(&qxl->ssd.lock);
1882 qemu_spice_cursor_refresh_unlocked(&qxl->ssd);
1883 qemu_mutex_unlock(&qxl->ssd.lock);
a19cbfb3
GH		 1884 }
1885}
1886
7c20b4a3
GH		 1887static DisplayChangeListenerOps display_listener_ops = {
1888 .dpy_name = "spice/qxl",
a93a4a22 1889 .dpy_gfx_update = display_update,
c12aeb86 1890 .dpy_gfx_switch = display_switch,
7c20b4a3 1891 .dpy_refresh = display_refresh,
a19cbfb3
GH		 1892};
1893
13d1fd44 1894static void qxl_init_ramsize(PCIQXLDevice *qxl)
a974192c 1895{
13d1fd44
AL		 1896 /* vga mode framebuffer / primary surface (bar 0, first part) */
1897 if (qxl->vgamem_size_mb < 8) {
1898 qxl->vgamem_size_mb = 8;
1899 }
1900 qxl->vgamem_size = qxl->vgamem_size_mb * 1024 * 1024;
1901
1902 /* vga ram (bar 0, total) */
017438ee
GH		 1903 if (qxl->ram_size_mb != -1) {
1904 qxl->vga.vram_size = qxl->ram_size_mb * 1024 * 1024;
1905 }
13d1fd44
AL		 1906 if (qxl->vga.vram_size < qxl->vgamem_size * 2) {
1907 qxl->vga.vram_size = qxl->vgamem_size * 2;
a974192c
GH		 1908 }
1909
6f2b175a
GH		 1910 /* vram32 (surfaces, 32bit, bar 1) */
1911 if (qxl->vram32_size_mb != -1) {
1912 qxl->vram32_size = qxl->vram32_size_mb * 1024 * 1024;
1913 }
1914 if (qxl->vram32_size < 4096) {
1915 qxl->vram32_size = 4096;
1916 }
1917
1918 /* vram (surfaces, 64bit, bar 4+5) */
017438ee
GH		 1919 if (qxl->vram_size_mb != -1) {
1920 qxl->vram_size = qxl->vram_size_mb * 1024 * 1024;
1921 }
6f2b175a
GH		 1922 if (qxl->vram_size < qxl->vram32_size) {
1923 qxl->vram_size = qxl->vram32_size;
a974192c 1924 }
6f2b175a 1925
a974192c 1926 if (qxl->revision == 1) {
6f2b175a 1927 qxl->vram32_size = 4096;
a974192c
GH		 1928 qxl->vram_size = 4096;
1929 }
13d1fd44 1930 qxl->vgamem_size = msb_mask(qxl->vgamem_size * 2 - 1);
a974192c 1931 qxl->vga.vram_size = msb_mask(qxl->vga.vram_size * 2 - 1);
6f2b175a 1932 qxl->vram32_size = msb_mask(qxl->vram32_size * 2 - 1);
a974192c
GH		 1933 qxl->vram_size = msb_mask(qxl->vram_size * 2 - 1);
1934}
1935
a19cbfb3
GH		 1936static int qxl_init_common(PCIQXLDevice *qxl)
1937{
1938 uint8_t* config = qxl->pci.config;
a19cbfb3
GH		 1939 uint32_t pci_device_rev;
1940 uint32_t io_size;
1941
1942 qxl->mode = QXL_MODE_UNDEFINED;
1943 qxl->generation = 1;
1944 qxl->num_memslots = NUM_MEMSLOTS;
14898cf6 1945 qemu_mutex_init(&qxl->track_lock);
5ff4e36c
AL		 1946 qemu_mutex_init(&qxl->async_lock);
1947 qxl->current_async = QXL_UNDEFINED_IO;
087e6a42 1948 qxl->guest_bug = 0;
a19cbfb3
GH		 1949
1950 switch (qxl->revision) {
1951 case 1: /* spice 0.4 -- qxl-1 */
a19cbfb3 1952 pci_device_rev = QXL_REVISION_STABLE_V04;
3f6297b9 1953 io_size = 8;
a19cbfb3
GH		 1954 break;
1955 case 2: /* spice 0.6 -- qxl-2 */
a19cbfb3 1956 pci_device_rev = QXL_REVISION_STABLE_V06;
3f6297b9 1957 io_size = 16;
a19cbfb3 1958 break;
9197a7c8 1959 case 3: /* qxl-3 */
020af1c4
AL		 1960 pci_device_rev = QXL_REVISION_STABLE_V10;
1961 io_size = 32; /* PCI region size must be pow2 */
1962 break;
020af1c4
AL		 1963 case 4: /* qxl-4 */
1964 pci_device_rev = QXL_REVISION_STABLE_V12;
3f6297b9 1965 io_size = msb_mask(QXL_IO_RANGE_SIZE * 2 - 1);
9197a7c8 1966 break;
36839d35
AL		 1967 default:
1968 error_report("Invalid revision %d for qxl device (max %d)",
1969 qxl->revision, QXL_DEFAULT_REVISION);
1970 return -1;
a19cbfb3
GH		 1971 }
1972
a19cbfb3
GH		 1973 pci_set_byte(&config[PCI_REVISION_ID], pci_device_rev);
1974 pci_set_byte(&config[PCI_INTERRUPT_PIN], 1);
1975
1976 qxl->rom_size = qxl_rom_size();
3eadad55
PB		 1977 memory_region_init_ram(&qxl->rom_bar, OBJECT(qxl), "qxl.vrom",
1978 qxl->rom_size);
c5705a77 1979 vmstate_register_ram(&qxl->rom_bar, &qxl->pci.qdev);
a19cbfb3
GH		 1980 init_qxl_rom(qxl);
1981 init_qxl_ram(qxl);
1982
ddd8fdc7 1983 qxl->guest_surfaces.cmds = g_new0(QXLPHYSICAL, qxl->ssd.num_surfaces);
3eadad55
PB		 1984 memory_region_init_ram(&qxl->vram_bar, OBJECT(qxl), "qxl.vram",
1985 qxl->vram_size);
c5705a77 1986 vmstate_register_ram(&qxl->vram_bar, &qxl->pci.qdev);
3eadad55
PB		 1987 memory_region_init_alias(&qxl->vram32_bar, OBJECT(qxl), "qxl.vram32",
1988 &qxl->vram_bar, 0, qxl->vram32_size);
a19cbfb3 1989
3eadad55 1990 memory_region_init_io(&qxl->io_bar, OBJECT(qxl), &qxl_io_ops, qxl,
b1950430
AK		 1991 "qxl-ioports", io_size);
1992 if (qxl->id == 0) {
1993 vga_dirty_log_start(&qxl->vga);
1994 }
bd8f2f5d 1995 memory_region_set_flush_coalesced(&qxl->io_bar);
b1950430
AK		 1996
1997
e824b2cc
AK		 1998 pci_register_bar(&qxl->pci, QXL_IO_RANGE_INDEX,
1999 PCI_BASE_ADDRESS_SPACE_IO, &qxl->io_bar);
a19cbfb3 2000
e824b2cc
AK		 2001 pci_register_bar(&qxl->pci, QXL_ROM_RANGE_INDEX,
2002 PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->rom_bar);
a19cbfb3 2003
e824b2cc
AK		 2004 pci_register_bar(&qxl->pci, QXL_RAM_RANGE_INDEX,
2005 PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->vga.vram);
a19cbfb3 2006
e824b2cc 2007 pci_register_bar(&qxl->pci, QXL_VRAM_RANGE_INDEX,
6f2b175a
GH		 2008 PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->vram32_bar);
2009
2010 if (qxl->vram32_size < qxl->vram_size) {
2011 /*
2012 * Make the 64bit vram bar show up only in case it is
2013 * configured to be larger than the 32bit vram bar.
2014 */
2015 pci_register_bar(&qxl->pci, QXL_VRAM64_RANGE_INDEX,
2016 PCI_BASE_ADDRESS_SPACE_MEMORY |
2017 PCI_BASE_ADDRESS_MEM_TYPE_64 |
2018 PCI_BASE_ADDRESS_MEM_PREFETCH,
2019 &qxl->vram_bar);
2020 }
2021
2022 /* print pci bar details */
2023 dprint(qxl, 1, "ram/%s: %d MB [region 0]\n",
2024 qxl->id == 0 ? "pri" : "sec",
2025 qxl->vga.vram_size / (1024*1024));
2026 dprint(qxl, 1, "vram/32: %d MB [region 1]\n",
2027 qxl->vram32_size / (1024*1024));
2028 dprint(qxl, 1, "vram/64: %d MB %s\n",
2029 qxl->vram_size / (1024*1024),
2030 qxl->vram32_size < qxl->vram_size ? "[region 4]" : "[unmapped]");
a19cbfb3
GH		 2031
2032 qxl->ssd.qxl.base.sif = &qxl_interface.base;
9fa03286 2033 if (qemu_spice_add_display_interface(&qxl->ssd.qxl, qxl->vga.con) != 0) {
312fd5f2 2034 error_report("qxl interface %d.%d not supported by spice-server",
e25a0651
AL		 2035 SPICE_INTERFACE_QXL_MAJOR, SPICE_INTERFACE_QXL_MINOR);
2036 return -1;
2037 }
a19cbfb3
GH		 2038 qemu_add_vm_change_state_handler(qxl_vm_change_state_handler, qxl);
2039
4a46c99c 2040 qxl->update_irq = qemu_bh_new(qxl_update_irq_bh, qxl);
a19cbfb3
GH		 2041 qxl_reset_state(qxl);
2042
81fb6f15
AL		 2043 qxl->update_area_bh = qemu_bh_new(qxl_render_update_area_bh, qxl);
2044
a19cbfb3
GH		 2045 return 0;
2046}
2047
380cd056
GH		 2048static const GraphicHwOps qxl_ops = {
2049 .invalidate = qxl_hw_invalidate,
2050 .gfx_update = qxl_hw_update,
2051 .text_update = qxl_hw_text_update,
2052};
2053
a19cbfb3
GH		 2054static int qxl_init_primary(PCIDevice *dev)
2055{
2056 PCIQXLDevice *qxl = DO_UPCAST(PCIQXLDevice, pci, dev);
2057 VGACommonState *vga = &qxl->vga;
f67ab77a 2058 PortioList *qxl_vga_port_list = g_new(PortioList, 1);
bdd4df33 2059 int rc;
a19cbfb3
GH		 2060
2061 qxl->id = 0;
13d1fd44 2062 qxl_init_ramsize(qxl);
4a1e244e 2063 vga->vram_size_mb = qxl->vga.vram_size >> 20;
270327fe 2064 vga_common_init(vga, OBJECT(dev));
712f0cc7
PB		 2065 vga_init(vga, OBJECT(dev),
2066 pci_address_space(dev), pci_address_space_io(dev), false);
db10ca90
PB		 2067 portio_list_init(qxl_vga_port_list, OBJECT(dev), qxl_vga_portio_list,
2068 vga, "vga");
c46860ea 2069 portio_list_set_flush_coalesced(qxl_vga_port_list);
f67ab77a 2070 portio_list_add(qxl_vga_port_list, pci_address_space_io(dev), 0x3b0);
a19cbfb3 2071
5643706a 2072 vga->con = graphic_console_init(DEVICE(dev), 0, &qxl_ops, qxl);
c78f7137 2073 qemu_spice_display_init_common(&qxl->ssd);
a19cbfb3 2074
bdd4df33
GH		 2075 rc = qxl_init_common(qxl);
2076 if (rc != 0) {
2077 return rc;
2078 }
2079
7c20b4a3 2080 qxl->ssd.dcl.ops = &display_listener_ops;
284d1c6b 2081 qxl->ssd.dcl.con = vga->con;
5209089f 2082 register_displaychangelistener(&qxl->ssd.dcl);
bdd4df33 2083 return rc;
a19cbfb3
GH		 2084}
2085
2086static int qxl_init_secondary(PCIDevice *dev)
2087{
2088 static int device_id = 1;
2089 PCIQXLDevice *qxl = DO_UPCAST(PCIQXLDevice, pci, dev);
a19cbfb3
GH		 2090
2091 qxl->id = device_id++;
13d1fd44 2092 qxl_init_ramsize(qxl);
3eadad55
PB		 2093 memory_region_init_ram(&qxl->vga.vram, OBJECT(dev), "qxl.vgavram",
2094 qxl->vga.vram_size);
c5705a77 2095 vmstate_register_ram(&qxl->vga.vram, &qxl->pci.qdev);
b1950430 2096 qxl->vga.vram_ptr = memory_region_get_ram_ptr(&qxl->vga.vram);
5643706a 2097 qxl->vga.con = graphic_console_init(DEVICE(dev), 0, &qxl_ops, qxl);
a19cbfb3 2098
a19cbfb3
GH		 2099 return qxl_init_common(qxl);
2100}
2101
2102static void qxl_pre_save(void *opaque)
2103{
2104 PCIQXLDevice* d = opaque;
2105 uint8_t *ram_start = d->vga.vram_ptr;
2106
c480bb7d 2107 trace_qxl_pre_save(d->id);
a19cbfb3
GH		 2108 if (d->last_release == NULL) {
2109 d->last_release_offset = 0;
2110 } else {
2111 d->last_release_offset = (uint8_t *)d->last_release - ram_start;
2112 }
2113 assert(d->last_release_offset < d->vga.vram_size);
2114}
2115
2116static int qxl_pre_load(void *opaque)
2117{
2118 PCIQXLDevice* d = opaque;
2119
c480bb7d 2120 trace_qxl_pre_load(d->id);
a19cbfb3
GH		 2121 qxl_hard_reset(d, 1);
2122 qxl_exit_vga_mode(d);
a19cbfb3
GH		 2123 return 0;
2124}
2125
54825d2e
AL		 2126static void qxl_create_memslots(PCIQXLDevice *d)
2127{
2128 int i;
2129
2130 for (i = 0; i < NUM_MEMSLOTS; i++) {
2131 if (!d->guest_slots[i].active) {
2132 continue;
2133 }
54825d2e
AL		 2134 qxl_add_memslot(d, i, 0, QXL_SYNC);
2135 }
2136}
2137
a19cbfb3
GH		 2138static int qxl_post_load(void *opaque, int version)
2139{
2140 PCIQXLDevice* d = opaque;
2141 uint8_t *ram_start = d->vga.vram_ptr;
2142 QXLCommandExt *cmds;
54825d2e 2143 int in, out, newmode;
a19cbfb3 2144
a19cbfb3
GH		 2145 assert(d->last_release_offset < d->vga.vram_size);
2146 if (d->last_release_offset == 0) {
2147 d->last_release = NULL;
2148 } else {
2149 d->last_release = (QXLReleaseInfo *)(ram_start + d->last_release_offset);
2150 }
2151
2152 d->modes = (QXLModes*)((uint8_t*)d->rom + d->rom->modes_offset);
2153
c480bb7d 2154 trace_qxl_post_load(d->id, qxl_mode_to_string(d->mode));
a19cbfb3
GH		 2155 newmode = d->mode;
2156 d->mode = QXL_MODE_UNDEFINED;
54825d2e 2157
a19cbfb3
GH		 2158 switch (newmode) {
2159 case QXL_MODE_UNDEFINED:
fa98efe9 2160 qxl_create_memslots(d);
a19cbfb3
GH		 2161 break;
2162 case QXL_MODE_VGA:
54825d2e 2163 qxl_create_memslots(d);
a19cbfb3
GH		 2164 qxl_enter_vga_mode(d);
2165 break;
2166 case QXL_MODE_NATIVE:
54825d2e 2167 qxl_create_memslots(d);
5ff4e36c 2168 qxl_create_guest_primary(d, 1, QXL_SYNC);
a19cbfb3
GH		 2169
2170 /* replay surface-create and cursor-set commands */
ddd8fdc7
GH		 2171 cmds = g_malloc0(sizeof(QXLCommandExt) * (d->ssd.num_surfaces + 1));
2172 for (in = 0, out = 0; in < d->ssd.num_surfaces; in++) {
a19cbfb3
GH		 2173 if (d->guest_surfaces.cmds[in] == 0) {
2174 continue;
2175 }
2176 cmds[out].cmd.data = d->guest_surfaces.cmds[in];
2177 cmds[out].cmd.type = QXL_CMD_SURFACE;
2178 cmds[out].group_id = MEMSLOT_GROUP_GUEST;
2179 out++;
2180 }
30f6da66
YH		 2181 if (d->guest_cursor) {
2182 cmds[out].cmd.data = d->guest_cursor;
2183 cmds[out].cmd.type = QXL_CMD_CURSOR;
2184 cmds[out].group_id = MEMSLOT_GROUP_GUEST;
2185 out++;
2186 }
aee32bf3 2187 qxl_spice_loadvm_commands(d, cmds, out);
7267c094 2188 g_free(cmds);
020af1c4
AL		 2189 if (d->guest_monitors_config) {
2190 qxl_spice_monitors_config_async(d, 1);
2191 }
a19cbfb3
GH		 2192 break;
2193 case QXL_MODE_COMPAT:
54825d2e
AL		 2194 /* note: no need to call qxl_create_memslots, qxl_set_mode
2195 * creates the mem slot. */
a19cbfb3
GH		 2196 qxl_set_mode(d, d->shadow_rom.mode, 1);
2197 break;
2198 }
a19cbfb3
GH		 2199 return 0;
2200}
2201
b67737a6 2202#define QXL_SAVE_VERSION 21
a19cbfb3 2203
020af1c4
AL		 2204static bool qxl_monitors_config_needed(void *opaque)
2205{
2206 PCIQXLDevice *qxl = opaque;
2207
2208 return qxl->guest_monitors_config != 0;
2209}
2210
2211
a19cbfb3
GH		 2212static VMStateDescription qxl_memslot = {
2213 .name = "qxl-memslot",
2214 .version_id = QXL_SAVE_VERSION,
2215 .minimum_version_id = QXL_SAVE_VERSION,
2216 .fields = (VMStateField[]) {
2217 VMSTATE_UINT64(slot.mem_start, struct guest_slots),
2218 VMSTATE_UINT64(slot.mem_end, struct guest_slots),
2219 VMSTATE_UINT32(active, struct guest_slots),
2220 VMSTATE_END_OF_LIST()
2221 }
2222};
2223
2224static VMStateDescription qxl_surface = {
2225 .name = "qxl-surface",
2226 .version_id = QXL_SAVE_VERSION,
2227 .minimum_version_id = QXL_SAVE_VERSION,
2228 .fields = (VMStateField[]) {
2229 VMSTATE_UINT32(width, QXLSurfaceCreate),
2230 VMSTATE_UINT32(height, QXLSurfaceCreate),
2231 VMSTATE_INT32(stride, QXLSurfaceCreate),
2232 VMSTATE_UINT32(format, QXLSurfaceCreate),
2233 VMSTATE_UINT32(position, QXLSurfaceCreate),
2234 VMSTATE_UINT32(mouse_mode, QXLSurfaceCreate),
2235 VMSTATE_UINT32(flags, QXLSurfaceCreate),
2236 VMSTATE_UINT32(type, QXLSurfaceCreate),
2237 VMSTATE_UINT64(mem, QXLSurfaceCreate),
2238 VMSTATE_END_OF_LIST()
2239 }
2240};
2241
020af1c4
AL		 2242static VMStateDescription qxl_vmstate_monitors_config = {
2243 .name = "qxl/monitors-config",
2244 .version_id = 1,
2245 .minimum_version_id = 1,
2246 .fields = (VMStateField[]) {
2247 VMSTATE_UINT64(guest_monitors_config, PCIQXLDevice),
2248 VMSTATE_END_OF_LIST()
2249 },
2250};
2251
a19cbfb3
GH		 2252static VMStateDescription qxl_vmstate = {
2253 .name = "qxl",
2254 .version_id = QXL_SAVE_VERSION,
2255 .minimum_version_id = QXL_SAVE_VERSION,
2256 .pre_save = qxl_pre_save,
2257 .pre_load = qxl_pre_load,
2258 .post_load = qxl_post_load,
020af1c4 2259 .fields = (VMStateField[]) {
a19cbfb3
GH		 2260 VMSTATE_PCI_DEVICE(pci, PCIQXLDevice),
2261 VMSTATE_STRUCT(vga, PCIQXLDevice, 0, vmstate_vga_common, VGACommonState),
2262 VMSTATE_UINT32(shadow_rom.mode, PCIQXLDevice),
2263 VMSTATE_UINT32(num_free_res, PCIQXLDevice),
2264 VMSTATE_UINT32(last_release_offset, PCIQXLDevice),
2265 VMSTATE_UINT32(mode, PCIQXLDevice),
2266 VMSTATE_UINT32(ssd.unique, PCIQXLDevice),
b67737a6
GH		 2267 VMSTATE_INT32_EQUAL(num_memslots, PCIQXLDevice),
2268 VMSTATE_STRUCT_ARRAY(guest_slots, PCIQXLDevice, NUM_MEMSLOTS, 0,
2269 qxl_memslot, struct guest_slots),
2270 VMSTATE_STRUCT(guest_primary.surface, PCIQXLDevice, 0,
2271 qxl_surface, QXLSurfaceCreate),
ddd8fdc7
GH		 2272 VMSTATE_INT32_EQUAL(ssd.num_surfaces, PCIQXLDevice),
2273 VMSTATE_VARRAY_INT32(guest_surfaces.cmds, PCIQXLDevice,
2274 ssd.num_surfaces, 0,
2275 vmstate_info_uint64, uint64_t),
b67737a6 2276 VMSTATE_UINT64(guest_cursor, PCIQXLDevice),
a19cbfb3
GH		 2277 VMSTATE_END_OF_LIST()
2278 },
020af1c4
AL		 2279 .subsections = (VMStateSubsection[]) {
2280 {
2281 .vmsd = &qxl_vmstate_monitors_config,
2282 .needed = qxl_monitors_config_needed,
2283 }, {
2284 /* empty */
2285 }
2286 }
a19cbfb3
GH		 2287};
2288
78e60ba5
GH		 2289static Property qxl_properties[] = {
2290 DEFINE_PROP_UINT32("ram_size", PCIQXLDevice, vga.vram_size,
2291 64 * 1024 * 1024),
6f2b175a 2292 DEFINE_PROP_UINT32("vram_size", PCIQXLDevice, vram32_size,
78e60ba5
GH		 2293 64 * 1024 * 1024),
2294 DEFINE_PROP_UINT32("revision", PCIQXLDevice, revision,
2295 QXL_DEFAULT_REVISION),
2296 DEFINE_PROP_UINT32("debug", PCIQXLDevice, debug, 0),
2297 DEFINE_PROP_UINT32("guestdebug", PCIQXLDevice, guestdebug, 0),
2298 DEFINE_PROP_UINT32("cmdlog", PCIQXLDevice, cmdlog, 0),
017438ee 2299 DEFINE_PROP_UINT32("ram_size_mb", PCIQXLDevice, ram_size_mb, -1),
79ce3567
AL		 2300 DEFINE_PROP_UINT32("vram_size_mb", PCIQXLDevice, vram32_size_mb, -1),
2301 DEFINE_PROP_UINT32("vram64_size_mb", PCIQXLDevice, vram_size_mb, -1),
9e56edcf 2302 DEFINE_PROP_UINT32("vgamem_mb", PCIQXLDevice, vgamem_size_mb, 16),
ddd8fdc7 2303 DEFINE_PROP_INT32("surfaces", PCIQXLDevice, ssd.num_surfaces, 1024),
78e60ba5
GH		 2304 DEFINE_PROP_END_OF_LIST(),
2305};
2306
40021f08
AL		 2307static void qxl_primary_class_init(ObjectClass *klass, void *data)
2308{
39bffca2 2309 DeviceClass *dc = DEVICE_CLASS(klass);
40021f08
AL		 2310 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
2311
40021f08
AL		 2312 k->init = qxl_init_primary;
2313 k->romfile = "vgabios-qxl.bin";
2314 k->vendor_id = REDHAT_PCI_VENDOR_ID;
2315 k->device_id = QXL_DEVICE_ID_STABLE;
2316 k->class_id = PCI_CLASS_DISPLAY_VGA;
125ee0ed 2317 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
39bffca2
AL		 2318 dc->desc = "Spice QXL GPU (primary, vga compatible)";
2319 dc->reset = qxl_reset_handler;
2320 dc->vmsd = &qxl_vmstate;
2321 dc->props = qxl_properties;
2897ae02 2322 dc->hotpluggable = false;
40021f08
AL		 2323}
2324
8c43a6f0 2325static const TypeInfo qxl_primary_info = {
39bffca2
AL		 2326 .name = "qxl-vga",
2327 .parent = TYPE_PCI_DEVICE,
2328 .instance_size = sizeof(PCIQXLDevice),
2329 .class_init = qxl_primary_class_init,
a19cbfb3
GH		 2330};
2331
40021f08
AL		 2332static void qxl_secondary_class_init(ObjectClass *klass, void *data)
2333{
39bffca2 2334 DeviceClass *dc = DEVICE_CLASS(klass);
40021f08
AL		 2335 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
2336
2337 k->init = qxl_init_secondary;
2338 k->vendor_id = REDHAT_PCI_VENDOR_ID;
2339 k->device_id = QXL_DEVICE_ID_STABLE;
2340 k->class_id = PCI_CLASS_DISPLAY_OTHER;
125ee0ed 2341 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
39bffca2
AL		 2342 dc->desc = "Spice QXL GPU (secondary)";
2343 dc->reset = qxl_reset_handler;
2344 dc->vmsd = &qxl_vmstate;
2345 dc->props = qxl_properties;
40021f08
AL		 2346}
2347
8c43a6f0 2348static const TypeInfo qxl_secondary_info = {
39bffca2
AL		 2349 .name = "qxl",
2350 .parent = TYPE_PCI_DEVICE,
2351 .instance_size = sizeof(PCIQXLDevice),
2352 .class_init = qxl_secondary_class_init,
a19cbfb3
GH		 2353};
2354
83f7d43a 2355static void qxl_register_types(void)
a19cbfb3 2356{
39bffca2
AL		 2357 type_register_static(&qxl_primary_info);
2358 type_register_static(&qxl_secondary_info);
a19cbfb3
GH		 2359}
2360
83f7d43a 2361type_init(qxl_register_types)
Empty description
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