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vga: pass owner to vga_init
[qemu.git] / hw / display / qxl.c
CommitLineData
a19cbfb3
GH		 1/*
2 * Copyright (C) 2010 Red Hat, Inc.
3 *
4 * written by Yaniv Kamay, Izik Eidus, Gerd Hoffmann
5 * maintained by Gerd Hoffmann <kraxel@redhat.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 or
10 * (at your option) version 3 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, see <http://www.gnu.org/licenses/>.
19 */
20
a639ab04
AL		 21#include <zlib.h>
22
a19cbfb3 23#include "qemu-common.h"
1de7afc9
PB		 24#include "qemu/timer.h"
25#include "qemu/queue.h"
83c9089e 26#include "monitor/monitor.h"
9c17d615 27#include "sysemu/sysemu.h"
c480bb7d 28#include "trace.h"
a19cbfb3 29
47b43a1f 30#include "qxl.h"
a19cbfb3 31
0b81c478
AL		 32/*
33 * NOTE: SPICE_RING_PROD_ITEM accesses memory on the pci bar and as
34 * such can be changed by the guest, so to avoid a guest trigerrable
0a530548 35 * abort we just qxl_set_guest_bug and set the return to NULL. Still
0b81c478
AL		 36 * it may happen as a result of emulator bug as well.
37 */
a19cbfb3 38#undef SPICE_RING_PROD_ITEM
0b81c478 39#define SPICE_RING_PROD_ITEM(qxl, r, ret) { \
a19cbfb3 40 uint32_t prod = (r)->prod & SPICE_RING_INDEX_MASK(r); \
bc5f92e5 41 if (prod >= ARRAY_SIZE((r)->items)) { \
0a530548 42 qxl_set_guest_bug(qxl, "SPICE_RING_PROD_ITEM indices mismatch " \
bc5f92e5 43 "%u >= %zu", prod, ARRAY_SIZE((r)->items)); \
0b81c478
AL		 44 ret = NULL; \
45 } else { \
bc5f92e5 46 ret = &(r)->items[prod].el; \
a19cbfb3 47 } \
a19cbfb3
GH		 48 }
49
50#undef SPICE_RING_CONS_ITEM
0b81c478 51#define SPICE_RING_CONS_ITEM(qxl, r, ret) { \
a19cbfb3 52 uint32_t cons = (r)->cons & SPICE_RING_INDEX_MASK(r); \
bc5f92e5 53 if (cons >= ARRAY_SIZE((r)->items)) { \
0a530548 54 qxl_set_guest_bug(qxl, "SPICE_RING_CONS_ITEM indices mismatch " \
bc5f92e5 55 "%u >= %zu", cons, ARRAY_SIZE((r)->items)); \
0b81c478
AL		 56 ret = NULL; \
57 } else { \
bc5f92e5 58 ret = &(r)->items[cons].el; \
a19cbfb3 59 } \
a19cbfb3
GH		 60 }
61
62#undef ALIGN
63#define ALIGN(a, b) (((a) + ((b) - 1)) & ~((b) - 1))
64
65#define PIXEL_SIZE 0.2936875 //1280x1024 is 14.8" x 11.9"
66
67#define QXL_MODE(_x, _y, _b, _o) \
68 { .x_res = _x, \
69 .y_res = _y, \
70 .bits = _b, \
71 .stride = (_x) * (_b) / 8, \
72 .x_mili = PIXEL_SIZE * (_x), \
73 .y_mili = PIXEL_SIZE * (_y), \
74 .orientation = _o, \
75 }
76
77#define QXL_MODE_16_32(x_res, y_res, orientation) \
78 QXL_MODE(x_res, y_res, 16, orientation), \
79 QXL_MODE(x_res, y_res, 32, orientation)
80
81#define QXL_MODE_EX(x_res, y_res) \
82 QXL_MODE_16_32(x_res, y_res, 0), \
038c1879 83 QXL_MODE_16_32(x_res, y_res, 1)
a19cbfb3
GH		 84
85static QXLMode qxl_modes[] = {
86 QXL_MODE_EX(640, 480),
87 QXL_MODE_EX(800, 480),
88 QXL_MODE_EX(800, 600),
89 QXL_MODE_EX(832, 624),
90 QXL_MODE_EX(960, 640),
91 QXL_MODE_EX(1024, 600),
92 QXL_MODE_EX(1024, 768),
93 QXL_MODE_EX(1152, 864),
94 QXL_MODE_EX(1152, 870),
95 QXL_MODE_EX(1280, 720),
96 QXL_MODE_EX(1280, 760),
97 QXL_MODE_EX(1280, 768),
98 QXL_MODE_EX(1280, 800),
99 QXL_MODE_EX(1280, 960),
100 QXL_MODE_EX(1280, 1024),
101 QXL_MODE_EX(1360, 768),
102 QXL_MODE_EX(1366, 768),
103 QXL_MODE_EX(1400, 1050),
104 QXL_MODE_EX(1440, 900),
105 QXL_MODE_EX(1600, 900),
106 QXL_MODE_EX(1600, 1200),
107 QXL_MODE_EX(1680, 1050),
108 QXL_MODE_EX(1920, 1080),
a19cbfb3
GH		 109 /* these modes need more than 8 MB video memory */
110 QXL_MODE_EX(1920, 1200),
111 QXL_MODE_EX(1920, 1440),
5c74fb27 112 QXL_MODE_EX(2000, 2000),
a19cbfb3 113 QXL_MODE_EX(2048, 1536),
5c74fb27 114 QXL_MODE_EX(2048, 2048),
a19cbfb3
GH		 115 QXL_MODE_EX(2560, 1440),
116 QXL_MODE_EX(2560, 1600),
a19cbfb3
GH		 117 /* these modes need more than 16 MB video memory */
118 QXL_MODE_EX(2560, 2048),
119 QXL_MODE_EX(2800, 2100),
120 QXL_MODE_EX(3200, 2400),
d4bcb199
GH		 121 QXL_MODE_EX(3840, 2160), /* 4k mainstream */
122 QXL_MODE_EX(4096, 2160), /* 4k */
123 QXL_MODE_EX(7680, 4320), /* 8k mainstream */
124 QXL_MODE_EX(8192, 4320), /* 8k */
a19cbfb3
GH		 125};
126
a19cbfb3 127static void qxl_send_events(PCIQXLDevice *d, uint32_t events);
5ff4e36c 128static int qxl_destroy_primary(PCIQXLDevice *d, qxl_async_io async);
a19cbfb3
GH		 129static void qxl_reset_memslots(PCIQXLDevice *d);
130static void qxl_reset_surfaces(PCIQXLDevice *d);
131static void qxl_ring_set_dirty(PCIQXLDevice *qxl);
132
0a530548 133void qxl_set_guest_bug(PCIQXLDevice *qxl, const char *msg, ...)
2bce0400 134{
917ae08c 135 trace_qxl_set_guest_bug(qxl->id);
2bce0400 136 qxl_send_events(qxl, QXL_INTERRUPT_ERROR);
087e6a42 137 qxl->guest_bug = 1;
2bce0400 138 if (qxl->guestdebug) {
7635392c
AL		 139 va_list ap;
140 va_start(ap, msg);
141 fprintf(stderr, "qxl-%d: guest bug: ", qxl->id);
142 vfprintf(stderr, msg, ap);
143 fprintf(stderr, "\n");
144 va_end(ap);
2bce0400
GH		 145 }
146}
147
087e6a42
AL		 148static void qxl_clear_guest_bug(PCIQXLDevice *qxl)
149{
150 qxl->guest_bug = 0;
151}
aee32bf3
GH		 152
153void qxl_spice_update_area(PCIQXLDevice *qxl, uint32_t surface_id,
154 struct QXLRect *area, struct QXLRect *dirty_rects,
155 uint32_t num_dirty_rects,
5ff4e36c 156 uint32_t clear_dirty_region,
2e1a98c9 157 qxl_async_io async, struct QXLCookie *cookie)
aee32bf3 158{
c480bb7d
AL		 159 trace_qxl_spice_update_area(qxl->id, surface_id, area->left, area->right,
160 area->top, area->bottom);
161 trace_qxl_spice_update_area_rest(qxl->id, num_dirty_rects,
162 clear_dirty_region);
5ff4e36c
AL		 163 if (async == QXL_SYNC) {
164 qxl->ssd.worker->update_area(qxl->ssd.worker, surface_id, area,
165 dirty_rects, num_dirty_rects, clear_dirty_region);
166 } else {
2e1a98c9 167 assert(cookie != NULL);
5ff4e36c 168 spice_qxl_update_area_async(&qxl->ssd.qxl, surface_id, area,
5dba0d45 169 clear_dirty_region, (uintptr_t)cookie);
5ff4e36c 170 }
aee32bf3
GH		 171}
172
5ff4e36c
AL		 173static void qxl_spice_destroy_surface_wait_complete(PCIQXLDevice *qxl,
174 uint32_t id)
aee32bf3 175{
c480bb7d 176 trace_qxl_spice_destroy_surface_wait_complete(qxl->id, id);
14898cf6 177 qemu_mutex_lock(&qxl->track_lock);
14898cf6
GH		 178 qxl->guest_surfaces.cmds[id] = 0;
179 qxl->guest_surfaces.count--;
180 qemu_mutex_unlock(&qxl->track_lock);
aee32bf3
GH		 181}
182
5ff4e36c
AL		 183static void qxl_spice_destroy_surface_wait(PCIQXLDevice *qxl, uint32_t id,
184 qxl_async_io async)
185{
2e1a98c9
AL		 186 QXLCookie *cookie;
187
c480bb7d 188 trace_qxl_spice_destroy_surface_wait(qxl->id, id, async);
5ff4e36c 189 if (async) {
2e1a98c9
AL		 190 cookie = qxl_cookie_new(QXL_COOKIE_TYPE_IO,
191 QXL_IO_DESTROY_SURFACE_ASYNC);
192 cookie->u.surface_id = id;
5dba0d45 193 spice_qxl_destroy_surface_async(&qxl->ssd.qxl, id, (uintptr_t)cookie);
5ff4e36c
AL		 194 } else {
195 qxl->ssd.worker->destroy_surface_wait(qxl->ssd.worker, id);
753b8b0d 196 qxl_spice_destroy_surface_wait_complete(qxl, id);
5ff4e36c
AL		 197 }
198}
199
3e16b9c5
AL		 200static void qxl_spice_flush_surfaces_async(PCIQXLDevice *qxl)
201{
c480bb7d
AL		 202 trace_qxl_spice_flush_surfaces_async(qxl->id, qxl->guest_surfaces.count,
203 qxl->num_free_res);
2e1a98c9 204 spice_qxl_flush_surfaces_async(&qxl->ssd.qxl,
5dba0d45
PM		 205 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO,
206 QXL_IO_FLUSH_SURFACES_ASYNC));
3e16b9c5 207}
3e16b9c5 208
aee32bf3
GH		 209void qxl_spice_loadvm_commands(PCIQXLDevice *qxl, struct QXLCommandExt *ext,
210 uint32_t count)
211{
c480bb7d 212 trace_qxl_spice_loadvm_commands(qxl->id, ext, count);
aee32bf3
GH		 213 qxl->ssd.worker->loadvm_commands(qxl->ssd.worker, ext, count);
214}
215
216void qxl_spice_oom(PCIQXLDevice *qxl)
217{
c480bb7d 218 trace_qxl_spice_oom(qxl->id);
aee32bf3
GH		 219 qxl->ssd.worker->oom(qxl->ssd.worker);
220}
221
222void qxl_spice_reset_memslots(PCIQXLDevice *qxl)
223{
c480bb7d 224 trace_qxl_spice_reset_memslots(qxl->id);
aee32bf3
GH		 225 qxl->ssd.worker->reset_memslots(qxl->ssd.worker);
226}
227
5ff4e36c 228static void qxl_spice_destroy_surfaces_complete(PCIQXLDevice *qxl)
aee32bf3 229{
c480bb7d 230 trace_qxl_spice_destroy_surfaces_complete(qxl->id);
14898cf6 231 qemu_mutex_lock(&qxl->track_lock);
ddd8fdc7 232 memset(qxl->guest_surfaces.cmds, 0,
8bb9f51c 233 sizeof(qxl->guest_surfaces.cmds[0]) * qxl->ssd.num_surfaces);
14898cf6
GH		 234 qxl->guest_surfaces.count = 0;
235 qemu_mutex_unlock(&qxl->track_lock);
aee32bf3
GH		 236}
237
5ff4e36c
AL		 238static void qxl_spice_destroy_surfaces(PCIQXLDevice *qxl, qxl_async_io async)
239{
c480bb7d 240 trace_qxl_spice_destroy_surfaces(qxl->id, async);
5ff4e36c 241 if (async) {
2e1a98c9 242 spice_qxl_destroy_surfaces_async(&qxl->ssd.qxl,
5dba0d45
PM		 243 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO,
244 QXL_IO_DESTROY_ALL_SURFACES_ASYNC));
5ff4e36c
AL		 245 } else {
246 qxl->ssd.worker->destroy_surfaces(qxl->ssd.worker);
247 qxl_spice_destroy_surfaces_complete(qxl);
248 }
249}
250
020af1c4
AL		 251static void qxl_spice_monitors_config_async(PCIQXLDevice *qxl, int replay)
252{
253 trace_qxl_spice_monitors_config(qxl->id);
020af1c4
AL		 254 if (replay) {
255 /*
256 * don't use QXL_COOKIE_TYPE_IO:
257 * - we are not running yet (post_load), we will assert
258 * in send_events
259 * - this is not a guest io, but a reply, so async_io isn't set.
260 */
261 spice_qxl_monitors_config_async(&qxl->ssd.qxl,
262 qxl->guest_monitors_config,
263 MEMSLOT_GROUP_GUEST,
264 (uintptr_t)qxl_cookie_new(
265 QXL_COOKIE_TYPE_POST_LOAD_MONITORS_CONFIG,
266 0));
267 } else {
268 qxl->guest_monitors_config = qxl->ram->monitors_config;
269 spice_qxl_monitors_config_async(&qxl->ssd.qxl,
270 qxl->ram->monitors_config,
271 MEMSLOT_GROUP_GUEST,
272 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO,
273 QXL_IO_MONITORS_CONFIG_ASYNC));
274 }
020af1c4
AL		 275}
276
aee32bf3
GH		 277void qxl_spice_reset_image_cache(PCIQXLDevice *qxl)
278{
c480bb7d 279 trace_qxl_spice_reset_image_cache(qxl->id);
aee32bf3
GH		 280 qxl->ssd.worker->reset_image_cache(qxl->ssd.worker);
281}
282
283void qxl_spice_reset_cursor(PCIQXLDevice *qxl)
284{
c480bb7d 285 trace_qxl_spice_reset_cursor(qxl->id);
aee32bf3 286 qxl->ssd.worker->reset_cursor(qxl->ssd.worker);
30f6da66
YH		 287 qemu_mutex_lock(&qxl->track_lock);
288 qxl->guest_cursor = 0;
289 qemu_mutex_unlock(&qxl->track_lock);
958c2bce
GH		 290 if (qxl->ssd.cursor) {
291 cursor_put(qxl->ssd.cursor);
292 }
293 qxl->ssd.cursor = cursor_builtin_hidden();
aee32bf3
GH		 294}
295
296
a19cbfb3
GH		 297static inline uint32_t msb_mask(uint32_t val)
298{
299 uint32_t mask;
300
301 do {
302 mask = ~(val - 1) & val;
303 val &= ~mask;
304 } while (mask < val);
305
306 return mask;
307}
308
309static ram_addr_t qxl_rom_size(void)
310{
038c1879
AL		 311 uint32_t required_rom_size = sizeof(QXLRom) + sizeof(QXLModes) +
312 sizeof(qxl_modes);
313 uint32_t rom_size = 8192; /* two pages */
13d1fd44 314
038c1879
AL		 315 required_rom_size = MAX(required_rom_size, TARGET_PAGE_SIZE);
316 required_rom_size = msb_mask(required_rom_size * 2 - 1);
317 assert(required_rom_size <= rom_size);
a19cbfb3
GH		 318 return rom_size;
319}
320
321static void init_qxl_rom(PCIQXLDevice *d)
322{
b1950430 323 QXLRom *rom = memory_region_get_ram_ptr(&d->rom_bar);
a19cbfb3
GH		 324 QXLModes *modes = (QXLModes *)(rom + 1);
325 uint32_t ram_header_size;
326 uint32_t surface0_area_size;
327 uint32_t num_pages;
13d1fd44
AL		 328 uint32_t fb;
329 int i, n;
a19cbfb3
GH		 330
331 memset(rom, 0, d->rom_size);
332
333 rom->magic = cpu_to_le32(QXL_ROM_MAGIC);
334 rom->id = cpu_to_le32(d->id);
335 rom->log_level = cpu_to_le32(d->guestdebug);
336 rom->modes_offset = cpu_to_le32(sizeof(QXLRom));
337
338 rom->slot_gen_bits = MEMSLOT_GENERATION_BITS;
339 rom->slot_id_bits = MEMSLOT_SLOT_BITS;
340 rom->slots_start = 1;
341 rom->slots_end = NUM_MEMSLOTS - 1;
ddd8fdc7 342 rom->n_surfaces = cpu_to_le32(d->ssd.num_surfaces);
a19cbfb3 343
13d1fd44 344 for (i = 0, n = 0; i < ARRAY_SIZE(qxl_modes); i++) {
a19cbfb3 345 fb = qxl_modes[i].y_res * qxl_modes[i].stride;
13d1fd44
AL		 346 if (fb > d->vgamem_size) {
347 continue;
a19cbfb3 348 }
13d1fd44
AL		 349 modes->modes[n].id = cpu_to_le32(i);
350 modes->modes[n].x_res = cpu_to_le32(qxl_modes[i].x_res);
351 modes->modes[n].y_res = cpu_to_le32(qxl_modes[i].y_res);
352 modes->modes[n].bits = cpu_to_le32(qxl_modes[i].bits);
353 modes->modes[n].stride = cpu_to_le32(qxl_modes[i].stride);
354 modes->modes[n].x_mili = cpu_to_le32(qxl_modes[i].x_mili);
355 modes->modes[n].y_mili = cpu_to_le32(qxl_modes[i].y_mili);
356 modes->modes[n].orientation = cpu_to_le32(qxl_modes[i].orientation);
357 n++;
358 }
359 modes->n_modes = cpu_to_le32(n);
a19cbfb3
GH		 360
361 ram_header_size = ALIGN(sizeof(QXLRam), 4096);
13d1fd44 362 surface0_area_size = ALIGN(d->vgamem_size, 4096);
a19cbfb3
GH		 363 num_pages = d->vga.vram_size;
364 num_pages -= ram_header_size;
365 num_pages -= surface0_area_size;
366 num_pages = num_pages / TARGET_PAGE_SIZE;
367
368 rom->draw_area_offset = cpu_to_le32(0);
369 rom->surface0_area_size = cpu_to_le32(surface0_area_size);
370 rom->pages_offset = cpu_to_le32(surface0_area_size);
371 rom->num_pages = cpu_to_le32(num_pages);
372 rom->ram_header_offset = cpu_to_le32(d->vga.vram_size - ram_header_size);
373
374 d->shadow_rom = *rom;
375 d->rom = rom;
376 d->modes = modes;
377}
378
379static void init_qxl_ram(PCIQXLDevice *d)
380{
381 uint8_t *buf;
382 uint64_t *item;
383
384 buf = d->vga.vram_ptr;
385 d->ram = (QXLRam *)(buf + le32_to_cpu(d->shadow_rom.ram_header_offset));
386 d->ram->magic = cpu_to_le32(QXL_RAM_MAGIC);
387 d->ram->int_pending = cpu_to_le32(0);
388 d->ram->int_mask = cpu_to_le32(0);
9f0f352d 389 d->ram->update_surface = 0;
329f97fc 390 d->ram->monitors_config = 0;
a19cbfb3
GH		 391 SPICE_RING_INIT(&d->ram->cmd_ring);
392 SPICE_RING_INIT(&d->ram->cursor_ring);
393 SPICE_RING_INIT(&d->ram->release_ring);
0b81c478
AL		 394 SPICE_RING_PROD_ITEM(d, &d->ram->release_ring, item);
395 assert(item);
a19cbfb3
GH		 396 *item = 0;
397 qxl_ring_set_dirty(d);
398}
399
400/* can be called from spice server thread context */
b1950430 401static void qxl_set_dirty(MemoryRegion *mr, ram_addr_t addr, ram_addr_t end)
a19cbfb3 402{
fd4aa979 403 memory_region_set_dirty(mr, addr, end - addr);
a19cbfb3
GH		 404}
405
406static void qxl_rom_set_dirty(PCIQXLDevice *qxl)
407{
b1950430 408 qxl_set_dirty(&qxl->rom_bar, 0, qxl->rom_size);
a19cbfb3
GH		 409}
410
411/* called from spice server thread context only */
412static void qxl_ram_set_dirty(PCIQXLDevice *qxl, void *ptr)
413{
a19cbfb3
GH		 414 void *base = qxl->vga.vram_ptr;
415 intptr_t offset;
416
417 offset = ptr - base;
418 offset &= ~(TARGET_PAGE_SIZE-1);
419 assert(offset < qxl->vga.vram_size);
b1950430 420 qxl_set_dirty(&qxl->vga.vram, offset, offset + TARGET_PAGE_SIZE);
a19cbfb3
GH		 421}
422
423/* can be called from spice server thread context */
424static void qxl_ring_set_dirty(PCIQXLDevice *qxl)
425{
b1950430
AK		 426 ram_addr_t addr = qxl->shadow_rom.ram_header_offset;
427 ram_addr_t end = qxl->vga.vram_size;
428 qxl_set_dirty(&qxl->vga.vram, addr, end);
a19cbfb3
GH		 429}
430
431/*
432 * keep track of some command state, for savevm/loadvm.
433 * called from spice server thread context only
434 */
fae2afb1 435static int qxl_track_command(PCIQXLDevice *qxl, struct QXLCommandExt *ext)
a19cbfb3
GH		 436{
437 switch (le32_to_cpu(ext->cmd.type)) {
438 case QXL_CMD_SURFACE:
439 {
440 QXLSurfaceCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id);
fae2afb1
AL		 441
442 if (!cmd) {
443 return 1;
444 }
a19cbfb3 445 uint32_t id = le32_to_cpu(cmd->surface_id);
47eddfbf 446
ddd8fdc7 447 if (id >= qxl->ssd.num_surfaces) {
0a530548 448 qxl_set_guest_bug(qxl, "QXL_CMD_SURFACE id %d >= %d", id,
ddd8fdc7 449 qxl->ssd.num_surfaces);
47eddfbf
AL		 450 return 1;
451 }
48f4ba67
AL		 452 if (cmd->type == QXL_SURFACE_CMD_CREATE &&
453 (cmd->u.surface_create.stride & 0x03) != 0) {
454 qxl_set_guest_bug(qxl, "QXL_CMD_SURFACE stride = %d %% 4 != 0\n",
455 cmd->u.surface_create.stride);
456 return 1;
457 }
14898cf6 458 qemu_mutex_lock(&qxl->track_lock);
a19cbfb3
GH		 459 if (cmd->type == QXL_SURFACE_CMD_CREATE) {
460 qxl->guest_surfaces.cmds[id] = ext->cmd.data;
461 qxl->guest_surfaces.count++;
462 if (qxl->guest_surfaces.max < qxl->guest_surfaces.count)
463 qxl->guest_surfaces.max = qxl->guest_surfaces.count;
464 }
465 if (cmd->type == QXL_SURFACE_CMD_DESTROY) {
466 qxl->guest_surfaces.cmds[id] = 0;
467 qxl->guest_surfaces.count--;
468 }
14898cf6 469 qemu_mutex_unlock(&qxl->track_lock);
a19cbfb3
GH		 470 break;
471 }
472 case QXL_CMD_CURSOR:
473 {
474 QXLCursorCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id);
fae2afb1
AL		 475
476 if (!cmd) {
477 return 1;
478 }
a19cbfb3 479 if (cmd->type == QXL_CURSOR_SET) {
30f6da66 480 qemu_mutex_lock(&qxl->track_lock);
a19cbfb3 481 qxl->guest_cursor = ext->cmd.data;
30f6da66 482 qemu_mutex_unlock(&qxl->track_lock);
a19cbfb3
GH		 483 }
484 break;
485 }
486 }
fae2afb1 487 return 0;
a19cbfb3
GH		 488}
489
490/* spice display interface callbacks */
491
492static void interface_attach_worker(QXLInstance *sin, QXLWorker *qxl_worker)
493{
494 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
495
c480bb7d 496 trace_qxl_interface_attach_worker(qxl->id);
a19cbfb3
GH		 497 qxl->ssd.worker = qxl_worker;
498}
499
500static void interface_set_compression_level(QXLInstance *sin, int level)
501{
502 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
503
c480bb7d 504 trace_qxl_interface_set_compression_level(qxl->id, level);
a19cbfb3
GH		 505 qxl->shadow_rom.compression_level = cpu_to_le32(level);
506 qxl->rom->compression_level = cpu_to_le32(level);
507 qxl_rom_set_dirty(qxl);
508}
509
510static void interface_set_mm_time(QXLInstance *sin, uint32_t mm_time)
511{
512 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
513
c480bb7d 514 trace_qxl_interface_set_mm_time(qxl->id, mm_time);
a19cbfb3
GH		 515 qxl->shadow_rom.mm_clock = cpu_to_le32(mm_time);
516 qxl->rom->mm_clock = cpu_to_le32(mm_time);
517 qxl_rom_set_dirty(qxl);
518}
519
520static void interface_get_init_info(QXLInstance *sin, QXLDevInitInfo *info)
521{
522 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
523
c480bb7d 524 trace_qxl_interface_get_init_info(qxl->id);
a19cbfb3
GH		 525 info->memslot_gen_bits = MEMSLOT_GENERATION_BITS;
526 info->memslot_id_bits = MEMSLOT_SLOT_BITS;
527 info->num_memslots = NUM_MEMSLOTS;
528 info->num_memslots_groups = NUM_MEMSLOTS_GROUPS;
529 info->internal_groupslot_id = 0;
530 info->qxl_ram_size = le32_to_cpu(qxl->shadow_rom.num_pages) << TARGET_PAGE_BITS;
ddd8fdc7 531 info->n_surfaces = qxl->ssd.num_surfaces;
a19cbfb3
GH		 532}
533
5b77870c
AL		 534static const char *qxl_mode_to_string(int mode)
535{
536 switch (mode) {
537 case QXL_MODE_COMPAT:
538 return "compat";
539 case QXL_MODE_NATIVE:
540 return "native";
541 case QXL_MODE_UNDEFINED:
542 return "undefined";
543 case QXL_MODE_VGA:
544 return "vga";
545 }
546 return "INVALID";
547}
548
8b92e298
AL		 549static const char *io_port_to_string(uint32_t io_port)
550{
551 if (io_port >= QXL_IO_RANGE_SIZE) {
552 return "out of range";
553 }
554 static const char *io_port_to_string[QXL_IO_RANGE_SIZE + 1] = {
555 [QXL_IO_NOTIFY_CMD] = "QXL_IO_NOTIFY_CMD",
556 [QXL_IO_NOTIFY_CURSOR] = "QXL_IO_NOTIFY_CURSOR",
557 [QXL_IO_UPDATE_AREA] = "QXL_IO_UPDATE_AREA",
558 [QXL_IO_UPDATE_IRQ] = "QXL_IO_UPDATE_IRQ",
559 [QXL_IO_NOTIFY_OOM] = "QXL_IO_NOTIFY_OOM",
560 [QXL_IO_RESET] = "QXL_IO_RESET",
561 [QXL_IO_SET_MODE] = "QXL_IO_SET_MODE",
562 [QXL_IO_LOG] = "QXL_IO_LOG",
563 [QXL_IO_MEMSLOT_ADD] = "QXL_IO_MEMSLOT_ADD",
564 [QXL_IO_MEMSLOT_DEL] = "QXL_IO_MEMSLOT_DEL",
565 [QXL_IO_DETACH_PRIMARY] = "QXL_IO_DETACH_PRIMARY",
566 [QXL_IO_ATTACH_PRIMARY] = "QXL_IO_ATTACH_PRIMARY",
567 [QXL_IO_CREATE_PRIMARY] = "QXL_IO_CREATE_PRIMARY",
568 [QXL_IO_DESTROY_PRIMARY] = "QXL_IO_DESTROY_PRIMARY",
569 [QXL_IO_DESTROY_SURFACE_WAIT] = "QXL_IO_DESTROY_SURFACE_WAIT",
570 [QXL_IO_DESTROY_ALL_SURFACES] = "QXL_IO_DESTROY_ALL_SURFACES",
8b92e298
AL		 571 [QXL_IO_UPDATE_AREA_ASYNC] = "QXL_IO_UPDATE_AREA_ASYNC",
572 [QXL_IO_MEMSLOT_ADD_ASYNC] = "QXL_IO_MEMSLOT_ADD_ASYNC",
573 [QXL_IO_CREATE_PRIMARY_ASYNC] = "QXL_IO_CREATE_PRIMARY_ASYNC",
574 [QXL_IO_DESTROY_PRIMARY_ASYNC] = "QXL_IO_DESTROY_PRIMARY_ASYNC",
575 [QXL_IO_DESTROY_SURFACE_ASYNC] = "QXL_IO_DESTROY_SURFACE_ASYNC",
576 [QXL_IO_DESTROY_ALL_SURFACES_ASYNC]
577 = "QXL_IO_DESTROY_ALL_SURFACES_ASYNC",
578 [QXL_IO_FLUSH_SURFACES_ASYNC] = "QXL_IO_FLUSH_SURFACES_ASYNC",
579 [QXL_IO_FLUSH_RELEASE] = "QXL_IO_FLUSH_RELEASE",
020af1c4 580 [QXL_IO_MONITORS_CONFIG_ASYNC] = "QXL_IO_MONITORS_CONFIG_ASYNC",
8b92e298
AL		 581 };
582 return io_port_to_string[io_port];
583}
584
a19cbfb3
GH		 585/* called from spice server thread context only */
586static int interface_get_command(QXLInstance *sin, struct QXLCommandExt *ext)
587{
588 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
589 SimpleSpiceUpdate *update;
590 QXLCommandRing *ring;
591 QXLCommand *cmd;
e0c64d08 592 int notify, ret;
a19cbfb3 593
c480bb7d
AL		 594 trace_qxl_ring_command_check(qxl->id, qxl_mode_to_string(qxl->mode));
595
a19cbfb3
GH		 596 switch (qxl->mode) {
597 case QXL_MODE_VGA:
e0c64d08
GH		 598 ret = false;
599 qemu_mutex_lock(&qxl->ssd.lock);
b1af98ba
GH		 600 update = QTAILQ_FIRST(&qxl->ssd.updates);
601 if (update != NULL) {
602 QTAILQ_REMOVE(&qxl->ssd.updates, update, next);
e0c64d08
GH		 603 *ext = update->ext;
604 ret = true;
a19cbfb3 605 }
e0c64d08 606 qemu_mutex_unlock(&qxl->ssd.lock);
212496c9 607 if (ret) {
c480bb7d 608 trace_qxl_ring_command_get(qxl->id, qxl_mode_to_string(qxl->mode));
212496c9
AL		 609 qxl_log_command(qxl, "vga", ext);
610 }
e0c64d08 611 return ret;
a19cbfb3
GH		 612 case QXL_MODE_COMPAT:
613 case QXL_MODE_NATIVE:
614 case QXL_MODE_UNDEFINED:
a19cbfb3 615 ring = &qxl->ram->cmd_ring;
087e6a42 616 if (qxl->guest_bug || SPICE_RING_IS_EMPTY(ring)) {
a19cbfb3
GH		 617 return false;
618 }
0b81c478
AL		 619 SPICE_RING_CONS_ITEM(qxl, ring, cmd);
620 if (!cmd) {
621 return false;
622 }
a19cbfb3
GH		 623 ext->cmd = *cmd;
624 ext->group_id = MEMSLOT_GROUP_GUEST;
625 ext->flags = qxl->cmdflags;
626 SPICE_RING_POP(ring, notify);
627 qxl_ring_set_dirty(qxl);
628 if (notify) {
629 qxl_send_events(qxl, QXL_INTERRUPT_DISPLAY);
630 }
631 qxl->guest_primary.commands++;
632 qxl_track_command(qxl, ext);
633 qxl_log_command(qxl, "cmd", ext);
0b81c478 634 trace_qxl_ring_command_get(qxl->id, qxl_mode_to_string(qxl->mode));
a19cbfb3
GH		 635 return true;
636 default:
637 return false;
638 }
639}
640
641/* called from spice server thread context only */
642static int interface_req_cmd_notification(QXLInstance *sin)
643{
644 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
645 int wait = 1;
646
c480bb7d 647 trace_qxl_ring_command_req_notification(qxl->id);
a19cbfb3
GH		 648 switch (qxl->mode) {
649 case QXL_MODE_COMPAT:
650 case QXL_MODE_NATIVE:
651 case QXL_MODE_UNDEFINED:
652 SPICE_RING_CONS_WAIT(&qxl->ram->cmd_ring, wait);
653 qxl_ring_set_dirty(qxl);
654 break;
655 default:
656 /* nothing */
657 break;
658 }
659 return wait;
660}
661
662/* called from spice server thread context only */
663static inline void qxl_push_free_res(PCIQXLDevice *d, int flush)
664{
665 QXLReleaseRing *ring = &d->ram->release_ring;
666 uint64_t *item;
667 int notify;
668
669#define QXL_FREE_BUNCH_SIZE 32
670
671 if (ring->prod - ring->cons + 1 == ring->num_items) {
672 /* ring full -- can't push */
673 return;
674 }
675 if (!flush && d->oom_running) {
676 /* collect everything from oom handler before pushing */
677 return;
678 }
679 if (!flush && d->num_free_res < QXL_FREE_BUNCH_SIZE) {
680 /* collect a bit more before pushing */
681 return;
682 }
683
684 SPICE_RING_PUSH(ring, notify);
c480bb7d
AL		 685 trace_qxl_ring_res_push(d->id, qxl_mode_to_string(d->mode),
686 d->guest_surfaces.count, d->num_free_res,
687 d->last_release, notify ? "yes" : "no");
688 trace_qxl_ring_res_push_rest(d->id, ring->prod - ring->cons,
689 ring->num_items, ring->prod, ring->cons);
a19cbfb3
GH		 690 if (notify) {
691 qxl_send_events(d, QXL_INTERRUPT_DISPLAY);
692 }
0b81c478
AL		 693 SPICE_RING_PROD_ITEM(d, ring, item);
694 if (!item) {
695 return;
696 }
a19cbfb3
GH		 697 *item = 0;
698 d->num_free_res = 0;
699 d->last_release = NULL;
700 qxl_ring_set_dirty(d);
701}
702
703/* called from spice server thread context only */
704static void interface_release_resource(QXLInstance *sin,
705 struct QXLReleaseInfoExt ext)
706{
707 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
708 QXLReleaseRing *ring;
709 uint64_t *item, id;
710
711 if (ext.group_id == MEMSLOT_GROUP_HOST) {
712 /* host group -> vga mode update request */
f4a8a424 713 qemu_spice_destroy_update(&qxl->ssd, (void *)(intptr_t)ext.info->id);
a19cbfb3
GH		 714 return;
715 }
716
717 /*
718 * ext->info points into guest-visible memory
719 * pci bar 0, $command.release_info
720 */
721 ring = &qxl->ram->release_ring;
0b81c478
AL		 722 SPICE_RING_PROD_ITEM(qxl, ring, item);
723 if (!item) {
724 return;
725 }
a19cbfb3
GH		 726 if (*item == 0) {
727 /* stick head into the ring */
728 id = ext.info->id;
729 ext.info->next = 0;
730 qxl_ram_set_dirty(qxl, &ext.info->next);
731 *item = id;
732 qxl_ring_set_dirty(qxl);
733 } else {
734 /* append item to the list */
735 qxl->last_release->next = ext.info->id;
736 qxl_ram_set_dirty(qxl, &qxl->last_release->next);
737 ext.info->next = 0;
738 qxl_ram_set_dirty(qxl, &ext.info->next);
739 }
740 qxl->last_release = ext.info;
741 qxl->num_free_res++;
c480bb7d 742 trace_qxl_ring_res_put(qxl->id, qxl->num_free_res);
a19cbfb3
GH		 743 qxl_push_free_res(qxl, 0);
744}
745
746/* called from spice server thread context only */
747static int interface_get_cursor_command(QXLInstance *sin, struct QXLCommandExt *ext)
748{
749 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
750 QXLCursorRing *ring;
751 QXLCommand *cmd;
752 int notify;
753
c480bb7d
AL		 754 trace_qxl_ring_cursor_check(qxl->id, qxl_mode_to_string(qxl->mode));
755
a19cbfb3
GH		 756 switch (qxl->mode) {
757 case QXL_MODE_COMPAT:
758 case QXL_MODE_NATIVE:
759 case QXL_MODE_UNDEFINED:
760 ring = &qxl->ram->cursor_ring;
761 if (SPICE_RING_IS_EMPTY(ring)) {
762 return false;
763 }
0b81c478
AL		 764 SPICE_RING_CONS_ITEM(qxl, ring, cmd);
765 if (!cmd) {
766 return false;
767 }
a19cbfb3
GH		 768 ext->cmd = *cmd;
769 ext->group_id = MEMSLOT_GROUP_GUEST;
770 ext->flags = qxl->cmdflags;
771 SPICE_RING_POP(ring, notify);
772 qxl_ring_set_dirty(qxl);
773 if (notify) {
774 qxl_send_events(qxl, QXL_INTERRUPT_CURSOR);
775 }
776 qxl->guest_primary.commands++;
777 qxl_track_command(qxl, ext);
778 qxl_log_command(qxl, "csr", ext);
779 if (qxl->id == 0) {
780 qxl_render_cursor(qxl, ext);
781 }
c480bb7d 782 trace_qxl_ring_cursor_get(qxl->id, qxl_mode_to_string(qxl->mode));
a19cbfb3
GH		 783 return true;
784 default:
785 return false;
786 }
787}
788
789/* called from spice server thread context only */
790static int interface_req_cursor_notification(QXLInstance *sin)
791{
792 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
793 int wait = 1;
794
c480bb7d 795 trace_qxl_ring_cursor_req_notification(qxl->id);
a19cbfb3
GH		 796 switch (qxl->mode) {
797 case QXL_MODE_COMPAT:
798 case QXL_MODE_NATIVE:
799 case QXL_MODE_UNDEFINED:
800 SPICE_RING_CONS_WAIT(&qxl->ram->cursor_ring, wait);
801 qxl_ring_set_dirty(qxl);
802 break;
803 default:
804 /* nothing */
805 break;
806 }
807 return wait;
808}
809
810/* called from spice server thread context */
811static void interface_notify_update(QXLInstance *sin, uint32_t update_id)
812{
baeae407
AL		 813 /*
814 * Called by spice-server as a result of a QXL_CMD_UPDATE which is not in
815 * use by xf86-video-qxl and is defined out in the qxl windows driver.
816 * Probably was at some earlier version that is prior to git start (2009),
817 * and is still guest trigerrable.
818 */
819 fprintf(stderr, "%s: deprecated\n", __func__);
a19cbfb3
GH		 820}
821
822/* called from spice server thread context only */
823static int interface_flush_resources(QXLInstance *sin)
824{
825 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
826 int ret;
827
a19cbfb3
GH		 828 ret = qxl->num_free_res;
829 if (ret) {
830 qxl_push_free_res(qxl, 1);
831 }
832 return ret;
833}
834
5ff4e36c
AL		 835static void qxl_create_guest_primary_complete(PCIQXLDevice *d);
836
5ff4e36c 837/* called from spice server thread context only */
2e1a98c9 838static void interface_async_complete_io(PCIQXLDevice *qxl, QXLCookie *cookie)
5ff4e36c 839{
5ff4e36c
AL		 840 uint32_t current_async;
841
842 qemu_mutex_lock(&qxl->async_lock);
843 current_async = qxl->current_async;
844 qxl->current_async = QXL_UNDEFINED_IO;
845 qemu_mutex_unlock(&qxl->async_lock);
846
c480bb7d 847 trace_qxl_interface_async_complete_io(qxl->id, current_async, cookie);
2e1a98c9
AL		 848 if (!cookie) {
849 fprintf(stderr, "qxl: %s: error, cookie is NULL\n", __func__);
850 return;
851 }
852 if (cookie && current_async != cookie->io) {
853 fprintf(stderr,
2fce7edf
AL		 854 "qxl: %s: error: current_async = %d != %"
855 PRId64 " = cookie->io\n", __func__, current_async, cookie->io);
2e1a98c9 856 }
5ff4e36c 857 switch (current_async) {
81fb6f15
AL		 858 case QXL_IO_MEMSLOT_ADD_ASYNC:
859 case QXL_IO_DESTROY_PRIMARY_ASYNC:
860 case QXL_IO_UPDATE_AREA_ASYNC:
861 case QXL_IO_FLUSH_SURFACES_ASYNC:
020af1c4 862 case QXL_IO_MONITORS_CONFIG_ASYNC:
81fb6f15 863 break;
5ff4e36c
AL		 864 case QXL_IO_CREATE_PRIMARY_ASYNC:
865 qxl_create_guest_primary_complete(qxl);
866 break;
867 case QXL_IO_DESTROY_ALL_SURFACES_ASYNC:
868 qxl_spice_destroy_surfaces_complete(qxl);
869 break;
870 case QXL_IO_DESTROY_SURFACE_ASYNC:
2e1a98c9 871 qxl_spice_destroy_surface_wait_complete(qxl, cookie->u.surface_id);
5ff4e36c 872 break;
81fb6f15
AL		 873 default:
874 fprintf(stderr, "qxl: %s: unexpected current_async %d\n", __func__,
875 current_async);
5ff4e36c
AL		 876 }
877 qxl_send_events(qxl, QXL_INTERRUPT_IO_CMD);
878}
879
81fb6f15
AL		 880/* called from spice server thread context only */
881static void interface_update_area_complete(QXLInstance *sin,
882 uint32_t surface_id,
883 QXLRect *dirty, uint32_t num_updated_rects)
884{
885 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
886 int i;
887 int qxl_i;
888
889 qemu_mutex_lock(&qxl->ssd.lock);
890 if (surface_id != 0 || !qxl->render_update_cookie_num) {
891 qemu_mutex_unlock(&qxl->ssd.lock);
892 return;
893 }
c480bb7d
AL		 894 trace_qxl_interface_update_area_complete(qxl->id, surface_id, dirty->left,
895 dirty->right, dirty->top, dirty->bottom);
896 trace_qxl_interface_update_area_complete_rest(qxl->id, num_updated_rects);
81fb6f15
AL		 897 if (qxl->num_dirty_rects + num_updated_rects > QXL_NUM_DIRTY_RECTS) {
898 /*
899 * overflow - treat this as a full update. Not expected to be common.
900 */
c480bb7d
AL		 901 trace_qxl_interface_update_area_complete_overflow(qxl->id,
902 QXL_NUM_DIRTY_RECTS);
81fb6f15
AL		 903 qxl->guest_primary.resized = 1;
904 }
905 if (qxl->guest_primary.resized) {
906 /*
907 * Don't bother copying or scheduling the bh since we will flip
908 * the whole area anyway on completion of the update_area async call
909 */
910 qemu_mutex_unlock(&qxl->ssd.lock);
911 return;
912 }
913 qxl_i = qxl->num_dirty_rects;
914 for (i = 0; i < num_updated_rects; i++) {
915 qxl->dirty[qxl_i++] = dirty[i];
916 }
917 qxl->num_dirty_rects += num_updated_rects;
c480bb7d
AL		 918 trace_qxl_interface_update_area_complete_schedule_bh(qxl->id,
919 qxl->num_dirty_rects);
81fb6f15
AL		 920 qemu_bh_schedule(qxl->update_area_bh);
921 qemu_mutex_unlock(&qxl->ssd.lock);
922}
923
2e1a98c9
AL		 924/* called from spice server thread context only */
925static void interface_async_complete(QXLInstance *sin, uint64_t cookie_token)
926{
927 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
5dba0d45 928 QXLCookie *cookie = (QXLCookie *)(uintptr_t)cookie_token;
2e1a98c9
AL		 929
930 switch (cookie->type) {
931 case QXL_COOKIE_TYPE_IO:
932 interface_async_complete_io(qxl, cookie);
81fb6f15
AL		 933 g_free(cookie);
934 break;
935 case QXL_COOKIE_TYPE_RENDER_UPDATE_AREA:
936 qxl_render_update_area_done(qxl, cookie);
2e1a98c9 937 break;
020af1c4
AL		 938 case QXL_COOKIE_TYPE_POST_LOAD_MONITORS_CONFIG:
939 break;
2e1a98c9
AL		 940 default:
941 fprintf(stderr, "qxl: %s: unexpected cookie type %d\n",
942 __func__, cookie->type);
81fb6f15 943 g_free(cookie);
2e1a98c9 944 }
2e1a98c9
AL		 945}
946
c10018d6
SSP		 947/* called from spice server thread context only */
948static void interface_set_client_capabilities(QXLInstance *sin,
949 uint8_t client_present,
950 uint8_t caps[58])
951{
952 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
953
e0ac6097
AL		 954 if (qxl->revision < 4) {
955 trace_qxl_set_client_capabilities_unsupported_by_revision(qxl->id,
956 qxl->revision);
957 return;
958 }
959
ab902981
HG		 960 if (runstate_check(RUN_STATE_INMIGRATE) ||
961 runstate_check(RUN_STATE_POSTMIGRATE)) {
962 return;
963 }
964
c10018d6 965 qxl->shadow_rom.client_present = client_present;
08688af0
MA		 966 memcpy(qxl->shadow_rom.client_capabilities, caps,
967 sizeof(qxl->shadow_rom.client_capabilities));
c10018d6 968 qxl->rom->client_present = client_present;
08688af0
MA		 969 memcpy(qxl->rom->client_capabilities, caps,
970 sizeof(qxl->rom->client_capabilities));
c10018d6
SSP		 971 qxl_rom_set_dirty(qxl);
972
973 qxl_send_events(qxl, QXL_INTERRUPT_CLIENT);
974}
975
a639ab04
AL		 976static uint32_t qxl_crc32(const uint8_t *p, unsigned len)
977{
978 /*
979 * zlib xors the seed with 0xffffffff, and xors the result
980 * again with 0xffffffff; Both are not done with linux's crc32,
981 * which we want to be compatible with, so undo that.
982 */
983 return crc32(0xffffffff, p, len) ^ 0xffffffff;
984}
985
986/* called from main context only */
987static int interface_client_monitors_config(QXLInstance *sin,
988 VDAgentMonitorsConfig *monitors_config)
989{
990 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
991 QXLRom *rom = memory_region_get_ram_ptr(&qxl->rom_bar);
992 int i;
993
e0ac6097
AL		 994 if (qxl->revision < 4) {
995 trace_qxl_client_monitors_config_unsupported_by_device(qxl->id,
996 qxl->revision);
997 return 0;
998 }
a639ab04
AL		 999 /*
1000 * Older windows drivers set int_mask to 0 when their ISR is called,
1001 * then later set it to ~0. So it doesn't relate to the actual interrupts
1002 * handled. However, they are old, so clearly they don't support this
1003 * interrupt
1004 */
1005 if (qxl->ram->int_mask == 0 || qxl->ram->int_mask == ~0 ||
1006 !(qxl->ram->int_mask & QXL_INTERRUPT_CLIENT_MONITORS_CONFIG)) {
1007 trace_qxl_client_monitors_config_unsupported_by_guest(qxl->id,
1008 qxl->ram->int_mask,
1009 monitors_config);
1010 return 0;
1011 }
1012 if (!monitors_config) {
1013 return 1;
1014 }
1015 memset(&rom->client_monitors_config, 0,
1016 sizeof(rom->client_monitors_config));
1017 rom->client_monitors_config.count = monitors_config->num_of_monitors;
1018 /* monitors_config->flags ignored */
1019 if (rom->client_monitors_config.count >=
1020 ARRAY_SIZE(rom->client_monitors_config.heads)) {
1021 trace_qxl_client_monitors_config_capped(qxl->id,
1022 monitors_config->num_of_monitors,
1023 ARRAY_SIZE(rom->client_monitors_config.heads));
1024 rom->client_monitors_config.count =
1025 ARRAY_SIZE(rom->client_monitors_config.heads);
1026 }
1027 for (i = 0 ; i < rom->client_monitors_config.count ; ++i) {
1028 VDAgentMonConfig *monitor = &monitors_config->monitors[i];
1029 QXLURect *rect = &rom->client_monitors_config.heads[i];
1030 /* monitor->depth ignored */
1031 rect->left = monitor->x;
1032 rect->top = monitor->y;
1033 rect->right = monitor->x + monitor->width;
1034 rect->bottom = monitor->y + monitor->height;
1035 }
1036 rom->client_monitors_config_crc = qxl_crc32(
1037 (const uint8_t *)&rom->client_monitors_config,
1038 sizeof(rom->client_monitors_config));
1039 trace_qxl_client_monitors_config_crc(qxl->id,
1040 sizeof(rom->client_monitors_config),
1041 rom->client_monitors_config_crc);
1042
1043 trace_qxl_interrupt_client_monitors_config(qxl->id,
1044 rom->client_monitors_config.count,
1045 rom->client_monitors_config.heads);
1046 qxl_send_events(qxl, QXL_INTERRUPT_CLIENT_MONITORS_CONFIG);
1047 return 1;
1048}
a639ab04 1049
a19cbfb3
GH		 1050static const QXLInterface qxl_interface = {
1051 .base.type = SPICE_INTERFACE_QXL,
1052 .base.description = "qxl gpu",
1053 .base.major_version = SPICE_INTERFACE_QXL_MAJOR,
1054 .base.minor_version = SPICE_INTERFACE_QXL_MINOR,
1055
1056 .attache_worker = interface_attach_worker,
1057 .set_compression_level = interface_set_compression_level,
1058 .set_mm_time = interface_set_mm_time,
1059 .get_init_info = interface_get_init_info,
1060
1061 /* the callbacks below are called from spice server thread context */
1062 .get_command = interface_get_command,
1063 .req_cmd_notification = interface_req_cmd_notification,
1064 .release_resource = interface_release_resource,
1065 .get_cursor_command = interface_get_cursor_command,
1066 .req_cursor_notification = interface_req_cursor_notification,
1067 .notify_update = interface_notify_update,
1068 .flush_resources = interface_flush_resources,
5ff4e36c 1069 .async_complete = interface_async_complete,
81fb6f15 1070 .update_area_complete = interface_update_area_complete,
c10018d6 1071 .set_client_capabilities = interface_set_client_capabilities,
a639ab04 1072 .client_monitors_config = interface_client_monitors_config,
a19cbfb3
GH		 1073};
1074
1075static void qxl_enter_vga_mode(PCIQXLDevice *d)
1076{
1077 if (d->mode == QXL_MODE_VGA) {
1078 return;
1079 }
c480bb7d 1080 trace_qxl_enter_vga_mode(d->id);
0a2b5e3a
HG		 1081#if SPICE_SERVER_VERSION >= 0x000c03 /* release 0.12.3 */
1082 spice_qxl_driver_unload(&d->ssd.qxl);
1083#endif
a19cbfb3
GH		 1084 qemu_spice_create_host_primary(&d->ssd);
1085 d->mode = QXL_MODE_VGA;
0f7bfd81 1086 vga_dirty_log_start(&d->vga);
1dbfa005 1087 graphic_hw_update(d->vga.con);
a19cbfb3
GH		 1088}
1089
1090static void qxl_exit_vga_mode(PCIQXLDevice *d)
1091{
1092 if (d->mode != QXL_MODE_VGA) {
1093 return;
1094 }
c480bb7d 1095 trace_qxl_exit_vga_mode(d->id);
0f7bfd81 1096 vga_dirty_log_stop(&d->vga);
5ff4e36c 1097 qxl_destroy_primary(d, QXL_SYNC);
a19cbfb3
GH		 1098}
1099
40010aea 1100static void qxl_update_irq(PCIQXLDevice *d)
a19cbfb3
GH		 1101{
1102 uint32_t pending = le32_to_cpu(d->ram->int_pending);
1103 uint32_t mask = le32_to_cpu(d->ram->int_mask);
1104 int level = !!(pending & mask);
1105 qemu_set_irq(d->pci.irq[0], level);
1106 qxl_ring_set_dirty(d);
1107}
1108
a19cbfb3
GH		 1109static void qxl_check_state(PCIQXLDevice *d)
1110{
1111 QXLRam *ram = d->ram;
71d388d4 1112 int spice_display_running = qemu_spice_display_is_running(&d->ssd);
a19cbfb3 1113
71d388d4
YH		 1114 assert(!spice_display_running || SPICE_RING_IS_EMPTY(&ram->cmd_ring));
1115 assert(!spice_display_running || SPICE_RING_IS_EMPTY(&ram->cursor_ring));
a19cbfb3
GH		 1116}
1117
1118static void qxl_reset_state(PCIQXLDevice *d)
1119{
a19cbfb3
GH		 1120 QXLRom *rom = d->rom;
1121
be48e995 1122 qxl_check_state(d);
a19cbfb3
GH		 1123 d->shadow_rom.update_id = cpu_to_le32(0);
1124 *rom = d->shadow_rom;
1125 qxl_rom_set_dirty(d);
1126 init_qxl_ram(d);
1127 d->num_free_res = 0;
1128 d->last_release = NULL;
1129 memset(&d->ssd.dirty, 0, sizeof(d->ssd.dirty));
1130}
1131
1132static void qxl_soft_reset(PCIQXLDevice *d)
1133{
c480bb7d 1134 trace_qxl_soft_reset(d->id);
a19cbfb3 1135 qxl_check_state(d);
087e6a42 1136 qxl_clear_guest_bug(d);
a5f68c22 1137 d->current_async = QXL_UNDEFINED_IO;
a19cbfb3
GH		 1138
1139 if (d->id == 0) {
1140 qxl_enter_vga_mode(d);
1141 } else {
1142 d->mode = QXL_MODE_UNDEFINED;
1143 }
1144}
1145
1146static void qxl_hard_reset(PCIQXLDevice *d, int loadvm)
1147{
c480bb7d 1148 trace_qxl_hard_reset(d->id, loadvm);
a19cbfb3 1149
aee32bf3
GH		 1150 qxl_spice_reset_cursor(d);
1151 qxl_spice_reset_image_cache(d);
a19cbfb3
GH		 1152 qxl_reset_surfaces(d);
1153 qxl_reset_memslots(d);
1154
1155 /* pre loadvm reset must not touch QXLRam. This lives in
1156 * device memory, is migrated together with RAM and thus
1157 * already loaded at this point */
1158 if (!loadvm) {
1159 qxl_reset_state(d);
1160 }
1161 qemu_spice_create_host_memslot(&d->ssd);
1162 qxl_soft_reset(d);
a19cbfb3
GH		 1163}
1164
1165static void qxl_reset_handler(DeviceState *dev)
1166{
1167 PCIQXLDevice *d = DO_UPCAST(PCIQXLDevice, pci.qdev, dev);
c480bb7d 1168
a19cbfb3
GH		 1169 qxl_hard_reset(d, 0);
1170}
1171
1172static void qxl_vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
1173{
1174 VGACommonState *vga = opaque;
1175 PCIQXLDevice *qxl = container_of(vga, PCIQXLDevice, vga);
1176
c480bb7d 1177 trace_qxl_io_write_vga(qxl->id, qxl_mode_to_string(qxl->mode), addr, val);
a19cbfb3 1178 if (qxl->mode != QXL_MODE_VGA) {
5ff4e36c 1179 qxl_destroy_primary(qxl, QXL_SYNC);
a19cbfb3
GH		 1180 qxl_soft_reset(qxl);
1181 }
1182 vga_ioport_write(opaque, addr, val);
1183}
1184
f67ab77a
GH		 1185static const MemoryRegionPortio qxl_vga_portio_list[] = {
1186 { 0x04, 2, 1, .read = vga_ioport_read,
1187 .write = qxl_vga_ioport_write }, /* 3b4 */
1188 { 0x0a, 1, 1, .read = vga_ioport_read,
1189 .write = qxl_vga_ioport_write }, /* 3ba */
1190 { 0x10, 16, 1, .read = vga_ioport_read,
1191 .write = qxl_vga_ioport_write }, /* 3c0 */
1192 { 0x24, 2, 1, .read = vga_ioport_read,
1193 .write = qxl_vga_ioport_write }, /* 3d4 */
1194 { 0x2a, 1, 1, .read = vga_ioport_read,
1195 .write = qxl_vga_ioport_write }, /* 3da */
1196 PORTIO_END_OF_LIST(),
1197};
1198
e954ea28
AL		 1199static int qxl_add_memslot(PCIQXLDevice *d, uint32_t slot_id, uint64_t delta,
1200 qxl_async_io async)
a19cbfb3
GH		 1201{
1202 static const int regions[] = {
1203 QXL_RAM_RANGE_INDEX,
1204 QXL_VRAM_RANGE_INDEX,
6f2b175a 1205 QXL_VRAM64_RANGE_INDEX,
a19cbfb3
GH		 1206 };
1207 uint64_t guest_start;
1208 uint64_t guest_end;
1209 int pci_region;
1210 pcibus_t pci_start;
1211 pcibus_t pci_end;
1212 intptr_t virt_start;
1213 QXLDevMemSlot memslot;
1214 int i;
1215
1216 guest_start = le64_to_cpu(d->guest_slots[slot_id].slot.mem_start);
1217 guest_end = le64_to_cpu(d->guest_slots[slot_id].slot.mem_end);
1218
c480bb7d 1219 trace_qxl_memslot_add_guest(d->id, slot_id, guest_start, guest_end);
a19cbfb3 1220
e954ea28 1221 if (slot_id >= NUM_MEMSLOTS) {
0a530548 1222 qxl_set_guest_bug(d, "%s: slot_id >= NUM_MEMSLOTS %d >= %d", __func__,
e954ea28
AL		 1223 slot_id, NUM_MEMSLOTS);
1224 return 1;
1225 }
1226 if (guest_start > guest_end) {
0a530548 1227 qxl_set_guest_bug(d, "%s: guest_start > guest_end 0x%" PRIx64
e954ea28
AL		 1228 " > 0x%" PRIx64, __func__, guest_start, guest_end);
1229 return 1;
1230 }
a19cbfb3
GH		 1231
1232 for (i = 0; i < ARRAY_SIZE(regions); i++) {
1233 pci_region = regions[i];
1234 pci_start = d->pci.io_regions[pci_region].addr;
1235 pci_end = pci_start + d->pci.io_regions[pci_region].size;
1236 /* mapped? */
1237 if (pci_start == -1) {
1238 continue;
1239 }
1240 /* start address in range ? */
1241 if (guest_start < pci_start || guest_start > pci_end) {
1242 continue;
1243 }
1244 /* end address in range ? */
1245 if (guest_end > pci_end) {
1246 continue;
1247 }
1248 /* passed */
1249 break;
1250 }
e954ea28 1251 if (i == ARRAY_SIZE(regions)) {
0a530548 1252 qxl_set_guest_bug(d, "%s: finished loop without match", __func__);
e954ea28
AL		 1253 return 1;
1254 }
a19cbfb3
GH		 1255
1256 switch (pci_region) {
1257 case QXL_RAM_RANGE_INDEX:
b1950430 1258 virt_start = (intptr_t)memory_region_get_ram_ptr(&d->vga.vram);
a19cbfb3
GH		 1259 break;
1260 case QXL_VRAM_RANGE_INDEX:
6f2b175a 1261 case 4 /* vram 64bit */:
b1950430 1262 virt_start = (intptr_t)memory_region_get_ram_ptr(&d->vram_bar);
a19cbfb3
GH		 1263 break;
1264 default:
1265 /* should not happen */
0a530548 1266 qxl_set_guest_bug(d, "%s: pci_region = %d", __func__, pci_region);
e954ea28 1267 return 1;
a19cbfb3
GH		 1268 }
1269
1270 memslot.slot_id = slot_id;
1271 memslot.slot_group_id = MEMSLOT_GROUP_GUEST; /* guest group */
1272 memslot.virt_start = virt_start + (guest_start - pci_start);
1273 memslot.virt_end = virt_start + (guest_end - pci_start);
1274 memslot.addr_delta = memslot.virt_start - delta;
1275 memslot.generation = d->rom->slot_generation = 0;
1276 qxl_rom_set_dirty(d);
1277
5ff4e36c 1278 qemu_spice_add_memslot(&d->ssd, &memslot, async);
a19cbfb3
GH		 1279 d->guest_slots[slot_id].ptr = (void*)memslot.virt_start;
1280 d->guest_slots[slot_id].size = memslot.virt_end - memslot.virt_start;
1281 d->guest_slots[slot_id].delta = delta;
1282 d->guest_slots[slot_id].active = 1;
e954ea28 1283 return 0;
a19cbfb3
GH		 1284}
1285
1286static void qxl_del_memslot(PCIQXLDevice *d, uint32_t slot_id)
1287{
5c59d118 1288 qemu_spice_del_memslot(&d->ssd, MEMSLOT_GROUP_HOST, slot_id);
a19cbfb3
GH		 1289 d->guest_slots[slot_id].active = 0;
1290}
1291
1292static void qxl_reset_memslots(PCIQXLDevice *d)
1293{
aee32bf3 1294 qxl_spice_reset_memslots(d);
a19cbfb3
GH		 1295 memset(&d->guest_slots, 0, sizeof(d->guest_slots));
1296}
1297
1298static void qxl_reset_surfaces(PCIQXLDevice *d)
1299{
c480bb7d 1300 trace_qxl_reset_surfaces(d->id);
a19cbfb3 1301 d->mode = QXL_MODE_UNDEFINED;
5ff4e36c 1302 qxl_spice_destroy_surfaces(d, QXL_SYNC);
a19cbfb3
GH		 1303}
1304
e25139b3 1305/* can be also called from spice server thread context */
a19cbfb3
GH		 1306void *qxl_phys2virt(PCIQXLDevice *qxl, QXLPHYSICAL pqxl, int group_id)
1307{
1308 uint64_t phys = le64_to_cpu(pqxl);
1309 uint32_t slot = (phys >> (64 - 8)) & 0xff;
1310 uint64_t offset = phys & 0xffffffffffff;
1311
1312 switch (group_id) {
1313 case MEMSLOT_GROUP_HOST:
f4a8a424 1314 return (void *)(intptr_t)offset;
a19cbfb3 1315 case MEMSLOT_GROUP_GUEST:
4b635c59 1316 if (slot >= NUM_MEMSLOTS) {
0a530548
AL		 1317 qxl_set_guest_bug(qxl, "slot too large %d >= %d", slot,
1318 NUM_MEMSLOTS);
4b635c59
AL		 1319 return NULL;
1320 }
1321 if (!qxl->guest_slots[slot].active) {
0a530548 1322 qxl_set_guest_bug(qxl, "inactive slot %d\n", slot);
4b635c59
AL		 1323 return NULL;
1324 }
1325 if (offset < qxl->guest_slots[slot].delta) {
0a530548
AL		 1326 qxl_set_guest_bug(qxl,
1327 "slot %d offset %"PRIu64" < delta %"PRIu64"\n",
4b635c59
AL		 1328 slot, offset, qxl->guest_slots[slot].delta);
1329 return NULL;
1330 }
a19cbfb3 1331 offset -= qxl->guest_slots[slot].delta;
4b635c59 1332 if (offset > qxl->guest_slots[slot].size) {
0a530548
AL		 1333 qxl_set_guest_bug(qxl,
1334 "slot %d offset %"PRIu64" > size %"PRIu64"\n",
4b635c59
AL		 1335 slot, offset, qxl->guest_slots[slot].size);
1336 return NULL;
1337 }
a19cbfb3 1338 return qxl->guest_slots[slot].ptr + offset;
a19cbfb3 1339 }
4b635c59 1340 return NULL;
a19cbfb3
GH		 1341}
1342
5ff4e36c
AL		 1343static void qxl_create_guest_primary_complete(PCIQXLDevice *qxl)
1344{
1345 /* for local rendering */
1346 qxl_render_resize(qxl);
1347}
1348
1349static void qxl_create_guest_primary(PCIQXLDevice *qxl, int loadvm,
1350 qxl_async_io async)
a19cbfb3
GH		 1351{
1352 QXLDevSurfaceCreate surface;
1353 QXLSurfaceCreate *sc = &qxl->guest_primary.surface;
13d1fd44
AL		 1354 int size;
1355 int requested_height = le32_to_cpu(sc->height);
1356 int requested_stride = le32_to_cpu(sc->stride);
1357
1358 size = abs(requested_stride) * requested_height;
1359 if (size > qxl->vgamem_size) {
1360 qxl_set_guest_bug(qxl, "%s: requested primary larger then framebuffer"
1361 " size", __func__);
1362 return;
1363 }
a19cbfb3 1364
ddf9f4b7 1365 if (qxl->mode == QXL_MODE_NATIVE) {
0a530548 1366 qxl_set_guest_bug(qxl, "%s: nop since already in QXL_MODE_NATIVE",
ddf9f4b7
AL		 1367 __func__);
1368 }
a19cbfb3
GH		 1369 qxl_exit_vga_mode(qxl);
1370
a19cbfb3
GH		 1371 surface.format = le32_to_cpu(sc->format);
1372 surface.height = le32_to_cpu(sc->height);
1373 surface.mem = le64_to_cpu(sc->mem);
1374 surface.position = le32_to_cpu(sc->position);
1375 surface.stride = le32_to_cpu(sc->stride);
1376 surface.width = le32_to_cpu(sc->width);
1377 surface.type = le32_to_cpu(sc->type);
1378 surface.flags = le32_to_cpu(sc->flags);
c480bb7d
AL		 1379 trace_qxl_create_guest_primary(qxl->id, sc->width, sc->height, sc->mem,
1380 sc->format, sc->position);
1381 trace_qxl_create_guest_primary_rest(qxl->id, sc->stride, sc->type,
1382 sc->flags);
a19cbfb3 1383
48f4ba67
AL		 1384 if ((surface.stride & 0x3) != 0) {
1385 qxl_set_guest_bug(qxl, "primary surface stride = %d %% 4 != 0",
1386 surface.stride);
1387 return;
1388 }
1389
a19cbfb3
GH		 1390 surface.mouse_mode = true;
1391 surface.group_id = MEMSLOT_GROUP_GUEST;
1392 if (loadvm) {
1393 surface.flags |= QXL_SURF_FLAG_KEEP_DATA;
1394 }
1395
1396 qxl->mode = QXL_MODE_NATIVE;
1397 qxl->cmdflags = 0;
5ff4e36c 1398 qemu_spice_create_primary_surface(&qxl->ssd, 0, &surface, async);
a19cbfb3 1399
5ff4e36c
AL		 1400 if (async == QXL_SYNC) {
1401 qxl_create_guest_primary_complete(qxl);
1402 }
a19cbfb3
GH		 1403}
1404
5ff4e36c
AL		 1405/* return 1 if surface destoy was initiated (in QXL_ASYNC case) or
1406 * done (in QXL_SYNC case), 0 otherwise. */
1407static int qxl_destroy_primary(PCIQXLDevice *d, qxl_async_io async)
a19cbfb3
GH		 1408{
1409 if (d->mode == QXL_MODE_UNDEFINED) {
5ff4e36c 1410 return 0;
a19cbfb3 1411 }
c480bb7d 1412 trace_qxl_destroy_primary(d->id);
a19cbfb3 1413 d->mode = QXL_MODE_UNDEFINED;
5ff4e36c 1414 qemu_spice_destroy_primary_surface(&d->ssd, 0, async);
30f6da66 1415 qxl_spice_reset_cursor(d);
5ff4e36c 1416 return 1;
a19cbfb3
GH		 1417}
1418
1419static void qxl_set_mode(PCIQXLDevice *d, int modenr, int loadvm)
1420{
1421 pcibus_t start = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr;
1422 pcibus_t end = d->pci.io_regions[QXL_RAM_RANGE_INDEX].size + start;
1423 QXLMode *mode = d->modes->modes + modenr;
1424 uint64_t devmem = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr;
1425 QXLMemSlot slot = {
1426 .mem_start = start,
1427 .mem_end = end
1428 };
1429 QXLSurfaceCreate surface = {
1430 .width = mode->x_res,
1431 .height = mode->y_res,
1432 .stride = -mode->x_res * 4,
1433 .format = SPICE_SURFACE_FMT_32_xRGB,
1434 .flags = loadvm ? QXL_SURF_FLAG_KEEP_DATA : 0,
1435 .mouse_mode = true,
1436 .mem = devmem + d->shadow_rom.draw_area_offset,
1437 };
1438
c480bb7d
AL		 1439 trace_qxl_set_mode(d->id, modenr, mode->x_res, mode->y_res, mode->bits,
1440 devmem);
a19cbfb3
GH		 1441 if (!loadvm) {
1442 qxl_hard_reset(d, 0);
1443 }
1444
1445 d->guest_slots[0].slot = slot;
e954ea28 1446 assert(qxl_add_memslot(d, 0, devmem, QXL_SYNC) == 0);
a19cbfb3
GH		 1447
1448 d->guest_primary.surface = surface;
5ff4e36c 1449 qxl_create_guest_primary(d, 0, QXL_SYNC);
a19cbfb3
GH		 1450
1451 d->mode = QXL_MODE_COMPAT;
1452 d->cmdflags = QXL_COMMAND_FLAG_COMPAT;
a19cbfb3
GH		 1453 if (mode->bits == 16) {
1454 d->cmdflags |= QXL_COMMAND_FLAG_COMPAT_16BPP;
1455 }
a19cbfb3
GH		 1456 d->shadow_rom.mode = cpu_to_le32(modenr);
1457 d->rom->mode = cpu_to_le32(modenr);
1458 qxl_rom_set_dirty(d);
1459}
1460
a8170e5e 1461static void ioport_write(void *opaque, hwaddr addr,
b1950430 1462 uint64_t val, unsigned size)
a19cbfb3
GH		 1463{
1464 PCIQXLDevice *d = opaque;
b1950430 1465 uint32_t io_port = addr;
5ff4e36c 1466 qxl_async_io async = QXL_SYNC;
5ff4e36c 1467 uint32_t orig_io_port = io_port;
a19cbfb3 1468
d96aafca 1469 if (d->guest_bug && io_port != QXL_IO_RESET) {
087e6a42
AL		 1470 return;
1471 }
1472
020af1c4 1473 if (d->revision <= QXL_REVISION_STABLE_V10 &&
ffe01e59 1474 io_port > QXL_IO_FLUSH_RELEASE) {
020af1c4
AL		 1475 qxl_set_guest_bug(d, "unsupported io %d for revision %d\n",
1476 io_port, d->revision);
1477 return;
1478 }
1479
a19cbfb3
GH		 1480 switch (io_port) {
1481 case QXL_IO_RESET:
1482 case QXL_IO_SET_MODE:
1483 case QXL_IO_MEMSLOT_ADD:
1484 case QXL_IO_MEMSLOT_DEL:
1485 case QXL_IO_CREATE_PRIMARY:
81144d1a 1486 case QXL_IO_UPDATE_IRQ:
a3d14054 1487 case QXL_IO_LOG:
5ff4e36c
AL		 1488 case QXL_IO_MEMSLOT_ADD_ASYNC:
1489 case QXL_IO_CREATE_PRIMARY_ASYNC:
a19cbfb3
GH		 1490 break;
1491 default:
e21a298a 1492 if (d->mode != QXL_MODE_VGA) {
a19cbfb3 1493 break;
e21a298a 1494 }
c480bb7d 1495 trace_qxl_io_unexpected_vga_mode(d->id,
917ae08c 1496 addr, val, io_port_to_string(io_port));
5ff4e36c
AL		 1497 /* be nice to buggy guest drivers */
1498 if (io_port >= QXL_IO_UPDATE_AREA_ASYNC &&
020af1c4 1499 io_port < QXL_IO_RANGE_SIZE) {
5ff4e36c
AL		 1500 qxl_send_events(d, QXL_INTERRUPT_IO_CMD);
1501 }
a19cbfb3
GH		 1502 return;
1503 }
1504
5ff4e36c
AL		 1505 /* we change the io_port to avoid ifdeffery in the main switch */
1506 orig_io_port = io_port;
1507 switch (io_port) {
1508 case QXL_IO_UPDATE_AREA_ASYNC:
1509 io_port = QXL_IO_UPDATE_AREA;
1510 goto async_common;
1511 case QXL_IO_MEMSLOT_ADD_ASYNC:
1512 io_port = QXL_IO_MEMSLOT_ADD;
1513 goto async_common;
1514 case QXL_IO_CREATE_PRIMARY_ASYNC:
1515 io_port = QXL_IO_CREATE_PRIMARY;
1516 goto async_common;
1517 case QXL_IO_DESTROY_PRIMARY_ASYNC:
1518 io_port = QXL_IO_DESTROY_PRIMARY;
1519 goto async_common;
1520 case QXL_IO_DESTROY_SURFACE_ASYNC:
1521 io_port = QXL_IO_DESTROY_SURFACE_WAIT;
1522 goto async_common;
1523 case QXL_IO_DESTROY_ALL_SURFACES_ASYNC:
1524 io_port = QXL_IO_DESTROY_ALL_SURFACES;
3e16b9c5
AL		 1525 goto async_common;
1526 case QXL_IO_FLUSH_SURFACES_ASYNC:
020af1c4 1527 case QXL_IO_MONITORS_CONFIG_ASYNC:
5ff4e36c
AL		 1528async_common:
1529 async = QXL_ASYNC;
1530 qemu_mutex_lock(&d->async_lock);
1531 if (d->current_async != QXL_UNDEFINED_IO) {
0a530548 1532 qxl_set_guest_bug(d, "%d async started before last (%d) complete",
5ff4e36c
AL		 1533 io_port, d->current_async);
1534 qemu_mutex_unlock(&d->async_lock);
1535 return;
1536 }
1537 d->current_async = orig_io_port;
1538 qemu_mutex_unlock(&d->async_lock);
5ff4e36c
AL		 1539 break;
1540 default:
1541 break;
1542 }
c480bb7d
AL		 1543 trace_qxl_io_write(d->id, qxl_mode_to_string(d->mode), addr, val, size,
1544 async);
5ff4e36c 1545
a19cbfb3
GH		 1546 switch (io_port) {
1547 case QXL_IO_UPDATE_AREA:
1548 {
81fb6f15 1549 QXLCookie *cookie = NULL;
a19cbfb3 1550 QXLRect update = d->ram->update_area;
81fb6f15 1551
ddd8fdc7 1552 if (d->ram->update_surface > d->ssd.num_surfaces) {
511b13e2
AL		 1553 qxl_set_guest_bug(d, "QXL_IO_UPDATE_AREA: invalid surface id %d\n",
1554 d->ram->update_surface);
36a03e0b 1555 break;
511b13e2 1556 }
36a03e0b
MT		 1557 if (update.left >= update.right || update.top >= update.bottom ||
1558 update.left < 0 || update.top < 0) {
511b13e2
AL		 1559 qxl_set_guest_bug(d,
1560 "QXL_IO_UPDATE_AREA: invalid area (%ux%u)x(%ux%u)\n",
1561 update.left, update.top, update.right, update.bottom);
ccc2960d
DH		 1562 break;
1563 }
81fb6f15
AL		 1564 if (async == QXL_ASYNC) {
1565 cookie = qxl_cookie_new(QXL_COOKIE_TYPE_IO,
1566 QXL_IO_UPDATE_AREA_ASYNC);
1567 cookie->u.area = update;
1568 }
aee32bf3 1569 qxl_spice_update_area(d, d->ram->update_surface,
81fb6f15
AL		 1570 cookie ? &cookie->u.area : &update,
1571 NULL, 0, 0, async, cookie);
a19cbfb3
GH		 1572 break;
1573 }
1574 case QXL_IO_NOTIFY_CMD:
5c59d118 1575 qemu_spice_wakeup(&d->ssd);
a19cbfb3
GH		 1576 break;
1577 case QXL_IO_NOTIFY_CURSOR:
5c59d118 1578 qemu_spice_wakeup(&d->ssd);
a19cbfb3
GH		 1579 break;
1580 case QXL_IO_UPDATE_IRQ:
40010aea 1581 qxl_update_irq(d);
a19cbfb3
GH		 1582 break;
1583 case QXL_IO_NOTIFY_OOM:
a19cbfb3
GH		 1584 if (!SPICE_RING_IS_EMPTY(&d->ram->release_ring)) {
1585 break;
1586 }
1587 d->oom_running = 1;
aee32bf3 1588 qxl_spice_oom(d);
a19cbfb3
GH		 1589 d->oom_running = 0;
1590 break;
1591 case QXL_IO_SET_MODE:
a19cbfb3
GH		 1592 qxl_set_mode(d, val, 0);
1593 break;
1594 case QXL_IO_LOG:
1a1bc085 1595 trace_qxl_io_log(d->id, d->ram->log_buf);
a19cbfb3 1596 if (d->guestdebug) {
a680f7e7 1597 fprintf(stderr, "qxl/guest-%d: %" PRId64 ": %s", d->id,
6ebebb55 1598 qemu_get_clock_ns(vm_clock), d->ram->log_buf);
a19cbfb3
GH		 1599 }
1600 break;
1601 case QXL_IO_RESET:
a19cbfb3
GH		 1602 qxl_hard_reset(d, 0);
1603 break;
1604 case QXL_IO_MEMSLOT_ADD:
2bce0400 1605 if (val >= NUM_MEMSLOTS) {
0a530548 1606 qxl_set_guest_bug(d, "QXL_IO_MEMSLOT_ADD: val out of range");
2bce0400
GH		 1607 break;
1608 }
1609 if (d->guest_slots[val].active) {
0a530548
AL		 1610 qxl_set_guest_bug(d,
1611 "QXL_IO_MEMSLOT_ADD: memory slot already active");
2bce0400
GH		 1612 break;
1613 }
a19cbfb3 1614 d->guest_slots[val].slot = d->ram->mem_slot;
5ff4e36c 1615 qxl_add_memslot(d, val, 0, async);
a19cbfb3
GH		 1616 break;
1617 case QXL_IO_MEMSLOT_DEL:
2bce0400 1618 if (val >= NUM_MEMSLOTS) {
0a530548 1619 qxl_set_guest_bug(d, "QXL_IO_MEMSLOT_DEL: val out of range");
2bce0400
GH		 1620 break;
1621 }
a19cbfb3
GH		 1622 qxl_del_memslot(d, val);
1623 break;
1624 case QXL_IO_CREATE_PRIMARY:
2bce0400 1625 if (val != 0) {
0a530548 1626 qxl_set_guest_bug(d, "QXL_IO_CREATE_PRIMARY (async=%d): val != 0",
5ff4e36c
AL		 1627 async);
1628 goto cancel_async;
2bce0400 1629 }
a19cbfb3 1630 d->guest_primary.surface = d->ram->create_surface;
5ff4e36c 1631 qxl_create_guest_primary(d, 0, async);
a19cbfb3
GH		 1632 break;
1633 case QXL_IO_DESTROY_PRIMARY:
2bce0400 1634 if (val != 0) {
0a530548 1635 qxl_set_guest_bug(d, "QXL_IO_DESTROY_PRIMARY (async=%d): val != 0",
5ff4e36c
AL		 1636 async);
1637 goto cancel_async;
1638 }
5ff4e36c 1639 if (!qxl_destroy_primary(d, async)) {
c480bb7d
AL		 1640 trace_qxl_io_destroy_primary_ignored(d->id,
1641 qxl_mode_to_string(d->mode));
5ff4e36c 1642 goto cancel_async;
2bce0400 1643 }
a19cbfb3
GH		 1644 break;
1645 case QXL_IO_DESTROY_SURFACE_WAIT:
ddd8fdc7 1646 if (val >= d->ssd.num_surfaces) {
0a530548 1647 qxl_set_guest_bug(d, "QXL_IO_DESTROY_SURFACE (async=%d):"
5f8daf2e 1648 "%" PRIu64 " >= NUM_SURFACES", async, val);
5ff4e36c
AL		 1649 goto cancel_async;
1650 }
1651 qxl_spice_destroy_surface_wait(d, val, async);
a19cbfb3 1652 break;
3e16b9c5
AL		 1653 case QXL_IO_FLUSH_RELEASE: {
1654 QXLReleaseRing *ring = &d->ram->release_ring;
1655 if (ring->prod - ring->cons + 1 == ring->num_items) {
1656 fprintf(stderr,
1657 "ERROR: no flush, full release ring [p%d,%dc]\n",
1658 ring->prod, ring->cons);
1659 }
1660 qxl_push_free_res(d, 1 /* flush */);
3e16b9c5
AL		 1661 break;
1662 }
1663 case QXL_IO_FLUSH_SURFACES_ASYNC:
3e16b9c5
AL		 1664 qxl_spice_flush_surfaces_async(d);
1665 break;
a19cbfb3 1666 case QXL_IO_DESTROY_ALL_SURFACES:
5ff4e36c
AL		 1667 d->mode = QXL_MODE_UNDEFINED;
1668 qxl_spice_destroy_surfaces(d, async);
a19cbfb3 1669 break;
020af1c4
AL		 1670 case QXL_IO_MONITORS_CONFIG_ASYNC:
1671 qxl_spice_monitors_config_async(d, 0);
1672 break;
a19cbfb3 1673 default:
0a530548 1674 qxl_set_guest_bug(d, "%s: unexpected ioport=0x%x\n", __func__, io_port);
a19cbfb3 1675 }
5ff4e36c
AL		 1676 return;
1677cancel_async:
5ff4e36c
AL		 1678 if (async) {
1679 qxl_send_events(d, QXL_INTERRUPT_IO_CMD);
1680 qemu_mutex_lock(&d->async_lock);
1681 d->current_async = QXL_UNDEFINED_IO;
1682 qemu_mutex_unlock(&d->async_lock);
1683 }
a19cbfb3
GH		 1684}
1685
a8170e5e 1686static uint64_t ioport_read(void *opaque, hwaddr addr,
b1950430 1687 unsigned size)
a19cbfb3 1688{
917ae08c 1689 PCIQXLDevice *qxl = opaque;
a19cbfb3 1690
917ae08c 1691 trace_qxl_io_read_unexpected(qxl->id);
a19cbfb3
GH		 1692 return 0xff;
1693}
1694
b1950430
AK		 1695static const MemoryRegionOps qxl_io_ops = {
1696 .read = ioport_read,
1697 .write = ioport_write,
1698 .valid = {
1699 .min_access_size = 1,
1700 .max_access_size = 1,
1701 },
1702};
a19cbfb3
GH		 1703
1704static void pipe_read(void *opaque)
1705{
1706 PCIQXLDevice *d = opaque;
1707 char dummy;
1708 int len;
1709
1710 do {
1711 len = read(d->pipe[0], &dummy, sizeof(dummy));
1712 } while (len == sizeof(dummy));
40010aea 1713 qxl_update_irq(d);
a19cbfb3
GH		 1714}
1715
a19cbfb3
GH		 1716static void qxl_send_events(PCIQXLDevice *d, uint32_t events)
1717{
1718 uint32_t old_pending;
1719 uint32_t le_events = cpu_to_le32(events);
1720
917ae08c 1721 trace_qxl_send_events(d->id, events);
511aefb0
AL		 1722 if (!qemu_spice_display_is_running(&d->ssd)) {
1723 /* spice-server tracks guest running state and should not do this */
1724 fprintf(stderr, "%s: spice-server bug: guest stopped, ignoring\n",
1725 __func__);
1726 trace_qxl_send_events_vm_stopped(d->id, events);
1727 return;
1728 }
a19cbfb3
GH		 1729 old_pending = __sync_fetch_and_or(&d->ram->int_pending, le_events);
1730 if ((old_pending & le_events) == le_events) {
1731 return;
1732 }
691f5c7b 1733 if (qemu_thread_is_self(&d->main)) {
40010aea 1734 qxl_update_irq(d);
a19cbfb3
GH		 1735 } else {
1736 if (write(d->pipe[1], d, 1) != 1) {
75fe0d7b 1737 dprint(d, 1, "%s: write to pipe failed\n", __func__);
a19cbfb3
GH		 1738 }
1739 }
1740}
1741
1742static void init_pipe_signaling(PCIQXLDevice *d)
1743{
aa3db423
AL		 1744 if (pipe(d->pipe) < 0) {
1745 fprintf(stderr, "%s:%s: qxl pipe creation failed\n",
1746 __FILE__, __func__);
1747 exit(1);
1748 }
1749 fcntl(d->pipe[0], F_SETFL, O_NONBLOCK);
1750 fcntl(d->pipe[1], F_SETFL, O_NONBLOCK);
1751 fcntl(d->pipe[0], F_SETOWN, getpid());
1752
1753 qemu_thread_get_self(&d->main);
1754 qemu_set_fd_handler(d->pipe[0], pipe_read, NULL, d);
a19cbfb3
GH		 1755}
1756
1757/* graphics console */
1758
1759static void qxl_hw_update(void *opaque)
1760{
1761 PCIQXLDevice *qxl = opaque;
1762 VGACommonState *vga = &qxl->vga;
1763
1764 switch (qxl->mode) {
1765 case QXL_MODE_VGA:
380cd056 1766 vga->hw_ops->gfx_update(vga);
a19cbfb3
GH		 1767 break;
1768 case QXL_MODE_COMPAT:
1769 case QXL_MODE_NATIVE:
1770 qxl_render_update(qxl);
1771 break;
1772 default:
1773 break;
1774 }
1775}
1776
1777static void qxl_hw_invalidate(void *opaque)
1778{
1779 PCIQXLDevice *qxl = opaque;
1780 VGACommonState *vga = &qxl->vga;
1781
bfe528b9
GH		 1782 if (qxl->mode == QXL_MODE_VGA) {
1783 vga->hw_ops->invalidate(vga);
1784 return;
1785 }
a19cbfb3
GH		 1786}
1787
a19cbfb3
GH		 1788static void qxl_hw_text_update(void *opaque, console_ch_t *chardata)
1789{
1790 PCIQXLDevice *qxl = opaque;
1791 VGACommonState *vga = &qxl->vga;
1792
1793 if (qxl->mode == QXL_MODE_VGA) {
380cd056 1794 vga->hw_ops->text_update(vga, chardata);
a19cbfb3
GH		 1795 return;
1796 }
1797}
1798
e25139b3
YH		 1799static void qxl_dirty_surfaces(PCIQXLDevice *qxl)
1800{
c5825ac6 1801 uintptr_t vram_start;
e25139b3
YH		 1802 int i;
1803
2aa9e85c 1804 if (qxl->mode != QXL_MODE_NATIVE && qxl->mode != QXL_MODE_COMPAT) {
e25139b3
YH		 1805 return;
1806 }
1807
1808 /* dirty the primary surface */
1809 qxl_set_dirty(&qxl->vga.vram, qxl->shadow_rom.draw_area_offset,
1810 qxl->shadow_rom.surface0_area_size);
1811
c5825ac6 1812 vram_start = (uintptr_t)memory_region_get_ram_ptr(&qxl->vram_bar);
e25139b3
YH		 1813
1814 /* dirty the off-screen surfaces */
ddd8fdc7 1815 for (i = 0; i < qxl->ssd.num_surfaces; i++) {
e25139b3
YH		 1816 QXLSurfaceCmd *cmd;
1817 intptr_t surface_offset;
1818 int surface_size;
1819
1820 if (qxl->guest_surfaces.cmds[i] == 0) {
1821 continue;
1822 }
1823
1824 cmd = qxl_phys2virt(qxl, qxl->guest_surfaces.cmds[i],
1825 MEMSLOT_GROUP_GUEST);
fae2afb1 1826 assert(cmd);
e25139b3
YH		 1827 assert(cmd->type == QXL_SURFACE_CMD_CREATE);
1828 surface_offset = (intptr_t)qxl_phys2virt(qxl,
1829 cmd->u.surface_create.data,
1830 MEMSLOT_GROUP_GUEST);
fae2afb1 1831 assert(surface_offset);
e25139b3
YH		 1832 surface_offset -= vram_start;
1833 surface_size = cmd->u.surface_create.height *
1834 abs(cmd->u.surface_create.stride);
c480bb7d 1835 trace_qxl_surfaces_dirty(qxl->id, i, (int)surface_offset, surface_size);
e25139b3
YH		 1836 qxl_set_dirty(&qxl->vram_bar, surface_offset, surface_size);
1837 }
1838}
1839
1dfb4dd9
LC		 1840static void qxl_vm_change_state_handler(void *opaque, int running,
1841 RunState state)
a19cbfb3
GH		 1842{
1843 PCIQXLDevice *qxl = opaque;
a19cbfb3 1844
efbf2950
YH		 1845 if (running) {
1846 /*
1847 * if qxl_send_events was called from spice server context before
40010aea 1848 * migration ended, qxl_update_irq for these events might not have been
efbf2950
YH		 1849 * called
1850 */
40010aea 1851 qxl_update_irq(qxl);
e25139b3
YH		 1852 } else {
1853 /* make sure surfaces are saved before migration */
1854 qxl_dirty_surfaces(qxl);
a19cbfb3
GH		 1855 }
1856}
1857
1858/* display change listener */
1859
7c20b4a3 1860static void display_update(DisplayChangeListener *dcl,
7c20b4a3 1861 int x, int y, int w, int h)
a19cbfb3 1862{
c6c06853
GH		 1863 PCIQXLDevice *qxl = container_of(dcl, PCIQXLDevice, ssd.dcl);
1864
1865 if (qxl->mode == QXL_MODE_VGA) {
1866 qemu_spice_display_update(&qxl->ssd, x, y, w, h);
a19cbfb3
GH		 1867 }
1868}
1869
c12aeb86 1870static void display_switch(DisplayChangeListener *dcl,
c12aeb86 1871 struct DisplaySurface *surface)
a19cbfb3 1872{
c6c06853
GH		 1873 PCIQXLDevice *qxl = container_of(dcl, PCIQXLDevice, ssd.dcl);
1874
71874c17 1875 qxl->ssd.ds = surface;
c6c06853 1876 if (qxl->mode == QXL_MODE_VGA) {
c12aeb86 1877 qemu_spice_display_switch(&qxl->ssd, surface);
a19cbfb3
GH		 1878 }
1879}
1880
bc2ed970 1881static void display_refresh(DisplayChangeListener *dcl)
a19cbfb3 1882{
c6c06853
GH		 1883 PCIQXLDevice *qxl = container_of(dcl, PCIQXLDevice, ssd.dcl);
1884
1885 if (qxl->mode == QXL_MODE_VGA) {
1886 qemu_spice_display_refresh(&qxl->ssd);
bb5a8cd5 1887 } else {
c6c06853
GH		 1888 qemu_mutex_lock(&qxl->ssd.lock);
1889 qemu_spice_cursor_refresh_unlocked(&qxl->ssd);
1890 qemu_mutex_unlock(&qxl->ssd.lock);
a19cbfb3
GH		 1891 }
1892}
1893
7c20b4a3
GH		 1894static DisplayChangeListenerOps display_listener_ops = {
1895 .dpy_name = "spice/qxl",
a93a4a22 1896 .dpy_gfx_update = display_update,
c12aeb86 1897 .dpy_gfx_switch = display_switch,
7c20b4a3 1898 .dpy_refresh = display_refresh,
a19cbfb3
GH		 1899};
1900
13d1fd44 1901static void qxl_init_ramsize(PCIQXLDevice *qxl)
a974192c 1902{
13d1fd44
AL		 1903 /* vga mode framebuffer / primary surface (bar 0, first part) */
1904 if (qxl->vgamem_size_mb < 8) {
1905 qxl->vgamem_size_mb = 8;
1906 }
1907 qxl->vgamem_size = qxl->vgamem_size_mb * 1024 * 1024;
1908
1909 /* vga ram (bar 0, total) */
017438ee
GH		 1910 if (qxl->ram_size_mb != -1) {
1911 qxl->vga.vram_size = qxl->ram_size_mb * 1024 * 1024;
1912 }
13d1fd44
AL		 1913 if (qxl->vga.vram_size < qxl->vgamem_size * 2) {
1914 qxl->vga.vram_size = qxl->vgamem_size * 2;
a974192c
GH		 1915 }
1916
6f2b175a
GH		 1917 /* vram32 (surfaces, 32bit, bar 1) */
1918 if (qxl->vram32_size_mb != -1) {
1919 qxl->vram32_size = qxl->vram32_size_mb * 1024 * 1024;
1920 }
1921 if (qxl->vram32_size < 4096) {
1922 qxl->vram32_size = 4096;
1923 }
1924
1925 /* vram (surfaces, 64bit, bar 4+5) */
017438ee
GH		 1926 if (qxl->vram_size_mb != -1) {
1927 qxl->vram_size = qxl->vram_size_mb * 1024 * 1024;
1928 }
6f2b175a
GH		 1929 if (qxl->vram_size < qxl->vram32_size) {
1930 qxl->vram_size = qxl->vram32_size;
a974192c 1931 }
6f2b175a 1932
a974192c 1933 if (qxl->revision == 1) {
6f2b175a 1934 qxl->vram32_size = 4096;
a974192c
GH		 1935 qxl->vram_size = 4096;
1936 }
13d1fd44 1937 qxl->vgamem_size = msb_mask(qxl->vgamem_size * 2 - 1);
a974192c 1938 qxl->vga.vram_size = msb_mask(qxl->vga.vram_size * 2 - 1);
6f2b175a 1939 qxl->vram32_size = msb_mask(qxl->vram32_size * 2 - 1);
a974192c
GH		 1940 qxl->vram_size = msb_mask(qxl->vram_size * 2 - 1);
1941}
1942
a19cbfb3
GH		 1943static int qxl_init_common(PCIQXLDevice *qxl)
1944{
1945 uint8_t* config = qxl->pci.config;
a19cbfb3
GH		 1946 uint32_t pci_device_rev;
1947 uint32_t io_size;
1948
1949 qxl->mode = QXL_MODE_UNDEFINED;
1950 qxl->generation = 1;
1951 qxl->num_memslots = NUM_MEMSLOTS;
14898cf6 1952 qemu_mutex_init(&qxl->track_lock);
5ff4e36c
AL		 1953 qemu_mutex_init(&qxl->async_lock);
1954 qxl->current_async = QXL_UNDEFINED_IO;
087e6a42 1955 qxl->guest_bug = 0;
a19cbfb3
GH		 1956
1957 switch (qxl->revision) {
1958 case 1: /* spice 0.4 -- qxl-1 */
a19cbfb3 1959 pci_device_rev = QXL_REVISION_STABLE_V04;
3f6297b9 1960 io_size = 8;
a19cbfb3
GH		 1961 break;
1962 case 2: /* spice 0.6 -- qxl-2 */
a19cbfb3 1963 pci_device_rev = QXL_REVISION_STABLE_V06;
3f6297b9 1964 io_size = 16;
a19cbfb3 1965 break;
9197a7c8 1966 case 3: /* qxl-3 */
020af1c4
AL		 1967 pci_device_rev = QXL_REVISION_STABLE_V10;
1968 io_size = 32; /* PCI region size must be pow2 */
1969 break;
020af1c4
AL		 1970 case 4: /* qxl-4 */
1971 pci_device_rev = QXL_REVISION_STABLE_V12;
3f6297b9 1972 io_size = msb_mask(QXL_IO_RANGE_SIZE * 2 - 1);
9197a7c8 1973 break;
36839d35
AL		 1974 default:
1975 error_report("Invalid revision %d for qxl device (max %d)",
1976 qxl->revision, QXL_DEFAULT_REVISION);
1977 return -1;
a19cbfb3
GH		 1978 }
1979
a19cbfb3
GH		 1980 pci_set_byte(&config[PCI_REVISION_ID], pci_device_rev);
1981 pci_set_byte(&config[PCI_INTERRUPT_PIN], 1);
1982
1983 qxl->rom_size = qxl_rom_size();
2c9b15ca 1984 memory_region_init_ram(&qxl->rom_bar, NULL, "qxl.vrom", qxl->rom_size);
c5705a77 1985 vmstate_register_ram(&qxl->rom_bar, &qxl->pci.qdev);
a19cbfb3
GH		 1986 init_qxl_rom(qxl);
1987 init_qxl_ram(qxl);
1988
ddd8fdc7 1989 qxl->guest_surfaces.cmds = g_new0(QXLPHYSICAL, qxl->ssd.num_surfaces);
2c9b15ca 1990 memory_region_init_ram(&qxl->vram_bar, NULL, "qxl.vram", qxl->vram_size);
c5705a77 1991 vmstate_register_ram(&qxl->vram_bar, &qxl->pci.qdev);
2c9b15ca 1992 memory_region_init_alias(&qxl->vram32_bar, NULL, "qxl.vram32", &qxl->vram_bar,
6f2b175a 1993 0, qxl->vram32_size);
a19cbfb3 1994
2c9b15ca 1995 memory_region_init_io(&qxl->io_bar, NULL, &qxl_io_ops, qxl,
b1950430
AK		 1996 "qxl-ioports", io_size);
1997 if (qxl->id == 0) {
1998 vga_dirty_log_start(&qxl->vga);
1999 }
bd8f2f5d 2000 memory_region_set_flush_coalesced(&qxl->io_bar);
b1950430
AK		 2001
2002
e824b2cc
AK		 2003 pci_register_bar(&qxl->pci, QXL_IO_RANGE_INDEX,
2004 PCI_BASE_ADDRESS_SPACE_IO, &qxl->io_bar);
a19cbfb3 2005
e824b2cc
AK		 2006 pci_register_bar(&qxl->pci, QXL_ROM_RANGE_INDEX,
2007 PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->rom_bar);
a19cbfb3 2008
e824b2cc
AK		 2009 pci_register_bar(&qxl->pci, QXL_RAM_RANGE_INDEX,
2010 PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->vga.vram);
a19cbfb3 2011
e824b2cc 2012 pci_register_bar(&qxl->pci, QXL_VRAM_RANGE_INDEX,
6f2b175a
GH		 2013 PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->vram32_bar);
2014
2015 if (qxl->vram32_size < qxl->vram_size) {
2016 /*
2017 * Make the 64bit vram bar show up only in case it is
2018 * configured to be larger than the 32bit vram bar.
2019 */
2020 pci_register_bar(&qxl->pci, QXL_VRAM64_RANGE_INDEX,
2021 PCI_BASE_ADDRESS_SPACE_MEMORY |
2022 PCI_BASE_ADDRESS_MEM_TYPE_64 |
2023 PCI_BASE_ADDRESS_MEM_PREFETCH,
2024 &qxl->vram_bar);
2025 }
2026
2027 /* print pci bar details */
2028 dprint(qxl, 1, "ram/%s: %d MB [region 0]\n",
2029 qxl->id == 0 ? "pri" : "sec",
2030 qxl->vga.vram_size / (1024*1024));
2031 dprint(qxl, 1, "vram/32: %d MB [region 1]\n",
2032 qxl->vram32_size / (1024*1024));
2033 dprint(qxl, 1, "vram/64: %d MB %s\n",
2034 qxl->vram_size / (1024*1024),
2035 qxl->vram32_size < qxl->vram_size ? "[region 4]" : "[unmapped]");
a19cbfb3
GH		 2036
2037 qxl->ssd.qxl.base.sif = &qxl_interface.base;
2038 qxl->ssd.qxl.id = qxl->id;
e25a0651 2039 if (qemu_spice_add_interface(&qxl->ssd.qxl.base) != 0) {
312fd5f2 2040 error_report("qxl interface %d.%d not supported by spice-server",
e25a0651
AL		 2041 SPICE_INTERFACE_QXL_MAJOR, SPICE_INTERFACE_QXL_MINOR);
2042 return -1;
2043 }
a19cbfb3
GH		 2044 qemu_add_vm_change_state_handler(qxl_vm_change_state_handler, qxl);
2045
2046 init_pipe_signaling(qxl);
2047 qxl_reset_state(qxl);
2048
81fb6f15
AL		 2049 qxl->update_area_bh = qemu_bh_new(qxl_render_update_area_bh, qxl);
2050
a19cbfb3
GH		 2051 return 0;
2052}
2053
380cd056
GH		 2054static const GraphicHwOps qxl_ops = {
2055 .invalidate = qxl_hw_invalidate,
2056 .gfx_update = qxl_hw_update,
2057 .text_update = qxl_hw_text_update,
2058};
2059
a19cbfb3
GH		 2060static int qxl_init_primary(PCIDevice *dev)
2061{
2062 PCIQXLDevice *qxl = DO_UPCAST(PCIQXLDevice, pci, dev);
2063 VGACommonState *vga = &qxl->vga;
f67ab77a 2064 PortioList *qxl_vga_port_list = g_new(PortioList, 1);
bdd4df33 2065 int rc;
a19cbfb3
GH		 2066
2067 qxl->id = 0;
13d1fd44 2068 qxl_init_ramsize(qxl);
4a1e244e
GH		 2069 vga->vram_size_mb = qxl->vga.vram_size >> 20;
2070 vga_common_init(vga);
712f0cc7
PB		 2071 vga_init(vga, OBJECT(dev),
2072 pci_address_space(dev), pci_address_space_io(dev), false);
f67ab77a
GH		 2073 portio_list_init(qxl_vga_port_list, qxl_vga_portio_list, vga, "vga");
2074 portio_list_add(qxl_vga_port_list, pci_address_space_io(dev), 0x3b0);
a19cbfb3 2075
aa2beaa1 2076 vga->con = graphic_console_init(DEVICE(dev), &qxl_ops, qxl);
c78f7137 2077 qemu_spice_display_init_common(&qxl->ssd);
a19cbfb3 2078
bdd4df33
GH		 2079 rc = qxl_init_common(qxl);
2080 if (rc != 0) {
2081 return rc;
2082 }
2083
7c20b4a3 2084 qxl->ssd.dcl.ops = &display_listener_ops;
284d1c6b 2085 qxl->ssd.dcl.con = vga->con;
5209089f 2086 register_displaychangelistener(&qxl->ssd.dcl);
bdd4df33 2087 return rc;
a19cbfb3
GH		 2088}
2089
2090static int qxl_init_secondary(PCIDevice *dev)
2091{
2092 static int device_id = 1;
2093 PCIQXLDevice *qxl = DO_UPCAST(PCIQXLDevice, pci, dev);
a19cbfb3
GH		 2094
2095 qxl->id = device_id++;
13d1fd44 2096 qxl_init_ramsize(qxl);
2c9b15ca 2097 memory_region_init_ram(&qxl->vga.vram, NULL, "qxl.vgavram", qxl->vga.vram_size);
c5705a77 2098 vmstate_register_ram(&qxl->vga.vram, &qxl->pci.qdev);
b1950430 2099 qxl->vga.vram_ptr = memory_region_get_ram_ptr(&qxl->vga.vram);
aa2beaa1 2100 qxl->vga.con = graphic_console_init(DEVICE(dev), &qxl_ops, qxl);
a19cbfb3 2101
a19cbfb3
GH		 2102 return qxl_init_common(qxl);
2103}
2104
2105static void qxl_pre_save(void *opaque)
2106{
2107 PCIQXLDevice* d = opaque;
2108 uint8_t *ram_start = d->vga.vram_ptr;
2109
c480bb7d 2110 trace_qxl_pre_save(d->id);
a19cbfb3
GH		 2111 if (d->last_release == NULL) {
2112 d->last_release_offset = 0;
2113 } else {
2114 d->last_release_offset = (uint8_t *)d->last_release - ram_start;
2115 }
2116 assert(d->last_release_offset < d->vga.vram_size);
2117}
2118
2119static int qxl_pre_load(void *opaque)
2120{
2121 PCIQXLDevice* d = opaque;
2122
c480bb7d 2123 trace_qxl_pre_load(d->id);
a19cbfb3
GH		 2124 qxl_hard_reset(d, 1);
2125 qxl_exit_vga_mode(d);
a19cbfb3
GH		 2126 return 0;
2127}
2128
54825d2e
AL		 2129static void qxl_create_memslots(PCIQXLDevice *d)
2130{
2131 int i;
2132
2133 for (i = 0; i < NUM_MEMSLOTS; i++) {
2134 if (!d->guest_slots[i].active) {
2135 continue;
2136 }
54825d2e
AL		 2137 qxl_add_memslot(d, i, 0, QXL_SYNC);
2138 }
2139}
2140
a19cbfb3
GH		 2141static int qxl_post_load(void *opaque, int version)
2142{
2143 PCIQXLDevice* d = opaque;
2144 uint8_t *ram_start = d->vga.vram_ptr;
2145 QXLCommandExt *cmds;
54825d2e 2146 int in, out, newmode;
a19cbfb3 2147
a19cbfb3
GH		 2148 assert(d->last_release_offset < d->vga.vram_size);
2149 if (d->last_release_offset == 0) {
2150 d->last_release = NULL;
2151 } else {
2152 d->last_release = (QXLReleaseInfo *)(ram_start + d->last_release_offset);
2153 }
2154
2155 d->modes = (QXLModes*)((uint8_t*)d->rom + d->rom->modes_offset);
2156
c480bb7d 2157 trace_qxl_post_load(d->id, qxl_mode_to_string(d->mode));
a19cbfb3
GH		 2158 newmode = d->mode;
2159 d->mode = QXL_MODE_UNDEFINED;
54825d2e 2160
a19cbfb3
GH		 2161 switch (newmode) {
2162 case QXL_MODE_UNDEFINED:
fa98efe9 2163 qxl_create_memslots(d);
a19cbfb3
GH		 2164 break;
2165 case QXL_MODE_VGA:
54825d2e 2166 qxl_create_memslots(d);
a19cbfb3
GH		 2167 qxl_enter_vga_mode(d);
2168 break;
2169 case QXL_MODE_NATIVE:
54825d2e 2170 qxl_create_memslots(d);
5ff4e36c 2171 qxl_create_guest_primary(d, 1, QXL_SYNC);
a19cbfb3
GH		 2172
2173 /* replay surface-create and cursor-set commands */
ddd8fdc7
GH		 2174 cmds = g_malloc0(sizeof(QXLCommandExt) * (d->ssd.num_surfaces + 1));
2175 for (in = 0, out = 0; in < d->ssd.num_surfaces; in++) {
a19cbfb3
GH		 2176 if (d->guest_surfaces.cmds[in] == 0) {
2177 continue;
2178 }
2179 cmds[out].cmd.data = d->guest_surfaces.cmds[in];
2180 cmds[out].cmd.type = QXL_CMD_SURFACE;
2181 cmds[out].group_id = MEMSLOT_GROUP_GUEST;
2182 out++;
2183 }
30f6da66
YH		 2184 if (d->guest_cursor) {
2185 cmds[out].cmd.data = d->guest_cursor;
2186 cmds[out].cmd.type = QXL_CMD_CURSOR;
2187 cmds[out].group_id = MEMSLOT_GROUP_GUEST;
2188 out++;
2189 }
aee32bf3 2190 qxl_spice_loadvm_commands(d, cmds, out);
7267c094 2191 g_free(cmds);
020af1c4
AL		 2192 if (d->guest_monitors_config) {
2193 qxl_spice_monitors_config_async(d, 1);
2194 }
a19cbfb3
GH		 2195 break;
2196 case QXL_MODE_COMPAT:
54825d2e
AL		 2197 /* note: no need to call qxl_create_memslots, qxl_set_mode
2198 * creates the mem slot. */
a19cbfb3
GH		 2199 qxl_set_mode(d, d->shadow_rom.mode, 1);
2200 break;
2201 }
a19cbfb3
GH		 2202 return 0;
2203}
2204
b67737a6 2205#define QXL_SAVE_VERSION 21
a19cbfb3 2206
020af1c4
AL		 2207static bool qxl_monitors_config_needed(void *opaque)
2208{
2209 PCIQXLDevice *qxl = opaque;
2210
2211 return qxl->guest_monitors_config != 0;
2212}
2213
2214
a19cbfb3
GH		 2215static VMStateDescription qxl_memslot = {
2216 .name = "qxl-memslot",
2217 .version_id = QXL_SAVE_VERSION,
2218 .minimum_version_id = QXL_SAVE_VERSION,
2219 .fields = (VMStateField[]) {
2220 VMSTATE_UINT64(slot.mem_start, struct guest_slots),
2221 VMSTATE_UINT64(slot.mem_end, struct guest_slots),
2222 VMSTATE_UINT32(active, struct guest_slots),
2223 VMSTATE_END_OF_LIST()
2224 }
2225};
2226
2227static VMStateDescription qxl_surface = {
2228 .name = "qxl-surface",
2229 .version_id = QXL_SAVE_VERSION,
2230 .minimum_version_id = QXL_SAVE_VERSION,
2231 .fields = (VMStateField[]) {
2232 VMSTATE_UINT32(width, QXLSurfaceCreate),
2233 VMSTATE_UINT32(height, QXLSurfaceCreate),
2234 VMSTATE_INT32(stride, QXLSurfaceCreate),
2235 VMSTATE_UINT32(format, QXLSurfaceCreate),
2236 VMSTATE_UINT32(position, QXLSurfaceCreate),
2237 VMSTATE_UINT32(mouse_mode, QXLSurfaceCreate),
2238 VMSTATE_UINT32(flags, QXLSurfaceCreate),
2239 VMSTATE_UINT32(type, QXLSurfaceCreate),
2240 VMSTATE_UINT64(mem, QXLSurfaceCreate),
2241 VMSTATE_END_OF_LIST()
2242 }
2243};
2244
020af1c4
AL		 2245static VMStateDescription qxl_vmstate_monitors_config = {
2246 .name = "qxl/monitors-config",
2247 .version_id = 1,
2248 .minimum_version_id = 1,
2249 .fields = (VMStateField[]) {
2250 VMSTATE_UINT64(guest_monitors_config, PCIQXLDevice),
2251 VMSTATE_END_OF_LIST()
2252 },
2253};
2254
a19cbfb3
GH		 2255static VMStateDescription qxl_vmstate = {
2256 .name = "qxl",
2257 .version_id = QXL_SAVE_VERSION,
2258 .minimum_version_id = QXL_SAVE_VERSION,
2259 .pre_save = qxl_pre_save,
2260 .pre_load = qxl_pre_load,
2261 .post_load = qxl_post_load,
020af1c4 2262 .fields = (VMStateField[]) {
a19cbfb3
GH		 2263 VMSTATE_PCI_DEVICE(pci, PCIQXLDevice),
2264 VMSTATE_STRUCT(vga, PCIQXLDevice, 0, vmstate_vga_common, VGACommonState),
2265 VMSTATE_UINT32(shadow_rom.mode, PCIQXLDevice),
2266 VMSTATE_UINT32(num_free_res, PCIQXLDevice),
2267 VMSTATE_UINT32(last_release_offset, PCIQXLDevice),
2268 VMSTATE_UINT32(mode, PCIQXLDevice),
2269 VMSTATE_UINT32(ssd.unique, PCIQXLDevice),
b67737a6
GH		 2270 VMSTATE_INT32_EQUAL(num_memslots, PCIQXLDevice),
2271 VMSTATE_STRUCT_ARRAY(guest_slots, PCIQXLDevice, NUM_MEMSLOTS, 0,
2272 qxl_memslot, struct guest_slots),
2273 VMSTATE_STRUCT(guest_primary.surface, PCIQXLDevice, 0,
2274 qxl_surface, QXLSurfaceCreate),
ddd8fdc7
GH		 2275 VMSTATE_INT32_EQUAL(ssd.num_surfaces, PCIQXLDevice),
2276 VMSTATE_VARRAY_INT32(guest_surfaces.cmds, PCIQXLDevice,
2277 ssd.num_surfaces, 0,
2278 vmstate_info_uint64, uint64_t),
b67737a6 2279 VMSTATE_UINT64(guest_cursor, PCIQXLDevice),
a19cbfb3
GH		 2280 VMSTATE_END_OF_LIST()
2281 },
020af1c4
AL		 2282 .subsections = (VMStateSubsection[]) {
2283 {
2284 .vmsd = &qxl_vmstate_monitors_config,
2285 .needed = qxl_monitors_config_needed,
2286 }, {
2287 /* empty */
2288 }
2289 }
a19cbfb3
GH		 2290};
2291
78e60ba5
GH		 2292static Property qxl_properties[] = {
2293 DEFINE_PROP_UINT32("ram_size", PCIQXLDevice, vga.vram_size,
2294 64 * 1024 * 1024),
6f2b175a 2295 DEFINE_PROP_UINT32("vram_size", PCIQXLDevice, vram32_size,
78e60ba5
GH		 2296 64 * 1024 * 1024),
2297 DEFINE_PROP_UINT32("revision", PCIQXLDevice, revision,
2298 QXL_DEFAULT_REVISION),
2299 DEFINE_PROP_UINT32("debug", PCIQXLDevice, debug, 0),
2300 DEFINE_PROP_UINT32("guestdebug", PCIQXLDevice, guestdebug, 0),
2301 DEFINE_PROP_UINT32("cmdlog", PCIQXLDevice, cmdlog, 0),
017438ee 2302 DEFINE_PROP_UINT32("ram_size_mb", PCIQXLDevice, ram_size_mb, -1),
79ce3567
AL		 2303 DEFINE_PROP_UINT32("vram_size_mb", PCIQXLDevice, vram32_size_mb, -1),
2304 DEFINE_PROP_UINT32("vram64_size_mb", PCIQXLDevice, vram_size_mb, -1),
9e56edcf 2305 DEFINE_PROP_UINT32("vgamem_mb", PCIQXLDevice, vgamem_size_mb, 16),
ddd8fdc7 2306 DEFINE_PROP_INT32("surfaces", PCIQXLDevice, ssd.num_surfaces, 1024),
78e60ba5
GH		 2307 DEFINE_PROP_END_OF_LIST(),
2308};
2309
40021f08
AL		 2310static void qxl_primary_class_init(ObjectClass *klass, void *data)
2311{
39bffca2 2312 DeviceClass *dc = DEVICE_CLASS(klass);
40021f08
AL		 2313 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
2314
2315 k->no_hotplug = 1;
2316 k->init = qxl_init_primary;
2317 k->romfile = "vgabios-qxl.bin";
2318 k->vendor_id = REDHAT_PCI_VENDOR_ID;
2319 k->device_id = QXL_DEVICE_ID_STABLE;
2320 k->class_id = PCI_CLASS_DISPLAY_VGA;
39bffca2
AL		 2321 dc->desc = "Spice QXL GPU (primary, vga compatible)";
2322 dc->reset = qxl_reset_handler;
2323 dc->vmsd = &qxl_vmstate;
2324 dc->props = qxl_properties;
40021f08
AL		 2325}
2326
8c43a6f0 2327static const TypeInfo qxl_primary_info = {
39bffca2
AL		 2328 .name = "qxl-vga",
2329 .parent = TYPE_PCI_DEVICE,
2330 .instance_size = sizeof(PCIQXLDevice),
2331 .class_init = qxl_primary_class_init,
a19cbfb3
GH		 2332};
2333
40021f08
AL		 2334static void qxl_secondary_class_init(ObjectClass *klass, void *data)
2335{
39bffca2 2336 DeviceClass *dc = DEVICE_CLASS(klass);
40021f08
AL		 2337 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
2338
2339 k->init = qxl_init_secondary;
2340 k->vendor_id = REDHAT_PCI_VENDOR_ID;
2341 k->device_id = QXL_DEVICE_ID_STABLE;
2342 k->class_id = PCI_CLASS_DISPLAY_OTHER;
39bffca2
AL		 2343 dc->desc = "Spice QXL GPU (secondary)";
2344 dc->reset = qxl_reset_handler;
2345 dc->vmsd = &qxl_vmstate;
2346 dc->props = qxl_properties;
40021f08
AL		 2347}
2348
8c43a6f0 2349static const TypeInfo qxl_secondary_info = {
39bffca2
AL		 2350 .name = "qxl",
2351 .parent = TYPE_PCI_DEVICE,
2352 .instance_size = sizeof(PCIQXLDevice),
2353 .class_init = qxl_secondary_class_init,
a19cbfb3
GH		 2354};
2355
83f7d43a 2356static void qxl_register_types(void)
a19cbfb3 2357{
39bffca2
AL		 2358 type_register_static(&qxl_primary_info);
2359 type_register_static(&qxl_secondary_info);
a19cbfb3
GH		 2360}
2361
83f7d43a 2362type_init(qxl_register_types)
Empty description
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