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qxl: add QXL_IO_FLUSH_{SURFACES,RELEASE} for guest S3&S4 support
[qemu.git] / hw / qxl.c
CommitLineData
a19cbfb3
GH		 1/*
2 * Copyright (C) 2010 Red Hat, Inc.
3 *
4 * written by Yaniv Kamay, Izik Eidus, Gerd Hoffmann
5 * maintained by Gerd Hoffmann <[email protected]>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 or
10 * (at your option) version 3 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21#include <pthread.h>
22
23#include "qemu-common.h"
24#include "qemu-timer.h"
25#include "qemu-queue.h"
26#include "monitor.h"
27#include "sysemu.h"
28
29#include "qxl.h"
30
31#undef SPICE_RING_PROD_ITEM
32#define SPICE_RING_PROD_ITEM(r, ret) { \
33 typeof(r) start = r; \
34 typeof(r) end = r + 1; \
35 uint32_t prod = (r)->prod & SPICE_RING_INDEX_MASK(r); \
36 typeof(&(r)->items[prod]) m_item = &(r)->items[prod]; \
37 if (!((uint8_t*)m_item >= (uint8_t*)(start) && (uint8_t*)(m_item + 1) <= (uint8_t*)(end))) { \
38 abort(); \
39 } \
40 ret = &m_item->el; \
41 }
42
43#undef SPICE_RING_CONS_ITEM
44#define SPICE_RING_CONS_ITEM(r, ret) { \
45 typeof(r) start = r; \
46 typeof(r) end = r + 1; \
47 uint32_t cons = (r)->cons & SPICE_RING_INDEX_MASK(r); \
48 typeof(&(r)->items[cons]) m_item = &(r)->items[cons]; \
49 if (!((uint8_t*)m_item >= (uint8_t*)(start) && (uint8_t*)(m_item + 1) <= (uint8_t*)(end))) { \
50 abort(); \
51 } \
52 ret = &m_item->el; \
53 }
54
55#undef ALIGN
56#define ALIGN(a, b) (((a) + ((b) - 1)) & ~((b) - 1))
57
58#define PIXEL_SIZE 0.2936875 //1280x1024 is 14.8" x 11.9"
59
60#define QXL_MODE(_x, _y, _b, _o) \
61 { .x_res = _x, \
62 .y_res = _y, \
63 .bits = _b, \
64 .stride = (_x) * (_b) / 8, \
65 .x_mili = PIXEL_SIZE * (_x), \
66 .y_mili = PIXEL_SIZE * (_y), \
67 .orientation = _o, \
68 }
69
70#define QXL_MODE_16_32(x_res, y_res, orientation) \
71 QXL_MODE(x_res, y_res, 16, orientation), \
72 QXL_MODE(x_res, y_res, 32, orientation)
73
74#define QXL_MODE_EX(x_res, y_res) \
75 QXL_MODE_16_32(x_res, y_res, 0), \
76 QXL_MODE_16_32(y_res, x_res, 1), \
77 QXL_MODE_16_32(x_res, y_res, 2), \
78 QXL_MODE_16_32(y_res, x_res, 3)
79
80static QXLMode qxl_modes[] = {
81 QXL_MODE_EX(640, 480),
82 QXL_MODE_EX(800, 480),
83 QXL_MODE_EX(800, 600),
84 QXL_MODE_EX(832, 624),
85 QXL_MODE_EX(960, 640),
86 QXL_MODE_EX(1024, 600),
87 QXL_MODE_EX(1024, 768),
88 QXL_MODE_EX(1152, 864),
89 QXL_MODE_EX(1152, 870),
90 QXL_MODE_EX(1280, 720),
91 QXL_MODE_EX(1280, 760),
92 QXL_MODE_EX(1280, 768),
93 QXL_MODE_EX(1280, 800),
94 QXL_MODE_EX(1280, 960),
95 QXL_MODE_EX(1280, 1024),
96 QXL_MODE_EX(1360, 768),
97 QXL_MODE_EX(1366, 768),
98 QXL_MODE_EX(1400, 1050),
99 QXL_MODE_EX(1440, 900),
100 QXL_MODE_EX(1600, 900),
101 QXL_MODE_EX(1600, 1200),
102 QXL_MODE_EX(1680, 1050),
103 QXL_MODE_EX(1920, 1080),
104#if VGA_RAM_SIZE >= (16 * 1024 * 1024)
105 /* these modes need more than 8 MB video memory */
106 QXL_MODE_EX(1920, 1200),
107 QXL_MODE_EX(1920, 1440),
108 QXL_MODE_EX(2048, 1536),
109 QXL_MODE_EX(2560, 1440),
110 QXL_MODE_EX(2560, 1600),
111#endif
112#if VGA_RAM_SIZE >= (32 * 1024 * 1024)
113 /* these modes need more than 16 MB video memory */
114 QXL_MODE_EX(2560, 2048),
115 QXL_MODE_EX(2800, 2100),
116 QXL_MODE_EX(3200, 2400),
117#endif
118};
119
120static PCIQXLDevice *qxl0;
121
122static void qxl_send_events(PCIQXLDevice *d, uint32_t events);
5ff4e36c 123static int qxl_destroy_primary(PCIQXLDevice *d, qxl_async_io async);
a19cbfb3
GH		 124static void qxl_reset_memslots(PCIQXLDevice *d);
125static void qxl_reset_surfaces(PCIQXLDevice *d);
126static void qxl_ring_set_dirty(PCIQXLDevice *qxl);
127
7635392c 128void qxl_guest_bug(PCIQXLDevice *qxl, const char *msg, ...)
2bce0400
GH		 129{
130#if SPICE_INTERFACE_QXL_MINOR >= 1
131 qxl_send_events(qxl, QXL_INTERRUPT_ERROR);
132#endif
133 if (qxl->guestdebug) {
7635392c
AL		 134 va_list ap;
135 va_start(ap, msg);
136 fprintf(stderr, "qxl-%d: guest bug: ", qxl->id);
137 vfprintf(stderr, msg, ap);
138 fprintf(stderr, "\n");
139 va_end(ap);
2bce0400
GH		 140 }
141}
142
aee32bf3
GH		 143
144void qxl_spice_update_area(PCIQXLDevice *qxl, uint32_t surface_id,
145 struct QXLRect *area, struct QXLRect *dirty_rects,
146 uint32_t num_dirty_rects,
5ff4e36c
AL		 147 uint32_t clear_dirty_region,
148 qxl_async_io async)
aee32bf3 149{
5ff4e36c
AL		 150 if (async == QXL_SYNC) {
151 qxl->ssd.worker->update_area(qxl->ssd.worker, surface_id, area,
152 dirty_rects, num_dirty_rects, clear_dirty_region);
153 } else {
154#if SPICE_INTERFACE_QXL_MINOR >= 1
155 spice_qxl_update_area_async(&qxl->ssd.qxl, surface_id, area,
156 clear_dirty_region, 0);
157#else
158 abort();
159#endif
160 }
aee32bf3
GH		 161}
162
5ff4e36c
AL		 163static void qxl_spice_destroy_surface_wait_complete(PCIQXLDevice *qxl,
164 uint32_t id)
aee32bf3 165{
14898cf6 166 qemu_mutex_lock(&qxl->track_lock);
14898cf6
GH		 167 qxl->guest_surfaces.cmds[id] = 0;
168 qxl->guest_surfaces.count--;
169 qemu_mutex_unlock(&qxl->track_lock);
aee32bf3
GH		 170}
171
5ff4e36c
AL		 172static void qxl_spice_destroy_surface_wait(PCIQXLDevice *qxl, uint32_t id,
173 qxl_async_io async)
174{
175 if (async) {
176#if SPICE_INTERFACE_QXL_MINOR < 1
177 abort();
178#else
179 spice_qxl_destroy_surface_async(&qxl->ssd.qxl, id,
180 (uint64_t)id);
181#endif
182 } else {
183 qxl->ssd.worker->destroy_surface_wait(qxl->ssd.worker, id);
184 qxl_spice_destroy_surface_wait_complete(qxl, id);
185 }
186}
187
3e16b9c5
AL		 188#if SPICE_INTERFACE_QXL_MINOR >= 1
189static void qxl_spice_flush_surfaces_async(PCIQXLDevice *qxl)
190{
191 spice_qxl_flush_surfaces_async(&qxl->ssd.qxl, 0);
192}
193#endif
194
aee32bf3
GH		 195void qxl_spice_loadvm_commands(PCIQXLDevice *qxl, struct QXLCommandExt *ext,
196 uint32_t count)
197{
198 qxl->ssd.worker->loadvm_commands(qxl->ssd.worker, ext, count);
199}
200
201void qxl_spice_oom(PCIQXLDevice *qxl)
202{
203 qxl->ssd.worker->oom(qxl->ssd.worker);
204}
205
206void qxl_spice_reset_memslots(PCIQXLDevice *qxl)
207{
208 qxl->ssd.worker->reset_memslots(qxl->ssd.worker);
209}
210
5ff4e36c 211static void qxl_spice_destroy_surfaces_complete(PCIQXLDevice *qxl)
aee32bf3 212{
14898cf6 213 qemu_mutex_lock(&qxl->track_lock);
14898cf6
GH		 214 memset(&qxl->guest_surfaces.cmds, 0, sizeof(qxl->guest_surfaces.cmds));
215 qxl->guest_surfaces.count = 0;
216 qemu_mutex_unlock(&qxl->track_lock);
aee32bf3
GH		 217}
218
5ff4e36c
AL		 219static void qxl_spice_destroy_surfaces(PCIQXLDevice *qxl, qxl_async_io async)
220{
221 if (async) {
222#if SPICE_INTERFACE_QXL_MINOR < 1
223 abort();
224#else
225 spice_qxl_destroy_surfaces_async(&qxl->ssd.qxl, 0);
226#endif
227 } else {
228 qxl->ssd.worker->destroy_surfaces(qxl->ssd.worker);
229 qxl_spice_destroy_surfaces_complete(qxl);
230 }
231}
232
aee32bf3
GH		 233void qxl_spice_reset_image_cache(PCIQXLDevice *qxl)
234{
235 qxl->ssd.worker->reset_image_cache(qxl->ssd.worker);
236}
237
238void qxl_spice_reset_cursor(PCIQXLDevice *qxl)
239{
240 qxl->ssd.worker->reset_cursor(qxl->ssd.worker);
241}
242
243
a19cbfb3
GH		 244static inline uint32_t msb_mask(uint32_t val)
245{
246 uint32_t mask;
247
248 do {
249 mask = ~(val - 1) & val;
250 val &= ~mask;
251 } while (mask < val);
252
253 return mask;
254}
255
256static ram_addr_t qxl_rom_size(void)
257{
258 uint32_t rom_size = sizeof(QXLRom) + sizeof(QXLModes) + sizeof(qxl_modes);
259 rom_size = MAX(rom_size, TARGET_PAGE_SIZE);
260 rom_size = msb_mask(rom_size * 2 - 1);
261 return rom_size;
262}
263
264static void init_qxl_rom(PCIQXLDevice *d)
265{
266 QXLRom *rom = qemu_get_ram_ptr(d->rom_offset);
267 QXLModes *modes = (QXLModes *)(rom + 1);
268 uint32_t ram_header_size;
269 uint32_t surface0_area_size;
270 uint32_t num_pages;
271 uint32_t fb, maxfb = 0;
272 int i;
273
274 memset(rom, 0, d->rom_size);
275
276 rom->magic = cpu_to_le32(QXL_ROM_MAGIC);
277 rom->id = cpu_to_le32(d->id);
278 rom->log_level = cpu_to_le32(d->guestdebug);
279 rom->modes_offset = cpu_to_le32(sizeof(QXLRom));
280
281 rom->slot_gen_bits = MEMSLOT_GENERATION_BITS;
282 rom->slot_id_bits = MEMSLOT_SLOT_BITS;
283 rom->slots_start = 1;
284 rom->slots_end = NUM_MEMSLOTS - 1;
285 rom->n_surfaces = cpu_to_le32(NUM_SURFACES);
286
287 modes->n_modes = cpu_to_le32(ARRAY_SIZE(qxl_modes));
288 for (i = 0; i < modes->n_modes; i++) {
289 fb = qxl_modes[i].y_res * qxl_modes[i].stride;
290 if (maxfb < fb) {
291 maxfb = fb;
292 }
293 modes->modes[i].id = cpu_to_le32(i);
294 modes->modes[i].x_res = cpu_to_le32(qxl_modes[i].x_res);
295 modes->modes[i].y_res = cpu_to_le32(qxl_modes[i].y_res);
296 modes->modes[i].bits = cpu_to_le32(qxl_modes[i].bits);
297 modes->modes[i].stride = cpu_to_le32(qxl_modes[i].stride);
298 modes->modes[i].x_mili = cpu_to_le32(qxl_modes[i].x_mili);
299 modes->modes[i].y_mili = cpu_to_le32(qxl_modes[i].y_mili);
300 modes->modes[i].orientation = cpu_to_le32(qxl_modes[i].orientation);
301 }
302 if (maxfb < VGA_RAM_SIZE && d->id == 0)
303 maxfb = VGA_RAM_SIZE;
304
305 ram_header_size = ALIGN(sizeof(QXLRam), 4096);
306 surface0_area_size = ALIGN(maxfb, 4096);
307 num_pages = d->vga.vram_size;
308 num_pages -= ram_header_size;
309 num_pages -= surface0_area_size;
310 num_pages = num_pages / TARGET_PAGE_SIZE;
311
312 rom->draw_area_offset = cpu_to_le32(0);
313 rom->surface0_area_size = cpu_to_le32(surface0_area_size);
314 rom->pages_offset = cpu_to_le32(surface0_area_size);
315 rom->num_pages = cpu_to_le32(num_pages);
316 rom->ram_header_offset = cpu_to_le32(d->vga.vram_size - ram_header_size);
317
318 d->shadow_rom = *rom;
319 d->rom = rom;
320 d->modes = modes;
321}
322
323static void init_qxl_ram(PCIQXLDevice *d)
324{
325 uint8_t *buf;
326 uint64_t *item;
327
328 buf = d->vga.vram_ptr;
329 d->ram = (QXLRam *)(buf + le32_to_cpu(d->shadow_rom.ram_header_offset));
330 d->ram->magic = cpu_to_le32(QXL_RAM_MAGIC);
331 d->ram->int_pending = cpu_to_le32(0);
332 d->ram->int_mask = cpu_to_le32(0);
333 SPICE_RING_INIT(&d->ram->cmd_ring);
334 SPICE_RING_INIT(&d->ram->cursor_ring);
335 SPICE_RING_INIT(&d->ram->release_ring);
336 SPICE_RING_PROD_ITEM(&d->ram->release_ring, item);
337 *item = 0;
338 qxl_ring_set_dirty(d);
339}
340
341/* can be called from spice server thread context */
342static void qxl_set_dirty(ram_addr_t addr, ram_addr_t end)
343{
344 while (addr < end) {
345 cpu_physical_memory_set_dirty(addr);
346 addr += TARGET_PAGE_SIZE;
347 }
348}
349
350static void qxl_rom_set_dirty(PCIQXLDevice *qxl)
351{
352 ram_addr_t addr = qxl->rom_offset;
353 qxl_set_dirty(addr, addr + qxl->rom_size);
354}
355
356/* called from spice server thread context only */
357static void qxl_ram_set_dirty(PCIQXLDevice *qxl, void *ptr)
358{
359 ram_addr_t addr = qxl->vga.vram_offset;
360 void *base = qxl->vga.vram_ptr;
361 intptr_t offset;
362
363 offset = ptr - base;
364 offset &= ~(TARGET_PAGE_SIZE-1);
365 assert(offset < qxl->vga.vram_size);
366 qxl_set_dirty(addr + offset, addr + offset + TARGET_PAGE_SIZE);
367}
368
369/* can be called from spice server thread context */
370static void qxl_ring_set_dirty(PCIQXLDevice *qxl)
371{
372 ram_addr_t addr = qxl->vga.vram_offset + qxl->shadow_rom.ram_header_offset;
373 ram_addr_t end = qxl->vga.vram_offset + qxl->vga.vram_size;
374 qxl_set_dirty(addr, end);
375}
376
377/*
378 * keep track of some command state, for savevm/loadvm.
379 * called from spice server thread context only
380 */
381static void qxl_track_command(PCIQXLDevice *qxl, struct QXLCommandExt *ext)
382{
383 switch (le32_to_cpu(ext->cmd.type)) {
384 case QXL_CMD_SURFACE:
385 {
386 QXLSurfaceCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id);
387 uint32_t id = le32_to_cpu(cmd->surface_id);
388 PANIC_ON(id >= NUM_SURFACES);
14898cf6 389 qemu_mutex_lock(&qxl->track_lock);
a19cbfb3
GH		 390 if (cmd->type == QXL_SURFACE_CMD_CREATE) {
391 qxl->guest_surfaces.cmds[id] = ext->cmd.data;
392 qxl->guest_surfaces.count++;
393 if (qxl->guest_surfaces.max < qxl->guest_surfaces.count)
394 qxl->guest_surfaces.max = qxl->guest_surfaces.count;
395 }
396 if (cmd->type == QXL_SURFACE_CMD_DESTROY) {
397 qxl->guest_surfaces.cmds[id] = 0;
398 qxl->guest_surfaces.count--;
399 }
14898cf6 400 qemu_mutex_unlock(&qxl->track_lock);
a19cbfb3
GH		 401 break;
402 }
403 case QXL_CMD_CURSOR:
404 {
405 QXLCursorCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id);
406 if (cmd->type == QXL_CURSOR_SET) {
407 qxl->guest_cursor = ext->cmd.data;
408 }
409 break;
410 }
411 }
412}
413
414/* spice display interface callbacks */
415
416static void interface_attach_worker(QXLInstance *sin, QXLWorker *qxl_worker)
417{
418 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
419
420 dprint(qxl, 1, "%s:\n", __FUNCTION__);
421 qxl->ssd.worker = qxl_worker;
422}
423
424static void interface_set_compression_level(QXLInstance *sin, int level)
425{
426 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
427
428 dprint(qxl, 1, "%s: %d\n", __FUNCTION__, level);
429 qxl->shadow_rom.compression_level = cpu_to_le32(level);
430 qxl->rom->compression_level = cpu_to_le32(level);
431 qxl_rom_set_dirty(qxl);
432}
433
434static void interface_set_mm_time(QXLInstance *sin, uint32_t mm_time)
435{
436 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
437
438 qxl->shadow_rom.mm_clock = cpu_to_le32(mm_time);
439 qxl->rom->mm_clock = cpu_to_le32(mm_time);
440 qxl_rom_set_dirty(qxl);
441}
442
443static void interface_get_init_info(QXLInstance *sin, QXLDevInitInfo *info)
444{
445 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
446
447 dprint(qxl, 1, "%s:\n", __FUNCTION__);
448 info->memslot_gen_bits = MEMSLOT_GENERATION_BITS;
449 info->memslot_id_bits = MEMSLOT_SLOT_BITS;
450 info->num_memslots = NUM_MEMSLOTS;
451 info->num_memslots_groups = NUM_MEMSLOTS_GROUPS;
452 info->internal_groupslot_id = 0;
453 info->qxl_ram_size = le32_to_cpu(qxl->shadow_rom.num_pages) << TARGET_PAGE_BITS;
454 info->n_surfaces = NUM_SURFACES;
455}
456
5b77870c
AL		 457static const char *qxl_mode_to_string(int mode)
458{
459 switch (mode) {
460 case QXL_MODE_COMPAT:
461 return "compat";
462 case QXL_MODE_NATIVE:
463 return "native";
464 case QXL_MODE_UNDEFINED:
465 return "undefined";
466 case QXL_MODE_VGA:
467 return "vga";
468 }
469 return "INVALID";
470}
471
8b92e298
AL		 472static const char *io_port_to_string(uint32_t io_port)
473{
474 if (io_port >= QXL_IO_RANGE_SIZE) {
475 return "out of range";
476 }
477 static const char *io_port_to_string[QXL_IO_RANGE_SIZE + 1] = {
478 [QXL_IO_NOTIFY_CMD] = "QXL_IO_NOTIFY_CMD",
479 [QXL_IO_NOTIFY_CURSOR] = "QXL_IO_NOTIFY_CURSOR",
480 [QXL_IO_UPDATE_AREA] = "QXL_IO_UPDATE_AREA",
481 [QXL_IO_UPDATE_IRQ] = "QXL_IO_UPDATE_IRQ",
482 [QXL_IO_NOTIFY_OOM] = "QXL_IO_NOTIFY_OOM",
483 [QXL_IO_RESET] = "QXL_IO_RESET",
484 [QXL_IO_SET_MODE] = "QXL_IO_SET_MODE",
485 [QXL_IO_LOG] = "QXL_IO_LOG",
486 [QXL_IO_MEMSLOT_ADD] = "QXL_IO_MEMSLOT_ADD",
487 [QXL_IO_MEMSLOT_DEL] = "QXL_IO_MEMSLOT_DEL",
488 [QXL_IO_DETACH_PRIMARY] = "QXL_IO_DETACH_PRIMARY",
489 [QXL_IO_ATTACH_PRIMARY] = "QXL_IO_ATTACH_PRIMARY",
490 [QXL_IO_CREATE_PRIMARY] = "QXL_IO_CREATE_PRIMARY",
491 [QXL_IO_DESTROY_PRIMARY] = "QXL_IO_DESTROY_PRIMARY",
492 [QXL_IO_DESTROY_SURFACE_WAIT] = "QXL_IO_DESTROY_SURFACE_WAIT",
493 [QXL_IO_DESTROY_ALL_SURFACES] = "QXL_IO_DESTROY_ALL_SURFACES",
494#if SPICE_INTERFACE_QXL_MINOR >= 1
495 [QXL_IO_UPDATE_AREA_ASYNC] = "QXL_IO_UPDATE_AREA_ASYNC",
496 [QXL_IO_MEMSLOT_ADD_ASYNC] = "QXL_IO_MEMSLOT_ADD_ASYNC",
497 [QXL_IO_CREATE_PRIMARY_ASYNC] = "QXL_IO_CREATE_PRIMARY_ASYNC",
498 [QXL_IO_DESTROY_PRIMARY_ASYNC] = "QXL_IO_DESTROY_PRIMARY_ASYNC",
499 [QXL_IO_DESTROY_SURFACE_ASYNC] = "QXL_IO_DESTROY_SURFACE_ASYNC",
500 [QXL_IO_DESTROY_ALL_SURFACES_ASYNC]
501 = "QXL_IO_DESTROY_ALL_SURFACES_ASYNC",
502 [QXL_IO_FLUSH_SURFACES_ASYNC] = "QXL_IO_FLUSH_SURFACES_ASYNC",
503 [QXL_IO_FLUSH_RELEASE] = "QXL_IO_FLUSH_RELEASE",
504#endif
505 };
506 return io_port_to_string[io_port];
507}
508
a19cbfb3
GH		 509/* called from spice server thread context only */
510static int interface_get_command(QXLInstance *sin, struct QXLCommandExt *ext)
511{
512 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
513 SimpleSpiceUpdate *update;
514 QXLCommandRing *ring;
515 QXLCommand *cmd;
e0c64d08 516 int notify, ret;
a19cbfb3
GH		 517
518 switch (qxl->mode) {
519 case QXL_MODE_VGA:
520 dprint(qxl, 2, "%s: vga\n", __FUNCTION__);
e0c64d08
GH		 521 ret = false;
522 qemu_mutex_lock(&qxl->ssd.lock);
523 if (qxl->ssd.update != NULL) {
524 update = qxl->ssd.update;
525 qxl->ssd.update = NULL;
526 *ext = update->ext;
527 ret = true;
a19cbfb3 528 }
e0c64d08 529 qemu_mutex_unlock(&qxl->ssd.lock);
212496c9 530 if (ret) {
5b77870c 531 dprint(qxl, 2, "%s %s\n", __FUNCTION__, qxl_mode_to_string(qxl->mode));
212496c9
AL		 532 qxl_log_command(qxl, "vga", ext);
533 }
e0c64d08 534 return ret;
a19cbfb3
GH		 535 case QXL_MODE_COMPAT:
536 case QXL_MODE_NATIVE:
537 case QXL_MODE_UNDEFINED:
5b77870c 538 dprint(qxl, 4, "%s: %s\n", __FUNCTION__, qxl_mode_to_string(qxl->mode));
a19cbfb3
GH		 539 ring = &qxl->ram->cmd_ring;
540 if (SPICE_RING_IS_EMPTY(ring)) {
541 return false;
542 }
5b77870c 543 dprint(qxl, 2, "%s: %s\n", __FUNCTION__, qxl_mode_to_string(qxl->mode));
a19cbfb3
GH		 544 SPICE_RING_CONS_ITEM(ring, cmd);
545 ext->cmd = *cmd;
546 ext->group_id = MEMSLOT_GROUP_GUEST;
547 ext->flags = qxl->cmdflags;
548 SPICE_RING_POP(ring, notify);
549 qxl_ring_set_dirty(qxl);
550 if (notify) {
551 qxl_send_events(qxl, QXL_INTERRUPT_DISPLAY);
552 }
553 qxl->guest_primary.commands++;
554 qxl_track_command(qxl, ext);
555 qxl_log_command(qxl, "cmd", ext);
556 return true;
557 default:
558 return false;
559 }
560}
561
562/* called from spice server thread context only */
563static int interface_req_cmd_notification(QXLInstance *sin)
564{
565 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
566 int wait = 1;
567
568 switch (qxl->mode) {
569 case QXL_MODE_COMPAT:
570 case QXL_MODE_NATIVE:
571 case QXL_MODE_UNDEFINED:
572 SPICE_RING_CONS_WAIT(&qxl->ram->cmd_ring, wait);
573 qxl_ring_set_dirty(qxl);
574 break;
575 default:
576 /* nothing */
577 break;
578 }
579 return wait;
580}
581
582/* called from spice server thread context only */
583static inline void qxl_push_free_res(PCIQXLDevice *d, int flush)
584{
585 QXLReleaseRing *ring = &d->ram->release_ring;
586 uint64_t *item;
587 int notify;
588
589#define QXL_FREE_BUNCH_SIZE 32
590
591 if (ring->prod - ring->cons + 1 == ring->num_items) {
592 /* ring full -- can't push */
593 return;
594 }
595 if (!flush && d->oom_running) {
596 /* collect everything from oom handler before pushing */
597 return;
598 }
599 if (!flush && d->num_free_res < QXL_FREE_BUNCH_SIZE) {
600 /* collect a bit more before pushing */
601 return;
602 }
603
604 SPICE_RING_PUSH(ring, notify);
605 dprint(d, 2, "free: push %d items, notify %s, ring %d/%d [%d,%d]\n",
606 d->num_free_res, notify ? "yes" : "no",
607 ring->prod - ring->cons, ring->num_items,
608 ring->prod, ring->cons);
609 if (notify) {
610 qxl_send_events(d, QXL_INTERRUPT_DISPLAY);
611 }
612 SPICE_RING_PROD_ITEM(ring, item);
613 *item = 0;
614 d->num_free_res = 0;
615 d->last_release = NULL;
616 qxl_ring_set_dirty(d);
617}
618
619/* called from spice server thread context only */
620static void interface_release_resource(QXLInstance *sin,
621 struct QXLReleaseInfoExt ext)
622{
623 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
624 QXLReleaseRing *ring;
625 uint64_t *item, id;
626
627 if (ext.group_id == MEMSLOT_GROUP_HOST) {
628 /* host group -> vga mode update request */
629 qemu_spice_destroy_update(&qxl->ssd, (void*)ext.info->id);
630 return;
631 }
632
633 /*
634 * ext->info points into guest-visible memory
635 * pci bar 0, $command.release_info
636 */
637 ring = &qxl->ram->release_ring;
638 SPICE_RING_PROD_ITEM(ring, item);
639 if (*item == 0) {
640 /* stick head into the ring */
641 id = ext.info->id;
642 ext.info->next = 0;
643 qxl_ram_set_dirty(qxl, &ext.info->next);
644 *item = id;
645 qxl_ring_set_dirty(qxl);
646 } else {
647 /* append item to the list */
648 qxl->last_release->next = ext.info->id;
649 qxl_ram_set_dirty(qxl, &qxl->last_release->next);
650 ext.info->next = 0;
651 qxl_ram_set_dirty(qxl, &ext.info->next);
652 }
653 qxl->last_release = ext.info;
654 qxl->num_free_res++;
655 dprint(qxl, 3, "%4d\r", qxl->num_free_res);
656 qxl_push_free_res(qxl, 0);
657}
658
659/* called from spice server thread context only */
660static int interface_get_cursor_command(QXLInstance *sin, struct QXLCommandExt *ext)
661{
662 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
663 QXLCursorRing *ring;
664 QXLCommand *cmd;
665 int notify;
666
667 switch (qxl->mode) {
668 case QXL_MODE_COMPAT:
669 case QXL_MODE_NATIVE:
670 case QXL_MODE_UNDEFINED:
671 ring = &qxl->ram->cursor_ring;
672 if (SPICE_RING_IS_EMPTY(ring)) {
673 return false;
674 }
675 SPICE_RING_CONS_ITEM(ring, cmd);
676 ext->cmd = *cmd;
677 ext->group_id = MEMSLOT_GROUP_GUEST;
678 ext->flags = qxl->cmdflags;
679 SPICE_RING_POP(ring, notify);
680 qxl_ring_set_dirty(qxl);
681 if (notify) {
682 qxl_send_events(qxl, QXL_INTERRUPT_CURSOR);
683 }
684 qxl->guest_primary.commands++;
685 qxl_track_command(qxl, ext);
686 qxl_log_command(qxl, "csr", ext);
687 if (qxl->id == 0) {
688 qxl_render_cursor(qxl, ext);
689 }
690 return true;
691 default:
692 return false;
693 }
694}
695
696/* called from spice server thread context only */
697static int interface_req_cursor_notification(QXLInstance *sin)
698{
699 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
700 int wait = 1;
701
702 switch (qxl->mode) {
703 case QXL_MODE_COMPAT:
704 case QXL_MODE_NATIVE:
705 case QXL_MODE_UNDEFINED:
706 SPICE_RING_CONS_WAIT(&qxl->ram->cursor_ring, wait);
707 qxl_ring_set_dirty(qxl);
708 break;
709 default:
710 /* nothing */
711 break;
712 }
713 return wait;
714}
715
716/* called from spice server thread context */
717static void interface_notify_update(QXLInstance *sin, uint32_t update_id)
718{
719 fprintf(stderr, "%s: abort()\n", __FUNCTION__);
720 abort();
721}
722
723/* called from spice server thread context only */
724static int interface_flush_resources(QXLInstance *sin)
725{
726 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
727 int ret;
728
729 dprint(qxl, 1, "free: guest flush (have %d)\n", qxl->num_free_res);
730 ret = qxl->num_free_res;
731 if (ret) {
732 qxl_push_free_res(qxl, 1);
733 }
734 return ret;
735}
736
5ff4e36c
AL		 737static void qxl_create_guest_primary_complete(PCIQXLDevice *d);
738
739#if SPICE_INTERFACE_QXL_MINOR >= 1
740
741/* called from spice server thread context only */
742static void interface_async_complete(QXLInstance *sin, uint64_t cookie)
743{
744 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
745 uint32_t current_async;
746
747 qemu_mutex_lock(&qxl->async_lock);
748 current_async = qxl->current_async;
749 qxl->current_async = QXL_UNDEFINED_IO;
750 qemu_mutex_unlock(&qxl->async_lock);
751
752 dprint(qxl, 2, "async_complete: %d (%ld) done\n", current_async, cookie);
753 switch (current_async) {
754 case QXL_IO_CREATE_PRIMARY_ASYNC:
755 qxl_create_guest_primary_complete(qxl);
756 break;
757 case QXL_IO_DESTROY_ALL_SURFACES_ASYNC:
758 qxl_spice_destroy_surfaces_complete(qxl);
759 break;
760 case QXL_IO_DESTROY_SURFACE_ASYNC:
761 qxl_spice_destroy_surface_wait_complete(qxl, (uint32_t)cookie);
762 break;
763 }
764 qxl_send_events(qxl, QXL_INTERRUPT_IO_CMD);
765}
766
767#endif
768
a19cbfb3
GH		 769static const QXLInterface qxl_interface = {
770 .base.type = SPICE_INTERFACE_QXL,
771 .base.description = "qxl gpu",
772 .base.major_version = SPICE_INTERFACE_QXL_MAJOR,
773 .base.minor_version = SPICE_INTERFACE_QXL_MINOR,
774
775 .attache_worker = interface_attach_worker,
776 .set_compression_level = interface_set_compression_level,
777 .set_mm_time = interface_set_mm_time,
778 .get_init_info = interface_get_init_info,
779
780 /* the callbacks below are called from spice server thread context */
781 .get_command = interface_get_command,
782 .req_cmd_notification = interface_req_cmd_notification,
783 .release_resource = interface_release_resource,
784 .get_cursor_command = interface_get_cursor_command,
785 .req_cursor_notification = interface_req_cursor_notification,
786 .notify_update = interface_notify_update,
787 .flush_resources = interface_flush_resources,
5ff4e36c
AL		 788#if SPICE_INTERFACE_QXL_MINOR >= 1
789 .async_complete = interface_async_complete,
790#endif
a19cbfb3
GH		 791};
792
793static void qxl_enter_vga_mode(PCIQXLDevice *d)
794{
795 if (d->mode == QXL_MODE_VGA) {
796 return;
797 }
798 dprint(d, 1, "%s\n", __FUNCTION__);
799 qemu_spice_create_host_primary(&d->ssd);
800 d->mode = QXL_MODE_VGA;
801 memset(&d->ssd.dirty, 0, sizeof(d->ssd.dirty));
802}
803
804static void qxl_exit_vga_mode(PCIQXLDevice *d)
805{
806 if (d->mode != QXL_MODE_VGA) {
807 return;
808 }
809 dprint(d, 1, "%s\n", __FUNCTION__);
5ff4e36c 810 qxl_destroy_primary(d, QXL_SYNC);
a19cbfb3
GH		 811}
812
813static void qxl_set_irq(PCIQXLDevice *d)
814{
815 uint32_t pending = le32_to_cpu(d->ram->int_pending);
816 uint32_t mask = le32_to_cpu(d->ram->int_mask);
817 int level = !!(pending & mask);
818 qemu_set_irq(d->pci.irq[0], level);
819 qxl_ring_set_dirty(d);
820}
821
822static void qxl_write_config(PCIDevice *d, uint32_t address,
823 uint32_t val, int len)
824{
825 PCIQXLDevice *qxl = DO_UPCAST(PCIQXLDevice, pci, d);
826 VGACommonState *vga = &qxl->vga;
827
828 vga_dirty_log_stop(vga);
829 pci_default_write_config(d, address, val, len);
830 if (vga->map_addr && qxl->pci.io_regions[0].addr == -1) {
831 vga->map_addr = 0;
832 }
833 vga_dirty_log_start(vga);
834}
835
836static void qxl_check_state(PCIQXLDevice *d)
837{
838 QXLRam *ram = d->ram;
839
840 assert(SPICE_RING_IS_EMPTY(&ram->cmd_ring));
841 assert(SPICE_RING_IS_EMPTY(&ram->cursor_ring));
842}
843
844static void qxl_reset_state(PCIQXLDevice *d)
845{
846 QXLRam *ram = d->ram;
847 QXLRom *rom = d->rom;
848
8927cfbb
YH		 849 assert(!d->ssd.running || SPICE_RING_IS_EMPTY(&ram->cmd_ring));
850 assert(!d->ssd.running || SPICE_RING_IS_EMPTY(&ram->cursor_ring));
a19cbfb3
GH		 851 d->shadow_rom.update_id = cpu_to_le32(0);
852 *rom = d->shadow_rom;
853 qxl_rom_set_dirty(d);
854 init_qxl_ram(d);
855 d->num_free_res = 0;
856 d->last_release = NULL;
857 memset(&d->ssd.dirty, 0, sizeof(d->ssd.dirty));
858}
859
860static void qxl_soft_reset(PCIQXLDevice *d)
861{
862 dprint(d, 1, "%s:\n", __FUNCTION__);
863 qxl_check_state(d);
864
865 if (d->id == 0) {
866 qxl_enter_vga_mode(d);
867 } else {
868 d->mode = QXL_MODE_UNDEFINED;
869 }
870}
871
872static void qxl_hard_reset(PCIQXLDevice *d, int loadvm)
873{
874 dprint(d, 1, "%s: start%s\n", __FUNCTION__,
875 loadvm ? " (loadvm)" : "");
876
aee32bf3
GH		 877 qxl_spice_reset_cursor(d);
878 qxl_spice_reset_image_cache(d);
a19cbfb3
GH		 879 qxl_reset_surfaces(d);
880 qxl_reset_memslots(d);
881
882 /* pre loadvm reset must not touch QXLRam. This lives in
883 * device memory, is migrated together with RAM and thus
884 * already loaded at this point */
885 if (!loadvm) {
886 qxl_reset_state(d);
887 }
888 qemu_spice_create_host_memslot(&d->ssd);
889 qxl_soft_reset(d);
890
891 dprint(d, 1, "%s: done\n", __FUNCTION__);
892}
893
894static void qxl_reset_handler(DeviceState *dev)
895{
896 PCIQXLDevice *d = DO_UPCAST(PCIQXLDevice, pci.qdev, dev);
897 qxl_hard_reset(d, 0);
898}
899
900static void qxl_vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
901{
902 VGACommonState *vga = opaque;
903 PCIQXLDevice *qxl = container_of(vga, PCIQXLDevice, vga);
904
905 if (qxl->mode != QXL_MODE_VGA) {
906 dprint(qxl, 1, "%s\n", __FUNCTION__);
5ff4e36c 907 qxl_destroy_primary(qxl, QXL_SYNC);
a19cbfb3
GH		 908 qxl_soft_reset(qxl);
909 }
910 vga_ioport_write(opaque, addr, val);
911}
912
5ff4e36c
AL		 913static void qxl_add_memslot(PCIQXLDevice *d, uint32_t slot_id, uint64_t delta,
914 qxl_async_io async)
a19cbfb3
GH		 915{
916 static const int regions[] = {
917 QXL_RAM_RANGE_INDEX,
918 QXL_VRAM_RANGE_INDEX,
919 };
920 uint64_t guest_start;
921 uint64_t guest_end;
922 int pci_region;
923 pcibus_t pci_start;
924 pcibus_t pci_end;
925 intptr_t virt_start;
926 QXLDevMemSlot memslot;
927 int i;
928
929 guest_start = le64_to_cpu(d->guest_slots[slot_id].slot.mem_start);
930 guest_end = le64_to_cpu(d->guest_slots[slot_id].slot.mem_end);
931
932 dprint(d, 1, "%s: slot %d: guest phys 0x%" PRIx64 " - 0x%" PRIx64 "\n",
933 __FUNCTION__, slot_id,
934 guest_start, guest_end);
935
936 PANIC_ON(slot_id >= NUM_MEMSLOTS);
937 PANIC_ON(guest_start > guest_end);
938
939 for (i = 0; i < ARRAY_SIZE(regions); i++) {
940 pci_region = regions[i];
941 pci_start = d->pci.io_regions[pci_region].addr;
942 pci_end = pci_start + d->pci.io_regions[pci_region].size;
943 /* mapped? */
944 if (pci_start == -1) {
945 continue;
946 }
947 /* start address in range ? */
948 if (guest_start < pci_start || guest_start > pci_end) {
949 continue;
950 }
951 /* end address in range ? */
952 if (guest_end > pci_end) {
953 continue;
954 }
955 /* passed */
956 break;
957 }
958 PANIC_ON(i == ARRAY_SIZE(regions)); /* finished loop without match */
959
960 switch (pci_region) {
961 case QXL_RAM_RANGE_INDEX:
962 virt_start = (intptr_t)qemu_get_ram_ptr(d->vga.vram_offset);
963 break;
964 case QXL_VRAM_RANGE_INDEX:
965 virt_start = (intptr_t)qemu_get_ram_ptr(d->vram_offset);
966 break;
967 default:
968 /* should not happen */
969 abort();
970 }
971
972 memslot.slot_id = slot_id;
973 memslot.slot_group_id = MEMSLOT_GROUP_GUEST; /* guest group */
974 memslot.virt_start = virt_start + (guest_start - pci_start);
975 memslot.virt_end = virt_start + (guest_end - pci_start);
976 memslot.addr_delta = memslot.virt_start - delta;
977 memslot.generation = d->rom->slot_generation = 0;
978 qxl_rom_set_dirty(d);
979
980 dprint(d, 1, "%s: slot %d: host virt 0x%" PRIx64 " - 0x%" PRIx64 "\n",
981 __FUNCTION__, memslot.slot_id,
982 memslot.virt_start, memslot.virt_end);
983
5ff4e36c 984 qemu_spice_add_memslot(&d->ssd, &memslot, async);
a19cbfb3
GH		 985 d->guest_slots[slot_id].ptr = (void*)memslot.virt_start;
986 d->guest_slots[slot_id].size = memslot.virt_end - memslot.virt_start;
987 d->guest_slots[slot_id].delta = delta;
988 d->guest_slots[slot_id].active = 1;
989}
990
991static void qxl_del_memslot(PCIQXLDevice *d, uint32_t slot_id)
992{
993 dprint(d, 1, "%s: slot %d\n", __FUNCTION__, slot_id);
5c59d118 994 qemu_spice_del_memslot(&d->ssd, MEMSLOT_GROUP_HOST, slot_id);
a19cbfb3
GH		 995 d->guest_slots[slot_id].active = 0;
996}
997
998static void qxl_reset_memslots(PCIQXLDevice *d)
999{
1000 dprint(d, 1, "%s:\n", __FUNCTION__);
aee32bf3 1001 qxl_spice_reset_memslots(d);
a19cbfb3
GH		 1002 memset(&d->guest_slots, 0, sizeof(d->guest_slots));
1003}
1004
1005static void qxl_reset_surfaces(PCIQXLDevice *d)
1006{
1007 dprint(d, 1, "%s:\n", __FUNCTION__);
1008 d->mode = QXL_MODE_UNDEFINED;
5ff4e36c 1009 qxl_spice_destroy_surfaces(d, QXL_SYNC);
a19cbfb3
GH		 1010}
1011
1012/* called from spice server thread context only */
1013void *qxl_phys2virt(PCIQXLDevice *qxl, QXLPHYSICAL pqxl, int group_id)
1014{
1015 uint64_t phys = le64_to_cpu(pqxl);
1016 uint32_t slot = (phys >> (64 - 8)) & 0xff;
1017 uint64_t offset = phys & 0xffffffffffff;
1018
1019 switch (group_id) {
1020 case MEMSLOT_GROUP_HOST:
1021 return (void*)offset;
1022 case MEMSLOT_GROUP_GUEST:
1023 PANIC_ON(slot > NUM_MEMSLOTS);
1024 PANIC_ON(!qxl->guest_slots[slot].active);
1025 PANIC_ON(offset < qxl->guest_slots[slot].delta);
1026 offset -= qxl->guest_slots[slot].delta;
1027 PANIC_ON(offset > qxl->guest_slots[slot].size)
1028 return qxl->guest_slots[slot].ptr + offset;
1029 default:
1030 PANIC_ON(1);
1031 }
1032}
1033
5ff4e36c
AL		 1034static void qxl_create_guest_primary_complete(PCIQXLDevice *qxl)
1035{
1036 /* for local rendering */
1037 qxl_render_resize(qxl);
1038}
1039
1040static void qxl_create_guest_primary(PCIQXLDevice *qxl, int loadvm,
1041 qxl_async_io async)
a19cbfb3
GH		 1042{
1043 QXLDevSurfaceCreate surface;
1044 QXLSurfaceCreate *sc = &qxl->guest_primary.surface;
1045
1046 assert(qxl->mode != QXL_MODE_NATIVE);
1047 qxl_exit_vga_mode(qxl);
1048
1049 dprint(qxl, 1, "%s: %dx%d\n", __FUNCTION__,
1050 le32_to_cpu(sc->width), le32_to_cpu(sc->height));
1051
1052 surface.format = le32_to_cpu(sc->format);
1053 surface.height = le32_to_cpu(sc->height);
1054 surface.mem = le64_to_cpu(sc->mem);
1055 surface.position = le32_to_cpu(sc->position);
1056 surface.stride = le32_to_cpu(sc->stride);
1057 surface.width = le32_to_cpu(sc->width);
1058 surface.type = le32_to_cpu(sc->type);
1059 surface.flags = le32_to_cpu(sc->flags);
1060
1061 surface.mouse_mode = true;
1062 surface.group_id = MEMSLOT_GROUP_GUEST;
1063 if (loadvm) {
1064 surface.flags |= QXL_SURF_FLAG_KEEP_DATA;
1065 }
1066
1067 qxl->mode = QXL_MODE_NATIVE;
1068 qxl->cmdflags = 0;
5ff4e36c 1069 qemu_spice_create_primary_surface(&qxl->ssd, 0, &surface, async);
a19cbfb3 1070
5ff4e36c
AL		 1071 if (async == QXL_SYNC) {
1072 qxl_create_guest_primary_complete(qxl);
1073 }
a19cbfb3
GH		 1074}
1075
5ff4e36c
AL		 1076/* return 1 if surface destoy was initiated (in QXL_ASYNC case) or
1077 * done (in QXL_SYNC case), 0 otherwise. */
1078static int qxl_destroy_primary(PCIQXLDevice *d, qxl_async_io async)
a19cbfb3
GH		 1079{
1080 if (d->mode == QXL_MODE_UNDEFINED) {
5ff4e36c 1081 return 0;
a19cbfb3
GH		 1082 }
1083
1084 dprint(d, 1, "%s\n", __FUNCTION__);
1085
1086 d->mode = QXL_MODE_UNDEFINED;
5ff4e36c
AL		 1087 qemu_spice_destroy_primary_surface(&d->ssd, 0, async);
1088 return 1;
a19cbfb3
GH		 1089}
1090
1091static void qxl_set_mode(PCIQXLDevice *d, int modenr, int loadvm)
1092{
1093 pcibus_t start = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr;
1094 pcibus_t end = d->pci.io_regions[QXL_RAM_RANGE_INDEX].size + start;
1095 QXLMode *mode = d->modes->modes + modenr;
1096 uint64_t devmem = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr;
1097 QXLMemSlot slot = {
1098 .mem_start = start,
1099 .mem_end = end
1100 };
1101 QXLSurfaceCreate surface = {
1102 .width = mode->x_res,
1103 .height = mode->y_res,
1104 .stride = -mode->x_res * 4,
1105 .format = SPICE_SURFACE_FMT_32_xRGB,
1106 .flags = loadvm ? QXL_SURF_FLAG_KEEP_DATA : 0,
1107 .mouse_mode = true,
1108 .mem = devmem + d->shadow_rom.draw_area_offset,
1109 };
1110
1111 dprint(d, 1, "%s: mode %d [ %d x %d @ %d bpp devmem 0x%lx ]\n", __FUNCTION__,
1112 modenr, mode->x_res, mode->y_res, mode->bits, devmem);
1113 if (!loadvm) {
1114 qxl_hard_reset(d, 0);
1115 }
1116
1117 d->guest_slots[0].slot = slot;
5ff4e36c 1118 qxl_add_memslot(d, 0, devmem, QXL_SYNC);
a19cbfb3
GH		 1119
1120 d->guest_primary.surface = surface;
5ff4e36c 1121 qxl_create_guest_primary(d, 0, QXL_SYNC);
a19cbfb3
GH		 1122
1123 d->mode = QXL_MODE_COMPAT;
1124 d->cmdflags = QXL_COMMAND_FLAG_COMPAT;
1125#ifdef QXL_COMMAND_FLAG_COMPAT_16BPP /* new in spice 0.6.1 */
1126 if (mode->bits == 16) {
1127 d->cmdflags |= QXL_COMMAND_FLAG_COMPAT_16BPP;
1128 }
1129#endif
1130 d->shadow_rom.mode = cpu_to_le32(modenr);
1131 d->rom->mode = cpu_to_le32(modenr);
1132 qxl_rom_set_dirty(d);
1133}
1134
1135static void ioport_write(void *opaque, uint32_t addr, uint32_t val)
1136{
1137 PCIQXLDevice *d = opaque;
1138 uint32_t io_port = addr - d->io_base;
5ff4e36c
AL		 1139 qxl_async_io async = QXL_SYNC;
1140#if SPICE_INTERFACE_QXL_MINOR >= 1
1141 uint32_t orig_io_port = io_port;
1142#endif
a19cbfb3
GH		 1143
1144 switch (io_port) {
1145 case QXL_IO_RESET:
1146 case QXL_IO_SET_MODE:
1147 case QXL_IO_MEMSLOT_ADD:
1148 case QXL_IO_MEMSLOT_DEL:
1149 case QXL_IO_CREATE_PRIMARY:
81144d1a 1150 case QXL_IO_UPDATE_IRQ:
a3d14054 1151 case QXL_IO_LOG:
5ff4e36c
AL		 1152#if SPICE_INTERFACE_QXL_MINOR >= 1
1153 case QXL_IO_MEMSLOT_ADD_ASYNC:
1154 case QXL_IO_CREATE_PRIMARY_ASYNC:
1155#endif
a19cbfb3
GH		 1156 break;
1157 default:
e21a298a 1158 if (d->mode != QXL_MODE_VGA) {
a19cbfb3 1159 break;
e21a298a 1160 }
8b92e298
AL		 1161 dprint(d, 1, "%s: unexpected port 0x%x (%s) in vga mode\n",
1162 __func__, io_port, io_port_to_string(io_port));
5ff4e36c
AL		 1163#if SPICE_INTERFACE_QXL_MINOR >= 1
1164 /* be nice to buggy guest drivers */
1165 if (io_port >= QXL_IO_UPDATE_AREA_ASYNC &&
1166 io_port <= QXL_IO_DESTROY_ALL_SURFACES_ASYNC) {
1167 qxl_send_events(d, QXL_INTERRUPT_IO_CMD);
1168 }
1169#endif
a19cbfb3
GH		 1170 return;
1171 }
1172
5ff4e36c
AL		 1173#if SPICE_INTERFACE_QXL_MINOR >= 1
1174 /* we change the io_port to avoid ifdeffery in the main switch */
1175 orig_io_port = io_port;
1176 switch (io_port) {
1177 case QXL_IO_UPDATE_AREA_ASYNC:
1178 io_port = QXL_IO_UPDATE_AREA;
1179 goto async_common;
1180 case QXL_IO_MEMSLOT_ADD_ASYNC:
1181 io_port = QXL_IO_MEMSLOT_ADD;
1182 goto async_common;
1183 case QXL_IO_CREATE_PRIMARY_ASYNC:
1184 io_port = QXL_IO_CREATE_PRIMARY;
1185 goto async_common;
1186 case QXL_IO_DESTROY_PRIMARY_ASYNC:
1187 io_port = QXL_IO_DESTROY_PRIMARY;
1188 goto async_common;
1189 case QXL_IO_DESTROY_SURFACE_ASYNC:
1190 io_port = QXL_IO_DESTROY_SURFACE_WAIT;
1191 goto async_common;
1192 case QXL_IO_DESTROY_ALL_SURFACES_ASYNC:
1193 io_port = QXL_IO_DESTROY_ALL_SURFACES;
3e16b9c5
AL		 1194 goto async_common;
1195 case QXL_IO_FLUSH_SURFACES_ASYNC:
5ff4e36c
AL		 1196async_common:
1197 async = QXL_ASYNC;
1198 qemu_mutex_lock(&d->async_lock);
1199 if (d->current_async != QXL_UNDEFINED_IO) {
1200 qxl_guest_bug(d, "%d async started before last (%d) complete",
1201 io_port, d->current_async);
1202 qemu_mutex_unlock(&d->async_lock);
1203 return;
1204 }
1205 d->current_async = orig_io_port;
1206 qemu_mutex_unlock(&d->async_lock);
1207 dprint(d, 2, "start async %d (%d)\n", io_port, val);
1208 break;
1209 default:
1210 break;
1211 }
1212#endif
1213
a19cbfb3
GH		 1214 switch (io_port) {
1215 case QXL_IO_UPDATE_AREA:
1216 {
1217 QXLRect update = d->ram->update_area;
aee32bf3 1218 qxl_spice_update_area(d, d->ram->update_surface,
5ff4e36c 1219 &update, NULL, 0, 0, async);
a19cbfb3
GH		 1220 break;
1221 }
1222 case QXL_IO_NOTIFY_CMD:
5c59d118 1223 qemu_spice_wakeup(&d->ssd);
a19cbfb3
GH		 1224 break;
1225 case QXL_IO_NOTIFY_CURSOR:
5c59d118 1226 qemu_spice_wakeup(&d->ssd);
a19cbfb3
GH		 1227 break;
1228 case QXL_IO_UPDATE_IRQ:
1229 qxl_set_irq(d);
1230 break;
1231 case QXL_IO_NOTIFY_OOM:
1232 if (!SPICE_RING_IS_EMPTY(&d->ram->release_ring)) {
1233 break;
1234 }
1235 pthread_yield();
1236 if (!SPICE_RING_IS_EMPTY(&d->ram->release_ring)) {
1237 break;
1238 }
1239 d->oom_running = 1;
aee32bf3 1240 qxl_spice_oom(d);
a19cbfb3
GH		 1241 d->oom_running = 0;
1242 break;
1243 case QXL_IO_SET_MODE:
1244 dprint(d, 1, "QXL_SET_MODE %d\n", val);
1245 qxl_set_mode(d, val, 0);
1246 break;
1247 case QXL_IO_LOG:
1248 if (d->guestdebug) {
6ebebb55
AL		 1249 fprintf(stderr, "qxl/guest-%d: %ld: %s", d->id,
1250 qemu_get_clock_ns(vm_clock), d->ram->log_buf);
a19cbfb3
GH		 1251 }
1252 break;
1253 case QXL_IO_RESET:
1254 dprint(d, 1, "QXL_IO_RESET\n");
1255 qxl_hard_reset(d, 0);
1256 break;
1257 case QXL_IO_MEMSLOT_ADD:
2bce0400
GH		 1258 if (val >= NUM_MEMSLOTS) {
1259 qxl_guest_bug(d, "QXL_IO_MEMSLOT_ADD: val out of range");
1260 break;
1261 }
1262 if (d->guest_slots[val].active) {
1263 qxl_guest_bug(d, "QXL_IO_MEMSLOT_ADD: memory slot already active");
1264 break;
1265 }
a19cbfb3 1266 d->guest_slots[val].slot = d->ram->mem_slot;
5ff4e36c 1267 qxl_add_memslot(d, val, 0, async);
a19cbfb3
GH		 1268 break;
1269 case QXL_IO_MEMSLOT_DEL:
2bce0400
GH		 1270 if (val >= NUM_MEMSLOTS) {
1271 qxl_guest_bug(d, "QXL_IO_MEMSLOT_DEL: val out of range");
1272 break;
1273 }
a19cbfb3
GH		 1274 qxl_del_memslot(d, val);
1275 break;
1276 case QXL_IO_CREATE_PRIMARY:
2bce0400 1277 if (val != 0) {
5ff4e36c
AL		 1278 qxl_guest_bug(d, "QXL_IO_CREATE_PRIMARY (async=%d): val != 0",
1279 async);
1280 goto cancel_async;
2bce0400 1281 }
5ff4e36c 1282 dprint(d, 1, "QXL_IO_CREATE_PRIMARY async=%d\n", async);
a19cbfb3 1283 d->guest_primary.surface = d->ram->create_surface;
5ff4e36c 1284 qxl_create_guest_primary(d, 0, async);
a19cbfb3
GH		 1285 break;
1286 case QXL_IO_DESTROY_PRIMARY:
2bce0400 1287 if (val != 0) {
5ff4e36c
AL		 1288 qxl_guest_bug(d, "QXL_IO_DESTROY_PRIMARY (async=%d): val != 0",
1289 async);
1290 goto cancel_async;
1291 }
1292 dprint(d, 1, "QXL_IO_DESTROY_PRIMARY (async=%d) (%s)\n", async,
1293 qxl_mode_to_string(d->mode));
1294 if (!qxl_destroy_primary(d, async)) {
1295 dprint(d, 1, "QXL_IO_DESTROY_PRIMARY_ASYNC in %s, ignored\n",
1296 qxl_mode_to_string(d->mode));
1297 goto cancel_async;
2bce0400 1298 }
a19cbfb3
GH		 1299 break;
1300 case QXL_IO_DESTROY_SURFACE_WAIT:
5ff4e36c
AL		 1301 if (val >= NUM_SURFACES) {
1302 qxl_guest_bug(d, "QXL_IO_DESTROY_SURFACE (async=%d):"
1303 "%d >= NUM_SURFACES", async, val);
1304 goto cancel_async;
1305 }
1306 qxl_spice_destroy_surface_wait(d, val, async);
a19cbfb3 1307 break;
3e16b9c5
AL		 1308#if SPICE_INTERFACE_QXL_MINOR >= 1
1309 case QXL_IO_FLUSH_RELEASE: {
1310 QXLReleaseRing *ring = &d->ram->release_ring;
1311 if (ring->prod - ring->cons + 1 == ring->num_items) {
1312 fprintf(stderr,
1313 "ERROR: no flush, full release ring [p%d,%dc]\n",
1314 ring->prod, ring->cons);
1315 }
1316 qxl_push_free_res(d, 1 /* flush */);
1317 dprint(d, 1, "QXL_IO_FLUSH_RELEASE exit (%s, s#=%d, res#=%d,%p)\n",
1318 qxl_mode_to_string(d->mode), d->guest_surfaces.count,
1319 d->num_free_res, d->last_release);
1320 break;
1321 }
1322 case QXL_IO_FLUSH_SURFACES_ASYNC:
1323 dprint(d, 1, "QXL_IO_FLUSH_SURFACES_ASYNC (%d) (%s, s#=%d, res#=%d)\n",
1324 val, qxl_mode_to_string(d->mode), d->guest_surfaces.count,
1325 d->num_free_res);
1326 qxl_spice_flush_surfaces_async(d);
1327 break;
1328#endif
a19cbfb3 1329 case QXL_IO_DESTROY_ALL_SURFACES:
5ff4e36c
AL		 1330 d->mode = QXL_MODE_UNDEFINED;
1331 qxl_spice_destroy_surfaces(d, async);
a19cbfb3
GH		 1332 break;
1333 default:
1334 fprintf(stderr, "%s: ioport=0x%x, abort()\n", __FUNCTION__, io_port);
1335 abort();
1336 }
5ff4e36c
AL		 1337 return;
1338cancel_async:
1339#if SPICE_INTERFACE_QXL_MINOR >= 1
1340 if (async) {
1341 qxl_send_events(d, QXL_INTERRUPT_IO_CMD);
1342 qemu_mutex_lock(&d->async_lock);
1343 d->current_async = QXL_UNDEFINED_IO;
1344 qemu_mutex_unlock(&d->async_lock);
1345 }
1346#else
1347 return;
1348#endif
a19cbfb3
GH		 1349}
1350
1351static uint32_t ioport_read(void *opaque, uint32_t addr)
1352{
1353 PCIQXLDevice *d = opaque;
1354
1355 dprint(d, 1, "%s: unexpected\n", __FUNCTION__);
1356 return 0xff;
1357}
1358
1359static void qxl_map(PCIDevice *pci, int region_num,
1360 pcibus_t addr, pcibus_t size, int type)
1361{
1362 static const char *names[] = {
1363 [ QXL_IO_RANGE_INDEX ] = "ioports",
1364 [ QXL_RAM_RANGE_INDEX ] = "devram",
1365 [ QXL_ROM_RANGE_INDEX ] = "rom",
1366 [ QXL_VRAM_RANGE_INDEX ] = "vram",
1367 };
1368 PCIQXLDevice *qxl = DO_UPCAST(PCIQXLDevice, pci, pci);
1369
1370 dprint(qxl, 1, "%s: bar %d [%s] addr 0x%lx size 0x%lx\n", __FUNCTION__,
1371 region_num, names[region_num], addr, size);
1372
1373 switch (region_num) {
1374 case QXL_IO_RANGE_INDEX:
1375 register_ioport_write(addr, size, 1, ioport_write, pci);
1376 register_ioport_read(addr, size, 1, ioport_read, pci);
1377 qxl->io_base = addr;
1378 break;
1379 case QXL_RAM_RANGE_INDEX:
1380 cpu_register_physical_memory(addr, size, qxl->vga.vram_offset | IO_MEM_RAM);
1381 qxl->vga.map_addr = addr;
1382 qxl->vga.map_end = addr + size;
1383 if (qxl->id == 0) {
1384 vga_dirty_log_start(&qxl->vga);
1385 }
1386 break;
1387 case QXL_ROM_RANGE_INDEX:
1388 cpu_register_physical_memory(addr, size, qxl->rom_offset | IO_MEM_ROM);
1389 break;
1390 case QXL_VRAM_RANGE_INDEX:
1391 cpu_register_physical_memory(addr, size, qxl->vram_offset | IO_MEM_RAM);
1392 break;
1393 }
1394}
1395
1396static void pipe_read(void *opaque)
1397{
1398 PCIQXLDevice *d = opaque;
1399 char dummy;
1400 int len;
1401
1402 do {
1403 len = read(d->pipe[0], &dummy, sizeof(dummy));
1404 } while (len == sizeof(dummy));
1405 qxl_set_irq(d);
1406}
1407
1408/* called from spice server thread context only */
1409static void qxl_send_events(PCIQXLDevice *d, uint32_t events)
1410{
1411 uint32_t old_pending;
1412 uint32_t le_events = cpu_to_le32(events);
1413
1414 assert(d->ssd.running);
1415 old_pending = __sync_fetch_and_or(&d->ram->int_pending, le_events);
1416 if ((old_pending & le_events) == le_events) {
1417 return;
1418 }
1419 if (pthread_self() == d->main) {
1420 qxl_set_irq(d);
1421 } else {
1422 if (write(d->pipe[1], d, 1) != 1) {
1423 dprint(d, 1, "%s: write to pipe failed\n", __FUNCTION__);
1424 }
1425 }
1426}
1427
1428static void init_pipe_signaling(PCIQXLDevice *d)
1429{
1430 if (pipe(d->pipe) < 0) {
1431 dprint(d, 1, "%s: pipe creation failed\n", __FUNCTION__);
1432 return;
1433 }
1434#ifdef CONFIG_IOTHREAD
1435 fcntl(d->pipe[0], F_SETFL, O_NONBLOCK);
1436#else
1437 fcntl(d->pipe[0], F_SETFL, O_NONBLOCK /* | O_ASYNC */);
1438#endif
1439 fcntl(d->pipe[1], F_SETFL, O_NONBLOCK);
1440 fcntl(d->pipe[0], F_SETOWN, getpid());
1441
1442 d->main = pthread_self();
1443 qemu_set_fd_handler(d->pipe[0], pipe_read, NULL, d);
1444}
1445
1446/* graphics console */
1447
1448static void qxl_hw_update(void *opaque)
1449{
1450 PCIQXLDevice *qxl = opaque;
1451 VGACommonState *vga = &qxl->vga;
1452
1453 switch (qxl->mode) {
1454 case QXL_MODE_VGA:
1455 vga->update(vga);
1456 break;
1457 case QXL_MODE_COMPAT:
1458 case QXL_MODE_NATIVE:
1459 qxl_render_update(qxl);
1460 break;
1461 default:
1462 break;
1463 }
1464}
1465
1466static void qxl_hw_invalidate(void *opaque)
1467{
1468 PCIQXLDevice *qxl = opaque;
1469 VGACommonState *vga = &qxl->vga;
1470
1471 vga->invalidate(vga);
1472}
1473
1474static void qxl_hw_screen_dump(void *opaque, const char *filename)
1475{
1476 PCIQXLDevice *qxl = opaque;
1477 VGACommonState *vga = &qxl->vga;
1478
1479 switch (qxl->mode) {
1480 case QXL_MODE_COMPAT:
1481 case QXL_MODE_NATIVE:
1482 qxl_render_update(qxl);
1483 ppm_save(filename, qxl->ssd.ds->surface);
1484 break;
1485 case QXL_MODE_VGA:
1486 vga->screen_dump(vga, filename);
1487 break;
1488 default:
1489 break;
1490 }
1491}
1492
1493static void qxl_hw_text_update(void *opaque, console_ch_t *chardata)
1494{
1495 PCIQXLDevice *qxl = opaque;
1496 VGACommonState *vga = &qxl->vga;
1497
1498 if (qxl->mode == QXL_MODE_VGA) {
1499 vga->text_update(vga, chardata);
1500 return;
1501 }
1502}
1503
1504static void qxl_vm_change_state_handler(void *opaque, int running, int reason)
1505{
1506 PCIQXLDevice *qxl = opaque;
1507 qemu_spice_vm_change_state_handler(&qxl->ssd, running, reason);
1508
1509 if (!running && qxl->mode == QXL_MODE_NATIVE) {
868379ce
YH		 1510 /* dirty all vram (which holds surfaces) and devram (primary surface)
1511 * to make sure they are saved */
a19cbfb3
GH		 1512 /* FIXME #1: should go out during "live" stage */
1513 /* FIXME #2: we only need to save the areas which are actually used */
868379ce
YH		 1514 ram_addr_t vram_addr = qxl->vram_offset;
1515 ram_addr_t surface0_addr = qxl->vga.vram_offset + qxl->shadow_rom.draw_area_offset;
1516 qxl_set_dirty(vram_addr, vram_addr + qxl->vram_size);
1517 qxl_set_dirty(surface0_addr, surface0_addr + qxl->shadow_rom.surface0_area_size);
a19cbfb3
GH		 1518 }
1519}
1520
1521/* display change listener */
1522
1523static void display_update(struct DisplayState *ds, int x, int y, int w, int h)
1524{
1525 if (qxl0->mode == QXL_MODE_VGA) {
1526 qemu_spice_display_update(&qxl0->ssd, x, y, w, h);
1527 }
1528}
1529
1530static void display_resize(struct DisplayState *ds)
1531{
1532 if (qxl0->mode == QXL_MODE_VGA) {
1533 qemu_spice_display_resize(&qxl0->ssd);
1534 }
1535}
1536
1537static void display_refresh(struct DisplayState *ds)
1538{
1539 if (qxl0->mode == QXL_MODE_VGA) {
1540 qemu_spice_display_refresh(&qxl0->ssd);
1541 }
1542}
1543
1544static DisplayChangeListener display_listener = {
1545 .dpy_update = display_update,
1546 .dpy_resize = display_resize,
1547 .dpy_refresh = display_refresh,
1548};
1549
1550static int qxl_init_common(PCIQXLDevice *qxl)
1551{
1552 uint8_t* config = qxl->pci.config;
a19cbfb3
GH		 1553 uint32_t pci_device_rev;
1554 uint32_t io_size;
1555
1556 qxl->mode = QXL_MODE_UNDEFINED;
1557 qxl->generation = 1;
1558 qxl->num_memslots = NUM_MEMSLOTS;
1559 qxl->num_surfaces = NUM_SURFACES;
14898cf6 1560 qemu_mutex_init(&qxl->track_lock);
5ff4e36c
AL		 1561 qemu_mutex_init(&qxl->async_lock);
1562 qxl->current_async = QXL_UNDEFINED_IO;
a19cbfb3
GH		 1563
1564 switch (qxl->revision) {
1565 case 1: /* spice 0.4 -- qxl-1 */
a19cbfb3
GH		 1566 pci_device_rev = QXL_REVISION_STABLE_V04;
1567 break;
1568 case 2: /* spice 0.6 -- qxl-2 */
638f4e47 1569 default:
a19cbfb3
GH		 1570 pci_device_rev = QXL_REVISION_STABLE_V06;
1571 break;
a19cbfb3
GH		 1572 }
1573
a19cbfb3
GH		 1574 pci_set_byte(&config[PCI_REVISION_ID], pci_device_rev);
1575 pci_set_byte(&config[PCI_INTERRUPT_PIN], 1);
1576
1577 qxl->rom_size = qxl_rom_size();
1578 qxl->rom_offset = qemu_ram_alloc(&qxl->pci.qdev, "qxl.vrom", qxl->rom_size);
1579 init_qxl_rom(qxl);
1580 init_qxl_ram(qxl);
1581
1582 if (qxl->vram_size < 16 * 1024 * 1024) {
1583 qxl->vram_size = 16 * 1024 * 1024;
1584 }
1585 if (qxl->revision == 1) {
1586 qxl->vram_size = 4096;
1587 }
1588 qxl->vram_size = msb_mask(qxl->vram_size * 2 - 1);
1589 qxl->vram_offset = qemu_ram_alloc(&qxl->pci.qdev, "qxl.vram", qxl->vram_size);
1590
1591 io_size = msb_mask(QXL_IO_RANGE_SIZE * 2 - 1);
1592 if (qxl->revision == 1) {
1593 io_size = 8;
1594 }
1595
1596 pci_register_bar(&qxl->pci, QXL_IO_RANGE_INDEX,
1597 io_size, PCI_BASE_ADDRESS_SPACE_IO, qxl_map);
1598
1599 pci_register_bar(&qxl->pci, QXL_ROM_RANGE_INDEX,
1600 qxl->rom_size, PCI_BASE_ADDRESS_SPACE_MEMORY,
1601 qxl_map);
1602
1603 pci_register_bar(&qxl->pci, QXL_RAM_RANGE_INDEX,
1604 qxl->vga.vram_size, PCI_BASE_ADDRESS_SPACE_MEMORY,
1605 qxl_map);
1606
1607 pci_register_bar(&qxl->pci, QXL_VRAM_RANGE_INDEX, qxl->vram_size,
1608 PCI_BASE_ADDRESS_SPACE_MEMORY, qxl_map);
1609
1610 qxl->ssd.qxl.base.sif = &qxl_interface.base;
1611 qxl->ssd.qxl.id = qxl->id;
1612 qemu_spice_add_interface(&qxl->ssd.qxl.base);
1613 qemu_add_vm_change_state_handler(qxl_vm_change_state_handler, qxl);
1614
1615 init_pipe_signaling(qxl);
1616 qxl_reset_state(qxl);
1617
1618 return 0;
1619}
1620
1621static int qxl_init_primary(PCIDevice *dev)
1622{
1623 PCIQXLDevice *qxl = DO_UPCAST(PCIQXLDevice, pci, dev);
1624 VGACommonState *vga = &qxl->vga;
1625 ram_addr_t ram_size = msb_mask(qxl->vga.vram_size * 2 - 1);
1626
1627 qxl->id = 0;
1628
1629 if (ram_size < 32 * 1024 * 1024) {
1630 ram_size = 32 * 1024 * 1024;
1631 }
1632 vga_common_init(vga, ram_size);
1633 vga_init(vga);
1634 register_ioport_write(0x3c0, 16, 1, qxl_vga_ioport_write, vga);
1635 register_ioport_write(0x3b4, 2, 1, qxl_vga_ioport_write, vga);
1636 register_ioport_write(0x3d4, 2, 1, qxl_vga_ioport_write, vga);
1637 register_ioport_write(0x3ba, 1, 1, qxl_vga_ioport_write, vga);
1638 register_ioport_write(0x3da, 1, 1, qxl_vga_ioport_write, vga);
1639
1640 vga->ds = graphic_console_init(qxl_hw_update, qxl_hw_invalidate,
1641 qxl_hw_screen_dump, qxl_hw_text_update, qxl);
a963f876 1642 qemu_spice_display_init_common(&qxl->ssd, vga->ds);
a19cbfb3
GH		 1643
1644 qxl0 = qxl;
1645 register_displaychangelistener(vga->ds, &display_listener);
1646
a19cbfb3
GH		 1647 return qxl_init_common(qxl);
1648}
1649
1650static int qxl_init_secondary(PCIDevice *dev)
1651{
1652 static int device_id = 1;
1653 PCIQXLDevice *qxl = DO_UPCAST(PCIQXLDevice, pci, dev);
1654 ram_addr_t ram_size = msb_mask(qxl->vga.vram_size * 2 - 1);
1655
1656 qxl->id = device_id++;
1657
1658 if (ram_size < 16 * 1024 * 1024) {
1659 ram_size = 16 * 1024 * 1024;
1660 }
1661 qxl->vga.vram_size = ram_size;
1662 qxl->vga.vram_offset = qemu_ram_alloc(&qxl->pci.qdev, "qxl.vgavram",
1663 qxl->vga.vram_size);
1664 qxl->vga.vram_ptr = qemu_get_ram_ptr(qxl->vga.vram_offset);
1665
a19cbfb3
GH		 1666 return qxl_init_common(qxl);
1667}
1668
1669static void qxl_pre_save(void *opaque)
1670{
1671 PCIQXLDevice* d = opaque;
1672 uint8_t *ram_start = d->vga.vram_ptr;
1673
1674 dprint(d, 1, "%s:\n", __FUNCTION__);
1675 if (d->last_release == NULL) {
1676 d->last_release_offset = 0;
1677 } else {
1678 d->last_release_offset = (uint8_t *)d->last_release - ram_start;
1679 }
1680 assert(d->last_release_offset < d->vga.vram_size);
1681}
1682
1683static int qxl_pre_load(void *opaque)
1684{
1685 PCIQXLDevice* d = opaque;
1686
1687 dprint(d, 1, "%s: start\n", __FUNCTION__);
1688 qxl_hard_reset(d, 1);
1689 qxl_exit_vga_mode(d);
1690 dprint(d, 1, "%s: done\n", __FUNCTION__);
1691 return 0;
1692}
1693
1694static int qxl_post_load(void *opaque, int version)
1695{
1696 PCIQXLDevice* d = opaque;
1697 uint8_t *ram_start = d->vga.vram_ptr;
1698 QXLCommandExt *cmds;
1699 int in, out, i, newmode;
1700
1701 dprint(d, 1, "%s: start\n", __FUNCTION__);
1702
1703 assert(d->last_release_offset < d->vga.vram_size);
1704 if (d->last_release_offset == 0) {
1705 d->last_release = NULL;
1706 } else {
1707 d->last_release = (QXLReleaseInfo *)(ram_start + d->last_release_offset);
1708 }
1709
1710 d->modes = (QXLModes*)((uint8_t*)d->rom + d->rom->modes_offset);
1711
5b77870c
AL		 1712 dprint(d, 1, "%s: restore mode (%s)\n", __FUNCTION__,
1713 qxl_mode_to_string(d->mode));
a19cbfb3
GH		 1714 newmode = d->mode;
1715 d->mode = QXL_MODE_UNDEFINED;
1716 switch (newmode) {
1717 case QXL_MODE_UNDEFINED:
1718 break;
1719 case QXL_MODE_VGA:
1720 qxl_enter_vga_mode(d);
1721 break;
1722 case QXL_MODE_NATIVE:
1723 for (i = 0; i < NUM_MEMSLOTS; i++) {
1724 if (!d->guest_slots[i].active) {
1725 continue;
1726 }
5ff4e36c 1727 qxl_add_memslot(d, i, 0, QXL_SYNC);
a19cbfb3 1728 }
5ff4e36c 1729 qxl_create_guest_primary(d, 1, QXL_SYNC);
a19cbfb3
GH		 1730
1731 /* replay surface-create and cursor-set commands */
1732 cmds = qemu_mallocz(sizeof(QXLCommandExt) * (NUM_SURFACES + 1));
1733 for (in = 0, out = 0; in < NUM_SURFACES; in++) {
1734 if (d->guest_surfaces.cmds[in] == 0) {
1735 continue;
1736 }
1737 cmds[out].cmd.data = d->guest_surfaces.cmds[in];
1738 cmds[out].cmd.type = QXL_CMD_SURFACE;
1739 cmds[out].group_id = MEMSLOT_GROUP_GUEST;
1740 out++;
1741 }
1742 cmds[out].cmd.data = d->guest_cursor;
1743 cmds[out].cmd.type = QXL_CMD_CURSOR;
1744 cmds[out].group_id = MEMSLOT_GROUP_GUEST;
1745 out++;
aee32bf3 1746 qxl_spice_loadvm_commands(d, cmds, out);
a19cbfb3
GH		 1747 qemu_free(cmds);
1748
1749 break;
1750 case QXL_MODE_COMPAT:
1751 qxl_set_mode(d, d->shadow_rom.mode, 1);
1752 break;
1753 }
1754 dprint(d, 1, "%s: done\n", __FUNCTION__);
1755
a19cbfb3
GH		 1756 return 0;
1757}
1758
b67737a6 1759#define QXL_SAVE_VERSION 21
a19cbfb3
GH		 1760
1761static VMStateDescription qxl_memslot = {
1762 .name = "qxl-memslot",
1763 .version_id = QXL_SAVE_VERSION,
1764 .minimum_version_id = QXL_SAVE_VERSION,
1765 .fields = (VMStateField[]) {
1766 VMSTATE_UINT64(slot.mem_start, struct guest_slots),
1767 VMSTATE_UINT64(slot.mem_end, struct guest_slots),
1768 VMSTATE_UINT32(active, struct guest_slots),
1769 VMSTATE_END_OF_LIST()
1770 }
1771};
1772
1773static VMStateDescription qxl_surface = {
1774 .name = "qxl-surface",
1775 .version_id = QXL_SAVE_VERSION,
1776 .minimum_version_id = QXL_SAVE_VERSION,
1777 .fields = (VMStateField[]) {
1778 VMSTATE_UINT32(width, QXLSurfaceCreate),
1779 VMSTATE_UINT32(height, QXLSurfaceCreate),
1780 VMSTATE_INT32(stride, QXLSurfaceCreate),
1781 VMSTATE_UINT32(format, QXLSurfaceCreate),
1782 VMSTATE_UINT32(position, QXLSurfaceCreate),
1783 VMSTATE_UINT32(mouse_mode, QXLSurfaceCreate),
1784 VMSTATE_UINT32(flags, QXLSurfaceCreate),
1785 VMSTATE_UINT32(type, QXLSurfaceCreate),
1786 VMSTATE_UINT64(mem, QXLSurfaceCreate),
1787 VMSTATE_END_OF_LIST()
1788 }
1789};
1790
a19cbfb3
GH		 1791static VMStateDescription qxl_vmstate = {
1792 .name = "qxl",
1793 .version_id = QXL_SAVE_VERSION,
1794 .minimum_version_id = QXL_SAVE_VERSION,
1795 .pre_save = qxl_pre_save,
1796 .pre_load = qxl_pre_load,
1797 .post_load = qxl_post_load,
1798 .fields = (VMStateField []) {
1799 VMSTATE_PCI_DEVICE(pci, PCIQXLDevice),
1800 VMSTATE_STRUCT(vga, PCIQXLDevice, 0, vmstate_vga_common, VGACommonState),
1801 VMSTATE_UINT32(shadow_rom.mode, PCIQXLDevice),
1802 VMSTATE_UINT32(num_free_res, PCIQXLDevice),
1803 VMSTATE_UINT32(last_release_offset, PCIQXLDevice),
1804 VMSTATE_UINT32(mode, PCIQXLDevice),
1805 VMSTATE_UINT32(ssd.unique, PCIQXLDevice),
b67737a6
GH		 1806 VMSTATE_INT32_EQUAL(num_memslots, PCIQXLDevice),
1807 VMSTATE_STRUCT_ARRAY(guest_slots, PCIQXLDevice, NUM_MEMSLOTS, 0,
1808 qxl_memslot, struct guest_slots),
1809 VMSTATE_STRUCT(guest_primary.surface, PCIQXLDevice, 0,
1810 qxl_surface, QXLSurfaceCreate),
1811 VMSTATE_INT32_EQUAL(num_surfaces, PCIQXLDevice),
1812 VMSTATE_ARRAY(guest_surfaces.cmds, PCIQXLDevice, NUM_SURFACES, 0,
1813 vmstate_info_uint64, uint64_t),
1814 VMSTATE_UINT64(guest_cursor, PCIQXLDevice),
a19cbfb3
GH		 1815 VMSTATE_END_OF_LIST()
1816 },
a19cbfb3
GH		 1817};
1818
1819static PCIDeviceInfo qxl_info_primary = {
1820 .qdev.name = "qxl-vga",
1821 .qdev.desc = "Spice QXL GPU (primary, vga compatible)",
1822 .qdev.size = sizeof(PCIQXLDevice),
1823 .qdev.reset = qxl_reset_handler,
1824 .qdev.vmsd = &qxl_vmstate,
2f6bfe3b 1825 .no_hotplug = 1,
a19cbfb3
GH		 1826 .init = qxl_init_primary,
1827 .config_write = qxl_write_config,
1828 .romfile = "vgabios-qxl.bin",
96c05abc 1829 .vendor_id = REDHAT_PCI_VENDOR_ID,
638f4e47 1830 .device_id = QXL_DEVICE_ID_STABLE,
96c05abc 1831 .class_id = PCI_CLASS_DISPLAY_VGA,
a19cbfb3
GH		 1832 .qdev.props = (Property[]) {
1833 DEFINE_PROP_UINT32("ram_size", PCIQXLDevice, vga.vram_size, 64 * 1024 * 1024),
1834 DEFINE_PROP_UINT32("vram_size", PCIQXLDevice, vram_size, 64 * 1024 * 1024),
1835 DEFINE_PROP_UINT32("revision", PCIQXLDevice, revision, 2),
1836 DEFINE_PROP_UINT32("debug", PCIQXLDevice, debug, 0),
1837 DEFINE_PROP_UINT32("guestdebug", PCIQXLDevice, guestdebug, 0),
1838 DEFINE_PROP_UINT32("cmdlog", PCIQXLDevice, cmdlog, 0),
1839 DEFINE_PROP_END_OF_LIST(),
1840 }
1841};
1842
1843static PCIDeviceInfo qxl_info_secondary = {
1844 .qdev.name = "qxl",
1845 .qdev.desc = "Spice QXL GPU (secondary)",
1846 .qdev.size = sizeof(PCIQXLDevice),
1847 .qdev.reset = qxl_reset_handler,
1848 .qdev.vmsd = &qxl_vmstate,
1849 .init = qxl_init_secondary,
96c05abc 1850 .vendor_id = REDHAT_PCI_VENDOR_ID,
638f4e47 1851 .device_id = QXL_DEVICE_ID_STABLE,
96c05abc 1852 .class_id = PCI_CLASS_DISPLAY_OTHER,
a19cbfb3
GH		 1853 .qdev.props = (Property[]) {
1854 DEFINE_PROP_UINT32("ram_size", PCIQXLDevice, vga.vram_size, 64 * 1024 * 1024),
1855 DEFINE_PROP_UINT32("vram_size", PCIQXLDevice, vram_size, 64 * 1024 * 1024),
1856 DEFINE_PROP_UINT32("revision", PCIQXLDevice, revision, 2),
1857 DEFINE_PROP_UINT32("debug", PCIQXLDevice, debug, 0),
1858 DEFINE_PROP_UINT32("guestdebug", PCIQXLDevice, guestdebug, 0),
1859 DEFINE_PROP_UINT32("cmdlog", PCIQXLDevice, cmdlog, 0),
1860 DEFINE_PROP_END_OF_LIST(),
1861 }
1862};
1863
1864static void qxl_register(void)
1865{
1866 pci_qdev_register(&qxl_info_primary);
1867 pci_qdev_register(&qxl_info_secondary);
1868}
1869
1870device_init(qxl_register);
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