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a19cbfb3 GH |
1 | /* |
2 | * Copyright (C) 2010 Red Hat, Inc. | |
3 | * | |
4 | * written by Yaniv Kamay, Izik Eidus, Gerd Hoffmann | |
5 | * maintained by Gerd Hoffmann <[email protected]> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License as | |
9 | * published by the Free Software Foundation; either version 2 or | |
10 | * (at your option) version 3 of the License. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, see <http://www.gnu.org/licenses/>. | |
19 | */ | |
20 | ||
a639ab04 AL |
21 | #include <zlib.h> |
22 | ||
a19cbfb3 | 23 | #include "qemu-common.h" |
1de7afc9 PB |
24 | #include "qemu/timer.h" |
25 | #include "qemu/queue.h" | |
83c9089e | 26 | #include "monitor/monitor.h" |
9c17d615 | 27 | #include "sysemu/sysemu.h" |
c480bb7d | 28 | #include "trace.h" |
a19cbfb3 | 29 | |
47b43a1f | 30 | #include "qxl.h" |
a19cbfb3 | 31 | |
0b81c478 AL |
32 | /* |
33 | * NOTE: SPICE_RING_PROD_ITEM accesses memory on the pci bar and as | |
34 | * such can be changed by the guest, so to avoid a guest trigerrable | |
0a530548 | 35 | * abort we just qxl_set_guest_bug and set the return to NULL. Still |
0b81c478 AL |
36 | * it may happen as a result of emulator bug as well. |
37 | */ | |
a19cbfb3 | 38 | #undef SPICE_RING_PROD_ITEM |
0b81c478 | 39 | #define SPICE_RING_PROD_ITEM(qxl, r, ret) { \ |
a19cbfb3 | 40 | uint32_t prod = (r)->prod & SPICE_RING_INDEX_MASK(r); \ |
bc5f92e5 | 41 | if (prod >= ARRAY_SIZE((r)->items)) { \ |
0a530548 | 42 | qxl_set_guest_bug(qxl, "SPICE_RING_PROD_ITEM indices mismatch " \ |
bc5f92e5 | 43 | "%u >= %zu", prod, ARRAY_SIZE((r)->items)); \ |
0b81c478 AL |
44 | ret = NULL; \ |
45 | } else { \ | |
bc5f92e5 | 46 | ret = &(r)->items[prod].el; \ |
a19cbfb3 | 47 | } \ |
a19cbfb3 GH |
48 | } |
49 | ||
50 | #undef SPICE_RING_CONS_ITEM | |
0b81c478 | 51 | #define SPICE_RING_CONS_ITEM(qxl, r, ret) { \ |
a19cbfb3 | 52 | uint32_t cons = (r)->cons & SPICE_RING_INDEX_MASK(r); \ |
bc5f92e5 | 53 | if (cons >= ARRAY_SIZE((r)->items)) { \ |
0a530548 | 54 | qxl_set_guest_bug(qxl, "SPICE_RING_CONS_ITEM indices mismatch " \ |
bc5f92e5 | 55 | "%u >= %zu", cons, ARRAY_SIZE((r)->items)); \ |
0b81c478 AL |
56 | ret = NULL; \ |
57 | } else { \ | |
bc5f92e5 | 58 | ret = &(r)->items[cons].el; \ |
a19cbfb3 | 59 | } \ |
a19cbfb3 GH |
60 | } |
61 | ||
62 | #undef ALIGN | |
63 | #define ALIGN(a, b) (((a) + ((b) - 1)) & ~((b) - 1)) | |
64 | ||
65 | #define PIXEL_SIZE 0.2936875 //1280x1024 is 14.8" x 11.9" | |
66 | ||
67 | #define QXL_MODE(_x, _y, _b, _o) \ | |
68 | { .x_res = _x, \ | |
69 | .y_res = _y, \ | |
70 | .bits = _b, \ | |
71 | .stride = (_x) * (_b) / 8, \ | |
72 | .x_mili = PIXEL_SIZE * (_x), \ | |
73 | .y_mili = PIXEL_SIZE * (_y), \ | |
74 | .orientation = _o, \ | |
75 | } | |
76 | ||
77 | #define QXL_MODE_16_32(x_res, y_res, orientation) \ | |
78 | QXL_MODE(x_res, y_res, 16, orientation), \ | |
79 | QXL_MODE(x_res, y_res, 32, orientation) | |
80 | ||
81 | #define QXL_MODE_EX(x_res, y_res) \ | |
82 | QXL_MODE_16_32(x_res, y_res, 0), \ | |
038c1879 | 83 | QXL_MODE_16_32(x_res, y_res, 1) |
a19cbfb3 GH |
84 | |
85 | static QXLMode qxl_modes[] = { | |
86 | QXL_MODE_EX(640, 480), | |
87 | QXL_MODE_EX(800, 480), | |
88 | QXL_MODE_EX(800, 600), | |
89 | QXL_MODE_EX(832, 624), | |
90 | QXL_MODE_EX(960, 640), | |
91 | QXL_MODE_EX(1024, 600), | |
92 | QXL_MODE_EX(1024, 768), | |
93 | QXL_MODE_EX(1152, 864), | |
94 | QXL_MODE_EX(1152, 870), | |
95 | QXL_MODE_EX(1280, 720), | |
96 | QXL_MODE_EX(1280, 760), | |
97 | QXL_MODE_EX(1280, 768), | |
98 | QXL_MODE_EX(1280, 800), | |
99 | QXL_MODE_EX(1280, 960), | |
100 | QXL_MODE_EX(1280, 1024), | |
101 | QXL_MODE_EX(1360, 768), | |
102 | QXL_MODE_EX(1366, 768), | |
103 | QXL_MODE_EX(1400, 1050), | |
104 | QXL_MODE_EX(1440, 900), | |
105 | QXL_MODE_EX(1600, 900), | |
106 | QXL_MODE_EX(1600, 1200), | |
107 | QXL_MODE_EX(1680, 1050), | |
108 | QXL_MODE_EX(1920, 1080), | |
a19cbfb3 GH |
109 | /* these modes need more than 8 MB video memory */ |
110 | QXL_MODE_EX(1920, 1200), | |
111 | QXL_MODE_EX(1920, 1440), | |
112 | QXL_MODE_EX(2048, 1536), | |
113 | QXL_MODE_EX(2560, 1440), | |
114 | QXL_MODE_EX(2560, 1600), | |
a19cbfb3 GH |
115 | /* these modes need more than 16 MB video memory */ |
116 | QXL_MODE_EX(2560, 2048), | |
117 | QXL_MODE_EX(2800, 2100), | |
118 | QXL_MODE_EX(3200, 2400), | |
d4bcb199 GH |
119 | QXL_MODE_EX(3840, 2160), /* 4k mainstream */ |
120 | QXL_MODE_EX(4096, 2160), /* 4k */ | |
121 | QXL_MODE_EX(7680, 4320), /* 8k mainstream */ | |
122 | QXL_MODE_EX(8192, 4320), /* 8k */ | |
a19cbfb3 GH |
123 | }; |
124 | ||
a19cbfb3 | 125 | static void qxl_send_events(PCIQXLDevice *d, uint32_t events); |
5ff4e36c | 126 | static int qxl_destroy_primary(PCIQXLDevice *d, qxl_async_io async); |
a19cbfb3 GH |
127 | static void qxl_reset_memslots(PCIQXLDevice *d); |
128 | static void qxl_reset_surfaces(PCIQXLDevice *d); | |
129 | static void qxl_ring_set_dirty(PCIQXLDevice *qxl); | |
130 | ||
0a530548 | 131 | void qxl_set_guest_bug(PCIQXLDevice *qxl, const char *msg, ...) |
2bce0400 | 132 | { |
917ae08c | 133 | trace_qxl_set_guest_bug(qxl->id); |
2bce0400 | 134 | qxl_send_events(qxl, QXL_INTERRUPT_ERROR); |
087e6a42 | 135 | qxl->guest_bug = 1; |
2bce0400 | 136 | if (qxl->guestdebug) { |
7635392c AL |
137 | va_list ap; |
138 | va_start(ap, msg); | |
139 | fprintf(stderr, "qxl-%d: guest bug: ", qxl->id); | |
140 | vfprintf(stderr, msg, ap); | |
141 | fprintf(stderr, "\n"); | |
142 | va_end(ap); | |
2bce0400 GH |
143 | } |
144 | } | |
145 | ||
087e6a42 AL |
146 | static void qxl_clear_guest_bug(PCIQXLDevice *qxl) |
147 | { | |
148 | qxl->guest_bug = 0; | |
149 | } | |
aee32bf3 GH |
150 | |
151 | void qxl_spice_update_area(PCIQXLDevice *qxl, uint32_t surface_id, | |
152 | struct QXLRect *area, struct QXLRect *dirty_rects, | |
153 | uint32_t num_dirty_rects, | |
5ff4e36c | 154 | uint32_t clear_dirty_region, |
2e1a98c9 | 155 | qxl_async_io async, struct QXLCookie *cookie) |
aee32bf3 | 156 | { |
c480bb7d AL |
157 | trace_qxl_spice_update_area(qxl->id, surface_id, area->left, area->right, |
158 | area->top, area->bottom); | |
159 | trace_qxl_spice_update_area_rest(qxl->id, num_dirty_rects, | |
160 | clear_dirty_region); | |
5ff4e36c AL |
161 | if (async == QXL_SYNC) { |
162 | qxl->ssd.worker->update_area(qxl->ssd.worker, surface_id, area, | |
163 | dirty_rects, num_dirty_rects, clear_dirty_region); | |
164 | } else { | |
2e1a98c9 | 165 | assert(cookie != NULL); |
5ff4e36c | 166 | spice_qxl_update_area_async(&qxl->ssd.qxl, surface_id, area, |
5dba0d45 | 167 | clear_dirty_region, (uintptr_t)cookie); |
5ff4e36c | 168 | } |
aee32bf3 GH |
169 | } |
170 | ||
5ff4e36c AL |
171 | static void qxl_spice_destroy_surface_wait_complete(PCIQXLDevice *qxl, |
172 | uint32_t id) | |
aee32bf3 | 173 | { |
c480bb7d | 174 | trace_qxl_spice_destroy_surface_wait_complete(qxl->id, id); |
14898cf6 | 175 | qemu_mutex_lock(&qxl->track_lock); |
14898cf6 GH |
176 | qxl->guest_surfaces.cmds[id] = 0; |
177 | qxl->guest_surfaces.count--; | |
178 | qemu_mutex_unlock(&qxl->track_lock); | |
aee32bf3 GH |
179 | } |
180 | ||
5ff4e36c AL |
181 | static void qxl_spice_destroy_surface_wait(PCIQXLDevice *qxl, uint32_t id, |
182 | qxl_async_io async) | |
183 | { | |
2e1a98c9 AL |
184 | QXLCookie *cookie; |
185 | ||
c480bb7d | 186 | trace_qxl_spice_destroy_surface_wait(qxl->id, id, async); |
5ff4e36c | 187 | if (async) { |
2e1a98c9 AL |
188 | cookie = qxl_cookie_new(QXL_COOKIE_TYPE_IO, |
189 | QXL_IO_DESTROY_SURFACE_ASYNC); | |
190 | cookie->u.surface_id = id; | |
5dba0d45 | 191 | spice_qxl_destroy_surface_async(&qxl->ssd.qxl, id, (uintptr_t)cookie); |
5ff4e36c AL |
192 | } else { |
193 | qxl->ssd.worker->destroy_surface_wait(qxl->ssd.worker, id); | |
753b8b0d | 194 | qxl_spice_destroy_surface_wait_complete(qxl, id); |
5ff4e36c AL |
195 | } |
196 | } | |
197 | ||
3e16b9c5 AL |
198 | static void qxl_spice_flush_surfaces_async(PCIQXLDevice *qxl) |
199 | { | |
c480bb7d AL |
200 | trace_qxl_spice_flush_surfaces_async(qxl->id, qxl->guest_surfaces.count, |
201 | qxl->num_free_res); | |
2e1a98c9 | 202 | spice_qxl_flush_surfaces_async(&qxl->ssd.qxl, |
5dba0d45 PM |
203 | (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO, |
204 | QXL_IO_FLUSH_SURFACES_ASYNC)); | |
3e16b9c5 | 205 | } |
3e16b9c5 | 206 | |
aee32bf3 GH |
207 | void qxl_spice_loadvm_commands(PCIQXLDevice *qxl, struct QXLCommandExt *ext, |
208 | uint32_t count) | |
209 | { | |
c480bb7d | 210 | trace_qxl_spice_loadvm_commands(qxl->id, ext, count); |
aee32bf3 GH |
211 | qxl->ssd.worker->loadvm_commands(qxl->ssd.worker, ext, count); |
212 | } | |
213 | ||
214 | void qxl_spice_oom(PCIQXLDevice *qxl) | |
215 | { | |
c480bb7d | 216 | trace_qxl_spice_oom(qxl->id); |
aee32bf3 GH |
217 | qxl->ssd.worker->oom(qxl->ssd.worker); |
218 | } | |
219 | ||
220 | void qxl_spice_reset_memslots(PCIQXLDevice *qxl) | |
221 | { | |
c480bb7d | 222 | trace_qxl_spice_reset_memslots(qxl->id); |
aee32bf3 GH |
223 | qxl->ssd.worker->reset_memslots(qxl->ssd.worker); |
224 | } | |
225 | ||
5ff4e36c | 226 | static void qxl_spice_destroy_surfaces_complete(PCIQXLDevice *qxl) |
aee32bf3 | 227 | { |
c480bb7d | 228 | trace_qxl_spice_destroy_surfaces_complete(qxl->id); |
14898cf6 | 229 | qemu_mutex_lock(&qxl->track_lock); |
ddd8fdc7 GH |
230 | memset(qxl->guest_surfaces.cmds, 0, |
231 | sizeof(qxl->guest_surfaces.cmds) * qxl->ssd.num_surfaces); | |
14898cf6 GH |
232 | qxl->guest_surfaces.count = 0; |
233 | qemu_mutex_unlock(&qxl->track_lock); | |
aee32bf3 GH |
234 | } |
235 | ||
5ff4e36c AL |
236 | static void qxl_spice_destroy_surfaces(PCIQXLDevice *qxl, qxl_async_io async) |
237 | { | |
c480bb7d | 238 | trace_qxl_spice_destroy_surfaces(qxl->id, async); |
5ff4e36c | 239 | if (async) { |
2e1a98c9 | 240 | spice_qxl_destroy_surfaces_async(&qxl->ssd.qxl, |
5dba0d45 PM |
241 | (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO, |
242 | QXL_IO_DESTROY_ALL_SURFACES_ASYNC)); | |
5ff4e36c AL |
243 | } else { |
244 | qxl->ssd.worker->destroy_surfaces(qxl->ssd.worker); | |
245 | qxl_spice_destroy_surfaces_complete(qxl); | |
246 | } | |
247 | } | |
248 | ||
020af1c4 AL |
249 | static void qxl_spice_monitors_config_async(PCIQXLDevice *qxl, int replay) |
250 | { | |
251 | trace_qxl_spice_monitors_config(qxl->id); | |
020af1c4 AL |
252 | if (replay) { |
253 | /* | |
254 | * don't use QXL_COOKIE_TYPE_IO: | |
255 | * - we are not running yet (post_load), we will assert | |
256 | * in send_events | |
257 | * - this is not a guest io, but a reply, so async_io isn't set. | |
258 | */ | |
259 | spice_qxl_monitors_config_async(&qxl->ssd.qxl, | |
260 | qxl->guest_monitors_config, | |
261 | MEMSLOT_GROUP_GUEST, | |
262 | (uintptr_t)qxl_cookie_new( | |
263 | QXL_COOKIE_TYPE_POST_LOAD_MONITORS_CONFIG, | |
264 | 0)); | |
265 | } else { | |
266 | qxl->guest_monitors_config = qxl->ram->monitors_config; | |
267 | spice_qxl_monitors_config_async(&qxl->ssd.qxl, | |
268 | qxl->ram->monitors_config, | |
269 | MEMSLOT_GROUP_GUEST, | |
270 | (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO, | |
271 | QXL_IO_MONITORS_CONFIG_ASYNC)); | |
272 | } | |
020af1c4 AL |
273 | } |
274 | ||
aee32bf3 GH |
275 | void qxl_spice_reset_image_cache(PCIQXLDevice *qxl) |
276 | { | |
c480bb7d | 277 | trace_qxl_spice_reset_image_cache(qxl->id); |
aee32bf3 GH |
278 | qxl->ssd.worker->reset_image_cache(qxl->ssd.worker); |
279 | } | |
280 | ||
281 | void qxl_spice_reset_cursor(PCIQXLDevice *qxl) | |
282 | { | |
c480bb7d | 283 | trace_qxl_spice_reset_cursor(qxl->id); |
aee32bf3 | 284 | qxl->ssd.worker->reset_cursor(qxl->ssd.worker); |
30f6da66 YH |
285 | qemu_mutex_lock(&qxl->track_lock); |
286 | qxl->guest_cursor = 0; | |
287 | qemu_mutex_unlock(&qxl->track_lock); | |
958c2bce GH |
288 | if (qxl->ssd.cursor) { |
289 | cursor_put(qxl->ssd.cursor); | |
290 | } | |
291 | qxl->ssd.cursor = cursor_builtin_hidden(); | |
aee32bf3 GH |
292 | } |
293 | ||
294 | ||
a19cbfb3 GH |
295 | static inline uint32_t msb_mask(uint32_t val) |
296 | { | |
297 | uint32_t mask; | |
298 | ||
299 | do { | |
300 | mask = ~(val - 1) & val; | |
301 | val &= ~mask; | |
302 | } while (mask < val); | |
303 | ||
304 | return mask; | |
305 | } | |
306 | ||
307 | static ram_addr_t qxl_rom_size(void) | |
308 | { | |
038c1879 AL |
309 | uint32_t required_rom_size = sizeof(QXLRom) + sizeof(QXLModes) + |
310 | sizeof(qxl_modes); | |
311 | uint32_t rom_size = 8192; /* two pages */ | |
13d1fd44 | 312 | |
038c1879 AL |
313 | required_rom_size = MAX(required_rom_size, TARGET_PAGE_SIZE); |
314 | required_rom_size = msb_mask(required_rom_size * 2 - 1); | |
315 | assert(required_rom_size <= rom_size); | |
a19cbfb3 GH |
316 | return rom_size; |
317 | } | |
318 | ||
319 | static void init_qxl_rom(PCIQXLDevice *d) | |
320 | { | |
b1950430 | 321 | QXLRom *rom = memory_region_get_ram_ptr(&d->rom_bar); |
a19cbfb3 GH |
322 | QXLModes *modes = (QXLModes *)(rom + 1); |
323 | uint32_t ram_header_size; | |
324 | uint32_t surface0_area_size; | |
325 | uint32_t num_pages; | |
13d1fd44 AL |
326 | uint32_t fb; |
327 | int i, n; | |
a19cbfb3 GH |
328 | |
329 | memset(rom, 0, d->rom_size); | |
330 | ||
331 | rom->magic = cpu_to_le32(QXL_ROM_MAGIC); | |
332 | rom->id = cpu_to_le32(d->id); | |
333 | rom->log_level = cpu_to_le32(d->guestdebug); | |
334 | rom->modes_offset = cpu_to_le32(sizeof(QXLRom)); | |
335 | ||
336 | rom->slot_gen_bits = MEMSLOT_GENERATION_BITS; | |
337 | rom->slot_id_bits = MEMSLOT_SLOT_BITS; | |
338 | rom->slots_start = 1; | |
339 | rom->slots_end = NUM_MEMSLOTS - 1; | |
ddd8fdc7 | 340 | rom->n_surfaces = cpu_to_le32(d->ssd.num_surfaces); |
a19cbfb3 | 341 | |
13d1fd44 | 342 | for (i = 0, n = 0; i < ARRAY_SIZE(qxl_modes); i++) { |
a19cbfb3 | 343 | fb = qxl_modes[i].y_res * qxl_modes[i].stride; |
13d1fd44 AL |
344 | if (fb > d->vgamem_size) { |
345 | continue; | |
a19cbfb3 | 346 | } |
13d1fd44 AL |
347 | modes->modes[n].id = cpu_to_le32(i); |
348 | modes->modes[n].x_res = cpu_to_le32(qxl_modes[i].x_res); | |
349 | modes->modes[n].y_res = cpu_to_le32(qxl_modes[i].y_res); | |
350 | modes->modes[n].bits = cpu_to_le32(qxl_modes[i].bits); | |
351 | modes->modes[n].stride = cpu_to_le32(qxl_modes[i].stride); | |
352 | modes->modes[n].x_mili = cpu_to_le32(qxl_modes[i].x_mili); | |
353 | modes->modes[n].y_mili = cpu_to_le32(qxl_modes[i].y_mili); | |
354 | modes->modes[n].orientation = cpu_to_le32(qxl_modes[i].orientation); | |
355 | n++; | |
356 | } | |
357 | modes->n_modes = cpu_to_le32(n); | |
a19cbfb3 GH |
358 | |
359 | ram_header_size = ALIGN(sizeof(QXLRam), 4096); | |
13d1fd44 | 360 | surface0_area_size = ALIGN(d->vgamem_size, 4096); |
a19cbfb3 GH |
361 | num_pages = d->vga.vram_size; |
362 | num_pages -= ram_header_size; | |
363 | num_pages -= surface0_area_size; | |
364 | num_pages = num_pages / TARGET_PAGE_SIZE; | |
365 | ||
366 | rom->draw_area_offset = cpu_to_le32(0); | |
367 | rom->surface0_area_size = cpu_to_le32(surface0_area_size); | |
368 | rom->pages_offset = cpu_to_le32(surface0_area_size); | |
369 | rom->num_pages = cpu_to_le32(num_pages); | |
370 | rom->ram_header_offset = cpu_to_le32(d->vga.vram_size - ram_header_size); | |
371 | ||
372 | d->shadow_rom = *rom; | |
373 | d->rom = rom; | |
374 | d->modes = modes; | |
375 | } | |
376 | ||
377 | static void init_qxl_ram(PCIQXLDevice *d) | |
378 | { | |
379 | uint8_t *buf; | |
380 | uint64_t *item; | |
381 | ||
382 | buf = d->vga.vram_ptr; | |
383 | d->ram = (QXLRam *)(buf + le32_to_cpu(d->shadow_rom.ram_header_offset)); | |
384 | d->ram->magic = cpu_to_le32(QXL_RAM_MAGIC); | |
385 | d->ram->int_pending = cpu_to_le32(0); | |
386 | d->ram->int_mask = cpu_to_le32(0); | |
9f0f352d | 387 | d->ram->update_surface = 0; |
a19cbfb3 GH |
388 | SPICE_RING_INIT(&d->ram->cmd_ring); |
389 | SPICE_RING_INIT(&d->ram->cursor_ring); | |
390 | SPICE_RING_INIT(&d->ram->release_ring); | |
0b81c478 AL |
391 | SPICE_RING_PROD_ITEM(d, &d->ram->release_ring, item); |
392 | assert(item); | |
a19cbfb3 GH |
393 | *item = 0; |
394 | qxl_ring_set_dirty(d); | |
395 | } | |
396 | ||
397 | /* can be called from spice server thread context */ | |
b1950430 | 398 | static void qxl_set_dirty(MemoryRegion *mr, ram_addr_t addr, ram_addr_t end) |
a19cbfb3 | 399 | { |
fd4aa979 | 400 | memory_region_set_dirty(mr, addr, end - addr); |
a19cbfb3 GH |
401 | } |
402 | ||
403 | static void qxl_rom_set_dirty(PCIQXLDevice *qxl) | |
404 | { | |
b1950430 | 405 | qxl_set_dirty(&qxl->rom_bar, 0, qxl->rom_size); |
a19cbfb3 GH |
406 | } |
407 | ||
408 | /* called from spice server thread context only */ | |
409 | static void qxl_ram_set_dirty(PCIQXLDevice *qxl, void *ptr) | |
410 | { | |
a19cbfb3 GH |
411 | void *base = qxl->vga.vram_ptr; |
412 | intptr_t offset; | |
413 | ||
414 | offset = ptr - base; | |
415 | offset &= ~(TARGET_PAGE_SIZE-1); | |
416 | assert(offset < qxl->vga.vram_size); | |
b1950430 | 417 | qxl_set_dirty(&qxl->vga.vram, offset, offset + TARGET_PAGE_SIZE); |
a19cbfb3 GH |
418 | } |
419 | ||
420 | /* can be called from spice server thread context */ | |
421 | static void qxl_ring_set_dirty(PCIQXLDevice *qxl) | |
422 | { | |
b1950430 AK |
423 | ram_addr_t addr = qxl->shadow_rom.ram_header_offset; |
424 | ram_addr_t end = qxl->vga.vram_size; | |
425 | qxl_set_dirty(&qxl->vga.vram, addr, end); | |
a19cbfb3 GH |
426 | } |
427 | ||
428 | /* | |
429 | * keep track of some command state, for savevm/loadvm. | |
430 | * called from spice server thread context only | |
431 | */ | |
fae2afb1 | 432 | static int qxl_track_command(PCIQXLDevice *qxl, struct QXLCommandExt *ext) |
a19cbfb3 GH |
433 | { |
434 | switch (le32_to_cpu(ext->cmd.type)) { | |
435 | case QXL_CMD_SURFACE: | |
436 | { | |
437 | QXLSurfaceCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id); | |
fae2afb1 AL |
438 | |
439 | if (!cmd) { | |
440 | return 1; | |
441 | } | |
a19cbfb3 | 442 | uint32_t id = le32_to_cpu(cmd->surface_id); |
47eddfbf | 443 | |
ddd8fdc7 | 444 | if (id >= qxl->ssd.num_surfaces) { |
0a530548 | 445 | qxl_set_guest_bug(qxl, "QXL_CMD_SURFACE id %d >= %d", id, |
ddd8fdc7 | 446 | qxl->ssd.num_surfaces); |
47eddfbf AL |
447 | return 1; |
448 | } | |
48f4ba67 AL |
449 | if (cmd->type == QXL_SURFACE_CMD_CREATE && |
450 | (cmd->u.surface_create.stride & 0x03) != 0) { | |
451 | qxl_set_guest_bug(qxl, "QXL_CMD_SURFACE stride = %d %% 4 != 0\n", | |
452 | cmd->u.surface_create.stride); | |
453 | return 1; | |
454 | } | |
14898cf6 | 455 | qemu_mutex_lock(&qxl->track_lock); |
a19cbfb3 GH |
456 | if (cmd->type == QXL_SURFACE_CMD_CREATE) { |
457 | qxl->guest_surfaces.cmds[id] = ext->cmd.data; | |
458 | qxl->guest_surfaces.count++; | |
459 | if (qxl->guest_surfaces.max < qxl->guest_surfaces.count) | |
460 | qxl->guest_surfaces.max = qxl->guest_surfaces.count; | |
461 | } | |
462 | if (cmd->type == QXL_SURFACE_CMD_DESTROY) { | |
463 | qxl->guest_surfaces.cmds[id] = 0; | |
464 | qxl->guest_surfaces.count--; | |
465 | } | |
14898cf6 | 466 | qemu_mutex_unlock(&qxl->track_lock); |
a19cbfb3 GH |
467 | break; |
468 | } | |
469 | case QXL_CMD_CURSOR: | |
470 | { | |
471 | QXLCursorCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id); | |
fae2afb1 AL |
472 | |
473 | if (!cmd) { | |
474 | return 1; | |
475 | } | |
a19cbfb3 | 476 | if (cmd->type == QXL_CURSOR_SET) { |
30f6da66 | 477 | qemu_mutex_lock(&qxl->track_lock); |
a19cbfb3 | 478 | qxl->guest_cursor = ext->cmd.data; |
30f6da66 | 479 | qemu_mutex_unlock(&qxl->track_lock); |
a19cbfb3 GH |
480 | } |
481 | break; | |
482 | } | |
483 | } | |
fae2afb1 | 484 | return 0; |
a19cbfb3 GH |
485 | } |
486 | ||
487 | /* spice display interface callbacks */ | |
488 | ||
489 | static void interface_attach_worker(QXLInstance *sin, QXLWorker *qxl_worker) | |
490 | { | |
491 | PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); | |
492 | ||
c480bb7d | 493 | trace_qxl_interface_attach_worker(qxl->id); |
a19cbfb3 GH |
494 | qxl->ssd.worker = qxl_worker; |
495 | } | |
496 | ||
497 | static void interface_set_compression_level(QXLInstance *sin, int level) | |
498 | { | |
499 | PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); | |
500 | ||
c480bb7d | 501 | trace_qxl_interface_set_compression_level(qxl->id, level); |
a19cbfb3 GH |
502 | qxl->shadow_rom.compression_level = cpu_to_le32(level); |
503 | qxl->rom->compression_level = cpu_to_le32(level); | |
504 | qxl_rom_set_dirty(qxl); | |
505 | } | |
506 | ||
507 | static void interface_set_mm_time(QXLInstance *sin, uint32_t mm_time) | |
508 | { | |
509 | PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); | |
510 | ||
c480bb7d | 511 | trace_qxl_interface_set_mm_time(qxl->id, mm_time); |
a19cbfb3 GH |
512 | qxl->shadow_rom.mm_clock = cpu_to_le32(mm_time); |
513 | qxl->rom->mm_clock = cpu_to_le32(mm_time); | |
514 | qxl_rom_set_dirty(qxl); | |
515 | } | |
516 | ||
517 | static void interface_get_init_info(QXLInstance *sin, QXLDevInitInfo *info) | |
518 | { | |
519 | PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); | |
520 | ||
c480bb7d | 521 | trace_qxl_interface_get_init_info(qxl->id); |
a19cbfb3 GH |
522 | info->memslot_gen_bits = MEMSLOT_GENERATION_BITS; |
523 | info->memslot_id_bits = MEMSLOT_SLOT_BITS; | |
524 | info->num_memslots = NUM_MEMSLOTS; | |
525 | info->num_memslots_groups = NUM_MEMSLOTS_GROUPS; | |
526 | info->internal_groupslot_id = 0; | |
527 | info->qxl_ram_size = le32_to_cpu(qxl->shadow_rom.num_pages) << TARGET_PAGE_BITS; | |
ddd8fdc7 | 528 | info->n_surfaces = qxl->ssd.num_surfaces; |
a19cbfb3 GH |
529 | } |
530 | ||
5b77870c AL |
531 | static const char *qxl_mode_to_string(int mode) |
532 | { | |
533 | switch (mode) { | |
534 | case QXL_MODE_COMPAT: | |
535 | return "compat"; | |
536 | case QXL_MODE_NATIVE: | |
537 | return "native"; | |
538 | case QXL_MODE_UNDEFINED: | |
539 | return "undefined"; | |
540 | case QXL_MODE_VGA: | |
541 | return "vga"; | |
542 | } | |
543 | return "INVALID"; | |
544 | } | |
545 | ||
8b92e298 AL |
546 | static const char *io_port_to_string(uint32_t io_port) |
547 | { | |
548 | if (io_port >= QXL_IO_RANGE_SIZE) { | |
549 | return "out of range"; | |
550 | } | |
551 | static const char *io_port_to_string[QXL_IO_RANGE_SIZE + 1] = { | |
552 | [QXL_IO_NOTIFY_CMD] = "QXL_IO_NOTIFY_CMD", | |
553 | [QXL_IO_NOTIFY_CURSOR] = "QXL_IO_NOTIFY_CURSOR", | |
554 | [QXL_IO_UPDATE_AREA] = "QXL_IO_UPDATE_AREA", | |
555 | [QXL_IO_UPDATE_IRQ] = "QXL_IO_UPDATE_IRQ", | |
556 | [QXL_IO_NOTIFY_OOM] = "QXL_IO_NOTIFY_OOM", | |
557 | [QXL_IO_RESET] = "QXL_IO_RESET", | |
558 | [QXL_IO_SET_MODE] = "QXL_IO_SET_MODE", | |
559 | [QXL_IO_LOG] = "QXL_IO_LOG", | |
560 | [QXL_IO_MEMSLOT_ADD] = "QXL_IO_MEMSLOT_ADD", | |
561 | [QXL_IO_MEMSLOT_DEL] = "QXL_IO_MEMSLOT_DEL", | |
562 | [QXL_IO_DETACH_PRIMARY] = "QXL_IO_DETACH_PRIMARY", | |
563 | [QXL_IO_ATTACH_PRIMARY] = "QXL_IO_ATTACH_PRIMARY", | |
564 | [QXL_IO_CREATE_PRIMARY] = "QXL_IO_CREATE_PRIMARY", | |
565 | [QXL_IO_DESTROY_PRIMARY] = "QXL_IO_DESTROY_PRIMARY", | |
566 | [QXL_IO_DESTROY_SURFACE_WAIT] = "QXL_IO_DESTROY_SURFACE_WAIT", | |
567 | [QXL_IO_DESTROY_ALL_SURFACES] = "QXL_IO_DESTROY_ALL_SURFACES", | |
8b92e298 AL |
568 | [QXL_IO_UPDATE_AREA_ASYNC] = "QXL_IO_UPDATE_AREA_ASYNC", |
569 | [QXL_IO_MEMSLOT_ADD_ASYNC] = "QXL_IO_MEMSLOT_ADD_ASYNC", | |
570 | [QXL_IO_CREATE_PRIMARY_ASYNC] = "QXL_IO_CREATE_PRIMARY_ASYNC", | |
571 | [QXL_IO_DESTROY_PRIMARY_ASYNC] = "QXL_IO_DESTROY_PRIMARY_ASYNC", | |
572 | [QXL_IO_DESTROY_SURFACE_ASYNC] = "QXL_IO_DESTROY_SURFACE_ASYNC", | |
573 | [QXL_IO_DESTROY_ALL_SURFACES_ASYNC] | |
574 | = "QXL_IO_DESTROY_ALL_SURFACES_ASYNC", | |
575 | [QXL_IO_FLUSH_SURFACES_ASYNC] = "QXL_IO_FLUSH_SURFACES_ASYNC", | |
576 | [QXL_IO_FLUSH_RELEASE] = "QXL_IO_FLUSH_RELEASE", | |
020af1c4 | 577 | [QXL_IO_MONITORS_CONFIG_ASYNC] = "QXL_IO_MONITORS_CONFIG_ASYNC", |
8b92e298 AL |
578 | }; |
579 | return io_port_to_string[io_port]; | |
580 | } | |
581 | ||
a19cbfb3 GH |
582 | /* called from spice server thread context only */ |
583 | static int interface_get_command(QXLInstance *sin, struct QXLCommandExt *ext) | |
584 | { | |
585 | PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); | |
586 | SimpleSpiceUpdate *update; | |
587 | QXLCommandRing *ring; | |
588 | QXLCommand *cmd; | |
e0c64d08 | 589 | int notify, ret; |
a19cbfb3 | 590 | |
c480bb7d AL |
591 | trace_qxl_ring_command_check(qxl->id, qxl_mode_to_string(qxl->mode)); |
592 | ||
a19cbfb3 GH |
593 | switch (qxl->mode) { |
594 | case QXL_MODE_VGA: | |
e0c64d08 GH |
595 | ret = false; |
596 | qemu_mutex_lock(&qxl->ssd.lock); | |
b1af98ba GH |
597 | update = QTAILQ_FIRST(&qxl->ssd.updates); |
598 | if (update != NULL) { | |
599 | QTAILQ_REMOVE(&qxl->ssd.updates, update, next); | |
e0c64d08 GH |
600 | *ext = update->ext; |
601 | ret = true; | |
a19cbfb3 | 602 | } |
e0c64d08 | 603 | qemu_mutex_unlock(&qxl->ssd.lock); |
212496c9 | 604 | if (ret) { |
c480bb7d | 605 | trace_qxl_ring_command_get(qxl->id, qxl_mode_to_string(qxl->mode)); |
212496c9 AL |
606 | qxl_log_command(qxl, "vga", ext); |
607 | } | |
e0c64d08 | 608 | return ret; |
a19cbfb3 GH |
609 | case QXL_MODE_COMPAT: |
610 | case QXL_MODE_NATIVE: | |
611 | case QXL_MODE_UNDEFINED: | |
a19cbfb3 | 612 | ring = &qxl->ram->cmd_ring; |
087e6a42 | 613 | if (qxl->guest_bug || SPICE_RING_IS_EMPTY(ring)) { |
a19cbfb3 GH |
614 | return false; |
615 | } | |
0b81c478 AL |
616 | SPICE_RING_CONS_ITEM(qxl, ring, cmd); |
617 | if (!cmd) { | |
618 | return false; | |
619 | } | |
a19cbfb3 GH |
620 | ext->cmd = *cmd; |
621 | ext->group_id = MEMSLOT_GROUP_GUEST; | |
622 | ext->flags = qxl->cmdflags; | |
623 | SPICE_RING_POP(ring, notify); | |
624 | qxl_ring_set_dirty(qxl); | |
625 | if (notify) { | |
626 | qxl_send_events(qxl, QXL_INTERRUPT_DISPLAY); | |
627 | } | |
628 | qxl->guest_primary.commands++; | |
629 | qxl_track_command(qxl, ext); | |
630 | qxl_log_command(qxl, "cmd", ext); | |
0b81c478 | 631 | trace_qxl_ring_command_get(qxl->id, qxl_mode_to_string(qxl->mode)); |
a19cbfb3 GH |
632 | return true; |
633 | default: | |
634 | return false; | |
635 | } | |
636 | } | |
637 | ||
638 | /* called from spice server thread context only */ | |
639 | static int interface_req_cmd_notification(QXLInstance *sin) | |
640 | { | |
641 | PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); | |
642 | int wait = 1; | |
643 | ||
c480bb7d | 644 | trace_qxl_ring_command_req_notification(qxl->id); |
a19cbfb3 GH |
645 | switch (qxl->mode) { |
646 | case QXL_MODE_COMPAT: | |
647 | case QXL_MODE_NATIVE: | |
648 | case QXL_MODE_UNDEFINED: | |
649 | SPICE_RING_CONS_WAIT(&qxl->ram->cmd_ring, wait); | |
650 | qxl_ring_set_dirty(qxl); | |
651 | break; | |
652 | default: | |
653 | /* nothing */ | |
654 | break; | |
655 | } | |
656 | return wait; | |
657 | } | |
658 | ||
659 | /* called from spice server thread context only */ | |
660 | static inline void qxl_push_free_res(PCIQXLDevice *d, int flush) | |
661 | { | |
662 | QXLReleaseRing *ring = &d->ram->release_ring; | |
663 | uint64_t *item; | |
664 | int notify; | |
665 | ||
666 | #define QXL_FREE_BUNCH_SIZE 32 | |
667 | ||
668 | if (ring->prod - ring->cons + 1 == ring->num_items) { | |
669 | /* ring full -- can't push */ | |
670 | return; | |
671 | } | |
672 | if (!flush && d->oom_running) { | |
673 | /* collect everything from oom handler before pushing */ | |
674 | return; | |
675 | } | |
676 | if (!flush && d->num_free_res < QXL_FREE_BUNCH_SIZE) { | |
677 | /* collect a bit more before pushing */ | |
678 | return; | |
679 | } | |
680 | ||
681 | SPICE_RING_PUSH(ring, notify); | |
c480bb7d AL |
682 | trace_qxl_ring_res_push(d->id, qxl_mode_to_string(d->mode), |
683 | d->guest_surfaces.count, d->num_free_res, | |
684 | d->last_release, notify ? "yes" : "no"); | |
685 | trace_qxl_ring_res_push_rest(d->id, ring->prod - ring->cons, | |
686 | ring->num_items, ring->prod, ring->cons); | |
a19cbfb3 GH |
687 | if (notify) { |
688 | qxl_send_events(d, QXL_INTERRUPT_DISPLAY); | |
689 | } | |
0b81c478 AL |
690 | SPICE_RING_PROD_ITEM(d, ring, item); |
691 | if (!item) { | |
692 | return; | |
693 | } | |
a19cbfb3 GH |
694 | *item = 0; |
695 | d->num_free_res = 0; | |
696 | d->last_release = NULL; | |
697 | qxl_ring_set_dirty(d); | |
698 | } | |
699 | ||
700 | /* called from spice server thread context only */ | |
701 | static void interface_release_resource(QXLInstance *sin, | |
702 | struct QXLReleaseInfoExt ext) | |
703 | { | |
704 | PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); | |
705 | QXLReleaseRing *ring; | |
706 | uint64_t *item, id; | |
707 | ||
708 | if (ext.group_id == MEMSLOT_GROUP_HOST) { | |
709 | /* host group -> vga mode update request */ | |
f4a8a424 | 710 | qemu_spice_destroy_update(&qxl->ssd, (void *)(intptr_t)ext.info->id); |
a19cbfb3 GH |
711 | return; |
712 | } | |
713 | ||
714 | /* | |
715 | * ext->info points into guest-visible memory | |
716 | * pci bar 0, $command.release_info | |
717 | */ | |
718 | ring = &qxl->ram->release_ring; | |
0b81c478 AL |
719 | SPICE_RING_PROD_ITEM(qxl, ring, item); |
720 | if (!item) { | |
721 | return; | |
722 | } | |
a19cbfb3 GH |
723 | if (*item == 0) { |
724 | /* stick head into the ring */ | |
725 | id = ext.info->id; | |
726 | ext.info->next = 0; | |
727 | qxl_ram_set_dirty(qxl, &ext.info->next); | |
728 | *item = id; | |
729 | qxl_ring_set_dirty(qxl); | |
730 | } else { | |
731 | /* append item to the list */ | |
732 | qxl->last_release->next = ext.info->id; | |
733 | qxl_ram_set_dirty(qxl, &qxl->last_release->next); | |
734 | ext.info->next = 0; | |
735 | qxl_ram_set_dirty(qxl, &ext.info->next); | |
736 | } | |
737 | qxl->last_release = ext.info; | |
738 | qxl->num_free_res++; | |
c480bb7d | 739 | trace_qxl_ring_res_put(qxl->id, qxl->num_free_res); |
a19cbfb3 GH |
740 | qxl_push_free_res(qxl, 0); |
741 | } | |
742 | ||
743 | /* called from spice server thread context only */ | |
744 | static int interface_get_cursor_command(QXLInstance *sin, struct QXLCommandExt *ext) | |
745 | { | |
746 | PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); | |
747 | QXLCursorRing *ring; | |
748 | QXLCommand *cmd; | |
749 | int notify; | |
750 | ||
c480bb7d AL |
751 | trace_qxl_ring_cursor_check(qxl->id, qxl_mode_to_string(qxl->mode)); |
752 | ||
a19cbfb3 GH |
753 | switch (qxl->mode) { |
754 | case QXL_MODE_COMPAT: | |
755 | case QXL_MODE_NATIVE: | |
756 | case QXL_MODE_UNDEFINED: | |
757 | ring = &qxl->ram->cursor_ring; | |
758 | if (SPICE_RING_IS_EMPTY(ring)) { | |
759 | return false; | |
760 | } | |
0b81c478 AL |
761 | SPICE_RING_CONS_ITEM(qxl, ring, cmd); |
762 | if (!cmd) { | |
763 | return false; | |
764 | } | |
a19cbfb3 GH |
765 | ext->cmd = *cmd; |
766 | ext->group_id = MEMSLOT_GROUP_GUEST; | |
767 | ext->flags = qxl->cmdflags; | |
768 | SPICE_RING_POP(ring, notify); | |
769 | qxl_ring_set_dirty(qxl); | |
770 | if (notify) { | |
771 | qxl_send_events(qxl, QXL_INTERRUPT_CURSOR); | |
772 | } | |
773 | qxl->guest_primary.commands++; | |
774 | qxl_track_command(qxl, ext); | |
775 | qxl_log_command(qxl, "csr", ext); | |
776 | if (qxl->id == 0) { | |
777 | qxl_render_cursor(qxl, ext); | |
778 | } | |
c480bb7d | 779 | trace_qxl_ring_cursor_get(qxl->id, qxl_mode_to_string(qxl->mode)); |
a19cbfb3 GH |
780 | return true; |
781 | default: | |
782 | return false; | |
783 | } | |
784 | } | |
785 | ||
786 | /* called from spice server thread context only */ | |
787 | static int interface_req_cursor_notification(QXLInstance *sin) | |
788 | { | |
789 | PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); | |
790 | int wait = 1; | |
791 | ||
c480bb7d | 792 | trace_qxl_ring_cursor_req_notification(qxl->id); |
a19cbfb3 GH |
793 | switch (qxl->mode) { |
794 | case QXL_MODE_COMPAT: | |
795 | case QXL_MODE_NATIVE: | |
796 | case QXL_MODE_UNDEFINED: | |
797 | SPICE_RING_CONS_WAIT(&qxl->ram->cursor_ring, wait); | |
798 | qxl_ring_set_dirty(qxl); | |
799 | break; | |
800 | default: | |
801 | /* nothing */ | |
802 | break; | |
803 | } | |
804 | return wait; | |
805 | } | |
806 | ||
807 | /* called from spice server thread context */ | |
808 | static void interface_notify_update(QXLInstance *sin, uint32_t update_id) | |
809 | { | |
baeae407 AL |
810 | /* |
811 | * Called by spice-server as a result of a QXL_CMD_UPDATE which is not in | |
812 | * use by xf86-video-qxl and is defined out in the qxl windows driver. | |
813 | * Probably was at some earlier version that is prior to git start (2009), | |
814 | * and is still guest trigerrable. | |
815 | */ | |
816 | fprintf(stderr, "%s: deprecated\n", __func__); | |
a19cbfb3 GH |
817 | } |
818 | ||
819 | /* called from spice server thread context only */ | |
820 | static int interface_flush_resources(QXLInstance *sin) | |
821 | { | |
822 | PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); | |
823 | int ret; | |
824 | ||
a19cbfb3 GH |
825 | ret = qxl->num_free_res; |
826 | if (ret) { | |
827 | qxl_push_free_res(qxl, 1); | |
828 | } | |
829 | return ret; | |
830 | } | |
831 | ||
5ff4e36c AL |
832 | static void qxl_create_guest_primary_complete(PCIQXLDevice *d); |
833 | ||
5ff4e36c | 834 | /* called from spice server thread context only */ |
2e1a98c9 | 835 | static void interface_async_complete_io(PCIQXLDevice *qxl, QXLCookie *cookie) |
5ff4e36c | 836 | { |
5ff4e36c AL |
837 | uint32_t current_async; |
838 | ||
839 | qemu_mutex_lock(&qxl->async_lock); | |
840 | current_async = qxl->current_async; | |
841 | qxl->current_async = QXL_UNDEFINED_IO; | |
842 | qemu_mutex_unlock(&qxl->async_lock); | |
843 | ||
c480bb7d | 844 | trace_qxl_interface_async_complete_io(qxl->id, current_async, cookie); |
2e1a98c9 AL |
845 | if (!cookie) { |
846 | fprintf(stderr, "qxl: %s: error, cookie is NULL\n", __func__); | |
847 | return; | |
848 | } | |
849 | if (cookie && current_async != cookie->io) { | |
850 | fprintf(stderr, | |
2fce7edf AL |
851 | "qxl: %s: error: current_async = %d != %" |
852 | PRId64 " = cookie->io\n", __func__, current_async, cookie->io); | |
2e1a98c9 | 853 | } |
5ff4e36c | 854 | switch (current_async) { |
81fb6f15 AL |
855 | case QXL_IO_MEMSLOT_ADD_ASYNC: |
856 | case QXL_IO_DESTROY_PRIMARY_ASYNC: | |
857 | case QXL_IO_UPDATE_AREA_ASYNC: | |
858 | case QXL_IO_FLUSH_SURFACES_ASYNC: | |
020af1c4 | 859 | case QXL_IO_MONITORS_CONFIG_ASYNC: |
81fb6f15 | 860 | break; |
5ff4e36c AL |
861 | case QXL_IO_CREATE_PRIMARY_ASYNC: |
862 | qxl_create_guest_primary_complete(qxl); | |
863 | break; | |
864 | case QXL_IO_DESTROY_ALL_SURFACES_ASYNC: | |
865 | qxl_spice_destroy_surfaces_complete(qxl); | |
866 | break; | |
867 | case QXL_IO_DESTROY_SURFACE_ASYNC: | |
2e1a98c9 | 868 | qxl_spice_destroy_surface_wait_complete(qxl, cookie->u.surface_id); |
5ff4e36c | 869 | break; |
81fb6f15 AL |
870 | default: |
871 | fprintf(stderr, "qxl: %s: unexpected current_async %d\n", __func__, | |
872 | current_async); | |
5ff4e36c AL |
873 | } |
874 | qxl_send_events(qxl, QXL_INTERRUPT_IO_CMD); | |
875 | } | |
876 | ||
81fb6f15 AL |
877 | /* called from spice server thread context only */ |
878 | static void interface_update_area_complete(QXLInstance *sin, | |
879 | uint32_t surface_id, | |
880 | QXLRect *dirty, uint32_t num_updated_rects) | |
881 | { | |
882 | PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); | |
883 | int i; | |
884 | int qxl_i; | |
885 | ||
886 | qemu_mutex_lock(&qxl->ssd.lock); | |
887 | if (surface_id != 0 || !qxl->render_update_cookie_num) { | |
888 | qemu_mutex_unlock(&qxl->ssd.lock); | |
889 | return; | |
890 | } | |
c480bb7d AL |
891 | trace_qxl_interface_update_area_complete(qxl->id, surface_id, dirty->left, |
892 | dirty->right, dirty->top, dirty->bottom); | |
893 | trace_qxl_interface_update_area_complete_rest(qxl->id, num_updated_rects); | |
81fb6f15 AL |
894 | if (qxl->num_dirty_rects + num_updated_rects > QXL_NUM_DIRTY_RECTS) { |
895 | /* | |
896 | * overflow - treat this as a full update. Not expected to be common. | |
897 | */ | |
c480bb7d AL |
898 | trace_qxl_interface_update_area_complete_overflow(qxl->id, |
899 | QXL_NUM_DIRTY_RECTS); | |
81fb6f15 AL |
900 | qxl->guest_primary.resized = 1; |
901 | } | |
902 | if (qxl->guest_primary.resized) { | |
903 | /* | |
904 | * Don't bother copying or scheduling the bh since we will flip | |
905 | * the whole area anyway on completion of the update_area async call | |
906 | */ | |
907 | qemu_mutex_unlock(&qxl->ssd.lock); | |
908 | return; | |
909 | } | |
910 | qxl_i = qxl->num_dirty_rects; | |
911 | for (i = 0; i < num_updated_rects; i++) { | |
912 | qxl->dirty[qxl_i++] = dirty[i]; | |
913 | } | |
914 | qxl->num_dirty_rects += num_updated_rects; | |
c480bb7d AL |
915 | trace_qxl_interface_update_area_complete_schedule_bh(qxl->id, |
916 | qxl->num_dirty_rects); | |
81fb6f15 AL |
917 | qemu_bh_schedule(qxl->update_area_bh); |
918 | qemu_mutex_unlock(&qxl->ssd.lock); | |
919 | } | |
920 | ||
2e1a98c9 AL |
921 | /* called from spice server thread context only */ |
922 | static void interface_async_complete(QXLInstance *sin, uint64_t cookie_token) | |
923 | { | |
924 | PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); | |
5dba0d45 | 925 | QXLCookie *cookie = (QXLCookie *)(uintptr_t)cookie_token; |
2e1a98c9 AL |
926 | |
927 | switch (cookie->type) { | |
928 | case QXL_COOKIE_TYPE_IO: | |
929 | interface_async_complete_io(qxl, cookie); | |
81fb6f15 AL |
930 | g_free(cookie); |
931 | break; | |
932 | case QXL_COOKIE_TYPE_RENDER_UPDATE_AREA: | |
933 | qxl_render_update_area_done(qxl, cookie); | |
2e1a98c9 | 934 | break; |
020af1c4 AL |
935 | case QXL_COOKIE_TYPE_POST_LOAD_MONITORS_CONFIG: |
936 | break; | |
2e1a98c9 AL |
937 | default: |
938 | fprintf(stderr, "qxl: %s: unexpected cookie type %d\n", | |
939 | __func__, cookie->type); | |
81fb6f15 | 940 | g_free(cookie); |
2e1a98c9 | 941 | } |
2e1a98c9 AL |
942 | } |
943 | ||
c10018d6 SSP |
944 | /* called from spice server thread context only */ |
945 | static void interface_set_client_capabilities(QXLInstance *sin, | |
946 | uint8_t client_present, | |
947 | uint8_t caps[58]) | |
948 | { | |
949 | PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); | |
950 | ||
e0ac6097 AL |
951 | if (qxl->revision < 4) { |
952 | trace_qxl_set_client_capabilities_unsupported_by_revision(qxl->id, | |
953 | qxl->revision); | |
954 | return; | |
955 | } | |
956 | ||
ab902981 HG |
957 | if (runstate_check(RUN_STATE_INMIGRATE) || |
958 | runstate_check(RUN_STATE_POSTMIGRATE)) { | |
959 | return; | |
960 | } | |
961 | ||
c10018d6 | 962 | qxl->shadow_rom.client_present = client_present; |
08688af0 MA |
963 | memcpy(qxl->shadow_rom.client_capabilities, caps, |
964 | sizeof(qxl->shadow_rom.client_capabilities)); | |
c10018d6 | 965 | qxl->rom->client_present = client_present; |
08688af0 MA |
966 | memcpy(qxl->rom->client_capabilities, caps, |
967 | sizeof(qxl->rom->client_capabilities)); | |
c10018d6 SSP |
968 | qxl_rom_set_dirty(qxl); |
969 | ||
970 | qxl_send_events(qxl, QXL_INTERRUPT_CLIENT); | |
971 | } | |
972 | ||
a639ab04 AL |
973 | static uint32_t qxl_crc32(const uint8_t *p, unsigned len) |
974 | { | |
975 | /* | |
976 | * zlib xors the seed with 0xffffffff, and xors the result | |
977 | * again with 0xffffffff; Both are not done with linux's crc32, | |
978 | * which we want to be compatible with, so undo that. | |
979 | */ | |
980 | return crc32(0xffffffff, p, len) ^ 0xffffffff; | |
981 | } | |
982 | ||
983 | /* called from main context only */ | |
984 | static int interface_client_monitors_config(QXLInstance *sin, | |
985 | VDAgentMonitorsConfig *monitors_config) | |
986 | { | |
987 | PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); | |
988 | QXLRom *rom = memory_region_get_ram_ptr(&qxl->rom_bar); | |
989 | int i; | |
990 | ||
e0ac6097 AL |
991 | if (qxl->revision < 4) { |
992 | trace_qxl_client_monitors_config_unsupported_by_device(qxl->id, | |
993 | qxl->revision); | |
994 | return 0; | |
995 | } | |
a639ab04 AL |
996 | /* |
997 | * Older windows drivers set int_mask to 0 when their ISR is called, | |
998 | * then later set it to ~0. So it doesn't relate to the actual interrupts | |
999 | * handled. However, they are old, so clearly they don't support this | |
1000 | * interrupt | |
1001 | */ | |
1002 | if (qxl->ram->int_mask == 0 || qxl->ram->int_mask == ~0 || | |
1003 | !(qxl->ram->int_mask & QXL_INTERRUPT_CLIENT_MONITORS_CONFIG)) { | |
1004 | trace_qxl_client_monitors_config_unsupported_by_guest(qxl->id, | |
1005 | qxl->ram->int_mask, | |
1006 | monitors_config); | |
1007 | return 0; | |
1008 | } | |
1009 | if (!monitors_config) { | |
1010 | return 1; | |
1011 | } | |
1012 | memset(&rom->client_monitors_config, 0, | |
1013 | sizeof(rom->client_monitors_config)); | |
1014 | rom->client_monitors_config.count = monitors_config->num_of_monitors; | |
1015 | /* monitors_config->flags ignored */ | |
1016 | if (rom->client_monitors_config.count >= | |
1017 | ARRAY_SIZE(rom->client_monitors_config.heads)) { | |
1018 | trace_qxl_client_monitors_config_capped(qxl->id, | |
1019 | monitors_config->num_of_monitors, | |
1020 | ARRAY_SIZE(rom->client_monitors_config.heads)); | |
1021 | rom->client_monitors_config.count = | |
1022 | ARRAY_SIZE(rom->client_monitors_config.heads); | |
1023 | } | |
1024 | for (i = 0 ; i < rom->client_monitors_config.count ; ++i) { | |
1025 | VDAgentMonConfig *monitor = &monitors_config->monitors[i]; | |
1026 | QXLURect *rect = &rom->client_monitors_config.heads[i]; | |
1027 | /* monitor->depth ignored */ | |
1028 | rect->left = monitor->x; | |
1029 | rect->top = monitor->y; | |
1030 | rect->right = monitor->x + monitor->width; | |
1031 | rect->bottom = monitor->y + monitor->height; | |
1032 | } | |
1033 | rom->client_monitors_config_crc = qxl_crc32( | |
1034 | (const uint8_t *)&rom->client_monitors_config, | |
1035 | sizeof(rom->client_monitors_config)); | |
1036 | trace_qxl_client_monitors_config_crc(qxl->id, | |
1037 | sizeof(rom->client_monitors_config), | |
1038 | rom->client_monitors_config_crc); | |
1039 | ||
1040 | trace_qxl_interrupt_client_monitors_config(qxl->id, | |
1041 | rom->client_monitors_config.count, | |
1042 | rom->client_monitors_config.heads); | |
1043 | qxl_send_events(qxl, QXL_INTERRUPT_CLIENT_MONITORS_CONFIG); | |
1044 | return 1; | |
1045 | } | |
a639ab04 | 1046 | |
a19cbfb3 GH |
1047 | static const QXLInterface qxl_interface = { |
1048 | .base.type = SPICE_INTERFACE_QXL, | |
1049 | .base.description = "qxl gpu", | |
1050 | .base.major_version = SPICE_INTERFACE_QXL_MAJOR, | |
1051 | .base.minor_version = SPICE_INTERFACE_QXL_MINOR, | |
1052 | ||
1053 | .attache_worker = interface_attach_worker, | |
1054 | .set_compression_level = interface_set_compression_level, | |
1055 | .set_mm_time = interface_set_mm_time, | |
1056 | .get_init_info = interface_get_init_info, | |
1057 | ||
1058 | /* the callbacks below are called from spice server thread context */ | |
1059 | .get_command = interface_get_command, | |
1060 | .req_cmd_notification = interface_req_cmd_notification, | |
1061 | .release_resource = interface_release_resource, | |
1062 | .get_cursor_command = interface_get_cursor_command, | |
1063 | .req_cursor_notification = interface_req_cursor_notification, | |
1064 | .notify_update = interface_notify_update, | |
1065 | .flush_resources = interface_flush_resources, | |
5ff4e36c | 1066 | .async_complete = interface_async_complete, |
81fb6f15 | 1067 | .update_area_complete = interface_update_area_complete, |
c10018d6 | 1068 | .set_client_capabilities = interface_set_client_capabilities, |
a639ab04 | 1069 | .client_monitors_config = interface_client_monitors_config, |
a19cbfb3 GH |
1070 | }; |
1071 | ||
1072 | static void qxl_enter_vga_mode(PCIQXLDevice *d) | |
1073 | { | |
1074 | if (d->mode == QXL_MODE_VGA) { | |
1075 | return; | |
1076 | } | |
c480bb7d | 1077 | trace_qxl_enter_vga_mode(d->id); |
a19cbfb3 GH |
1078 | qemu_spice_create_host_primary(&d->ssd); |
1079 | d->mode = QXL_MODE_VGA; | |
0f7bfd81 | 1080 | vga_dirty_log_start(&d->vga); |
c099e7aa | 1081 | vga_hw_update(); |
a19cbfb3 GH |
1082 | } |
1083 | ||
1084 | static void qxl_exit_vga_mode(PCIQXLDevice *d) | |
1085 | { | |
1086 | if (d->mode != QXL_MODE_VGA) { | |
1087 | return; | |
1088 | } | |
c480bb7d | 1089 | trace_qxl_exit_vga_mode(d->id); |
0f7bfd81 | 1090 | vga_dirty_log_stop(&d->vga); |
5ff4e36c | 1091 | qxl_destroy_primary(d, QXL_SYNC); |
a19cbfb3 GH |
1092 | } |
1093 | ||
40010aea | 1094 | static void qxl_update_irq(PCIQXLDevice *d) |
a19cbfb3 GH |
1095 | { |
1096 | uint32_t pending = le32_to_cpu(d->ram->int_pending); | |
1097 | uint32_t mask = le32_to_cpu(d->ram->int_mask); | |
1098 | int level = !!(pending & mask); | |
1099 | qemu_set_irq(d->pci.irq[0], level); | |
1100 | qxl_ring_set_dirty(d); | |
1101 | } | |
1102 | ||
a19cbfb3 GH |
1103 | static void qxl_check_state(PCIQXLDevice *d) |
1104 | { | |
1105 | QXLRam *ram = d->ram; | |
71d388d4 | 1106 | int spice_display_running = qemu_spice_display_is_running(&d->ssd); |
a19cbfb3 | 1107 | |
71d388d4 YH |
1108 | assert(!spice_display_running || SPICE_RING_IS_EMPTY(&ram->cmd_ring)); |
1109 | assert(!spice_display_running || SPICE_RING_IS_EMPTY(&ram->cursor_ring)); | |
a19cbfb3 GH |
1110 | } |
1111 | ||
1112 | static void qxl_reset_state(PCIQXLDevice *d) | |
1113 | { | |
a19cbfb3 GH |
1114 | QXLRom *rom = d->rom; |
1115 | ||
be48e995 | 1116 | qxl_check_state(d); |
a19cbfb3 GH |
1117 | d->shadow_rom.update_id = cpu_to_le32(0); |
1118 | *rom = d->shadow_rom; | |
1119 | qxl_rom_set_dirty(d); | |
1120 | init_qxl_ram(d); | |
1121 | d->num_free_res = 0; | |
1122 | d->last_release = NULL; | |
1123 | memset(&d->ssd.dirty, 0, sizeof(d->ssd.dirty)); | |
1124 | } | |
1125 | ||
1126 | static void qxl_soft_reset(PCIQXLDevice *d) | |
1127 | { | |
c480bb7d | 1128 | trace_qxl_soft_reset(d->id); |
a19cbfb3 | 1129 | qxl_check_state(d); |
087e6a42 | 1130 | qxl_clear_guest_bug(d); |
a5f68c22 | 1131 | d->current_async = QXL_UNDEFINED_IO; |
a19cbfb3 GH |
1132 | |
1133 | if (d->id == 0) { | |
1134 | qxl_enter_vga_mode(d); | |
1135 | } else { | |
1136 | d->mode = QXL_MODE_UNDEFINED; | |
1137 | } | |
1138 | } | |
1139 | ||
1140 | static void qxl_hard_reset(PCIQXLDevice *d, int loadvm) | |
1141 | { | |
c480bb7d | 1142 | trace_qxl_hard_reset(d->id, loadvm); |
a19cbfb3 | 1143 | |
aee32bf3 GH |
1144 | qxl_spice_reset_cursor(d); |
1145 | qxl_spice_reset_image_cache(d); | |
a19cbfb3 GH |
1146 | qxl_reset_surfaces(d); |
1147 | qxl_reset_memslots(d); | |
1148 | ||
1149 | /* pre loadvm reset must not touch QXLRam. This lives in | |
1150 | * device memory, is migrated together with RAM and thus | |
1151 | * already loaded at this point */ | |
1152 | if (!loadvm) { | |
1153 | qxl_reset_state(d); | |
1154 | } | |
1155 | qemu_spice_create_host_memslot(&d->ssd); | |
1156 | qxl_soft_reset(d); | |
a19cbfb3 GH |
1157 | } |
1158 | ||
1159 | static void qxl_reset_handler(DeviceState *dev) | |
1160 | { | |
1161 | PCIQXLDevice *d = DO_UPCAST(PCIQXLDevice, pci.qdev, dev); | |
c480bb7d | 1162 | |
a19cbfb3 GH |
1163 | qxl_hard_reset(d, 0); |
1164 | } | |
1165 | ||
1166 | static void qxl_vga_ioport_write(void *opaque, uint32_t addr, uint32_t val) | |
1167 | { | |
1168 | VGACommonState *vga = opaque; | |
1169 | PCIQXLDevice *qxl = container_of(vga, PCIQXLDevice, vga); | |
1170 | ||
c480bb7d | 1171 | trace_qxl_io_write_vga(qxl->id, qxl_mode_to_string(qxl->mode), addr, val); |
a19cbfb3 | 1172 | if (qxl->mode != QXL_MODE_VGA) { |
5ff4e36c | 1173 | qxl_destroy_primary(qxl, QXL_SYNC); |
a19cbfb3 GH |
1174 | qxl_soft_reset(qxl); |
1175 | } | |
1176 | vga_ioport_write(opaque, addr, val); | |
1177 | } | |
1178 | ||
f67ab77a GH |
1179 | static const MemoryRegionPortio qxl_vga_portio_list[] = { |
1180 | { 0x04, 2, 1, .read = vga_ioport_read, | |
1181 | .write = qxl_vga_ioport_write }, /* 3b4 */ | |
1182 | { 0x0a, 1, 1, .read = vga_ioport_read, | |
1183 | .write = qxl_vga_ioport_write }, /* 3ba */ | |
1184 | { 0x10, 16, 1, .read = vga_ioport_read, | |
1185 | .write = qxl_vga_ioport_write }, /* 3c0 */ | |
1186 | { 0x24, 2, 1, .read = vga_ioport_read, | |
1187 | .write = qxl_vga_ioport_write }, /* 3d4 */ | |
1188 | { 0x2a, 1, 1, .read = vga_ioport_read, | |
1189 | .write = qxl_vga_ioport_write }, /* 3da */ | |
1190 | PORTIO_END_OF_LIST(), | |
1191 | }; | |
1192 | ||
e954ea28 AL |
1193 | static int qxl_add_memslot(PCIQXLDevice *d, uint32_t slot_id, uint64_t delta, |
1194 | qxl_async_io async) | |
a19cbfb3 GH |
1195 | { |
1196 | static const int regions[] = { | |
1197 | QXL_RAM_RANGE_INDEX, | |
1198 | QXL_VRAM_RANGE_INDEX, | |
6f2b175a | 1199 | QXL_VRAM64_RANGE_INDEX, |
a19cbfb3 GH |
1200 | }; |
1201 | uint64_t guest_start; | |
1202 | uint64_t guest_end; | |
1203 | int pci_region; | |
1204 | pcibus_t pci_start; | |
1205 | pcibus_t pci_end; | |
1206 | intptr_t virt_start; | |
1207 | QXLDevMemSlot memslot; | |
1208 | int i; | |
1209 | ||
1210 | guest_start = le64_to_cpu(d->guest_slots[slot_id].slot.mem_start); | |
1211 | guest_end = le64_to_cpu(d->guest_slots[slot_id].slot.mem_end); | |
1212 | ||
c480bb7d | 1213 | trace_qxl_memslot_add_guest(d->id, slot_id, guest_start, guest_end); |
a19cbfb3 | 1214 | |
e954ea28 | 1215 | if (slot_id >= NUM_MEMSLOTS) { |
0a530548 | 1216 | qxl_set_guest_bug(d, "%s: slot_id >= NUM_MEMSLOTS %d >= %d", __func__, |
e954ea28 AL |
1217 | slot_id, NUM_MEMSLOTS); |
1218 | return 1; | |
1219 | } | |
1220 | if (guest_start > guest_end) { | |
0a530548 | 1221 | qxl_set_guest_bug(d, "%s: guest_start > guest_end 0x%" PRIx64 |
e954ea28 AL |
1222 | " > 0x%" PRIx64, __func__, guest_start, guest_end); |
1223 | return 1; | |
1224 | } | |
a19cbfb3 GH |
1225 | |
1226 | for (i = 0; i < ARRAY_SIZE(regions); i++) { | |
1227 | pci_region = regions[i]; | |
1228 | pci_start = d->pci.io_regions[pci_region].addr; | |
1229 | pci_end = pci_start + d->pci.io_regions[pci_region].size; | |
1230 | /* mapped? */ | |
1231 | if (pci_start == -1) { | |
1232 | continue; | |
1233 | } | |
1234 | /* start address in range ? */ | |
1235 | if (guest_start < pci_start || guest_start > pci_end) { | |
1236 | continue; | |
1237 | } | |
1238 | /* end address in range ? */ | |
1239 | if (guest_end > pci_end) { | |
1240 | continue; | |
1241 | } | |
1242 | /* passed */ | |
1243 | break; | |
1244 | } | |
e954ea28 | 1245 | if (i == ARRAY_SIZE(regions)) { |
0a530548 | 1246 | qxl_set_guest_bug(d, "%s: finished loop without match", __func__); |
e954ea28 AL |
1247 | return 1; |
1248 | } | |
a19cbfb3 GH |
1249 | |
1250 | switch (pci_region) { | |
1251 | case QXL_RAM_RANGE_INDEX: | |
b1950430 | 1252 | virt_start = (intptr_t)memory_region_get_ram_ptr(&d->vga.vram); |
a19cbfb3 GH |
1253 | break; |
1254 | case QXL_VRAM_RANGE_INDEX: | |
6f2b175a | 1255 | case 4 /* vram 64bit */: |
b1950430 | 1256 | virt_start = (intptr_t)memory_region_get_ram_ptr(&d->vram_bar); |
a19cbfb3 GH |
1257 | break; |
1258 | default: | |
1259 | /* should not happen */ | |
0a530548 | 1260 | qxl_set_guest_bug(d, "%s: pci_region = %d", __func__, pci_region); |
e954ea28 | 1261 | return 1; |
a19cbfb3 GH |
1262 | } |
1263 | ||
1264 | memslot.slot_id = slot_id; | |
1265 | memslot.slot_group_id = MEMSLOT_GROUP_GUEST; /* guest group */ | |
1266 | memslot.virt_start = virt_start + (guest_start - pci_start); | |
1267 | memslot.virt_end = virt_start + (guest_end - pci_start); | |
1268 | memslot.addr_delta = memslot.virt_start - delta; | |
1269 | memslot.generation = d->rom->slot_generation = 0; | |
1270 | qxl_rom_set_dirty(d); | |
1271 | ||
5ff4e36c | 1272 | qemu_spice_add_memslot(&d->ssd, &memslot, async); |
a19cbfb3 GH |
1273 | d->guest_slots[slot_id].ptr = (void*)memslot.virt_start; |
1274 | d->guest_slots[slot_id].size = memslot.virt_end - memslot.virt_start; | |
1275 | d->guest_slots[slot_id].delta = delta; | |
1276 | d->guest_slots[slot_id].active = 1; | |
e954ea28 | 1277 | return 0; |
a19cbfb3 GH |
1278 | } |
1279 | ||
1280 | static void qxl_del_memslot(PCIQXLDevice *d, uint32_t slot_id) | |
1281 | { | |
5c59d118 | 1282 | qemu_spice_del_memslot(&d->ssd, MEMSLOT_GROUP_HOST, slot_id); |
a19cbfb3 GH |
1283 | d->guest_slots[slot_id].active = 0; |
1284 | } | |
1285 | ||
1286 | static void qxl_reset_memslots(PCIQXLDevice *d) | |
1287 | { | |
aee32bf3 | 1288 | qxl_spice_reset_memslots(d); |
a19cbfb3 GH |
1289 | memset(&d->guest_slots, 0, sizeof(d->guest_slots)); |
1290 | } | |
1291 | ||
1292 | static void qxl_reset_surfaces(PCIQXLDevice *d) | |
1293 | { | |
c480bb7d | 1294 | trace_qxl_reset_surfaces(d->id); |
a19cbfb3 | 1295 | d->mode = QXL_MODE_UNDEFINED; |
5ff4e36c | 1296 | qxl_spice_destroy_surfaces(d, QXL_SYNC); |
a19cbfb3 GH |
1297 | } |
1298 | ||
e25139b3 | 1299 | /* can be also called from spice server thread context */ |
a19cbfb3 GH |
1300 | void *qxl_phys2virt(PCIQXLDevice *qxl, QXLPHYSICAL pqxl, int group_id) |
1301 | { | |
1302 | uint64_t phys = le64_to_cpu(pqxl); | |
1303 | uint32_t slot = (phys >> (64 - 8)) & 0xff; | |
1304 | uint64_t offset = phys & 0xffffffffffff; | |
1305 | ||
1306 | switch (group_id) { | |
1307 | case MEMSLOT_GROUP_HOST: | |
f4a8a424 | 1308 | return (void *)(intptr_t)offset; |
a19cbfb3 | 1309 | case MEMSLOT_GROUP_GUEST: |
4b635c59 | 1310 | if (slot >= NUM_MEMSLOTS) { |
0a530548 AL |
1311 | qxl_set_guest_bug(qxl, "slot too large %d >= %d", slot, |
1312 | NUM_MEMSLOTS); | |
4b635c59 AL |
1313 | return NULL; |
1314 | } | |
1315 | if (!qxl->guest_slots[slot].active) { | |
0a530548 | 1316 | qxl_set_guest_bug(qxl, "inactive slot %d\n", slot); |
4b635c59 AL |
1317 | return NULL; |
1318 | } | |
1319 | if (offset < qxl->guest_slots[slot].delta) { | |
0a530548 AL |
1320 | qxl_set_guest_bug(qxl, |
1321 | "slot %d offset %"PRIu64" < delta %"PRIu64"\n", | |
4b635c59 AL |
1322 | slot, offset, qxl->guest_slots[slot].delta); |
1323 | return NULL; | |
1324 | } | |
a19cbfb3 | 1325 | offset -= qxl->guest_slots[slot].delta; |
4b635c59 | 1326 | if (offset > qxl->guest_slots[slot].size) { |
0a530548 AL |
1327 | qxl_set_guest_bug(qxl, |
1328 | "slot %d offset %"PRIu64" > size %"PRIu64"\n", | |
4b635c59 AL |
1329 | slot, offset, qxl->guest_slots[slot].size); |
1330 | return NULL; | |
1331 | } | |
a19cbfb3 | 1332 | return qxl->guest_slots[slot].ptr + offset; |
a19cbfb3 | 1333 | } |
4b635c59 | 1334 | return NULL; |
a19cbfb3 GH |
1335 | } |
1336 | ||
5ff4e36c AL |
1337 | static void qxl_create_guest_primary_complete(PCIQXLDevice *qxl) |
1338 | { | |
1339 | /* for local rendering */ | |
1340 | qxl_render_resize(qxl); | |
1341 | } | |
1342 | ||
1343 | static void qxl_create_guest_primary(PCIQXLDevice *qxl, int loadvm, | |
1344 | qxl_async_io async) | |
a19cbfb3 GH |
1345 | { |
1346 | QXLDevSurfaceCreate surface; | |
1347 | QXLSurfaceCreate *sc = &qxl->guest_primary.surface; | |
13d1fd44 AL |
1348 | int size; |
1349 | int requested_height = le32_to_cpu(sc->height); | |
1350 | int requested_stride = le32_to_cpu(sc->stride); | |
1351 | ||
1352 | size = abs(requested_stride) * requested_height; | |
1353 | if (size > qxl->vgamem_size) { | |
1354 | qxl_set_guest_bug(qxl, "%s: requested primary larger then framebuffer" | |
1355 | " size", __func__); | |
1356 | return; | |
1357 | } | |
a19cbfb3 | 1358 | |
ddf9f4b7 | 1359 | if (qxl->mode == QXL_MODE_NATIVE) { |
0a530548 | 1360 | qxl_set_guest_bug(qxl, "%s: nop since already in QXL_MODE_NATIVE", |
ddf9f4b7 AL |
1361 | __func__); |
1362 | } | |
a19cbfb3 GH |
1363 | qxl_exit_vga_mode(qxl); |
1364 | ||
a19cbfb3 GH |
1365 | surface.format = le32_to_cpu(sc->format); |
1366 | surface.height = le32_to_cpu(sc->height); | |
1367 | surface.mem = le64_to_cpu(sc->mem); | |
1368 | surface.position = le32_to_cpu(sc->position); | |
1369 | surface.stride = le32_to_cpu(sc->stride); | |
1370 | surface.width = le32_to_cpu(sc->width); | |
1371 | surface.type = le32_to_cpu(sc->type); | |
1372 | surface.flags = le32_to_cpu(sc->flags); | |
c480bb7d AL |
1373 | trace_qxl_create_guest_primary(qxl->id, sc->width, sc->height, sc->mem, |
1374 | sc->format, sc->position); | |
1375 | trace_qxl_create_guest_primary_rest(qxl->id, sc->stride, sc->type, | |
1376 | sc->flags); | |
a19cbfb3 | 1377 | |
48f4ba67 AL |
1378 | if ((surface.stride & 0x3) != 0) { |
1379 | qxl_set_guest_bug(qxl, "primary surface stride = %d %% 4 != 0", | |
1380 | surface.stride); | |
1381 | return; | |
1382 | } | |
1383 | ||
a19cbfb3 GH |
1384 | surface.mouse_mode = true; |
1385 | surface.group_id = MEMSLOT_GROUP_GUEST; | |
1386 | if (loadvm) { | |
1387 | surface.flags |= QXL_SURF_FLAG_KEEP_DATA; | |
1388 | } | |
1389 | ||
1390 | qxl->mode = QXL_MODE_NATIVE; | |
1391 | qxl->cmdflags = 0; | |
5ff4e36c | 1392 | qemu_spice_create_primary_surface(&qxl->ssd, 0, &surface, async); |
a19cbfb3 | 1393 | |
5ff4e36c AL |
1394 | if (async == QXL_SYNC) { |
1395 | qxl_create_guest_primary_complete(qxl); | |
1396 | } | |
a19cbfb3 GH |
1397 | } |
1398 | ||
5ff4e36c AL |
1399 | /* return 1 if surface destoy was initiated (in QXL_ASYNC case) or |
1400 | * done (in QXL_SYNC case), 0 otherwise. */ | |
1401 | static int qxl_destroy_primary(PCIQXLDevice *d, qxl_async_io async) | |
a19cbfb3 GH |
1402 | { |
1403 | if (d->mode == QXL_MODE_UNDEFINED) { | |
5ff4e36c | 1404 | return 0; |
a19cbfb3 | 1405 | } |
c480bb7d | 1406 | trace_qxl_destroy_primary(d->id); |
a19cbfb3 | 1407 | d->mode = QXL_MODE_UNDEFINED; |
5ff4e36c | 1408 | qemu_spice_destroy_primary_surface(&d->ssd, 0, async); |
30f6da66 | 1409 | qxl_spice_reset_cursor(d); |
5ff4e36c | 1410 | return 1; |
a19cbfb3 GH |
1411 | } |
1412 | ||
1413 | static void qxl_set_mode(PCIQXLDevice *d, int modenr, int loadvm) | |
1414 | { | |
1415 | pcibus_t start = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr; | |
1416 | pcibus_t end = d->pci.io_regions[QXL_RAM_RANGE_INDEX].size + start; | |
1417 | QXLMode *mode = d->modes->modes + modenr; | |
1418 | uint64_t devmem = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr; | |
1419 | QXLMemSlot slot = { | |
1420 | .mem_start = start, | |
1421 | .mem_end = end | |
1422 | }; | |
1423 | QXLSurfaceCreate surface = { | |
1424 | .width = mode->x_res, | |
1425 | .height = mode->y_res, | |
1426 | .stride = -mode->x_res * 4, | |
1427 | .format = SPICE_SURFACE_FMT_32_xRGB, | |
1428 | .flags = loadvm ? QXL_SURF_FLAG_KEEP_DATA : 0, | |
1429 | .mouse_mode = true, | |
1430 | .mem = devmem + d->shadow_rom.draw_area_offset, | |
1431 | }; | |
1432 | ||
c480bb7d AL |
1433 | trace_qxl_set_mode(d->id, modenr, mode->x_res, mode->y_res, mode->bits, |
1434 | devmem); | |
a19cbfb3 GH |
1435 | if (!loadvm) { |
1436 | qxl_hard_reset(d, 0); | |
1437 | } | |
1438 | ||
1439 | d->guest_slots[0].slot = slot; | |
e954ea28 | 1440 | assert(qxl_add_memslot(d, 0, devmem, QXL_SYNC) == 0); |
a19cbfb3 GH |
1441 | |
1442 | d->guest_primary.surface = surface; | |
5ff4e36c | 1443 | qxl_create_guest_primary(d, 0, QXL_SYNC); |
a19cbfb3 GH |
1444 | |
1445 | d->mode = QXL_MODE_COMPAT; | |
1446 | d->cmdflags = QXL_COMMAND_FLAG_COMPAT; | |
a19cbfb3 GH |
1447 | if (mode->bits == 16) { |
1448 | d->cmdflags |= QXL_COMMAND_FLAG_COMPAT_16BPP; | |
1449 | } | |
a19cbfb3 GH |
1450 | d->shadow_rom.mode = cpu_to_le32(modenr); |
1451 | d->rom->mode = cpu_to_le32(modenr); | |
1452 | qxl_rom_set_dirty(d); | |
1453 | } | |
1454 | ||
a8170e5e | 1455 | static void ioport_write(void *opaque, hwaddr addr, |
b1950430 | 1456 | uint64_t val, unsigned size) |
a19cbfb3 GH |
1457 | { |
1458 | PCIQXLDevice *d = opaque; | |
b1950430 | 1459 | uint32_t io_port = addr; |
5ff4e36c | 1460 | qxl_async_io async = QXL_SYNC; |
5ff4e36c | 1461 | uint32_t orig_io_port = io_port; |
a19cbfb3 | 1462 | |
d96aafca | 1463 | if (d->guest_bug && io_port != QXL_IO_RESET) { |
087e6a42 AL |
1464 | return; |
1465 | } | |
1466 | ||
020af1c4 | 1467 | if (d->revision <= QXL_REVISION_STABLE_V10 && |
ffe01e59 | 1468 | io_port > QXL_IO_FLUSH_RELEASE) { |
020af1c4 AL |
1469 | qxl_set_guest_bug(d, "unsupported io %d for revision %d\n", |
1470 | io_port, d->revision); | |
1471 | return; | |
1472 | } | |
1473 | ||
a19cbfb3 GH |
1474 | switch (io_port) { |
1475 | case QXL_IO_RESET: | |
1476 | case QXL_IO_SET_MODE: | |
1477 | case QXL_IO_MEMSLOT_ADD: | |
1478 | case QXL_IO_MEMSLOT_DEL: | |
1479 | case QXL_IO_CREATE_PRIMARY: | |
81144d1a | 1480 | case QXL_IO_UPDATE_IRQ: |
a3d14054 | 1481 | case QXL_IO_LOG: |
5ff4e36c AL |
1482 | case QXL_IO_MEMSLOT_ADD_ASYNC: |
1483 | case QXL_IO_CREATE_PRIMARY_ASYNC: | |
a19cbfb3 GH |
1484 | break; |
1485 | default: | |
e21a298a | 1486 | if (d->mode != QXL_MODE_VGA) { |
a19cbfb3 | 1487 | break; |
e21a298a | 1488 | } |
c480bb7d | 1489 | trace_qxl_io_unexpected_vga_mode(d->id, |
917ae08c | 1490 | addr, val, io_port_to_string(io_port)); |
5ff4e36c AL |
1491 | /* be nice to buggy guest drivers */ |
1492 | if (io_port >= QXL_IO_UPDATE_AREA_ASYNC && | |
020af1c4 | 1493 | io_port < QXL_IO_RANGE_SIZE) { |
5ff4e36c AL |
1494 | qxl_send_events(d, QXL_INTERRUPT_IO_CMD); |
1495 | } | |
a19cbfb3 GH |
1496 | return; |
1497 | } | |
1498 | ||
5ff4e36c AL |
1499 | /* we change the io_port to avoid ifdeffery in the main switch */ |
1500 | orig_io_port = io_port; | |
1501 | switch (io_port) { | |
1502 | case QXL_IO_UPDATE_AREA_ASYNC: | |
1503 | io_port = QXL_IO_UPDATE_AREA; | |
1504 | goto async_common; | |
1505 | case QXL_IO_MEMSLOT_ADD_ASYNC: | |
1506 | io_port = QXL_IO_MEMSLOT_ADD; | |
1507 | goto async_common; | |
1508 | case QXL_IO_CREATE_PRIMARY_ASYNC: | |
1509 | io_port = QXL_IO_CREATE_PRIMARY; | |
1510 | goto async_common; | |
1511 | case QXL_IO_DESTROY_PRIMARY_ASYNC: | |
1512 | io_port = QXL_IO_DESTROY_PRIMARY; | |
1513 | goto async_common; | |
1514 | case QXL_IO_DESTROY_SURFACE_ASYNC: | |
1515 | io_port = QXL_IO_DESTROY_SURFACE_WAIT; | |
1516 | goto async_common; | |
1517 | case QXL_IO_DESTROY_ALL_SURFACES_ASYNC: | |
1518 | io_port = QXL_IO_DESTROY_ALL_SURFACES; | |
3e16b9c5 AL |
1519 | goto async_common; |
1520 | case QXL_IO_FLUSH_SURFACES_ASYNC: | |
020af1c4 | 1521 | case QXL_IO_MONITORS_CONFIG_ASYNC: |
5ff4e36c AL |
1522 | async_common: |
1523 | async = QXL_ASYNC; | |
1524 | qemu_mutex_lock(&d->async_lock); | |
1525 | if (d->current_async != QXL_UNDEFINED_IO) { | |
0a530548 | 1526 | qxl_set_guest_bug(d, "%d async started before last (%d) complete", |
5ff4e36c AL |
1527 | io_port, d->current_async); |
1528 | qemu_mutex_unlock(&d->async_lock); | |
1529 | return; | |
1530 | } | |
1531 | d->current_async = orig_io_port; | |
1532 | qemu_mutex_unlock(&d->async_lock); | |
5ff4e36c AL |
1533 | break; |
1534 | default: | |
1535 | break; | |
1536 | } | |
c480bb7d AL |
1537 | trace_qxl_io_write(d->id, qxl_mode_to_string(d->mode), addr, val, size, |
1538 | async); | |
5ff4e36c | 1539 | |
a19cbfb3 GH |
1540 | switch (io_port) { |
1541 | case QXL_IO_UPDATE_AREA: | |
1542 | { | |
81fb6f15 | 1543 | QXLCookie *cookie = NULL; |
a19cbfb3 | 1544 | QXLRect update = d->ram->update_area; |
81fb6f15 | 1545 | |
ddd8fdc7 | 1546 | if (d->ram->update_surface > d->ssd.num_surfaces) { |
511b13e2 AL |
1547 | qxl_set_guest_bug(d, "QXL_IO_UPDATE_AREA: invalid surface id %d\n", |
1548 | d->ram->update_surface); | |
36a03e0b | 1549 | break; |
511b13e2 | 1550 | } |
36a03e0b MT |
1551 | if (update.left >= update.right || update.top >= update.bottom || |
1552 | update.left < 0 || update.top < 0) { | |
511b13e2 AL |
1553 | qxl_set_guest_bug(d, |
1554 | "QXL_IO_UPDATE_AREA: invalid area (%ux%u)x(%ux%u)\n", | |
1555 | update.left, update.top, update.right, update.bottom); | |
ccc2960d DH |
1556 | break; |
1557 | } | |
81fb6f15 AL |
1558 | if (async == QXL_ASYNC) { |
1559 | cookie = qxl_cookie_new(QXL_COOKIE_TYPE_IO, | |
1560 | QXL_IO_UPDATE_AREA_ASYNC); | |
1561 | cookie->u.area = update; | |
1562 | } | |
aee32bf3 | 1563 | qxl_spice_update_area(d, d->ram->update_surface, |
81fb6f15 AL |
1564 | cookie ? &cookie->u.area : &update, |
1565 | NULL, 0, 0, async, cookie); | |
a19cbfb3 GH |
1566 | break; |
1567 | } | |
1568 | case QXL_IO_NOTIFY_CMD: | |
5c59d118 | 1569 | qemu_spice_wakeup(&d->ssd); |
a19cbfb3 GH |
1570 | break; |
1571 | case QXL_IO_NOTIFY_CURSOR: | |
5c59d118 | 1572 | qemu_spice_wakeup(&d->ssd); |
a19cbfb3 GH |
1573 | break; |
1574 | case QXL_IO_UPDATE_IRQ: | |
40010aea | 1575 | qxl_update_irq(d); |
a19cbfb3 GH |
1576 | break; |
1577 | case QXL_IO_NOTIFY_OOM: | |
a19cbfb3 GH |
1578 | if (!SPICE_RING_IS_EMPTY(&d->ram->release_ring)) { |
1579 | break; | |
1580 | } | |
1581 | d->oom_running = 1; | |
aee32bf3 | 1582 | qxl_spice_oom(d); |
a19cbfb3 GH |
1583 | d->oom_running = 0; |
1584 | break; | |
1585 | case QXL_IO_SET_MODE: | |
a19cbfb3 GH |
1586 | qxl_set_mode(d, val, 0); |
1587 | break; | |
1588 | case QXL_IO_LOG: | |
1a1bc085 | 1589 | trace_qxl_io_log(d->id, d->ram->log_buf); |
a19cbfb3 | 1590 | if (d->guestdebug) { |
a680f7e7 | 1591 | fprintf(stderr, "qxl/guest-%d: %" PRId64 ": %s", d->id, |
6ebebb55 | 1592 | qemu_get_clock_ns(vm_clock), d->ram->log_buf); |
a19cbfb3 GH |
1593 | } |
1594 | break; | |
1595 | case QXL_IO_RESET: | |
a19cbfb3 GH |
1596 | qxl_hard_reset(d, 0); |
1597 | break; | |
1598 | case QXL_IO_MEMSLOT_ADD: | |
2bce0400 | 1599 | if (val >= NUM_MEMSLOTS) { |
0a530548 | 1600 | qxl_set_guest_bug(d, "QXL_IO_MEMSLOT_ADD: val out of range"); |
2bce0400 GH |
1601 | break; |
1602 | } | |
1603 | if (d->guest_slots[val].active) { | |
0a530548 AL |
1604 | qxl_set_guest_bug(d, |
1605 | "QXL_IO_MEMSLOT_ADD: memory slot already active"); | |
2bce0400 GH |
1606 | break; |
1607 | } | |
a19cbfb3 | 1608 | d->guest_slots[val].slot = d->ram->mem_slot; |
5ff4e36c | 1609 | qxl_add_memslot(d, val, 0, async); |
a19cbfb3 GH |
1610 | break; |
1611 | case QXL_IO_MEMSLOT_DEL: | |
2bce0400 | 1612 | if (val >= NUM_MEMSLOTS) { |
0a530548 | 1613 | qxl_set_guest_bug(d, "QXL_IO_MEMSLOT_DEL: val out of range"); |
2bce0400 GH |
1614 | break; |
1615 | } | |
a19cbfb3 GH |
1616 | qxl_del_memslot(d, val); |
1617 | break; | |
1618 | case QXL_IO_CREATE_PRIMARY: | |
2bce0400 | 1619 | if (val != 0) { |
0a530548 | 1620 | qxl_set_guest_bug(d, "QXL_IO_CREATE_PRIMARY (async=%d): val != 0", |
5ff4e36c AL |
1621 | async); |
1622 | goto cancel_async; | |
2bce0400 | 1623 | } |
a19cbfb3 | 1624 | d->guest_primary.surface = d->ram->create_surface; |
5ff4e36c | 1625 | qxl_create_guest_primary(d, 0, async); |
a19cbfb3 GH |
1626 | break; |
1627 | case QXL_IO_DESTROY_PRIMARY: | |
2bce0400 | 1628 | if (val != 0) { |
0a530548 | 1629 | qxl_set_guest_bug(d, "QXL_IO_DESTROY_PRIMARY (async=%d): val != 0", |
5ff4e36c AL |
1630 | async); |
1631 | goto cancel_async; | |
1632 | } | |
5ff4e36c | 1633 | if (!qxl_destroy_primary(d, async)) { |
c480bb7d AL |
1634 | trace_qxl_io_destroy_primary_ignored(d->id, |
1635 | qxl_mode_to_string(d->mode)); | |
5ff4e36c | 1636 | goto cancel_async; |
2bce0400 | 1637 | } |
a19cbfb3 GH |
1638 | break; |
1639 | case QXL_IO_DESTROY_SURFACE_WAIT: | |
ddd8fdc7 | 1640 | if (val >= d->ssd.num_surfaces) { |
0a530548 | 1641 | qxl_set_guest_bug(d, "QXL_IO_DESTROY_SURFACE (async=%d):" |
5f8daf2e | 1642 | "%" PRIu64 " >= NUM_SURFACES", async, val); |
5ff4e36c AL |
1643 | goto cancel_async; |
1644 | } | |
1645 | qxl_spice_destroy_surface_wait(d, val, async); | |
a19cbfb3 | 1646 | break; |
3e16b9c5 AL |
1647 | case QXL_IO_FLUSH_RELEASE: { |
1648 | QXLReleaseRing *ring = &d->ram->release_ring; | |
1649 | if (ring->prod - ring->cons + 1 == ring->num_items) { | |
1650 | fprintf(stderr, | |
1651 | "ERROR: no flush, full release ring [p%d,%dc]\n", | |
1652 | ring->prod, ring->cons); | |
1653 | } | |
1654 | qxl_push_free_res(d, 1 /* flush */); | |
3e16b9c5 AL |
1655 | break; |
1656 | } | |
1657 | case QXL_IO_FLUSH_SURFACES_ASYNC: | |
3e16b9c5 AL |
1658 | qxl_spice_flush_surfaces_async(d); |
1659 | break; | |
a19cbfb3 | 1660 | case QXL_IO_DESTROY_ALL_SURFACES: |
5ff4e36c AL |
1661 | d->mode = QXL_MODE_UNDEFINED; |
1662 | qxl_spice_destroy_surfaces(d, async); | |
a19cbfb3 | 1663 | break; |
020af1c4 AL |
1664 | case QXL_IO_MONITORS_CONFIG_ASYNC: |
1665 | qxl_spice_monitors_config_async(d, 0); | |
1666 | break; | |
a19cbfb3 | 1667 | default: |
0a530548 | 1668 | qxl_set_guest_bug(d, "%s: unexpected ioport=0x%x\n", __func__, io_port); |
a19cbfb3 | 1669 | } |
5ff4e36c AL |
1670 | return; |
1671 | cancel_async: | |
5ff4e36c AL |
1672 | if (async) { |
1673 | qxl_send_events(d, QXL_INTERRUPT_IO_CMD); | |
1674 | qemu_mutex_lock(&d->async_lock); | |
1675 | d->current_async = QXL_UNDEFINED_IO; | |
1676 | qemu_mutex_unlock(&d->async_lock); | |
1677 | } | |
a19cbfb3 GH |
1678 | } |
1679 | ||
a8170e5e | 1680 | static uint64_t ioport_read(void *opaque, hwaddr addr, |
b1950430 | 1681 | unsigned size) |
a19cbfb3 | 1682 | { |
917ae08c | 1683 | PCIQXLDevice *qxl = opaque; |
a19cbfb3 | 1684 | |
917ae08c | 1685 | trace_qxl_io_read_unexpected(qxl->id); |
a19cbfb3 GH |
1686 | return 0xff; |
1687 | } | |
1688 | ||
b1950430 AK |
1689 | static const MemoryRegionOps qxl_io_ops = { |
1690 | .read = ioport_read, | |
1691 | .write = ioport_write, | |
1692 | .valid = { | |
1693 | .min_access_size = 1, | |
1694 | .max_access_size = 1, | |
1695 | }, | |
1696 | }; | |
a19cbfb3 GH |
1697 | |
1698 | static void pipe_read(void *opaque) | |
1699 | { | |
1700 | PCIQXLDevice *d = opaque; | |
1701 | char dummy; | |
1702 | int len; | |
1703 | ||
1704 | do { | |
1705 | len = read(d->pipe[0], &dummy, sizeof(dummy)); | |
1706 | } while (len == sizeof(dummy)); | |
40010aea | 1707 | qxl_update_irq(d); |
a19cbfb3 GH |
1708 | } |
1709 | ||
a19cbfb3 GH |
1710 | static void qxl_send_events(PCIQXLDevice *d, uint32_t events) |
1711 | { | |
1712 | uint32_t old_pending; | |
1713 | uint32_t le_events = cpu_to_le32(events); | |
1714 | ||
917ae08c | 1715 | trace_qxl_send_events(d->id, events); |
511aefb0 AL |
1716 | if (!qemu_spice_display_is_running(&d->ssd)) { |
1717 | /* spice-server tracks guest running state and should not do this */ | |
1718 | fprintf(stderr, "%s: spice-server bug: guest stopped, ignoring\n", | |
1719 | __func__); | |
1720 | trace_qxl_send_events_vm_stopped(d->id, events); | |
1721 | return; | |
1722 | } | |
a19cbfb3 GH |
1723 | old_pending = __sync_fetch_and_or(&d->ram->int_pending, le_events); |
1724 | if ((old_pending & le_events) == le_events) { | |
1725 | return; | |
1726 | } | |
691f5c7b | 1727 | if (qemu_thread_is_self(&d->main)) { |
40010aea | 1728 | qxl_update_irq(d); |
a19cbfb3 GH |
1729 | } else { |
1730 | if (write(d->pipe[1], d, 1) != 1) { | |
75fe0d7b | 1731 | dprint(d, 1, "%s: write to pipe failed\n", __func__); |
a19cbfb3 GH |
1732 | } |
1733 | } | |
1734 | } | |
1735 | ||
1736 | static void init_pipe_signaling(PCIQXLDevice *d) | |
1737 | { | |
aa3db423 AL |
1738 | if (pipe(d->pipe) < 0) { |
1739 | fprintf(stderr, "%s:%s: qxl pipe creation failed\n", | |
1740 | __FILE__, __func__); | |
1741 | exit(1); | |
1742 | } | |
1743 | fcntl(d->pipe[0], F_SETFL, O_NONBLOCK); | |
1744 | fcntl(d->pipe[1], F_SETFL, O_NONBLOCK); | |
1745 | fcntl(d->pipe[0], F_SETOWN, getpid()); | |
1746 | ||
1747 | qemu_thread_get_self(&d->main); | |
1748 | qemu_set_fd_handler(d->pipe[0], pipe_read, NULL, d); | |
a19cbfb3 GH |
1749 | } |
1750 | ||
1751 | /* graphics console */ | |
1752 | ||
1753 | static void qxl_hw_update(void *opaque) | |
1754 | { | |
1755 | PCIQXLDevice *qxl = opaque; | |
1756 | VGACommonState *vga = &qxl->vga; | |
1757 | ||
1758 | switch (qxl->mode) { | |
1759 | case QXL_MODE_VGA: | |
1760 | vga->update(vga); | |
1761 | break; | |
1762 | case QXL_MODE_COMPAT: | |
1763 | case QXL_MODE_NATIVE: | |
1764 | qxl_render_update(qxl); | |
1765 | break; | |
1766 | default: | |
1767 | break; | |
1768 | } | |
1769 | } | |
1770 | ||
1771 | static void qxl_hw_invalidate(void *opaque) | |
1772 | { | |
1773 | PCIQXLDevice *qxl = opaque; | |
1774 | VGACommonState *vga = &qxl->vga; | |
1775 | ||
1776 | vga->invalidate(vga); | |
1777 | } | |
1778 | ||
d7098135 LC |
1779 | static void qxl_hw_screen_dump(void *opaque, const char *filename, bool cswitch, |
1780 | Error **errp) | |
a19cbfb3 GH |
1781 | { |
1782 | PCIQXLDevice *qxl = opaque; | |
1783 | VGACommonState *vga = &qxl->vga; | |
1784 | ||
1785 | switch (qxl->mode) { | |
1786 | case QXL_MODE_COMPAT: | |
1787 | case QXL_MODE_NATIVE: | |
1788 | qxl_render_update(qxl); | |
71874c17 | 1789 | ppm_save(filename, qxl->ssd.ds, errp); |
a19cbfb3 GH |
1790 | break; |
1791 | case QXL_MODE_VGA: | |
d7098135 | 1792 | vga->screen_dump(vga, filename, cswitch, errp); |
a19cbfb3 GH |
1793 | break; |
1794 | default: | |
1795 | break; | |
1796 | } | |
1797 | } | |
1798 | ||
1799 | static void qxl_hw_text_update(void *opaque, console_ch_t *chardata) | |
1800 | { | |
1801 | PCIQXLDevice *qxl = opaque; | |
1802 | VGACommonState *vga = &qxl->vga; | |
1803 | ||
1804 | if (qxl->mode == QXL_MODE_VGA) { | |
1805 | vga->text_update(vga, chardata); | |
1806 | return; | |
1807 | } | |
1808 | } | |
1809 | ||
e25139b3 YH |
1810 | static void qxl_dirty_surfaces(PCIQXLDevice *qxl) |
1811 | { | |
c5825ac6 | 1812 | uintptr_t vram_start; |
e25139b3 YH |
1813 | int i; |
1814 | ||
2aa9e85c | 1815 | if (qxl->mode != QXL_MODE_NATIVE && qxl->mode != QXL_MODE_COMPAT) { |
e25139b3 YH |
1816 | return; |
1817 | } | |
1818 | ||
1819 | /* dirty the primary surface */ | |
1820 | qxl_set_dirty(&qxl->vga.vram, qxl->shadow_rom.draw_area_offset, | |
1821 | qxl->shadow_rom.surface0_area_size); | |
1822 | ||
c5825ac6 | 1823 | vram_start = (uintptr_t)memory_region_get_ram_ptr(&qxl->vram_bar); |
e25139b3 YH |
1824 | |
1825 | /* dirty the off-screen surfaces */ | |
ddd8fdc7 | 1826 | for (i = 0; i < qxl->ssd.num_surfaces; i++) { |
e25139b3 YH |
1827 | QXLSurfaceCmd *cmd; |
1828 | intptr_t surface_offset; | |
1829 | int surface_size; | |
1830 | ||
1831 | if (qxl->guest_surfaces.cmds[i] == 0) { | |
1832 | continue; | |
1833 | } | |
1834 | ||
1835 | cmd = qxl_phys2virt(qxl, qxl->guest_surfaces.cmds[i], | |
1836 | MEMSLOT_GROUP_GUEST); | |
fae2afb1 | 1837 | assert(cmd); |
e25139b3 YH |
1838 | assert(cmd->type == QXL_SURFACE_CMD_CREATE); |
1839 | surface_offset = (intptr_t)qxl_phys2virt(qxl, | |
1840 | cmd->u.surface_create.data, | |
1841 | MEMSLOT_GROUP_GUEST); | |
fae2afb1 | 1842 | assert(surface_offset); |
e25139b3 YH |
1843 | surface_offset -= vram_start; |
1844 | surface_size = cmd->u.surface_create.height * | |
1845 | abs(cmd->u.surface_create.stride); | |
c480bb7d | 1846 | trace_qxl_surfaces_dirty(qxl->id, i, (int)surface_offset, surface_size); |
e25139b3 YH |
1847 | qxl_set_dirty(&qxl->vram_bar, surface_offset, surface_size); |
1848 | } | |
1849 | } | |
1850 | ||
1dfb4dd9 LC |
1851 | static void qxl_vm_change_state_handler(void *opaque, int running, |
1852 | RunState state) | |
a19cbfb3 GH |
1853 | { |
1854 | PCIQXLDevice *qxl = opaque; | |
a19cbfb3 | 1855 | |
efbf2950 YH |
1856 | if (running) { |
1857 | /* | |
1858 | * if qxl_send_events was called from spice server context before | |
40010aea | 1859 | * migration ended, qxl_update_irq for these events might not have been |
efbf2950 YH |
1860 | * called |
1861 | */ | |
40010aea | 1862 | qxl_update_irq(qxl); |
e25139b3 YH |
1863 | } else { |
1864 | /* make sure surfaces are saved before migration */ | |
1865 | qxl_dirty_surfaces(qxl); | |
a19cbfb3 GH |
1866 | } |
1867 | } | |
1868 | ||
1869 | /* display change listener */ | |
1870 | ||
7c20b4a3 | 1871 | static void display_update(DisplayChangeListener *dcl, |
7c20b4a3 | 1872 | int x, int y, int w, int h) |
a19cbfb3 | 1873 | { |
c6c06853 GH |
1874 | PCIQXLDevice *qxl = container_of(dcl, PCIQXLDevice, ssd.dcl); |
1875 | ||
1876 | if (qxl->mode == QXL_MODE_VGA) { | |
1877 | qemu_spice_display_update(&qxl->ssd, x, y, w, h); | |
a19cbfb3 GH |
1878 | } |
1879 | } | |
1880 | ||
c12aeb86 | 1881 | static void display_switch(DisplayChangeListener *dcl, |
c12aeb86 | 1882 | struct DisplaySurface *surface) |
a19cbfb3 | 1883 | { |
c6c06853 GH |
1884 | PCIQXLDevice *qxl = container_of(dcl, PCIQXLDevice, ssd.dcl); |
1885 | ||
71874c17 | 1886 | qxl->ssd.ds = surface; |
c6c06853 | 1887 | if (qxl->mode == QXL_MODE_VGA) { |
c12aeb86 | 1888 | qemu_spice_display_switch(&qxl->ssd, surface); |
a19cbfb3 GH |
1889 | } |
1890 | } | |
1891 | ||
bc2ed970 | 1892 | static void display_refresh(DisplayChangeListener *dcl) |
a19cbfb3 | 1893 | { |
c6c06853 GH |
1894 | PCIQXLDevice *qxl = container_of(dcl, PCIQXLDevice, ssd.dcl); |
1895 | ||
1896 | if (qxl->mode == QXL_MODE_VGA) { | |
1897 | qemu_spice_display_refresh(&qxl->ssd); | |
bb5a8cd5 | 1898 | } else { |
c6c06853 GH |
1899 | qemu_mutex_lock(&qxl->ssd.lock); |
1900 | qemu_spice_cursor_refresh_unlocked(&qxl->ssd); | |
1901 | qemu_mutex_unlock(&qxl->ssd.lock); | |
a19cbfb3 GH |
1902 | } |
1903 | } | |
1904 | ||
7c20b4a3 GH |
1905 | static DisplayChangeListenerOps display_listener_ops = { |
1906 | .dpy_name = "spice/qxl", | |
a93a4a22 | 1907 | .dpy_gfx_update = display_update, |
c12aeb86 | 1908 | .dpy_gfx_switch = display_switch, |
7c20b4a3 | 1909 | .dpy_refresh = display_refresh, |
a19cbfb3 GH |
1910 | }; |
1911 | ||
13d1fd44 | 1912 | static void qxl_init_ramsize(PCIQXLDevice *qxl) |
a974192c | 1913 | { |
13d1fd44 AL |
1914 | /* vga mode framebuffer / primary surface (bar 0, first part) */ |
1915 | if (qxl->vgamem_size_mb < 8) { | |
1916 | qxl->vgamem_size_mb = 8; | |
1917 | } | |
1918 | qxl->vgamem_size = qxl->vgamem_size_mb * 1024 * 1024; | |
1919 | ||
1920 | /* vga ram (bar 0, total) */ | |
017438ee GH |
1921 | if (qxl->ram_size_mb != -1) { |
1922 | qxl->vga.vram_size = qxl->ram_size_mb * 1024 * 1024; | |
1923 | } | |
13d1fd44 AL |
1924 | if (qxl->vga.vram_size < qxl->vgamem_size * 2) { |
1925 | qxl->vga.vram_size = qxl->vgamem_size * 2; | |
a974192c GH |
1926 | } |
1927 | ||
6f2b175a GH |
1928 | /* vram32 (surfaces, 32bit, bar 1) */ |
1929 | if (qxl->vram32_size_mb != -1) { | |
1930 | qxl->vram32_size = qxl->vram32_size_mb * 1024 * 1024; | |
1931 | } | |
1932 | if (qxl->vram32_size < 4096) { | |
1933 | qxl->vram32_size = 4096; | |
1934 | } | |
1935 | ||
1936 | /* vram (surfaces, 64bit, bar 4+5) */ | |
017438ee GH |
1937 | if (qxl->vram_size_mb != -1) { |
1938 | qxl->vram_size = qxl->vram_size_mb * 1024 * 1024; | |
1939 | } | |
6f2b175a GH |
1940 | if (qxl->vram_size < qxl->vram32_size) { |
1941 | qxl->vram_size = qxl->vram32_size; | |
a974192c | 1942 | } |
6f2b175a | 1943 | |
a974192c | 1944 | if (qxl->revision == 1) { |
6f2b175a | 1945 | qxl->vram32_size = 4096; |
a974192c GH |
1946 | qxl->vram_size = 4096; |
1947 | } | |
13d1fd44 | 1948 | qxl->vgamem_size = msb_mask(qxl->vgamem_size * 2 - 1); |
a974192c | 1949 | qxl->vga.vram_size = msb_mask(qxl->vga.vram_size * 2 - 1); |
6f2b175a | 1950 | qxl->vram32_size = msb_mask(qxl->vram32_size * 2 - 1); |
a974192c GH |
1951 | qxl->vram_size = msb_mask(qxl->vram_size * 2 - 1); |
1952 | } | |
1953 | ||
a19cbfb3 GH |
1954 | static int qxl_init_common(PCIQXLDevice *qxl) |
1955 | { | |
1956 | uint8_t* config = qxl->pci.config; | |
a19cbfb3 GH |
1957 | uint32_t pci_device_rev; |
1958 | uint32_t io_size; | |
1959 | ||
1960 | qxl->mode = QXL_MODE_UNDEFINED; | |
1961 | qxl->generation = 1; | |
1962 | qxl->num_memslots = NUM_MEMSLOTS; | |
14898cf6 | 1963 | qemu_mutex_init(&qxl->track_lock); |
5ff4e36c AL |
1964 | qemu_mutex_init(&qxl->async_lock); |
1965 | qxl->current_async = QXL_UNDEFINED_IO; | |
087e6a42 | 1966 | qxl->guest_bug = 0; |
a19cbfb3 GH |
1967 | |
1968 | switch (qxl->revision) { | |
1969 | case 1: /* spice 0.4 -- qxl-1 */ | |
a19cbfb3 | 1970 | pci_device_rev = QXL_REVISION_STABLE_V04; |
3f6297b9 | 1971 | io_size = 8; |
a19cbfb3 GH |
1972 | break; |
1973 | case 2: /* spice 0.6 -- qxl-2 */ | |
a19cbfb3 | 1974 | pci_device_rev = QXL_REVISION_STABLE_V06; |
3f6297b9 | 1975 | io_size = 16; |
a19cbfb3 | 1976 | break; |
9197a7c8 | 1977 | case 3: /* qxl-3 */ |
020af1c4 AL |
1978 | pci_device_rev = QXL_REVISION_STABLE_V10; |
1979 | io_size = 32; /* PCI region size must be pow2 */ | |
1980 | break; | |
020af1c4 AL |
1981 | case 4: /* qxl-4 */ |
1982 | pci_device_rev = QXL_REVISION_STABLE_V12; | |
3f6297b9 | 1983 | io_size = msb_mask(QXL_IO_RANGE_SIZE * 2 - 1); |
9197a7c8 | 1984 | break; |
36839d35 AL |
1985 | default: |
1986 | error_report("Invalid revision %d for qxl device (max %d)", | |
1987 | qxl->revision, QXL_DEFAULT_REVISION); | |
1988 | return -1; | |
a19cbfb3 GH |
1989 | } |
1990 | ||
a19cbfb3 GH |
1991 | pci_set_byte(&config[PCI_REVISION_ID], pci_device_rev); |
1992 | pci_set_byte(&config[PCI_INTERRUPT_PIN], 1); | |
1993 | ||
1994 | qxl->rom_size = qxl_rom_size(); | |
c5705a77 AK |
1995 | memory_region_init_ram(&qxl->rom_bar, "qxl.vrom", qxl->rom_size); |
1996 | vmstate_register_ram(&qxl->rom_bar, &qxl->pci.qdev); | |
a19cbfb3 GH |
1997 | init_qxl_rom(qxl); |
1998 | init_qxl_ram(qxl); | |
1999 | ||
ddd8fdc7 | 2000 | qxl->guest_surfaces.cmds = g_new0(QXLPHYSICAL, qxl->ssd.num_surfaces); |
c5705a77 AK |
2001 | memory_region_init_ram(&qxl->vram_bar, "qxl.vram", qxl->vram_size); |
2002 | vmstate_register_ram(&qxl->vram_bar, &qxl->pci.qdev); | |
6f2b175a GH |
2003 | memory_region_init_alias(&qxl->vram32_bar, "qxl.vram32", &qxl->vram_bar, |
2004 | 0, qxl->vram32_size); | |
a19cbfb3 | 2005 | |
b1950430 AK |
2006 | memory_region_init_io(&qxl->io_bar, &qxl_io_ops, qxl, |
2007 | "qxl-ioports", io_size); | |
2008 | if (qxl->id == 0) { | |
2009 | vga_dirty_log_start(&qxl->vga); | |
2010 | } | |
bd8f2f5d | 2011 | memory_region_set_flush_coalesced(&qxl->io_bar); |
b1950430 AK |
2012 | |
2013 | ||
e824b2cc AK |
2014 | pci_register_bar(&qxl->pci, QXL_IO_RANGE_INDEX, |
2015 | PCI_BASE_ADDRESS_SPACE_IO, &qxl->io_bar); | |
a19cbfb3 | 2016 | |
e824b2cc AK |
2017 | pci_register_bar(&qxl->pci, QXL_ROM_RANGE_INDEX, |
2018 | PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->rom_bar); | |
a19cbfb3 | 2019 | |
e824b2cc AK |
2020 | pci_register_bar(&qxl->pci, QXL_RAM_RANGE_INDEX, |
2021 | PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->vga.vram); | |
a19cbfb3 | 2022 | |
e824b2cc | 2023 | pci_register_bar(&qxl->pci, QXL_VRAM_RANGE_INDEX, |
6f2b175a GH |
2024 | PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->vram32_bar); |
2025 | ||
2026 | if (qxl->vram32_size < qxl->vram_size) { | |
2027 | /* | |
2028 | * Make the 64bit vram bar show up only in case it is | |
2029 | * configured to be larger than the 32bit vram bar. | |
2030 | */ | |
2031 | pci_register_bar(&qxl->pci, QXL_VRAM64_RANGE_INDEX, | |
2032 | PCI_BASE_ADDRESS_SPACE_MEMORY | | |
2033 | PCI_BASE_ADDRESS_MEM_TYPE_64 | | |
2034 | PCI_BASE_ADDRESS_MEM_PREFETCH, | |
2035 | &qxl->vram_bar); | |
2036 | } | |
2037 | ||
2038 | /* print pci bar details */ | |
2039 | dprint(qxl, 1, "ram/%s: %d MB [region 0]\n", | |
2040 | qxl->id == 0 ? "pri" : "sec", | |
2041 | qxl->vga.vram_size / (1024*1024)); | |
2042 | dprint(qxl, 1, "vram/32: %d MB [region 1]\n", | |
2043 | qxl->vram32_size / (1024*1024)); | |
2044 | dprint(qxl, 1, "vram/64: %d MB %s\n", | |
2045 | qxl->vram_size / (1024*1024), | |
2046 | qxl->vram32_size < qxl->vram_size ? "[region 4]" : "[unmapped]"); | |
a19cbfb3 GH |
2047 | |
2048 | qxl->ssd.qxl.base.sif = &qxl_interface.base; | |
2049 | qxl->ssd.qxl.id = qxl->id; | |
e25a0651 | 2050 | if (qemu_spice_add_interface(&qxl->ssd.qxl.base) != 0) { |
312fd5f2 | 2051 | error_report("qxl interface %d.%d not supported by spice-server", |
e25a0651 AL |
2052 | SPICE_INTERFACE_QXL_MAJOR, SPICE_INTERFACE_QXL_MINOR); |
2053 | return -1; | |
2054 | } | |
a19cbfb3 GH |
2055 | qemu_add_vm_change_state_handler(qxl_vm_change_state_handler, qxl); |
2056 | ||
2057 | init_pipe_signaling(qxl); | |
2058 | qxl_reset_state(qxl); | |
2059 | ||
81fb6f15 AL |
2060 | qxl->update_area_bh = qemu_bh_new(qxl_render_update_area_bh, qxl); |
2061 | ||
a19cbfb3 GH |
2062 | return 0; |
2063 | } | |
2064 | ||
2065 | static int qxl_init_primary(PCIDevice *dev) | |
2066 | { | |
2067 | PCIQXLDevice *qxl = DO_UPCAST(PCIQXLDevice, pci, dev); | |
2068 | VGACommonState *vga = &qxl->vga; | |
f67ab77a | 2069 | PortioList *qxl_vga_port_list = g_new(PortioList, 1); |
c78f7137 | 2070 | DisplayState *ds; |
bdd4df33 | 2071 | int rc; |
a19cbfb3 GH |
2072 | |
2073 | qxl->id = 0; | |
13d1fd44 | 2074 | qxl_init_ramsize(qxl); |
4a1e244e GH |
2075 | vga->vram_size_mb = qxl->vga.vram_size >> 20; |
2076 | vga_common_init(vga); | |
0a039dc7 | 2077 | vga_init(vga, pci_address_space(dev), pci_address_space_io(dev), false); |
f67ab77a GH |
2078 | portio_list_init(qxl_vga_port_list, qxl_vga_portio_list, vga, "vga"); |
2079 | portio_list_add(qxl_vga_port_list, pci_address_space_io(dev), 0x3b0); | |
a19cbfb3 | 2080 | |
c78f7137 GH |
2081 | vga->con = graphic_console_init(qxl_hw_update, qxl_hw_invalidate, |
2082 | qxl_hw_screen_dump, qxl_hw_text_update, | |
2083 | qxl); | |
2084 | qxl->ssd.con = vga->con, | |
2085 | qemu_spice_display_init_common(&qxl->ssd); | |
a19cbfb3 | 2086 | |
bdd4df33 GH |
2087 | rc = qxl_init_common(qxl); |
2088 | if (rc != 0) { | |
2089 | return rc; | |
2090 | } | |
2091 | ||
7c20b4a3 | 2092 | qxl->ssd.dcl.ops = &display_listener_ops; |
c78f7137 GH |
2093 | ds = qemu_console_displaystate(vga->con); |
2094 | register_displaychangelistener(ds, &qxl->ssd.dcl); | |
bdd4df33 | 2095 | return rc; |
a19cbfb3 GH |
2096 | } |
2097 | ||
2098 | static int qxl_init_secondary(PCIDevice *dev) | |
2099 | { | |
2100 | static int device_id = 1; | |
2101 | PCIQXLDevice *qxl = DO_UPCAST(PCIQXLDevice, pci, dev); | |
a19cbfb3 GH |
2102 | |
2103 | qxl->id = device_id++; | |
13d1fd44 | 2104 | qxl_init_ramsize(qxl); |
c5705a77 AK |
2105 | memory_region_init_ram(&qxl->vga.vram, "qxl.vgavram", qxl->vga.vram_size); |
2106 | vmstate_register_ram(&qxl->vga.vram, &qxl->pci.qdev); | |
b1950430 | 2107 | qxl->vga.vram_ptr = memory_region_get_ram_ptr(&qxl->vga.vram); |
a19cbfb3 | 2108 | |
a19cbfb3 GH |
2109 | return qxl_init_common(qxl); |
2110 | } | |
2111 | ||
2112 | static void qxl_pre_save(void *opaque) | |
2113 | { | |
2114 | PCIQXLDevice* d = opaque; | |
2115 | uint8_t *ram_start = d->vga.vram_ptr; | |
2116 | ||
c480bb7d | 2117 | trace_qxl_pre_save(d->id); |
a19cbfb3 GH |
2118 | if (d->last_release == NULL) { |
2119 | d->last_release_offset = 0; | |
2120 | } else { | |
2121 | d->last_release_offset = (uint8_t *)d->last_release - ram_start; | |
2122 | } | |
2123 | assert(d->last_release_offset < d->vga.vram_size); | |
2124 | } | |
2125 | ||
2126 | static int qxl_pre_load(void *opaque) | |
2127 | { | |
2128 | PCIQXLDevice* d = opaque; | |
2129 | ||
c480bb7d | 2130 | trace_qxl_pre_load(d->id); |
a19cbfb3 GH |
2131 | qxl_hard_reset(d, 1); |
2132 | qxl_exit_vga_mode(d); | |
a19cbfb3 GH |
2133 | return 0; |
2134 | } | |
2135 | ||
54825d2e AL |
2136 | static void qxl_create_memslots(PCIQXLDevice *d) |
2137 | { | |
2138 | int i; | |
2139 | ||
2140 | for (i = 0; i < NUM_MEMSLOTS; i++) { | |
2141 | if (!d->guest_slots[i].active) { | |
2142 | continue; | |
2143 | } | |
54825d2e AL |
2144 | qxl_add_memslot(d, i, 0, QXL_SYNC); |
2145 | } | |
2146 | } | |
2147 | ||
a19cbfb3 GH |
2148 | static int qxl_post_load(void *opaque, int version) |
2149 | { | |
2150 | PCIQXLDevice* d = opaque; | |
2151 | uint8_t *ram_start = d->vga.vram_ptr; | |
2152 | QXLCommandExt *cmds; | |
54825d2e | 2153 | int in, out, newmode; |
a19cbfb3 | 2154 | |
a19cbfb3 GH |
2155 | assert(d->last_release_offset < d->vga.vram_size); |
2156 | if (d->last_release_offset == 0) { | |
2157 | d->last_release = NULL; | |
2158 | } else { | |
2159 | d->last_release = (QXLReleaseInfo *)(ram_start + d->last_release_offset); | |
2160 | } | |
2161 | ||
2162 | d->modes = (QXLModes*)((uint8_t*)d->rom + d->rom->modes_offset); | |
2163 | ||
c480bb7d | 2164 | trace_qxl_post_load(d->id, qxl_mode_to_string(d->mode)); |
a19cbfb3 GH |
2165 | newmode = d->mode; |
2166 | d->mode = QXL_MODE_UNDEFINED; | |
54825d2e | 2167 | |
a19cbfb3 GH |
2168 | switch (newmode) { |
2169 | case QXL_MODE_UNDEFINED: | |
fa98efe9 | 2170 | qxl_create_memslots(d); |
a19cbfb3 GH |
2171 | break; |
2172 | case QXL_MODE_VGA: | |
54825d2e | 2173 | qxl_create_memslots(d); |
a19cbfb3 GH |
2174 | qxl_enter_vga_mode(d); |
2175 | break; | |
2176 | case QXL_MODE_NATIVE: | |
54825d2e | 2177 | qxl_create_memslots(d); |
5ff4e36c | 2178 | qxl_create_guest_primary(d, 1, QXL_SYNC); |
a19cbfb3 GH |
2179 | |
2180 | /* replay surface-create and cursor-set commands */ | |
ddd8fdc7 GH |
2181 | cmds = g_malloc0(sizeof(QXLCommandExt) * (d->ssd.num_surfaces + 1)); |
2182 | for (in = 0, out = 0; in < d->ssd.num_surfaces; in++) { | |
a19cbfb3 GH |
2183 | if (d->guest_surfaces.cmds[in] == 0) { |
2184 | continue; | |
2185 | } | |
2186 | cmds[out].cmd.data = d->guest_surfaces.cmds[in]; | |
2187 | cmds[out].cmd.type = QXL_CMD_SURFACE; | |
2188 | cmds[out].group_id = MEMSLOT_GROUP_GUEST; | |
2189 | out++; | |
2190 | } | |
30f6da66 YH |
2191 | if (d->guest_cursor) { |
2192 | cmds[out].cmd.data = d->guest_cursor; | |
2193 | cmds[out].cmd.type = QXL_CMD_CURSOR; | |
2194 | cmds[out].group_id = MEMSLOT_GROUP_GUEST; | |
2195 | out++; | |
2196 | } | |
aee32bf3 | 2197 | qxl_spice_loadvm_commands(d, cmds, out); |
7267c094 | 2198 | g_free(cmds); |
020af1c4 AL |
2199 | if (d->guest_monitors_config) { |
2200 | qxl_spice_monitors_config_async(d, 1); | |
2201 | } | |
a19cbfb3 GH |
2202 | break; |
2203 | case QXL_MODE_COMPAT: | |
54825d2e AL |
2204 | /* note: no need to call qxl_create_memslots, qxl_set_mode |
2205 | * creates the mem slot. */ | |
a19cbfb3 GH |
2206 | qxl_set_mode(d, d->shadow_rom.mode, 1); |
2207 | break; | |
2208 | } | |
a19cbfb3 GH |
2209 | return 0; |
2210 | } | |
2211 | ||
b67737a6 | 2212 | #define QXL_SAVE_VERSION 21 |
a19cbfb3 | 2213 | |
020af1c4 AL |
2214 | static bool qxl_monitors_config_needed(void *opaque) |
2215 | { | |
2216 | PCIQXLDevice *qxl = opaque; | |
2217 | ||
2218 | return qxl->guest_monitors_config != 0; | |
2219 | } | |
2220 | ||
2221 | ||
a19cbfb3 GH |
2222 | static VMStateDescription qxl_memslot = { |
2223 | .name = "qxl-memslot", | |
2224 | .version_id = QXL_SAVE_VERSION, | |
2225 | .minimum_version_id = QXL_SAVE_VERSION, | |
2226 | .fields = (VMStateField[]) { | |
2227 | VMSTATE_UINT64(slot.mem_start, struct guest_slots), | |
2228 | VMSTATE_UINT64(slot.mem_end, struct guest_slots), | |
2229 | VMSTATE_UINT32(active, struct guest_slots), | |
2230 | VMSTATE_END_OF_LIST() | |
2231 | } | |
2232 | }; | |
2233 | ||
2234 | static VMStateDescription qxl_surface = { | |
2235 | .name = "qxl-surface", | |
2236 | .version_id = QXL_SAVE_VERSION, | |
2237 | .minimum_version_id = QXL_SAVE_VERSION, | |
2238 | .fields = (VMStateField[]) { | |
2239 | VMSTATE_UINT32(width, QXLSurfaceCreate), | |
2240 | VMSTATE_UINT32(height, QXLSurfaceCreate), | |
2241 | VMSTATE_INT32(stride, QXLSurfaceCreate), | |
2242 | VMSTATE_UINT32(format, QXLSurfaceCreate), | |
2243 | VMSTATE_UINT32(position, QXLSurfaceCreate), | |
2244 | VMSTATE_UINT32(mouse_mode, QXLSurfaceCreate), | |
2245 | VMSTATE_UINT32(flags, QXLSurfaceCreate), | |
2246 | VMSTATE_UINT32(type, QXLSurfaceCreate), | |
2247 | VMSTATE_UINT64(mem, QXLSurfaceCreate), | |
2248 | VMSTATE_END_OF_LIST() | |
2249 | } | |
2250 | }; | |
2251 | ||
020af1c4 AL |
2252 | static VMStateDescription qxl_vmstate_monitors_config = { |
2253 | .name = "qxl/monitors-config", | |
2254 | .version_id = 1, | |
2255 | .minimum_version_id = 1, | |
2256 | .fields = (VMStateField[]) { | |
2257 | VMSTATE_UINT64(guest_monitors_config, PCIQXLDevice), | |
2258 | VMSTATE_END_OF_LIST() | |
2259 | }, | |
2260 | }; | |
2261 | ||
a19cbfb3 GH |
2262 | static VMStateDescription qxl_vmstate = { |
2263 | .name = "qxl", | |
2264 | .version_id = QXL_SAVE_VERSION, | |
2265 | .minimum_version_id = QXL_SAVE_VERSION, | |
2266 | .pre_save = qxl_pre_save, | |
2267 | .pre_load = qxl_pre_load, | |
2268 | .post_load = qxl_post_load, | |
020af1c4 | 2269 | .fields = (VMStateField[]) { |
a19cbfb3 GH |
2270 | VMSTATE_PCI_DEVICE(pci, PCIQXLDevice), |
2271 | VMSTATE_STRUCT(vga, PCIQXLDevice, 0, vmstate_vga_common, VGACommonState), | |
2272 | VMSTATE_UINT32(shadow_rom.mode, PCIQXLDevice), | |
2273 | VMSTATE_UINT32(num_free_res, PCIQXLDevice), | |
2274 | VMSTATE_UINT32(last_release_offset, PCIQXLDevice), | |
2275 | VMSTATE_UINT32(mode, PCIQXLDevice), | |
2276 | VMSTATE_UINT32(ssd.unique, PCIQXLDevice), | |
b67737a6 GH |
2277 | VMSTATE_INT32_EQUAL(num_memslots, PCIQXLDevice), |
2278 | VMSTATE_STRUCT_ARRAY(guest_slots, PCIQXLDevice, NUM_MEMSLOTS, 0, | |
2279 | qxl_memslot, struct guest_slots), | |
2280 | VMSTATE_STRUCT(guest_primary.surface, PCIQXLDevice, 0, | |
2281 | qxl_surface, QXLSurfaceCreate), | |
ddd8fdc7 GH |
2282 | VMSTATE_INT32_EQUAL(ssd.num_surfaces, PCIQXLDevice), |
2283 | VMSTATE_VARRAY_INT32(guest_surfaces.cmds, PCIQXLDevice, | |
2284 | ssd.num_surfaces, 0, | |
2285 | vmstate_info_uint64, uint64_t), | |
b67737a6 | 2286 | VMSTATE_UINT64(guest_cursor, PCIQXLDevice), |
a19cbfb3 GH |
2287 | VMSTATE_END_OF_LIST() |
2288 | }, | |
020af1c4 AL |
2289 | .subsections = (VMStateSubsection[]) { |
2290 | { | |
2291 | .vmsd = &qxl_vmstate_monitors_config, | |
2292 | .needed = qxl_monitors_config_needed, | |
2293 | }, { | |
2294 | /* empty */ | |
2295 | } | |
2296 | } | |
a19cbfb3 GH |
2297 | }; |
2298 | ||
78e60ba5 GH |
2299 | static Property qxl_properties[] = { |
2300 | DEFINE_PROP_UINT32("ram_size", PCIQXLDevice, vga.vram_size, | |
2301 | 64 * 1024 * 1024), | |
6f2b175a | 2302 | DEFINE_PROP_UINT32("vram_size", PCIQXLDevice, vram32_size, |
78e60ba5 GH |
2303 | 64 * 1024 * 1024), |
2304 | DEFINE_PROP_UINT32("revision", PCIQXLDevice, revision, | |
2305 | QXL_DEFAULT_REVISION), | |
2306 | DEFINE_PROP_UINT32("debug", PCIQXLDevice, debug, 0), | |
2307 | DEFINE_PROP_UINT32("guestdebug", PCIQXLDevice, guestdebug, 0), | |
2308 | DEFINE_PROP_UINT32("cmdlog", PCIQXLDevice, cmdlog, 0), | |
017438ee | 2309 | DEFINE_PROP_UINT32("ram_size_mb", PCIQXLDevice, ram_size_mb, -1), |
79ce3567 AL |
2310 | DEFINE_PROP_UINT32("vram_size_mb", PCIQXLDevice, vram32_size_mb, -1), |
2311 | DEFINE_PROP_UINT32("vram64_size_mb", PCIQXLDevice, vram_size_mb, -1), | |
9e56edcf | 2312 | DEFINE_PROP_UINT32("vgamem_mb", PCIQXLDevice, vgamem_size_mb, 16), |
ddd8fdc7 | 2313 | DEFINE_PROP_INT32("surfaces", PCIQXLDevice, ssd.num_surfaces, 1024), |
78e60ba5 GH |
2314 | DEFINE_PROP_END_OF_LIST(), |
2315 | }; | |
2316 | ||
40021f08 AL |
2317 | static void qxl_primary_class_init(ObjectClass *klass, void *data) |
2318 | { | |
39bffca2 | 2319 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
2320 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
2321 | ||
2322 | k->no_hotplug = 1; | |
2323 | k->init = qxl_init_primary; | |
2324 | k->romfile = "vgabios-qxl.bin"; | |
2325 | k->vendor_id = REDHAT_PCI_VENDOR_ID; | |
2326 | k->device_id = QXL_DEVICE_ID_STABLE; | |
2327 | k->class_id = PCI_CLASS_DISPLAY_VGA; | |
39bffca2 AL |
2328 | dc->desc = "Spice QXL GPU (primary, vga compatible)"; |
2329 | dc->reset = qxl_reset_handler; | |
2330 | dc->vmsd = &qxl_vmstate; | |
2331 | dc->props = qxl_properties; | |
40021f08 AL |
2332 | } |
2333 | ||
8c43a6f0 | 2334 | static const TypeInfo qxl_primary_info = { |
39bffca2 AL |
2335 | .name = "qxl-vga", |
2336 | .parent = TYPE_PCI_DEVICE, | |
2337 | .instance_size = sizeof(PCIQXLDevice), | |
2338 | .class_init = qxl_primary_class_init, | |
a19cbfb3 GH |
2339 | }; |
2340 | ||
40021f08 AL |
2341 | static void qxl_secondary_class_init(ObjectClass *klass, void *data) |
2342 | { | |
39bffca2 | 2343 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
2344 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
2345 | ||
2346 | k->init = qxl_init_secondary; | |
2347 | k->vendor_id = REDHAT_PCI_VENDOR_ID; | |
2348 | k->device_id = QXL_DEVICE_ID_STABLE; | |
2349 | k->class_id = PCI_CLASS_DISPLAY_OTHER; | |
39bffca2 AL |
2350 | dc->desc = "Spice QXL GPU (secondary)"; |
2351 | dc->reset = qxl_reset_handler; | |
2352 | dc->vmsd = &qxl_vmstate; | |
2353 | dc->props = qxl_properties; | |
40021f08 AL |
2354 | } |
2355 | ||
8c43a6f0 | 2356 | static const TypeInfo qxl_secondary_info = { |
39bffca2 AL |
2357 | .name = "qxl", |
2358 | .parent = TYPE_PCI_DEVICE, | |
2359 | .instance_size = sizeof(PCIQXLDevice), | |
2360 | .class_init = qxl_secondary_class_init, | |
a19cbfb3 GH |
2361 | }; |
2362 | ||
83f7d43a | 2363 | static void qxl_register_types(void) |
a19cbfb3 | 2364 | { |
39bffca2 AL |
2365 | type_register_static(&qxl_primary_info); |
2366 | type_register_static(&qxl_secondary_info); | |
a19cbfb3 GH |
2367 | } |
2368 | ||
83f7d43a | 2369 | type_init(qxl_register_types) |