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target/ppc: Remove msr_ile macro
[qemu.git] / target / ppc / cpu.h
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79aceca5 1/*
3fc6c082 2 * PowerPC emulation cpu definitions for qemu.
5fafdf24 3 *
76a66253 4 * Copyright (c) 2003-2007 Jocelyn Mayer
79aceca5
FB		 5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
6bd039cd 9 * version 2.1 of the License, or (at your option) any later version.
79aceca5
FB		 10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
8167ee88 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
79aceca5 18 */
07f5a258
MA		 19
20#ifndef PPC_CPU_H
21#define PPC_CPU_H
79aceca5 22
60caf221 23#include "qemu/int128.h"
69242e7e 24#include "qemu/cpu-float.h"
74433bf0
RH		 25#include "exec/cpu-defs.h"
26#include "cpu-qom.h"
db1015e9 27#include "qom/object.h"
d41ccf6e 28#include "hw/registerfields.h"
3fc6c082 29
f0b0685d
ND		 30#define TCG_GUEST_DEFAULT_MO 0
31
ad3e67d0 32#define TARGET_PAGE_BITS_64K 16
81762d6d
DG		 33#define TARGET_PAGE_BITS_16M 24
34
c647e3fe 35#if defined(TARGET_PPC64)
4ecd4d16 36#define PPC_ELF_MACHINE EM_PPC64
76a66253 37#else
4ecd4d16 38#define PPC_ELF_MACHINE EM_PPC
76a66253 39#endif
9042c0e2 40
a7d4b1bf
CLG		 41#define PPC_BIT(bit) (0x8000000000000000ULL >> (bit))
42#define PPC_BIT32(bit) (0x80000000 >> (bit))
43#define PPC_BIT8(bit) (0x80 >> (bit))
2a83f997
CLG		 44#define PPC_BITMASK(bs, be) ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs))
45#define PPC_BITMASK32(bs, be) ((PPC_BIT32(bs) - PPC_BIT32(be)) | \
46 PPC_BIT32(bs))
a6a444a8
CLG		 47#define PPC_BITMASK8(bs, be) ((PPC_BIT8(bs) - PPC_BIT8(be)) | PPC_BIT8(bs))
48
e1833e1f
JM		 49/*****************************************************************************/
50/* Exception vectors definitions */
51enum {
52 POWERPC_EXCP_NONE = -1,
53 /* The 64 first entries are used by the PowerPC embedded specification */
54 POWERPC_EXCP_CRITICAL = 0, /* Critical input */
55 POWERPC_EXCP_MCHECK = 1, /* Machine check exception */
56 POWERPC_EXCP_DSI = 2, /* Data storage exception */
57 POWERPC_EXCP_ISI = 3, /* Instruction storage exception */
58 POWERPC_EXCP_EXTERNAL = 4, /* External input */
59 POWERPC_EXCP_ALIGN = 5, /* Alignment exception */
60 POWERPC_EXCP_PROGRAM = 6, /* Program exception */
61 POWERPC_EXCP_FPU = 7, /* Floating-point unavailable exception */
62 POWERPC_EXCP_SYSCALL = 8, /* System call exception */
63 POWERPC_EXCP_APU = 9, /* Auxiliary processor unavailable */
64 POWERPC_EXCP_DECR = 10, /* Decrementer exception */
65 POWERPC_EXCP_FIT = 11, /* Fixed-interval timer interrupt */
66 POWERPC_EXCP_WDT = 12, /* Watchdog timer interrupt */
b4095fed
JM		 67 POWERPC_EXCP_DTLB = 13, /* Data TLB miss */
68 POWERPC_EXCP_ITLB = 14, /* Instruction TLB miss */
e1833e1f
JM		 69 POWERPC_EXCP_DEBUG = 15, /* Debug interrupt */
70 /* Vectors 16 to 31 are reserved */
e1833e1f
JM		 71 POWERPC_EXCP_SPEU = 32, /* SPE/embedded floating-point unavailable */
72 POWERPC_EXCP_EFPDI = 33, /* Embedded floating-point data interrupt */
73 POWERPC_EXCP_EFPRI = 34, /* Embedded floating-point round interrupt */
74 POWERPC_EXCP_EPERFM = 35, /* Embedded performance monitor interrupt */
75 POWERPC_EXCP_DOORI = 36, /* Embedded doorbell interrupt */
76 POWERPC_EXCP_DOORCI = 37, /* Embedded doorbell critical interrupt */
0ef654e3
AG		 77 POWERPC_EXCP_GDOORI = 38, /* Embedded guest doorbell interrupt */
78 POWERPC_EXCP_GDOORCI = 39, /* Embedded guest doorbell critical interrupt*/
79 POWERPC_EXCP_HYPPRIV = 41, /* Embedded hypervisor priv instruction */
80 /* Vectors 42 to 63 are reserved */
e1833e1f
JM		 81 /* Exceptions defined in the PowerPC server specification */
82 POWERPC_EXCP_RESET = 64, /* System reset exception */
e1833e1f
JM		 83 POWERPC_EXCP_DSEG = 65, /* Data segment exception */
84 POWERPC_EXCP_ISEG = 66, /* Instruction segment exception */
e1833e1f 85 POWERPC_EXCP_HDECR = 67, /* Hypervisor decrementer exception */
e1833e1f 86 POWERPC_EXCP_TRACE = 68, /* Trace exception */
e1833e1f
JM		 87 POWERPC_EXCP_HDSI = 69, /* Hypervisor data storage exception */
88 POWERPC_EXCP_HISI = 70, /* Hypervisor instruction storage exception */
89 POWERPC_EXCP_HDSEG = 71, /* Hypervisor data segment exception */
90 POWERPC_EXCP_HISEG = 72, /* Hypervisor instruction segment exception */
e1833e1f
JM		 91 POWERPC_EXCP_VPU = 73, /* Vector unavailable exception */
92 /* 40x specific exceptions */
93 POWERPC_EXCP_PIT = 74, /* Programmable interval timer interrupt */
005b69fd 94 /* Vectors 75-76 are 601 specific exceptions */
e1833e1f 95 /* 602 specific exceptions */
005b69fd 96 POWERPC_EXCP_EMUL = 77, /* Emulation trap exception */
e1833e1f 97 /* 602/603 specific exceptions */
b4095fed 98 POWERPC_EXCP_IFTLB = 78, /* Instruction fetch TLB miss */
e1833e1f
JM		 99 POWERPC_EXCP_DLTLB = 79, /* Data load TLB miss */
100 POWERPC_EXCP_DSTLB = 80, /* Data store TLB miss */
101 /* Exceptions available on most PowerPC */
102 POWERPC_EXCP_FPA = 81, /* Floating-point assist exception */
b4095fed
JM		 103 POWERPC_EXCP_DABR = 82, /* Data address breakpoint */
104 POWERPC_EXCP_IABR = 83, /* Instruction address breakpoint */
105 POWERPC_EXCP_SMI = 84, /* System management interrupt */
106 POWERPC_EXCP_PERFM = 85, /* Embedded performance monitor interrupt */
e1833e1f 107 /* 7xx/74xx specific exceptions */
b4095fed 108 POWERPC_EXCP_THERM = 86, /* Thermal interrupt */
e1833e1f 109 /* 74xx specific exceptions */
b4095fed 110 POWERPC_EXCP_VPUA = 87, /* Vector assist exception */
e1833e1f 111 /* 970FX specific exceptions */
b4095fed
JM		 112 POWERPC_EXCP_SOFTP = 88, /* Soft patch exception */
113 POWERPC_EXCP_MAINT = 89, /* Maintenance exception */
5b46d07d 114 /* Freescale embedded cores specific exceptions */
b4095fed
JM		 115 POWERPC_EXCP_MEXTBR = 90, /* Maskable external breakpoint */
116 POWERPC_EXCP_NMEXTBR = 91, /* Non maskable external breakpoint */
117 POWERPC_EXCP_ITLBE = 92, /* Instruction TLB error */
118 POWERPC_EXCP_DTLBE = 93, /* Data TLB error */
1f29871c
TM		 119 /* VSX Unavailable (Power ISA 2.06 and later) */
120 POWERPC_EXCP_VSXU = 94, /* VSX Unavailable */
7019cb3d 121 POWERPC_EXCP_FU = 95, /* Facility Unavailable */
f03a1af5
BH		 122 /* Additional ISA 2.06 and later server exceptions */
123 POWERPC_EXCP_HV_EMU = 96, /* HV emulation assistance */
124 POWERPC_EXCP_HV_MAINT = 97, /* HMI */
125 POWERPC_EXCP_HV_FU = 98, /* Hypervisor Facility unavailable */
1414c75d
CLG		 126 /* Server doorbell variants */
127 POWERPC_EXCP_SDOOR = 99,
128 POWERPC_EXCP_SDOOR_HV = 100,
d8ce5fd6
BH		 129 /* ISA 3.00 additions */
130 POWERPC_EXCP_HVIRT = 101,
3c89b8d6 131 POWERPC_EXCP_SYSCALL_VECTORED = 102, /* scv exception */
cb76bbc4
DHB		 132 POWERPC_EXCP_PERFM_EBB = 103, /* Performance Monitor EBB Exception */
133 POWERPC_EXCP_EXTERNAL_EBB = 104, /* External EBB Exception */
e1833e1f 134 /* EOL */
cb76bbc4 135 POWERPC_EXCP_NB = 105,
5cbdb3a3 136 /* QEMU exceptions: special cases we want to stop translation */
e1833e1f
JM		 137 POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only */
138};
139
e1833e1f
JM		 140/* Exceptions error codes */
141enum {
142 /* Exception subtypes for POWERPC_EXCP_ALIGN */
143 POWERPC_EXCP_ALIGN_FP = 0x01, /* FP alignment exception */
144 POWERPC_EXCP_ALIGN_LST = 0x02, /* Unaligned mult/extern load/store */
145 POWERPC_EXCP_ALIGN_LE = 0x03, /* Multiple little-endian access */
146 POWERPC_EXCP_ALIGN_PROT = 0x04, /* Access cross protection boundary */
147 POWERPC_EXCP_ALIGN_BAT = 0x05, /* Access cross a BAT/seg boundary */
148 POWERPC_EXCP_ALIGN_CACHE = 0x06, /* Impossible dcbz access */
99082815 149 POWERPC_EXCP_ALIGN_INSN = 0x07, /* Pref. insn x-ing 64-byte boundary */
e1833e1f
JM		 150 /* Exception subtypes for POWERPC_EXCP_PROGRAM */
151 /* FP exceptions */
152 POWERPC_EXCP_FP = 0x10,
153 POWERPC_EXCP_FP_OX = 0x01, /* FP overflow */
154 POWERPC_EXCP_FP_UX = 0x02, /* FP underflow */
155 POWERPC_EXCP_FP_ZX = 0x03, /* FP divide by zero */
156 POWERPC_EXCP_FP_XX = 0x04, /* FP inexact */
7c58044c 157 POWERPC_EXCP_FP_VXSNAN = 0x05, /* FP invalid SNaN op */
e1833e1f
JM		 158 POWERPC_EXCP_FP_VXISI = 0x06, /* FP invalid infinite subtraction */
159 POWERPC_EXCP_FP_VXIDI = 0x07, /* FP invalid infinite divide */
160 POWERPC_EXCP_FP_VXZDZ = 0x08, /* FP invalid zero divide */
161 POWERPC_EXCP_FP_VXIMZ = 0x09, /* FP invalid infinite * zero */
162 POWERPC_EXCP_FP_VXVC = 0x0A, /* FP invalid compare */
163 POWERPC_EXCP_FP_VXSOFT = 0x0B, /* FP invalid operation */
164 POWERPC_EXCP_FP_VXSQRT = 0x0C, /* FP invalid square root */
165 POWERPC_EXCP_FP_VXCVI = 0x0D, /* FP invalid integer conversion */
166 /* Invalid instruction */
167 POWERPC_EXCP_INVAL = 0x20,
168 POWERPC_EXCP_INVAL_INVAL = 0x01, /* Invalid instruction */
169 POWERPC_EXCP_INVAL_LSWX = 0x02, /* Invalid lswx instruction */
170 POWERPC_EXCP_INVAL_SPR = 0x03, /* Invalid SPR access */
171 POWERPC_EXCP_INVAL_FP = 0x04, /* Unimplemented mandatory fp instr */
172 /* Privileged instruction */
173 POWERPC_EXCP_PRIV = 0x30,
174 POWERPC_EXCP_PRIV_OPC = 0x01, /* Privileged operation exception */
175 POWERPC_EXCP_PRIV_REG = 0x02, /* Privileged register exception */
176 /* Trap */
177 POWERPC_EXCP_TRAP = 0x40,
178};
179
25458103 180#define PPC_INPUT(env) ((env)->bus_model)
3fc6c082 181
be147d08 182/*****************************************************************************/
c227f099 183typedef struct opc_handler_t opc_handler_t;
79aceca5 184
3fc6c082 185/*****************************************************************************/
7222b94a 186/* Types used to describe some PowerPC registers etc. */
69b058c8 187typedef struct DisasContext DisasContext;
c227f099 188typedef struct ppc_spr_t ppc_spr_t;
c227f099 189typedef union ppc_tlb_t ppc_tlb_t;
1ad9f0a4 190typedef struct ppc_hash_pte64 ppc_hash_pte64_t;
76a66253 191
3fc6c082 192/* SPR access micro-ops generations callbacks */
c227f099 193struct ppc_spr_t {
72369f5c
RH		 194 const char *name;
195 target_ulong default_value;
196#ifndef CONFIG_USER_ONLY
197 unsigned int gdb_id;
198#endif
199#ifdef CONFIG_TCG
69b058c8
PB		 200 void (*uea_read)(DisasContext *ctx, int gpr_num, int spr_num);
201 void (*uea_write)(DisasContext *ctx, int spr_num, int gpr_num);
72369f5c 202# ifndef CONFIG_USER_ONLY
69b058c8
PB		 203 void (*oea_read)(DisasContext *ctx, int gpr_num, int spr_num);
204 void (*oea_write)(DisasContext *ctx, int spr_num, int gpr_num);
205 void (*hea_read)(DisasContext *ctx, int gpr_num, int spr_num);
206 void (*hea_write)(DisasContext *ctx, int spr_num, int gpr_num);
72369f5c 207# endif
76a66253 208#endif
d67d40ea 209#ifdef CONFIG_KVM
c647e3fe
DG		 210 /*
211 * We (ab)use the fact that all the SPRs will have ids for the
d67d40ea 212 * ONE_REG interface will have KVM_REG_PPC to use 0 as meaning,
c647e3fe
DG		 213 * don't sync this
214 */
d67d40ea
DG		 215 uint64_t one_reg_id;
216#endif
3fc6c082
FB		 217};
218
05ee3e8a
MCA		 219/* VSX/Altivec registers (128 bits) */
220typedef union _ppc_vsr_t {
a9d9eb8f
JM		 221 uint8_t u8[16];
222 uint16_t u16[8];
223 uint32_t u32[4];
05ee3e8a 224 uint64_t u64[2];
ab5f265d
AJ		 225 int8_t s8[16];
226 int16_t s16[8];
227 int32_t s32[4];
bb527533 228 int64_t s64[2];
05ee3e8a
MCA		 229 float32 f32[4];
230 float64 f64[2];
231 float128 f128;
bb527533
TM		 232#ifdef CONFIG_INT128
233 __uint128_t u128;
234#endif
05ee3e8a
MCA		 235 Int128 s128;
236} ppc_vsr_t;
237
238typedef ppc_vsr_t ppc_avr_t;
d9acba31 239typedef ppc_vsr_t ppc_fprp_t;
9fddaa0c 240
3c7b48b7 241#if !defined(CONFIG_USER_ONLY)
3fc6c082 242/* Software TLB cache */
c227f099
AL		 243typedef struct ppc6xx_tlb_t ppc6xx_tlb_t;
244struct ppc6xx_tlb_t {
76a66253
JM		 245 target_ulong pte0;
246 target_ulong pte1;
247 target_ulong EPN;
1d0a48fb
JM		 248};
249
c227f099
AL		 250typedef struct ppcemb_tlb_t ppcemb_tlb_t;
251struct ppcemb_tlb_t {
b162d02e 252 uint64_t RPN;
1d0a48fb 253 target_ulong EPN;
76a66253 254 target_ulong PID;
c55e9aef
JM		 255 target_ulong size;
256 uint32_t prot;
257 uint32_t attr; /* Storage attributes */
1d0a48fb
JM		 258};
259
d1e256fe
AG		 260typedef struct ppcmas_tlb_t {
261 uint32_t mas8;
262 uint32_t mas1;
263 uint64_t mas2;
264 uint64_t mas7_3;
265} ppcmas_tlb_t;
266
c227f099 267union ppc_tlb_t {
1c53accc
AG		 268 ppc6xx_tlb_t *tlb6;
269 ppcemb_tlb_t *tlbe;
270 ppcmas_tlb_t *tlbm;
3fc6c082 271};
1c53accc
AG		 272
273/* possible TLB variants */
274#define TLB_NONE 0
275#define TLB_6XX 1
276#define TLB_EMB 2
277#define TLB_MAS 3
3c7b48b7 278#endif
3fc6c082 279
b07c59f7
DG		 280typedef struct PPCHash64SegmentPageSizes PPCHash64SegmentPageSizes;
281
c227f099
AL		 282typedef struct ppc_slb_t ppc_slb_t;
283struct ppc_slb_t {
81762d6d
DG		 284 uint64_t esid;
285 uint64_t vsid;
b07c59f7 286 const PPCHash64SegmentPageSizes *sps;
8eee0af9
BS		 287};
288
d83af167 289#define MAX_SLB_ENTRIES 64
81762d6d
DG		 290#define SEGMENT_SHIFT_256M 28
291#define SEGMENT_MASK_256M (~((1ULL << SEGMENT_SHIFT_256M) - 1))
292
cdaee006
DG		 293#define SEGMENT_SHIFT_1T 40
294#define SEGMENT_MASK_1T (~((1ULL << SEGMENT_SHIFT_1T) - 1))
295
79825f4d
BH		 296typedef struct ppc_v3_pate_t {
297 uint64_t dw0;
298 uint64_t dw1;
299} ppc_v3_pate_t;
cdaee006 300
8f2e9d40
DHB		 301/* PMU related structs and defines */
302#define PMU_COUNTERS_NUM 6
303typedef enum {
304 PMU_EVENT_INVALID = 0,
305 PMU_EVENT_INACTIVE,
306 PMU_EVENT_CYCLES,
307 PMU_EVENT_INSTRUCTIONS,
7aeac354 308 PMU_EVENT_INSN_RUN_LATCH,
8f2e9d40
DHB		 309} PMUEventType;
310
3fc6c082
FB		 311/*****************************************************************************/
312/* Machine state register bits definition */
76a66253 313#define MSR_SF 63 /* Sixty-four-bit mode hflags */
bd928eba 314#define MSR_TAG 62 /* Tag-active mode (POWERx ?) */
3fc6c082 315#define MSR_ISF 61 /* Sixty-four-bit interrupt mode on 630 */
23513f81 316#define MSR_HV 60 /* hypervisor state hflags */
cdcdda27
AK		 317#define MSR_TS0 34 /* Transactional state, 2 bits (Book3s) */
318#define MSR_TS1 33
319#define MSR_TM 32 /* Transactional Memory Available (Book3s) */
363be49c
JM		 320#define MSR_CM 31 /* Computation mode for BookE hflags */
321#define MSR_ICM 30 /* Interrupt computation mode for BookE */
71afeb61 322#define MSR_GS 28 /* guest state for BookE */
363be49c 323#define MSR_UCLE 26 /* User-mode cache lock enable for BookE */
d26bfc9a
JM		 324#define MSR_VR 25 /* altivec available x hflags */
325#define MSR_SPE 25 /* SPE enable for BookE x hflags */
1f29871c 326#define MSR_VSX 23 /* Vector Scalar Extension (ISA 2.06 and later) x hflags */
6fa5726b 327#define MSR_S 22 /* Secure state */
3fc6c082 328#define MSR_KEY 19 /* key bit on 603e */
25ba3a68 329#define MSR_POW 18 /* Power management */
645d843c 330#define MSR_WE 18 /* Wait State Enable on 405 */
d26bfc9a
JM		 331#define MSR_TGPR 17 /* TGPR usage on 602/603 x */
332#define MSR_CE 17 /* Critical interrupt enable on embedded PowerPC x */
3fc6c082
FB		 333#define MSR_ILE 16 /* Interrupt little-endian mode */
334#define MSR_EE 15 /* External interrupt enable */
76a66253
JM		 335#define MSR_PR 14 /* Problem state hflags */
336#define MSR_FP 13 /* Floating point available hflags */
3fc6c082 337#define MSR_ME 12 /* Machine check interrupt enable */
56ced497 338#define MSR_FE0 11 /* Floating point exception mode 0 */
d26bfc9a
JM		 339#define MSR_SE 10 /* Single-step trace enable x hflags */
340#define MSR_DWE 10 /* Debug wait enable on 405 x */
341#define MSR_UBLE 10 /* User BTB lock enable on e500 x */
342#define MSR_BE 9 /* Branch trace enable x hflags */
343#define MSR_DE 9 /* Debug interrupts enable on embedded PowerPC x */
56ced497 344#define MSR_FE1 8 /* Floating point exception mode 1 */
3fc6c082 345#define MSR_AL 7 /* AL bit on POWER */
0411a972 346#define MSR_EP 6 /* Exception prefix on 601 */
3fc6c082 347#define MSR_IR 5 /* Instruction relocate */
3fc6c082 348#define MSR_DR 4 /* Data relocate */
9fb04491
BH		 349#define MSR_IS 5 /* Instruction address space (BookE) */
350#define MSR_DS 4 /* Data address space (BookE) */
25ba3a68 351#define MSR_PE 3 /* Protection enable on 403 */
d26bfc9a
JM		 352#define MSR_PX 2 /* Protection exclusive on 403 x */
353#define MSR_PMM 2 /* Performance monitor mark on POWER x */
354#define MSR_RI 1 /* Recoverable interrupt 1 */
355#define MSR_LE 0 /* Little-endian mode 1 hflags */
0411a972 356
3868540f 357FIELD(MSR, ILE, MSR_ILE, 1)
d41ccf6e 358FIELD(MSR, PR, MSR_PR, 1)
26363616 359FIELD(MSR, DS, MSR_DS, 1)
1922322c 360FIELD(MSR, LE, MSR_LE, 1)
d41ccf6e 361
f7460df2 362/* PMU bits */
565cb109
GR		 363#define MMCR0_FC PPC_BIT(32) /* Freeze Counters */
364#define MMCR0_PMAO PPC_BIT(56) /* Perf Monitor Alert Ocurred */
365#define MMCR0_PMAE PPC_BIT(37) /* Perf Monitor Alert Enable */
366#define MMCR0_EBE PPC_BIT(43) /* Perf Monitor EBB Enable */
367#define MMCR0_FCECE PPC_BIT(38) /* FC on Enabled Cond or Event */
f7460df2
DHB		 368#define MMCR0_PMCC0 PPC_BIT(44) /* PMC Control bit 0 */
369#define MMCR0_PMCC1 PPC_BIT(45) /* PMC Control bit 1 */
c2eff582
DHB		 370#define MMCR0_PMCC PPC_BITMASK(44, 45) /* PMC Control */
371#define MMCR0_FC14 PPC_BIT(58) /* PMC Freeze Counters 1-4 bit */
372#define MMCR0_FC56 PPC_BIT(59) /* PMC Freeze Counters 5-6 bit */
1474ba6d
DHB		 373#define MMCR0_PMC1CE PPC_BIT(48) /* MMCR0 PMC1 Condition Enabled */
374#define MMCR0_PMCjCE PPC_BIT(49) /* MMCR0 PMCj Condition Enabled */
565cb109
GR		 375/* MMCR0 userspace r/w mask */
376#define MMCR0_UREG_MASK (MMCR0_FC | MMCR0_PMAO | MMCR0_PMAE)
7b3ecf16
DHB		 377/* MMCR2 userspace r/w mask */
378#define MMCR2_FC1P0 PPC_BIT(1) /* MMCR2 FCnP0 for PMC1 */
379#define MMCR2_FC2P0 PPC_BIT(10) /* MMCR2 FCnP0 for PMC2 */
380#define MMCR2_FC3P0 PPC_BIT(19) /* MMCR2 FCnP0 for PMC3 */
381#define MMCR2_FC4P0 PPC_BIT(28) /* MMCR2 FCnP0 for PMC4 */
382#define MMCR2_FC5P0 PPC_BIT(37) /* MMCR2 FCnP0 for PMC5 */
383#define MMCR2_FC6P0 PPC_BIT(46) /* MMCR2 FCnP0 for PMC6 */
384#define MMCR2_UREG_MASK (MMCR2_FC1P0 | MMCR2_FC2P0 | MMCR2_FC3P0 | \
385 MMCR2_FC4P0 | MMCR2_FC5P0 | MMCR2_FC6P0)
f7460df2 386
c2eff582
DHB		 387#define MMCR1_EVT_SIZE 8
388/* extract64() does a right shift before extracting */
389#define MMCR1_PMC1SEL_START 32
390#define MMCR1_PMC1EVT_EXTR (64 - MMCR1_PMC1SEL_START - MMCR1_EVT_SIZE)
391#define MMCR1_PMC2SEL_START 40
392#define MMCR1_PMC2EVT_EXTR (64 - MMCR1_PMC2SEL_START - MMCR1_EVT_SIZE)
393#define MMCR1_PMC3SEL_START 48
394#define MMCR1_PMC3EVT_EXTR (64 - MMCR1_PMC3SEL_START - MMCR1_EVT_SIZE)
395#define MMCR1_PMC4SEL_START 56
396#define MMCR1_PMC4EVT_EXTR (64 - MMCR1_PMC4SEL_START - MMCR1_EVT_SIZE)
397
7aeac354
DHB		 398/* PMU uses CTRL_RUN to sample PM_RUN_INST_CMPL */
399#define CTRL_RUN PPC_BIT(63)
400
1f26c751
DHB		 401/* EBB/BESCR bits */
402/* Global Enable */
403#define BESCR_GE PPC_BIT(0)
404/* External Event-based Exception Enable */
405#define BESCR_EE PPC_BIT(30)
406/* Performance Monitor Event-based Exception Enable */
407#define BESCR_PME PPC_BIT(31)
408/* External Event-based Exception Occurred */
409#define BESCR_EEO PPC_BIT(62)
410/* Performance Monitor Event-based Exception Occurred */
411#define BESCR_PMEO PPC_BIT(63)
412#define BESCR_INVALID PPC_BITMASK(32, 33)
413
1488270e 414/* LPCR bits */
2a83f997
CLG		 415#define LPCR_VPM0 PPC_BIT(0)
416#define LPCR_VPM1 PPC_BIT(1)
417#define LPCR_ISL PPC_BIT(2)
418#define LPCR_KBV PPC_BIT(3)
88536935 419#define LPCR_DPFD_SHIFT (63 - 11)
7659ca1a 420#define LPCR_DPFD (0x7ull << LPCR_DPFD_SHIFT)
88536935
BH		 421#define LPCR_VRMASD_SHIFT (63 - 16)
422#define LPCR_VRMASD (0x1full << LPCR_VRMASD_SHIFT)
18aa49ec
SJS		 423/* P9: Power-saving mode Exit Cause Enable (Upper Section) Mask */
424#define LPCR_PECE_U_SHIFT (63 - 19)
425#define LPCR_PECE_U_MASK (0x7ull << LPCR_PECE_U_SHIFT)
2a83f997 426#define LPCR_HVEE PPC_BIT(17) /* Hypervisor Virt Exit Enable */
526cdce7 427#define LPCR_RMLS_SHIFT (63 - 37) /* RMLS (removed in ISA v3.0) */
88536935 428#define LPCR_RMLS (0xfull << LPCR_RMLS_SHIFT)
526cdce7 429#define LPCR_HAIL PPC_BIT(37) /* ISA v3.1 HV AIL=3 equivalent */
2a83f997 430#define LPCR_ILE PPC_BIT(38)
526cdce7 431#define LPCR_AIL_SHIFT (63 - 40) /* Alternate interrupt location */
1488270e 432#define LPCR_AIL (3ull << LPCR_AIL_SHIFT)
2a83f997
CLG		 433#define LPCR_UPRT PPC_BIT(41) /* Use Process Table */
434#define LPCR_EVIRT PPC_BIT(42) /* Enhanced Virtualisation */
00fd075e 435#define LPCR_HR PPC_BIT(43) /* Host Radix */
2a83f997
CLG		 436#define LPCR_ONL PPC_BIT(45)
437#define LPCR_LD PPC_BIT(46) /* Large Decrementer */
438#define LPCR_P7_PECE0 PPC_BIT(49)
439#define LPCR_P7_PECE1 PPC_BIT(50)
440#define LPCR_P7_PECE2 PPC_BIT(51)
441#define LPCR_P8_PECE0 PPC_BIT(47)
442#define LPCR_P8_PECE1 PPC_BIT(48)
443#define LPCR_P8_PECE2 PPC_BIT(49)
444#define LPCR_P8_PECE3 PPC_BIT(50)
445#define LPCR_P8_PECE4 PPC_BIT(51)
18aa49ec
SJS		 446/* P9: Power-saving mode Exit Cause Enable (Lower Section) Mask */
447#define LPCR_PECE_L_SHIFT (63 - 51)
448#define LPCR_PECE_L_MASK (0x1full << LPCR_PECE_L_SHIFT)
2a83f997
CLG		 449#define LPCR_PDEE PPC_BIT(47) /* Privileged Doorbell Exit EN */
450#define LPCR_HDEE PPC_BIT(48) /* Hyperv Doorbell Exit Enable */
451#define LPCR_EEE PPC_BIT(49) /* External Exit Enable */
452#define LPCR_DEE PPC_BIT(50) /* Decrementer Exit Enable */
453#define LPCR_OEE PPC_BIT(51) /* Other Exit Enable */
454#define LPCR_MER PPC_BIT(52)
455#define LPCR_GTSE PPC_BIT(53) /* Guest Translation Shootdown */
456#define LPCR_TC PPC_BIT(54)
457#define LPCR_HEIC PPC_BIT(59) /* HV Extern Interrupt Control */
458#define LPCR_LPES0 PPC_BIT(60)
459#define LPCR_LPES1 PPC_BIT(61)
460#define LPCR_RMI PPC_BIT(62)
461#define LPCR_HVICE PPC_BIT(62) /* HV Virtualisation Int Enable */
462#define LPCR_HDICE PPC_BIT(63)
1e0c7e55 463
21c0d66a
BH		 464/* PSSCR bits */
465#define PSSCR_ESL PPC_BIT(42) /* Enable State Loss */
466#define PSSCR_EC PPC_BIT(43) /* Exit Criterion */
467
493028d8
CLG		 468/* HFSCR bits */
469#define HFSCR_MSGP PPC_BIT(53) /* Privileged Message Send Facilities */
470#define HFSCR_IC_MSGP 0xA
471
23513f81
DG		 472#if defined(TARGET_PPC64)
473#define msr_hv ((env->msr >> MSR_HV) & 1)
474#else
475#define msr_hv (0)
476#endif
0411a972 477#define msr_cm ((env->msr >> MSR_CM) & 1)
71afeb61 478#define msr_gs ((env->msr >> MSR_GS) & 1)
0411a972 479#define msr_pow ((env->msr >> MSR_POW) & 1)
0411a972 480#define msr_ce ((env->msr >> MSR_CE) & 1)
0411a972 481#define msr_ee ((env->msr >> MSR_EE) & 1)
0411a972
JM		 482#define msr_fp ((env->msr >> MSR_FP) & 1)
483#define msr_me ((env->msr >> MSR_ME) & 1)
484#define msr_fe0 ((env->msr >> MSR_FE0) & 1)
0411a972
JM		 485#define msr_de ((env->msr >> MSR_DE) & 1)
486#define msr_fe1 ((env->msr >> MSR_FE1) & 1)
0411a972
JM		 487#define msr_ep ((env->msr >> MSR_EP) & 1)
488#define msr_ir ((env->msr >> MSR_IR) & 1)
489#define msr_dr ((env->msr >> MSR_DR) & 1)
cdcdda27 490#define msr_ts ((env->msr >> MSR_TS1) & 3)
cdcdda27 491
0e3bf489
RK		 492#define DBCR0_ICMP (1 << 27)
493#define DBCR0_BRT (1 << 26)
494#define DBSR_ICMP (1 << 27)
495#define DBSR_BRT (1 << 26)
496
a4f30719
JM		 497/* Hypervisor bit is more specific */
498#if defined(TARGET_PPC64)
23513f81 499#define MSR_HVB (1ULL << MSR_HV)
a4f30719
JM		 500#else
501#define MSR_HVB (0ULL)
a4f30719 502#endif
79aceca5 503
da82c73a
SJS		 504/* DSISR */
505#define DSISR_NOPTE 0x40000000
506/* Not permitted by access authority of encoded access authority */
507#define DSISR_PROTFAULT 0x08000000
508#define DSISR_ISSTORE 0x02000000
509/* Not permitted by virtual page class key protection */
510#define DSISR_AMR 0x00200000
d5fee0bb
SJS		 511/* Unsupported Radix Tree Configuration */
512#define DSISR_R_BADCONFIG 0x00080000
d04ea940
CLG		 513#define DSISR_ATOMIC_RC 0x00040000
514/* Unable to translate address of (guest) pde or process/page table entry */
515#define DSISR_PRTABLE_FAULT 0x00020000
da82c73a 516
a6152b52
SJS		 517/* SRR1 error code fields */
518
da82c73a
SJS		 519#define SRR1_NOPTE DSISR_NOPTE
520/* Not permitted due to no-execute or guard bit set */
07a68f99 521#define SRR1_NOEXEC_GUARD 0x10000000
da82c73a
SJS		 522#define SRR1_PROTFAULT DSISR_PROTFAULT
523#define SRR1_IAMR DSISR_AMR
a6152b52 524
0911a60c
LB		 525/* SRR1[42:45] wakeup fields for System Reset Interrupt */
526
527#define SRR1_WAKEMASK 0x003c0000 /* reason for wakeup */
528
529#define SRR1_WAKEHMI 0x00280000 /* Hypervisor maintenance */
530#define SRR1_WAKEHVI 0x00240000 /* Hypervisor Virt. Interrupt (P9) */
531#define SRR1_WAKEEE 0x00200000 /* External interrupt */
532#define SRR1_WAKEDEC 0x00180000 /* Decrementer interrupt */
533#define SRR1_WAKEDBELL 0x00140000 /* Privileged doorbell */
534#define SRR1_WAKERESET 0x00100000 /* System reset */
535#define SRR1_WAKEHDBELL 0x000c0000 /* Hypervisor doorbell */
536#define SRR1_WAKESCOM 0x00080000 /* SCOM not in power-saving mode */
537
538/* SRR1[46:47] power-saving exit mode */
539
540#define SRR1_WAKESTATE 0x00030000 /* Powersave exit mask */
541
542#define SRR1_WS_HVLOSS 0x00030000 /* HV resources not maintained */
543#define SRR1_WS_GPRLOSS 0x00020000 /* GPRs not maintained */
544#define SRR1_WS_NOLOSS 0x00010000 /* All resources maintained */
545
7019cb3d
AK		 546/* Facility Status and Control (FSCR) bits */
547#define FSCR_EBB (63 - 56) /* Event-Based Branch Facility */
548#define FSCR_TAR (63 - 55) /* Target Address Register */
3c89b8d6 549#define FSCR_SCV (63 - 51) /* System call vectored */
7019cb3d
AK		 550/* Interrupt cause mask and position in FSCR. HFSCR has the same format */
551#define FSCR_IC_MASK (0xFFULL)
552#define FSCR_IC_POS (63 - 7)
553#define FSCR_IC_DSCR_SPR3 2
554#define FSCR_IC_PMU 3
555#define FSCR_IC_BHRB 4
556#define FSCR_IC_TM 5
557#define FSCR_IC_EBB 7
558#define FSCR_IC_TAR 8
3c89b8d6 559#define FSCR_IC_SCV 12
7019cb3d 560
a586e548 561/* Exception state register bits definition */
2a83f997
CLG		 562#define ESR_PIL PPC_BIT(36) /* Illegal Instruction */
563#define ESR_PPR PPC_BIT(37) /* Privileged Instruction */
564#define ESR_PTR PPC_BIT(38) /* Trap */
565#define ESR_FP PPC_BIT(39) /* Floating-Point Operation */
566#define ESR_ST PPC_BIT(40) /* Store Operation */
567#define ESR_AP PPC_BIT(44) /* Auxiliary Processor Operation */
568#define ESR_PUO PPC_BIT(45) /* Unimplemented Operation */
569#define ESR_BO PPC_BIT(46) /* Byte Ordering */
570#define ESR_PIE PPC_BIT(47) /* Imprecise exception */
571#define ESR_DATA PPC_BIT(53) /* Data Access (Embedded page table) */
572#define ESR_TLBI PPC_BIT(54) /* TLB Ineligible (Embedded page table) */
573#define ESR_PT PPC_BIT(55) /* Page Table (Embedded page table) */
574#define ESR_SPV PPC_BIT(56) /* SPE/VMX operation */
575#define ESR_EPID PPC_BIT(57) /* External Process ID operation */
576#define ESR_VLEMI PPC_BIT(58) /* VLE operation */
577#define ESR_MIF PPC_BIT(62) /* Misaligned instruction (VLE) */
a586e548 578
aac86237
TM		 579/* Transaction EXception And Summary Register bits */
580#define TEXASR_FAILURE_PERSISTENT (63 - 7)
581#define TEXASR_DISALLOWED (63 - 8)
582#define TEXASR_NESTING_OVERFLOW (63 - 9)
583#define TEXASR_FOOTPRINT_OVERFLOW (63 - 10)
584#define TEXASR_SELF_INDUCED_CONFLICT (63 - 11)
585#define TEXASR_NON_TRANSACTIONAL_CONFLICT (63 - 12)
586#define TEXASR_TRANSACTION_CONFLICT (63 - 13)
587#define TEXASR_TRANSLATION_INVALIDATION_CONFLICT (63 - 14)
588#define TEXASR_IMPLEMENTATION_SPECIFIC (63 - 15)
589#define TEXASR_INSTRUCTION_FETCH_CONFLICT (63 - 16)
590#define TEXASR_ABORT (63 - 31)
591#define TEXASR_SUSPENDED (63 - 32)
592#define TEXASR_PRIVILEGE_HV (63 - 34)
593#define TEXASR_PRIVILEGE_PR (63 - 35)
594#define TEXASR_FAILURE_SUMMARY (63 - 36)
595#define TEXASR_TFIAR_EXACT (63 - 37)
596#define TEXASR_ROT (63 - 38)
597#define TEXASR_TRANSACTION_LEVEL (63 - 52) /* 12 bits */
598
d26bfc9a 599enum {
4018bae9 600 POWERPC_FLAG_NONE = 0x00000000,
d26bfc9a 601 /* Flag for MSR bit 25 signification (VRE/SPE) */
4018bae9
JM		 602 POWERPC_FLAG_SPE = 0x00000001,
603 POWERPC_FLAG_VRE = 0x00000002,
d26bfc9a 604 /* Flag for MSR bit 17 signification (TGPR/CE) */
4018bae9
JM		 605 POWERPC_FLAG_TGPR = 0x00000004,
606 POWERPC_FLAG_CE = 0x00000008,
d26bfc9a 607 /* Flag for MSR bit 10 signification (SE/DWE/UBLE) */
4018bae9
JM		 608 POWERPC_FLAG_SE = 0x00000010,
609 POWERPC_FLAG_DWE = 0x00000020,
610 POWERPC_FLAG_UBLE = 0x00000040,
d26bfc9a 611 /* Flag for MSR bit 9 signification (BE/DE) */
4018bae9
JM		 612 POWERPC_FLAG_BE = 0x00000080,
613 POWERPC_FLAG_DE = 0x00000100,
a4f30719 614 /* Flag for MSR bit 2 signification (PX/PMM) */
4018bae9
JM		 615 POWERPC_FLAG_PX = 0x00000200,
616 POWERPC_FLAG_PMM = 0x00000400,
617 /* Flag for special features */
005b69fd 618 /* Decrementer clock */
4018bae9 619 POWERPC_FLAG_BUS_CLK = 0x00020000,
697ab892
DG		 620 /* Has CFAR */
621 POWERPC_FLAG_CFAR = 0x00040000,
74f23997
TM		 622 /* Has VSX */
623 POWERPC_FLAG_VSX = 0x00080000,
e43668a7
TM		 624 /* Has Transaction Memory (ISA 2.07) */
625 POWERPC_FLAG_TM = 0x00100000,
3c89b8d6
NP		 626 /* Has SCV (ISA 3.00) */
627 POWERPC_FLAG_SCV = 0x00200000,
d26bfc9a
JM		 628};
629
2df4fe7a
RH		 630/*
631 * Bits for env->hflags.
632 *
633 * Most of these bits overlap with corresponding bits in MSR,
634 * but some come from other sources. Those that do come from
635 * the MSR are validated in hreg_compute_hflags.
636 */
637enum {
005b69fd 638 HFLAGS_LE = 0, /* MSR_LE */
2df4fe7a
RH		 639 HFLAGS_HV = 1, /* computed from MSR_HV and other state */
640 HFLAGS_64 = 2, /* computed from MSR_CE and MSR_SF */
f03de3b4 641 HFLAGS_GTSE = 3, /* computed from SPR_LPCR[GTSE] */
2df4fe7a 642 HFLAGS_DR = 4, /* MSR_DR */
1db3632a 643 HFLAGS_HR = 5, /* computed from SPR_LPCR[HR] */
2df4fe7a 644 HFLAGS_SPE = 6, /* from MSR_SPE if cpu has SPE; avoid overlap w/ MSR_VR */
2df4fe7a
RH		 645 HFLAGS_TM = 8, /* computed from MSR_TM */
646 HFLAGS_BE = 9, /* MSR_BE -- from elsewhere on embedded ppc */
647 HFLAGS_SE = 10, /* MSR_SE -- from elsewhere on embedded ppc */
648 HFLAGS_FP = 13, /* MSR_FP */
649 HFLAGS_PR = 14, /* MSR_PR */
f7460df2
DHB		 650 HFLAGS_PMCC0 = 15, /* MMCR0 PMCC bit 0 */
651 HFLAGS_PMCC1 = 16, /* MMCR0 PMCC bit 1 */
46d396bd 652 HFLAGS_INSN_CNT = 17, /* PMU instruction count enabled */
0e6bac3e 653 HFLAGS_VSX = 23, /* MSR_VSX if cpu has VSX */
2df4fe7a 654 HFLAGS_VR = 25, /* MSR_VR if cpu has VRE */
d764184d
RH		 655
656 HFLAGS_IMMU_IDX = 26, /* 26..28 -- the composite immu_idx */
657 HFLAGS_DMMU_IDX = 29, /* 29..31 -- the composite dmmu_idx */
2df4fe7a
RH		 658};
659
7c58044c
JM		 660/*****************************************************************************/
661/* Floating point status and control register */
a2735cf4
PC		 662#define FPSCR_DRN2 34 /* Decimal Floating-Point rounding control */
663#define FPSCR_DRN1 33 /* Decimal Floating-Point rounding control */
664#define FPSCR_DRN0 32 /* Decimal Floating-Point rounding control */
7c58044c
JM		 665#define FPSCR_FX 31 /* Floating-point exception summary */
666#define FPSCR_FEX 30 /* Floating-point enabled exception summary */
667#define FPSCR_VX 29 /* Floating-point invalid operation exception summ. */
668#define FPSCR_OX 28 /* Floating-point overflow exception */
669#define FPSCR_UX 27 /* Floating-point underflow exception */
670#define FPSCR_ZX 26 /* Floating-point zero divide exception */
671#define FPSCR_XX 25 /* Floating-point inexact exception */
672#define FPSCR_VXSNAN 24 /* Floating-point invalid operation exception (sNan) */
673#define FPSCR_VXISI 23 /* Floating-point invalid operation exception (inf) */
674#define FPSCR_VXIDI 22 /* Floating-point invalid operation exception (inf) */
675#define FPSCR_VXZDZ 21 /* Floating-point invalid operation exception (zero) */
676#define FPSCR_VXIMZ 20 /* Floating-point invalid operation exception (inf) */
677#define FPSCR_VXVC 19 /* Floating-point invalid operation exception (comp) */
678#define FPSCR_FR 18 /* Floating-point fraction rounded */
679#define FPSCR_FI 17 /* Floating-point fraction inexact */
680#define FPSCR_C 16 /* Floating-point result class descriptor */
681#define FPSCR_FL 15 /* Floating-point less than or negative */
682#define FPSCR_FG 14 /* Floating-point greater than or negative */
683#define FPSCR_FE 13 /* Floating-point equal or zero */
684#define FPSCR_FU 12 /* Floating-point unordered or NaN */
685#define FPSCR_FPCC 12 /* Floating-point condition code */
686#define FPSCR_FPRF 12 /* Floating-point result flags */
687#define FPSCR_VXSOFT 10 /* Floating-point invalid operation exception (soft) */
688#define FPSCR_VXSQRT 9 /* Floating-point invalid operation exception (sqrt) */
689#define FPSCR_VXCVI 8 /* Floating-point invalid operation exception (int) */
690#define FPSCR_VE 7 /* Floating-point invalid operation exception enable */
691#define FPSCR_OE 6 /* Floating-point overflow exception enable */
136fbf65 692#define FPSCR_UE 5 /* Floating-point underflow exception enable */
7c58044c
JM		 693#define FPSCR_ZE 4 /* Floating-point zero divide exception enable */
694#define FPSCR_XE 3 /* Floating-point inexact exception enable */
695#define FPSCR_NI 2 /* Floating-point non-IEEE mode */
696#define FPSCR_RN1 1
31eb7ddd 697#define FPSCR_RN0 0 /* Floating-point rounding control */
7c58044c 698/* Invalid operation exception summary */
fe43ba97
BL		 699#define FPSCR_IX ((1 << FPSCR_VXSNAN) | (1 << FPSCR_VXISI) | \
700 (1 << FPSCR_VXIDI) | (1 << FPSCR_VXZDZ) | \
701 (1 << FPSCR_VXIMZ) | (1 << FPSCR_VXVC) | \
702 (1 << FPSCR_VXSOFT) | (1 << FPSCR_VXSQRT) | \
703 (1 << FPSCR_VXCVI))
7c58044c 704
a2735cf4
PC		 705#define FP_DRN2 (1ull << FPSCR_DRN2)
706#define FP_DRN1 (1ull << FPSCR_DRN1)
707#define FP_DRN0 (1ull << FPSCR_DRN0)
708#define FP_DRN (FP_DRN2 | FP_DRN1 | FP_DRN0)
c647e3fe
DG		 709#define FP_FX (1ull << FPSCR_FX)
710#define FP_FEX (1ull << FPSCR_FEX)
711#define FP_VX (1ull << FPSCR_VX)
712#define FP_OX (1ull << FPSCR_OX)
713#define FP_UX (1ull << FPSCR_UX)
714#define FP_ZX (1ull << FPSCR_ZX)
715#define FP_XX (1ull << FPSCR_XX)
716#define FP_VXSNAN (1ull << FPSCR_VXSNAN)
717#define FP_VXISI (1ull << FPSCR_VXISI)
718#define FP_VXIDI (1ull << FPSCR_VXIDI)
719#define FP_VXZDZ (1ull << FPSCR_VXZDZ)
720#define FP_VXIMZ (1ull << FPSCR_VXIMZ)
721#define FP_VXVC (1ull << FPSCR_VXVC)
31eb7ddd 722#define FP_FR (1ull << FPSCR_FR)
c647e3fe
DG		 723#define FP_FI (1ull << FPSCR_FI)
724#define FP_C (1ull << FPSCR_C)
725#define FP_FL (1ull << FPSCR_FL)
726#define FP_FG (1ull << FPSCR_FG)
727#define FP_FE (1ull << FPSCR_FE)
728#define FP_FU (1ull << FPSCR_FU)
729#define FP_FPCC (FP_FL | FP_FG | FP_FE | FP_FU)
31eb7ddd 730#define FP_FPRF (FP_C | FP_FPCC)
c647e3fe
DG		 731#define FP_VXSOFT (1ull << FPSCR_VXSOFT)
732#define FP_VXSQRT (1ull << FPSCR_VXSQRT)
733#define FP_VXCVI (1ull << FPSCR_VXCVI)
734#define FP_VE (1ull << FPSCR_VE)
735#define FP_OE (1ull << FPSCR_OE)
736#define FP_UE (1ull << FPSCR_UE)
737#define FP_ZE (1ull << FPSCR_ZE)
738#define FP_XE (1ull << FPSCR_XE)
739#define FP_NI (1ull << FPSCR_NI)
740#define FP_RN1 (1ull << FPSCR_RN1)
31eb7ddd
PC		 741#define FP_RN0 (1ull << FPSCR_RN0)
742#define FP_RN (FP_RN1 | FP_RN0)
743
31eb7ddd
PC		 744#define FP_ENABLES (FP_VE | FP_OE | FP_UE | FP_ZE | FP_XE)
745#define FP_STATUS (FP_FR | FP_FI | FP_FPRF)
dbdc13a1 746
d1277156
JC		 747/* the exception bits which can be cleared by mcrfs - includes FX */
748#define FP_EX_CLEAR_BITS (FP_FX | FP_OX | FP_UX | FP_ZX | \
749 FP_XX | FP_VXSNAN | FP_VXISI | FP_VXIDI | \
750 FP_VXZDZ | FP_VXIMZ | FP_VXVC | FP_VXSOFT | \
751 FP_VXSQRT | FP_VXCVI)
752
25ee608d
LMC		 753/* FPSCR bits that can be set by mtfsf, mtfsfi and mtfsb1 */
754#define FPSCR_MTFS_MASK (~(MAKE_64BIT_MASK(36, 28) | PPC_BIT(28) | \
755 FP_FEX | FP_VX | PPC_BIT(52)))
756
7c58044c 757/*****************************************************************************/
6fa724a3 758/* Vector status and control register */
c647e3fe
DG		 759#define VSCR_NJ 16 /* Vector non-java */
760#define VSCR_SAT 0 /* Vector saturation */
6fa724a3 761
01662f3e
AG		 762/*****************************************************************************/
763/* BookE e500 MMU registers */
764
765#define MAS0_NV_SHIFT 0
766#define MAS0_NV_MASK (0xfff << MAS0_NV_SHIFT)
767
768#define MAS0_WQ_SHIFT 12
769#define MAS0_WQ_MASK (3 << MAS0_WQ_SHIFT)
770/* Write TLB entry regardless of reservation */
771#define MAS0_WQ_ALWAYS (0 << MAS0_WQ_SHIFT)
772/* Write TLB entry only already in use */
773#define MAS0_WQ_COND (1 << MAS0_WQ_SHIFT)
774/* Clear TLB entry */
775#define MAS0_WQ_CLR_RSRV (2 << MAS0_WQ_SHIFT)
776
777#define MAS0_HES_SHIFT 14
778#define MAS0_HES (1 << MAS0_HES_SHIFT)
779
780#define MAS0_ESEL_SHIFT 16
781#define MAS0_ESEL_MASK (0xfff << MAS0_ESEL_SHIFT)
782
783#define MAS0_TLBSEL_SHIFT 28
784#define MAS0_TLBSEL_MASK (3 << MAS0_TLBSEL_SHIFT)
785#define MAS0_TLBSEL_TLB0 (0 << MAS0_TLBSEL_SHIFT)
786#define MAS0_TLBSEL_TLB1 (1 << MAS0_TLBSEL_SHIFT)
787#define MAS0_TLBSEL_TLB2 (2 << MAS0_TLBSEL_SHIFT)
788#define MAS0_TLBSEL_TLB3 (3 << MAS0_TLBSEL_SHIFT)
789
790#define MAS0_ATSEL_SHIFT 31
791#define MAS0_ATSEL (1 << MAS0_ATSEL_SHIFT)
792#define MAS0_ATSEL_TLB 0
793#define MAS0_ATSEL_LRAT MAS0_ATSEL
794
2bd9543c
SW		 795#define MAS1_TSIZE_SHIFT 7
796#define MAS1_TSIZE_MASK (0x1f << MAS1_TSIZE_SHIFT)
01662f3e
AG		 797
798#define MAS1_TS_SHIFT 12
799#define MAS1_TS (1 << MAS1_TS_SHIFT)
800
801#define MAS1_IND_SHIFT 13
802#define MAS1_IND (1 << MAS1_IND_SHIFT)
803
804#define MAS1_TID_SHIFT 16
805#define MAS1_TID_MASK (0x3fff << MAS1_TID_SHIFT)
806
807#define MAS1_IPROT_SHIFT 30
808#define MAS1_IPROT (1 << MAS1_IPROT_SHIFT)
809
810#define MAS1_VALID_SHIFT 31
811#define MAS1_VALID 0x80000000
812
813#define MAS2_EPN_SHIFT 12
96091698 814#define MAS2_EPN_MASK (~0ULL << MAS2_EPN_SHIFT)
01662f3e
AG		 815
816#define MAS2_ACM_SHIFT 6
817#define MAS2_ACM (1 << MAS2_ACM_SHIFT)
818
819#define MAS2_VLE_SHIFT 5
820#define MAS2_VLE (1 << MAS2_VLE_SHIFT)
821
822#define MAS2_W_SHIFT 4
823#define MAS2_W (1 << MAS2_W_SHIFT)
824
825#define MAS2_I_SHIFT 3
826#define MAS2_I (1 << MAS2_I_SHIFT)
827
828#define MAS2_M_SHIFT 2
829#define MAS2_M (1 << MAS2_M_SHIFT)
830
831#define MAS2_G_SHIFT 1
832#define MAS2_G (1 << MAS2_G_SHIFT)
833
834#define MAS2_E_SHIFT 0
835#define MAS2_E (1 << MAS2_E_SHIFT)
836
837#define MAS3_RPN_SHIFT 12
838#define MAS3_RPN_MASK (0xfffff << MAS3_RPN_SHIFT)
839
840#define MAS3_U0 0x00000200
841#define MAS3_U1 0x00000100
842#define MAS3_U2 0x00000080
843#define MAS3_U3 0x00000040
844#define MAS3_UX 0x00000020
845#define MAS3_SX 0x00000010
846#define MAS3_UW 0x00000008
847#define MAS3_SW 0x00000004
848#define MAS3_UR 0x00000002
849#define MAS3_SR 0x00000001
850#define MAS3_SPSIZE_SHIFT 1
851#define MAS3_SPSIZE_MASK (0x3e << MAS3_SPSIZE_SHIFT)
852
853#define MAS4_TLBSELD_SHIFT MAS0_TLBSEL_SHIFT
854#define MAS4_TLBSELD_MASK MAS0_TLBSEL_MASK
855#define MAS4_TIDSELD_MASK 0x00030000
856#define MAS4_TIDSELD_PID0 0x00000000
857#define MAS4_TIDSELD_PID1 0x00010000
858#define MAS4_TIDSELD_PID2 0x00020000
859#define MAS4_TIDSELD_PIDZ 0x00030000
860#define MAS4_INDD 0x00008000 /* Default IND */
861#define MAS4_TSIZED_SHIFT MAS1_TSIZE_SHIFT
862#define MAS4_TSIZED_MASK MAS1_TSIZE_MASK
863#define MAS4_ACMD 0x00000040
864#define MAS4_VLED 0x00000020
865#define MAS4_WD 0x00000010
866#define MAS4_ID 0x00000008
867#define MAS4_MD 0x00000004
868#define MAS4_GD 0x00000002
869#define MAS4_ED 0x00000001
870#define MAS4_WIMGED_MASK 0x0000001f /* Default WIMGE */
871#define MAS4_WIMGED_SHIFT 0
872
873#define MAS5_SGS 0x80000000
874#define MAS5_SLPID_MASK 0x00000fff
875
876#define MAS6_SPID0 0x3fff0000
877#define MAS6_SPID1 0x00007ffe
878#define MAS6_ISIZE(x) MAS1_TSIZE(x)
879#define MAS6_SAS 0x00000001
880#define MAS6_SPID MAS6_SPID0
881#define MAS6_SIND 0x00000002 /* Indirect page */
882#define MAS6_SIND_SHIFT 1
883#define MAS6_SPID_MASK 0x3fff0000
884#define MAS6_SPID_SHIFT 16
885#define MAS6_ISIZE_MASK 0x00000f80
886#define MAS6_ISIZE_SHIFT 7
887
888#define MAS7_RPN 0xffffffff
889
890#define MAS8_TGS 0x80000000
891#define MAS8_VF 0x40000000
892#define MAS8_TLBPID 0x00000fff
893
894/* Bit definitions for MMUCFG */
895#define MMUCFG_MAVN 0x00000003 /* MMU Architecture Version Number */
896#define MMUCFG_MAVN_V1 0x00000000 /* v1.0 */
897#define MMUCFG_MAVN_V2 0x00000001 /* v2.0 */
898#define MMUCFG_NTLBS 0x0000000c /* Number of TLBs */
899#define MMUCFG_PIDSIZE 0x000007c0 /* PID Reg Size */
900#define MMUCFG_TWC 0x00008000 /* TLB Write Conditional (v2.0) */
901#define MMUCFG_LRAT 0x00010000 /* LRAT Supported (v2.0) */
902#define MMUCFG_RASIZE 0x00fe0000 /* Real Addr Size */
903#define MMUCFG_LPIDSIZE 0x0f000000 /* LPID Reg Size */
904
905/* Bit definitions for MMUCSR0 */
906#define MMUCSR0_TLB1FI 0x00000002 /* TLB1 Flash invalidate */
907#define MMUCSR0_TLB0FI 0x00000004 /* TLB0 Flash invalidate */
908#define MMUCSR0_TLB2FI 0x00000040 /* TLB2 Flash invalidate */
909#define MMUCSR0_TLB3FI 0x00000020 /* TLB3 Flash invalidate */
910#define MMUCSR0_TLBFI (MMUCSR0_TLB0FI | MMUCSR0_TLB1FI | \
911 MMUCSR0_TLB2FI | MMUCSR0_TLB3FI)
912#define MMUCSR0_TLB0PS 0x00000780 /* TLB0 Page Size */
913#define MMUCSR0_TLB1PS 0x00007800 /* TLB1 Page Size */
914#define MMUCSR0_TLB2PS 0x00078000 /* TLB2 Page Size */
915#define MMUCSR0_TLB3PS 0x00780000 /* TLB3 Page Size */
916
917/* TLBnCFG encoding */
918#define TLBnCFG_N_ENTRY 0x00000fff /* number of entries */
919#define TLBnCFG_HES 0x00002000 /* HW select supported */
920#define TLBnCFG_AVAIL 0x00004000 /* variable page size */
921#define TLBnCFG_IPROT 0x00008000 /* IPROT supported */
922#define TLBnCFG_GTWE 0x00010000 /* Guest can write */
923#define TLBnCFG_IND 0x00020000 /* IND entries supported */
924#define TLBnCFG_PT 0x00040000 /* Can load from page table */
925#define TLBnCFG_MINSIZE 0x00f00000 /* Minimum Page Size (v1.0) */
926#define TLBnCFG_MINSIZE_SHIFT 20
927#define TLBnCFG_MAXSIZE 0x000f0000 /* Maximum Page Size (v1.0) */
928#define TLBnCFG_MAXSIZE_SHIFT 16
929#define TLBnCFG_ASSOC 0xff000000 /* Associativity */
930#define TLBnCFG_ASSOC_SHIFT 24
931
932/* TLBnPS encoding */
933#define TLBnPS_4K 0x00000004
934#define TLBnPS_8K 0x00000008
935#define TLBnPS_16K 0x00000010
936#define TLBnPS_32K 0x00000020
937#define TLBnPS_64K 0x00000040
938#define TLBnPS_128K 0x00000080
939#define TLBnPS_256K 0x00000100
940#define TLBnPS_512K 0x00000200
941#define TLBnPS_1M 0x00000400
942#define TLBnPS_2M 0x00000800
943#define TLBnPS_4M 0x00001000
944#define TLBnPS_8M 0x00002000
945#define TLBnPS_16M 0x00004000
946#define TLBnPS_32M 0x00008000
947#define TLBnPS_64M 0x00010000
948#define TLBnPS_128M 0x00020000
949#define TLBnPS_256M 0x00040000
950#define TLBnPS_512M 0x00080000
951#define TLBnPS_1G 0x00100000
952#define TLBnPS_2G 0x00200000
953#define TLBnPS_4G 0x00400000
954#define TLBnPS_8G 0x00800000
955#define TLBnPS_16G 0x01000000
956#define TLBnPS_32G 0x02000000
957#define TLBnPS_64G 0x04000000
958#define TLBnPS_128G 0x08000000
959#define TLBnPS_256G 0x10000000
960
961/* tlbilx action encoding */
962#define TLBILX_T_ALL 0
963#define TLBILX_T_TID 1
964#define TLBILX_T_FULLMATCH 3
965#define TLBILX_T_CLASS0 4
966#define TLBILX_T_CLASS1 5
967#define TLBILX_T_CLASS2 6
968#define TLBILX_T_CLASS3 7
969
970/* BookE 2.06 helper defines */
971
972#define BOOKE206_FLUSH_TLB0 (1 << 0)
973#define BOOKE206_FLUSH_TLB1 (1 << 1)
974#define BOOKE206_FLUSH_TLB2 (1 << 2)
975#define BOOKE206_FLUSH_TLB3 (1 << 3)
976
977/* number of possible TLBs */
978#define BOOKE206_MAX_TLBN 4
979
50728199
RK		 980#define EPID_EPID_SHIFT 0x0
981#define EPID_EPID 0xFF
982#define EPID_ELPID_SHIFT 0x10
983#define EPID_ELPID 0x3F0000
984#define EPID_EGS 0x20000000
985#define EPID_EGS_SHIFT 29
986#define EPID_EAS 0x40000000
987#define EPID_EAS_SHIFT 30
988#define EPID_EPR 0x80000000
989#define EPID_EPR_SHIFT 31
990/* We don't support EGS and ELPID */
991#define EPID_MASK (EPID_EPID | EPID_EAS | EPID_EPR)
992
58e00a24 993/*****************************************************************************/
7af1e7b0 994/* Server and Embedded Processor Control */
58e00a24
AG		 995
996#define DBELL_TYPE_SHIFT 27
997#define DBELL_TYPE_MASK (0x1f << DBELL_TYPE_SHIFT)
998#define DBELL_TYPE_DBELL (0x00 << DBELL_TYPE_SHIFT)
999#define DBELL_TYPE_DBELL_CRIT (0x01 << DBELL_TYPE_SHIFT)
1000#define DBELL_TYPE_G_DBELL (0x02 << DBELL_TYPE_SHIFT)
1001#define DBELL_TYPE_G_DBELL_CRIT (0x03 << DBELL_TYPE_SHIFT)
1002#define DBELL_TYPE_G_DBELL_MC (0x04 << DBELL_TYPE_SHIFT)
1003
7af1e7b0
CLG		 1004#define DBELL_TYPE_DBELL_SERVER (0x05 << DBELL_TYPE_SHIFT)
1005
1006#define DBELL_BRDCAST PPC_BIT(37)
58e00a24
AG		 1007#define DBELL_LPIDTAG_SHIFT 14
1008#define DBELL_LPIDTAG_MASK (0xfff << DBELL_LPIDTAG_SHIFT)
1009#define DBELL_PIRTAG_MASK 0x3fff
1010
7af1e7b0
CLG		 1011#define DBELL_PROCIDTAG_MASK PPC_BITMASK(44, 63)
1012
4656e1f0
BH		 1013#define PPC_PAGE_SIZES_MAX_SZ 8
1014
c64abd1f
SB		 1015struct ppc_radix_page_info {
1016 uint32_t count;
1017 uint32_t entries[PPC_PAGE_SIZES_MAX_SZ];
1018};
4656e1f0 1019
6fa724a3 1020/*****************************************************************************/
7c58044c 1021/* The whole PowerPC CPU context */
50728199 1022
c647e3fe
DG		 1023/*
1024 * PowerPC needs eight modes for different hypervisor/supervisor/guest
1025 * + real/paged mode combinations. The other two modes are for
1026 * external PID load/store.
50728199 1027 */
50728199
RK		 1028#define PPC_TLB_EPID_LOAD 8
1029#define PPC_TLB_EPID_STORE 9
6ebbf390 1030
54ff58bb
BR		 1031#define PPC_CPU_OPCODES_LEN 0x40
1032#define PPC_CPU_INDIRECT_OPCODES_LEN 0x20
b048960f 1033
1ea4a06a 1034struct CPUArchState {
ad5db2e7
BZ		 1035 /* Most commonly used resources during translated code execution first */
1036 target_ulong gpr[32]; /* general purpose registers */
1037 target_ulong gprh[32]; /* storage for GPR MSB, used by the SPE extension */
3fc6c082 1038 target_ulong lr;
3fc6c082 1039 target_ulong ctr;
ad5db2e7 1040 uint32_t crf[8]; /* condition register */
697ab892 1041#if defined(TARGET_PPC64)
697ab892
DG		 1042 target_ulong cfar;
1043#endif
ad5db2e7 1044 target_ulong xer; /* XER (with SO, OV, CA split out) */
da91a00f
RH		 1045 target_ulong so;
1046 target_ulong ov;
1047 target_ulong ca;
dd09c361
ND		 1048 target_ulong ov32;
1049 target_ulong ca32;
3fc6c082 1050
ad5db2e7
BZ		 1051 target_ulong reserve_addr; /* Reservation address */
1052 target_ulong reserve_val; /* Reservation value */
1053 target_ulong reserve_val2;
3fc6c082 1054
ad5db2e7
BZ		 1055 /* These are used in supervisor mode only */
1056 target_ulong msr; /* machine state register */
1057 target_ulong tgpr[4]; /* temporary general purpose registers, */
1058 /* used to speed-up TLB assist handlers */
a316d335 1059
ad5db2e7
BZ		 1060 target_ulong nip; /* next instruction pointer */
1061 uint64_t retxh; /* high part of 128-bit helper return */
94bf2658 1062
c647e3fe
DG		 1063 /* when a memory exception occurs, the access type is stored here */
1064 int access_type;
a541f297 1065
f2e63a42 1066#if !defined(CONFIG_USER_ONLY)
ad5db2e7 1067 /* MMU context, only relevant for full system emulation */
f2e63a42 1068#if defined(TARGET_PPC64)
ad5db2e7 1069 ppc_slb_t slb[MAX_SLB_ENTRIES]; /* PowerPC 64 SLB area */
f2e63a42 1070#endif
ad5db2e7
BZ		 1071 target_ulong sr[32]; /* segment registers */
1072 uint32_t nb_BATs; /* number of BATs */
3fc6c082
FB		 1073 target_ulong DBAT[2][8];
1074 target_ulong IBAT[2][8];
01662f3e 1075 /* PowerPC TLB registers (for 4xx, e500 and 60x software driven TLBs) */
ad5db2e7 1076 int32_t nb_tlb; /* Total number of TLB */
f2e63a42 1077 int tlb_per_way; /* Speed-up helper: used to avoid divisions at run time */
ad5db2e7
BZ		 1078 int nb_ways; /* Number of ways in the TLB set */
1079 int last_way; /* Last used way used to allocate TLB in a LRU way */
f2e63a42 1080 int id_tlbs; /* If 1, MMU has separated TLBs for instructions & data */
ad5db2e7
BZ		 1081 int nb_pids; /* Number of available PID registers */
1082 int tlb_type; /* Type of TLB we're dealing with */
1083 ppc_tlb_t tlb; /* TLB is optional. Allocate them only if needed */
ad5db2e7
BZ		 1084 bool tlb_dirty; /* Set to non-zero when modifying TLB */
1085 bool kvm_sw_tlb; /* non-zero if KVM SW TLB API is active */
c5a8d8f3 1086 uint32_t tlb_need_flush; /* Delayed flush needed */
a8a6d53e 1087#define TLB_NEED_LOCAL_FLUSH 0x1
d76ab5e1 1088#define TLB_NEED_GLOBAL_FLUSH 0x2
f2e63a42 1089#endif
9fddaa0c 1090
3fc6c082 1091 /* Other registers */
ad5db2e7 1092 target_ulong spr[1024]; /* special purpose registers */
c227f099 1093 ppc_spr_t spr_cb[1024];
6e8b9903
RH		 1094 /* Composite status for PMC[1-6] enabled and counting insns or cycles. */
1095 uint8_t pmc_ins_cnt;
1096 uint8_t pmc_cyc_cnt;
ad5db2e7 1097 /* Vector status and control register, minus VSCR_SAT */
3fc6c082 1098 uint32_t vscr;
ef96e3ae
MCA		 1099 /* VSX registers (including FP and AVR) */
1100 ppc_vsr_t vsr[64] QEMU_ALIGNED(16);
ad5db2e7 1101 /* Non-zero if and only if VSCR_SAT should be set */
9b5b74da 1102 ppc_vsr_t vscr_sat QEMU_ALIGNED(16);
d9bce9d9 1103 /* SPE registers */
2231ef10 1104 uint64_t spe_acc;
d9bce9d9 1105 uint32_t spe_fscr;
ad5db2e7 1106 /* SPE and Altivec share status as they'll never be used simultaneously */
fbd265b6 1107 float_status vec_status;
ad5db2e7
BZ		 1108 float_status fp_status; /* Floating point execution context */
1109 target_ulong fpscr; /* Floating point status and control register */
3fc6c082
FB		 1110
1111 /* Internal devices resources */
ad5db2e7
BZ		 1112 ppc_tb_t *tb_env; /* Time base and decrementer */
1113 ppc_dcr_t *dcr_env; /* Device control registers */
3fc6c082 1114
d63001d1
JM		 1115 int dcache_line_size;
1116 int icache_line_size;
1117
ad5db2e7 1118 /* These resources are used during exception processing */
3fc6c082 1119 /* CPU model definition */
a750fc0b 1120 target_ulong msr_mask;
c227f099
AL		 1121 powerpc_mmu_t mmu_model;
1122 powerpc_excp_t excp_model;
1123 powerpc_input_t bus_model;
237c0af0 1124 int bfd_mach;
3fc6c082 1125 uint32_t flags;
c29b735c 1126 uint64_t insns_flags;
a5858d7a 1127 uint64_t insns_flags2;
3fc6c082 1128
3fc6c082 1129 int error_code;
47103572 1130 uint32_t pending_interrupts;
e9df014c 1131#if !defined(CONFIG_USER_ONLY)
c647e3fe 1132 /*
ad5db2e7
BZ		 1133 * This is the IRQ controller, which is implementation dependent and only
1134 * relevant when emulating a complete machine. Note that this isn't used
1135 * by recent Book3s compatible CPUs (POWER7 and newer).
e9df014c
JM		 1136 */
1137 uint32_t irq_input_state;
1138 void **irq_inputs;
ad5db2e7
BZ		 1139
1140 target_ulong excp_vectors[POWERPC_EXCP_NB]; /* Exception vectors */
e1833e1f
JM		 1141 target_ulong excp_prefix;
1142 target_ulong ivor_mask;
1143 target_ulong ivpr_mask;
d63001d1 1144 target_ulong hreset_vector;
68c2dd70 1145 hwaddr mpic_iack;
ad5db2e7
BZ		 1146 bool mpic_proxy; /* true if the external proxy facility mode is enabled */
1147 bool has_hv_mode; /* set when the processor has an HV mode, thus HV priv */
1148 /* instructions and SPRs are diallowed if MSR:HV is 0 */
21c0d66a 1149 /*
ad5db2e7
BZ		 1150 * On P7/P8/P9, set when in PM state so we need to handle resume in a
1151 * special way (such as routing some resume causes to 0x100, i.e. sreset).
7778a575 1152 */
1e7fd61d 1153 bool resume_as_sreset;
e9df014c 1154#endif
3fc6c082 1155
26c55599
RH		 1156 /* These resources are used only in TCG */
1157 uint32_t hflags;
f7a7b652 1158 target_ulong hflags_compat_nmsr; /* for migration compatibility */
3fc6c082 1159
9fddaa0c 1160 /* Power management */
cd346349 1161 int (*check_pow)(CPUPPCState *env);
a541f297 1162
2c50e26e 1163#if !defined(CONFIG_USER_ONLY)
ad5db2e7 1164 void *load_info; /* holds boot loading state */
2c50e26e 1165#endif
ddd1055b
FC		 1166
1167 /* booke timers */
1168
c647e3fe 1169 /*
ad5db2e7
BZ		 1170 * Specifies bit locations of the Time Base used to signal a fixed timer
1171 * exception on a transition from 0 to 1 (watchdog or fixed-interval timer)
ddd1055b 1172 *
ad5db2e7 1173 * 0 selects the least significant bit, 63 selects the most significant bit
ddd1055b
FC		 1174 */
1175 uint8_t fit_period[4];
1176 uint8_t wdt_period[4];
80b3f79b
AK		 1177
1178 /* Transactional memory state */
1179 target_ulong tm_gpr[32];
1180 ppc_avr_t tm_vsr[64];
1181 uint64_t tm_cr;
1182 uint64_t tm_lr;
1183 uint64_t tm_ctr;
1184 uint64_t tm_fpscr;
1185 uint64_t tm_amr;
1186 uint64_t tm_ppr;
1187 uint64_t tm_vrsave;
1188 uint32_t tm_vscr;
1189 uint64_t tm_dscr;
1190 uint64_t tm_tar;
8f2e9d40
DHB		 1191
1192 /*
1193 * Timers used to fire performance monitor alerts
1194 * when counting cycles.
1195 */
1196 QEMUTimer *pmu_cyc_overflow_timers[PMU_COUNTERS_NUM];
c2eff582
DHB		 1197
1198 /*
1199 * PMU base time value used by the PMU to calculate
1200 * running cycles.
1201 */
1202 uint64_t pmu_base_time;
3fc6c082 1203};
79aceca5 1204
ddd1055b
FC		 1205#define SET_FIT_PERIOD(a_, b_, c_, d_) \
1206do { \
1207 env->fit_period[0] = (a_); \
1208 env->fit_period[1] = (b_); \
1209 env->fit_period[2] = (c_); \
1210 env->fit_period[3] = (d_); \
1211 } while (0)
1212
1213#define SET_WDT_PERIOD(a_, b_, c_, d_) \
1214do { \
1215 env->wdt_period[0] = (a_); \
1216 env->wdt_period[1] = (b_); \
1217 env->wdt_period[2] = (c_); \
1218 env->wdt_period[3] = (d_); \
1219 } while (0)
1220
1d1be34d
DG		 1221typedef struct PPCVirtualHypervisor PPCVirtualHypervisor;
1222typedef struct PPCVirtualHypervisorClass PPCVirtualHypervisorClass;
0d8d6a24 1223
2d34fe39
PB		 1224/**
1225 * PowerPCCPU:
1226 * @env: #CPUPPCState
81210c20 1227 * @vcpu_id: vCPU identifier given to KVM
d6e166c0 1228 * @compat_pvr: Current logical PVR, zero if in "raw" mode
2d34fe39
PB		 1229 *
1230 * A PowerPC CPU.
1231 */
b36e239e 1232struct ArchCPU {
2d34fe39
PB		 1233 /*< private >*/
1234 CPUState parent_obj;
1235 /*< public >*/
1236
5b146dc7 1237 CPUNegativeOffsetState neg;
2d34fe39 1238 CPUPPCState env;
5b146dc7 1239
81210c20 1240 int vcpu_id;
d6e166c0 1241 uint32_t compat_pvr;
1d1be34d 1242 PPCVirtualHypervisor *vhyp;
7388efaf 1243 void *machine_data;
15f8b142 1244 int32_t node_id; /* NUMA node this CPU belongs to */
b07c59f7 1245 PPCHash64Options *hash64_opts;
16a2497b 1246
28876bf2
AB		 1247 /* Those resources are used only during code translation */
1248 /* opcode handlers */
1249 opc_handler_t *opcodes[PPC_CPU_OPCODES_LEN];
1250
146c11f1
DG		 1251 /* Fields related to migration compatibility hacks */
1252 bool pre_2_8_migration;
16a2497b
DG		 1253 target_ulong mig_msr_mask;
1254 uint64_t mig_insns_flags;
1255 uint64_t mig_insns_flags2;
1256 uint32_t mig_nb_BATs;
d5fc133e 1257 bool pre_2_10_migration;
d8c0c7af 1258 bool pre_3_0_migration;
67d7d66f 1259 int32_t mig_slb_nr;
2d34fe39
PB		 1260};
1261
2d34fe39
PB		 1262
1263PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr);
1264PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr);
e9edd931 1265PowerPCCPUClass *ppc_cpu_get_family_class(PowerPCCPUClass *pcc);
2d34fe39 1266
e89aac1a 1267#ifndef CONFIG_USER_ONLY
1d1be34d
DG		 1268struct PPCVirtualHypervisorClass {
1269 InterfaceClass parent;
7cebc5db
NP		 1270 bool (*cpu_in_nested)(PowerPCCPU *cpu);
1271 void (*deliver_hv_excp)(PowerPCCPU *cpu, int excp);
1d1be34d 1272 void (*hypercall)(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu);
e57ca75c
DG		 1273 hwaddr (*hpt_mask)(PPCVirtualHypervisor *vhyp);
1274 const ppc_hash_pte64_t *(*map_hptes)(PPCVirtualHypervisor *vhyp,
1275 hwaddr ptex, int n);
1276 void (*unmap_hptes)(PPCVirtualHypervisor *vhyp,
1277 const ppc_hash_pte64_t *hptes,
1278 hwaddr ptex, int n);
a2dd4e83
BH		 1279 void (*hpte_set_c)(PPCVirtualHypervisor *vhyp, hwaddr ptex, uint64_t pte1);
1280 void (*hpte_set_r)(PPCVirtualHypervisor *vhyp, hwaddr ptex, uint64_t pte1);
f32d4ab4
NP		 1281 bool (*get_pate)(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu,
1282 target_ulong lpid, ppc_v3_pate_t *entry);
1ec26c75 1283 target_ulong (*encode_hpt_for_kvm_pr)(PPCVirtualHypervisor *vhyp);
03ef074c
NP		 1284 void (*cpu_exec_enter)(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu);
1285 void (*cpu_exec_exit)(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu);
1d1be34d
DG		 1286};
1287
1288#define TYPE_PPC_VIRTUAL_HYPERVISOR "ppc-virtual-hypervisor"
8110fa1d
EH		 1289DECLARE_OBJ_CHECKERS(PPCVirtualHypervisor, PPCVirtualHypervisorClass,
1290 PPC_VIRTUAL_HYPERVISOR, TYPE_PPC_VIRTUAL_HYPERVISOR)
7cebc5db
NP		 1291
1292static inline bool vhyp_cpu_in_nested(PowerPCCPU *cpu)
1293{
1294 return PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp)->cpu_in_nested(cpu);
1295}
e89aac1a 1296#endif /* CONFIG_USER_ONLY */
1d1be34d 1297
90c84c56 1298void ppc_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
2d34fe39 1299hwaddr ppc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
a010bdbe
AB		 1300int ppc_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
1301int ppc_cpu_gdb_read_register_apple(CPUState *cpu, GByteArray *buf, int reg);
2d34fe39
PB		 1302int ppc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
1303int ppc_cpu_gdb_write_register_apple(CPUState *cpu, uint8_t *buf, int reg);
707c7c2e
FR		 1304#ifndef CONFIG_USER_ONLY
1305void ppc_gdb_gen_spr_xml(PowerPCCPU *cpu);
1306const char *ppc_gdb_get_dynamic_xml(CPUState *cs, const char *xml_name);
1307#endif
2d34fe39
PB		 1308int ppc64_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
1309 int cpuid, void *opaque);
356bb70e
MN		 1310int ppc32_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
1311 int cpuid, void *opaque);
2d34fe39 1312#ifndef CONFIG_USER_ONLY
f725245c
PMD		 1313void ppc_cpu_do_interrupt(CPUState *cpu);
1314bool ppc_cpu_exec_interrupt(CPUState *cpu, int int_req);
b5b7f391 1315void ppc_cpu_do_system_reset(CPUState *cs);
ad77c6ca 1316void ppc_cpu_do_fwnmi_machine_check(CPUState *cs, target_ulong vector);
8a9358cc 1317extern const VMStateDescription vmstate_ppc_cpu;
2d34fe39 1318#endif
1d0cb67d 1319
3fc6c082 1320/*****************************************************************************/
2e70f6ef 1321void ppc_translate_init(void);
a541f297 1322
76a66253 1323#if !defined(CONFIG_USER_ONLY)
c647e3fe 1324void ppc_store_sdr1(CPUPPCState *env, target_ulong value);
12de9a39 1325#endif /* !defined(CONFIG_USER_ONLY) */
c647e3fe 1326void ppc_store_msr(CPUPPCState *env, target_ulong value);
45998ffc 1327void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val);
3fc6c082 1328
0442428a 1329void ppc_cpu_list(void);
aaed909a 1330
9fddaa0c
FB		 1331/* Time-base and decrementer management */
1332#ifndef NO_CPU_IO_DEFS
c647e3fe
DG		 1333uint64_t cpu_ppc_load_tbl(CPUPPCState *env);
1334uint32_t cpu_ppc_load_tbu(CPUPPCState *env);
1335void cpu_ppc_store_tbu(CPUPPCState *env, uint32_t value);
1336void cpu_ppc_store_tbl(CPUPPCState *env, uint32_t value);
1337uint64_t cpu_ppc_load_atbl(CPUPPCState *env);
1338uint32_t cpu_ppc_load_atbu(CPUPPCState *env);
1339void cpu_ppc_store_atbl(CPUPPCState *env, uint32_t value);
1340void cpu_ppc_store_atbu(CPUPPCState *env, uint32_t value);
5d62725b
SJS		 1341uint64_t cpu_ppc_load_vtb(CPUPPCState *env);
1342void cpu_ppc_store_vtb(CPUPPCState *env, uint64_t value);
e81a982a 1343bool ppc_decr_clear_on_delivery(CPUPPCState *env);
a8dafa52
SJS		 1344target_ulong cpu_ppc_load_decr(CPUPPCState *env);
1345void cpu_ppc_store_decr(CPUPPCState *env, target_ulong value);
1346target_ulong cpu_ppc_load_hdecr(CPUPPCState *env);
1347void cpu_ppc_store_hdecr(CPUPPCState *env, target_ulong value);
f0ec31b1 1348void cpu_ppc_store_tbu40(CPUPPCState *env, uint64_t value);
c647e3fe 1349uint64_t cpu_ppc_load_purr(CPUPPCState *env);
5cc7e69f 1350void cpu_ppc_store_purr(CPUPPCState *env, uint64_t value);
d9bce9d9 1351#if !defined(CONFIG_USER_ONLY)
c647e3fe
DG		 1352target_ulong load_40x_pit(CPUPPCState *env);
1353void store_40x_pit(CPUPPCState *env, target_ulong val);
1354void store_40x_dbcr0(CPUPPCState *env, uint32_t val);
1355void store_40x_sler(CPUPPCState *env, uint32_t val);
cbd8f17d
CLG		 1356void store_40x_tcr(CPUPPCState *env, target_ulong val);
1357void store_40x_tsr(CPUPPCState *env, target_ulong val);
c647e3fe
DG		 1358void store_booke_tcr(CPUPPCState *env, target_ulong val);
1359void store_booke_tsr(CPUPPCState *env, target_ulong val);
1360void ppc_tlb_invalidate_all(CPUPPCState *env);
1361void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr);
da20aed1 1362void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp);
5118ebe8
LMC		 1363int ppcmas_tlb_check(CPUPPCState *env, ppcmas_tlb_t *tlb,
1364 hwaddr *raddrp, target_ulong address,
1365 uint32_t pid);
1366int ppcemb_tlb_check(CPUPPCState *env, ppcemb_tlb_t *tlb,
1367 hwaddr *raddrp,
1368 target_ulong address, uint32_t pid, int ext,
1369 int i);
1370hwaddr booke206_tlb_to_page_size(CPUPPCState *env,
1371 ppcmas_tlb_t *tlb);
d9bce9d9 1372#endif
9fddaa0c 1373#endif
79aceca5 1374
fe43ba97 1375void ppc_store_fpscr(CPUPPCState *env, target_ulong val);
493028d8
CLG		 1376void helper_hfscr_facility_check(CPUPPCState *env, uint32_t bit,
1377 const char *caller, uint32_t cause);
d6478bc7 1378
636aa200 1379static inline uint64_t ppc_dump_gpr(CPUPPCState *env, int gprn)
6b542af7
JM		 1380{
1381 uint64_t gprv;
1382
1383 gprv = env->gpr[gprn];
6b542af7 1384 if (env->flags & POWERPC_FLAG_SPE) {
c647e3fe
DG		 1385 /*
1386 * If the CPU implements the SPE extension, we have to get the
6b542af7
JM		 1387 * high bits of the GPR from the gprh storage area
1388 */
1389 gprv &= 0xFFFFFFFFULL;
1390 gprv |= (uint64_t)env->gprh[gprn] << 32;
1391 }
6b542af7
JM		 1392
1393 return gprv;
1394}
1395
2e719ba3 1396/* Device control registers */
c647e3fe
DG		 1397int ppc_dcr_read(ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp);
1398int ppc_dcr_write(ppc_dcr_t *dcr_env, int dcrn, uint32_t val);
2e719ba3 1399
c9137065
IM		 1400#define POWERPC_CPU_TYPE_SUFFIX "-" TYPE_POWERPC_CPU
1401#define POWERPC_CPU_TYPE_NAME(model) model POWERPC_CPU_TYPE_SUFFIX
0dacec87 1402#define CPU_RESOLVING_TYPE TYPE_POWERPC_CPU
c9137065 1403
c732abe2 1404#define cpu_list ppc_cpu_list
9467d44c 1405
6ebbf390 1406/* MMU modes definitions */
6ebbf390 1407#define MMU_USER_IDX 0
c647e3fe 1408static inline int cpu_mmu_index(CPUPPCState *env, bool ifetch)
6ebbf390 1409{
d764184d
RH		 1410#ifdef CONFIG_USER_ONLY
1411 return MMU_USER_IDX;
1412#else
1413 return (env->hflags >> (ifetch ? HFLAGS_IMMU_IDX : HFLAGS_DMMU_IDX)) & 7;
1414#endif
6ebbf390
JM		 1415}
1416
9d6f1065
DG		 1417/* Compatibility modes */
1418#if defined(TARGET_PPC64)
9d2179d6
DG		 1419bool ppc_check_compat(PowerPCCPU *cpu, uint32_t compat_pvr,
1420 uint32_t min_compat_pvr, uint32_t max_compat_pvr);
ad99d04c
DG		 1421bool ppc_type_check_compat(const char *cputype, uint32_t compat_pvr,
1422 uint32_t min_compat_pvr, uint32_t max_compat_pvr);
1423
2c82e8df 1424int ppc_set_compat(PowerPCCPU *cpu, uint32_t compat_pvr, Error **errp);
ad99d04c 1425
f6f242c7 1426#if !defined(CONFIG_USER_ONLY)
2c82e8df 1427int ppc_set_compat_all(uint32_t compat_pvr, Error **errp);
f6f242c7 1428#endif
abbc1247 1429int ppc_compat_max_vthreads(PowerPCCPU *cpu);
7843c0d6 1430void ppc_compat_add_property(Object *obj, const char *name,
40c2281c 1431 uint32_t *compat_pvr, const char *basedesc);
9d6f1065
DG		 1432#endif /* defined(TARGET_PPC64) */
1433
022c62cb 1434#include "exec/cpu-all.h"
79aceca5 1435
3fc6c082 1436/*****************************************************************************/
e1571908 1437/* CRF definitions */
efa73196
ND		 1438#define CRF_LT_BIT 3
1439#define CRF_GT_BIT 2
1440#define CRF_EQ_BIT 1
1441#define CRF_SO_BIT 0
1442#define CRF_LT (1 << CRF_LT_BIT)
1443#define CRF_GT (1 << CRF_GT_BIT)
1444#define CRF_EQ (1 << CRF_EQ_BIT)
1445#define CRF_SO (1 << CRF_SO_BIT)
1446/* For SPE extensions */
1447#define CRF_CH (1 << CRF_LT_BIT)
1448#define CRF_CL (1 << CRF_GT_BIT)
1449#define CRF_CH_OR_CL (1 << CRF_EQ_BIT)
1450#define CRF_CH_AND_CL (1 << CRF_SO_BIT)
e1571908
AJ		 1451
1452/* XER definitions */
3d7b417e
AJ		 1453#define XER_SO 31
1454#define XER_OV 30
1455#define XER_CA 29
dd09c361
ND		 1456#define XER_OV32 19
1457#define XER_CA32 18
3d7b417e
AJ		 1458#define XER_CMP 8
1459#define XER_BC 0
da91a00f
RH		 1460#define xer_so (env->so)
1461#define xer_ov (env->ov)
1462#define xer_ca (env->ca)
dd09c361
ND		 1463#define xer_ov32 (env->ov)
1464#define xer_ca32 (env->ca)
3d7b417e
AJ		 1465#define xer_cmp ((env->xer >> XER_CMP) & 0xFF)
1466#define xer_bc ((env->xer >> XER_BC) & 0x7F)
79aceca5 1467
3fc6c082 1468/* SPR definitions */
80d11f44
JM		 1469#define SPR_MQ (0x000)
1470#define SPR_XER (0x001)
80d11f44
JM		 1471#define SPR_LR (0x008)
1472#define SPR_CTR (0x009)
f244115c 1473#define SPR_UAMR (0x00D)
697ab892 1474#define SPR_DSCR (0x011)
80d11f44 1475#define SPR_DSISR (0x012)
005b69fd 1476#define SPR_DAR (0x013)
80d11f44
JM		 1477#define SPR_DECR (0x016)
1478#define SPR_SDR1 (0x019)
1479#define SPR_SRR0 (0x01A)
1480#define SPR_SRR1 (0x01B)
697ab892 1481#define SPR_CFAR (0x01C)
80d11f44 1482#define SPR_AMR (0x01D)
9c1cf38d 1483#define SPR_ACOP (0x01F)
80d11f44 1484#define SPR_BOOKE_PID (0x030)
9c1cf38d 1485#define SPR_BOOKS_PID (0x030)
80d11f44
JM		 1486#define SPR_BOOKE_DECAR (0x036)
1487#define SPR_BOOKE_CSRR0 (0x03A)
1488#define SPR_BOOKE_CSRR1 (0x03B)
1489#define SPR_BOOKE_DEAR (0x03D)
a6eabb9e 1490#define SPR_IAMR (0x03D)
80d11f44
JM		 1491#define SPR_BOOKE_ESR (0x03E)
1492#define SPR_BOOKE_IVPR (0x03F)
1493#define SPR_MPC_EIE (0x050)
1494#define SPR_MPC_EID (0x051)
1495#define SPR_MPC_NRI (0x052)
cdcdda27
AK		 1496#define SPR_TFHAR (0x080)
1497#define SPR_TFIAR (0x081)
1498#define SPR_TEXASR (0x082)
1499#define SPR_TEXASRU (0x083)
0bfe9299 1500#define SPR_UCTRL (0x088)
650f3287 1501#define SPR_TIDR (0x090)
80d11f44
JM		 1502#define SPR_MPC_CMPA (0x090)
1503#define SPR_MPC_CMPB (0x091)
1504#define SPR_MPC_CMPC (0x092)
1505#define SPR_MPC_CMPD (0x093)
1506#define SPR_MPC_ECR (0x094)
1507#define SPR_MPC_DER (0x095)
1508#define SPR_MPC_COUNTA (0x096)
1509#define SPR_MPC_COUNTB (0x097)
0bfe9299 1510#define SPR_CTRL (0x098)
80d11f44
JM		 1511#define SPR_MPC_CMPE (0x098)
1512#define SPR_MPC_CMPF (0x099)
7019cb3d 1513#define SPR_FSCR (0x099)
80d11f44
JM		 1514#define SPR_MPC_CMPG (0x09A)
1515#define SPR_MPC_CMPH (0x09B)
1516#define SPR_MPC_LCTRL1 (0x09C)
1517#define SPR_MPC_LCTRL2 (0x09D)
f80872e2 1518#define SPR_UAMOR (0x09D)
80d11f44
JM		 1519#define SPR_MPC_ICTRL (0x09E)
1520#define SPR_MPC_BAR (0x09F)
d6f1445f 1521#define SPR_PSPB (0x09F)
cfc61ba6 1522#define SPR_DPDES (0x0B0)
a7913d5e 1523#define SPR_DAWR0 (0x0B4)
1488270e 1524#define SPR_RPR (0x0BA)
eb5ceb4d 1525#define SPR_CIABR (0x0BB)
a7913d5e 1526#define SPR_DAWRX0 (0x0BC)
1488270e 1527#define SPR_HFSCR (0x0BE)
80d11f44
JM		 1528#define SPR_VRSAVE (0x100)
1529#define SPR_USPRG0 (0x100)
1530#define SPR_USPRG1 (0x101)
1531#define SPR_USPRG2 (0x102)
1532#define SPR_USPRG3 (0x103)
1533#define SPR_USPRG4 (0x104)
1534#define SPR_USPRG5 (0x105)
1535#define SPR_USPRG6 (0x106)
1536#define SPR_USPRG7 (0x107)
1537#define SPR_VTBL (0x10C)
1538#define SPR_VTBU (0x10D)
1539#define SPR_SPRG0 (0x110)
1540#define SPR_SPRG1 (0x111)
1541#define SPR_SPRG2 (0x112)
1542#define SPR_SPRG3 (0x113)
1543#define SPR_SPRG4 (0x114)
1544#define SPR_SCOMC (0x114)
1545#define SPR_SPRG5 (0x115)
1546#define SPR_SCOMD (0x115)
1547#define SPR_SPRG6 (0x116)
1548#define SPR_SPRG7 (0x117)
1549#define SPR_ASR (0x118)
1550#define SPR_EAR (0x11A)
1551#define SPR_TBL (0x11C)
1552#define SPR_TBU (0x11D)
1553#define SPR_TBU40 (0x11E)
1554#define SPR_SVR (0x11E)
1555#define SPR_BOOKE_PIR (0x11E)
1556#define SPR_PVR (0x11F)
1557#define SPR_HSPRG0 (0x130)
1558#define SPR_BOOKE_DBSR (0x130)
1559#define SPR_HSPRG1 (0x131)
1560#define SPR_HDSISR (0x132)
1561#define SPR_HDAR (0x133)
90dc8812 1562#define SPR_BOOKE_EPCR (0x133)
9d52e907 1563#define SPR_SPURR (0x134)
80d11f44
JM		 1564#define SPR_BOOKE_DBCR0 (0x134)
1565#define SPR_IBCR (0x135)
1566#define SPR_PURR (0x135)
1567#define SPR_BOOKE_DBCR1 (0x135)
1568#define SPR_DBCR (0x136)
1569#define SPR_HDEC (0x136)
1570#define SPR_BOOKE_DBCR2 (0x136)
1571#define SPR_HIOR (0x137)
1572#define SPR_MBAR (0x137)
1573#define SPR_RMOR (0x138)
1574#define SPR_BOOKE_IAC1 (0x138)
1575#define SPR_HRMOR (0x139)
1576#define SPR_BOOKE_IAC2 (0x139)
1577#define SPR_HSRR0 (0x13A)
1578#define SPR_BOOKE_IAC3 (0x13A)
1579#define SPR_HSRR1 (0x13B)
1580#define SPR_BOOKE_IAC4 (0x13B)
80d11f44 1581#define SPR_BOOKE_DAC1 (0x13C)
1488270e 1582#define SPR_MMCRH (0x13C)
80d11f44
JM		 1583#define SPR_DABR2 (0x13D)
1584#define SPR_BOOKE_DAC2 (0x13D)
1488270e 1585#define SPR_TFMR (0x13D)
80d11f44 1586#define SPR_BOOKE_DVC1 (0x13E)
6475c9f0 1587#define SPR_LPCR (0x13E)
80d11f44 1588#define SPR_BOOKE_DVC2 (0x13F)
1488270e 1589#define SPR_LPIDR (0x13F)
80d11f44 1590#define SPR_BOOKE_TSR (0x150)
1488270e
BH		 1591#define SPR_HMER (0x150)
1592#define SPR_HMEER (0x151)
6d9412ea 1593#define SPR_PCR (0x152)
1488270e 1594#define SPR_BOOKE_LPIDR (0x152)
80d11f44 1595#define SPR_BOOKE_TCR (0x154)
a1ef618a
AG		 1596#define SPR_BOOKE_TLB0PS (0x158)
1597#define SPR_BOOKE_TLB1PS (0x159)
1598#define SPR_BOOKE_TLB2PS (0x15A)
1599#define SPR_BOOKE_TLB3PS (0x15B)
1488270e 1600#define SPR_AMOR (0x15D)
84755ed5 1601#define SPR_BOOKE_MAS7_MAS3 (0x174)
80d11f44
JM		 1602#define SPR_BOOKE_IVOR0 (0x190)
1603#define SPR_BOOKE_IVOR1 (0x191)
1604#define SPR_BOOKE_IVOR2 (0x192)
1605#define SPR_BOOKE_IVOR3 (0x193)
1606#define SPR_BOOKE_IVOR4 (0x194)
1607#define SPR_BOOKE_IVOR5 (0x195)
1608#define SPR_BOOKE_IVOR6 (0x196)
1609#define SPR_BOOKE_IVOR7 (0x197)
1610#define SPR_BOOKE_IVOR8 (0x198)
1611#define SPR_BOOKE_IVOR9 (0x199)
1612#define SPR_BOOKE_IVOR10 (0x19A)
1613#define SPR_BOOKE_IVOR11 (0x19B)
1614#define SPR_BOOKE_IVOR12 (0x19C)
1615#define SPR_BOOKE_IVOR13 (0x19D)
1616#define SPR_BOOKE_IVOR14 (0x19E)
1617#define SPR_BOOKE_IVOR15 (0x19F)
e9205258
AG		 1618#define SPR_BOOKE_IVOR38 (0x1B0)
1619#define SPR_BOOKE_IVOR39 (0x1B1)
1620#define SPR_BOOKE_IVOR40 (0x1B2)
1621#define SPR_BOOKE_IVOR41 (0x1B3)
1622#define SPR_BOOKE_IVOR42 (0x1B4)
45eb5611
AG		 1623#define SPR_BOOKE_GIVOR2 (0x1B8)
1624#define SPR_BOOKE_GIVOR3 (0x1B9)
1625#define SPR_BOOKE_GIVOR4 (0x1BA)
1626#define SPR_BOOKE_GIVOR8 (0x1BB)
1627#define SPR_BOOKE_GIVOR13 (0x1BC)
1628#define SPR_BOOKE_GIVOR14 (0x1BD)
d1a721ab 1629#define SPR_TIR (0x1BE)
4a7518e0 1630#define SPR_PTCR (0x1D0)
80d11f44
JM		 1631#define SPR_BOOKE_SPEFSCR (0x200)
1632#define SPR_Exxx_BBEAR (0x201)
1633#define SPR_Exxx_BBTAR (0x202)
1634#define SPR_Exxx_L1CFG0 (0x203)
d2ea2bf7 1635#define SPR_Exxx_L1CFG1 (0x204)
80d11f44
JM		 1636#define SPR_Exxx_NPIDR (0x205)
1637#define SPR_ATBL (0x20E)
1638#define SPR_ATBU (0x20F)
1639#define SPR_IBAT0U (0x210)
1640#define SPR_BOOKE_IVOR32 (0x210)
1641#define SPR_RCPU_MI_GRA (0x210)
1642#define SPR_IBAT0L (0x211)
1643#define SPR_BOOKE_IVOR33 (0x211)
1644#define SPR_IBAT1U (0x212)
1645#define SPR_BOOKE_IVOR34 (0x212)
1646#define SPR_IBAT1L (0x213)
1647#define SPR_BOOKE_IVOR35 (0x213)
1648#define SPR_IBAT2U (0x214)
1649#define SPR_BOOKE_IVOR36 (0x214)
1650#define SPR_IBAT2L (0x215)
1651#define SPR_BOOKE_IVOR37 (0x215)
1652#define SPR_IBAT3U (0x216)
1653#define SPR_IBAT3L (0x217)
1654#define SPR_DBAT0U (0x218)
1655#define SPR_RCPU_L2U_GRA (0x218)
1656#define SPR_DBAT0L (0x219)
1657#define SPR_DBAT1U (0x21A)
1658#define SPR_DBAT1L (0x21B)
1659#define SPR_DBAT2U (0x21C)
1660#define SPR_DBAT2L (0x21D)
1661#define SPR_DBAT3U (0x21E)
1662#define SPR_DBAT3L (0x21F)
1663#define SPR_IBAT4U (0x230)
1664#define SPR_RPCU_BBCMCR (0x230)
1665#define SPR_MPC_IC_CST (0x230)
1666#define SPR_Exxx_CTXCR (0x230)
1667#define SPR_IBAT4L (0x231)
1668#define SPR_MPC_IC_ADR (0x231)
1669#define SPR_Exxx_DBCR3 (0x231)
1670#define SPR_IBAT5U (0x232)
1671#define SPR_MPC_IC_DAT (0x232)
1672#define SPR_Exxx_DBCNT (0x232)
1673#define SPR_IBAT5L (0x233)
1674#define SPR_IBAT6U (0x234)
1675#define SPR_IBAT6L (0x235)
1676#define SPR_IBAT7U (0x236)
1677#define SPR_IBAT7L (0x237)
1678#define SPR_DBAT4U (0x238)
1679#define SPR_RCPU_L2U_MCR (0x238)
1680#define SPR_MPC_DC_CST (0x238)
1681#define SPR_Exxx_ALTCTXCR (0x238)
1682#define SPR_DBAT4L (0x239)
1683#define SPR_MPC_DC_ADR (0x239)
1684#define SPR_DBAT5U (0x23A)
1685#define SPR_BOOKE_MCSRR0 (0x23A)
1686#define SPR_MPC_DC_DAT (0x23A)
1687#define SPR_DBAT5L (0x23B)
1688#define SPR_BOOKE_MCSRR1 (0x23B)
1689#define SPR_DBAT6U (0x23C)
1690#define SPR_BOOKE_MCSR (0x23C)
1691#define SPR_DBAT6L (0x23D)
1692#define SPR_Exxx_MCAR (0x23D)
1693#define SPR_DBAT7U (0x23E)
1694#define SPR_BOOKE_DSRR0 (0x23E)
1695#define SPR_DBAT7L (0x23F)
1696#define SPR_BOOKE_DSRR1 (0x23F)
1697#define SPR_BOOKE_SPRG8 (0x25C)
1698#define SPR_BOOKE_SPRG9 (0x25D)
1699#define SPR_BOOKE_MAS0 (0x270)
1700#define SPR_BOOKE_MAS1 (0x271)
1701#define SPR_BOOKE_MAS2 (0x272)
1702#define SPR_BOOKE_MAS3 (0x273)
1703#define SPR_BOOKE_MAS4 (0x274)
1704#define SPR_BOOKE_MAS5 (0x275)
1705#define SPR_BOOKE_MAS6 (0x276)
1706#define SPR_BOOKE_PID1 (0x279)
1707#define SPR_BOOKE_PID2 (0x27A)
1708#define SPR_MPC_DPDR (0x280)
1709#define SPR_MPC_IMMR (0x288)
1710#define SPR_BOOKE_TLB0CFG (0x2B0)
1711#define SPR_BOOKE_TLB1CFG (0x2B1)
1712#define SPR_BOOKE_TLB2CFG (0x2B2)
1713#define SPR_BOOKE_TLB3CFG (0x2B3)
1714#define SPR_BOOKE_EPR (0x2BE)
1715#define SPR_PERF0 (0x300)
1716#define SPR_RCPU_MI_RBA0 (0x300)
1717#define SPR_MPC_MI_CTR (0x300)
14646457 1718#define SPR_POWER_USIER (0x300)
80d11f44
JM		 1719#define SPR_PERF1 (0x301)
1720#define SPR_RCPU_MI_RBA1 (0x301)
70c53407 1721#define SPR_POWER_UMMCR2 (0x301)
80d11f44
JM		 1722#define SPR_PERF2 (0x302)
1723#define SPR_RCPU_MI_RBA2 (0x302)
1724#define SPR_MPC_MI_AP (0x302)
75b9c321 1725#define SPR_POWER_UMMCRA (0x302)
80d11f44
JM		 1726#define SPR_PERF3 (0x303)
1727#define SPR_RCPU_MI_RBA3 (0x303)
1728#define SPR_MPC_MI_EPN (0x303)
fd51ff63 1729#define SPR_POWER_UPMC1 (0x303)
80d11f44 1730#define SPR_PERF4 (0x304)
fd51ff63 1731#define SPR_POWER_UPMC2 (0x304)
80d11f44
JM		 1732#define SPR_PERF5 (0x305)
1733#define SPR_MPC_MI_TWC (0x305)
fd51ff63 1734#define SPR_POWER_UPMC3 (0x305)
80d11f44
JM		 1735#define SPR_PERF6 (0x306)
1736#define SPR_MPC_MI_RPN (0x306)
fd51ff63 1737#define SPR_POWER_UPMC4 (0x306)
80d11f44 1738#define SPR_PERF7 (0x307)
fd51ff63 1739#define SPR_POWER_UPMC5 (0x307)
80d11f44
JM		 1740#define SPR_PERF8 (0x308)
1741#define SPR_RCPU_L2U_RBA0 (0x308)
1742#define SPR_MPC_MD_CTR (0x308)
fd51ff63 1743#define SPR_POWER_UPMC6 (0x308)
80d11f44
JM		 1744#define SPR_PERF9 (0x309)
1745#define SPR_RCPU_L2U_RBA1 (0x309)
1746#define SPR_MPC_MD_CASID (0x309)
c36c97f8 1747#define SPR_970_UPMC7 (0X309)
80d11f44
JM		 1748#define SPR_PERFA (0x30A)
1749#define SPR_RCPU_L2U_RBA2 (0x30A)
1750#define SPR_MPC_MD_AP (0x30A)
c36c97f8 1751#define SPR_970_UPMC8 (0X30A)
80d11f44
JM		 1752#define SPR_PERFB (0x30B)
1753#define SPR_RCPU_L2U_RBA3 (0x30B)
1754#define SPR_MPC_MD_EPN (0x30B)
fd51ff63 1755#define SPR_POWER_UMMCR0 (0X30B)
80d11f44
JM		 1756#define SPR_PERFC (0x30C)
1757#define SPR_MPC_MD_TWB (0x30C)
fd51ff63 1758#define SPR_POWER_USIAR (0X30C)
80d11f44
JM		 1759#define SPR_PERFD (0x30D)
1760#define SPR_MPC_MD_TWC (0x30D)
fd51ff63 1761#define SPR_POWER_USDAR (0X30D)
80d11f44
JM		 1762#define SPR_PERFE (0x30E)
1763#define SPR_MPC_MD_RPN (0x30E)
fd51ff63 1764#define SPR_POWER_UMMCR1 (0X30E)
80d11f44
JM		 1765#define SPR_PERFF (0x30F)
1766#define SPR_MPC_MD_TW (0x30F)
1767#define SPR_UPERF0 (0x310)
14646457 1768#define SPR_POWER_SIER (0x310)
80d11f44 1769#define SPR_UPERF1 (0x311)
70c53407 1770#define SPR_POWER_MMCR2 (0x311)
80d11f44 1771#define SPR_UPERF2 (0x312)
75b9c321 1772#define SPR_POWER_MMCRA (0X312)
80d11f44 1773#define SPR_UPERF3 (0x313)
fd51ff63 1774#define SPR_POWER_PMC1 (0X313)
80d11f44 1775#define SPR_UPERF4 (0x314)
fd51ff63 1776#define SPR_POWER_PMC2 (0X314)
80d11f44 1777#define SPR_UPERF5 (0x315)
fd51ff63 1778#define SPR_POWER_PMC3 (0X315)
80d11f44 1779#define SPR_UPERF6 (0x316)
fd51ff63 1780#define SPR_POWER_PMC4 (0X316)
80d11f44 1781#define SPR_UPERF7 (0x317)
fd51ff63 1782#define SPR_POWER_PMC5 (0X317)
80d11f44 1783#define SPR_UPERF8 (0x318)
fd51ff63 1784#define SPR_POWER_PMC6 (0X318)
80d11f44 1785#define SPR_UPERF9 (0x319)
c36c97f8 1786#define SPR_970_PMC7 (0X319)
80d11f44 1787#define SPR_UPERFA (0x31A)
c36c97f8 1788#define SPR_970_PMC8 (0X31A)
80d11f44 1789#define SPR_UPERFB (0x31B)
fd51ff63 1790#define SPR_POWER_MMCR0 (0X31B)
80d11f44 1791#define SPR_UPERFC (0x31C)
fd51ff63 1792#define SPR_POWER_SIAR (0X31C)
80d11f44 1793#define SPR_UPERFD (0x31D)
fd51ff63 1794#define SPR_POWER_SDAR (0X31D)
80d11f44 1795#define SPR_UPERFE (0x31E)
fd51ff63 1796#define SPR_POWER_MMCR1 (0X31E)
80d11f44
JM		 1797#define SPR_UPERFF (0x31F)
1798#define SPR_RCPU_MI_RA0 (0x320)
1799#define SPR_MPC_MI_DBCAM (0x320)
4ee4a03b 1800#define SPR_BESCRS (0x320)
80d11f44
JM		 1801#define SPR_RCPU_MI_RA1 (0x321)
1802#define SPR_MPC_MI_DBRAM0 (0x321)
4ee4a03b 1803#define SPR_BESCRSU (0x321)
80d11f44
JM		 1804#define SPR_RCPU_MI_RA2 (0x322)
1805#define SPR_MPC_MI_DBRAM1 (0x322)
4ee4a03b 1806#define SPR_BESCRR (0x322)
80d11f44 1807#define SPR_RCPU_MI_RA3 (0x323)
4ee4a03b
AK		 1808#define SPR_BESCRRU (0x323)
1809#define SPR_EBBHR (0x324)
1810#define SPR_EBBRR (0x325)
1811#define SPR_BESCR (0x326)
80d11f44
JM		 1812#define SPR_RCPU_L2U_RA0 (0x328)
1813#define SPR_MPC_MD_DBCAM (0x328)
1814#define SPR_RCPU_L2U_RA1 (0x329)
1815#define SPR_MPC_MD_DBRAM0 (0x329)
1816#define SPR_RCPU_L2U_RA2 (0x32A)
1817#define SPR_MPC_MD_DBRAM1 (0x32A)
1818#define SPR_RCPU_L2U_RA3 (0x32B)
60511041 1819#define SPR_TAR (0x32F)
32d0f0d8 1820#define SPR_ASDR (0x330)
21a558be 1821#define SPR_IC (0x350)
3ba55e39 1822#define SPR_VTB (0x351)
1488270e 1823#define SPR_MMCRC (0x353)
b8af5b2d 1824#define SPR_PSSCR (0x357)
80d11f44
JM		 1825#define SPR_440_INV0 (0x370)
1826#define SPR_440_INV1 (0x371)
1827#define SPR_440_INV2 (0x372)
1828#define SPR_440_INV3 (0x373)
1829#define SPR_440_ITV0 (0x374)
1830#define SPR_440_ITV1 (0x375)
1831#define SPR_440_ITV2 (0x376)
1832#define SPR_440_ITV3 (0x377)
1833#define SPR_440_CCR1 (0x378)
14646457
BH		 1834#define SPR_TACR (0x378)
1835#define SPR_TCSCR (0x379)
1836#define SPR_CSIGR (0x37a)
80d11f44 1837#define SPR_DCRIPR (0x37B)
14646457
BH		 1838#define SPR_POWER_SPMC1 (0x37C)
1839#define SPR_POWER_SPMC2 (0x37D)
70c53407 1840#define SPR_POWER_MMCRS (0x37E)
9c1cf38d 1841#define SPR_WORT (0x37F)
80d11f44 1842#define SPR_PPR (0x380)
bd928eba 1843#define SPR_750_GQR0 (0x390)
80d11f44 1844#define SPR_440_DNV0 (0x390)
bd928eba 1845#define SPR_750_GQR1 (0x391)
80d11f44 1846#define SPR_440_DNV1 (0x391)
bd928eba 1847#define SPR_750_GQR2 (0x392)
80d11f44 1848#define SPR_440_DNV2 (0x392)
bd928eba 1849#define SPR_750_GQR3 (0x393)
80d11f44 1850#define SPR_440_DNV3 (0x393)
bd928eba 1851#define SPR_750_GQR4 (0x394)
80d11f44 1852#define SPR_440_DTV0 (0x394)
bd928eba 1853#define SPR_750_GQR5 (0x395)
80d11f44 1854#define SPR_440_DTV1 (0x395)
bd928eba 1855#define SPR_750_GQR6 (0x396)
80d11f44 1856#define SPR_440_DTV2 (0x396)
bd928eba 1857#define SPR_750_GQR7 (0x397)
80d11f44 1858#define SPR_440_DTV3 (0x397)
bd928eba
JM		 1859#define SPR_750_THRM4 (0x398)
1860#define SPR_750CL_HID2 (0x398)
80d11f44 1861#define SPR_440_DVLIM (0x398)
bd928eba 1862#define SPR_750_WPAR (0x399)
80d11f44 1863#define SPR_440_IVLIM (0x399)
1488270e 1864#define SPR_TSCR (0x399)
bd928eba
JM		 1865#define SPR_750_DMAU (0x39A)
1866#define SPR_750_DMAL (0x39B)
80d11f44
JM		 1867#define SPR_440_RSTCFG (0x39B)
1868#define SPR_BOOKE_DCDBTRL (0x39C)
1869#define SPR_BOOKE_DCDBTRH (0x39D)
1870#define SPR_BOOKE_ICDBTRL (0x39E)
1871#define SPR_BOOKE_ICDBTRH (0x39F)
cb8b8bf8
AK		 1872#define SPR_74XX_UMMCR2 (0x3A0)
1873#define SPR_7XX_UPMC5 (0x3A1)
1874#define SPR_7XX_UPMC6 (0x3A2)
80d11f44 1875#define SPR_UBAMR (0x3A7)
cb8b8bf8
AK		 1876#define SPR_7XX_UMMCR0 (0x3A8)
1877#define SPR_7XX_UPMC1 (0x3A9)
1878#define SPR_7XX_UPMC2 (0x3AA)
1879#define SPR_7XX_USIAR (0x3AB)
1880#define SPR_7XX_UMMCR1 (0x3AC)
1881#define SPR_7XX_UPMC3 (0x3AD)
1882#define SPR_7XX_UPMC4 (0x3AE)
80d11f44
JM		 1883#define SPR_USDA (0x3AF)
1884#define SPR_40x_ZPR (0x3B0)
1885#define SPR_BOOKE_MAS7 (0x3B0)
cb8b8bf8
AK		 1886#define SPR_74XX_MMCR2 (0x3B0)
1887#define SPR_7XX_PMC5 (0x3B1)
80d11f44 1888#define SPR_40x_PID (0x3B1)
cb8b8bf8 1889#define SPR_7XX_PMC6 (0x3B2)
80d11f44 1890#define SPR_440_MMUCR (0x3B2)
80d11f44
JM		 1891#define SPR_4xx_CCR0 (0x3B3)
1892#define SPR_BOOKE_EPLC (0x3B3)
80d11f44
JM		 1893#define SPR_405_IAC3 (0x3B4)
1894#define SPR_BOOKE_EPSC (0x3B4)
80d11f44 1895#define SPR_405_IAC4 (0x3B5)
80d11f44 1896#define SPR_405_DVC1 (0x3B6)
80d11f44 1897#define SPR_405_DVC2 (0x3B7)
80d11f44 1898#define SPR_BAMR (0x3B7)
cb8b8bf8
AK		 1899#define SPR_7XX_MMCR0 (0x3B8)
1900#define SPR_7XX_PMC1 (0x3B9)
80d11f44 1901#define SPR_40x_SGR (0x3B9)
cb8b8bf8 1902#define SPR_7XX_PMC2 (0x3BA)
80d11f44 1903#define SPR_40x_DCWR (0x3BA)
cb8b8bf8 1904#define SPR_7XX_SIAR (0x3BB)
80d11f44 1905#define SPR_405_SLER (0x3BB)
cb8b8bf8 1906#define SPR_7XX_MMCR1 (0x3BC)
80d11f44 1907#define SPR_405_SU0R (0x3BC)
80d11f44 1908#define SPR_401_SKR (0x3BC)
cb8b8bf8 1909#define SPR_7XX_PMC3 (0x3BD)
80d11f44 1910#define SPR_405_DBCR1 (0x3BD)
cb8b8bf8 1911#define SPR_7XX_PMC4 (0x3BE)
80d11f44 1912#define SPR_SDA (0x3BF)
80d11f44
JM		 1913#define SPR_403_VTBL (0x3CC)
1914#define SPR_403_VTBU (0x3CD)
1915#define SPR_DMISS (0x3D0)
1916#define SPR_DCMP (0x3D1)
1917#define SPR_HASH1 (0x3D2)
1918#define SPR_HASH2 (0x3D3)
1919#define SPR_BOOKE_ICDBDR (0x3D3)
1920#define SPR_TLBMISS (0x3D4)
1921#define SPR_IMISS (0x3D4)
1922#define SPR_40x_ESR (0x3D4)
1923#define SPR_PTEHI (0x3D5)
1924#define SPR_ICMP (0x3D5)
1925#define SPR_40x_DEAR (0x3D5)
1926#define SPR_PTELO (0x3D6)
1927#define SPR_RPA (0x3D6)
1928#define SPR_40x_EVPR (0x3D6)
1929#define SPR_L3PM (0x3D7)
1930#define SPR_403_CDBCR (0x3D7)
4e777442 1931#define SPR_L3ITCR0 (0x3D8)
80d11f44
JM		 1932#define SPR_TCR (0x3D8)
1933#define SPR_40x_TSR (0x3D8)
1934#define SPR_IBR (0x3DA)
1935#define SPR_40x_TCR (0x3DA)
1936#define SPR_ESASRR (0x3DB)
1937#define SPR_40x_PIT (0x3DB)
1938#define SPR_403_TBL (0x3DC)
1939#define SPR_403_TBU (0x3DD)
1940#define SPR_SEBR (0x3DE)
1941#define SPR_40x_SRR2 (0x3DE)
1942#define SPR_SER (0x3DF)
1943#define SPR_40x_SRR3 (0x3DF)
4e777442 1944#define SPR_L3OHCR (0x3E8)
80d11f44
JM		 1945#define SPR_L3ITCR1 (0x3E9)
1946#define SPR_L3ITCR2 (0x3EA)
1947#define SPR_L3ITCR3 (0x3EB)
1948#define SPR_HID0 (0x3F0)
1949#define SPR_40x_DBSR (0x3F0)
1950#define SPR_HID1 (0x3F1)
1951#define SPR_IABR (0x3F2)
1952#define SPR_40x_DBCR0 (0x3F2)
80d11f44
JM		 1953#define SPR_Exxx_L1CSR0 (0x3F2)
1954#define SPR_ICTRL (0x3F3)
1955#define SPR_HID2 (0x3F3)
bd928eba 1956#define SPR_750CL_HID4 (0x3F3)
80d11f44
JM		 1957#define SPR_Exxx_L1CSR1 (0x3F3)
1958#define SPR_440_DBDR (0x3F3)
1959#define SPR_LDSTDB (0x3F4)
bd928eba 1960#define SPR_750_TDCL (0x3F4)
80d11f44
JM		 1961#define SPR_40x_IAC1 (0x3F4)
1962#define SPR_MMUCSR0 (0x3F4)
ba881002 1963#define SPR_970_HID4 (0x3F4)
80d11f44 1964#define SPR_DABR (0x3F5)
3fc6c082 1965#define DABR_MASK (~(target_ulong)0x7)
80d11f44
JM		 1966#define SPR_Exxx_BUCSR (0x3F5)
1967#define SPR_40x_IAC2 (0x3F5)
80d11f44
JM		 1968#define SPR_40x_DAC1 (0x3F6)
1969#define SPR_MSSCR0 (0x3F6)
1970#define SPR_970_HID5 (0x3F6)
1971#define SPR_MSSSR0 (0x3F7)
4e777442 1972#define SPR_MSSCR1 (0x3F7)
80d11f44
JM		 1973#define SPR_DABRX (0x3F7)
1974#define SPR_40x_DAC2 (0x3F7)
1975#define SPR_MMUCFG (0x3F7)
1976#define SPR_LDSTCR (0x3F8)
1977#define SPR_L2PMCR (0x3F8)
bd928eba 1978#define SPR_750FX_HID2 (0x3F8)
80d11f44
JM		 1979#define SPR_Exxx_L1FINV0 (0x3F8)
1980#define SPR_L2CR (0x3F9)
298091f8 1981#define SPR_Exxx_L2CSR0 (0x3F9)
80d11f44 1982#define SPR_L3CR (0x3FA)
bd928eba 1983#define SPR_750_TDCH (0x3FA)
80d11f44
JM		 1984#define SPR_IABR2 (0x3FA)
1985#define SPR_40x_DCCR (0x3FA)
1986#define SPR_ICTC (0x3FB)
1987#define SPR_40x_ICCR (0x3FB)
1988#define SPR_THRM1 (0x3FC)
1989#define SPR_403_PBL1 (0x3FC)
1990#define SPR_SP (0x3FD)
1991#define SPR_THRM2 (0x3FD)
1992#define SPR_403_PBU1 (0x3FD)
1993#define SPR_604_HID13 (0x3FD)
1994#define SPR_LT (0x3FE)
1995#define SPR_THRM3 (0x3FE)
1996#define SPR_RCPU_FPECR (0x3FE)
1997#define SPR_403_PBL2 (0x3FE)
1998#define SPR_PIR (0x3FF)
1999#define SPR_403_PBU2 (0x3FF)
80d11f44
JM		 2000#define SPR_604_HID15 (0x3FF)
2001#define SPR_E500_SVR (0x3FF)
79aceca5 2002
84755ed5
AG		 2003/* Disable MAS Interrupt Updates for Hypervisor */
2004#define EPCR_DMIUH (1 << 22)
2005/* Disable Guest TLB Management Instructions */
2006#define EPCR_DGTMI (1 << 23)
2007/* Guest Interrupt Computation Mode */
2008#define EPCR_GICM (1 << 24)
2009/* Interrupt Computation Mode */
2010#define EPCR_ICM (1 << 25)
2011/* Disable Embedded Hypervisor Debug */
2012#define EPCR_DUVD (1 << 26)
2013/* Instruction Storage Interrupt Directed to Guest State */
2014#define EPCR_ISIGS (1 << 27)
2015/* Data Storage Interrupt Directed to Guest State */
2016#define EPCR_DSIGS (1 << 28)
2017/* Instruction TLB Error Interrupt Directed to Guest State */
2018#define EPCR_ITLBGS (1 << 29)
2019/* Data TLB Error Interrupt Directed to Guest State */
2020#define EPCR_DTLBGS (1 << 30)
2021/* External Input Interrupt Directed to Guest State */
2022#define EPCR_EXTGS (1 << 31)
2023
c647e3fe
DG		 2024#define L1CSR0_CPE 0x00010000 /* Data Cache Parity Enable */
2025#define L1CSR0_CUL 0x00000400 /* (D-)Cache Unable to Lock */
2026#define L1CSR0_DCLFR 0x00000100 /* D-Cache Lock Flash Reset */
2027#define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */
2028#define L1CSR0_DCE 0x00000001 /* Data Cache Enable */
ea71258d 2029
c647e3fe
DG		 2030#define L1CSR1_CPE 0x00010000 /* Instruction Cache Parity Enable */
2031#define L1CSR1_ICUL 0x00000400 /* I-Cache Unable to Lock */
2032#define L1CSR1_ICLFR 0x00000100 /* I-Cache Lock Flash Reset */
2033#define L1CSR1_ICFI 0x00000002 /* Instruction Cache Flash Invalidate */
2034#define L1CSR1_ICE 0x00000001 /* Instruction Cache Enable */
ea71258d 2035
298091f8
BM		 2036/* E500 L2CSR0 */
2037#define E500_L2CSR0_L2FI (1 << 21) /* L2 cache flash invalidate */
2038#define E500_L2CSR0_L2FL (1 << 11) /* L2 cache flush */
2039#define E500_L2CSR0_L2LFC (1 << 10) /* L2 cache lock flash clear */
2040
bbc01ca7 2041/* HID0 bits */
1488270e
BH		 2042#define HID0_DEEPNAP (1 << 24) /* pre-2.06 */
2043#define HID0_DOZE (1 << 23) /* pre-2.06 */
2044#define HID0_NAP (1 << 22) /* pre-2.06 */
2a83f997 2045#define HID0_HILE PPC_BIT(19) /* POWER8 */
0bfc0cf0 2046#define HID0_POWER9_HILE PPC_BIT(4)
bbc01ca7 2047
c29b735c
NF		 2048/*****************************************************************************/
2049/* PowerPC Instructions types definitions */
2050enum {
2051 PPC_NONE = 0x0000000000000000ULL,
2052 /* PowerPC base instructions set */
2053 PPC_INSNS_BASE = 0x0000000000000001ULL,
2054 /* integer operations instructions */
2055#define PPC_INTEGER PPC_INSNS_BASE
2056 /* flow control instructions */
2057#define PPC_FLOW PPC_INSNS_BASE
2058 /* virtual memory instructions */
2059#define PPC_MEM PPC_INSNS_BASE
2060 /* ld/st with reservation instructions */
2061#define PPC_RES PPC_INSNS_BASE
2062 /* spr/msr access instructions */
2063#define PPC_MISC PPC_INSNS_BASE
c29b735c
NF		 2064 /* 64 bits PowerPC instruction set */
2065 PPC_64B = 0x0000000000000020ULL,
2066 /* New 64 bits extensions (PowerPC 2.0x) */
2067 PPC_64BX = 0x0000000000000040ULL,
2068 /* 64 bits hypervisor extensions */
2069 PPC_64H = 0x0000000000000080ULL,
2070 /* New wait instruction (PowerPC 2.0x) */
2071 PPC_WAIT = 0x0000000000000100ULL,
2072 /* Time base mftb instruction */
2073 PPC_MFTB = 0x0000000000000200ULL,
2074
2075 /* Fixed-point unit extensions */
c29b735c
NF		 2076 /* isel instruction */
2077 PPC_ISEL = 0x0000000000000800ULL,
2078 /* popcntb instruction */
2079 PPC_POPCNTB = 0x0000000000001000ULL,
2080 /* string load / store */
2081 PPC_STRING = 0x0000000000002000ULL,
b7815375
BH		 2082 /* real mode cache inhibited load / store */
2083 PPC_CILDST = 0x0000000000004000ULL,
c29b735c
NF		 2084
2085 /* Floating-point unit extensions */
2086 /* Optional floating point instructions */
2087 PPC_FLOAT = 0x0000000000010000ULL,
2088 /* New floating-point extensions (PowerPC 2.0x) */
2089 PPC_FLOAT_EXT = 0x0000000000020000ULL,
2090 PPC_FLOAT_FSQRT = 0x0000000000040000ULL,
2091 PPC_FLOAT_FRES = 0x0000000000080000ULL,
2092 PPC_FLOAT_FRSQRTE = 0x0000000000100000ULL,
2093 PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
2094 PPC_FLOAT_FSEL = 0x0000000000400000ULL,
2095 PPC_FLOAT_STFIWX = 0x0000000000800000ULL,
2096
2097 /* Vector/SIMD extensions */
2098 /* Altivec support */
2099 PPC_ALTIVEC = 0x0000000001000000ULL,
2100 /* PowerPC 2.03 SPE extension */
2101 PPC_SPE = 0x0000000002000000ULL,
2102 /* PowerPC 2.03 SPE single-precision floating-point extension */
2103 PPC_SPE_SINGLE = 0x0000000004000000ULL,
2104 /* PowerPC 2.03 SPE double-precision floating-point extension */
2105 PPC_SPE_DOUBLE = 0x0000000008000000ULL,
2106
2107 /* Optional memory control instructions */
2108 PPC_MEM_TLBIA = 0x0000000010000000ULL,
2109 PPC_MEM_TLBIE = 0x0000000020000000ULL,
2110 PPC_MEM_TLBSYNC = 0x0000000040000000ULL,
2111 /* sync instruction */
2112 PPC_MEM_SYNC = 0x0000000080000000ULL,
2113 /* eieio instruction */
2114 PPC_MEM_EIEIO = 0x0000000100000000ULL,
2115
2116 /* Cache control instructions */
2117 PPC_CACHE = 0x0000000200000000ULL,
2118 /* icbi instruction */
2119 PPC_CACHE_ICBI = 0x0000000400000000ULL,
8e33944f 2120 /* dcbz instruction */
c29b735c 2121 PPC_CACHE_DCBZ = 0x0000000800000000ULL,
c29b735c
NF		 2122 /* dcba instruction */
2123 PPC_CACHE_DCBA = 0x0000002000000000ULL,
2124 /* Freescale cache locking instructions */
2125 PPC_CACHE_LOCK = 0x0000004000000000ULL,
2126
2127 /* MMU related extensions */
2128 /* external control instructions */
2129 PPC_EXTERN = 0x0000010000000000ULL,
2130 /* segment register access instructions */
2131 PPC_SEGMENT = 0x0000020000000000ULL,
2132 /* PowerPC 6xx TLB management instructions */
2133 PPC_6xx_TLB = 0x0000040000000000ULL,
c29b735c
NF		 2134 /* PowerPC 40x TLB management instructions */
2135 PPC_40x_TLB = 0x0000100000000000ULL,
2136 /* segment register access instructions for PowerPC 64 "bridge" */
2137 PPC_SEGMENT_64B = 0x0000200000000000ULL,
2138 /* SLB management */
2139 PPC_SLBI = 0x0000400000000000ULL,
2140
2141 /* Embedded PowerPC dedicated instructions */
2142 PPC_WRTEE = 0x0001000000000000ULL,
2143 /* PowerPC 40x exception model */
2144 PPC_40x_EXCP = 0x0002000000000000ULL,
2145 /* PowerPC 405 Mac instructions */
2146 PPC_405_MAC = 0x0004000000000000ULL,
2147 /* PowerPC 440 specific instructions */
2148 PPC_440_SPEC = 0x0008000000000000ULL,
2149 /* BookE (embedded) PowerPC specification */
2150 PPC_BOOKE = 0x0010000000000000ULL,
2151 /* mfapidi instruction */
2152 PPC_MFAPIDI = 0x0020000000000000ULL,
2153 /* tlbiva instruction */
2154 PPC_TLBIVA = 0x0040000000000000ULL,
2155 /* tlbivax instruction */
2156 PPC_TLBIVAX = 0x0080000000000000ULL,
2157 /* PowerPC 4xx dedicated instructions */
2158 PPC_4xx_COMMON = 0x0100000000000000ULL,
2159 /* PowerPC 40x ibct instructions */
2160 PPC_40x_ICBT = 0x0200000000000000ULL,
2161 /* rfmci is not implemented in all BookE PowerPC */
2162 PPC_RFMCI = 0x0400000000000000ULL,
2163 /* rfdi instruction */
2164 PPC_RFDI = 0x0800000000000000ULL,
2165 /* DCR accesses */
2166 PPC_DCR = 0x1000000000000000ULL,
2167 /* DCR extended accesse */
2168 PPC_DCRX = 0x2000000000000000ULL,
2169 /* user-mode DCR access, implemented in PowerPC 460 */
2170 PPC_DCRUX = 0x4000000000000000ULL,
eaabeef2
DG		 2171 /* popcntw and popcntd instructions */
2172 PPC_POPCNTWD = 0x8000000000000000ULL,
01662f3e 2173
005b69fd 2174#define PPC_TCG_INSNS (PPC_INSNS_BASE | PPC_64B \
02d4eae4 2175 | PPC_64BX | PPC_64H | PPC_WAIT | PPC_MFTB \
4537d62d 2176 | PPC_ISEL | PPC_POPCNTB \
02d4eae4
DG		 2177 | PPC_STRING | PPC_FLOAT | PPC_FLOAT_EXT \
2178 | PPC_FLOAT_FSQRT | PPC_FLOAT_FRES \
2179 | PPC_FLOAT_FRSQRTE | PPC_FLOAT_FRSQRTES \
2180 | PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX \
2181 | PPC_ALTIVEC | PPC_SPE | PPC_SPE_SINGLE \
2182 | PPC_SPE_DOUBLE | PPC_MEM_TLBIA \
2183 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC \
2184 | PPC_MEM_SYNC | PPC_MEM_EIEIO \
2185 | PPC_CACHE | PPC_CACHE_ICBI \
8e33944f 2186 | PPC_CACHE_DCBZ \
02d4eae4
DG		 2187 | PPC_CACHE_DCBA | PPC_CACHE_LOCK \
2188 | PPC_EXTERN | PPC_SEGMENT | PPC_6xx_TLB \
a09410ed 2189 | PPC_40x_TLB | PPC_SEGMENT_64B \
02d4eae4
DG		 2190 | PPC_SLBI | PPC_WRTEE | PPC_40x_EXCP \
2191 | PPC_405_MAC | PPC_440_SPEC | PPC_BOOKE \
2192 | PPC_MFAPIDI | PPC_TLBIVA | PPC_TLBIVAX \
2193 | PPC_4xx_COMMON | PPC_40x_ICBT | PPC_RFMCI \
2194 | PPC_RFDI | PPC_DCR | PPC_DCRX | PPC_DCRUX \
b7815375 2195 | PPC_POPCNTWD | PPC_CILDST)
02d4eae4 2196
01662f3e
AG		 2197 /* extended type values */
2198
2199 /* BookE 2.06 PowerPC specification */
2200 PPC2_BOOKE206 = 0x0000000000000001ULL,
a7342588
DG		 2201 /* VSX (extensions to Altivec / VMX) */
2202 PPC2_VSX = 0x0000000000000002ULL,
2203 /* Decimal Floating Point (DFP) */
2204 PPC2_DFP = 0x0000000000000004ULL,
3f9f6a50
AG		 2205 /* Embedded.Processor Control */
2206 PPC2_PRCNTL = 0x0000000000000008ULL,
cd6e9320
TH		 2207 /* Byte-reversed, indexed, double-word load and store */
2208 PPC2_DBRX = 0x0000000000000010ULL,
9c2627b0
AJ		 2209 /* Book I 2.05 PowerPC specification */
2210 PPC2_ISA205 = 0x0000000000000020ULL,
dbcc48fa
TM		 2211 /* VSX additions in ISA 2.07 */
2212 PPC2_VSX207 = 0x0000000000000040ULL,
86ba37ed
TM		 2213 /* ISA 2.06B bpermd */
2214 PPC2_PERM_ISA206 = 0x0000000000000080ULL,
a824bc19
TM		 2215 /* ISA 2.06B divide extended variants */
2216 PPC2_DIVE_ISA206 = 0x0000000000000100ULL,
1fa6c533
TM		 2217 /* ISA 2.06B larx/stcx. instructions */
2218 PPC2_ATOMIC_ISA206 = 0x0000000000000200ULL,
1b0bd002
TM		 2219 /* ISA 2.06B floating point integer conversion */
2220 PPC2_FP_CVT_ISA206 = 0x0000000000000400ULL,
29a0e4e9
TM		 2221 /* ISA 2.06B floating point test instructions */
2222 PPC2_FP_TST_ISA206 = 0x0000000000000800ULL,
94840e07
TM		 2223 /* ISA 2.07 bctar instruction */
2224 PPC2_BCTAR_ISA207 = 0x0000000000001000ULL,
38a85337
TM		 2225 /* ISA 2.07 load/store quadword */
2226 PPC2_LSQ_ISA207 = 0x0000000000002000ULL,
32ea54ab
TM		 2227 /* ISA 2.07 Altivec */
2228 PPC2_ALTIVEC_207 = 0x0000000000004000ULL,
df99d30d
AK		 2229 /* PowerISA 2.07 Book3s specification */
2230 PPC2_ISA207S = 0x0000000000008000ULL,
4171853c
PM		 2231 /* Double precision floating point conversion for signed integer 64 */
2232 PPC2_FP_CVT_S64 = 0x0000000000010000ULL,
f90468b6
TM		 2233 /* Transactional Memory (ISA 2.07, Book II) */
2234 PPC2_TM = 0x0000000000020000ULL,
7778a575
BH		 2235 /* Server PM instructgions (ISA 2.06, Book III) */
2236 PPC2_PM_ISA206 = 0x0000000000040000ULL,
eb640b13
ND		 2237 /* POWER ISA 3.0 */
2238 PPC2_ISA300 = 0x0000000000080000ULL,
ca7a2fda
LP		 2239 /* POWER ISA 3.1 */
2240 PPC2_ISA310 = 0x0000000000100000ULL,
02d4eae4 2241
74f23997 2242#define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX | \
a824bc19 2243 PPC2_ISA205 | PPC2_VSX207 | PPC2_PERM_ISA206 | \
1b0bd002 2244 PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | \
94840e07 2245 PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | \
32ea54ab 2246 PPC2_BCTAR_ISA207 | PPC2_LSQ_ISA207 | \
4171853c 2247 PPC2_ALTIVEC_207 | PPC2_ISA207S | PPC2_DFP | \
eb640b13 2248 PPC2_FP_CVT_S64 | PPC2_TM | PPC2_PM_ISA206 | \
9495edb0 2249 PPC2_ISA300 | PPC2_ISA310)
c29b735c
NF		 2250};
2251
76a66253 2252/*****************************************************************************/
c647e3fe
DG		 2253/*
2254 * Memory access type :
9a64fbe4
FB		 2255 * may be needed for precise access rights control and precise exceptions.
2256 */
79aceca5 2257enum {
9a64fbe4
FB		 2258 /* Type of instruction that generated the access */
2259 ACCESS_CODE = 0x10, /* Code fetch access */
2260 ACCESS_INT = 0x20, /* Integer load/store access */
2261 ACCESS_FLOAT = 0x30, /* floating point load/store access */
2262 ACCESS_RES = 0x40, /* load/store with reservation */
2263 ACCESS_EXT = 0x50, /* external access */
2264 ACCESS_CACHE = 0x60, /* Cache manipulation */
2265};
2266
c647e3fe
DG		 2267/*
2268 * Hardware interrupt sources:
2269 * all those exception can be raised simulteaneously
47103572 2270 */
e9df014c
JM		 2271/* Input pins definitions */
2272enum {
2273 /* 6xx bus input pins */
24be5ae3
JM		 2274 PPC6xx_INPUT_HRESET = 0,
2275 PPC6xx_INPUT_SRESET = 1,
2276 PPC6xx_INPUT_CKSTP_IN = 2,
2277 PPC6xx_INPUT_MCP = 3,
2278 PPC6xx_INPUT_SMI = 4,
2279 PPC6xx_INPUT_INT = 5,
d68f1306
JM		 2280 PPC6xx_INPUT_TBEN = 6,
2281 PPC6xx_INPUT_WAKEUP = 7,
2282 PPC6xx_INPUT_NB,
24be5ae3
JM		 2283};
2284
2285enum {
e9df014c 2286 /* Embedded PowerPC input pins */
24be5ae3
JM		 2287 PPCBookE_INPUT_HRESET = 0,
2288 PPCBookE_INPUT_SRESET = 1,
2289 PPCBookE_INPUT_CKSTP_IN = 2,
2290 PPCBookE_INPUT_MCP = 3,
2291 PPCBookE_INPUT_SMI = 4,
2292 PPCBookE_INPUT_INT = 5,
2293 PPCBookE_INPUT_CINT = 6,
d68f1306 2294 PPCBookE_INPUT_NB,
24be5ae3
JM		 2295};
2296
9fdc60bf
AJ		 2297enum {
2298 /* PowerPC E500 input pins */
2299 PPCE500_INPUT_RESET_CORE = 0,
2300 PPCE500_INPUT_MCK = 1,
2301 PPCE500_INPUT_CINT = 3,
2302 PPCE500_INPUT_INT = 4,
2303 PPCE500_INPUT_DEBUG = 6,
2304 PPCE500_INPUT_NB,
2305};
2306
a750fc0b 2307enum {
4e290a0b
JM		 2308 /* PowerPC 40x input pins */
2309 PPC40x_INPUT_RESET_CORE = 0,
2310 PPC40x_INPUT_RESET_CHIP = 1,
2311 PPC40x_INPUT_RESET_SYS = 2,
2312 PPC40x_INPUT_CINT = 3,
2313 PPC40x_INPUT_INT = 4,
2314 PPC40x_INPUT_HALT = 5,
2315 PPC40x_INPUT_DEBUG = 6,
2316 PPC40x_INPUT_NB,
e9df014c
JM		 2317};
2318
b4095fed
JM		 2319enum {
2320 /* RCPU input pins */
2321 PPCRCPU_INPUT_PORESET = 0,
2322 PPCRCPU_INPUT_HRESET = 1,
2323 PPCRCPU_INPUT_SRESET = 2,
2324 PPCRCPU_INPUT_IRQ0 = 3,
2325 PPCRCPU_INPUT_IRQ1 = 4,
2326 PPCRCPU_INPUT_IRQ2 = 5,
2327 PPCRCPU_INPUT_IRQ3 = 6,
2328 PPCRCPU_INPUT_IRQ4 = 7,
2329 PPCRCPU_INPUT_IRQ5 = 8,
2330 PPCRCPU_INPUT_IRQ6 = 9,
2331 PPCRCPU_INPUT_IRQ7 = 10,
2332 PPCRCPU_INPUT_NB,
2333};
2334
00af685f 2335#if defined(TARGET_PPC64)
d0dfae6e
JM		 2336enum {
2337 /* PowerPC 970 input pins */
2338 PPC970_INPUT_HRESET = 0,
2339 PPC970_INPUT_SRESET = 1,
2340 PPC970_INPUT_CKSTP = 2,
2341 PPC970_INPUT_TBEN = 3,
2342 PPC970_INPUT_MCP = 4,
2343 PPC970_INPUT_INT = 5,
2344 PPC970_INPUT_THINT = 6,
7b62a955 2345 PPC970_INPUT_NB,
9d52e907
DG		 2346};
2347
2348enum {
2349 /* POWER7 input pins */
2350 POWER7_INPUT_INT = 0,
c647e3fe
DG		 2351 /*
2352 * POWER7 probably has other inputs, but we don't care about them
9d52e907 2353 * for any existing machine. We can wire these up when we need
c647e3fe
DG		 2354 * them
2355 */
9d52e907 2356 POWER7_INPUT_NB,
d0dfae6e 2357};
67afe775
BH		 2358
2359enum {
2360 /* POWER9 input pins */
2361 POWER9_INPUT_INT = 0,
2362 POWER9_INPUT_HINT = 1,
2363 POWER9_INPUT_NB,
2364};
00af685f 2365#endif
d0dfae6e 2366
e9df014c 2367/* Hardware exceptions definitions */
47103572 2368enum {
e9df014c 2369 /* External hardware exception sources */
e1833e1f 2370 PPC_INTERRUPT_RESET = 0, /* Reset exception */
d68f1306
JM		 2371 PPC_INTERRUPT_WAKEUP, /* Wakeup exception */
2372 PPC_INTERRUPT_MCK, /* Machine check exception */
2373 PPC_INTERRUPT_EXT, /* External interrupt */
2374 PPC_INTERRUPT_SMI, /* System management interrupt */
2375 PPC_INTERRUPT_CEXT, /* Critical external interrupt */
2376 PPC_INTERRUPT_DEBUG, /* External debug exception */
2377 PPC_INTERRUPT_THERM, /* Thermal exception */
e9df014c 2378 /* Internal hardware exception sources */
d68f1306
JM		 2379 PPC_INTERRUPT_DECR, /* Decrementer exception */
2380 PPC_INTERRUPT_HDECR, /* Hypervisor decrementer exception */
136fbf65 2381 PPC_INTERRUPT_PIT, /* Programmable interval timer interrupt */
d68f1306
JM		 2382 PPC_INTERRUPT_FIT, /* Fixed interval timer interrupt */
2383 PPC_INTERRUPT_WDT, /* Watchdog timer interrupt */
2384 PPC_INTERRUPT_CDOORBELL, /* Critical doorbell interrupt */
2385 PPC_INTERRUPT_DOORBELL, /* Doorbell interrupt */
2386 PPC_INTERRUPT_PERFM, /* Performance monitor interrupt */
136fbf65 2387 PPC_INTERRUPT_HMI, /* Hypervisor Maintenance interrupt */
f03a1af5 2388 PPC_INTERRUPT_HDOORBELL, /* Hypervisor Doorbell interrupt */
d8ce5fd6 2389 PPC_INTERRUPT_HVIRT, /* Hypervisor virtualization interrupt */
cb76bbc4 2390 PPC_INTERRUPT_EBB, /* Event-based Branch exception */
47103572
JM		 2391};
2392
6d9412ea
AK		 2393/* Processor Compatibility mask (PCR) */
2394enum {
a6a444a8
CLG		 2395 PCR_COMPAT_2_05 = PPC_BIT(62),
2396 PCR_COMPAT_2_06 = PPC_BIT(61),
2397 PCR_COMPAT_2_07 = PPC_BIT(60),
2398 PCR_COMPAT_3_00 = PPC_BIT(59),
7d37b274 2399 PCR_COMPAT_3_10 = PPC_BIT(58),
a6a444a8
CLG		 2400 PCR_VEC_DIS = PPC_BIT(0), /* Vec. disable (bit NA since POWER8) */
2401 PCR_VSX_DIS = PPC_BIT(1), /* VSX disable (bit NA since POWER8) */
2402 PCR_TM_DIS = PPC_BIT(2), /* Trans. memory disable (POWER8) */
6d9412ea
AK		 2403};
2404
1488270e
BH		 2405/* HMER/HMEER */
2406enum {
a6a444a8
CLG		 2407 HMER_MALFUNCTION_ALERT = PPC_BIT(0),
2408 HMER_PROC_RECV_DONE = PPC_BIT(2),
2409 HMER_PROC_RECV_ERROR_MASKED = PPC_BIT(3),
2410 HMER_TFAC_ERROR = PPC_BIT(4),
2411 HMER_TFMR_PARITY_ERROR = PPC_BIT(5),
2412 HMER_XSCOM_FAIL = PPC_BIT(8),
2413 HMER_XSCOM_DONE = PPC_BIT(9),
2414 HMER_PROC_RECV_AGAIN = PPC_BIT(11),
2415 HMER_WARN_RISE = PPC_BIT(14),
2416 HMER_WARN_FALL = PPC_BIT(15),
2417 HMER_SCOM_FIR_HMI = PPC_BIT(16),
2418 HMER_TRIG_FIR_HMI = PPC_BIT(17),
2419 HMER_HYP_RESOURCE_ERR = PPC_BIT(20),
2420 HMER_XSCOM_STATUS_MASK = PPC_BITMASK(21, 23),
1488270e
BH		 2421};
2422
9a64fbe4
FB		 2423/*****************************************************************************/
2424
dd09c361 2425#define is_isa300(ctx) (!!(ctx->insns_flags2 & PPC2_ISA300))
10de0521 2426target_ulong cpu_read_xer(const CPUPPCState *env);
00b70788 2427void cpu_write_xer(CPUPPCState *env, target_ulong xer);
da91a00f 2428
d0db7cad
GK		 2429/*
2430 * All 64-bit server processors compliant with arch 2.x, ie. 970 and newer,
2431 * have PPC_SEGMENT_64B.
2432 */
2433#define is_book3s_arch2x(ctx) (!!((ctx)->insns_flags & PPC_SEGMENT_64B))
2434
2da8a6bc
RH		 2435#ifdef CONFIG_DEBUG_TCG
2436void cpu_get_tb_cpu_state(CPUPPCState *env, target_ulong *pc,
2437 target_ulong *cs_base, uint32_t *flags);
2438#else
1328c2bf 2439static inline void cpu_get_tb_cpu_state(CPUPPCState *env, target_ulong *pc,
89fee74a 2440 target_ulong *cs_base, uint32_t *flags)
6b917547
AL		 2441{
2442 *pc = env->nip;
2443 *cs_base = 0;
2444 *flags = env->hflags;
2445}
2da8a6bc 2446#endif
6b917547 2447
8905770b
MAL		 2448G_NORETURN void raise_exception(CPUPPCState *env, uint32_t exception);
2449G_NORETURN void raise_exception_ra(CPUPPCState *env, uint32_t exception,
2450 uintptr_t raddr);
2451G_NORETURN void raise_exception_err(CPUPPCState *env, uint32_t exception,
2452 uint32_t error_code);
2453G_NORETURN void raise_exception_err_ra(CPUPPCState *env, uint32_t exception,
2454 uint32_t error_code, uintptr_t raddr);
db789c6c 2455
d3412df2
DHB		 2456/* PERFM EBB helper*/
2457#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
2458void raise_ebb_perfm_exception(CPUPPCState *env);
2459#endif
2460
01662f3e 2461#if !defined(CONFIG_USER_ONLY)
1328c2bf 2462static inline int booke206_tlbm_id(CPUPPCState *env, ppcmas_tlb_t *tlbm)
01662f3e 2463{
d1e256fe 2464 uintptr_t tlbml = (uintptr_t)tlbm;
1c53accc 2465 uintptr_t tlbl = (uintptr_t)env->tlb.tlbm;
01662f3e 2466
1c53accc 2467 return (tlbml - tlbl) / sizeof(env->tlb.tlbm[0]);
01662f3e
AG		 2468}
2469
1328c2bf 2470static inline int booke206_tlb_size(CPUPPCState *env, int tlbn)
01662f3e
AG		 2471{
2472 uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2473 int r = tlbncfg & TLBnCFG_N_ENTRY;
2474 return r;
2475}
2476
1328c2bf 2477static inline int booke206_tlb_ways(CPUPPCState *env, int tlbn)
01662f3e
AG		 2478{
2479 uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2480 int r = tlbncfg >> TLBnCFG_ASSOC_SHIFT;
2481 return r;
2482}
2483
1328c2bf 2484static inline int booke206_tlbm_to_tlbn(CPUPPCState *env, ppcmas_tlb_t *tlbm)
01662f3e 2485{
d1e256fe 2486 int id = booke206_tlbm_id(env, tlbm);
01662f3e
AG		 2487 int end = 0;
2488 int i;
2489
2490 for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
2491 end += booke206_tlb_size(env, i);
2492 if (id < end) {
2493 return i;
2494 }
2495 }
2496
db70b311 2497 cpu_abort(env_cpu(env), "Unknown TLBe: %d\n", id);
01662f3e
AG		 2498 return 0;
2499}
2500
1328c2bf 2501static inline int booke206_tlbm_to_way(CPUPPCState *env, ppcmas_tlb_t *tlb)
01662f3e 2502{
d1e256fe
AG		 2503 int tlbn = booke206_tlbm_to_tlbn(env, tlb);
2504 int tlbid = booke206_tlbm_id(env, tlb);
01662f3e
AG		 2505 return tlbid & (booke206_tlb_ways(env, tlbn) - 1);
2506}
2507
1328c2bf 2508static inline ppcmas_tlb_t *booke206_get_tlbm(CPUPPCState *env, const int tlbn,
01662f3e
AG		 2509 target_ulong ea, int way)
2510{
2511 int r;
2512 uint32_t ways = booke206_tlb_ways(env, tlbn);
786a4ea8
SH		 2513 int ways_bits = ctz32(ways);
2514 int tlb_bits = ctz32(booke206_tlb_size(env, tlbn));
01662f3e
AG		 2515 int i;
2516
2517 way &= ways - 1;
2518 ea >>= MAS2_EPN_SHIFT;
2519 ea &= (1 << (tlb_bits - ways_bits)) - 1;
2520 r = (ea << ways_bits) | way;
2521
3f162d11
AG		 2522 if (r >= booke206_tlb_size(env, tlbn)) {
2523 return NULL;
2524 }
2525
01662f3e
AG		 2526 /* bump up to tlbn index */
2527 for (i = 0; i < tlbn; i++) {
2528 r += booke206_tlb_size(env, i);
2529 }
2530
1c53accc 2531 return &env->tlb.tlbm[r];
01662f3e
AG		 2532}
2533
a1ef618a 2534/* returns bitmap of supported page sizes for a given TLB */
1328c2bf 2535static inline uint32_t booke206_tlbnps(CPUPPCState *env, const int tlbn)
a1ef618a 2536{
a1ef618a
AG		 2537 uint32_t ret = 0;
2538
3f330293
KF		 2539 if ((env->spr[SPR_MMUCFG] & MMUCFG_MAVN) == MMUCFG_MAVN_V2) {
2540 /* MAV2 */
a1ef618a
AG		 2541 ret = env->spr[SPR_BOOKE_TLB0PS + tlbn];
2542 } else {
2543 uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2544 uint32_t min = (tlbncfg & TLBnCFG_MINSIZE) >> TLBnCFG_MINSIZE_SHIFT;
2545 uint32_t max = (tlbncfg & TLBnCFG_MAXSIZE) >> TLBnCFG_MAXSIZE_SHIFT;
2546 int i;
2547 for (i = min; i <= max; i++) {
2548 ret |= (1 << (i << 1));
2549 }
2550 }
2551
2552 return ret;
2553}
2554
c449d8ba
KF		 2555static inline void booke206_fixed_size_tlbn(CPUPPCState *env, const int tlbn,
2556 ppcmas_tlb_t *tlb)
2557{
2558 uint8_t i;
2559 int32_t tsize = -1;
2560
2561 for (i = 0; i < 32; i++) {
2562 if ((env->spr[SPR_BOOKE_TLB0PS + tlbn]) & (1ULL << i)) {
2563 if (tsize == -1) {
2564 tsize = i;
2565 } else {
2566 return;
2567 }
2568 }
2569 }
2570
2571 /* TLBnPS unimplemented? Odd.. */
2572 assert(tsize != -1);
2573 tlb->mas1 &= ~MAS1_TSIZE_MASK;
2574 tlb->mas1 |= ((uint32_t)tsize) << MAS1_TSIZE_SHIFT;
2575}
2576
01662f3e
AG		 2577#endif
2578
e42a61f1
AG		 2579static inline bool msr_is_64bit(CPUPPCState *env, target_ulong msr)
2580{
2581 if (env->mmu_model == POWERPC_MMU_BOOKE206) {
2582 return msr & (1ULL << MSR_CM);
2583 }
2584
2585 return msr & (1ULL << MSR_SF);
2586}
2587
afbee712
TH		 2588/**
2589 * Check whether register rx is in the range between start and
2590 * start + nregs (as needed by the LSWX and LSWI instructions)
2591 */
2592static inline bool lsw_reg_in_range(int start, int nregs, int rx)
2593{
2594 return (start + nregs <= 32 && rx >= start && rx < start + nregs) ||
2595 (start + nregs > 32 && (rx >= start || rx < start + nregs - 32));
2596}
2597
ef96e3ae 2598/* Accessors for FP, VMX and VSX registers */
e03b5686 2599#if HOST_BIG_ENDIAN
da7815ef
MCA		 2600#define VsrB(i) u8[i]
2601#define VsrSB(i) s8[i]
2602#define VsrH(i) u16[i]
2603#define VsrSH(i) s16[i]
2604#define VsrW(i) u32[i]
2605#define VsrSW(i) s32[i]
2606#define VsrD(i) u64[i]
2607#define VsrSD(i) s64[i]
2608#else
2609#define VsrB(i) u8[15 - (i)]
2610#define VsrSB(i) s8[15 - (i)]
2611#define VsrH(i) u16[7 - (i)]
2612#define VsrSH(i) s16[7 - (i)]
2613#define VsrW(i) u32[3 - (i)]
2614#define VsrSW(i) s32[3 - (i)]
2615#define VsrD(i) u64[1 - (i)]
2616#define VsrSD(i) s64[1 - (i)]
2617#endif
2618
d59d1182 2619static inline int vsr64_offset(int i, bool high)
e7d3b272 2620{
d59d1182 2621 return offsetof(CPUPPCState, vsr[i].VsrD(high ? 0 : 1));
e7d3b272
MCA		 2622}
2623
d59d1182 2624static inline int vsr_full_offset(int i)
ef96e3ae 2625{
d59d1182 2626 return offsetof(CPUPPCState, vsr[i].u64[0]);
ef96e3ae
MCA		 2627}
2628
d59d1182 2629static inline int fpr_offset(int i)
45141dfd 2630{
d59d1182 2631 return vsr64_offset(i, true);
45141dfd
MCA		 2632}
2633
d59d1182 2634static inline uint64_t *cpu_fpr_ptr(CPUPPCState *env, int i)
c82a8a85 2635{
d59d1182 2636 return (uint64_t *)((uintptr_t)env + fpr_offset(i));
c82a8a85
MCA		 2637}
2638
ef96e3ae
MCA		 2639static inline uint64_t *cpu_vsrl_ptr(CPUPPCState *env, int i)
2640{
d59d1182 2641 return (uint64_t *)((uintptr_t)env + vsr64_offset(i, false));
ef96e3ae
MCA		 2642}
2643
37da91f1
MCA		 2644static inline long avr64_offset(int i, bool high)
2645{
d59d1182 2646 return vsr64_offset(i + 32, high);
37da91f1
MCA		 2647}
2648
c82a8a85
MCA		 2649static inline int avr_full_offset(int i)
2650{
2651 return vsr_full_offset(i + 32);
2652}
2653
ef96e3ae
MCA		 2654static inline ppc_avr_t *cpu_avr_ptr(CPUPPCState *env, int i)
2655{
c82a8a85 2656 return (ppc_avr_t *)((uintptr_t)env + avr_full_offset(i));
ef96e3ae
MCA		 2657}
2658
03282a3a
LMC		 2659static inline bool ppc_has_spr(PowerPCCPU *cpu, int spr)
2660{
2661 /* We can test whether the SPR is defined by checking for a valid name */
2662 return cpu->env.spr_cb[spr].name != NULL;
2663}
2664
516fc103
FR		 2665#if !defined(CONFIG_USER_ONLY)
2666static inline bool ppc_interrupts_little_endian(PowerPCCPU *cpu, bool hv)
c11dc15d
GK		 2667{
2668 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
516fc103 2669 CPUPPCState *env = &cpu->env;
2e894848 2670 bool ile;
516fc103
FR		 2671
2672 if (hv && env->has_hv_mode) {
2673 if (is_isa300(pcc)) {
2674 ile = !!(env->spr[SPR_HID0] & HID0_POWER9_HILE);
2675 } else {
2676 ile = !!(env->spr[SPR_HID0] & HID0_HILE);
2677 }
c11dc15d 2678
516fc103
FR		 2679 } else if (pcc->lpcr_mask & LPCR_ILE) {
2680 ile = !!(env->spr[SPR_LPCR] & LPCR_ILE);
2e894848 2681 } else {
3868540f 2682 ile = FIELD_EX64(env->msr, MSR, ILE);
c11dc15d
GK		 2683 }
2684
516fc103 2685 return ile;
c11dc15d 2686}
516fc103 2687#endif
c11dc15d 2688
fad866da 2689void dump_mmu(CPUPPCState *env);
bebabbc7 2690
376dbce0 2691void ppc_maybe_bswap_register(CPUPPCState *env, uint8_t *mem_buf, int len);
c19940db
BL		 2692void ppc_store_vscr(CPUPPCState *env, uint32_t vscr);
2693uint32_t ppc_get_vscr(CPUPPCState *env);
b58fd0c3
FR		 2694
2695/*****************************************************************************/
2696/* Power management enable checks */
2697static inline int check_pow_none(CPUPPCState *env)
2698{
2699 return 0;
2700}
2701
2702static inline int check_pow_nocheck(CPUPPCState *env)
2703{
2704 return 1;
2705}
2706
2707/*****************************************************************************/
2708/* PowerPC implementations definitions */
2709
2710#define POWERPC_FAMILY(_name) \
2711 static void \
2712 glue(glue(ppc_, _name), _cpu_family_class_init)(ObjectClass *, void *); \
2713 \
2714 static const TypeInfo \
2715 glue(glue(ppc_, _name), _cpu_family_type_info) = { \
2716 .name = stringify(_name) "-family-" TYPE_POWERPC_CPU, \
2717 .parent = TYPE_POWERPC_CPU, \
2718 .abstract = true, \
2719 .class_init = glue(glue(ppc_, _name), _cpu_family_class_init), \
2720 }; \
2721 \
2722 static void glue(glue(ppc_, _name), _cpu_family_register_types)(void) \
2723 { \
2724 type_register_static( \
2725 &glue(glue(ppc_, _name), _cpu_family_type_info)); \
2726 } \
2727 \
2728 type_init(glue(glue(ppc_, _name), _cpu_family_register_types)) \
2729 \
2730 static void glue(glue(ppc_, _name), _cpu_family_class_init)
2731
2732
07f5a258 2733#endif /* PPC_CPU_H */
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