]> Git Repo - qemu.git/blame - target/ppc/cpu.h
projects / qemu.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ppc: Move spapr-related prototypes from xics.h into a seperate header file
[qemu.git] / target / ppc / cpu.h
CommitLineData
79aceca5 1/*
3fc6c082 2 * PowerPC emulation cpu definitions for qemu.
5fafdf24 3 *
76a66253 4 * Copyright (c) 2003-2007 Jocelyn Mayer
79aceca5
FB		 5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
8167ee88 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
79aceca5 18 */
07f5a258
MA		 19
20#ifndef PPC_CPU_H
21#define PPC_CPU_H
79aceca5 22
9a78eead 23#include "qemu-common.h"
60caf221 24#include "qemu/int128.h"
3fc6c082 25
a4f30719
JM		 26//#define PPC_EMULATE_32BITS_HYPV
27
76a66253 28#if defined (TARGET_PPC64)
3cd7d1dd 29/* PowerPC 64 definitions */
d9d7210c 30#define TARGET_LONG_BITS 64
35cdaad6 31#define TARGET_PAGE_BITS 12
3cd7d1dd 32
f0b0685d
ND		 33#define TCG_GUEST_DEFAULT_MO 0
34
52705890
RH		 35/* Note that the official physical address space bits is 62-M where M
36 is implementation dependent. I've not looked up M for the set of
37 cpus we emulate at the system level. */
38#define TARGET_PHYS_ADDR_SPACE_BITS 62
39
40/* Note that the PPC environment architecture talks about 80 bit virtual
41 addresses, with segmentation. Obviously that's not all visible to a
42 single process, which is all we're concerned with here. */
43#ifdef TARGET_ABI32
44# define TARGET_VIRT_ADDR_SPACE_BITS 32
45#else
46# define TARGET_VIRT_ADDR_SPACE_BITS 64
47#endif
48
ad3e67d0 49#define TARGET_PAGE_BITS_64K 16
81762d6d
DG		 50#define TARGET_PAGE_BITS_16M 24
51
3cd7d1dd
JM		 52#else /* defined (TARGET_PPC64) */
53/* PowerPC 32 definitions */
d9d7210c 54#define TARGET_LONG_BITS 32
3cd7d1dd 55#define TARGET_PAGE_BITS 12
3cd7d1dd 56
8b242eba 57#define TARGET_PHYS_ADDR_SPACE_BITS 36
52705890
RH		 58#define TARGET_VIRT_ADDR_SPACE_BITS 32
59
3cd7d1dd 60#endif /* defined (TARGET_PPC64) */
3cf1e035 61
9349b4f9 62#define CPUArchState struct CPUPPCState
c2764719 63
022c62cb 64#include "exec/cpu-defs.h"
2d34fe39 65#include "cpu-qom.h"
4ecc3190 66
7f70c937 67#if defined (TARGET_PPC64)
4ecd4d16 68#define PPC_ELF_MACHINE EM_PPC64
76a66253 69#else
4ecd4d16 70#define PPC_ELF_MACHINE EM_PPC
76a66253 71#endif
9042c0e2 72
a7d4b1bf
CLG		 73#define PPC_BIT(bit) (0x8000000000000000ULL >> (bit))
74#define PPC_BIT32(bit) (0x80000000 >> (bit))
75#define PPC_BIT8(bit) (0x80 >> (bit))
2a83f997
CLG		 76#define PPC_BITMASK(bs, be) ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs))
77#define PPC_BITMASK32(bs, be) ((PPC_BIT32(bs) - PPC_BIT32(be)) | \
78 PPC_BIT32(bs))
a6a444a8
CLG		 79#define PPC_BITMASK8(bs, be) ((PPC_BIT8(bs) - PPC_BIT8(be)) | PPC_BIT8(bs))
80
e1833e1f
JM		 81/*****************************************************************************/
82/* Exception vectors definitions */
83enum {
84 POWERPC_EXCP_NONE = -1,
85 /* The 64 first entries are used by the PowerPC embedded specification */
86 POWERPC_EXCP_CRITICAL = 0, /* Critical input */
87 POWERPC_EXCP_MCHECK = 1, /* Machine check exception */
88 POWERPC_EXCP_DSI = 2, /* Data storage exception */
89 POWERPC_EXCP_ISI = 3, /* Instruction storage exception */
90 POWERPC_EXCP_EXTERNAL = 4, /* External input */
91 POWERPC_EXCP_ALIGN = 5, /* Alignment exception */
92 POWERPC_EXCP_PROGRAM = 6, /* Program exception */
93 POWERPC_EXCP_FPU = 7, /* Floating-point unavailable exception */
94 POWERPC_EXCP_SYSCALL = 8, /* System call exception */
95 POWERPC_EXCP_APU = 9, /* Auxiliary processor unavailable */
96 POWERPC_EXCP_DECR = 10, /* Decrementer exception */
97 POWERPC_EXCP_FIT = 11, /* Fixed-interval timer interrupt */
98 POWERPC_EXCP_WDT = 12, /* Watchdog timer interrupt */
b4095fed
JM		 99 POWERPC_EXCP_DTLB = 13, /* Data TLB miss */
100 POWERPC_EXCP_ITLB = 14, /* Instruction TLB miss */
e1833e1f
JM		 101 POWERPC_EXCP_DEBUG = 15, /* Debug interrupt */
102 /* Vectors 16 to 31 are reserved */
e1833e1f
JM		 103 POWERPC_EXCP_SPEU = 32, /* SPE/embedded floating-point unavailable */
104 POWERPC_EXCP_EFPDI = 33, /* Embedded floating-point data interrupt */
105 POWERPC_EXCP_EFPRI = 34, /* Embedded floating-point round interrupt */
106 POWERPC_EXCP_EPERFM = 35, /* Embedded performance monitor interrupt */
107 POWERPC_EXCP_DOORI = 36, /* Embedded doorbell interrupt */
108 POWERPC_EXCP_DOORCI = 37, /* Embedded doorbell critical interrupt */
0ef654e3
AG		 109 POWERPC_EXCP_GDOORI = 38, /* Embedded guest doorbell interrupt */
110 POWERPC_EXCP_GDOORCI = 39, /* Embedded guest doorbell critical interrupt*/
111 POWERPC_EXCP_HYPPRIV = 41, /* Embedded hypervisor priv instruction */
112 /* Vectors 42 to 63 are reserved */
e1833e1f
JM		 113 /* Exceptions defined in the PowerPC server specification */
114 POWERPC_EXCP_RESET = 64, /* System reset exception */
e1833e1f
JM		 115 POWERPC_EXCP_DSEG = 65, /* Data segment exception */
116 POWERPC_EXCP_ISEG = 66, /* Instruction segment exception */
e1833e1f 117 POWERPC_EXCP_HDECR = 67, /* Hypervisor decrementer exception */
e1833e1f 118 POWERPC_EXCP_TRACE = 68, /* Trace exception */
e1833e1f
JM		 119 POWERPC_EXCP_HDSI = 69, /* Hypervisor data storage exception */
120 POWERPC_EXCP_HISI = 70, /* Hypervisor instruction storage exception */
121 POWERPC_EXCP_HDSEG = 71, /* Hypervisor data segment exception */
122 POWERPC_EXCP_HISEG = 72, /* Hypervisor instruction segment exception */
e1833e1f
JM		 123 POWERPC_EXCP_VPU = 73, /* Vector unavailable exception */
124 /* 40x specific exceptions */
125 POWERPC_EXCP_PIT = 74, /* Programmable interval timer interrupt */
126 /* 601 specific exceptions */
127 POWERPC_EXCP_IO = 75, /* IO error exception */
128 POWERPC_EXCP_RUNM = 76, /* Run mode exception */
129 /* 602 specific exceptions */
130 POWERPC_EXCP_EMUL = 77, /* Emulation trap exception */
131 /* 602/603 specific exceptions */
b4095fed 132 POWERPC_EXCP_IFTLB = 78, /* Instruction fetch TLB miss */
e1833e1f
JM		 133 POWERPC_EXCP_DLTLB = 79, /* Data load TLB miss */
134 POWERPC_EXCP_DSTLB = 80, /* Data store TLB miss */
135 /* Exceptions available on most PowerPC */
136 POWERPC_EXCP_FPA = 81, /* Floating-point assist exception */
b4095fed
JM		 137 POWERPC_EXCP_DABR = 82, /* Data address breakpoint */
138 POWERPC_EXCP_IABR = 83, /* Instruction address breakpoint */
139 POWERPC_EXCP_SMI = 84, /* System management interrupt */
140 POWERPC_EXCP_PERFM = 85, /* Embedded performance monitor interrupt */
e1833e1f 141 /* 7xx/74xx specific exceptions */
b4095fed 142 POWERPC_EXCP_THERM = 86, /* Thermal interrupt */
e1833e1f 143 /* 74xx specific exceptions */
b4095fed 144 POWERPC_EXCP_VPUA = 87, /* Vector assist exception */
e1833e1f 145 /* 970FX specific exceptions */
b4095fed
JM		 146 POWERPC_EXCP_SOFTP = 88, /* Soft patch exception */
147 POWERPC_EXCP_MAINT = 89, /* Maintenance exception */
5b46d07d 148 /* Freescale embedded cores specific exceptions */
b4095fed
JM		 149 POWERPC_EXCP_MEXTBR = 90, /* Maskable external breakpoint */
150 POWERPC_EXCP_NMEXTBR = 91, /* Non maskable external breakpoint */
151 POWERPC_EXCP_ITLBE = 92, /* Instruction TLB error */
152 POWERPC_EXCP_DTLBE = 93, /* Data TLB error */
1f29871c
TM		 153 /* VSX Unavailable (Power ISA 2.06 and later) */
154 POWERPC_EXCP_VSXU = 94, /* VSX Unavailable */
7019cb3d 155 POWERPC_EXCP_FU = 95, /* Facility Unavailable */
f03a1af5
BH		 156 /* Additional ISA 2.06 and later server exceptions */
157 POWERPC_EXCP_HV_EMU = 96, /* HV emulation assistance */
158 POWERPC_EXCP_HV_MAINT = 97, /* HMI */
159 POWERPC_EXCP_HV_FU = 98, /* Hypervisor Facility unavailable */
1414c75d
CLG		 160 /* Server doorbell variants */
161 POWERPC_EXCP_SDOOR = 99,
162 POWERPC_EXCP_SDOOR_HV = 100,
e1833e1f 163 /* EOL */
1414c75d 164 POWERPC_EXCP_NB = 101,
5cbdb3a3 165 /* QEMU exceptions: used internally during code translation */
e1833e1f
JM		 166 POWERPC_EXCP_STOP = 0x200, /* stop translation */
167 POWERPC_EXCP_BRANCH = 0x201, /* branch instruction */
5cbdb3a3 168 /* QEMU exceptions: special cases we want to stop translation */
e1833e1f
JM		 169 POWERPC_EXCP_SYNC = 0x202, /* context synchronizing instruction */
170 POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only */
171};
172
e1833e1f
JM		 173/* Exceptions error codes */
174enum {
175 /* Exception subtypes for POWERPC_EXCP_ALIGN */
176 POWERPC_EXCP_ALIGN_FP = 0x01, /* FP alignment exception */
177 POWERPC_EXCP_ALIGN_LST = 0x02, /* Unaligned mult/extern load/store */
178 POWERPC_EXCP_ALIGN_LE = 0x03, /* Multiple little-endian access */
179 POWERPC_EXCP_ALIGN_PROT = 0x04, /* Access cross protection boundary */
180 POWERPC_EXCP_ALIGN_BAT = 0x05, /* Access cross a BAT/seg boundary */
181 POWERPC_EXCP_ALIGN_CACHE = 0x06, /* Impossible dcbz access */
182 /* Exception subtypes for POWERPC_EXCP_PROGRAM */
183 /* FP exceptions */
184 POWERPC_EXCP_FP = 0x10,
185 POWERPC_EXCP_FP_OX = 0x01, /* FP overflow */
186 POWERPC_EXCP_FP_UX = 0x02, /* FP underflow */
187 POWERPC_EXCP_FP_ZX = 0x03, /* FP divide by zero */
188 POWERPC_EXCP_FP_XX = 0x04, /* FP inexact */
7c58044c 189 POWERPC_EXCP_FP_VXSNAN = 0x05, /* FP invalid SNaN op */
e1833e1f
JM		 190 POWERPC_EXCP_FP_VXISI = 0x06, /* FP invalid infinite subtraction */
191 POWERPC_EXCP_FP_VXIDI = 0x07, /* FP invalid infinite divide */
192 POWERPC_EXCP_FP_VXZDZ = 0x08, /* FP invalid zero divide */
193 POWERPC_EXCP_FP_VXIMZ = 0x09, /* FP invalid infinite * zero */
194 POWERPC_EXCP_FP_VXVC = 0x0A, /* FP invalid compare */
195 POWERPC_EXCP_FP_VXSOFT = 0x0B, /* FP invalid operation */
196 POWERPC_EXCP_FP_VXSQRT = 0x0C, /* FP invalid square root */
197 POWERPC_EXCP_FP_VXCVI = 0x0D, /* FP invalid integer conversion */
198 /* Invalid instruction */
199 POWERPC_EXCP_INVAL = 0x20,
200 POWERPC_EXCP_INVAL_INVAL = 0x01, /* Invalid instruction */
201 POWERPC_EXCP_INVAL_LSWX = 0x02, /* Invalid lswx instruction */
202 POWERPC_EXCP_INVAL_SPR = 0x03, /* Invalid SPR access */
203 POWERPC_EXCP_INVAL_FP = 0x04, /* Unimplemented mandatory fp instr */
204 /* Privileged instruction */
205 POWERPC_EXCP_PRIV = 0x30,
206 POWERPC_EXCP_PRIV_OPC = 0x01, /* Privileged operation exception */
207 POWERPC_EXCP_PRIV_REG = 0x02, /* Privileged register exception */
208 /* Trap */
209 POWERPC_EXCP_TRAP = 0x40,
210};
211
a750fc0b 212#define PPC_INPUT(env) (env->bus_model)
3fc6c082 213
be147d08 214/*****************************************************************************/
c227f099 215typedef struct opc_handler_t opc_handler_t;
79aceca5 216
3fc6c082 217/*****************************************************************************/
7222b94a 218/* Types used to describe some PowerPC registers etc. */
69b058c8 219typedef struct DisasContext DisasContext;
c227f099 220typedef struct ppc_spr_t ppc_spr_t;
c227f099 221typedef union ppc_tlb_t ppc_tlb_t;
1ad9f0a4 222typedef struct ppc_hash_pte64 ppc_hash_pte64_t;
76a66253 223
3fc6c082 224/* SPR access micro-ops generations callbacks */
c227f099 225struct ppc_spr_t {
69b058c8
PB		 226 void (*uea_read)(DisasContext *ctx, int gpr_num, int spr_num);
227 void (*uea_write)(DisasContext *ctx, int spr_num, int gpr_num);
76a66253 228#if !defined(CONFIG_USER_ONLY)
69b058c8
PB		 229 void (*oea_read)(DisasContext *ctx, int gpr_num, int spr_num);
230 void (*oea_write)(DisasContext *ctx, int spr_num, int gpr_num);
231 void (*hea_read)(DisasContext *ctx, int gpr_num, int spr_num);
232 void (*hea_write)(DisasContext *ctx, int spr_num, int gpr_num);
76a66253 233#endif
b55266b5 234 const char *name;
d197fdbc 235 target_ulong default_value;
d67d40ea
DG		 236#ifdef CONFIG_KVM
237 /* We (ab)use the fact that all the SPRs will have ids for the
238 * ONE_REG interface will have KVM_REG_PPC to use 0 as meaning,
239 * don't sync this */
240 uint64_t one_reg_id;
241#endif
3fc6c082
FB		 242};
243
05ee3e8a
MCA		 244/* VSX/Altivec registers (128 bits) */
245typedef union _ppc_vsr_t {
a9d9eb8f
JM		 246 uint8_t u8[16];
247 uint16_t u16[8];
248 uint32_t u32[4];
05ee3e8a 249 uint64_t u64[2];
ab5f265d
AJ		 250 int8_t s8[16];
251 int16_t s16[8];
252 int32_t s32[4];
bb527533 253 int64_t s64[2];
05ee3e8a
MCA		 254 float32 f32[4];
255 float64 f64[2];
256 float128 f128;
bb527533
TM		 257#ifdef CONFIG_INT128
258 __uint128_t u128;
259#endif
05ee3e8a
MCA		 260 Int128 s128;
261} ppc_vsr_t;
262
263typedef ppc_vsr_t ppc_avr_t;
9fddaa0c 264
3c7b48b7 265#if !defined(CONFIG_USER_ONLY)
3fc6c082 266/* Software TLB cache */
c227f099
AL		 267typedef struct ppc6xx_tlb_t ppc6xx_tlb_t;
268struct ppc6xx_tlb_t {
76a66253
JM		 269 target_ulong pte0;
270 target_ulong pte1;
271 target_ulong EPN;
1d0a48fb
JM		 272};
273
c227f099
AL		 274typedef struct ppcemb_tlb_t ppcemb_tlb_t;
275struct ppcemb_tlb_t {
b162d02e 276 uint64_t RPN;
1d0a48fb 277 target_ulong EPN;
76a66253 278 target_ulong PID;
c55e9aef
JM		 279 target_ulong size;
280 uint32_t prot;
281 uint32_t attr; /* Storage attributes */
1d0a48fb
JM		 282};
283
d1e256fe
AG		 284typedef struct ppcmas_tlb_t {
285 uint32_t mas8;
286 uint32_t mas1;
287 uint64_t mas2;
288 uint64_t mas7_3;
289} ppcmas_tlb_t;
290
c227f099 291union ppc_tlb_t {
1c53accc
AG		 292 ppc6xx_tlb_t *tlb6;
293 ppcemb_tlb_t *tlbe;
294 ppcmas_tlb_t *tlbm;
3fc6c082 295};
1c53accc
AG		 296
297/* possible TLB variants */
298#define TLB_NONE 0
299#define TLB_6XX 1
300#define TLB_EMB 2
301#define TLB_MAS 3
3c7b48b7 302#endif
3fc6c082 303
b07c59f7
DG		 304typedef struct PPCHash64SegmentPageSizes PPCHash64SegmentPageSizes;
305
c227f099
AL		 306typedef struct ppc_slb_t ppc_slb_t;
307struct ppc_slb_t {
81762d6d
DG		 308 uint64_t esid;
309 uint64_t vsid;
b07c59f7 310 const PPCHash64SegmentPageSizes *sps;
8eee0af9
BS		 311};
312
d83af167 313#define MAX_SLB_ENTRIES 64
81762d6d
DG		 314#define SEGMENT_SHIFT_256M 28
315#define SEGMENT_MASK_256M (~((1ULL << SEGMENT_SHIFT_256M) - 1))
316
cdaee006
DG		 317#define SEGMENT_SHIFT_1T 40
318#define SEGMENT_MASK_1T (~((1ULL << SEGMENT_SHIFT_1T) - 1))
319
320
3fc6c082
FB		 321/*****************************************************************************/
322/* Machine state register bits definition */
76a66253 323#define MSR_SF 63 /* Sixty-four-bit mode hflags */
bd928eba 324#define MSR_TAG 62 /* Tag-active mode (POWERx ?) */
3fc6c082 325#define MSR_ISF 61 /* Sixty-four-bit interrupt mode on 630 */
a4f30719 326#define MSR_SHV 60 /* hypervisor state hflags */
cdcdda27
AK		 327#define MSR_TS0 34 /* Transactional state, 2 bits (Book3s) */
328#define MSR_TS1 33
329#define MSR_TM 32 /* Transactional Memory Available (Book3s) */
363be49c
JM		 330#define MSR_CM 31 /* Computation mode for BookE hflags */
331#define MSR_ICM 30 /* Interrupt computation mode for BookE */
a4f30719 332#define MSR_THV 29 /* hypervisor state for 32 bits PowerPC hflags */
71afeb61 333#define MSR_GS 28 /* guest state for BookE */
363be49c 334#define MSR_UCLE 26 /* User-mode cache lock enable for BookE */
d26bfc9a
JM		 335#define MSR_VR 25 /* altivec available x hflags */
336#define MSR_SPE 25 /* SPE enable for BookE x hflags */
76a66253 337#define MSR_AP 23 /* Access privilege state on 602 hflags */
1f29871c 338#define MSR_VSX 23 /* Vector Scalar Extension (ISA 2.06 and later) x hflags */
76a66253 339#define MSR_SA 22 /* Supervisor access mode on 602 hflags */
3fc6c082 340#define MSR_KEY 19 /* key bit on 603e */
25ba3a68 341#define MSR_POW 18 /* Power management */
d26bfc9a
JM		 342#define MSR_TGPR 17 /* TGPR usage on 602/603 x */
343#define MSR_CE 17 /* Critical interrupt enable on embedded PowerPC x */
3fc6c082
FB		 344#define MSR_ILE 16 /* Interrupt little-endian mode */
345#define MSR_EE 15 /* External interrupt enable */
76a66253
JM		 346#define MSR_PR 14 /* Problem state hflags */
347#define MSR_FP 13 /* Floating point available hflags */
3fc6c082 348#define MSR_ME 12 /* Machine check interrupt enable */
76a66253 349#define MSR_FE0 11 /* Floating point exception mode 0 hflags */
d26bfc9a
JM		 350#define MSR_SE 10 /* Single-step trace enable x hflags */
351#define MSR_DWE 10 /* Debug wait enable on 405 x */
352#define MSR_UBLE 10 /* User BTB lock enable on e500 x */
353#define MSR_BE 9 /* Branch trace enable x hflags */
354#define MSR_DE 9 /* Debug interrupts enable on embedded PowerPC x */
76a66253 355#define MSR_FE1 8 /* Floating point exception mode 1 hflags */
3fc6c082 356#define MSR_AL 7 /* AL bit on POWER */
0411a972 357#define MSR_EP 6 /* Exception prefix on 601 */
3fc6c082 358#define MSR_IR 5 /* Instruction relocate */
3fc6c082 359#define MSR_DR 4 /* Data relocate */
9fb04491
BH		 360#define MSR_IS 5 /* Instruction address space (BookE) */
361#define MSR_DS 4 /* Data address space (BookE) */
25ba3a68 362#define MSR_PE 3 /* Protection enable on 403 */
d26bfc9a
JM		 363#define MSR_PX 2 /* Protection exclusive on 403 x */
364#define MSR_PMM 2 /* Performance monitor mark on POWER x */
365#define MSR_RI 1 /* Recoverable interrupt 1 */
366#define MSR_LE 0 /* Little-endian mode 1 hflags */
0411a972 367
1488270e 368/* LPCR bits */
2a83f997
CLG		 369#define LPCR_VPM0 PPC_BIT(0)
370#define LPCR_VPM1 PPC_BIT(1)
371#define LPCR_ISL PPC_BIT(2)
372#define LPCR_KBV PPC_BIT(3)
88536935 373#define LPCR_DPFD_SHIFT (63 - 11)
7659ca1a 374#define LPCR_DPFD (0x7ull << LPCR_DPFD_SHIFT)
88536935
BH		 375#define LPCR_VRMASD_SHIFT (63 - 16)
376#define LPCR_VRMASD (0x1full << LPCR_VRMASD_SHIFT)
18aa49ec
SJS		 377/* P9: Power-saving mode Exit Cause Enable (Upper Section) Mask */
378#define LPCR_PECE_U_SHIFT (63 - 19)
379#define LPCR_PECE_U_MASK (0x7ull << LPCR_PECE_U_SHIFT)
2a83f997 380#define LPCR_HVEE PPC_BIT(17) /* Hypervisor Virt Exit Enable */
88536935
BH		 381#define LPCR_RMLS_SHIFT (63 - 37)
382#define LPCR_RMLS (0xfull << LPCR_RMLS_SHIFT)
2a83f997 383#define LPCR_ILE PPC_BIT(38)
1488270e
BH		 384#define LPCR_AIL_SHIFT (63 - 40) /* Alternate interrupt location */
385#define LPCR_AIL (3ull << LPCR_AIL_SHIFT)
2a83f997
CLG		 386#define LPCR_UPRT PPC_BIT(41) /* Use Process Table */
387#define LPCR_EVIRT PPC_BIT(42) /* Enhanced Virtualisation */
388#define LPCR_ONL PPC_BIT(45)
389#define LPCR_LD PPC_BIT(46) /* Large Decrementer */
390#define LPCR_P7_PECE0 PPC_BIT(49)
391#define LPCR_P7_PECE1 PPC_BIT(50)
392#define LPCR_P7_PECE2 PPC_BIT(51)
393#define LPCR_P8_PECE0 PPC_BIT(47)
394#define LPCR_P8_PECE1 PPC_BIT(48)
395#define LPCR_P8_PECE2 PPC_BIT(49)
396#define LPCR_P8_PECE3 PPC_BIT(50)
397#define LPCR_P8_PECE4 PPC_BIT(51)
18aa49ec
SJS		 398/* P9: Power-saving mode Exit Cause Enable (Lower Section) Mask */
399#define LPCR_PECE_L_SHIFT (63 - 51)
400#define LPCR_PECE_L_MASK (0x1full << LPCR_PECE_L_SHIFT)
2a83f997
CLG		 401#define LPCR_PDEE PPC_BIT(47) /* Privileged Doorbell Exit EN */
402#define LPCR_HDEE PPC_BIT(48) /* Hyperv Doorbell Exit Enable */
403#define LPCR_EEE PPC_BIT(49) /* External Exit Enable */
404#define LPCR_DEE PPC_BIT(50) /* Decrementer Exit Enable */
405#define LPCR_OEE PPC_BIT(51) /* Other Exit Enable */
406#define LPCR_MER PPC_BIT(52)
407#define LPCR_GTSE PPC_BIT(53) /* Guest Translation Shootdown */
408#define LPCR_TC PPC_BIT(54)
409#define LPCR_HEIC PPC_BIT(59) /* HV Extern Interrupt Control */
410#define LPCR_LPES0 PPC_BIT(60)
411#define LPCR_LPES1 PPC_BIT(61)
412#define LPCR_RMI PPC_BIT(62)
413#define LPCR_HVICE PPC_BIT(62) /* HV Virtualisation Int Enable */
414#define LPCR_HDICE PPC_BIT(63)
1e0c7e55 415
0411a972
JM		 416#define msr_sf ((env->msr >> MSR_SF) & 1)
417#define msr_isf ((env->msr >> MSR_ISF) & 1)
a4f30719 418#define msr_shv ((env->msr >> MSR_SHV) & 1)
0411a972
JM		 419#define msr_cm ((env->msr >> MSR_CM) & 1)
420#define msr_icm ((env->msr >> MSR_ICM) & 1)
a4f30719 421#define msr_thv ((env->msr >> MSR_THV) & 1)
71afeb61 422#define msr_gs ((env->msr >> MSR_GS) & 1)
0411a972
JM		 423#define msr_ucle ((env->msr >> MSR_UCLE) & 1)
424#define msr_vr ((env->msr >> MSR_VR) & 1)
f9320410 425#define msr_spe ((env->msr >> MSR_SPE) & 1)
0411a972 426#define msr_ap ((env->msr >> MSR_AP) & 1)
1f29871c 427#define msr_vsx ((env->msr >> MSR_VSX) & 1)
0411a972
JM		 428#define msr_sa ((env->msr >> MSR_SA) & 1)
429#define msr_key ((env->msr >> MSR_KEY) & 1)
430#define msr_pow ((env->msr >> MSR_POW) & 1)
431#define msr_tgpr ((env->msr >> MSR_TGPR) & 1)
432#define msr_ce ((env->msr >> MSR_CE) & 1)
433#define msr_ile ((env->msr >> MSR_ILE) & 1)
434#define msr_ee ((env->msr >> MSR_EE) & 1)
435#define msr_pr ((env->msr >> MSR_PR) & 1)
436#define msr_fp ((env->msr >> MSR_FP) & 1)
437#define msr_me ((env->msr >> MSR_ME) & 1)
438#define msr_fe0 ((env->msr >> MSR_FE0) & 1)
439#define msr_se ((env->msr >> MSR_SE) & 1)
440#define msr_dwe ((env->msr >> MSR_DWE) & 1)
441#define msr_uble ((env->msr >> MSR_UBLE) & 1)
442#define msr_be ((env->msr >> MSR_BE) & 1)
443#define msr_de ((env->msr >> MSR_DE) & 1)
444#define msr_fe1 ((env->msr >> MSR_FE1) & 1)
445#define msr_al ((env->msr >> MSR_AL) & 1)
446#define msr_ep ((env->msr >> MSR_EP) & 1)
447#define msr_ir ((env->msr >> MSR_IR) & 1)
448#define msr_dr ((env->msr >> MSR_DR) & 1)
9fb04491
BH		 449#define msr_is ((env->msr >> MSR_IS) & 1)
450#define msr_ds ((env->msr >> MSR_DS) & 1)
0411a972
JM		 451#define msr_pe ((env->msr >> MSR_PE) & 1)
452#define msr_px ((env->msr >> MSR_PX) & 1)
453#define msr_pmm ((env->msr >> MSR_PMM) & 1)
454#define msr_ri ((env->msr >> MSR_RI) & 1)
455#define msr_le ((env->msr >> MSR_LE) & 1)
cdcdda27
AK		 456#define msr_ts ((env->msr >> MSR_TS1) & 3)
457#define msr_tm ((env->msr >> MSR_TM) & 1)
458
0e3bf489
RK		 459#define DBCR0_ICMP (1 << 27)
460#define DBCR0_BRT (1 << 26)
461#define DBSR_ICMP (1 << 27)
462#define DBSR_BRT (1 << 26)
463
a4f30719
JM		 464/* Hypervisor bit is more specific */
465#if defined(TARGET_PPC64)
466#define MSR_HVB (1ULL << MSR_SHV)
467#define msr_hv msr_shv
468#else
469#if defined(PPC_EMULATE_32BITS_HYPV)
470#define MSR_HVB (1ULL << MSR_THV)
471#define msr_hv msr_thv
a4f30719
JM		 472#else
473#define MSR_HVB (0ULL)
474#define msr_hv (0)
475#endif
476#endif
79aceca5 477
da82c73a
SJS		 478/* DSISR */
479#define DSISR_NOPTE 0x40000000
480/* Not permitted by access authority of encoded access authority */
481#define DSISR_PROTFAULT 0x08000000
482#define DSISR_ISSTORE 0x02000000
483/* Not permitted by virtual page class key protection */
484#define DSISR_AMR 0x00200000
d5fee0bb
SJS		 485/* Unsupported Radix Tree Configuration */
486#define DSISR_R_BADCONFIG 0x00080000
da82c73a 487
a6152b52
SJS		 488/* SRR1 error code fields */
489
da82c73a
SJS		 490#define SRR1_NOPTE DSISR_NOPTE
491/* Not permitted due to no-execute or guard bit set */
07a68f99 492#define SRR1_NOEXEC_GUARD 0x10000000
da82c73a
SJS		 493#define SRR1_PROTFAULT DSISR_PROTFAULT
494#define SRR1_IAMR DSISR_AMR
a6152b52 495
7019cb3d
AK		 496/* Facility Status and Control (FSCR) bits */
497#define FSCR_EBB (63 - 56) /* Event-Based Branch Facility */
498#define FSCR_TAR (63 - 55) /* Target Address Register */
499/* Interrupt cause mask and position in FSCR. HFSCR has the same format */
500#define FSCR_IC_MASK (0xFFULL)
501#define FSCR_IC_POS (63 - 7)
502#define FSCR_IC_DSCR_SPR3 2
503#define FSCR_IC_PMU 3
504#define FSCR_IC_BHRB 4
505#define FSCR_IC_TM 5
506#define FSCR_IC_EBB 7
507#define FSCR_IC_TAR 8
508
a586e548 509/* Exception state register bits definition */
2a83f997
CLG		 510#define ESR_PIL PPC_BIT(36) /* Illegal Instruction */
511#define ESR_PPR PPC_BIT(37) /* Privileged Instruction */
512#define ESR_PTR PPC_BIT(38) /* Trap */
513#define ESR_FP PPC_BIT(39) /* Floating-Point Operation */
514#define ESR_ST PPC_BIT(40) /* Store Operation */
515#define ESR_AP PPC_BIT(44) /* Auxiliary Processor Operation */
516#define ESR_PUO PPC_BIT(45) /* Unimplemented Operation */
517#define ESR_BO PPC_BIT(46) /* Byte Ordering */
518#define ESR_PIE PPC_BIT(47) /* Imprecise exception */
519#define ESR_DATA PPC_BIT(53) /* Data Access (Embedded page table) */
520#define ESR_TLBI PPC_BIT(54) /* TLB Ineligible (Embedded page table) */
521#define ESR_PT PPC_BIT(55) /* Page Table (Embedded page table) */
522#define ESR_SPV PPC_BIT(56) /* SPE/VMX operation */
523#define ESR_EPID PPC_BIT(57) /* External Process ID operation */
524#define ESR_VLEMI PPC_BIT(58) /* VLE operation */
525#define ESR_MIF PPC_BIT(62) /* Misaligned instruction (VLE) */
a586e548 526
aac86237
TM		 527/* Transaction EXception And Summary Register bits */
528#define TEXASR_FAILURE_PERSISTENT (63 - 7)
529#define TEXASR_DISALLOWED (63 - 8)
530#define TEXASR_NESTING_OVERFLOW (63 - 9)
531#define TEXASR_FOOTPRINT_OVERFLOW (63 - 10)
532#define TEXASR_SELF_INDUCED_CONFLICT (63 - 11)
533#define TEXASR_NON_TRANSACTIONAL_CONFLICT (63 - 12)
534#define TEXASR_TRANSACTION_CONFLICT (63 - 13)
535#define TEXASR_TRANSLATION_INVALIDATION_CONFLICT (63 - 14)
536#define TEXASR_IMPLEMENTATION_SPECIFIC (63 - 15)
537#define TEXASR_INSTRUCTION_FETCH_CONFLICT (63 - 16)
538#define TEXASR_ABORT (63 - 31)
539#define TEXASR_SUSPENDED (63 - 32)
540#define TEXASR_PRIVILEGE_HV (63 - 34)
541#define TEXASR_PRIVILEGE_PR (63 - 35)
542#define TEXASR_FAILURE_SUMMARY (63 - 36)
543#define TEXASR_TFIAR_EXACT (63 - 37)
544#define TEXASR_ROT (63 - 38)
545#define TEXASR_TRANSACTION_LEVEL (63 - 52) /* 12 bits */
546
d26bfc9a 547enum {
4018bae9 548 POWERPC_FLAG_NONE = 0x00000000,
d26bfc9a 549 /* Flag for MSR bit 25 signification (VRE/SPE) */
4018bae9
JM		 550 POWERPC_FLAG_SPE = 0x00000001,
551 POWERPC_FLAG_VRE = 0x00000002,
d26bfc9a 552 /* Flag for MSR bit 17 signification (TGPR/CE) */
4018bae9
JM		 553 POWERPC_FLAG_TGPR = 0x00000004,
554 POWERPC_FLAG_CE = 0x00000008,
d26bfc9a 555 /* Flag for MSR bit 10 signification (SE/DWE/UBLE) */
4018bae9
JM		 556 POWERPC_FLAG_SE = 0x00000010,
557 POWERPC_FLAG_DWE = 0x00000020,
558 POWERPC_FLAG_UBLE = 0x00000040,
d26bfc9a 559 /* Flag for MSR bit 9 signification (BE/DE) */
4018bae9
JM		 560 POWERPC_FLAG_BE = 0x00000080,
561 POWERPC_FLAG_DE = 0x00000100,
a4f30719 562 /* Flag for MSR bit 2 signification (PX/PMM) */
4018bae9
JM		 563 POWERPC_FLAG_PX = 0x00000200,
564 POWERPC_FLAG_PMM = 0x00000400,
565 /* Flag for special features */
566 /* Decrementer clock: RTC clock (POWER, 601) or bus clock */
567 POWERPC_FLAG_RTC_CLK = 0x00010000,
568 POWERPC_FLAG_BUS_CLK = 0x00020000,
697ab892
DG		 569 /* Has CFAR */
570 POWERPC_FLAG_CFAR = 0x00040000,
74f23997
TM		 571 /* Has VSX */
572 POWERPC_FLAG_VSX = 0x00080000,
e43668a7
TM		 573 /* Has Transaction Memory (ISA 2.07) */
574 POWERPC_FLAG_TM = 0x00100000,
d26bfc9a
JM		 575};
576
7c58044c
JM		 577/*****************************************************************************/
578/* Floating point status and control register */
579#define FPSCR_FX 31 /* Floating-point exception summary */
580#define FPSCR_FEX 30 /* Floating-point enabled exception summary */
581#define FPSCR_VX 29 /* Floating-point invalid operation exception summ. */
582#define FPSCR_OX 28 /* Floating-point overflow exception */
583#define FPSCR_UX 27 /* Floating-point underflow exception */
584#define FPSCR_ZX 26 /* Floating-point zero divide exception */
585#define FPSCR_XX 25 /* Floating-point inexact exception */
586#define FPSCR_VXSNAN 24 /* Floating-point invalid operation exception (sNan) */
587#define FPSCR_VXISI 23 /* Floating-point invalid operation exception (inf) */
588#define FPSCR_VXIDI 22 /* Floating-point invalid operation exception (inf) */
589#define FPSCR_VXZDZ 21 /* Floating-point invalid operation exception (zero) */
590#define FPSCR_VXIMZ 20 /* Floating-point invalid operation exception (inf) */
591#define FPSCR_VXVC 19 /* Floating-point invalid operation exception (comp) */
592#define FPSCR_FR 18 /* Floating-point fraction rounded */
593#define FPSCR_FI 17 /* Floating-point fraction inexact */
594#define FPSCR_C 16 /* Floating-point result class descriptor */
595#define FPSCR_FL 15 /* Floating-point less than or negative */
596#define FPSCR_FG 14 /* Floating-point greater than or negative */
597#define FPSCR_FE 13 /* Floating-point equal or zero */
598#define FPSCR_FU 12 /* Floating-point unordered or NaN */
599#define FPSCR_FPCC 12 /* Floating-point condition code */
600#define FPSCR_FPRF 12 /* Floating-point result flags */
601#define FPSCR_VXSOFT 10 /* Floating-point invalid operation exception (soft) */
602#define FPSCR_VXSQRT 9 /* Floating-point invalid operation exception (sqrt) */
603#define FPSCR_VXCVI 8 /* Floating-point invalid operation exception (int) */
604#define FPSCR_VE 7 /* Floating-point invalid operation exception enable */
605#define FPSCR_OE 6 /* Floating-point overflow exception enable */
606#define FPSCR_UE 5 /* Floating-point undeflow exception enable */
607#define FPSCR_ZE 4 /* Floating-point zero divide exception enable */
608#define FPSCR_XE 3 /* Floating-point inexact exception enable */
609#define FPSCR_NI 2 /* Floating-point non-IEEE mode */
610#define FPSCR_RN1 1
611#define FPSCR_RN 0 /* Floating-point rounding control */
612#define fpscr_fex (((env->fpscr) >> FPSCR_FEX) & 0x1)
613#define fpscr_vx (((env->fpscr) >> FPSCR_VX) & 0x1)
614#define fpscr_ox (((env->fpscr) >> FPSCR_OX) & 0x1)
615#define fpscr_ux (((env->fpscr) >> FPSCR_UX) & 0x1)
616#define fpscr_zx (((env->fpscr) >> FPSCR_ZX) & 0x1)
617#define fpscr_xx (((env->fpscr) >> FPSCR_XX) & 0x1)
618#define fpscr_vxsnan (((env->fpscr) >> FPSCR_VXSNAN) & 0x1)
619#define fpscr_vxisi (((env->fpscr) >> FPSCR_VXISI) & 0x1)
620#define fpscr_vxidi (((env->fpscr) >> FPSCR_VXIDI) & 0x1)
621#define fpscr_vxzdz (((env->fpscr) >> FPSCR_VXZDZ) & 0x1)
622#define fpscr_vximz (((env->fpscr) >> FPSCR_VXIMZ) & 0x1)
623#define fpscr_vxvc (((env->fpscr) >> FPSCR_VXVC) & 0x1)
624#define fpscr_fpcc (((env->fpscr) >> FPSCR_FPCC) & 0xF)
625#define fpscr_vxsoft (((env->fpscr) >> FPSCR_VXSOFT) & 0x1)
626#define fpscr_vxsqrt (((env->fpscr) >> FPSCR_VXSQRT) & 0x1)
627#define fpscr_vxcvi (((env->fpscr) >> FPSCR_VXCVI) & 0x1)
628#define fpscr_ve (((env->fpscr) >> FPSCR_VE) & 0x1)
629#define fpscr_oe (((env->fpscr) >> FPSCR_OE) & 0x1)
630#define fpscr_ue (((env->fpscr) >> FPSCR_UE) & 0x1)
631#define fpscr_ze (((env->fpscr) >> FPSCR_ZE) & 0x1)
632#define fpscr_xe (((env->fpscr) >> FPSCR_XE) & 0x1)
633#define fpscr_ni (((env->fpscr) >> FPSCR_NI) & 0x1)
634#define fpscr_rn (((env->fpscr) >> FPSCR_RN) & 0x3)
635/* Invalid operation exception summary */
636#define fpscr_ix ((env->fpscr) & ((1 << FPSCR_VXSNAN) | (1 << FPSCR_VXISI) | \
637 (1 << FPSCR_VXIDI) | (1 << FPSCR_VXZDZ) | \
638 (1 << FPSCR_VXIMZ) | (1 << FPSCR_VXVC) | \
639 (1 << FPSCR_VXSOFT) | (1 << FPSCR_VXSQRT) | \
640 (1 << FPSCR_VXCVI)))
641/* exception summary */
642#define fpscr_ex (((env->fpscr) >> FPSCR_XX) & 0x1F)
643/* enabled exception summary */
644#define fpscr_eex (((env->fpscr) >> FPSCR_XX) & ((env->fpscr) >> FPSCR_XE) & \
645 0x1F)
646
dbdc13a1
MS		 647#define FP_FX (1ull << FPSCR_FX)
648#define FP_FEX (1ull << FPSCR_FEX)
fc03cfef 649#define FP_VX (1ull << FPSCR_VX)
dbdc13a1 650#define FP_OX (1ull << FPSCR_OX)
dbdc13a1 651#define FP_UX (1ull << FPSCR_UX)
dbdc13a1 652#define FP_ZX (1ull << FPSCR_ZX)
fc03cfef 653#define FP_XX (1ull << FPSCR_XX)
dbdc13a1
MS		 654#define FP_VXSNAN (1ull << FPSCR_VXSNAN)
655#define FP_VXISI (1ull << FPSCR_VXISI)
dbdc13a1 656#define FP_VXIDI (1ull << FPSCR_VXIDI)
fc03cfef
JC		 657#define FP_VXZDZ (1ull << FPSCR_VXZDZ)
658#define FP_VXIMZ (1ull << FPSCR_VXIMZ)
dbdc13a1 659#define FP_VXVC (1ull << FPSCR_VXVC)
fc03cfef
JC		 660#define FP_FR (1ull << FSPCR_FR)
661#define FP_FI (1ull << FPSCR_FI)
662#define FP_C (1ull << FPSCR_C)
663#define FP_FL (1ull << FPSCR_FL)
664#define FP_FG (1ull << FPSCR_FG)
665#define FP_FE (1ull << FPSCR_FE)
666#define FP_FU (1ull << FPSCR_FU)
667#define FP_FPCC (FP_FL | FP_FG | FP_FE | FP_FU)
668#define FP_FPRF (FP_C | FP_FL | FP_FG | FP_FE | FP_FU)
669#define FP_VXSOFT (1ull << FPSCR_VXSOFT)
670#define FP_VXSQRT (1ull << FPSCR_VXSQRT)
dbdc13a1
MS		 671#define FP_VXCVI (1ull << FPSCR_VXCVI)
672#define FP_VE (1ull << FPSCR_VE)
fc03cfef
JC		 673#define FP_OE (1ull << FPSCR_OE)
674#define FP_UE (1ull << FPSCR_UE)
675#define FP_ZE (1ull << FPSCR_ZE)
676#define FP_XE (1ull << FPSCR_XE)
677#define FP_NI (1ull << FPSCR_NI)
678#define FP_RN1 (1ull << FPSCR_RN1)
679#define FP_RN (1ull << FPSCR_RN)
dbdc13a1 680
d1277156
JC		 681/* the exception bits which can be cleared by mcrfs - includes FX */
682#define FP_EX_CLEAR_BITS (FP_FX | FP_OX | FP_UX | FP_ZX | \
683 FP_XX | FP_VXSNAN | FP_VXISI | FP_VXIDI | \
684 FP_VXZDZ | FP_VXIMZ | FP_VXVC | FP_VXSOFT | \
685 FP_VXSQRT | FP_VXCVI)
686
7c58044c 687/*****************************************************************************/
6fa724a3
AJ		 688/* Vector status and control register */
689#define VSCR_NJ 16 /* Vector non-java */
690#define VSCR_SAT 0 /* Vector saturation */
691#define vscr_nj (((env->vscr) >> VSCR_NJ) & 0x1)
692#define vscr_sat (((env->vscr) >> VSCR_SAT) & 0x1)
693
01662f3e
AG		 694/*****************************************************************************/
695/* BookE e500 MMU registers */
696
697#define MAS0_NV_SHIFT 0
698#define MAS0_NV_MASK (0xfff << MAS0_NV_SHIFT)
699
700#define MAS0_WQ_SHIFT 12
701#define MAS0_WQ_MASK (3 << MAS0_WQ_SHIFT)
702/* Write TLB entry regardless of reservation */
703#define MAS0_WQ_ALWAYS (0 << MAS0_WQ_SHIFT)
704/* Write TLB entry only already in use */
705#define MAS0_WQ_COND (1 << MAS0_WQ_SHIFT)
706/* Clear TLB entry */
707#define MAS0_WQ_CLR_RSRV (2 << MAS0_WQ_SHIFT)
708
709#define MAS0_HES_SHIFT 14
710#define MAS0_HES (1 << MAS0_HES_SHIFT)
711
712#define MAS0_ESEL_SHIFT 16
713#define MAS0_ESEL_MASK (0xfff << MAS0_ESEL_SHIFT)
714
715#define MAS0_TLBSEL_SHIFT 28
716#define MAS0_TLBSEL_MASK (3 << MAS0_TLBSEL_SHIFT)
717#define MAS0_TLBSEL_TLB0 (0 << MAS0_TLBSEL_SHIFT)
718#define MAS0_TLBSEL_TLB1 (1 << MAS0_TLBSEL_SHIFT)
719#define MAS0_TLBSEL_TLB2 (2 << MAS0_TLBSEL_SHIFT)
720#define MAS0_TLBSEL_TLB3 (3 << MAS0_TLBSEL_SHIFT)
721
722#define MAS0_ATSEL_SHIFT 31
723#define MAS0_ATSEL (1 << MAS0_ATSEL_SHIFT)
724#define MAS0_ATSEL_TLB 0
725#define MAS0_ATSEL_LRAT MAS0_ATSEL
726
2bd9543c
SW		 727#define MAS1_TSIZE_SHIFT 7
728#define MAS1_TSIZE_MASK (0x1f << MAS1_TSIZE_SHIFT)
01662f3e
AG		 729
730#define MAS1_TS_SHIFT 12
731#define MAS1_TS (1 << MAS1_TS_SHIFT)
732
733#define MAS1_IND_SHIFT 13
734#define MAS1_IND (1 << MAS1_IND_SHIFT)
735
736#define MAS1_TID_SHIFT 16
737#define MAS1_TID_MASK (0x3fff << MAS1_TID_SHIFT)
738
739#define MAS1_IPROT_SHIFT 30
740#define MAS1_IPROT (1 << MAS1_IPROT_SHIFT)
741
742#define MAS1_VALID_SHIFT 31
743#define MAS1_VALID 0x80000000
744
745#define MAS2_EPN_SHIFT 12
96091698 746#define MAS2_EPN_MASK (~0ULL << MAS2_EPN_SHIFT)
01662f3e
AG		 747
748#define MAS2_ACM_SHIFT 6
749#define MAS2_ACM (1 << MAS2_ACM_SHIFT)
750
751#define MAS2_VLE_SHIFT 5
752#define MAS2_VLE (1 << MAS2_VLE_SHIFT)
753
754#define MAS2_W_SHIFT 4
755#define MAS2_W (1 << MAS2_W_SHIFT)
756
757#define MAS2_I_SHIFT 3
758#define MAS2_I (1 << MAS2_I_SHIFT)
759
760#define MAS2_M_SHIFT 2
761#define MAS2_M (1 << MAS2_M_SHIFT)
762
763#define MAS2_G_SHIFT 1
764#define MAS2_G (1 << MAS2_G_SHIFT)
765
766#define MAS2_E_SHIFT 0
767#define MAS2_E (1 << MAS2_E_SHIFT)
768
769#define MAS3_RPN_SHIFT 12
770#define MAS3_RPN_MASK (0xfffff << MAS3_RPN_SHIFT)
771
772#define MAS3_U0 0x00000200
773#define MAS3_U1 0x00000100
774#define MAS3_U2 0x00000080
775#define MAS3_U3 0x00000040
776#define MAS3_UX 0x00000020
777#define MAS3_SX 0x00000010
778#define MAS3_UW 0x00000008
779#define MAS3_SW 0x00000004
780#define MAS3_UR 0x00000002
781#define MAS3_SR 0x00000001
782#define MAS3_SPSIZE_SHIFT 1
783#define MAS3_SPSIZE_MASK (0x3e << MAS3_SPSIZE_SHIFT)
784
785#define MAS4_TLBSELD_SHIFT MAS0_TLBSEL_SHIFT
786#define MAS4_TLBSELD_MASK MAS0_TLBSEL_MASK
787#define MAS4_TIDSELD_MASK 0x00030000
788#define MAS4_TIDSELD_PID0 0x00000000
789#define MAS4_TIDSELD_PID1 0x00010000
790#define MAS4_TIDSELD_PID2 0x00020000
791#define MAS4_TIDSELD_PIDZ 0x00030000
792#define MAS4_INDD 0x00008000 /* Default IND */
793#define MAS4_TSIZED_SHIFT MAS1_TSIZE_SHIFT
794#define MAS4_TSIZED_MASK MAS1_TSIZE_MASK
795#define MAS4_ACMD 0x00000040
796#define MAS4_VLED 0x00000020
797#define MAS4_WD 0x00000010
798#define MAS4_ID 0x00000008
799#define MAS4_MD 0x00000004
800#define MAS4_GD 0x00000002
801#define MAS4_ED 0x00000001
802#define MAS4_WIMGED_MASK 0x0000001f /* Default WIMGE */
803#define MAS4_WIMGED_SHIFT 0
804
805#define MAS5_SGS 0x80000000
806#define MAS5_SLPID_MASK 0x00000fff
807
808#define MAS6_SPID0 0x3fff0000
809#define MAS6_SPID1 0x00007ffe
810#define MAS6_ISIZE(x) MAS1_TSIZE(x)
811#define MAS6_SAS 0x00000001
812#define MAS6_SPID MAS6_SPID0
813#define MAS6_SIND 0x00000002 /* Indirect page */
814#define MAS6_SIND_SHIFT 1
815#define MAS6_SPID_MASK 0x3fff0000
816#define MAS6_SPID_SHIFT 16
817#define MAS6_ISIZE_MASK 0x00000f80
818#define MAS6_ISIZE_SHIFT 7
819
820#define MAS7_RPN 0xffffffff
821
822#define MAS8_TGS 0x80000000
823#define MAS8_VF 0x40000000
824#define MAS8_TLBPID 0x00000fff
825
826/* Bit definitions for MMUCFG */
827#define MMUCFG_MAVN 0x00000003 /* MMU Architecture Version Number */
828#define MMUCFG_MAVN_V1 0x00000000 /* v1.0 */
829#define MMUCFG_MAVN_V2 0x00000001 /* v2.0 */
830#define MMUCFG_NTLBS 0x0000000c /* Number of TLBs */
831#define MMUCFG_PIDSIZE 0x000007c0 /* PID Reg Size */
832#define MMUCFG_TWC 0x00008000 /* TLB Write Conditional (v2.0) */
833#define MMUCFG_LRAT 0x00010000 /* LRAT Supported (v2.0) */
834#define MMUCFG_RASIZE 0x00fe0000 /* Real Addr Size */
835#define MMUCFG_LPIDSIZE 0x0f000000 /* LPID Reg Size */
836
837/* Bit definitions for MMUCSR0 */
838#define MMUCSR0_TLB1FI 0x00000002 /* TLB1 Flash invalidate */
839#define MMUCSR0_TLB0FI 0x00000004 /* TLB0 Flash invalidate */
840#define MMUCSR0_TLB2FI 0x00000040 /* TLB2 Flash invalidate */
841#define MMUCSR0_TLB3FI 0x00000020 /* TLB3 Flash invalidate */
842#define MMUCSR0_TLBFI (MMUCSR0_TLB0FI | MMUCSR0_TLB1FI | \
843 MMUCSR0_TLB2FI | MMUCSR0_TLB3FI)
844#define MMUCSR0_TLB0PS 0x00000780 /* TLB0 Page Size */
845#define MMUCSR0_TLB1PS 0x00007800 /* TLB1 Page Size */
846#define MMUCSR0_TLB2PS 0x00078000 /* TLB2 Page Size */
847#define MMUCSR0_TLB3PS 0x00780000 /* TLB3 Page Size */
848
849/* TLBnCFG encoding */
850#define TLBnCFG_N_ENTRY 0x00000fff /* number of entries */
851#define TLBnCFG_HES 0x00002000 /* HW select supported */
852#define TLBnCFG_AVAIL 0x00004000 /* variable page size */
853#define TLBnCFG_IPROT 0x00008000 /* IPROT supported */
854#define TLBnCFG_GTWE 0x00010000 /* Guest can write */
855#define TLBnCFG_IND 0x00020000 /* IND entries supported */
856#define TLBnCFG_PT 0x00040000 /* Can load from page table */
857#define TLBnCFG_MINSIZE 0x00f00000 /* Minimum Page Size (v1.0) */
858#define TLBnCFG_MINSIZE_SHIFT 20
859#define TLBnCFG_MAXSIZE 0x000f0000 /* Maximum Page Size (v1.0) */
860#define TLBnCFG_MAXSIZE_SHIFT 16
861#define TLBnCFG_ASSOC 0xff000000 /* Associativity */
862#define TLBnCFG_ASSOC_SHIFT 24
863
864/* TLBnPS encoding */
865#define TLBnPS_4K 0x00000004
866#define TLBnPS_8K 0x00000008
867#define TLBnPS_16K 0x00000010
868#define TLBnPS_32K 0x00000020
869#define TLBnPS_64K 0x00000040
870#define TLBnPS_128K 0x00000080
871#define TLBnPS_256K 0x00000100
872#define TLBnPS_512K 0x00000200
873#define TLBnPS_1M 0x00000400
874#define TLBnPS_2M 0x00000800
875#define TLBnPS_4M 0x00001000
876#define TLBnPS_8M 0x00002000
877#define TLBnPS_16M 0x00004000
878#define TLBnPS_32M 0x00008000
879#define TLBnPS_64M 0x00010000
880#define TLBnPS_128M 0x00020000
881#define TLBnPS_256M 0x00040000
882#define TLBnPS_512M 0x00080000
883#define TLBnPS_1G 0x00100000
884#define TLBnPS_2G 0x00200000
885#define TLBnPS_4G 0x00400000
886#define TLBnPS_8G 0x00800000
887#define TLBnPS_16G 0x01000000
888#define TLBnPS_32G 0x02000000
889#define TLBnPS_64G 0x04000000
890#define TLBnPS_128G 0x08000000
891#define TLBnPS_256G 0x10000000
892
893/* tlbilx action encoding */
894#define TLBILX_T_ALL 0
895#define TLBILX_T_TID 1
896#define TLBILX_T_FULLMATCH 3
897#define TLBILX_T_CLASS0 4
898#define TLBILX_T_CLASS1 5
899#define TLBILX_T_CLASS2 6
900#define TLBILX_T_CLASS3 7
901
902/* BookE 2.06 helper defines */
903
904#define BOOKE206_FLUSH_TLB0 (1 << 0)
905#define BOOKE206_FLUSH_TLB1 (1 << 1)
906#define BOOKE206_FLUSH_TLB2 (1 << 2)
907#define BOOKE206_FLUSH_TLB3 (1 << 3)
908
909/* number of possible TLBs */
910#define BOOKE206_MAX_TLBN 4
911
50728199
RK		 912#define EPID_EPID_SHIFT 0x0
913#define EPID_EPID 0xFF
914#define EPID_ELPID_SHIFT 0x10
915#define EPID_ELPID 0x3F0000
916#define EPID_EGS 0x20000000
917#define EPID_EGS_SHIFT 29
918#define EPID_EAS 0x40000000
919#define EPID_EAS_SHIFT 30
920#define EPID_EPR 0x80000000
921#define EPID_EPR_SHIFT 31
922/* We don't support EGS and ELPID */
923#define EPID_MASK (EPID_EPID | EPID_EAS | EPID_EPR)
924
58e00a24 925/*****************************************************************************/
7af1e7b0 926/* Server and Embedded Processor Control */
58e00a24
AG		 927
928#define DBELL_TYPE_SHIFT 27
929#define DBELL_TYPE_MASK (0x1f << DBELL_TYPE_SHIFT)
930#define DBELL_TYPE_DBELL (0x00 << DBELL_TYPE_SHIFT)
931#define DBELL_TYPE_DBELL_CRIT (0x01 << DBELL_TYPE_SHIFT)
932#define DBELL_TYPE_G_DBELL (0x02 << DBELL_TYPE_SHIFT)
933#define DBELL_TYPE_G_DBELL_CRIT (0x03 << DBELL_TYPE_SHIFT)
934#define DBELL_TYPE_G_DBELL_MC (0x04 << DBELL_TYPE_SHIFT)
935
7af1e7b0
CLG		 936#define DBELL_TYPE_DBELL_SERVER (0x05 << DBELL_TYPE_SHIFT)
937
938#define DBELL_BRDCAST PPC_BIT(37)
58e00a24
AG		 939#define DBELL_LPIDTAG_SHIFT 14
940#define DBELL_LPIDTAG_MASK (0xfff << DBELL_LPIDTAG_SHIFT)
941#define DBELL_PIRTAG_MASK 0x3fff
942
7af1e7b0
CLG		 943#define DBELL_PROCIDTAG_MASK PPC_BITMASK(44, 63)
944
4656e1f0
BH		 945#define PPC_PAGE_SIZES_MAX_SZ 8
946
c64abd1f
SB		 947struct ppc_radix_page_info {
948 uint32_t count;
949 uint32_t entries[PPC_PAGE_SIZES_MAX_SZ];
950};
4656e1f0 951
6fa724a3 952/*****************************************************************************/
7c58044c 953/* The whole PowerPC CPU context */
50728199
RK		 954
955/* PowerPC needs eight modes for different hypervisor/supervisor/guest +
956 * real/paged mode combinations. The other two modes are for external PID
957 * load/store.
958 */
959#define NB_MMU_MODES 10
960#define MMU_MODE8_SUFFIX _epl
961#define MMU_MODE9_SUFFIX _eps
962#define PPC_TLB_EPID_LOAD 8
963#define PPC_TLB_EPID_STORE 9
6ebbf390 964
54ff58bb
BR		 965#define PPC_CPU_OPCODES_LEN 0x40
966#define PPC_CPU_INDIRECT_OPCODES_LEN 0x20
b048960f 967
3fc6c082
FB		 968struct CPUPPCState {
969 /* First are the most commonly used resources
970 * during translated code execution
971 */
79aceca5 972 /* general purpose registers */
bd7d9a6d 973 target_ulong gpr[32];
3cd7d1dd 974 /* Storage for GPR MSB, used by the SPE extension */
bd7d9a6d 975 target_ulong gprh[32];
3fc6c082
FB		 976 /* LR */
977 target_ulong lr;
978 /* CTR */
979 target_ulong ctr;
980 /* condition register */
47e4661c 981 uint32_t crf[8];
697ab892
DG		 982#if defined(TARGET_PPC64)
983 /* CFAR */
984 target_ulong cfar;
985#endif
da91a00f 986 /* XER (with SO, OV, CA split out) */
3d7b417e 987 target_ulong xer;
da91a00f
RH		 988 target_ulong so;
989 target_ulong ov;
990 target_ulong ca;
dd09c361
ND		 991 target_ulong ov32;
992 target_ulong ca32;
79aceca5 993 /* Reservation address */
18b21a2f
NF		 994 target_ulong reserve_addr;
995 /* Reservation value */
996 target_ulong reserve_val;
9c294d5a 997 target_ulong reserve_val2;
3fc6c082
FB		 998
999 /* Those ones are used in supervisor mode only */
79aceca5 1000 /* machine state register */
0411a972 1001 target_ulong msr;
3fc6c082 1002 /* temporary general purpose registers */
bd7d9a6d 1003 target_ulong tgpr[4]; /* Used to speed-up TLB assist handlers */
3fc6c082
FB		 1004
1005 /* Floating point execution context */
4ecc3190 1006 float_status fp_status;
3fc6c082 1007 /* floating point status and control register */
30304420 1008 target_ulong fpscr;
4ecc3190 1009
cb2dbfc3
AJ		 1010 /* Next instruction pointer */
1011 target_ulong nip;
a316d335 1012
94bf2658
RH		 1013 /* High part of 128-bit helper return. */
1014 uint64_t retxh;
1015
ac9eb073
FB		 1016 int access_type; /* when a memory exception occurs, the access
1017 type is stored here */
a541f297 1018
cb2dbfc3
AJ		 1019 CPU_COMMON
1020
f2e63a42
JM		 1021 /* MMU context - only relevant for full system emulation */
1022#if !defined(CONFIG_USER_ONLY)
1023#if defined(TARGET_PPC64)
f2e63a42 1024 /* PowerPC 64 SLB area */
d83af167 1025 ppc_slb_t slb[MAX_SLB_ENTRIES];
cd0c6f47 1026 /* tcg TLB needs flush (deferred slb inval instruction typically) */
f2e63a42 1027#endif
3fc6c082 1028 /* segment registers */
74d37793 1029 target_ulong sr[32];
3fc6c082 1030 /* BATs */
a90db158 1031 uint32_t nb_BATs;
3fc6c082
FB		 1032 target_ulong DBAT[2][8];
1033 target_ulong IBAT[2][8];
01662f3e 1034 /* PowerPC TLB registers (for 4xx, e500 and 60x software driven TLBs) */
a90db158 1035 int32_t nb_tlb; /* Total number of TLB */
f2e63a42
JM		 1036 int tlb_per_way; /* Speed-up helper: used to avoid divisions at run time */
1037 int nb_ways; /* Number of ways in the TLB set */
1038 int last_way; /* Last used way used to allocate TLB in a LRU way */
1039 int id_tlbs; /* If 1, MMU has separated TLBs for instructions & data */
1040 int nb_pids; /* Number of available PID registers */
1c53accc
AG		 1041 int tlb_type; /* Type of TLB we're dealing with */
1042 ppc_tlb_t tlb; /* TLB is optional. Allocate them only if needed */
f2e63a42
JM		 1043 /* 403 dedicated access protection registers */
1044 target_ulong pb[4];
93dd5e85
SW		 1045 bool tlb_dirty; /* Set to non-zero when modifying TLB */
1046 bool kvm_sw_tlb; /* non-zero if KVM SW TLB API is active */
c5a8d8f3 1047 uint32_t tlb_need_flush; /* Delayed flush needed */
a8a6d53e 1048#define TLB_NEED_LOCAL_FLUSH 0x1
d76ab5e1 1049#define TLB_NEED_GLOBAL_FLUSH 0x2
f2e63a42 1050#endif
9fddaa0c 1051
3fc6c082
FB		 1052 /* Other registers */
1053 /* Special purpose registers */
1054 target_ulong spr[1024];
c227f099 1055 ppc_spr_t spr_cb[1024];
ef96e3ae 1056 /* Vector status and control register */
3fc6c082 1057 uint32_t vscr;
ef96e3ae
MCA		 1058 /* VSX registers (including FP and AVR) */
1059 ppc_vsr_t vsr[64] QEMU_ALIGNED(16);
d9bce9d9 1060 /* SPE registers */
2231ef10 1061 uint64_t spe_acc;
d9bce9d9 1062 uint32_t spe_fscr;
fbd265b6
AJ		 1063 /* SPE and Altivec can share a status since they will never be used
1064 * simultaneously */
1065 float_status vec_status;
3fc6c082
FB		 1066
1067 /* Internal devices resources */
9fddaa0c 1068 /* Time base and decrementer */
c227f099 1069 ppc_tb_t *tb_env;
3fc6c082 1070 /* Device control registers */
c227f099 1071 ppc_dcr_t *dcr_env;
3fc6c082 1072
d63001d1
JM		 1073 int dcache_line_size;
1074 int icache_line_size;
1075
3fc6c082
FB		 1076 /* Those resources are used during exception processing */
1077 /* CPU model definition */
a750fc0b 1078 target_ulong msr_mask;
c227f099
AL		 1079 powerpc_mmu_t mmu_model;
1080 powerpc_excp_t excp_model;
1081 powerpc_input_t bus_model;
237c0af0 1082 int bfd_mach;
3fc6c082 1083 uint32_t flags;
c29b735c 1084 uint64_t insns_flags;
a5858d7a 1085 uint64_t insns_flags2;
4656e1f0 1086#if defined(TARGET_PPC64)
912acdf4
BH		 1087 ppc_slb_t vrma_slb;
1088 target_ulong rmls;
4656e1f0 1089#endif
3fc6c082 1090
3fc6c082 1091 int error_code;
47103572 1092 uint32_t pending_interrupts;
e9df014c 1093#if !defined(CONFIG_USER_ONLY)
4abf79a4 1094 /* This is the IRQ controller, which is implementation dependent
e9df014c
JM		 1095 * and only relevant when emulating a complete machine.
1096 */
1097 uint32_t irq_input_state;
1098 void **irq_inputs;
e1833e1f
JM		 1099 /* Exception vectors */
1100 target_ulong excp_vectors[POWERPC_EXCP_NB];
1101 target_ulong excp_prefix;
1102 target_ulong ivor_mask;
1103 target_ulong ivpr_mask;
d63001d1 1104 target_ulong hreset_vector;
68c2dd70
AG		 1105 hwaddr mpic_iack;
1106 /* true when the external proxy facility mode is enabled */
1107 bool mpic_proxy;
932ccbdd
BH		 1108 /* set when the processor has an HV mode, thus HV priv
1109 * instructions and SPRs are diallowed if MSR:HV is 0
1110 */
1111 bool has_hv_mode;
7778a575
BH		 1112 /* On P7/P8, set when in PM state, we need to handle resume
1113 * in a special way (such as routing some resume causes to
1114 * 0x100), so flag this here.
1115 */
1116 bool in_pm_state;
e9df014c 1117#endif
3fc6c082
FB		 1118
1119 /* Those resources are used only during code translation */
3fc6c082 1120 /* opcode handlers */
b048960f 1121 opc_handler_t *opcodes[PPC_CPU_OPCODES_LEN];
3fc6c082 1122
5cbdb3a3 1123 /* Those resources are used only in QEMU core */
056401ea 1124 target_ulong hflags; /* hflags is a MSR & HFLAGS_MASK */
4abf79a4 1125 target_ulong hflags_nmsr; /* specific hflags, not coming from MSR */
9fb04491
BH		 1126 int immu_idx; /* precomputed MMU index to speed up insn access */
1127 int dmmu_idx; /* precomputed MMU index to speed up data accesses */
3fc6c082 1128
9fddaa0c 1129 /* Power management */
cd346349 1130 int (*check_pow)(CPUPPCState *env);
a541f297 1131
2c50e26e
EI		 1132#if !defined(CONFIG_USER_ONLY)
1133 void *load_info; /* Holds boot loading state. */
1134#endif
ddd1055b
FC		 1135
1136 /* booke timers */
1137
1138 /* Specifies bit locations of the Time Base used to signal a fixed timer
1139 * exception on a transition from 0 to 1. (watchdog or fixed-interval timer)
1140 *
1141 * 0 selects the least significant bit.
1142 * 63 selects the most significant bit.
1143 */
1144 uint8_t fit_period[4];
1145 uint8_t wdt_period[4];
80b3f79b
AK		 1146
1147 /* Transactional memory state */
1148 target_ulong tm_gpr[32];
1149 ppc_avr_t tm_vsr[64];
1150 uint64_t tm_cr;
1151 uint64_t tm_lr;
1152 uint64_t tm_ctr;
1153 uint64_t tm_fpscr;
1154 uint64_t tm_amr;
1155 uint64_t tm_ppr;
1156 uint64_t tm_vrsave;
1157 uint32_t tm_vscr;
1158 uint64_t tm_dscr;
1159 uint64_t tm_tar;
3fc6c082 1160};
79aceca5 1161
ddd1055b
FC		 1162#define SET_FIT_PERIOD(a_, b_, c_, d_) \
1163do { \
1164 env->fit_period[0] = (a_); \
1165 env->fit_period[1] = (b_); \
1166 env->fit_period[2] = (c_); \
1167 env->fit_period[3] = (d_); \
1168 } while (0)
1169
1170#define SET_WDT_PERIOD(a_, b_, c_, d_) \
1171do { \
1172 env->wdt_period[0] = (a_); \
1173 env->wdt_period[1] = (b_); \
1174 env->wdt_period[2] = (c_); \
1175 env->wdt_period[3] = (d_); \
1176 } while (0)
1177
1d1be34d
DG		 1178typedef struct PPCVirtualHypervisor PPCVirtualHypervisor;
1179typedef struct PPCVirtualHypervisorClass PPCVirtualHypervisorClass;
129dbe69 1180typedef struct XiveTCTX XiveTCTX;
3ff73aa2 1181typedef struct ICPState ICPState;
1d1be34d 1182
2d34fe39
PB		 1183/**
1184 * PowerPCCPU:
1185 * @env: #CPUPPCState
81210c20 1186 * @vcpu_id: vCPU identifier given to KVM
d6e166c0 1187 * @compat_pvr: Current logical PVR, zero if in "raw" mode
2d34fe39
PB		 1188 *
1189 * A PowerPC CPU.
1190 */
1191struct PowerPCCPU {
1192 /*< private >*/
1193 CPUState parent_obj;
1194 /*< public >*/
1195
1196 CPUPPCState env;
81210c20 1197 int vcpu_id;
d6e166c0 1198 uint32_t compat_pvr;
1d1be34d 1199 PPCVirtualHypervisor *vhyp;
3ff73aa2 1200 ICPState *icp;
129dbe69 1201 XiveTCTX *tctx;
7388efaf 1202 void *machine_data;
15f8b142 1203 int32_t node_id; /* NUMA node this CPU belongs to */
b07c59f7 1204 PPCHash64Options *hash64_opts;
16a2497b 1205
146c11f1
DG		 1206 /* Fields related to migration compatibility hacks */
1207 bool pre_2_8_migration;
16a2497b
DG		 1208 target_ulong mig_msr_mask;
1209 uint64_t mig_insns_flags;
1210 uint64_t mig_insns_flags2;
1211 uint32_t mig_nb_BATs;
d5fc133e 1212 bool pre_2_10_migration;
d8c0c7af 1213 bool pre_3_0_migration;
67d7d66f 1214 int32_t mig_slb_nr;
2d34fe39
PB		 1215};
1216
1217static inline PowerPCCPU *ppc_env_get_cpu(CPUPPCState *env)
1218{
1219 return container_of(env, PowerPCCPU, env);
1220}
1221
1222#define ENV_GET_CPU(e) CPU(ppc_env_get_cpu(e))
1223
1224#define ENV_OFFSET offsetof(PowerPCCPU, env)
1225
1226PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr);
1227PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr);
e9edd931 1228PowerPCCPUClass *ppc_cpu_get_family_class(PowerPCCPUClass *pcc);
2d34fe39 1229
1d1be34d
DG		 1230struct PPCVirtualHypervisor {
1231 Object parent;
1232};
1233
1234struct PPCVirtualHypervisorClass {
1235 InterfaceClass parent;
1236 void (*hypercall)(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu);
e57ca75c
DG		 1237 hwaddr (*hpt_mask)(PPCVirtualHypervisor *vhyp);
1238 const ppc_hash_pte64_t *(*map_hptes)(PPCVirtualHypervisor *vhyp,
1239 hwaddr ptex, int n);
1240 void (*unmap_hptes)(PPCVirtualHypervisor *vhyp,
1241 const ppc_hash_pte64_t *hptes,
1242 hwaddr ptex, int n);
1243 void (*store_hpte)(PPCVirtualHypervisor *vhyp, hwaddr ptex,
1244 uint64_t pte0, uint64_t pte1);
9861bb3e 1245 uint64_t (*get_patbe)(PPCVirtualHypervisor *vhyp);
1ec26c75 1246 target_ulong (*encode_hpt_for_kvm_pr)(PPCVirtualHypervisor *vhyp);
1d1be34d
DG		 1247};
1248
1249#define TYPE_PPC_VIRTUAL_HYPERVISOR "ppc-virtual-hypervisor"
1250#define PPC_VIRTUAL_HYPERVISOR(obj) \
1251 OBJECT_CHECK(PPCVirtualHypervisor, (obj), TYPE_PPC_VIRTUAL_HYPERVISOR)
1252#define PPC_VIRTUAL_HYPERVISOR_CLASS(klass) \
1253 OBJECT_CLASS_CHECK(PPCVirtualHypervisorClass, (klass), \
1254 TYPE_PPC_VIRTUAL_HYPERVISOR)
1255#define PPC_VIRTUAL_HYPERVISOR_GET_CLASS(obj) \
1256 OBJECT_GET_CLASS(PPCVirtualHypervisorClass, (obj), \
1257 TYPE_PPC_VIRTUAL_HYPERVISOR)
1258
2d34fe39
PB		 1259void ppc_cpu_do_interrupt(CPUState *cpu);
1260bool ppc_cpu_exec_interrupt(CPUState *cpu, int int_req);
1261void ppc_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
1262 int flags);
1263void ppc_cpu_dump_statistics(CPUState *cpu, FILE *f,
1264 fprintf_function cpu_fprintf, int flags);
2d34fe39
PB		 1265hwaddr ppc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
1266int ppc_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
1267int ppc_cpu_gdb_read_register_apple(CPUState *cpu, uint8_t *buf, int reg);
1268int ppc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
1269int ppc_cpu_gdb_write_register_apple(CPUState *cpu, uint8_t *buf, int reg);
1270int ppc64_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
1271 int cpuid, void *opaque);
356bb70e
MN		 1272int ppc32_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
1273 int cpuid, void *opaque);
2d34fe39
PB		 1274#ifndef CONFIG_USER_ONLY
1275void ppc_cpu_do_system_reset(CPUState *cs);
1276extern const struct VMStateDescription vmstate_ppc_cpu;
1277#endif
1d0cb67d 1278
3fc6c082 1279/*****************************************************************************/
2e70f6ef 1280void ppc_translate_init(void);
79aceca5
FB		 1281/* you can call this signal handler from your SIGBUS and SIGSEGV
1282 signal handlers to inform the virtual CPU of exceptions. non zero
1283 is returned if the signal was handled by the virtual CPU. */
36081602
JM		 1284int cpu_ppc_signal_handler (int host_signum, void *pinfo,
1285 void *puc);
cc8eae8a 1286#if defined(CONFIG_USER_ONLY)
98670d47 1287int ppc_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int rw,
7510454e 1288 int mmu_idx);
cc8eae8a 1289#endif
a541f297 1290
76a66253 1291#if !defined(CONFIG_USER_ONLY)
45d827d2 1292void ppc_store_sdr1 (CPUPPCState *env, target_ulong value);
4a7518e0 1293void ppc_store_ptcr(CPUPPCState *env, target_ulong value);
12de9a39 1294#endif /* !defined(CONFIG_USER_ONLY) */
0411a972 1295void ppc_store_msr (CPUPPCState *env, target_ulong value);
3fc6c082 1296
9a78eead 1297void ppc_cpu_list (FILE *f, fprintf_function cpu_fprintf);
aaed909a 1298
9fddaa0c
FB		 1299/* Time-base and decrementer management */
1300#ifndef NO_CPU_IO_DEFS
e3ea6529 1301uint64_t cpu_ppc_load_tbl (CPUPPCState *env);
9fddaa0c
FB		 1302uint32_t cpu_ppc_load_tbu (CPUPPCState *env);
1303void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value);
1304void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value);
b711de95 1305uint64_t cpu_ppc_load_atbl (CPUPPCState *env);
a062e36c
JM		 1306uint32_t cpu_ppc_load_atbu (CPUPPCState *env);
1307void cpu_ppc_store_atbl (CPUPPCState *env, uint32_t value);
1308void cpu_ppc_store_atbu (CPUPPCState *env, uint32_t value);
e81a982a 1309bool ppc_decr_clear_on_delivery(CPUPPCState *env);
9fddaa0c
FB		 1310uint32_t cpu_ppc_load_decr (CPUPPCState *env);
1311void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value);
58a7d328
JM		 1312uint32_t cpu_ppc_load_hdecr (CPUPPCState *env);
1313void cpu_ppc_store_hdecr (CPUPPCState *env, uint32_t value);
1314uint64_t cpu_ppc_load_purr (CPUPPCState *env);
d9bce9d9
JM		 1315uint32_t cpu_ppc601_load_rtcl (CPUPPCState *env);
1316uint32_t cpu_ppc601_load_rtcu (CPUPPCState *env);
1317#if !defined(CONFIG_USER_ONLY)
1318void cpu_ppc601_store_rtcl (CPUPPCState *env, uint32_t value);
1319void cpu_ppc601_store_rtcu (CPUPPCState *env, uint32_t value);
1320target_ulong load_40x_pit (CPUPPCState *env);
1321void store_40x_pit (CPUPPCState *env, target_ulong val);
8ecc7913 1322void store_40x_dbcr0 (CPUPPCState *env, uint32_t val);
c294fc58 1323void store_40x_sler (CPUPPCState *env, uint32_t val);
d9bce9d9
JM		 1324void store_booke_tcr (CPUPPCState *env, target_ulong val);
1325void store_booke_tsr (CPUPPCState *env, target_ulong val);
0a032cbe 1326void ppc_tlb_invalidate_all (CPUPPCState *env);
daf4f96e 1327void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr);
da20aed1 1328void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp);
d9bce9d9 1329#endif
9fddaa0c 1330#endif
79aceca5 1331
d6478bc7
FC		 1332void store_fpscr(CPUPPCState *env, uint64_t arg, uint32_t mask);
1333
636aa200 1334static inline uint64_t ppc_dump_gpr(CPUPPCState *env, int gprn)
6b542af7
JM		 1335{
1336 uint64_t gprv;
1337
1338 gprv = env->gpr[gprn];
6b542af7
JM		 1339 if (env->flags & POWERPC_FLAG_SPE) {
1340 /* If the CPU implements the SPE extension, we have to get the
1341 * high bits of the GPR from the gprh storage area
1342 */
1343 gprv &= 0xFFFFFFFFULL;
1344 gprv |= (uint64_t)env->gprh[gprn] << 32;
1345 }
6b542af7
JM		 1346
1347 return gprv;
1348}
1349
2e719ba3 1350/* Device control registers */
73b01960
AG		 1351int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp);
1352int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val);
2e719ba3 1353
c9137065
IM		 1354#define POWERPC_CPU_TYPE_SUFFIX "-" TYPE_POWERPC_CPU
1355#define POWERPC_CPU_TYPE_NAME(model) model POWERPC_CPU_TYPE_SUFFIX
0dacec87 1356#define CPU_RESOLVING_TYPE TYPE_POWERPC_CPU
c9137065 1357
9467d44c 1358#define cpu_signal_handler cpu_ppc_signal_handler
c732abe2 1359#define cpu_list ppc_cpu_list
9467d44c 1360
6ebbf390 1361/* MMU modes definitions */
6ebbf390 1362#define MMU_USER_IDX 0
97ed5ccd 1363static inline int cpu_mmu_index (CPUPPCState *env, bool ifetch)
6ebbf390 1364{
9fb04491 1365 return ifetch ? env->immu_idx : env->dmmu_idx;
6ebbf390
JM		 1366}
1367
9d6f1065
DG		 1368/* Compatibility modes */
1369#if defined(TARGET_PPC64)
9d2179d6
DG		 1370bool ppc_check_compat(PowerPCCPU *cpu, uint32_t compat_pvr,
1371 uint32_t min_compat_pvr, uint32_t max_compat_pvr);
ad99d04c
DG		 1372bool ppc_type_check_compat(const char *cputype, uint32_t compat_pvr,
1373 uint32_t min_compat_pvr, uint32_t max_compat_pvr);
1374
9d6f1065 1375void ppc_set_compat(PowerPCCPU *cpu, uint32_t compat_pvr, Error **errp);
ad99d04c 1376
f6f242c7
DG		 1377#if !defined(CONFIG_USER_ONLY)
1378void ppc_set_compat_all(uint32_t compat_pvr, Error **errp);
1379#endif
abbc1247 1380int ppc_compat_max_vthreads(PowerPCCPU *cpu);
7843c0d6
DG		 1381void ppc_compat_add_property(Object *obj, const char *name,
1382 uint32_t *compat_pvr, const char *basedesc,
1383 Error **errp);
9d6f1065
DG		 1384#endif /* defined(TARGET_PPC64) */
1385
022c62cb 1386#include "exec/cpu-all.h"
79aceca5 1387
3fc6c082 1388/*****************************************************************************/
e1571908 1389/* CRF definitions */
efa73196
ND		 1390#define CRF_LT_BIT 3
1391#define CRF_GT_BIT 2
1392#define CRF_EQ_BIT 1
1393#define CRF_SO_BIT 0
1394#define CRF_LT (1 << CRF_LT_BIT)
1395#define CRF_GT (1 << CRF_GT_BIT)
1396#define CRF_EQ (1 << CRF_EQ_BIT)
1397#define CRF_SO (1 << CRF_SO_BIT)
1398/* For SPE extensions */
1399#define CRF_CH (1 << CRF_LT_BIT)
1400#define CRF_CL (1 << CRF_GT_BIT)
1401#define CRF_CH_OR_CL (1 << CRF_EQ_BIT)
1402#define CRF_CH_AND_CL (1 << CRF_SO_BIT)
e1571908
AJ		 1403
1404/* XER definitions */
3d7b417e
AJ		 1405#define XER_SO 31
1406#define XER_OV 30
1407#define XER_CA 29
dd09c361
ND		 1408#define XER_OV32 19
1409#define XER_CA32 18
3d7b417e
AJ		 1410#define XER_CMP 8
1411#define XER_BC 0
da91a00f
RH		 1412#define xer_so (env->so)
1413#define xer_ov (env->ov)
1414#define xer_ca (env->ca)
dd09c361
ND		 1415#define xer_ov32 (env->ov)
1416#define xer_ca32 (env->ca)
3d7b417e
AJ		 1417#define xer_cmp ((env->xer >> XER_CMP) & 0xFF)
1418#define xer_bc ((env->xer >> XER_BC) & 0x7F)
79aceca5 1419
3fc6c082 1420/* SPR definitions */
80d11f44
JM		 1421#define SPR_MQ (0x000)
1422#define SPR_XER (0x001)
1423#define SPR_601_VRTCU (0x004)
1424#define SPR_601_VRTCL (0x005)
1425#define SPR_601_UDECR (0x006)
1426#define SPR_LR (0x008)
1427#define SPR_CTR (0x009)
f244115c 1428#define SPR_UAMR (0x00D)
697ab892 1429#define SPR_DSCR (0x011)
80d11f44
JM		 1430#define SPR_DSISR (0x012)
1431#define SPR_DAR (0x013) /* DAE for PowerPC 601 */
1432#define SPR_601_RTCU (0x014)
1433#define SPR_601_RTCL (0x015)
1434#define SPR_DECR (0x016)
1435#define SPR_SDR1 (0x019)
1436#define SPR_SRR0 (0x01A)
1437#define SPR_SRR1 (0x01B)
697ab892 1438#define SPR_CFAR (0x01C)
80d11f44 1439#define SPR_AMR (0x01D)
9c1cf38d 1440#define SPR_ACOP (0x01F)
80d11f44 1441#define SPR_BOOKE_PID (0x030)
9c1cf38d 1442#define SPR_BOOKS_PID (0x030)
80d11f44
JM		 1443#define SPR_BOOKE_DECAR (0x036)
1444#define SPR_BOOKE_CSRR0 (0x03A)
1445#define SPR_BOOKE_CSRR1 (0x03B)
1446#define SPR_BOOKE_DEAR (0x03D)
a6eabb9e 1447#define SPR_IAMR (0x03D)
80d11f44
JM		 1448#define SPR_BOOKE_ESR (0x03E)
1449#define SPR_BOOKE_IVPR (0x03F)
1450#define SPR_MPC_EIE (0x050)
1451#define SPR_MPC_EID (0x051)
1452#define SPR_MPC_NRI (0x052)
cdcdda27
AK		 1453#define SPR_TFHAR (0x080)
1454#define SPR_TFIAR (0x081)
1455#define SPR_TEXASR (0x082)
1456#define SPR_TEXASRU (0x083)
0bfe9299 1457#define SPR_UCTRL (0x088)
650f3287 1458#define SPR_TIDR (0x090)
80d11f44
JM		 1459#define SPR_MPC_CMPA (0x090)
1460#define SPR_MPC_CMPB (0x091)
1461#define SPR_MPC_CMPC (0x092)
1462#define SPR_MPC_CMPD (0x093)
1463#define SPR_MPC_ECR (0x094)
1464#define SPR_MPC_DER (0x095)
1465#define SPR_MPC_COUNTA (0x096)
1466#define SPR_MPC_COUNTB (0x097)
0bfe9299 1467#define SPR_CTRL (0x098)
80d11f44
JM		 1468#define SPR_MPC_CMPE (0x098)
1469#define SPR_MPC_CMPF (0x099)
7019cb3d 1470#define SPR_FSCR (0x099)
80d11f44
JM		 1471#define SPR_MPC_CMPG (0x09A)
1472#define SPR_MPC_CMPH (0x09B)
1473#define SPR_MPC_LCTRL1 (0x09C)
1474#define SPR_MPC_LCTRL2 (0x09D)
f80872e2 1475#define SPR_UAMOR (0x09D)
80d11f44
JM		 1476#define SPR_MPC_ICTRL (0x09E)
1477#define SPR_MPC_BAR (0x09F)
d6f1445f 1478#define SPR_PSPB (0x09F)
1488270e
BH		 1479#define SPR_DAWR (0x0B4)
1480#define SPR_RPR (0x0BA)
eb5ceb4d 1481#define SPR_CIABR (0x0BB)
1488270e
BH		 1482#define SPR_DAWRX (0x0BC)
1483#define SPR_HFSCR (0x0BE)
80d11f44
JM		 1484#define SPR_VRSAVE (0x100)
1485#define SPR_USPRG0 (0x100)
1486#define SPR_USPRG1 (0x101)
1487#define SPR_USPRG2 (0x102)
1488#define SPR_USPRG3 (0x103)
1489#define SPR_USPRG4 (0x104)
1490#define SPR_USPRG5 (0x105)
1491#define SPR_USPRG6 (0x106)
1492#define SPR_USPRG7 (0x107)
1493#define SPR_VTBL (0x10C)
1494#define SPR_VTBU (0x10D)
1495#define SPR_SPRG0 (0x110)
1496#define SPR_SPRG1 (0x111)
1497#define SPR_SPRG2 (0x112)
1498#define SPR_SPRG3 (0x113)
1499#define SPR_SPRG4 (0x114)
1500#define SPR_SCOMC (0x114)
1501#define SPR_SPRG5 (0x115)
1502#define SPR_SCOMD (0x115)
1503#define SPR_SPRG6 (0x116)
1504#define SPR_SPRG7 (0x117)
1505#define SPR_ASR (0x118)
1506#define SPR_EAR (0x11A)
1507#define SPR_TBL (0x11C)
1508#define SPR_TBU (0x11D)
1509#define SPR_TBU40 (0x11E)
1510#define SPR_SVR (0x11E)
1511#define SPR_BOOKE_PIR (0x11E)
1512#define SPR_PVR (0x11F)
1513#define SPR_HSPRG0 (0x130)
1514#define SPR_BOOKE_DBSR (0x130)
1515#define SPR_HSPRG1 (0x131)
1516#define SPR_HDSISR (0x132)
1517#define SPR_HDAR (0x133)
90dc8812 1518#define SPR_BOOKE_EPCR (0x133)
9d52e907 1519#define SPR_SPURR (0x134)
80d11f44
JM		 1520#define SPR_BOOKE_DBCR0 (0x134)
1521#define SPR_IBCR (0x135)
1522#define SPR_PURR (0x135)
1523#define SPR_BOOKE_DBCR1 (0x135)
1524#define SPR_DBCR (0x136)
1525#define SPR_HDEC (0x136)
1526#define SPR_BOOKE_DBCR2 (0x136)
1527#define SPR_HIOR (0x137)
1528#define SPR_MBAR (0x137)
1529#define SPR_RMOR (0x138)
1530#define SPR_BOOKE_IAC1 (0x138)
1531#define SPR_HRMOR (0x139)
1532#define SPR_BOOKE_IAC2 (0x139)
1533#define SPR_HSRR0 (0x13A)
1534#define SPR_BOOKE_IAC3 (0x13A)
1535#define SPR_HSRR1 (0x13B)
1536#define SPR_BOOKE_IAC4 (0x13B)
80d11f44 1537#define SPR_BOOKE_DAC1 (0x13C)
1488270e 1538#define SPR_MMCRH (0x13C)
80d11f44
JM		 1539#define SPR_DABR2 (0x13D)
1540#define SPR_BOOKE_DAC2 (0x13D)
1488270e 1541#define SPR_TFMR (0x13D)
80d11f44 1542#define SPR_BOOKE_DVC1 (0x13E)
6475c9f0 1543#define SPR_LPCR (0x13E)
80d11f44 1544#define SPR_BOOKE_DVC2 (0x13F)
1488270e 1545#define SPR_LPIDR (0x13F)
80d11f44 1546#define SPR_BOOKE_TSR (0x150)
1488270e
BH		 1547#define SPR_HMER (0x150)
1548#define SPR_HMEER (0x151)
6d9412ea 1549#define SPR_PCR (0x152)
1488270e 1550#define SPR_BOOKE_LPIDR (0x152)
80d11f44 1551#define SPR_BOOKE_TCR (0x154)
a1ef618a
AG		 1552#define SPR_BOOKE_TLB0PS (0x158)
1553#define SPR_BOOKE_TLB1PS (0x159)
1554#define SPR_BOOKE_TLB2PS (0x15A)
1555#define SPR_BOOKE_TLB3PS (0x15B)
1488270e 1556#define SPR_AMOR (0x15D)
84755ed5 1557#define SPR_BOOKE_MAS7_MAS3 (0x174)
80d11f44
JM		 1558#define SPR_BOOKE_IVOR0 (0x190)
1559#define SPR_BOOKE_IVOR1 (0x191)
1560#define SPR_BOOKE_IVOR2 (0x192)
1561#define SPR_BOOKE_IVOR3 (0x193)
1562#define SPR_BOOKE_IVOR4 (0x194)
1563#define SPR_BOOKE_IVOR5 (0x195)
1564#define SPR_BOOKE_IVOR6 (0x196)
1565#define SPR_BOOKE_IVOR7 (0x197)
1566#define SPR_BOOKE_IVOR8 (0x198)
1567#define SPR_BOOKE_IVOR9 (0x199)
1568#define SPR_BOOKE_IVOR10 (0x19A)
1569#define SPR_BOOKE_IVOR11 (0x19B)
1570#define SPR_BOOKE_IVOR12 (0x19C)
1571#define SPR_BOOKE_IVOR13 (0x19D)
1572#define SPR_BOOKE_IVOR14 (0x19E)
1573#define SPR_BOOKE_IVOR15 (0x19F)
e9205258
AG		 1574#define SPR_BOOKE_IVOR38 (0x1B0)
1575#define SPR_BOOKE_IVOR39 (0x1B1)
1576#define SPR_BOOKE_IVOR40 (0x1B2)
1577#define SPR_BOOKE_IVOR41 (0x1B3)
1578#define SPR_BOOKE_IVOR42 (0x1B4)
45eb5611
AG		 1579#define SPR_BOOKE_GIVOR2 (0x1B8)
1580#define SPR_BOOKE_GIVOR3 (0x1B9)
1581#define SPR_BOOKE_GIVOR4 (0x1BA)
1582#define SPR_BOOKE_GIVOR8 (0x1BB)
1583#define SPR_BOOKE_GIVOR13 (0x1BC)
1584#define SPR_BOOKE_GIVOR14 (0x1BD)
d1a721ab 1585#define SPR_TIR (0x1BE)
4a7518e0 1586#define SPR_PTCR (0x1D0)
80d11f44
JM		 1587#define SPR_BOOKE_SPEFSCR (0x200)
1588#define SPR_Exxx_BBEAR (0x201)
1589#define SPR_Exxx_BBTAR (0x202)
1590#define SPR_Exxx_L1CFG0 (0x203)
d2ea2bf7 1591#define SPR_Exxx_L1CFG1 (0x204)
80d11f44
JM		 1592#define SPR_Exxx_NPIDR (0x205)
1593#define SPR_ATBL (0x20E)
1594#define SPR_ATBU (0x20F)
1595#define SPR_IBAT0U (0x210)
1596#define SPR_BOOKE_IVOR32 (0x210)
1597#define SPR_RCPU_MI_GRA (0x210)
1598#define SPR_IBAT0L (0x211)
1599#define SPR_BOOKE_IVOR33 (0x211)
1600#define SPR_IBAT1U (0x212)
1601#define SPR_BOOKE_IVOR34 (0x212)
1602#define SPR_IBAT1L (0x213)
1603#define SPR_BOOKE_IVOR35 (0x213)
1604#define SPR_IBAT2U (0x214)
1605#define SPR_BOOKE_IVOR36 (0x214)
1606#define SPR_IBAT2L (0x215)
1607#define SPR_BOOKE_IVOR37 (0x215)
1608#define SPR_IBAT3U (0x216)
1609#define SPR_IBAT3L (0x217)
1610#define SPR_DBAT0U (0x218)
1611#define SPR_RCPU_L2U_GRA (0x218)
1612#define SPR_DBAT0L (0x219)
1613#define SPR_DBAT1U (0x21A)
1614#define SPR_DBAT1L (0x21B)
1615#define SPR_DBAT2U (0x21C)
1616#define SPR_DBAT2L (0x21D)
1617#define SPR_DBAT3U (0x21E)
1618#define SPR_DBAT3L (0x21F)
1619#define SPR_IBAT4U (0x230)
1620#define SPR_RPCU_BBCMCR (0x230)
1621#define SPR_MPC_IC_CST (0x230)
1622#define SPR_Exxx_CTXCR (0x230)
1623#define SPR_IBAT4L (0x231)
1624#define SPR_MPC_IC_ADR (0x231)
1625#define SPR_Exxx_DBCR3 (0x231)
1626#define SPR_IBAT5U (0x232)
1627#define SPR_MPC_IC_DAT (0x232)
1628#define SPR_Exxx_DBCNT (0x232)
1629#define SPR_IBAT5L (0x233)
1630#define SPR_IBAT6U (0x234)
1631#define SPR_IBAT6L (0x235)
1632#define SPR_IBAT7U (0x236)
1633#define SPR_IBAT7L (0x237)
1634#define SPR_DBAT4U (0x238)
1635#define SPR_RCPU_L2U_MCR (0x238)
1636#define SPR_MPC_DC_CST (0x238)
1637#define SPR_Exxx_ALTCTXCR (0x238)
1638#define SPR_DBAT4L (0x239)
1639#define SPR_MPC_DC_ADR (0x239)
1640#define SPR_DBAT5U (0x23A)
1641#define SPR_BOOKE_MCSRR0 (0x23A)
1642#define SPR_MPC_DC_DAT (0x23A)
1643#define SPR_DBAT5L (0x23B)
1644#define SPR_BOOKE_MCSRR1 (0x23B)
1645#define SPR_DBAT6U (0x23C)
1646#define SPR_BOOKE_MCSR (0x23C)
1647#define SPR_DBAT6L (0x23D)
1648#define SPR_Exxx_MCAR (0x23D)
1649#define SPR_DBAT7U (0x23E)
1650#define SPR_BOOKE_DSRR0 (0x23E)
1651#define SPR_DBAT7L (0x23F)
1652#define SPR_BOOKE_DSRR1 (0x23F)
1653#define SPR_BOOKE_SPRG8 (0x25C)
1654#define SPR_BOOKE_SPRG9 (0x25D)
1655#define SPR_BOOKE_MAS0 (0x270)
1656#define SPR_BOOKE_MAS1 (0x271)
1657#define SPR_BOOKE_MAS2 (0x272)
1658#define SPR_BOOKE_MAS3 (0x273)
1659#define SPR_BOOKE_MAS4 (0x274)
1660#define SPR_BOOKE_MAS5 (0x275)
1661#define SPR_BOOKE_MAS6 (0x276)
1662#define SPR_BOOKE_PID1 (0x279)
1663#define SPR_BOOKE_PID2 (0x27A)
1664#define SPR_MPC_DPDR (0x280)
1665#define SPR_MPC_IMMR (0x288)
1666#define SPR_BOOKE_TLB0CFG (0x2B0)
1667#define SPR_BOOKE_TLB1CFG (0x2B1)
1668#define SPR_BOOKE_TLB2CFG (0x2B2)
1669#define SPR_BOOKE_TLB3CFG (0x2B3)
1670#define SPR_BOOKE_EPR (0x2BE)
1671#define SPR_PERF0 (0x300)
1672#define SPR_RCPU_MI_RBA0 (0x300)
1673#define SPR_MPC_MI_CTR (0x300)
14646457 1674#define SPR_POWER_USIER (0x300)
80d11f44
JM		 1675#define SPR_PERF1 (0x301)
1676#define SPR_RCPU_MI_RBA1 (0x301)
70c53407 1677#define SPR_POWER_UMMCR2 (0x301)
80d11f44
JM		 1678#define SPR_PERF2 (0x302)
1679#define SPR_RCPU_MI_RBA2 (0x302)
1680#define SPR_MPC_MI_AP (0x302)
75b9c321 1681#define SPR_POWER_UMMCRA (0x302)
80d11f44
JM		 1682#define SPR_PERF3 (0x303)
1683#define SPR_RCPU_MI_RBA3 (0x303)
1684#define SPR_MPC_MI_EPN (0x303)
fd51ff63 1685#define SPR_POWER_UPMC1 (0x303)
80d11f44 1686#define SPR_PERF4 (0x304)
fd51ff63 1687#define SPR_POWER_UPMC2 (0x304)
80d11f44
JM		 1688#define SPR_PERF5 (0x305)
1689#define SPR_MPC_MI_TWC (0x305)
fd51ff63 1690#define SPR_POWER_UPMC3 (0x305)
80d11f44
JM		 1691#define SPR_PERF6 (0x306)
1692#define SPR_MPC_MI_RPN (0x306)
fd51ff63 1693#define SPR_POWER_UPMC4 (0x306)
80d11f44 1694#define SPR_PERF7 (0x307)
fd51ff63 1695#define SPR_POWER_UPMC5 (0x307)
80d11f44
JM		 1696#define SPR_PERF8 (0x308)
1697#define SPR_RCPU_L2U_RBA0 (0x308)
1698#define SPR_MPC_MD_CTR (0x308)
fd51ff63 1699#define SPR_POWER_UPMC6 (0x308)
80d11f44
JM		 1700#define SPR_PERF9 (0x309)
1701#define SPR_RCPU_L2U_RBA1 (0x309)
1702#define SPR_MPC_MD_CASID (0x309)
c36c97f8 1703#define SPR_970_UPMC7 (0X309)
80d11f44
JM		 1704#define SPR_PERFA (0x30A)
1705#define SPR_RCPU_L2U_RBA2 (0x30A)
1706#define SPR_MPC_MD_AP (0x30A)
c36c97f8 1707#define SPR_970_UPMC8 (0X30A)
80d11f44
JM		 1708#define SPR_PERFB (0x30B)
1709#define SPR_RCPU_L2U_RBA3 (0x30B)
1710#define SPR_MPC_MD_EPN (0x30B)
fd51ff63 1711#define SPR_POWER_UMMCR0 (0X30B)
80d11f44
JM		 1712#define SPR_PERFC (0x30C)
1713#define SPR_MPC_MD_TWB (0x30C)
fd51ff63 1714#define SPR_POWER_USIAR (0X30C)
80d11f44
JM		 1715#define SPR_PERFD (0x30D)
1716#define SPR_MPC_MD_TWC (0x30D)
fd51ff63 1717#define SPR_POWER_USDAR (0X30D)
80d11f44
JM		 1718#define SPR_PERFE (0x30E)
1719#define SPR_MPC_MD_RPN (0x30E)
fd51ff63 1720#define SPR_POWER_UMMCR1 (0X30E)
80d11f44
JM		 1721#define SPR_PERFF (0x30F)
1722#define SPR_MPC_MD_TW (0x30F)
1723#define SPR_UPERF0 (0x310)
14646457 1724#define SPR_POWER_SIER (0x310)
80d11f44 1725#define SPR_UPERF1 (0x311)
70c53407 1726#define SPR_POWER_MMCR2 (0x311)
80d11f44 1727#define SPR_UPERF2 (0x312)
75b9c321 1728#define SPR_POWER_MMCRA (0X312)
80d11f44 1729#define SPR_UPERF3 (0x313)
fd51ff63 1730#define SPR_POWER_PMC1 (0X313)
80d11f44 1731#define SPR_UPERF4 (0x314)
fd51ff63 1732#define SPR_POWER_PMC2 (0X314)
80d11f44 1733#define SPR_UPERF5 (0x315)
fd51ff63 1734#define SPR_POWER_PMC3 (0X315)
80d11f44 1735#define SPR_UPERF6 (0x316)
fd51ff63 1736#define SPR_POWER_PMC4 (0X316)
80d11f44 1737#define SPR_UPERF7 (0x317)
fd51ff63 1738#define SPR_POWER_PMC5 (0X317)
80d11f44 1739#define SPR_UPERF8 (0x318)
fd51ff63 1740#define SPR_POWER_PMC6 (0X318)
80d11f44 1741#define SPR_UPERF9 (0x319)
c36c97f8 1742#define SPR_970_PMC7 (0X319)
80d11f44 1743#define SPR_UPERFA (0x31A)
c36c97f8 1744#define SPR_970_PMC8 (0X31A)
80d11f44 1745#define SPR_UPERFB (0x31B)
fd51ff63 1746#define SPR_POWER_MMCR0 (0X31B)
80d11f44 1747#define SPR_UPERFC (0x31C)
fd51ff63 1748#define SPR_POWER_SIAR (0X31C)
80d11f44 1749#define SPR_UPERFD (0x31D)
fd51ff63 1750#define SPR_POWER_SDAR (0X31D)
80d11f44 1751#define SPR_UPERFE (0x31E)
fd51ff63 1752#define SPR_POWER_MMCR1 (0X31E)
80d11f44
JM		 1753#define SPR_UPERFF (0x31F)
1754#define SPR_RCPU_MI_RA0 (0x320)
1755#define SPR_MPC_MI_DBCAM (0x320)
4ee4a03b 1756#define SPR_BESCRS (0x320)
80d11f44
JM		 1757#define SPR_RCPU_MI_RA1 (0x321)
1758#define SPR_MPC_MI_DBRAM0 (0x321)
4ee4a03b 1759#define SPR_BESCRSU (0x321)
80d11f44
JM		 1760#define SPR_RCPU_MI_RA2 (0x322)
1761#define SPR_MPC_MI_DBRAM1 (0x322)
4ee4a03b 1762#define SPR_BESCRR (0x322)
80d11f44 1763#define SPR_RCPU_MI_RA3 (0x323)
4ee4a03b
AK		 1764#define SPR_BESCRRU (0x323)
1765#define SPR_EBBHR (0x324)
1766#define SPR_EBBRR (0x325)
1767#define SPR_BESCR (0x326)
80d11f44
JM		 1768#define SPR_RCPU_L2U_RA0 (0x328)
1769#define SPR_MPC_MD_DBCAM (0x328)
1770#define SPR_RCPU_L2U_RA1 (0x329)
1771#define SPR_MPC_MD_DBRAM0 (0x329)
1772#define SPR_RCPU_L2U_RA2 (0x32A)
1773#define SPR_MPC_MD_DBRAM1 (0x32A)
1774#define SPR_RCPU_L2U_RA3 (0x32B)
60511041 1775#define SPR_TAR (0x32F)
21a558be 1776#define SPR_IC (0x350)
3ba55e39 1777#define SPR_VTB (0x351)
1488270e 1778#define SPR_MMCRC (0x353)
b8af5b2d 1779#define SPR_PSSCR (0x357)
80d11f44
JM		 1780#define SPR_440_INV0 (0x370)
1781#define SPR_440_INV1 (0x371)
1782#define SPR_440_INV2 (0x372)
1783#define SPR_440_INV3 (0x373)
1784#define SPR_440_ITV0 (0x374)
1785#define SPR_440_ITV1 (0x375)
1786#define SPR_440_ITV2 (0x376)
1787#define SPR_440_ITV3 (0x377)
1788#define SPR_440_CCR1 (0x378)
14646457
BH		 1789#define SPR_TACR (0x378)
1790#define SPR_TCSCR (0x379)
1791#define SPR_CSIGR (0x37a)
80d11f44 1792#define SPR_DCRIPR (0x37B)
14646457
BH		 1793#define SPR_POWER_SPMC1 (0x37C)
1794#define SPR_POWER_SPMC2 (0x37D)
70c53407 1795#define SPR_POWER_MMCRS (0x37E)
9c1cf38d 1796#define SPR_WORT (0x37F)
80d11f44 1797#define SPR_PPR (0x380)
bd928eba 1798#define SPR_750_GQR0 (0x390)
80d11f44 1799#define SPR_440_DNV0 (0x390)
bd928eba 1800#define SPR_750_GQR1 (0x391)
80d11f44 1801#define SPR_440_DNV1 (0x391)
bd928eba 1802#define SPR_750_GQR2 (0x392)
80d11f44 1803#define SPR_440_DNV2 (0x392)
bd928eba 1804#define SPR_750_GQR3 (0x393)
80d11f44 1805#define SPR_440_DNV3 (0x393)
bd928eba 1806#define SPR_750_GQR4 (0x394)
80d11f44 1807#define SPR_440_DTV0 (0x394)
bd928eba 1808#define SPR_750_GQR5 (0x395)
80d11f44 1809#define SPR_440_DTV1 (0x395)
bd928eba 1810#define SPR_750_GQR6 (0x396)
80d11f44 1811#define SPR_440_DTV2 (0x396)
bd928eba 1812#define SPR_750_GQR7 (0x397)
80d11f44 1813#define SPR_440_DTV3 (0x397)
bd928eba
JM		 1814#define SPR_750_THRM4 (0x398)
1815#define SPR_750CL_HID2 (0x398)
80d11f44 1816#define SPR_440_DVLIM (0x398)
bd928eba 1817#define SPR_750_WPAR (0x399)
80d11f44 1818#define SPR_440_IVLIM (0x399)
1488270e 1819#define SPR_TSCR (0x399)
bd928eba
JM		 1820#define SPR_750_DMAU (0x39A)
1821#define SPR_750_DMAL (0x39B)
80d11f44
JM		 1822#define SPR_440_RSTCFG (0x39B)
1823#define SPR_BOOKE_DCDBTRL (0x39C)
1824#define SPR_BOOKE_DCDBTRH (0x39D)
1825#define SPR_BOOKE_ICDBTRL (0x39E)
1826#define SPR_BOOKE_ICDBTRH (0x39F)
cb8b8bf8
AK		 1827#define SPR_74XX_UMMCR2 (0x3A0)
1828#define SPR_7XX_UPMC5 (0x3A1)
1829#define SPR_7XX_UPMC6 (0x3A2)
80d11f44 1830#define SPR_UBAMR (0x3A7)
cb8b8bf8
AK		 1831#define SPR_7XX_UMMCR0 (0x3A8)
1832#define SPR_7XX_UPMC1 (0x3A9)
1833#define SPR_7XX_UPMC2 (0x3AA)
1834#define SPR_7XX_USIAR (0x3AB)
1835#define SPR_7XX_UMMCR1 (0x3AC)
1836#define SPR_7XX_UPMC3 (0x3AD)
1837#define SPR_7XX_UPMC4 (0x3AE)
80d11f44
JM		 1838#define SPR_USDA (0x3AF)
1839#define SPR_40x_ZPR (0x3B0)
1840#define SPR_BOOKE_MAS7 (0x3B0)
cb8b8bf8
AK		 1841#define SPR_74XX_MMCR2 (0x3B0)
1842#define SPR_7XX_PMC5 (0x3B1)
80d11f44 1843#define SPR_40x_PID (0x3B1)
cb8b8bf8 1844#define SPR_7XX_PMC6 (0x3B2)
80d11f44 1845#define SPR_440_MMUCR (0x3B2)
80d11f44
JM		 1846#define SPR_4xx_CCR0 (0x3B3)
1847#define SPR_BOOKE_EPLC (0x3B3)
80d11f44
JM		 1848#define SPR_405_IAC3 (0x3B4)
1849#define SPR_BOOKE_EPSC (0x3B4)
80d11f44 1850#define SPR_405_IAC4 (0x3B5)
80d11f44 1851#define SPR_405_DVC1 (0x3B6)
80d11f44 1852#define SPR_405_DVC2 (0x3B7)
80d11f44 1853#define SPR_BAMR (0x3B7)
cb8b8bf8
AK		 1854#define SPR_7XX_MMCR0 (0x3B8)
1855#define SPR_7XX_PMC1 (0x3B9)
80d11f44 1856#define SPR_40x_SGR (0x3B9)
cb8b8bf8 1857#define SPR_7XX_PMC2 (0x3BA)
80d11f44 1858#define SPR_40x_DCWR (0x3BA)
cb8b8bf8 1859#define SPR_7XX_SIAR (0x3BB)
80d11f44 1860#define SPR_405_SLER (0x3BB)
cb8b8bf8 1861#define SPR_7XX_MMCR1 (0x3BC)
80d11f44 1862#define SPR_405_SU0R (0x3BC)
80d11f44 1863#define SPR_401_SKR (0x3BC)
cb8b8bf8 1864#define SPR_7XX_PMC3 (0x3BD)
80d11f44 1865#define SPR_405_DBCR1 (0x3BD)
cb8b8bf8 1866#define SPR_7XX_PMC4 (0x3BE)
80d11f44 1867#define SPR_SDA (0x3BF)
80d11f44
JM		 1868#define SPR_403_VTBL (0x3CC)
1869#define SPR_403_VTBU (0x3CD)
1870#define SPR_DMISS (0x3D0)
1871#define SPR_DCMP (0x3D1)
1872#define SPR_HASH1 (0x3D2)
1873#define SPR_HASH2 (0x3D3)
1874#define SPR_BOOKE_ICDBDR (0x3D3)
1875#define SPR_TLBMISS (0x3D4)
1876#define SPR_IMISS (0x3D4)
1877#define SPR_40x_ESR (0x3D4)
1878#define SPR_PTEHI (0x3D5)
1879#define SPR_ICMP (0x3D5)
1880#define SPR_40x_DEAR (0x3D5)
1881#define SPR_PTELO (0x3D6)
1882#define SPR_RPA (0x3D6)
1883#define SPR_40x_EVPR (0x3D6)
1884#define SPR_L3PM (0x3D7)
1885#define SPR_403_CDBCR (0x3D7)
4e777442 1886#define SPR_L3ITCR0 (0x3D8)
80d11f44
JM		 1887#define SPR_TCR (0x3D8)
1888#define SPR_40x_TSR (0x3D8)
1889#define SPR_IBR (0x3DA)
1890#define SPR_40x_TCR (0x3DA)
1891#define SPR_ESASRR (0x3DB)
1892#define SPR_40x_PIT (0x3DB)
1893#define SPR_403_TBL (0x3DC)
1894#define SPR_403_TBU (0x3DD)
1895#define SPR_SEBR (0x3DE)
1896#define SPR_40x_SRR2 (0x3DE)
1897#define SPR_SER (0x3DF)
1898#define SPR_40x_SRR3 (0x3DF)
4e777442 1899#define SPR_L3OHCR (0x3E8)
80d11f44
JM		 1900#define SPR_L3ITCR1 (0x3E9)
1901#define SPR_L3ITCR2 (0x3EA)
1902#define SPR_L3ITCR3 (0x3EB)
1903#define SPR_HID0 (0x3F0)
1904#define SPR_40x_DBSR (0x3F0)
1905#define SPR_HID1 (0x3F1)
1906#define SPR_IABR (0x3F2)
1907#define SPR_40x_DBCR0 (0x3F2)
1908#define SPR_601_HID2 (0x3F2)
1909#define SPR_Exxx_L1CSR0 (0x3F2)
1910#define SPR_ICTRL (0x3F3)
1911#define SPR_HID2 (0x3F3)
bd928eba 1912#define SPR_750CL_HID4 (0x3F3)
80d11f44
JM		 1913#define SPR_Exxx_L1CSR1 (0x3F3)
1914#define SPR_440_DBDR (0x3F3)
1915#define SPR_LDSTDB (0x3F4)
bd928eba 1916#define SPR_750_TDCL (0x3F4)
80d11f44
JM		 1917#define SPR_40x_IAC1 (0x3F4)
1918#define SPR_MMUCSR0 (0x3F4)
ba881002 1919#define SPR_970_HID4 (0x3F4)
80d11f44 1920#define SPR_DABR (0x3F5)
3fc6c082 1921#define DABR_MASK (~(target_ulong)0x7)
80d11f44
JM		 1922#define SPR_Exxx_BUCSR (0x3F5)
1923#define SPR_40x_IAC2 (0x3F5)
1924#define SPR_601_HID5 (0x3F5)
1925#define SPR_40x_DAC1 (0x3F6)
1926#define SPR_MSSCR0 (0x3F6)
1927#define SPR_970_HID5 (0x3F6)
1928#define SPR_MSSSR0 (0x3F7)
4e777442 1929#define SPR_MSSCR1 (0x3F7)
80d11f44
JM		 1930#define SPR_DABRX (0x3F7)
1931#define SPR_40x_DAC2 (0x3F7)
1932#define SPR_MMUCFG (0x3F7)
1933#define SPR_LDSTCR (0x3F8)
1934#define SPR_L2PMCR (0x3F8)
bd928eba 1935#define SPR_750FX_HID2 (0x3F8)
80d11f44
JM		 1936#define SPR_Exxx_L1FINV0 (0x3F8)
1937#define SPR_L2CR (0x3F9)
80d11f44 1938#define SPR_L3CR (0x3FA)
bd928eba 1939#define SPR_750_TDCH (0x3FA)
80d11f44
JM		 1940#define SPR_IABR2 (0x3FA)
1941#define SPR_40x_DCCR (0x3FA)
1942#define SPR_ICTC (0x3FB)
1943#define SPR_40x_ICCR (0x3FB)
1944#define SPR_THRM1 (0x3FC)
1945#define SPR_403_PBL1 (0x3FC)
1946#define SPR_SP (0x3FD)
1947#define SPR_THRM2 (0x3FD)
1948#define SPR_403_PBU1 (0x3FD)
1949#define SPR_604_HID13 (0x3FD)
1950#define SPR_LT (0x3FE)
1951#define SPR_THRM3 (0x3FE)
1952#define SPR_RCPU_FPECR (0x3FE)
1953#define SPR_403_PBL2 (0x3FE)
1954#define SPR_PIR (0x3FF)
1955#define SPR_403_PBU2 (0x3FF)
1956#define SPR_601_HID15 (0x3FF)
1957#define SPR_604_HID15 (0x3FF)
1958#define SPR_E500_SVR (0x3FF)
79aceca5 1959
84755ed5
AG		 1960/* Disable MAS Interrupt Updates for Hypervisor */
1961#define EPCR_DMIUH (1 << 22)
1962/* Disable Guest TLB Management Instructions */
1963#define EPCR_DGTMI (1 << 23)
1964/* Guest Interrupt Computation Mode */
1965#define EPCR_GICM (1 << 24)
1966/* Interrupt Computation Mode */
1967#define EPCR_ICM (1 << 25)
1968/* Disable Embedded Hypervisor Debug */
1969#define EPCR_DUVD (1 << 26)
1970/* Instruction Storage Interrupt Directed to Guest State */
1971#define EPCR_ISIGS (1 << 27)
1972/* Data Storage Interrupt Directed to Guest State */
1973#define EPCR_DSIGS (1 << 28)
1974/* Instruction TLB Error Interrupt Directed to Guest State */
1975#define EPCR_ITLBGS (1 << 29)
1976/* Data TLB Error Interrupt Directed to Guest State */
1977#define EPCR_DTLBGS (1 << 30)
1978/* External Input Interrupt Directed to Guest State */
1979#define EPCR_EXTGS (1 << 31)
1980
ea71258d
AG		 1981#define L1CSR0_CPE 0x00010000 /* Data Cache Parity Enable */
1982#define L1CSR0_CUL 0x00000400 /* (D-)Cache Unable to Lock */
1983#define L1CSR0_DCLFR 0x00000100 /* D-Cache Lock Flash Reset */
1984#define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */
1985#define L1CSR0_DCE 0x00000001 /* Data Cache Enable */
1986
1987#define L1CSR1_CPE 0x00010000 /* Instruction Cache Parity Enable */
1988#define L1CSR1_ICUL 0x00000400 /* I-Cache Unable to Lock */
1989#define L1CSR1_ICLFR 0x00000100 /* I-Cache Lock Flash Reset */
1990#define L1CSR1_ICFI 0x00000002 /* Instruction Cache Flash Invalidate */
1991#define L1CSR1_ICE 0x00000001 /* Instruction Cache Enable */
1992
bbc01ca7 1993/* HID0 bits */
1488270e
BH		 1994#define HID0_DEEPNAP (1 << 24) /* pre-2.06 */
1995#define HID0_DOZE (1 << 23) /* pre-2.06 */
1996#define HID0_NAP (1 << 22) /* pre-2.06 */
2a83f997 1997#define HID0_HILE PPC_BIT(19) /* POWER8 */
0bfc0cf0 1998#define HID0_POWER9_HILE PPC_BIT(4)
bbc01ca7 1999
c29b735c
NF		 2000/*****************************************************************************/
2001/* PowerPC Instructions types definitions */
2002enum {
2003 PPC_NONE = 0x0000000000000000ULL,
2004 /* PowerPC base instructions set */
2005 PPC_INSNS_BASE = 0x0000000000000001ULL,
2006 /* integer operations instructions */
2007#define PPC_INTEGER PPC_INSNS_BASE
2008 /* flow control instructions */
2009#define PPC_FLOW PPC_INSNS_BASE
2010 /* virtual memory instructions */
2011#define PPC_MEM PPC_INSNS_BASE
2012 /* ld/st with reservation instructions */
2013#define PPC_RES PPC_INSNS_BASE
2014 /* spr/msr access instructions */
2015#define PPC_MISC PPC_INSNS_BASE
2016 /* Deprecated instruction sets */
2017 /* Original POWER instruction set */
2018 PPC_POWER = 0x0000000000000002ULL,
2019 /* POWER2 instruction set extension */
2020 PPC_POWER2 = 0x0000000000000004ULL,
2021 /* Power RTC support */
2022 PPC_POWER_RTC = 0x0000000000000008ULL,
2023 /* Power-to-PowerPC bridge (601) */
2024 PPC_POWER_BR = 0x0000000000000010ULL,
2025 /* 64 bits PowerPC instruction set */
2026 PPC_64B = 0x0000000000000020ULL,
2027 /* New 64 bits extensions (PowerPC 2.0x) */
2028 PPC_64BX = 0x0000000000000040ULL,
2029 /* 64 bits hypervisor extensions */
2030 PPC_64H = 0x0000000000000080ULL,
2031 /* New wait instruction (PowerPC 2.0x) */
2032 PPC_WAIT = 0x0000000000000100ULL,
2033 /* Time base mftb instruction */
2034 PPC_MFTB = 0x0000000000000200ULL,
2035
2036 /* Fixed-point unit extensions */
2037 /* PowerPC 602 specific */
2038 PPC_602_SPEC = 0x0000000000000400ULL,
2039 /* isel instruction */
2040 PPC_ISEL = 0x0000000000000800ULL,
2041 /* popcntb instruction */
2042 PPC_POPCNTB = 0x0000000000001000ULL,
2043 /* string load / store */
2044 PPC_STRING = 0x0000000000002000ULL,
b7815375
BH		 2045 /* real mode cache inhibited load / store */
2046 PPC_CILDST = 0x0000000000004000ULL,
c29b735c
NF		 2047
2048 /* Floating-point unit extensions */
2049 /* Optional floating point instructions */
2050 PPC_FLOAT = 0x0000000000010000ULL,
2051 /* New floating-point extensions (PowerPC 2.0x) */
2052 PPC_FLOAT_EXT = 0x0000000000020000ULL,
2053 PPC_FLOAT_FSQRT = 0x0000000000040000ULL,
2054 PPC_FLOAT_FRES = 0x0000000000080000ULL,
2055 PPC_FLOAT_FRSQRTE = 0x0000000000100000ULL,
2056 PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
2057 PPC_FLOAT_FSEL = 0x0000000000400000ULL,
2058 PPC_FLOAT_STFIWX = 0x0000000000800000ULL,
2059
2060 /* Vector/SIMD extensions */
2061 /* Altivec support */
2062 PPC_ALTIVEC = 0x0000000001000000ULL,
2063 /* PowerPC 2.03 SPE extension */
2064 PPC_SPE = 0x0000000002000000ULL,
2065 /* PowerPC 2.03 SPE single-precision floating-point extension */
2066 PPC_SPE_SINGLE = 0x0000000004000000ULL,
2067 /* PowerPC 2.03 SPE double-precision floating-point extension */
2068 PPC_SPE_DOUBLE = 0x0000000008000000ULL,
2069
2070 /* Optional memory control instructions */
2071 PPC_MEM_TLBIA = 0x0000000010000000ULL,
2072 PPC_MEM_TLBIE = 0x0000000020000000ULL,
2073 PPC_MEM_TLBSYNC = 0x0000000040000000ULL,
2074 /* sync instruction */
2075 PPC_MEM_SYNC = 0x0000000080000000ULL,
2076 /* eieio instruction */
2077 PPC_MEM_EIEIO = 0x0000000100000000ULL,
2078
2079 /* Cache control instructions */
2080 PPC_CACHE = 0x0000000200000000ULL,
2081 /* icbi instruction */
2082 PPC_CACHE_ICBI = 0x0000000400000000ULL,
8e33944f 2083 /* dcbz instruction */
c29b735c 2084 PPC_CACHE_DCBZ = 0x0000000800000000ULL,
c29b735c
NF		 2085 /* dcba instruction */
2086 PPC_CACHE_DCBA = 0x0000002000000000ULL,
2087 /* Freescale cache locking instructions */
2088 PPC_CACHE_LOCK = 0x0000004000000000ULL,
2089
2090 /* MMU related extensions */
2091 /* external control instructions */
2092 PPC_EXTERN = 0x0000010000000000ULL,
2093 /* segment register access instructions */
2094 PPC_SEGMENT = 0x0000020000000000ULL,
2095 /* PowerPC 6xx TLB management instructions */
2096 PPC_6xx_TLB = 0x0000040000000000ULL,
2097 /* PowerPC 74xx TLB management instructions */
2098 PPC_74xx_TLB = 0x0000080000000000ULL,
2099 /* PowerPC 40x TLB management instructions */
2100 PPC_40x_TLB = 0x0000100000000000ULL,
2101 /* segment register access instructions for PowerPC 64 "bridge" */
2102 PPC_SEGMENT_64B = 0x0000200000000000ULL,
2103 /* SLB management */
2104 PPC_SLBI = 0x0000400000000000ULL,
2105
2106 /* Embedded PowerPC dedicated instructions */
2107 PPC_WRTEE = 0x0001000000000000ULL,
2108 /* PowerPC 40x exception model */
2109 PPC_40x_EXCP = 0x0002000000000000ULL,
2110 /* PowerPC 405 Mac instructions */
2111 PPC_405_MAC = 0x0004000000000000ULL,
2112 /* PowerPC 440 specific instructions */
2113 PPC_440_SPEC = 0x0008000000000000ULL,
2114 /* BookE (embedded) PowerPC specification */
2115 PPC_BOOKE = 0x0010000000000000ULL,
2116 /* mfapidi instruction */
2117 PPC_MFAPIDI = 0x0020000000000000ULL,
2118 /* tlbiva instruction */
2119 PPC_TLBIVA = 0x0040000000000000ULL,
2120 /* tlbivax instruction */
2121 PPC_TLBIVAX = 0x0080000000000000ULL,
2122 /* PowerPC 4xx dedicated instructions */
2123 PPC_4xx_COMMON = 0x0100000000000000ULL,
2124 /* PowerPC 40x ibct instructions */
2125 PPC_40x_ICBT = 0x0200000000000000ULL,
2126 /* rfmci is not implemented in all BookE PowerPC */
2127 PPC_RFMCI = 0x0400000000000000ULL,
2128 /* rfdi instruction */
2129 PPC_RFDI = 0x0800000000000000ULL,
2130 /* DCR accesses */
2131 PPC_DCR = 0x1000000000000000ULL,
2132 /* DCR extended accesse */
2133 PPC_DCRX = 0x2000000000000000ULL,
2134 /* user-mode DCR access, implemented in PowerPC 460 */
2135 PPC_DCRUX = 0x4000000000000000ULL,
eaabeef2
DG		 2136 /* popcntw and popcntd instructions */
2137 PPC_POPCNTWD = 0x8000000000000000ULL,
01662f3e 2138
02d4eae4
DG		 2139#define PPC_TCG_INSNS (PPC_INSNS_BASE | PPC_POWER | PPC_POWER2 \
2140 | PPC_POWER_RTC | PPC_POWER_BR | PPC_64B \
2141 | PPC_64BX | PPC_64H | PPC_WAIT | PPC_MFTB \
2142 | PPC_602_SPEC | PPC_ISEL | PPC_POPCNTB \
2143 | PPC_STRING | PPC_FLOAT | PPC_FLOAT_EXT \
2144 | PPC_FLOAT_FSQRT | PPC_FLOAT_FRES \
2145 | PPC_FLOAT_FRSQRTE | PPC_FLOAT_FRSQRTES \
2146 | PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX \
2147 | PPC_ALTIVEC | PPC_SPE | PPC_SPE_SINGLE \
2148 | PPC_SPE_DOUBLE | PPC_MEM_TLBIA \
2149 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC \
2150 | PPC_MEM_SYNC | PPC_MEM_EIEIO \
2151 | PPC_CACHE | PPC_CACHE_ICBI \
8e33944f 2152 | PPC_CACHE_DCBZ \
02d4eae4
DG		 2153 | PPC_CACHE_DCBA | PPC_CACHE_LOCK \
2154 | PPC_EXTERN | PPC_SEGMENT | PPC_6xx_TLB \
2155 | PPC_74xx_TLB | PPC_40x_TLB | PPC_SEGMENT_64B \
2156 | PPC_SLBI | PPC_WRTEE | PPC_40x_EXCP \
2157 | PPC_405_MAC | PPC_440_SPEC | PPC_BOOKE \
2158 | PPC_MFAPIDI | PPC_TLBIVA | PPC_TLBIVAX \
2159 | PPC_4xx_COMMON | PPC_40x_ICBT | PPC_RFMCI \
2160 | PPC_RFDI | PPC_DCR | PPC_DCRX | PPC_DCRUX \
b7815375 2161 | PPC_POPCNTWD | PPC_CILDST)
02d4eae4 2162
01662f3e
AG		 2163 /* extended type values */
2164
2165 /* BookE 2.06 PowerPC specification */
2166 PPC2_BOOKE206 = 0x0000000000000001ULL,
a7342588
DG		 2167 /* VSX (extensions to Altivec / VMX) */
2168 PPC2_VSX = 0x0000000000000002ULL,
2169 /* Decimal Floating Point (DFP) */
2170 PPC2_DFP = 0x0000000000000004ULL,
3f9f6a50
AG		 2171 /* Embedded.Processor Control */
2172 PPC2_PRCNTL = 0x0000000000000008ULL,
cd6e9320
TH		 2173 /* Byte-reversed, indexed, double-word load and store */
2174 PPC2_DBRX = 0x0000000000000010ULL,
9c2627b0
AJ		 2175 /* Book I 2.05 PowerPC specification */
2176 PPC2_ISA205 = 0x0000000000000020ULL,
dbcc48fa
TM		 2177 /* VSX additions in ISA 2.07 */
2178 PPC2_VSX207 = 0x0000000000000040ULL,
86ba37ed
TM		 2179 /* ISA 2.06B bpermd */
2180 PPC2_PERM_ISA206 = 0x0000000000000080ULL,
a824bc19
TM		 2181 /* ISA 2.06B divide extended variants */
2182 PPC2_DIVE_ISA206 = 0x0000000000000100ULL,
1fa6c533
TM		 2183 /* ISA 2.06B larx/stcx. instructions */
2184 PPC2_ATOMIC_ISA206 = 0x0000000000000200ULL,
1b0bd002
TM		 2185 /* ISA 2.06B floating point integer conversion */
2186 PPC2_FP_CVT_ISA206 = 0x0000000000000400ULL,
29a0e4e9
TM		 2187 /* ISA 2.06B floating point test instructions */
2188 PPC2_FP_TST_ISA206 = 0x0000000000000800ULL,
94840e07
TM		 2189 /* ISA 2.07 bctar instruction */
2190 PPC2_BCTAR_ISA207 = 0x0000000000001000ULL,
38a85337
TM		 2191 /* ISA 2.07 load/store quadword */
2192 PPC2_LSQ_ISA207 = 0x0000000000002000ULL,
32ea54ab
TM		 2193 /* ISA 2.07 Altivec */
2194 PPC2_ALTIVEC_207 = 0x0000000000004000ULL,
df99d30d
AK		 2195 /* PowerISA 2.07 Book3s specification */
2196 PPC2_ISA207S = 0x0000000000008000ULL,
4171853c
PM		 2197 /* Double precision floating point conversion for signed integer 64 */
2198 PPC2_FP_CVT_S64 = 0x0000000000010000ULL,
f90468b6
TM		 2199 /* Transactional Memory (ISA 2.07, Book II) */
2200 PPC2_TM = 0x0000000000020000ULL,
7778a575
BH		 2201 /* Server PM instructgions (ISA 2.06, Book III) */
2202 PPC2_PM_ISA206 = 0x0000000000040000ULL,
eb640b13
ND		 2203 /* POWER ISA 3.0 */
2204 PPC2_ISA300 = 0x0000000000080000ULL,
02d4eae4 2205
74f23997 2206#define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX | \
a824bc19 2207 PPC2_ISA205 | PPC2_VSX207 | PPC2_PERM_ISA206 | \
1b0bd002 2208 PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | \
94840e07 2209 PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | \
32ea54ab 2210 PPC2_BCTAR_ISA207 | PPC2_LSQ_ISA207 | \
4171853c 2211 PPC2_ALTIVEC_207 | PPC2_ISA207S | PPC2_DFP | \
eb640b13
ND		 2212 PPC2_FP_CVT_S64 | PPC2_TM | PPC2_PM_ISA206 | \
2213 PPC2_ISA300)
c29b735c
NF		 2214};
2215
76a66253 2216/*****************************************************************************/
9a64fbe4
FB		 2217/* Memory access type :
2218 * may be needed for precise access rights control and precise exceptions.
2219 */
79aceca5 2220enum {
9a64fbe4
FB		 2221 /* 1 bit to define user level / supervisor access */
2222 ACCESS_USER = 0x00,
2223 ACCESS_SUPER = 0x01,
2224 /* Type of instruction that generated the access */
2225 ACCESS_CODE = 0x10, /* Code fetch access */
2226 ACCESS_INT = 0x20, /* Integer load/store access */
2227 ACCESS_FLOAT = 0x30, /* floating point load/store access */
2228 ACCESS_RES = 0x40, /* load/store with reservation */
2229 ACCESS_EXT = 0x50, /* external access */
2230 ACCESS_CACHE = 0x60, /* Cache manipulation */
2231};
2232
47103572
JM		 2233/* Hardware interruption sources:
2234 * all those exception can be raised simulteaneously
2235 */
e9df014c
JM		 2236/* Input pins definitions */
2237enum {
2238 /* 6xx bus input pins */
24be5ae3
JM		 2239 PPC6xx_INPUT_HRESET = 0,
2240 PPC6xx_INPUT_SRESET = 1,
2241 PPC6xx_INPUT_CKSTP_IN = 2,
2242 PPC6xx_INPUT_MCP = 3,
2243 PPC6xx_INPUT_SMI = 4,
2244 PPC6xx_INPUT_INT = 5,
d68f1306
JM		 2245 PPC6xx_INPUT_TBEN = 6,
2246 PPC6xx_INPUT_WAKEUP = 7,
2247 PPC6xx_INPUT_NB,
24be5ae3
JM		 2248};
2249
2250enum {
e9df014c 2251 /* Embedded PowerPC input pins */
24be5ae3
JM		 2252 PPCBookE_INPUT_HRESET = 0,
2253 PPCBookE_INPUT_SRESET = 1,
2254 PPCBookE_INPUT_CKSTP_IN = 2,
2255 PPCBookE_INPUT_MCP = 3,
2256 PPCBookE_INPUT_SMI = 4,
2257 PPCBookE_INPUT_INT = 5,
2258 PPCBookE_INPUT_CINT = 6,
d68f1306 2259 PPCBookE_INPUT_NB,
24be5ae3
JM		 2260};
2261
9fdc60bf
AJ		 2262enum {
2263 /* PowerPC E500 input pins */
2264 PPCE500_INPUT_RESET_CORE = 0,
2265 PPCE500_INPUT_MCK = 1,
2266 PPCE500_INPUT_CINT = 3,
2267 PPCE500_INPUT_INT = 4,
2268 PPCE500_INPUT_DEBUG = 6,
2269 PPCE500_INPUT_NB,
2270};
2271
a750fc0b 2272enum {
4e290a0b
JM		 2273 /* PowerPC 40x input pins */
2274 PPC40x_INPUT_RESET_CORE = 0,
2275 PPC40x_INPUT_RESET_CHIP = 1,
2276 PPC40x_INPUT_RESET_SYS = 2,
2277 PPC40x_INPUT_CINT = 3,
2278 PPC40x_INPUT_INT = 4,
2279 PPC40x_INPUT_HALT = 5,
2280 PPC40x_INPUT_DEBUG = 6,
2281 PPC40x_INPUT_NB,
e9df014c
JM		 2282};
2283
b4095fed
JM		 2284enum {
2285 /* RCPU input pins */
2286 PPCRCPU_INPUT_PORESET = 0,
2287 PPCRCPU_INPUT_HRESET = 1,
2288 PPCRCPU_INPUT_SRESET = 2,
2289 PPCRCPU_INPUT_IRQ0 = 3,
2290 PPCRCPU_INPUT_IRQ1 = 4,
2291 PPCRCPU_INPUT_IRQ2 = 5,
2292 PPCRCPU_INPUT_IRQ3 = 6,
2293 PPCRCPU_INPUT_IRQ4 = 7,
2294 PPCRCPU_INPUT_IRQ5 = 8,
2295 PPCRCPU_INPUT_IRQ6 = 9,
2296 PPCRCPU_INPUT_IRQ7 = 10,
2297 PPCRCPU_INPUT_NB,
2298};
2299
00af685f 2300#if defined(TARGET_PPC64)
d0dfae6e
JM		 2301enum {
2302 /* PowerPC 970 input pins */
2303 PPC970_INPUT_HRESET = 0,
2304 PPC970_INPUT_SRESET = 1,
2305 PPC970_INPUT_CKSTP = 2,
2306 PPC970_INPUT_TBEN = 3,
2307 PPC970_INPUT_MCP = 4,
2308 PPC970_INPUT_INT = 5,
2309 PPC970_INPUT_THINT = 6,
7b62a955 2310 PPC970_INPUT_NB,
9d52e907
DG		 2311};
2312
2313enum {
2314 /* POWER7 input pins */
2315 POWER7_INPUT_INT = 0,
2316 /* POWER7 probably has other inputs, but we don't care about them
2317 * for any existing machine. We can wire these up when we need
2318 * them */
2319 POWER7_INPUT_NB,
d0dfae6e 2320};
00af685f 2321#endif
d0dfae6e 2322
e9df014c 2323/* Hardware exceptions definitions */
47103572 2324enum {
e9df014c 2325 /* External hardware exception sources */
e1833e1f 2326 PPC_INTERRUPT_RESET = 0, /* Reset exception */
d68f1306
JM		 2327 PPC_INTERRUPT_WAKEUP, /* Wakeup exception */
2328 PPC_INTERRUPT_MCK, /* Machine check exception */
2329 PPC_INTERRUPT_EXT, /* External interrupt */
2330 PPC_INTERRUPT_SMI, /* System management interrupt */
2331 PPC_INTERRUPT_CEXT, /* Critical external interrupt */
2332 PPC_INTERRUPT_DEBUG, /* External debug exception */
2333 PPC_INTERRUPT_THERM, /* Thermal exception */
e9df014c 2334 /* Internal hardware exception sources */
d68f1306
JM		 2335 PPC_INTERRUPT_DECR, /* Decrementer exception */
2336 PPC_INTERRUPT_HDECR, /* Hypervisor decrementer exception */
2337 PPC_INTERRUPT_PIT, /* Programmable inteval timer interrupt */
2338 PPC_INTERRUPT_FIT, /* Fixed interval timer interrupt */
2339 PPC_INTERRUPT_WDT, /* Watchdog timer interrupt */
2340 PPC_INTERRUPT_CDOORBELL, /* Critical doorbell interrupt */
2341 PPC_INTERRUPT_DOORBELL, /* Doorbell interrupt */
2342 PPC_INTERRUPT_PERFM, /* Performance monitor interrupt */
f03a1af5
BH		 2343 PPC_INTERRUPT_HMI, /* Hypervisor Maintainance interrupt */
2344 PPC_INTERRUPT_HDOORBELL, /* Hypervisor Doorbell interrupt */
47103572
JM		 2345};
2346
6d9412ea
AK		 2347/* Processor Compatibility mask (PCR) */
2348enum {
a6a444a8
CLG		 2349 PCR_COMPAT_2_05 = PPC_BIT(62),
2350 PCR_COMPAT_2_06 = PPC_BIT(61),
2351 PCR_COMPAT_2_07 = PPC_BIT(60),
2352 PCR_COMPAT_3_00 = PPC_BIT(59),
2353 PCR_VEC_DIS = PPC_BIT(0), /* Vec. disable (bit NA since POWER8) */
2354 PCR_VSX_DIS = PPC_BIT(1), /* VSX disable (bit NA since POWER8) */
2355 PCR_TM_DIS = PPC_BIT(2), /* Trans. memory disable (POWER8) */
6d9412ea
AK		 2356};
2357
1488270e
BH		 2358/* HMER/HMEER */
2359enum {
a6a444a8
CLG		 2360 HMER_MALFUNCTION_ALERT = PPC_BIT(0),
2361 HMER_PROC_RECV_DONE = PPC_BIT(2),
2362 HMER_PROC_RECV_ERROR_MASKED = PPC_BIT(3),
2363 HMER_TFAC_ERROR = PPC_BIT(4),
2364 HMER_TFMR_PARITY_ERROR = PPC_BIT(5),
2365 HMER_XSCOM_FAIL = PPC_BIT(8),
2366 HMER_XSCOM_DONE = PPC_BIT(9),
2367 HMER_PROC_RECV_AGAIN = PPC_BIT(11),
2368 HMER_WARN_RISE = PPC_BIT(14),
2369 HMER_WARN_FALL = PPC_BIT(15),
2370 HMER_SCOM_FIR_HMI = PPC_BIT(16),
2371 HMER_TRIG_FIR_HMI = PPC_BIT(17),
2372 HMER_HYP_RESOURCE_ERR = PPC_BIT(20),
2373 HMER_XSCOM_STATUS_MASK = PPC_BITMASK(21, 23),
1488270e
BH		 2374};
2375
5c94b2a5
CLG		 2376/* Alternate Interrupt Location (AIL) */
2377enum {
2378 AIL_NONE = 0,
2379 AIL_RESERVED = 1,
2380 AIL_0001_8000 = 2,
2381 AIL_C000_0000_0000_4000 = 3,
2382};
2383
9a64fbe4
FB		 2384/*****************************************************************************/
2385
dd09c361 2386#define is_isa300(ctx) (!!(ctx->insns_flags2 & PPC2_ISA300))
00b70788
ND		 2387target_ulong cpu_read_xer(CPUPPCState *env);
2388void cpu_write_xer(CPUPPCState *env, target_ulong xer);
da91a00f 2389
1328c2bf 2390static inline void cpu_get_tb_cpu_state(CPUPPCState *env, target_ulong *pc,
89fee74a 2391 target_ulong *cs_base, uint32_t *flags)
6b917547
AL		 2392{
2393 *pc = env->nip;
2394 *cs_base = 0;
2395 *flags = env->hflags;
2396}
2397
db789c6c
BH		 2398void QEMU_NORETURN raise_exception(CPUPPCState *env, uint32_t exception);
2399void QEMU_NORETURN raise_exception_ra(CPUPPCState *env, uint32_t exception,
2400 uintptr_t raddr);
2401void QEMU_NORETURN raise_exception_err(CPUPPCState *env, uint32_t exception,
2402 uint32_t error_code);
2403void QEMU_NORETURN raise_exception_err_ra(CPUPPCState *env, uint32_t exception,
2404 uint32_t error_code, uintptr_t raddr);
2405
01662f3e 2406#if !defined(CONFIG_USER_ONLY)
1328c2bf 2407static inline int booke206_tlbm_id(CPUPPCState *env, ppcmas_tlb_t *tlbm)
01662f3e 2408{
d1e256fe 2409 uintptr_t tlbml = (uintptr_t)tlbm;
1c53accc 2410 uintptr_t tlbl = (uintptr_t)env->tlb.tlbm;
01662f3e 2411
1c53accc 2412 return (tlbml - tlbl) / sizeof(env->tlb.tlbm[0]);
01662f3e
AG		 2413}
2414
1328c2bf 2415static inline int booke206_tlb_size(CPUPPCState *env, int tlbn)
01662f3e
AG		 2416{
2417 uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2418 int r = tlbncfg & TLBnCFG_N_ENTRY;
2419 return r;
2420}
2421
1328c2bf 2422static inline int booke206_tlb_ways(CPUPPCState *env, int tlbn)
01662f3e
AG		 2423{
2424 uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2425 int r = tlbncfg >> TLBnCFG_ASSOC_SHIFT;
2426 return r;
2427}
2428
1328c2bf 2429static inline int booke206_tlbm_to_tlbn(CPUPPCState *env, ppcmas_tlb_t *tlbm)
01662f3e 2430{
d1e256fe 2431 int id = booke206_tlbm_id(env, tlbm);
01662f3e
AG		 2432 int end = 0;
2433 int i;
2434
2435 for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
2436 end += booke206_tlb_size(env, i);
2437 if (id < end) {
2438 return i;
2439 }
2440 }
2441
a47dddd7 2442 cpu_abort(CPU(ppc_env_get_cpu(env)), "Unknown TLBe: %d\n", id);
01662f3e
AG		 2443 return 0;
2444}
2445
1328c2bf 2446static inline int booke206_tlbm_to_way(CPUPPCState *env, ppcmas_tlb_t *tlb)
01662f3e 2447{
d1e256fe
AG		 2448 int tlbn = booke206_tlbm_to_tlbn(env, tlb);
2449 int tlbid = booke206_tlbm_id(env, tlb);
01662f3e
AG		 2450 return tlbid & (booke206_tlb_ways(env, tlbn) - 1);
2451}
2452
1328c2bf 2453static inline ppcmas_tlb_t *booke206_get_tlbm(CPUPPCState *env, const int tlbn,
01662f3e
AG		 2454 target_ulong ea, int way)
2455{
2456 int r;
2457 uint32_t ways = booke206_tlb_ways(env, tlbn);
786a4ea8
SH		 2458 int ways_bits = ctz32(ways);
2459 int tlb_bits = ctz32(booke206_tlb_size(env, tlbn));
01662f3e
AG		 2460 int i;
2461
2462 way &= ways - 1;
2463 ea >>= MAS2_EPN_SHIFT;
2464 ea &= (1 << (tlb_bits - ways_bits)) - 1;
2465 r = (ea << ways_bits) | way;
2466
3f162d11
AG		 2467 if (r >= booke206_tlb_size(env, tlbn)) {
2468 return NULL;
2469 }
2470
01662f3e
AG		 2471 /* bump up to tlbn index */
2472 for (i = 0; i < tlbn; i++) {
2473 r += booke206_tlb_size(env, i);
2474 }
2475
1c53accc 2476 return &env->tlb.tlbm[r];
01662f3e
AG		 2477}
2478
a1ef618a 2479/* returns bitmap of supported page sizes for a given TLB */
1328c2bf 2480static inline uint32_t booke206_tlbnps(CPUPPCState *env, const int tlbn)
a1ef618a 2481{
a1ef618a
AG		 2482 uint32_t ret = 0;
2483
3f330293
KF		 2484 if ((env->spr[SPR_MMUCFG] & MMUCFG_MAVN) == MMUCFG_MAVN_V2) {
2485 /* MAV2 */
a1ef618a
AG		 2486 ret = env->spr[SPR_BOOKE_TLB0PS + tlbn];
2487 } else {
2488 uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2489 uint32_t min = (tlbncfg & TLBnCFG_MINSIZE) >> TLBnCFG_MINSIZE_SHIFT;
2490 uint32_t max = (tlbncfg & TLBnCFG_MAXSIZE) >> TLBnCFG_MAXSIZE_SHIFT;
2491 int i;
2492 for (i = min; i <= max; i++) {
2493 ret |= (1 << (i << 1));
2494 }
2495 }
2496
2497 return ret;
2498}
2499
c449d8ba
KF		 2500static inline void booke206_fixed_size_tlbn(CPUPPCState *env, const int tlbn,
2501 ppcmas_tlb_t *tlb)
2502{
2503 uint8_t i;
2504 int32_t tsize = -1;
2505
2506 for (i = 0; i < 32; i++) {
2507 if ((env->spr[SPR_BOOKE_TLB0PS + tlbn]) & (1ULL << i)) {
2508 if (tsize == -1) {
2509 tsize = i;
2510 } else {
2511 return;
2512 }
2513 }
2514 }
2515
2516 /* TLBnPS unimplemented? Odd.. */
2517 assert(tsize != -1);
2518 tlb->mas1 &= ~MAS1_TSIZE_MASK;
2519 tlb->mas1 |= ((uint32_t)tsize) << MAS1_TSIZE_SHIFT;
2520}
2521
01662f3e
AG		 2522#endif
2523
e42a61f1
AG		 2524static inline bool msr_is_64bit(CPUPPCState *env, target_ulong msr)
2525{
2526 if (env->mmu_model == POWERPC_MMU_BOOKE206) {
2527 return msr & (1ULL << MSR_CM);
2528 }
2529
2530 return msr & (1ULL << MSR_SF);
2531}
2532
afbee712
TH		 2533/**
2534 * Check whether register rx is in the range between start and
2535 * start + nregs (as needed by the LSWX and LSWI instructions)
2536 */
2537static inline bool lsw_reg_in_range(int start, int nregs, int rx)
2538{
2539 return (start + nregs <= 32 && rx >= start && rx < start + nregs) ||
2540 (start + nregs > 32 && (rx >= start || rx < start + nregs - 32));
2541}
2542
ef96e3ae
MCA		 2543/* Accessors for FP, VMX and VSX registers */
2544static inline uint64_t *cpu_fpr_ptr(CPUPPCState *env, int i)
2545{
2546 return &env->vsr[i].u64[0];
2547}
2548
2549static inline uint64_t *cpu_vsrl_ptr(CPUPPCState *env, int i)
2550{
2551 return &env->vsr[i].u64[1];
2552}
2553
2554static inline ppc_avr_t *cpu_avr_ptr(CPUPPCState *env, int i)
2555{
2556 return &env->vsr[32 + i];
2557}
2558
1328c2bf 2559void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env);
bebabbc7 2560
376dbce0 2561void ppc_maybe_bswap_register(CPUPPCState *env, uint8_t *mem_buf, int len);
07f5a258 2562#endif /* PPC_CPU_H */
Empty description
This page took 1.512944 seconds and 4 git commands to generate.