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ppc: Fix migration of the TAR SPR
[qemu.git] / target-ppc / cpu.h
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79aceca5 1/*
3fc6c082 2 * PowerPC emulation cpu definitions for qemu.
5fafdf24 3 *
76a66253 4 * Copyright (c) 2003-2007 Jocelyn Mayer
79aceca5
FB		 5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
8167ee88 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
79aceca5
FB		 18 */
19#if !defined (__CPU_PPC_H__)
20#define __CPU_PPC_H__
21
9a78eead 22#include "qemu-common.h"
3fc6c082 23
a4f30719
JM		 24//#define PPC_EMULATE_32BITS_HYPV
25
76a66253 26#if defined (TARGET_PPC64)
3cd7d1dd 27/* PowerPC 64 definitions */
d9d7210c 28#define TARGET_LONG_BITS 64
35cdaad6 29#define TARGET_PAGE_BITS 12
3cd7d1dd 30
7826c2b2
GK		 31#define TARGET_IS_BIENDIAN 1
32
52705890
RH		 33/* Note that the official physical address space bits is 62-M where M
34 is implementation dependent. I've not looked up M for the set of
35 cpus we emulate at the system level. */
36#define TARGET_PHYS_ADDR_SPACE_BITS 62
37
38/* Note that the PPC environment architecture talks about 80 bit virtual
39 addresses, with segmentation. Obviously that's not all visible to a
40 single process, which is all we're concerned with here. */
41#ifdef TARGET_ABI32
42# define TARGET_VIRT_ADDR_SPACE_BITS 32
43#else
44# define TARGET_VIRT_ADDR_SPACE_BITS 64
45#endif
46
ad3e67d0 47#define TARGET_PAGE_BITS_64K 16
81762d6d
DG		 48#define TARGET_PAGE_BITS_16M 24
49
3cd7d1dd
JM		 50#else /* defined (TARGET_PPC64) */
51/* PowerPC 32 definitions */
d9d7210c 52#define TARGET_LONG_BITS 32
3cd7d1dd
JM		 53
54#if defined(TARGET_PPCEMB)
55/* Specific definitions for PowerPC embedded */
56/* BookE have 36 bits physical address space */
3cd7d1dd
JM		 57#if defined(CONFIG_USER_ONLY)
58/* It looks like a lot of Linux programs assume page size
59 * is 4kB long. This is evil, but we have to deal with it...
60 */
35cdaad6 61#define TARGET_PAGE_BITS 12
3cd7d1dd
JM		 62#else /* defined(CONFIG_USER_ONLY) */
63/* Pages can be 1 kB small */
64#define TARGET_PAGE_BITS 10
65#endif /* defined(CONFIG_USER_ONLY) */
66#else /* defined(TARGET_PPCEMB) */
67/* "standard" PowerPC 32 definitions */
68#define TARGET_PAGE_BITS 12
69#endif /* defined(TARGET_PPCEMB) */
70
8b242eba 71#define TARGET_PHYS_ADDR_SPACE_BITS 36
52705890
RH		 72#define TARGET_VIRT_ADDR_SPACE_BITS 32
73
3cd7d1dd 74#endif /* defined (TARGET_PPC64) */
3cf1e035 75
9349b4f9 76#define CPUArchState struct CPUPPCState
c2764719 77
022c62cb 78#include "exec/cpu-defs.h"
79aceca5 79
6b4c305c 80#include "fpu/softfloat.h"
4ecc3190 81
7f70c937 82#if defined (TARGET_PPC64)
4ecd4d16 83#define PPC_ELF_MACHINE EM_PPC64
76a66253 84#else
4ecd4d16 85#define PPC_ELF_MACHINE EM_PPC
76a66253 86#endif
9042c0e2 87
3fc6c082 88/*****************************************************************************/
a750fc0b 89/* MMU model */
c227f099
AL		 90typedef enum powerpc_mmu_t powerpc_mmu_t;
91enum powerpc_mmu_t {
add78955 92 POWERPC_MMU_UNKNOWN = 0x00000000,
a750fc0b 93 /* Standard 32 bits PowerPC MMU */
add78955 94 POWERPC_MMU_32B = 0x00000001,
a750fc0b 95 /* PowerPC 6xx MMU with software TLB */
add78955 96 POWERPC_MMU_SOFT_6xx = 0x00000002,
a750fc0b 97 /* PowerPC 74xx MMU with software TLB */
add78955 98 POWERPC_MMU_SOFT_74xx = 0x00000003,
a750fc0b 99 /* PowerPC 4xx MMU with software TLB */
add78955 100 POWERPC_MMU_SOFT_4xx = 0x00000004,
a750fc0b 101 /* PowerPC 4xx MMU with software TLB and zones protections */
add78955 102 POWERPC_MMU_SOFT_4xx_Z = 0x00000005,
b4095fed 103 /* PowerPC MMU in real mode only */
add78955 104 POWERPC_MMU_REAL = 0x00000006,
b4095fed 105 /* Freescale MPC8xx MMU model */
add78955 106 POWERPC_MMU_MPC8xx = 0x00000007,
a750fc0b 107 /* BookE MMU model */
add78955 108 POWERPC_MMU_BOOKE = 0x00000008,
01662f3e
AG		 109 /* BookE 2.06 MMU model */
110 POWERPC_MMU_BOOKE206 = 0x00000009,
faadf50e 111 /* PowerPC 601 MMU model (specific BATs format) */
add78955 112 POWERPC_MMU_601 = 0x0000000A,
00af685f 113#if defined(TARGET_PPC64)
add78955 114#define POWERPC_MMU_64 0x00010000
cdaee006 115#define POWERPC_MMU_1TSEG 0x00020000
f80872e2 116#define POWERPC_MMU_AMR 0x00040000
12de9a39 117 /* 64 bits PowerPC MMU */
add78955 118 POWERPC_MMU_64B = POWERPC_MMU_64 | 0x00000001,
aa4bb587
BH		 119 /* Architecture 2.03 and later (has LPCR) */
120 POWERPC_MMU_2_03 = POWERPC_MMU_64 | 0x00000002,
9d52e907 121 /* Architecture 2.06 variant */
f80872e2
DG		 122 POWERPC_MMU_2_06 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG
123 | POWERPC_MMU_AMR | 0x00000003,
ba3ecda0
BR		 124 /* Architecture 2.06 "degraded" (no 1T segments) */
125 POWERPC_MMU_2_06a = POWERPC_MMU_64 | POWERPC_MMU_AMR
126 | 0x00000003,
aa4bb587
BH		 127 /* Architecture 2.07 variant */
128 POWERPC_MMU_2_07 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG
129 | POWERPC_MMU_AMR | 0x00000004,
ba3ecda0
BR		 130 /* Architecture 2.07 "degraded" (no 1T segments) */
131 POWERPC_MMU_2_07a = POWERPC_MMU_64 | POWERPC_MMU_AMR
132 | 0x00000004,
00af685f 133#endif /* defined(TARGET_PPC64) */
3fc6c082
FB		 134};
135
136/*****************************************************************************/
a750fc0b 137/* Exception model */
c227f099
AL		 138typedef enum powerpc_excp_t powerpc_excp_t;
139enum powerpc_excp_t {
a750fc0b 140 POWERPC_EXCP_UNKNOWN = 0,
3fc6c082 141 /* Standard PowerPC exception model */
a750fc0b 142 POWERPC_EXCP_STD,
2662a059 143 /* PowerPC 40x exception model */
a750fc0b 144 POWERPC_EXCP_40x,
2662a059 145 /* PowerPC 601 exception model */
a750fc0b 146 POWERPC_EXCP_601,
2662a059 147 /* PowerPC 602 exception model */
a750fc0b 148 POWERPC_EXCP_602,
2662a059 149 /* PowerPC 603 exception model */
a750fc0b
JM		 150 POWERPC_EXCP_603,
151 /* PowerPC 603e exception model */
152 POWERPC_EXCP_603E,
153 /* PowerPC G2 exception model */
154 POWERPC_EXCP_G2,
2662a059 155 /* PowerPC 604 exception model */
a750fc0b 156 POWERPC_EXCP_604,
2662a059 157 /* PowerPC 7x0 exception model */
a750fc0b 158 POWERPC_EXCP_7x0,
2662a059 159 /* PowerPC 7x5 exception model */
a750fc0b 160 POWERPC_EXCP_7x5,
2662a059 161 /* PowerPC 74xx exception model */
a750fc0b 162 POWERPC_EXCP_74xx,
2662a059 163 /* BookE exception model */
a750fc0b 164 POWERPC_EXCP_BOOKE,
00af685f
JM		 165#if defined(TARGET_PPC64)
166 /* PowerPC 970 exception model */
167 POWERPC_EXCP_970,
9d52e907
DG		 168 /* POWER7 exception model */
169 POWERPC_EXCP_POWER7,
00af685f 170#endif /* defined(TARGET_PPC64) */
a750fc0b
JM		 171};
172
e1833e1f
JM		 173/*****************************************************************************/
174/* Exception vectors definitions */
175enum {
176 POWERPC_EXCP_NONE = -1,
177 /* The 64 first entries are used by the PowerPC embedded specification */
178 POWERPC_EXCP_CRITICAL = 0, /* Critical input */
179 POWERPC_EXCP_MCHECK = 1, /* Machine check exception */
180 POWERPC_EXCP_DSI = 2, /* Data storage exception */
181 POWERPC_EXCP_ISI = 3, /* Instruction storage exception */
182 POWERPC_EXCP_EXTERNAL = 4, /* External input */
183 POWERPC_EXCP_ALIGN = 5, /* Alignment exception */
184 POWERPC_EXCP_PROGRAM = 6, /* Program exception */
185 POWERPC_EXCP_FPU = 7, /* Floating-point unavailable exception */
186 POWERPC_EXCP_SYSCALL = 8, /* System call exception */
187 POWERPC_EXCP_APU = 9, /* Auxiliary processor unavailable */
188 POWERPC_EXCP_DECR = 10, /* Decrementer exception */
189 POWERPC_EXCP_FIT = 11, /* Fixed-interval timer interrupt */
190 POWERPC_EXCP_WDT = 12, /* Watchdog timer interrupt */
b4095fed
JM		 191 POWERPC_EXCP_DTLB = 13, /* Data TLB miss */
192 POWERPC_EXCP_ITLB = 14, /* Instruction TLB miss */
e1833e1f
JM		 193 POWERPC_EXCP_DEBUG = 15, /* Debug interrupt */
194 /* Vectors 16 to 31 are reserved */
e1833e1f
JM		 195 POWERPC_EXCP_SPEU = 32, /* SPE/embedded floating-point unavailable */
196 POWERPC_EXCP_EFPDI = 33, /* Embedded floating-point data interrupt */
197 POWERPC_EXCP_EFPRI = 34, /* Embedded floating-point round interrupt */
198 POWERPC_EXCP_EPERFM = 35, /* Embedded performance monitor interrupt */
199 POWERPC_EXCP_DOORI = 36, /* Embedded doorbell interrupt */
200 POWERPC_EXCP_DOORCI = 37, /* Embedded doorbell critical interrupt */
0ef654e3
AG		 201 POWERPC_EXCP_GDOORI = 38, /* Embedded guest doorbell interrupt */
202 POWERPC_EXCP_GDOORCI = 39, /* Embedded guest doorbell critical interrupt*/
203 POWERPC_EXCP_HYPPRIV = 41, /* Embedded hypervisor priv instruction */
204 /* Vectors 42 to 63 are reserved */
e1833e1f
JM		 205 /* Exceptions defined in the PowerPC server specification */
206 POWERPC_EXCP_RESET = 64, /* System reset exception */
e1833e1f
JM		 207 POWERPC_EXCP_DSEG = 65, /* Data segment exception */
208 POWERPC_EXCP_ISEG = 66, /* Instruction segment exception */
e1833e1f 209 POWERPC_EXCP_HDECR = 67, /* Hypervisor decrementer exception */
e1833e1f 210 POWERPC_EXCP_TRACE = 68, /* Trace exception */
e1833e1f
JM		 211 POWERPC_EXCP_HDSI = 69, /* Hypervisor data storage exception */
212 POWERPC_EXCP_HISI = 70, /* Hypervisor instruction storage exception */
213 POWERPC_EXCP_HDSEG = 71, /* Hypervisor data segment exception */
214 POWERPC_EXCP_HISEG = 72, /* Hypervisor instruction segment exception */
e1833e1f
JM		 215 POWERPC_EXCP_VPU = 73, /* Vector unavailable exception */
216 /* 40x specific exceptions */
217 POWERPC_EXCP_PIT = 74, /* Programmable interval timer interrupt */
218 /* 601 specific exceptions */
219 POWERPC_EXCP_IO = 75, /* IO error exception */
220 POWERPC_EXCP_RUNM = 76, /* Run mode exception */
221 /* 602 specific exceptions */
222 POWERPC_EXCP_EMUL = 77, /* Emulation trap exception */
223 /* 602/603 specific exceptions */
b4095fed 224 POWERPC_EXCP_IFTLB = 78, /* Instruction fetch TLB miss */
e1833e1f
JM		 225 POWERPC_EXCP_DLTLB = 79, /* Data load TLB miss */
226 POWERPC_EXCP_DSTLB = 80, /* Data store TLB miss */
227 /* Exceptions available on most PowerPC */
228 POWERPC_EXCP_FPA = 81, /* Floating-point assist exception */
b4095fed
JM		 229 POWERPC_EXCP_DABR = 82, /* Data address breakpoint */
230 POWERPC_EXCP_IABR = 83, /* Instruction address breakpoint */
231 POWERPC_EXCP_SMI = 84, /* System management interrupt */
232 POWERPC_EXCP_PERFM = 85, /* Embedded performance monitor interrupt */
e1833e1f 233 /* 7xx/74xx specific exceptions */
b4095fed 234 POWERPC_EXCP_THERM = 86, /* Thermal interrupt */
e1833e1f 235 /* 74xx specific exceptions */
b4095fed 236 POWERPC_EXCP_VPUA = 87, /* Vector assist exception */
e1833e1f 237 /* 970FX specific exceptions */
b4095fed
JM		 238 POWERPC_EXCP_SOFTP = 88, /* Soft patch exception */
239 POWERPC_EXCP_MAINT = 89, /* Maintenance exception */
5b46d07d 240 /* Freescale embedded cores specific exceptions */
b4095fed
JM		 241 POWERPC_EXCP_MEXTBR = 90, /* Maskable external breakpoint */
242 POWERPC_EXCP_NMEXTBR = 91, /* Non maskable external breakpoint */
243 POWERPC_EXCP_ITLBE = 92, /* Instruction TLB error */
244 POWERPC_EXCP_DTLBE = 93, /* Data TLB error */
1f29871c
TM		 245 /* VSX Unavailable (Power ISA 2.06 and later) */
246 POWERPC_EXCP_VSXU = 94, /* VSX Unavailable */
7019cb3d 247 POWERPC_EXCP_FU = 95, /* Facility Unavailable */
e1833e1f
JM		 248 /* EOL */
249 POWERPC_EXCP_NB = 96,
5cbdb3a3 250 /* QEMU exceptions: used internally during code translation */
e1833e1f
JM		 251 POWERPC_EXCP_STOP = 0x200, /* stop translation */
252 POWERPC_EXCP_BRANCH = 0x201, /* branch instruction */
5cbdb3a3 253 /* QEMU exceptions: special cases we want to stop translation */
e1833e1f
JM		 254 POWERPC_EXCP_SYNC = 0x202, /* context synchronizing instruction */
255 POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only */
4425265b 256 POWERPC_EXCP_STCX = 0x204 /* Conditional stores in user mode */
e1833e1f
JM		 257};
258
e1833e1f
JM		 259/* Exceptions error codes */
260enum {
261 /* Exception subtypes for POWERPC_EXCP_ALIGN */
262 POWERPC_EXCP_ALIGN_FP = 0x01, /* FP alignment exception */
263 POWERPC_EXCP_ALIGN_LST = 0x02, /* Unaligned mult/extern load/store */
264 POWERPC_EXCP_ALIGN_LE = 0x03, /* Multiple little-endian access */
265 POWERPC_EXCP_ALIGN_PROT = 0x04, /* Access cross protection boundary */
266 POWERPC_EXCP_ALIGN_BAT = 0x05, /* Access cross a BAT/seg boundary */
267 POWERPC_EXCP_ALIGN_CACHE = 0x06, /* Impossible dcbz access */
268 /* Exception subtypes for POWERPC_EXCP_PROGRAM */
269 /* FP exceptions */
270 POWERPC_EXCP_FP = 0x10,
271 POWERPC_EXCP_FP_OX = 0x01, /* FP overflow */
272 POWERPC_EXCP_FP_UX = 0x02, /* FP underflow */
273 POWERPC_EXCP_FP_ZX = 0x03, /* FP divide by zero */
274 POWERPC_EXCP_FP_XX = 0x04, /* FP inexact */
7c58044c 275 POWERPC_EXCP_FP_VXSNAN = 0x05, /* FP invalid SNaN op */
e1833e1f
JM		 276 POWERPC_EXCP_FP_VXISI = 0x06, /* FP invalid infinite subtraction */
277 POWERPC_EXCP_FP_VXIDI = 0x07, /* FP invalid infinite divide */
278 POWERPC_EXCP_FP_VXZDZ = 0x08, /* FP invalid zero divide */
279 POWERPC_EXCP_FP_VXIMZ = 0x09, /* FP invalid infinite * zero */
280 POWERPC_EXCP_FP_VXVC = 0x0A, /* FP invalid compare */
281 POWERPC_EXCP_FP_VXSOFT = 0x0B, /* FP invalid operation */
282 POWERPC_EXCP_FP_VXSQRT = 0x0C, /* FP invalid square root */
283 POWERPC_EXCP_FP_VXCVI = 0x0D, /* FP invalid integer conversion */
284 /* Invalid instruction */
285 POWERPC_EXCP_INVAL = 0x20,
286 POWERPC_EXCP_INVAL_INVAL = 0x01, /* Invalid instruction */
287 POWERPC_EXCP_INVAL_LSWX = 0x02, /* Invalid lswx instruction */
288 POWERPC_EXCP_INVAL_SPR = 0x03, /* Invalid SPR access */
289 POWERPC_EXCP_INVAL_FP = 0x04, /* Unimplemented mandatory fp instr */
290 /* Privileged instruction */
291 POWERPC_EXCP_PRIV = 0x30,
292 POWERPC_EXCP_PRIV_OPC = 0x01, /* Privileged operation exception */
293 POWERPC_EXCP_PRIV_REG = 0x02, /* Privileged register exception */
294 /* Trap */
295 POWERPC_EXCP_TRAP = 0x40,
296};
297
a750fc0b
JM		 298/*****************************************************************************/
299/* Input pins model */
c227f099
AL		 300typedef enum powerpc_input_t powerpc_input_t;
301enum powerpc_input_t {
a750fc0b 302 PPC_FLAGS_INPUT_UNKNOWN = 0,
2662a059 303 /* PowerPC 6xx bus */
a750fc0b 304 PPC_FLAGS_INPUT_6xx,
2662a059 305 /* BookE bus */
a750fc0b
JM		 306 PPC_FLAGS_INPUT_BookE,
307 /* PowerPC 405 bus */
308 PPC_FLAGS_INPUT_405,
2662a059 309 /* PowerPC 970 bus */
a750fc0b 310 PPC_FLAGS_INPUT_970,
9d52e907
DG		 311 /* PowerPC POWER7 bus */
312 PPC_FLAGS_INPUT_POWER7,
a750fc0b
JM		 313 /* PowerPC 401 bus */
314 PPC_FLAGS_INPUT_401,
b4095fed
JM		 315 /* Freescale RCPU bus */
316 PPC_FLAGS_INPUT_RCPU,
3fc6c082
FB		 317};
318
a750fc0b 319#define PPC_INPUT(env) (env->bus_model)
3fc6c082 320
be147d08 321/*****************************************************************************/
c227f099 322typedef struct opc_handler_t opc_handler_t;
79aceca5 323
3fc6c082
FB		 324/*****************************************************************************/
325/* Types used to describe some PowerPC registers */
326typedef struct CPUPPCState CPUPPCState;
69b058c8 327typedef struct DisasContext DisasContext;
c227f099
AL		 328typedef struct ppc_tb_t ppc_tb_t;
329typedef struct ppc_spr_t ppc_spr_t;
330typedef struct ppc_dcr_t ppc_dcr_t;
331typedef union ppc_avr_t ppc_avr_t;
332typedef union ppc_tlb_t ppc_tlb_t;
76a66253 333
3fc6c082 334/* SPR access micro-ops generations callbacks */
c227f099 335struct ppc_spr_t {
69b058c8
PB		 336 void (*uea_read)(DisasContext *ctx, int gpr_num, int spr_num);
337 void (*uea_write)(DisasContext *ctx, int spr_num, int gpr_num);
76a66253 338#if !defined(CONFIG_USER_ONLY)
69b058c8
PB		 339 void (*oea_read)(DisasContext *ctx, int gpr_num, int spr_num);
340 void (*oea_write)(DisasContext *ctx, int spr_num, int gpr_num);
341 void (*hea_read)(DisasContext *ctx, int gpr_num, int spr_num);
342 void (*hea_write)(DisasContext *ctx, int spr_num, int gpr_num);
76a66253 343#endif
b55266b5 344 const char *name;
d197fdbc 345 target_ulong default_value;
d67d40ea
DG		 346#ifdef CONFIG_KVM
347 /* We (ab)use the fact that all the SPRs will have ids for the
348 * ONE_REG interface will have KVM_REG_PPC to use 0 as meaning,
349 * don't sync this */
350 uint64_t one_reg_id;
351#endif
3fc6c082
FB		 352};
353
354/* Altivec registers (128 bits) */
c227f099 355union ppc_avr_t {
0f6fbcbc 356 float32 f[4];
a9d9eb8f
JM		 357 uint8_t u8[16];
358 uint16_t u16[8];
359 uint32_t u32[4];
ab5f265d
AJ		 360 int8_t s8[16];
361 int16_t s16[8];
362 int32_t s32[4];
a9d9eb8f 363 uint64_t u64[2];
bb527533
TM		 364 int64_t s64[2];
365#ifdef CONFIG_INT128
366 __uint128_t u128;
367#endif
3fc6c082 368};
9fddaa0c 369
3c7b48b7 370#if !defined(CONFIG_USER_ONLY)
3fc6c082 371/* Software TLB cache */
c227f099
AL		 372typedef struct ppc6xx_tlb_t ppc6xx_tlb_t;
373struct ppc6xx_tlb_t {
76a66253
JM		 374 target_ulong pte0;
375 target_ulong pte1;
376 target_ulong EPN;
1d0a48fb
JM		 377};
378
c227f099
AL		 379typedef struct ppcemb_tlb_t ppcemb_tlb_t;
380struct ppcemb_tlb_t {
b162d02e 381 uint64_t RPN;
1d0a48fb 382 target_ulong EPN;
76a66253 383 target_ulong PID;
c55e9aef
JM		 384 target_ulong size;
385 uint32_t prot;
386 uint32_t attr; /* Storage attributes */
1d0a48fb
JM		 387};
388
d1e256fe
AG		 389typedef struct ppcmas_tlb_t {
390 uint32_t mas8;
391 uint32_t mas1;
392 uint64_t mas2;
393 uint64_t mas7_3;
394} ppcmas_tlb_t;
395
c227f099 396union ppc_tlb_t {
1c53accc
AG		 397 ppc6xx_tlb_t *tlb6;
398 ppcemb_tlb_t *tlbe;
399 ppcmas_tlb_t *tlbm;
3fc6c082 400};
1c53accc
AG		 401
402/* possible TLB variants */
403#define TLB_NONE 0
404#define TLB_6XX 1
405#define TLB_EMB 2
406#define TLB_MAS 3
3c7b48b7 407#endif
3fc6c082 408
bb593904
DG		 409#define SDR_32_HTABORG 0xFFFF0000UL
410#define SDR_32_HTABMASK 0x000001FFUL
411
412#if defined(TARGET_PPC64)
413#define SDR_64_HTABORG 0xFFFFFFFFFFFC0000ULL
414#define SDR_64_HTABSIZE 0x000000000000001FULL
415#endif /* defined(TARGET_PPC64 */
416
c227f099
AL		 417typedef struct ppc_slb_t ppc_slb_t;
418struct ppc_slb_t {
81762d6d
DG		 419 uint64_t esid;
420 uint64_t vsid;
cd6a9bb6 421 const struct ppc_one_seg_page_size *sps;
8eee0af9
BS		 422};
423
d83af167 424#define MAX_SLB_ENTRIES 64
81762d6d
DG		 425#define SEGMENT_SHIFT_256M 28
426#define SEGMENT_MASK_256M (~((1ULL << SEGMENT_SHIFT_256M) - 1))
427
cdaee006
DG		 428#define SEGMENT_SHIFT_1T 40
429#define SEGMENT_MASK_1T (~((1ULL << SEGMENT_SHIFT_1T) - 1))
430
431
3fc6c082
FB		 432/*****************************************************************************/
433/* Machine state register bits definition */
76a66253 434#define MSR_SF 63 /* Sixty-four-bit mode hflags */
bd928eba 435#define MSR_TAG 62 /* Tag-active mode (POWERx ?) */
3fc6c082 436#define MSR_ISF 61 /* Sixty-four-bit interrupt mode on 630 */
a4f30719 437#define MSR_SHV 60 /* hypervisor state hflags */
cdcdda27
AK		 438#define MSR_TS0 34 /* Transactional state, 2 bits (Book3s) */
439#define MSR_TS1 33
440#define MSR_TM 32 /* Transactional Memory Available (Book3s) */
363be49c
JM		 441#define MSR_CM 31 /* Computation mode for BookE hflags */
442#define MSR_ICM 30 /* Interrupt computation mode for BookE */
a4f30719 443#define MSR_THV 29 /* hypervisor state for 32 bits PowerPC hflags */
71afeb61 444#define MSR_GS 28 /* guest state for BookE */
363be49c 445#define MSR_UCLE 26 /* User-mode cache lock enable for BookE */
d26bfc9a
JM		 446#define MSR_VR 25 /* altivec available x hflags */
447#define MSR_SPE 25 /* SPE enable for BookE x hflags */
76a66253 448#define MSR_AP 23 /* Access privilege state on 602 hflags */
1f29871c 449#define MSR_VSX 23 /* Vector Scalar Extension (ISA 2.06 and later) x hflags */
76a66253 450#define MSR_SA 22 /* Supervisor access mode on 602 hflags */
3fc6c082 451#define MSR_KEY 19 /* key bit on 603e */
25ba3a68 452#define MSR_POW 18 /* Power management */
d26bfc9a
JM		 453#define MSR_TGPR 17 /* TGPR usage on 602/603 x */
454#define MSR_CE 17 /* Critical interrupt enable on embedded PowerPC x */
3fc6c082
FB		 455#define MSR_ILE 16 /* Interrupt little-endian mode */
456#define MSR_EE 15 /* External interrupt enable */
76a66253
JM		 457#define MSR_PR 14 /* Problem state hflags */
458#define MSR_FP 13 /* Floating point available hflags */
3fc6c082 459#define MSR_ME 12 /* Machine check interrupt enable */
76a66253 460#define MSR_FE0 11 /* Floating point exception mode 0 hflags */
d26bfc9a
JM		 461#define MSR_SE 10 /* Single-step trace enable x hflags */
462#define MSR_DWE 10 /* Debug wait enable on 405 x */
463#define MSR_UBLE 10 /* User BTB lock enable on e500 x */
464#define MSR_BE 9 /* Branch trace enable x hflags */
465#define MSR_DE 9 /* Debug interrupts enable on embedded PowerPC x */
76a66253 466#define MSR_FE1 8 /* Floating point exception mode 1 hflags */
3fc6c082 467#define MSR_AL 7 /* AL bit on POWER */
0411a972 468#define MSR_EP 6 /* Exception prefix on 601 */
3fc6c082 469#define MSR_IR 5 /* Instruction relocate */
3fc6c082 470#define MSR_DR 4 /* Data relocate */
25ba3a68 471#define MSR_PE 3 /* Protection enable on 403 */
d26bfc9a
JM		 472#define MSR_PX 2 /* Protection exclusive on 403 x */
473#define MSR_PMM 2 /* Performance monitor mark on POWER x */
474#define MSR_RI 1 /* Recoverable interrupt 1 */
475#define MSR_LE 0 /* Little-endian mode 1 hflags */
0411a972 476
1e0c7e55 477#define LPCR_ILE (1 << (63-38))
d5ac4f54
AK		 478#define LPCR_AIL_SHIFT (63-40) /* Alternate interrupt location */
479#define LPCR_AIL (3 << LPCR_AIL_SHIFT)
1e0c7e55 480
0411a972
JM		 481#define msr_sf ((env->msr >> MSR_SF) & 1)
482#define msr_isf ((env->msr >> MSR_ISF) & 1)
a4f30719 483#define msr_shv ((env->msr >> MSR_SHV) & 1)
0411a972
JM		 484#define msr_cm ((env->msr >> MSR_CM) & 1)
485#define msr_icm ((env->msr >> MSR_ICM) & 1)
a4f30719 486#define msr_thv ((env->msr >> MSR_THV) & 1)
71afeb61 487#define msr_gs ((env->msr >> MSR_GS) & 1)
0411a972
JM		 488#define msr_ucle ((env->msr >> MSR_UCLE) & 1)
489#define msr_vr ((env->msr >> MSR_VR) & 1)
f9320410 490#define msr_spe ((env->msr >> MSR_SPE) & 1)
0411a972 491#define msr_ap ((env->msr >> MSR_AP) & 1)
1f29871c 492#define msr_vsx ((env->msr >> MSR_VSX) & 1)
0411a972
JM		 493#define msr_sa ((env->msr >> MSR_SA) & 1)
494#define msr_key ((env->msr >> MSR_KEY) & 1)
495#define msr_pow ((env->msr >> MSR_POW) & 1)
496#define msr_tgpr ((env->msr >> MSR_TGPR) & 1)
497#define msr_ce ((env->msr >> MSR_CE) & 1)
498#define msr_ile ((env->msr >> MSR_ILE) & 1)
499#define msr_ee ((env->msr >> MSR_EE) & 1)
500#define msr_pr ((env->msr >> MSR_PR) & 1)
501#define msr_fp ((env->msr >> MSR_FP) & 1)
502#define msr_me ((env->msr >> MSR_ME) & 1)
503#define msr_fe0 ((env->msr >> MSR_FE0) & 1)
504#define msr_se ((env->msr >> MSR_SE) & 1)
505#define msr_dwe ((env->msr >> MSR_DWE) & 1)
506#define msr_uble ((env->msr >> MSR_UBLE) & 1)
507#define msr_be ((env->msr >> MSR_BE) & 1)
508#define msr_de ((env->msr >> MSR_DE) & 1)
509#define msr_fe1 ((env->msr >> MSR_FE1) & 1)
510#define msr_al ((env->msr >> MSR_AL) & 1)
511#define msr_ep ((env->msr >> MSR_EP) & 1)
512#define msr_ir ((env->msr >> MSR_IR) & 1)
513#define msr_dr ((env->msr >> MSR_DR) & 1)
514#define msr_pe ((env->msr >> MSR_PE) & 1)
515#define msr_px ((env->msr >> MSR_PX) & 1)
516#define msr_pmm ((env->msr >> MSR_PMM) & 1)
517#define msr_ri ((env->msr >> MSR_RI) & 1)
518#define msr_le ((env->msr >> MSR_LE) & 1)
cdcdda27
AK		 519#define msr_ts ((env->msr >> MSR_TS1) & 3)
520#define msr_tm ((env->msr >> MSR_TM) & 1)
521
a4f30719
JM		 522/* Hypervisor bit is more specific */
523#if defined(TARGET_PPC64)
524#define MSR_HVB (1ULL << MSR_SHV)
525#define msr_hv msr_shv
526#else
527#if defined(PPC_EMULATE_32BITS_HYPV)
528#define MSR_HVB (1ULL << MSR_THV)
529#define msr_hv msr_thv
a4f30719
JM		 530#else
531#define MSR_HVB (0ULL)
532#define msr_hv (0)
533#endif
534#endif
79aceca5 535
7019cb3d
AK		 536/* Facility Status and Control (FSCR) bits */
537#define FSCR_EBB (63 - 56) /* Event-Based Branch Facility */
538#define FSCR_TAR (63 - 55) /* Target Address Register */
539/* Interrupt cause mask and position in FSCR. HFSCR has the same format */
540#define FSCR_IC_MASK (0xFFULL)
541#define FSCR_IC_POS (63 - 7)
542#define FSCR_IC_DSCR_SPR3 2
543#define FSCR_IC_PMU 3
544#define FSCR_IC_BHRB 4
545#define FSCR_IC_TM 5
546#define FSCR_IC_EBB 7
547#define FSCR_IC_TAR 8
548
a586e548 549/* Exception state register bits definition */
542df9bf
AG		 550#define ESR_PIL (1 << (63 - 36)) /* Illegal Instruction */
551#define ESR_PPR (1 << (63 - 37)) /* Privileged Instruction */
552#define ESR_PTR (1 << (63 - 38)) /* Trap */
553#define ESR_FP (1 << (63 - 39)) /* Floating-Point Operation */
554#define ESR_ST (1 << (63 - 40)) /* Store Operation */
555#define ESR_AP (1 << (63 - 44)) /* Auxiliary Processor Operation */
556#define ESR_PUO (1 << (63 - 45)) /* Unimplemented Operation */
557#define ESR_BO (1 << (63 - 46)) /* Byte Ordering */
558#define ESR_PIE (1 << (63 - 47)) /* Imprecise exception */
559#define ESR_DATA (1 << (63 - 53)) /* Data Access (Embedded page table) */
560#define ESR_TLBI (1 << (63 - 54)) /* TLB Ineligible (Embedded page table) */
561#define ESR_PT (1 << (63 - 55)) /* Page Table (Embedded page table) */
562#define ESR_SPV (1 << (63 - 56)) /* SPE/VMX operation */
563#define ESR_EPID (1 << (63 - 57)) /* External Process ID operation */
564#define ESR_VLEMI (1 << (63 - 58)) /* VLE operation */
565#define ESR_MIF (1 << (63 - 62)) /* Misaligned instruction (VLE) */
a586e548 566
aac86237
TM		 567/* Transaction EXception And Summary Register bits */
568#define TEXASR_FAILURE_PERSISTENT (63 - 7)
569#define TEXASR_DISALLOWED (63 - 8)
570#define TEXASR_NESTING_OVERFLOW (63 - 9)
571#define TEXASR_FOOTPRINT_OVERFLOW (63 - 10)
572#define TEXASR_SELF_INDUCED_CONFLICT (63 - 11)
573#define TEXASR_NON_TRANSACTIONAL_CONFLICT (63 - 12)
574#define TEXASR_TRANSACTION_CONFLICT (63 - 13)
575#define TEXASR_TRANSLATION_INVALIDATION_CONFLICT (63 - 14)
576#define TEXASR_IMPLEMENTATION_SPECIFIC (63 - 15)
577#define TEXASR_INSTRUCTION_FETCH_CONFLICT (63 - 16)
578#define TEXASR_ABORT (63 - 31)
579#define TEXASR_SUSPENDED (63 - 32)
580#define TEXASR_PRIVILEGE_HV (63 - 34)
581#define TEXASR_PRIVILEGE_PR (63 - 35)
582#define TEXASR_FAILURE_SUMMARY (63 - 36)
583#define TEXASR_TFIAR_EXACT (63 - 37)
584#define TEXASR_ROT (63 - 38)
585#define TEXASR_TRANSACTION_LEVEL (63 - 52) /* 12 bits */
586
d26bfc9a 587enum {
4018bae9 588 POWERPC_FLAG_NONE = 0x00000000,
d26bfc9a 589 /* Flag for MSR bit 25 signification (VRE/SPE) */
4018bae9
JM		 590 POWERPC_FLAG_SPE = 0x00000001,
591 POWERPC_FLAG_VRE = 0x00000002,
d26bfc9a 592 /* Flag for MSR bit 17 signification (TGPR/CE) */
4018bae9
JM		 593 POWERPC_FLAG_TGPR = 0x00000004,
594 POWERPC_FLAG_CE = 0x00000008,
d26bfc9a 595 /* Flag for MSR bit 10 signification (SE/DWE/UBLE) */
4018bae9
JM		 596 POWERPC_FLAG_SE = 0x00000010,
597 POWERPC_FLAG_DWE = 0x00000020,
598 POWERPC_FLAG_UBLE = 0x00000040,
d26bfc9a 599 /* Flag for MSR bit 9 signification (BE/DE) */
4018bae9
JM		 600 POWERPC_FLAG_BE = 0x00000080,
601 POWERPC_FLAG_DE = 0x00000100,
a4f30719 602 /* Flag for MSR bit 2 signification (PX/PMM) */
4018bae9
JM		 603 POWERPC_FLAG_PX = 0x00000200,
604 POWERPC_FLAG_PMM = 0x00000400,
605 /* Flag for special features */
606 /* Decrementer clock: RTC clock (POWER, 601) or bus clock */
607 POWERPC_FLAG_RTC_CLK = 0x00010000,
608 POWERPC_FLAG_BUS_CLK = 0x00020000,
697ab892
DG		 609 /* Has CFAR */
610 POWERPC_FLAG_CFAR = 0x00040000,
74f23997
TM		 611 /* Has VSX */
612 POWERPC_FLAG_VSX = 0x00080000,
e43668a7
TM		 613 /* Has Transaction Memory (ISA 2.07) */
614 POWERPC_FLAG_TM = 0x00100000,
d26bfc9a
JM		 615};
616
7c58044c
JM		 617/*****************************************************************************/
618/* Floating point status and control register */
619#define FPSCR_FX 31 /* Floating-point exception summary */
620#define FPSCR_FEX 30 /* Floating-point enabled exception summary */
621#define FPSCR_VX 29 /* Floating-point invalid operation exception summ. */
622#define FPSCR_OX 28 /* Floating-point overflow exception */
623#define FPSCR_UX 27 /* Floating-point underflow exception */
624#define FPSCR_ZX 26 /* Floating-point zero divide exception */
625#define FPSCR_XX 25 /* Floating-point inexact exception */
626#define FPSCR_VXSNAN 24 /* Floating-point invalid operation exception (sNan) */
627#define FPSCR_VXISI 23 /* Floating-point invalid operation exception (inf) */
628#define FPSCR_VXIDI 22 /* Floating-point invalid operation exception (inf) */
629#define FPSCR_VXZDZ 21 /* Floating-point invalid operation exception (zero) */
630#define FPSCR_VXIMZ 20 /* Floating-point invalid operation exception (inf) */
631#define FPSCR_VXVC 19 /* Floating-point invalid operation exception (comp) */
632#define FPSCR_FR 18 /* Floating-point fraction rounded */
633#define FPSCR_FI 17 /* Floating-point fraction inexact */
634#define FPSCR_C 16 /* Floating-point result class descriptor */
635#define FPSCR_FL 15 /* Floating-point less than or negative */
636#define FPSCR_FG 14 /* Floating-point greater than or negative */
637#define FPSCR_FE 13 /* Floating-point equal or zero */
638#define FPSCR_FU 12 /* Floating-point unordered or NaN */
639#define FPSCR_FPCC 12 /* Floating-point condition code */
640#define FPSCR_FPRF 12 /* Floating-point result flags */
641#define FPSCR_VXSOFT 10 /* Floating-point invalid operation exception (soft) */
642#define FPSCR_VXSQRT 9 /* Floating-point invalid operation exception (sqrt) */
643#define FPSCR_VXCVI 8 /* Floating-point invalid operation exception (int) */
644#define FPSCR_VE 7 /* Floating-point invalid operation exception enable */
645#define FPSCR_OE 6 /* Floating-point overflow exception enable */
646#define FPSCR_UE 5 /* Floating-point undeflow exception enable */
647#define FPSCR_ZE 4 /* Floating-point zero divide exception enable */
648#define FPSCR_XE 3 /* Floating-point inexact exception enable */
649#define FPSCR_NI 2 /* Floating-point non-IEEE mode */
650#define FPSCR_RN1 1
651#define FPSCR_RN 0 /* Floating-point rounding control */
652#define fpscr_fex (((env->fpscr) >> FPSCR_FEX) & 0x1)
653#define fpscr_vx (((env->fpscr) >> FPSCR_VX) & 0x1)
654#define fpscr_ox (((env->fpscr) >> FPSCR_OX) & 0x1)
655#define fpscr_ux (((env->fpscr) >> FPSCR_UX) & 0x1)
656#define fpscr_zx (((env->fpscr) >> FPSCR_ZX) & 0x1)
657#define fpscr_xx (((env->fpscr) >> FPSCR_XX) & 0x1)
658#define fpscr_vxsnan (((env->fpscr) >> FPSCR_VXSNAN) & 0x1)
659#define fpscr_vxisi (((env->fpscr) >> FPSCR_VXISI) & 0x1)
660#define fpscr_vxidi (((env->fpscr) >> FPSCR_VXIDI) & 0x1)
661#define fpscr_vxzdz (((env->fpscr) >> FPSCR_VXZDZ) & 0x1)
662#define fpscr_vximz (((env->fpscr) >> FPSCR_VXIMZ) & 0x1)
663#define fpscr_vxvc (((env->fpscr) >> FPSCR_VXVC) & 0x1)
664#define fpscr_fpcc (((env->fpscr) >> FPSCR_FPCC) & 0xF)
665#define fpscr_vxsoft (((env->fpscr) >> FPSCR_VXSOFT) & 0x1)
666#define fpscr_vxsqrt (((env->fpscr) >> FPSCR_VXSQRT) & 0x1)
667#define fpscr_vxcvi (((env->fpscr) >> FPSCR_VXCVI) & 0x1)
668#define fpscr_ve (((env->fpscr) >> FPSCR_VE) & 0x1)
669#define fpscr_oe (((env->fpscr) >> FPSCR_OE) & 0x1)
670#define fpscr_ue (((env->fpscr) >> FPSCR_UE) & 0x1)
671#define fpscr_ze (((env->fpscr) >> FPSCR_ZE) & 0x1)
672#define fpscr_xe (((env->fpscr) >> FPSCR_XE) & 0x1)
673#define fpscr_ni (((env->fpscr) >> FPSCR_NI) & 0x1)
674#define fpscr_rn (((env->fpscr) >> FPSCR_RN) & 0x3)
675/* Invalid operation exception summary */
676#define fpscr_ix ((env->fpscr) & ((1 << FPSCR_VXSNAN) | (1 << FPSCR_VXISI) | \
677 (1 << FPSCR_VXIDI) | (1 << FPSCR_VXZDZ) | \
678 (1 << FPSCR_VXIMZ) | (1 << FPSCR_VXVC) | \
679 (1 << FPSCR_VXSOFT) | (1 << FPSCR_VXSQRT) | \
680 (1 << FPSCR_VXCVI)))
681/* exception summary */
682#define fpscr_ex (((env->fpscr) >> FPSCR_XX) & 0x1F)
683/* enabled exception summary */
684#define fpscr_eex (((env->fpscr) >> FPSCR_XX) & ((env->fpscr) >> FPSCR_XE) & \
685 0x1F)
686
dbdc13a1
MS		 687#define FP_FX (1ull << FPSCR_FX)
688#define FP_FEX (1ull << FPSCR_FEX)
fc03cfef 689#define FP_VX (1ull << FPSCR_VX)
dbdc13a1 690#define FP_OX (1ull << FPSCR_OX)
dbdc13a1 691#define FP_UX (1ull << FPSCR_UX)
dbdc13a1 692#define FP_ZX (1ull << FPSCR_ZX)
fc03cfef 693#define FP_XX (1ull << FPSCR_XX)
dbdc13a1
MS		 694#define FP_VXSNAN (1ull << FPSCR_VXSNAN)
695#define FP_VXISI (1ull << FPSCR_VXISI)
dbdc13a1 696#define FP_VXIDI (1ull << FPSCR_VXIDI)
fc03cfef
JC		 697#define FP_VXZDZ (1ull << FPSCR_VXZDZ)
698#define FP_VXIMZ (1ull << FPSCR_VXIMZ)
dbdc13a1 699#define FP_VXVC (1ull << FPSCR_VXVC)
fc03cfef
JC		 700#define FP_FR (1ull << FSPCR_FR)
701#define FP_FI (1ull << FPSCR_FI)
702#define FP_C (1ull << FPSCR_C)
703#define FP_FL (1ull << FPSCR_FL)
704#define FP_FG (1ull << FPSCR_FG)
705#define FP_FE (1ull << FPSCR_FE)
706#define FP_FU (1ull << FPSCR_FU)
707#define FP_FPCC (FP_FL | FP_FG | FP_FE | FP_FU)
708#define FP_FPRF (FP_C | FP_FL | FP_FG | FP_FE | FP_FU)
709#define FP_VXSOFT (1ull << FPSCR_VXSOFT)
710#define FP_VXSQRT (1ull << FPSCR_VXSQRT)
dbdc13a1
MS		 711#define FP_VXCVI (1ull << FPSCR_VXCVI)
712#define FP_VE (1ull << FPSCR_VE)
fc03cfef
JC		 713#define FP_OE (1ull << FPSCR_OE)
714#define FP_UE (1ull << FPSCR_UE)
715#define FP_ZE (1ull << FPSCR_ZE)
716#define FP_XE (1ull << FPSCR_XE)
717#define FP_NI (1ull << FPSCR_NI)
718#define FP_RN1 (1ull << FPSCR_RN1)
719#define FP_RN (1ull << FPSCR_RN)
dbdc13a1 720
d1277156
JC		 721/* the exception bits which can be cleared by mcrfs - includes FX */
722#define FP_EX_CLEAR_BITS (FP_FX | FP_OX | FP_UX | FP_ZX | \
723 FP_XX | FP_VXSNAN | FP_VXISI | FP_VXIDI | \
724 FP_VXZDZ | FP_VXIMZ | FP_VXVC | FP_VXSOFT | \
725 FP_VXSQRT | FP_VXCVI)
726
7c58044c 727/*****************************************************************************/
6fa724a3
AJ		 728/* Vector status and control register */
729#define VSCR_NJ 16 /* Vector non-java */
730#define VSCR_SAT 0 /* Vector saturation */
731#define vscr_nj (((env->vscr) >> VSCR_NJ) & 0x1)
732#define vscr_sat (((env->vscr) >> VSCR_SAT) & 0x1)
733
01662f3e
AG		 734/*****************************************************************************/
735/* BookE e500 MMU registers */
736
737#define MAS0_NV_SHIFT 0
738#define MAS0_NV_MASK (0xfff << MAS0_NV_SHIFT)
739
740#define MAS0_WQ_SHIFT 12
741#define MAS0_WQ_MASK (3 << MAS0_WQ_SHIFT)
742/* Write TLB entry regardless of reservation */
743#define MAS0_WQ_ALWAYS (0 << MAS0_WQ_SHIFT)
744/* Write TLB entry only already in use */
745#define MAS0_WQ_COND (1 << MAS0_WQ_SHIFT)
746/* Clear TLB entry */
747#define MAS0_WQ_CLR_RSRV (2 << MAS0_WQ_SHIFT)
748
749#define MAS0_HES_SHIFT 14
750#define MAS0_HES (1 << MAS0_HES_SHIFT)
751
752#define MAS0_ESEL_SHIFT 16
753#define MAS0_ESEL_MASK (0xfff << MAS0_ESEL_SHIFT)
754
755#define MAS0_TLBSEL_SHIFT 28
756#define MAS0_TLBSEL_MASK (3 << MAS0_TLBSEL_SHIFT)
757#define MAS0_TLBSEL_TLB0 (0 << MAS0_TLBSEL_SHIFT)
758#define MAS0_TLBSEL_TLB1 (1 << MAS0_TLBSEL_SHIFT)
759#define MAS0_TLBSEL_TLB2 (2 << MAS0_TLBSEL_SHIFT)
760#define MAS0_TLBSEL_TLB3 (3 << MAS0_TLBSEL_SHIFT)
761
762#define MAS0_ATSEL_SHIFT 31
763#define MAS0_ATSEL (1 << MAS0_ATSEL_SHIFT)
764#define MAS0_ATSEL_TLB 0
765#define MAS0_ATSEL_LRAT MAS0_ATSEL
766
2bd9543c
SW		 767#define MAS1_TSIZE_SHIFT 7
768#define MAS1_TSIZE_MASK (0x1f << MAS1_TSIZE_SHIFT)
01662f3e
AG		 769
770#define MAS1_TS_SHIFT 12
771#define MAS1_TS (1 << MAS1_TS_SHIFT)
772
773#define MAS1_IND_SHIFT 13
774#define MAS1_IND (1 << MAS1_IND_SHIFT)
775
776#define MAS1_TID_SHIFT 16
777#define MAS1_TID_MASK (0x3fff << MAS1_TID_SHIFT)
778
779#define MAS1_IPROT_SHIFT 30
780#define MAS1_IPROT (1 << MAS1_IPROT_SHIFT)
781
782#define MAS1_VALID_SHIFT 31
783#define MAS1_VALID 0x80000000
784
785#define MAS2_EPN_SHIFT 12
96091698 786#define MAS2_EPN_MASK (~0ULL << MAS2_EPN_SHIFT)
01662f3e
AG		 787
788#define MAS2_ACM_SHIFT 6
789#define MAS2_ACM (1 << MAS2_ACM_SHIFT)
790
791#define MAS2_VLE_SHIFT 5
792#define MAS2_VLE (1 << MAS2_VLE_SHIFT)
793
794#define MAS2_W_SHIFT 4
795#define MAS2_W (1 << MAS2_W_SHIFT)
796
797#define MAS2_I_SHIFT 3
798#define MAS2_I (1 << MAS2_I_SHIFT)
799
800#define MAS2_M_SHIFT 2
801#define MAS2_M (1 << MAS2_M_SHIFT)
802
803#define MAS2_G_SHIFT 1
804#define MAS2_G (1 << MAS2_G_SHIFT)
805
806#define MAS2_E_SHIFT 0
807#define MAS2_E (1 << MAS2_E_SHIFT)
808
809#define MAS3_RPN_SHIFT 12
810#define MAS3_RPN_MASK (0xfffff << MAS3_RPN_SHIFT)
811
812#define MAS3_U0 0x00000200
813#define MAS3_U1 0x00000100
814#define MAS3_U2 0x00000080
815#define MAS3_U3 0x00000040
816#define MAS3_UX 0x00000020
817#define MAS3_SX 0x00000010
818#define MAS3_UW 0x00000008
819#define MAS3_SW 0x00000004
820#define MAS3_UR 0x00000002
821#define MAS3_SR 0x00000001
822#define MAS3_SPSIZE_SHIFT 1
823#define MAS3_SPSIZE_MASK (0x3e << MAS3_SPSIZE_SHIFT)
824
825#define MAS4_TLBSELD_SHIFT MAS0_TLBSEL_SHIFT
826#define MAS4_TLBSELD_MASK MAS0_TLBSEL_MASK
827#define MAS4_TIDSELD_MASK 0x00030000
828#define MAS4_TIDSELD_PID0 0x00000000
829#define MAS4_TIDSELD_PID1 0x00010000
830#define MAS4_TIDSELD_PID2 0x00020000
831#define MAS4_TIDSELD_PIDZ 0x00030000
832#define MAS4_INDD 0x00008000 /* Default IND */
833#define MAS4_TSIZED_SHIFT MAS1_TSIZE_SHIFT
834#define MAS4_TSIZED_MASK MAS1_TSIZE_MASK
835#define MAS4_ACMD 0x00000040
836#define MAS4_VLED 0x00000020
837#define MAS4_WD 0x00000010
838#define MAS4_ID 0x00000008
839#define MAS4_MD 0x00000004
840#define MAS4_GD 0x00000002
841#define MAS4_ED 0x00000001
842#define MAS4_WIMGED_MASK 0x0000001f /* Default WIMGE */
843#define MAS4_WIMGED_SHIFT 0
844
845#define MAS5_SGS 0x80000000
846#define MAS5_SLPID_MASK 0x00000fff
847
848#define MAS6_SPID0 0x3fff0000
849#define MAS6_SPID1 0x00007ffe
850#define MAS6_ISIZE(x) MAS1_TSIZE(x)
851#define MAS6_SAS 0x00000001
852#define MAS6_SPID MAS6_SPID0
853#define MAS6_SIND 0x00000002 /* Indirect page */
854#define MAS6_SIND_SHIFT 1
855#define MAS6_SPID_MASK 0x3fff0000
856#define MAS6_SPID_SHIFT 16
857#define MAS6_ISIZE_MASK 0x00000f80
858#define MAS6_ISIZE_SHIFT 7
859
860#define MAS7_RPN 0xffffffff
861
862#define MAS8_TGS 0x80000000
863#define MAS8_VF 0x40000000
864#define MAS8_TLBPID 0x00000fff
865
866/* Bit definitions for MMUCFG */
867#define MMUCFG_MAVN 0x00000003 /* MMU Architecture Version Number */
868#define MMUCFG_MAVN_V1 0x00000000 /* v1.0 */
869#define MMUCFG_MAVN_V2 0x00000001 /* v2.0 */
870#define MMUCFG_NTLBS 0x0000000c /* Number of TLBs */
871#define MMUCFG_PIDSIZE 0x000007c0 /* PID Reg Size */
872#define MMUCFG_TWC 0x00008000 /* TLB Write Conditional (v2.0) */
873#define MMUCFG_LRAT 0x00010000 /* LRAT Supported (v2.0) */
874#define MMUCFG_RASIZE 0x00fe0000 /* Real Addr Size */
875#define MMUCFG_LPIDSIZE 0x0f000000 /* LPID Reg Size */
876
877/* Bit definitions for MMUCSR0 */
878#define MMUCSR0_TLB1FI 0x00000002 /* TLB1 Flash invalidate */
879#define MMUCSR0_TLB0FI 0x00000004 /* TLB0 Flash invalidate */
880#define MMUCSR0_TLB2FI 0x00000040 /* TLB2 Flash invalidate */
881#define MMUCSR0_TLB3FI 0x00000020 /* TLB3 Flash invalidate */
882#define MMUCSR0_TLBFI (MMUCSR0_TLB0FI | MMUCSR0_TLB1FI | \
883 MMUCSR0_TLB2FI | MMUCSR0_TLB3FI)
884#define MMUCSR0_TLB0PS 0x00000780 /* TLB0 Page Size */
885#define MMUCSR0_TLB1PS 0x00007800 /* TLB1 Page Size */
886#define MMUCSR0_TLB2PS 0x00078000 /* TLB2 Page Size */
887#define MMUCSR0_TLB3PS 0x00780000 /* TLB3 Page Size */
888
889/* TLBnCFG encoding */
890#define TLBnCFG_N_ENTRY 0x00000fff /* number of entries */
891#define TLBnCFG_HES 0x00002000 /* HW select supported */
892#define TLBnCFG_AVAIL 0x00004000 /* variable page size */
893#define TLBnCFG_IPROT 0x00008000 /* IPROT supported */
894#define TLBnCFG_GTWE 0x00010000 /* Guest can write */
895#define TLBnCFG_IND 0x00020000 /* IND entries supported */
896#define TLBnCFG_PT 0x00040000 /* Can load from page table */
897#define TLBnCFG_MINSIZE 0x00f00000 /* Minimum Page Size (v1.0) */
898#define TLBnCFG_MINSIZE_SHIFT 20
899#define TLBnCFG_MAXSIZE 0x000f0000 /* Maximum Page Size (v1.0) */
900#define TLBnCFG_MAXSIZE_SHIFT 16
901#define TLBnCFG_ASSOC 0xff000000 /* Associativity */
902#define TLBnCFG_ASSOC_SHIFT 24
903
904/* TLBnPS encoding */
905#define TLBnPS_4K 0x00000004
906#define TLBnPS_8K 0x00000008
907#define TLBnPS_16K 0x00000010
908#define TLBnPS_32K 0x00000020
909#define TLBnPS_64K 0x00000040
910#define TLBnPS_128K 0x00000080
911#define TLBnPS_256K 0x00000100
912#define TLBnPS_512K 0x00000200
913#define TLBnPS_1M 0x00000400
914#define TLBnPS_2M 0x00000800
915#define TLBnPS_4M 0x00001000
916#define TLBnPS_8M 0x00002000
917#define TLBnPS_16M 0x00004000
918#define TLBnPS_32M 0x00008000
919#define TLBnPS_64M 0x00010000
920#define TLBnPS_128M 0x00020000
921#define TLBnPS_256M 0x00040000
922#define TLBnPS_512M 0x00080000
923#define TLBnPS_1G 0x00100000
924#define TLBnPS_2G 0x00200000
925#define TLBnPS_4G 0x00400000
926#define TLBnPS_8G 0x00800000
927#define TLBnPS_16G 0x01000000
928#define TLBnPS_32G 0x02000000
929#define TLBnPS_64G 0x04000000
930#define TLBnPS_128G 0x08000000
931#define TLBnPS_256G 0x10000000
932
933/* tlbilx action encoding */
934#define TLBILX_T_ALL 0
935#define TLBILX_T_TID 1
936#define TLBILX_T_FULLMATCH 3
937#define TLBILX_T_CLASS0 4
938#define TLBILX_T_CLASS1 5
939#define TLBILX_T_CLASS2 6
940#define TLBILX_T_CLASS3 7
941
942/* BookE 2.06 helper defines */
943
944#define BOOKE206_FLUSH_TLB0 (1 << 0)
945#define BOOKE206_FLUSH_TLB1 (1 << 1)
946#define BOOKE206_FLUSH_TLB2 (1 << 2)
947#define BOOKE206_FLUSH_TLB3 (1 << 3)
948
949/* number of possible TLBs */
950#define BOOKE206_MAX_TLBN 4
951
58e00a24
AG		 952/*****************************************************************************/
953/* Embedded.Processor Control */
954
955#define DBELL_TYPE_SHIFT 27
956#define DBELL_TYPE_MASK (0x1f << DBELL_TYPE_SHIFT)
957#define DBELL_TYPE_DBELL (0x00 << DBELL_TYPE_SHIFT)
958#define DBELL_TYPE_DBELL_CRIT (0x01 << DBELL_TYPE_SHIFT)
959#define DBELL_TYPE_G_DBELL (0x02 << DBELL_TYPE_SHIFT)
960#define DBELL_TYPE_G_DBELL_CRIT (0x03 << DBELL_TYPE_SHIFT)
961#define DBELL_TYPE_G_DBELL_MC (0x04 << DBELL_TYPE_SHIFT)
962
963#define DBELL_BRDCAST (1 << 26)
964#define DBELL_LPIDTAG_SHIFT 14
965#define DBELL_LPIDTAG_MASK (0xfff << DBELL_LPIDTAG_SHIFT)
966#define DBELL_PIRTAG_MASK 0x3fff
967
4656e1f0
BH		 968/*****************************************************************************/
969/* Segment page size information, used by recent hash MMUs
970 * The format of this structure mirrors kvm_ppc_smmu_info
971 */
972
973#define PPC_PAGE_SIZES_MAX_SZ 8
974
975struct ppc_one_page_size {
976 uint32_t page_shift; /* Page shift (or 0) */
977 uint32_t pte_enc; /* Encoding in the HPTE (>>12) */
978};
979
980struct ppc_one_seg_page_size {
981 uint32_t page_shift; /* Base page shift of segment (or 0) */
982 uint32_t slb_enc; /* SLB encoding for BookS */
983 struct ppc_one_page_size enc[PPC_PAGE_SIZES_MAX_SZ];
984};
985
986struct ppc_segment_page_sizes {
987 struct ppc_one_seg_page_size sps[PPC_PAGE_SIZES_MAX_SZ];
988};
989
990
6fa724a3 991/*****************************************************************************/
7c58044c 992/* The whole PowerPC CPU context */
6ebbf390 993#define NB_MMU_MODES 3
6ebbf390 994
54ff58bb
BR		 995#define PPC_CPU_OPCODES_LEN 0x40
996#define PPC_CPU_INDIRECT_OPCODES_LEN 0x20
b048960f 997
3fc6c082
FB		 998struct CPUPPCState {
999 /* First are the most commonly used resources
1000 * during translated code execution
1001 */
79aceca5 1002 /* general purpose registers */
bd7d9a6d 1003 target_ulong gpr[32];
3cd7d1dd 1004 /* Storage for GPR MSB, used by the SPE extension */
bd7d9a6d 1005 target_ulong gprh[32];
3fc6c082
FB		 1006 /* LR */
1007 target_ulong lr;
1008 /* CTR */
1009 target_ulong ctr;
1010 /* condition register */
47e4661c 1011 uint32_t crf[8];
697ab892
DG		 1012#if defined(TARGET_PPC64)
1013 /* CFAR */
1014 target_ulong cfar;
1015#endif
da91a00f 1016 /* XER (with SO, OV, CA split out) */
3d7b417e 1017 target_ulong xer;
da91a00f
RH		 1018 target_ulong so;
1019 target_ulong ov;
1020 target_ulong ca;
79aceca5 1021 /* Reservation address */
18b21a2f
NF		 1022 target_ulong reserve_addr;
1023 /* Reservation value */
1024 target_ulong reserve_val;
9c294d5a 1025 target_ulong reserve_val2;
4425265b
NF		 1026 /* Reservation store address */
1027 target_ulong reserve_ea;
1028 /* Reserved store source register and size */
1029 target_ulong reserve_info;
3fc6c082
FB		 1030
1031 /* Those ones are used in supervisor mode only */
79aceca5 1032 /* machine state register */
0411a972 1033 target_ulong msr;
3fc6c082 1034 /* temporary general purpose registers */
bd7d9a6d 1035 target_ulong tgpr[4]; /* Used to speed-up TLB assist handlers */
3fc6c082
FB		 1036
1037 /* Floating point execution context */
4ecc3190 1038 float_status fp_status;
3fc6c082
FB		 1039 /* floating point registers */
1040 float64 fpr[32];
1041 /* floating point status and control register */
30304420 1042 target_ulong fpscr;
4ecc3190 1043
cb2dbfc3
AJ		 1044 /* Next instruction pointer */
1045 target_ulong nip;
a316d335 1046
ac9eb073
FB		 1047 int access_type; /* when a memory exception occurs, the access
1048 type is stored here */
a541f297 1049
cb2dbfc3
AJ		 1050 CPU_COMMON
1051
f2e63a42
JM		 1052 /* MMU context - only relevant for full system emulation */
1053#if !defined(CONFIG_USER_ONLY)
1054#if defined(TARGET_PPC64)
f2e63a42 1055 /* PowerPC 64 SLB area */
d83af167 1056 ppc_slb_t slb[MAX_SLB_ENTRIES];
a90db158 1057 int32_t slb_nr;
f2e63a42 1058#endif
3fc6c082 1059 /* segment registers */
a8170e5e 1060 hwaddr htab_base;
f3c75d42 1061 /* mask used to normalize hash value to PTEG index */
a8170e5e 1062 hwaddr htab_mask;
74d37793 1063 target_ulong sr[32];
f43e3525
DG		 1064 /* externally stored hash table */
1065 uint8_t *external_htab;
3fc6c082 1066 /* BATs */
a90db158 1067 uint32_t nb_BATs;
3fc6c082
FB		 1068 target_ulong DBAT[2][8];
1069 target_ulong IBAT[2][8];
01662f3e 1070 /* PowerPC TLB registers (for 4xx, e500 and 60x software driven TLBs) */
a90db158 1071 int32_t nb_tlb; /* Total number of TLB */
f2e63a42
JM		 1072 int tlb_per_way; /* Speed-up helper: used to avoid divisions at run time */
1073 int nb_ways; /* Number of ways in the TLB set */
1074 int last_way; /* Last used way used to allocate TLB in a LRU way */
1075 int id_tlbs; /* If 1, MMU has separated TLBs for instructions & data */
1076 int nb_pids; /* Number of available PID registers */
1c53accc
AG		 1077 int tlb_type; /* Type of TLB we're dealing with */
1078 ppc_tlb_t tlb; /* TLB is optional. Allocate them only if needed */
f2e63a42
JM		 1079 /* 403 dedicated access protection registers */
1080 target_ulong pb[4];
93dd5e85
SW		 1081 bool tlb_dirty; /* Set to non-zero when modifying TLB */
1082 bool kvm_sw_tlb; /* non-zero if KVM SW TLB API is active */
f2e63a42 1083#endif
9fddaa0c 1084
3fc6c082
FB		 1085 /* Other registers */
1086 /* Special purpose registers */
1087 target_ulong spr[1024];
c227f099 1088 ppc_spr_t spr_cb[1024];
3fc6c082 1089 /* Altivec registers */
c227f099 1090 ppc_avr_t avr[32];
3fc6c082 1091 uint32_t vscr;
30304420
DG		 1092 /* VSX registers */
1093 uint64_t vsr[32];
d9bce9d9 1094 /* SPE registers */
2231ef10 1095 uint64_t spe_acc;
d9bce9d9 1096 uint32_t spe_fscr;
fbd265b6
AJ		 1097 /* SPE and Altivec can share a status since they will never be used
1098 * simultaneously */
1099 float_status vec_status;
3fc6c082
FB		 1100
1101 /* Internal devices resources */
9fddaa0c 1102 /* Time base and decrementer */
c227f099 1103 ppc_tb_t *tb_env;
3fc6c082 1104 /* Device control registers */
c227f099 1105 ppc_dcr_t *dcr_env;
3fc6c082 1106
d63001d1
JM		 1107 int dcache_line_size;
1108 int icache_line_size;
1109
3fc6c082
FB		 1110 /* Those resources are used during exception processing */
1111 /* CPU model definition */
a750fc0b 1112 target_ulong msr_mask;
c227f099
AL		 1113 powerpc_mmu_t mmu_model;
1114 powerpc_excp_t excp_model;
1115 powerpc_input_t bus_model;
237c0af0 1116 int bfd_mach;
3fc6c082 1117 uint32_t flags;
c29b735c 1118 uint64_t insns_flags;
a5858d7a 1119 uint64_t insns_flags2;
4656e1f0
BH		 1120#if defined(TARGET_PPC64)
1121 struct ppc_segment_page_sizes sps;
90da0d5a 1122 bool ci_large_pages;
4656e1f0 1123#endif
3fc6c082 1124
ed120055 1125#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
ac7d12ba
DG		 1126 uint64_t vpa_addr;
1127 uint64_t slb_shadow_addr, slb_shadow_size;
1128 uint64_t dtl_addr, dtl_size;
ed120055
DG		 1129#endif /* TARGET_PPC64 */
1130
3fc6c082 1131 int error_code;
47103572 1132 uint32_t pending_interrupts;
e9df014c 1133#if !defined(CONFIG_USER_ONLY)
4abf79a4 1134 /* This is the IRQ controller, which is implementation dependent
e9df014c
JM		 1135 * and only relevant when emulating a complete machine.
1136 */
1137 uint32_t irq_input_state;
1138 void **irq_inputs;
e1833e1f
JM		 1139 /* Exception vectors */
1140 target_ulong excp_vectors[POWERPC_EXCP_NB];
1141 target_ulong excp_prefix;
1142 target_ulong ivor_mask;
1143 target_ulong ivpr_mask;
d63001d1 1144 target_ulong hreset_vector;
68c2dd70
AG		 1145 hwaddr mpic_iack;
1146 /* true when the external proxy facility mode is enabled */
1147 bool mpic_proxy;
e9df014c 1148#endif
3fc6c082
FB		 1149
1150 /* Those resources are used only during code translation */
3fc6c082 1151 /* opcode handlers */
b048960f 1152 opc_handler_t *opcodes[PPC_CPU_OPCODES_LEN];
3fc6c082 1153
5cbdb3a3 1154 /* Those resources are used only in QEMU core */
056401ea 1155 target_ulong hflags; /* hflags is a MSR & HFLAGS_MASK */
4abf79a4 1156 target_ulong hflags_nmsr; /* specific hflags, not coming from MSR */
6ebbf390 1157 int mmu_idx; /* precomputed MMU index to speed up mem accesses */
3fc6c082 1158
9fddaa0c 1159 /* Power management */
cd346349 1160 int (*check_pow)(CPUPPCState *env);
a541f297 1161
2c50e26e
EI		 1162#if !defined(CONFIG_USER_ONLY)
1163 void *load_info; /* Holds boot loading state. */
1164#endif
ddd1055b
FC		 1165
1166 /* booke timers */
1167
1168 /* Specifies bit locations of the Time Base used to signal a fixed timer
1169 * exception on a transition from 0 to 1. (watchdog or fixed-interval timer)
1170 *
1171 * 0 selects the least significant bit.
1172 * 63 selects the most significant bit.
1173 */
1174 uint8_t fit_period[4];
1175 uint8_t wdt_period[4];
80b3f79b
AK		 1176
1177 /* Transactional memory state */
1178 target_ulong tm_gpr[32];
1179 ppc_avr_t tm_vsr[64];
1180 uint64_t tm_cr;
1181 uint64_t tm_lr;
1182 uint64_t tm_ctr;
1183 uint64_t tm_fpscr;
1184 uint64_t tm_amr;
1185 uint64_t tm_ppr;
1186 uint64_t tm_vrsave;
1187 uint32_t tm_vscr;
1188 uint64_t tm_dscr;
1189 uint64_t tm_tar;
3fc6c082 1190};
79aceca5 1191
ddd1055b
FC		 1192#define SET_FIT_PERIOD(a_, b_, c_, d_) \
1193do { \
1194 env->fit_period[0] = (a_); \
1195 env->fit_period[1] = (b_); \
1196 env->fit_period[2] = (c_); \
1197 env->fit_period[3] = (d_); \
1198 } while (0)
1199
1200#define SET_WDT_PERIOD(a_, b_, c_, d_) \
1201do { \
1202 env->wdt_period[0] = (a_); \
1203 env->wdt_period[1] = (b_); \
1204 env->wdt_period[2] = (c_); \
1205 env->wdt_period[3] = (d_); \
1206 } while (0)
1207
1d0cb67d
AF		 1208#include "cpu-qom.h"
1209
3fc6c082 1210/*****************************************************************************/
397b457d 1211PowerPCCPU *cpu_ppc_init(const char *cpu_model);
2e70f6ef 1212void ppc_translate_init(void);
7019cb3d 1213void gen_update_current_nip(void *opaque);
ea3e9847 1214int cpu_ppc_exec (CPUState *s);
79aceca5
FB		 1215/* you can call this signal handler from your SIGBUS and SIGSEGV
1216 signal handlers to inform the virtual CPU of exceptions. non zero
1217 is returned if the signal was handled by the virtual CPU. */
36081602
JM		 1218int cpu_ppc_signal_handler (int host_signum, void *pinfo,
1219 void *puc);
cc8eae8a 1220#if defined(CONFIG_USER_ONLY)
7510454e
AF		 1221int ppc_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
1222 int mmu_idx);
cc8eae8a 1223#endif
a541f297 1224
76a66253 1225#if !defined(CONFIG_USER_ONLY)
45d827d2 1226void ppc_store_sdr1 (CPUPPCState *env, target_ulong value);
12de9a39 1227#endif /* !defined(CONFIG_USER_ONLY) */
0411a972 1228void ppc_store_msr (CPUPPCState *env, target_ulong value);
3fc6c082 1229
9a78eead 1230void ppc_cpu_list (FILE *f, fprintf_function cpu_fprintf);
2a48d993 1231int ppc_get_compat_smt_threads(PowerPCCPU *cpu);
f9ab1e87 1232void ppc_set_compat(PowerPCCPU *cpu, uint32_t cpu_version, Error **errp);
aaed909a 1233
9fddaa0c
FB		 1234/* Time-base and decrementer management */
1235#ifndef NO_CPU_IO_DEFS
e3ea6529 1236uint64_t cpu_ppc_load_tbl (CPUPPCState *env);
9fddaa0c
FB		 1237uint32_t cpu_ppc_load_tbu (CPUPPCState *env);
1238void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value);
1239void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value);
b711de95 1240uint64_t cpu_ppc_load_atbl (CPUPPCState *env);
a062e36c
JM		 1241uint32_t cpu_ppc_load_atbu (CPUPPCState *env);
1242void cpu_ppc_store_atbl (CPUPPCState *env, uint32_t value);
1243void cpu_ppc_store_atbu (CPUPPCState *env, uint32_t value);
e81a982a 1244bool ppc_decr_clear_on_delivery(CPUPPCState *env);
9fddaa0c
FB		 1245uint32_t cpu_ppc_load_decr (CPUPPCState *env);
1246void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value);
58a7d328
JM		 1247uint32_t cpu_ppc_load_hdecr (CPUPPCState *env);
1248void cpu_ppc_store_hdecr (CPUPPCState *env, uint32_t value);
1249uint64_t cpu_ppc_load_purr (CPUPPCState *env);
d9bce9d9
JM		 1250uint32_t cpu_ppc601_load_rtcl (CPUPPCState *env);
1251uint32_t cpu_ppc601_load_rtcu (CPUPPCState *env);
1252#if !defined(CONFIG_USER_ONLY)
1253void cpu_ppc601_store_rtcl (CPUPPCState *env, uint32_t value);
1254void cpu_ppc601_store_rtcu (CPUPPCState *env, uint32_t value);
1255target_ulong load_40x_pit (CPUPPCState *env);
1256void store_40x_pit (CPUPPCState *env, target_ulong val);
8ecc7913 1257void store_40x_dbcr0 (CPUPPCState *env, uint32_t val);
c294fc58 1258void store_40x_sler (CPUPPCState *env, uint32_t val);
d9bce9d9
JM		 1259void store_booke_tcr (CPUPPCState *env, target_ulong val);
1260void store_booke_tsr (CPUPPCState *env, target_ulong val);
0a032cbe 1261void ppc_tlb_invalidate_all (CPUPPCState *env);
daf4f96e 1262void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr);
d9bce9d9 1263#endif
9fddaa0c 1264#endif
79aceca5 1265
d6478bc7
FC		 1266void store_fpscr(CPUPPCState *env, uint64_t arg, uint32_t mask);
1267
636aa200 1268static inline uint64_t ppc_dump_gpr(CPUPPCState *env, int gprn)
6b542af7
JM		 1269{
1270 uint64_t gprv;
1271
1272 gprv = env->gpr[gprn];
6b542af7
JM		 1273 if (env->flags & POWERPC_FLAG_SPE) {
1274 /* If the CPU implements the SPE extension, we have to get the
1275 * high bits of the GPR from the gprh storage area
1276 */
1277 gprv &= 0xFFFFFFFFULL;
1278 gprv |= (uint64_t)env->gprh[gprn] << 32;
1279 }
6b542af7
JM		 1280
1281 return gprv;
1282}
1283
2e719ba3 1284/* Device control registers */
73b01960
AG		 1285int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp);
1286int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val);
2e719ba3 1287
2994fd96 1288#define cpu_init(cpu_model) CPU(cpu_ppc_init(cpu_model))
397b457d 1289
9467d44c 1290#define cpu_exec cpu_ppc_exec
9467d44c 1291#define cpu_signal_handler cpu_ppc_signal_handler
c732abe2 1292#define cpu_list ppc_cpu_list
9467d44c 1293
6ebbf390
JM		 1294/* MMU modes definitions */
1295#define MMU_MODE0_SUFFIX _user
1296#define MMU_MODE1_SUFFIX _kernel
6ebbf390 1297#define MMU_MODE2_SUFFIX _hypv
6ebbf390 1298#define MMU_USER_IDX 0
97ed5ccd 1299static inline int cpu_mmu_index (CPUPPCState *env, bool ifetch)
6ebbf390
JM		 1300{
1301 return env->mmu_idx;
1302}
1303
022c62cb 1304#include "exec/cpu-all.h"
79aceca5 1305
3fc6c082 1306/*****************************************************************************/
e1571908 1307/* CRF definitions */
57951c27
AJ		 1308#define CRF_LT 3
1309#define CRF_GT 2
1310#define CRF_EQ 1
1311#define CRF_SO 0
e6bba2ef
NF		 1312#define CRF_CH (1 << CRF_LT)
1313#define CRF_CL (1 << CRF_GT)
1314#define CRF_CH_OR_CL (1 << CRF_EQ)
1315#define CRF_CH_AND_CL (1 << CRF_SO)
e1571908
AJ		 1316
1317/* XER definitions */
3d7b417e
AJ		 1318#define XER_SO 31
1319#define XER_OV 30
1320#define XER_CA 29
1321#define XER_CMP 8
1322#define XER_BC 0
da91a00f
RH		 1323#define xer_so (env->so)
1324#define xer_ov (env->ov)
1325#define xer_ca (env->ca)
3d7b417e
AJ		 1326#define xer_cmp ((env->xer >> XER_CMP) & 0xFF)
1327#define xer_bc ((env->xer >> XER_BC) & 0x7F)
79aceca5 1328
3fc6c082 1329/* SPR definitions */
80d11f44
JM		 1330#define SPR_MQ (0x000)
1331#define SPR_XER (0x001)
1332#define SPR_601_VRTCU (0x004)
1333#define SPR_601_VRTCL (0x005)
1334#define SPR_601_UDECR (0x006)
1335#define SPR_LR (0x008)
1336#define SPR_CTR (0x009)
f80872e2 1337#define SPR_UAMR (0x00C)
697ab892 1338#define SPR_DSCR (0x011)
80d11f44
JM		 1339#define SPR_DSISR (0x012)
1340#define SPR_DAR (0x013) /* DAE for PowerPC 601 */
1341#define SPR_601_RTCU (0x014)
1342#define SPR_601_RTCL (0x015)
1343#define SPR_DECR (0x016)
1344#define SPR_SDR1 (0x019)
1345#define SPR_SRR0 (0x01A)
1346#define SPR_SRR1 (0x01B)
697ab892 1347#define SPR_CFAR (0x01C)
80d11f44
JM		 1348#define SPR_AMR (0x01D)
1349#define SPR_BOOKE_PID (0x030)
1350#define SPR_BOOKE_DECAR (0x036)
1351#define SPR_BOOKE_CSRR0 (0x03A)
1352#define SPR_BOOKE_CSRR1 (0x03B)
1353#define SPR_BOOKE_DEAR (0x03D)
1354#define SPR_BOOKE_ESR (0x03E)
1355#define SPR_BOOKE_IVPR (0x03F)
1356#define SPR_MPC_EIE (0x050)
1357#define SPR_MPC_EID (0x051)
1358#define SPR_MPC_NRI (0x052)
cdcdda27
AK		 1359#define SPR_TFHAR (0x080)
1360#define SPR_TFIAR (0x081)
1361#define SPR_TEXASR (0x082)
1362#define SPR_TEXASRU (0x083)
0bfe9299 1363#define SPR_UCTRL (0x088)
80d11f44
JM		 1364#define SPR_MPC_CMPA (0x090)
1365#define SPR_MPC_CMPB (0x091)
1366#define SPR_MPC_CMPC (0x092)
1367#define SPR_MPC_CMPD (0x093)
1368#define SPR_MPC_ECR (0x094)
1369#define SPR_MPC_DER (0x095)
1370#define SPR_MPC_COUNTA (0x096)
1371#define SPR_MPC_COUNTB (0x097)
0bfe9299 1372#define SPR_CTRL (0x098)
80d11f44
JM		 1373#define SPR_MPC_CMPE (0x098)
1374#define SPR_MPC_CMPF (0x099)
7019cb3d 1375#define SPR_FSCR (0x099)
80d11f44
JM		 1376#define SPR_MPC_CMPG (0x09A)
1377#define SPR_MPC_CMPH (0x09B)
1378#define SPR_MPC_LCTRL1 (0x09C)
1379#define SPR_MPC_LCTRL2 (0x09D)
f80872e2 1380#define SPR_UAMOR (0x09D)
80d11f44
JM		 1381#define SPR_MPC_ICTRL (0x09E)
1382#define SPR_MPC_BAR (0x09F)
d6f1445f 1383#define SPR_PSPB (0x09F)
80d11f44
JM		 1384#define SPR_VRSAVE (0x100)
1385#define SPR_USPRG0 (0x100)
1386#define SPR_USPRG1 (0x101)
1387#define SPR_USPRG2 (0x102)
1388#define SPR_USPRG3 (0x103)
1389#define SPR_USPRG4 (0x104)
1390#define SPR_USPRG5 (0x105)
1391#define SPR_USPRG6 (0x106)
1392#define SPR_USPRG7 (0x107)
1393#define SPR_VTBL (0x10C)
1394#define SPR_VTBU (0x10D)
1395#define SPR_SPRG0 (0x110)
1396#define SPR_SPRG1 (0x111)
1397#define SPR_SPRG2 (0x112)
1398#define SPR_SPRG3 (0x113)
1399#define SPR_SPRG4 (0x114)
1400#define SPR_SCOMC (0x114)
1401#define SPR_SPRG5 (0x115)
1402#define SPR_SCOMD (0x115)
1403#define SPR_SPRG6 (0x116)
1404#define SPR_SPRG7 (0x117)
1405#define SPR_ASR (0x118)
1406#define SPR_EAR (0x11A)
1407#define SPR_TBL (0x11C)
1408#define SPR_TBU (0x11D)
1409#define SPR_TBU40 (0x11E)
1410#define SPR_SVR (0x11E)
1411#define SPR_BOOKE_PIR (0x11E)
1412#define SPR_PVR (0x11F)
1413#define SPR_HSPRG0 (0x130)
1414#define SPR_BOOKE_DBSR (0x130)
1415#define SPR_HSPRG1 (0x131)
1416#define SPR_HDSISR (0x132)
1417#define SPR_HDAR (0x133)
90dc8812 1418#define SPR_BOOKE_EPCR (0x133)
9d52e907 1419#define SPR_SPURR (0x134)
80d11f44
JM		 1420#define SPR_BOOKE_DBCR0 (0x134)
1421#define SPR_IBCR (0x135)
1422#define SPR_PURR (0x135)
1423#define SPR_BOOKE_DBCR1 (0x135)
1424#define SPR_DBCR (0x136)
1425#define SPR_HDEC (0x136)
1426#define SPR_BOOKE_DBCR2 (0x136)
1427#define SPR_HIOR (0x137)
1428#define SPR_MBAR (0x137)
1429#define SPR_RMOR (0x138)
1430#define SPR_BOOKE_IAC1 (0x138)
1431#define SPR_HRMOR (0x139)
1432#define SPR_BOOKE_IAC2 (0x139)
1433#define SPR_HSRR0 (0x13A)
1434#define SPR_BOOKE_IAC3 (0x13A)
1435#define SPR_HSRR1 (0x13B)
1436#define SPR_BOOKE_IAC4 (0x13B)
80d11f44
JM		 1437#define SPR_BOOKE_DAC1 (0x13C)
1438#define SPR_LPIDR (0x13D)
1439#define SPR_DABR2 (0x13D)
1440#define SPR_BOOKE_DAC2 (0x13D)
1441#define SPR_BOOKE_DVC1 (0x13E)
6475c9f0 1442#define SPR_LPCR (0x13E)
80d11f44
JM		 1443#define SPR_BOOKE_DVC2 (0x13F)
1444#define SPR_BOOKE_TSR (0x150)
6d9412ea 1445#define SPR_PCR (0x152)
80d11f44 1446#define SPR_BOOKE_TCR (0x154)
a1ef618a
AG		 1447#define SPR_BOOKE_TLB0PS (0x158)
1448#define SPR_BOOKE_TLB1PS (0x159)
1449#define SPR_BOOKE_TLB2PS (0x15A)
1450#define SPR_BOOKE_TLB3PS (0x15B)
84755ed5 1451#define SPR_BOOKE_MAS7_MAS3 (0x174)
80d11f44
JM		 1452#define SPR_BOOKE_IVOR0 (0x190)
1453#define SPR_BOOKE_IVOR1 (0x191)
1454#define SPR_BOOKE_IVOR2 (0x192)
1455#define SPR_BOOKE_IVOR3 (0x193)
1456#define SPR_BOOKE_IVOR4 (0x194)
1457#define SPR_BOOKE_IVOR5 (0x195)
1458#define SPR_BOOKE_IVOR6 (0x196)
1459#define SPR_BOOKE_IVOR7 (0x197)
1460#define SPR_BOOKE_IVOR8 (0x198)
1461#define SPR_BOOKE_IVOR9 (0x199)
1462#define SPR_BOOKE_IVOR10 (0x19A)
1463#define SPR_BOOKE_IVOR11 (0x19B)
1464#define SPR_BOOKE_IVOR12 (0x19C)
1465#define SPR_BOOKE_IVOR13 (0x19D)
1466#define SPR_BOOKE_IVOR14 (0x19E)
1467#define SPR_BOOKE_IVOR15 (0x19F)
e9205258
AG		 1468#define SPR_BOOKE_IVOR38 (0x1B0)
1469#define SPR_BOOKE_IVOR39 (0x1B1)
1470#define SPR_BOOKE_IVOR40 (0x1B2)
1471#define SPR_BOOKE_IVOR41 (0x1B3)
1472#define SPR_BOOKE_IVOR42 (0x1B4)
45eb5611
AG		 1473#define SPR_BOOKE_GIVOR2 (0x1B8)
1474#define SPR_BOOKE_GIVOR3 (0x1B9)
1475#define SPR_BOOKE_GIVOR4 (0x1BA)
1476#define SPR_BOOKE_GIVOR8 (0x1BB)
1477#define SPR_BOOKE_GIVOR13 (0x1BC)
1478#define SPR_BOOKE_GIVOR14 (0x1BD)
d1a721ab 1479#define SPR_TIR (0x1BE)
80d11f44
JM		 1480#define SPR_BOOKE_SPEFSCR (0x200)
1481#define SPR_Exxx_BBEAR (0x201)
1482#define SPR_Exxx_BBTAR (0x202)
1483#define SPR_Exxx_L1CFG0 (0x203)
d2ea2bf7 1484#define SPR_Exxx_L1CFG1 (0x204)
80d11f44
JM		 1485#define SPR_Exxx_NPIDR (0x205)
1486#define SPR_ATBL (0x20E)
1487#define SPR_ATBU (0x20F)
1488#define SPR_IBAT0U (0x210)
1489#define SPR_BOOKE_IVOR32 (0x210)
1490#define SPR_RCPU_MI_GRA (0x210)
1491#define SPR_IBAT0L (0x211)
1492#define SPR_BOOKE_IVOR33 (0x211)
1493#define SPR_IBAT1U (0x212)
1494#define SPR_BOOKE_IVOR34 (0x212)
1495#define SPR_IBAT1L (0x213)
1496#define SPR_BOOKE_IVOR35 (0x213)
1497#define SPR_IBAT2U (0x214)
1498#define SPR_BOOKE_IVOR36 (0x214)
1499#define SPR_IBAT2L (0x215)
1500#define SPR_BOOKE_IVOR37 (0x215)
1501#define SPR_IBAT3U (0x216)
1502#define SPR_IBAT3L (0x217)
1503#define SPR_DBAT0U (0x218)
1504#define SPR_RCPU_L2U_GRA (0x218)
1505#define SPR_DBAT0L (0x219)
1506#define SPR_DBAT1U (0x21A)
1507#define SPR_DBAT1L (0x21B)
1508#define SPR_DBAT2U (0x21C)
1509#define SPR_DBAT2L (0x21D)
1510#define SPR_DBAT3U (0x21E)
1511#define SPR_DBAT3L (0x21F)
1512#define SPR_IBAT4U (0x230)
1513#define SPR_RPCU_BBCMCR (0x230)
1514#define SPR_MPC_IC_CST (0x230)
1515#define SPR_Exxx_CTXCR (0x230)
1516#define SPR_IBAT4L (0x231)
1517#define SPR_MPC_IC_ADR (0x231)
1518#define SPR_Exxx_DBCR3 (0x231)
1519#define SPR_IBAT5U (0x232)
1520#define SPR_MPC_IC_DAT (0x232)
1521#define SPR_Exxx_DBCNT (0x232)
1522#define SPR_IBAT5L (0x233)
1523#define SPR_IBAT6U (0x234)
1524#define SPR_IBAT6L (0x235)
1525#define SPR_IBAT7U (0x236)
1526#define SPR_IBAT7L (0x237)
1527#define SPR_DBAT4U (0x238)
1528#define SPR_RCPU_L2U_MCR (0x238)
1529#define SPR_MPC_DC_CST (0x238)
1530#define SPR_Exxx_ALTCTXCR (0x238)
1531#define SPR_DBAT4L (0x239)
1532#define SPR_MPC_DC_ADR (0x239)
1533#define SPR_DBAT5U (0x23A)
1534#define SPR_BOOKE_MCSRR0 (0x23A)
1535#define SPR_MPC_DC_DAT (0x23A)
1536#define SPR_DBAT5L (0x23B)
1537#define SPR_BOOKE_MCSRR1 (0x23B)
1538#define SPR_DBAT6U (0x23C)
1539#define SPR_BOOKE_MCSR (0x23C)
1540#define SPR_DBAT6L (0x23D)
1541#define SPR_Exxx_MCAR (0x23D)
1542#define SPR_DBAT7U (0x23E)
1543#define SPR_BOOKE_DSRR0 (0x23E)
1544#define SPR_DBAT7L (0x23F)
1545#define SPR_BOOKE_DSRR1 (0x23F)
1546#define SPR_BOOKE_SPRG8 (0x25C)
1547#define SPR_BOOKE_SPRG9 (0x25D)
1548#define SPR_BOOKE_MAS0 (0x270)
1549#define SPR_BOOKE_MAS1 (0x271)
1550#define SPR_BOOKE_MAS2 (0x272)
1551#define SPR_BOOKE_MAS3 (0x273)
1552#define SPR_BOOKE_MAS4 (0x274)
1553#define SPR_BOOKE_MAS5 (0x275)
1554#define SPR_BOOKE_MAS6 (0x276)
1555#define SPR_BOOKE_PID1 (0x279)
1556#define SPR_BOOKE_PID2 (0x27A)
1557#define SPR_MPC_DPDR (0x280)
1558#define SPR_MPC_IMMR (0x288)
1559#define SPR_BOOKE_TLB0CFG (0x2B0)
1560#define SPR_BOOKE_TLB1CFG (0x2B1)
1561#define SPR_BOOKE_TLB2CFG (0x2B2)
1562#define SPR_BOOKE_TLB3CFG (0x2B3)
1563#define SPR_BOOKE_EPR (0x2BE)
1564#define SPR_PERF0 (0x300)
1565#define SPR_RCPU_MI_RBA0 (0x300)
1566#define SPR_MPC_MI_CTR (0x300)
1567#define SPR_PERF1 (0x301)
1568#define SPR_RCPU_MI_RBA1 (0x301)
70c53407 1569#define SPR_POWER_UMMCR2 (0x301)
80d11f44
JM		 1570#define SPR_PERF2 (0x302)
1571#define SPR_RCPU_MI_RBA2 (0x302)
1572#define SPR_MPC_MI_AP (0x302)
75b9c321 1573#define SPR_POWER_UMMCRA (0x302)
80d11f44
JM		 1574#define SPR_PERF3 (0x303)
1575#define SPR_RCPU_MI_RBA3 (0x303)
1576#define SPR_MPC_MI_EPN (0x303)
fd51ff63 1577#define SPR_POWER_UPMC1 (0x303)
80d11f44 1578#define SPR_PERF4 (0x304)
fd51ff63 1579#define SPR_POWER_UPMC2 (0x304)
80d11f44
JM		 1580#define SPR_PERF5 (0x305)
1581#define SPR_MPC_MI_TWC (0x305)
fd51ff63 1582#define SPR_POWER_UPMC3 (0x305)
80d11f44
JM		 1583#define SPR_PERF6 (0x306)
1584#define SPR_MPC_MI_RPN (0x306)
fd51ff63 1585#define SPR_POWER_UPMC4 (0x306)
80d11f44 1586#define SPR_PERF7 (0x307)
fd51ff63 1587#define SPR_POWER_UPMC5 (0x307)
80d11f44
JM		 1588#define SPR_PERF8 (0x308)
1589#define SPR_RCPU_L2U_RBA0 (0x308)
1590#define SPR_MPC_MD_CTR (0x308)
fd51ff63 1591#define SPR_POWER_UPMC6 (0x308)
80d11f44
JM		 1592#define SPR_PERF9 (0x309)
1593#define SPR_RCPU_L2U_RBA1 (0x309)
1594#define SPR_MPC_MD_CASID (0x309)
c36c97f8 1595#define SPR_970_UPMC7 (0X309)
80d11f44
JM		 1596#define SPR_PERFA (0x30A)
1597#define SPR_RCPU_L2U_RBA2 (0x30A)
1598#define SPR_MPC_MD_AP (0x30A)
c36c97f8 1599#define SPR_970_UPMC8 (0X30A)
80d11f44
JM		 1600#define SPR_PERFB (0x30B)
1601#define SPR_RCPU_L2U_RBA3 (0x30B)
1602#define SPR_MPC_MD_EPN (0x30B)
fd51ff63 1603#define SPR_POWER_UMMCR0 (0X30B)
80d11f44
JM		 1604#define SPR_PERFC (0x30C)
1605#define SPR_MPC_MD_TWB (0x30C)
fd51ff63 1606#define SPR_POWER_USIAR (0X30C)
80d11f44
JM		 1607#define SPR_PERFD (0x30D)
1608#define SPR_MPC_MD_TWC (0x30D)
fd51ff63 1609#define SPR_POWER_USDAR (0X30D)
80d11f44
JM		 1610#define SPR_PERFE (0x30E)
1611#define SPR_MPC_MD_RPN (0x30E)
fd51ff63 1612#define SPR_POWER_UMMCR1 (0X30E)
80d11f44
JM		 1613#define SPR_PERFF (0x30F)
1614#define SPR_MPC_MD_TW (0x30F)
1615#define SPR_UPERF0 (0x310)
1616#define SPR_UPERF1 (0x311)
70c53407 1617#define SPR_POWER_MMCR2 (0x311)
80d11f44 1618#define SPR_UPERF2 (0x312)
75b9c321 1619#define SPR_POWER_MMCRA (0X312)
80d11f44 1620#define SPR_UPERF3 (0x313)
fd51ff63 1621#define SPR_POWER_PMC1 (0X313)
80d11f44 1622#define SPR_UPERF4 (0x314)
fd51ff63 1623#define SPR_POWER_PMC2 (0X314)
80d11f44 1624#define SPR_UPERF5 (0x315)
fd51ff63 1625#define SPR_POWER_PMC3 (0X315)
80d11f44 1626#define SPR_UPERF6 (0x316)
fd51ff63 1627#define SPR_POWER_PMC4 (0X316)
80d11f44 1628#define SPR_UPERF7 (0x317)
fd51ff63 1629#define SPR_POWER_PMC5 (0X317)
80d11f44 1630#define SPR_UPERF8 (0x318)
fd51ff63 1631#define SPR_POWER_PMC6 (0X318)
80d11f44 1632#define SPR_UPERF9 (0x319)
c36c97f8 1633#define SPR_970_PMC7 (0X319)
80d11f44 1634#define SPR_UPERFA (0x31A)
c36c97f8 1635#define SPR_970_PMC8 (0X31A)
80d11f44 1636#define SPR_UPERFB (0x31B)
fd51ff63 1637#define SPR_POWER_MMCR0 (0X31B)
80d11f44 1638#define SPR_UPERFC (0x31C)
fd51ff63 1639#define SPR_POWER_SIAR (0X31C)
80d11f44 1640#define SPR_UPERFD (0x31D)
fd51ff63 1641#define SPR_POWER_SDAR (0X31D)
80d11f44 1642#define SPR_UPERFE (0x31E)
fd51ff63 1643#define SPR_POWER_MMCR1 (0X31E)
80d11f44
JM		 1644#define SPR_UPERFF (0x31F)
1645#define SPR_RCPU_MI_RA0 (0x320)
1646#define SPR_MPC_MI_DBCAM (0x320)
4ee4a03b 1647#define SPR_BESCRS (0x320)
80d11f44
JM		 1648#define SPR_RCPU_MI_RA1 (0x321)
1649#define SPR_MPC_MI_DBRAM0 (0x321)
4ee4a03b 1650#define SPR_BESCRSU (0x321)
80d11f44
JM		 1651#define SPR_RCPU_MI_RA2 (0x322)
1652#define SPR_MPC_MI_DBRAM1 (0x322)
4ee4a03b 1653#define SPR_BESCRR (0x322)
80d11f44 1654#define SPR_RCPU_MI_RA3 (0x323)
4ee4a03b
AK		 1655#define SPR_BESCRRU (0x323)
1656#define SPR_EBBHR (0x324)
1657#define SPR_EBBRR (0x325)
1658#define SPR_BESCR (0x326)
80d11f44
JM		 1659#define SPR_RCPU_L2U_RA0 (0x328)
1660#define SPR_MPC_MD_DBCAM (0x328)
1661#define SPR_RCPU_L2U_RA1 (0x329)
1662#define SPR_MPC_MD_DBRAM0 (0x329)
1663#define SPR_RCPU_L2U_RA2 (0x32A)
1664#define SPR_MPC_MD_DBRAM1 (0x32A)
1665#define SPR_RCPU_L2U_RA3 (0x32B)
60511041 1666#define SPR_TAR (0x32F)
3ba55e39 1667#define SPR_VTB (0x351)
80d11f44
JM		 1668#define SPR_440_INV0 (0x370)
1669#define SPR_440_INV1 (0x371)
1670#define SPR_440_INV2 (0x372)
1671#define SPR_440_INV3 (0x373)
1672#define SPR_440_ITV0 (0x374)
1673#define SPR_440_ITV1 (0x375)
1674#define SPR_440_ITV2 (0x376)
1675#define SPR_440_ITV3 (0x377)
1676#define SPR_440_CCR1 (0x378)
1677#define SPR_DCRIPR (0x37B)
70c53407 1678#define SPR_POWER_MMCRS (0x37E)
80d11f44 1679#define SPR_PPR (0x380)
bd928eba 1680#define SPR_750_GQR0 (0x390)
80d11f44 1681#define SPR_440_DNV0 (0x390)
bd928eba 1682#define SPR_750_GQR1 (0x391)
80d11f44 1683#define SPR_440_DNV1 (0x391)
bd928eba 1684#define SPR_750_GQR2 (0x392)
80d11f44 1685#define SPR_440_DNV2 (0x392)
bd928eba 1686#define SPR_750_GQR3 (0x393)
80d11f44 1687#define SPR_440_DNV3 (0x393)
bd928eba 1688#define SPR_750_GQR4 (0x394)
80d11f44 1689#define SPR_440_DTV0 (0x394)
bd928eba 1690#define SPR_750_GQR5 (0x395)
80d11f44 1691#define SPR_440_DTV1 (0x395)
bd928eba 1692#define SPR_750_GQR6 (0x396)
80d11f44 1693#define SPR_440_DTV2 (0x396)
bd928eba 1694#define SPR_750_GQR7 (0x397)
80d11f44 1695#define SPR_440_DTV3 (0x397)
bd928eba
JM		 1696#define SPR_750_THRM4 (0x398)
1697#define SPR_750CL_HID2 (0x398)
80d11f44 1698#define SPR_440_DVLIM (0x398)
bd928eba 1699#define SPR_750_WPAR (0x399)
80d11f44 1700#define SPR_440_IVLIM (0x399)
bd928eba
JM		 1701#define SPR_750_DMAU (0x39A)
1702#define SPR_750_DMAL (0x39B)
80d11f44
JM		 1703#define SPR_440_RSTCFG (0x39B)
1704#define SPR_BOOKE_DCDBTRL (0x39C)
1705#define SPR_BOOKE_DCDBTRH (0x39D)
1706#define SPR_BOOKE_ICDBTRL (0x39E)
1707#define SPR_BOOKE_ICDBTRH (0x39F)
cb8b8bf8
AK		 1708#define SPR_74XX_UMMCR2 (0x3A0)
1709#define SPR_7XX_UPMC5 (0x3A1)
1710#define SPR_7XX_UPMC6 (0x3A2)
80d11f44 1711#define SPR_UBAMR (0x3A7)
cb8b8bf8
AK		 1712#define SPR_7XX_UMMCR0 (0x3A8)
1713#define SPR_7XX_UPMC1 (0x3A9)
1714#define SPR_7XX_UPMC2 (0x3AA)
1715#define SPR_7XX_USIAR (0x3AB)
1716#define SPR_7XX_UMMCR1 (0x3AC)
1717#define SPR_7XX_UPMC3 (0x3AD)
1718#define SPR_7XX_UPMC4 (0x3AE)
80d11f44
JM		 1719#define SPR_USDA (0x3AF)
1720#define SPR_40x_ZPR (0x3B0)
1721#define SPR_BOOKE_MAS7 (0x3B0)
cb8b8bf8
AK		 1722#define SPR_74XX_MMCR2 (0x3B0)
1723#define SPR_7XX_PMC5 (0x3B1)
80d11f44 1724#define SPR_40x_PID (0x3B1)
cb8b8bf8 1725#define SPR_7XX_PMC6 (0x3B2)
80d11f44 1726#define SPR_440_MMUCR (0x3B2)
80d11f44
JM		 1727#define SPR_4xx_CCR0 (0x3B3)
1728#define SPR_BOOKE_EPLC (0x3B3)
80d11f44
JM		 1729#define SPR_405_IAC3 (0x3B4)
1730#define SPR_BOOKE_EPSC (0x3B4)
80d11f44 1731#define SPR_405_IAC4 (0x3B5)
80d11f44 1732#define SPR_405_DVC1 (0x3B6)
80d11f44 1733#define SPR_405_DVC2 (0x3B7)
80d11f44 1734#define SPR_BAMR (0x3B7)
cb8b8bf8
AK		 1735#define SPR_7XX_MMCR0 (0x3B8)
1736#define SPR_7XX_PMC1 (0x3B9)
80d11f44 1737#define SPR_40x_SGR (0x3B9)
cb8b8bf8 1738#define SPR_7XX_PMC2 (0x3BA)
80d11f44 1739#define SPR_40x_DCWR (0x3BA)
cb8b8bf8 1740#define SPR_7XX_SIAR (0x3BB)
80d11f44 1741#define SPR_405_SLER (0x3BB)
cb8b8bf8 1742#define SPR_7XX_MMCR1 (0x3BC)
80d11f44 1743#define SPR_405_SU0R (0x3BC)
80d11f44 1744#define SPR_401_SKR (0x3BC)
cb8b8bf8 1745#define SPR_7XX_PMC3 (0x3BD)
80d11f44 1746#define SPR_405_DBCR1 (0x3BD)
cb8b8bf8 1747#define SPR_7XX_PMC4 (0x3BE)
80d11f44 1748#define SPR_SDA (0x3BF)
80d11f44
JM		 1749#define SPR_403_VTBL (0x3CC)
1750#define SPR_403_VTBU (0x3CD)
1751#define SPR_DMISS (0x3D0)
1752#define SPR_DCMP (0x3D1)
1753#define SPR_HASH1 (0x3D2)
1754#define SPR_HASH2 (0x3D3)
1755#define SPR_BOOKE_ICDBDR (0x3D3)
1756#define SPR_TLBMISS (0x3D4)
1757#define SPR_IMISS (0x3D4)
1758#define SPR_40x_ESR (0x3D4)
1759#define SPR_PTEHI (0x3D5)
1760#define SPR_ICMP (0x3D5)
1761#define SPR_40x_DEAR (0x3D5)
1762#define SPR_PTELO (0x3D6)
1763#define SPR_RPA (0x3D6)
1764#define SPR_40x_EVPR (0x3D6)
1765#define SPR_L3PM (0x3D7)
1766#define SPR_403_CDBCR (0x3D7)
4e777442 1767#define SPR_L3ITCR0 (0x3D8)
80d11f44
JM		 1768#define SPR_TCR (0x3D8)
1769#define SPR_40x_TSR (0x3D8)
1770#define SPR_IBR (0x3DA)
1771#define SPR_40x_TCR (0x3DA)
1772#define SPR_ESASRR (0x3DB)
1773#define SPR_40x_PIT (0x3DB)
1774#define SPR_403_TBL (0x3DC)
1775#define SPR_403_TBU (0x3DD)
1776#define SPR_SEBR (0x3DE)
1777#define SPR_40x_SRR2 (0x3DE)
1778#define SPR_SER (0x3DF)
1779#define SPR_40x_SRR3 (0x3DF)
4e777442 1780#define SPR_L3OHCR (0x3E8)
80d11f44
JM		 1781#define SPR_L3ITCR1 (0x3E9)
1782#define SPR_L3ITCR2 (0x3EA)
1783#define SPR_L3ITCR3 (0x3EB)
1784#define SPR_HID0 (0x3F0)
1785#define SPR_40x_DBSR (0x3F0)
1786#define SPR_HID1 (0x3F1)
1787#define SPR_IABR (0x3F2)
1788#define SPR_40x_DBCR0 (0x3F2)
1789#define SPR_601_HID2 (0x3F2)
1790#define SPR_Exxx_L1CSR0 (0x3F2)
1791#define SPR_ICTRL (0x3F3)
1792#define SPR_HID2 (0x3F3)
bd928eba 1793#define SPR_750CL_HID4 (0x3F3)
80d11f44
JM		 1794#define SPR_Exxx_L1CSR1 (0x3F3)
1795#define SPR_440_DBDR (0x3F3)
1796#define SPR_LDSTDB (0x3F4)
bd928eba 1797#define SPR_750_TDCL (0x3F4)
80d11f44
JM		 1798#define SPR_40x_IAC1 (0x3F4)
1799#define SPR_MMUCSR0 (0x3F4)
ba881002 1800#define SPR_970_HID4 (0x3F4)
80d11f44 1801#define SPR_DABR (0x3F5)
3fc6c082 1802#define DABR_MASK (~(target_ulong)0x7)
80d11f44
JM		 1803#define SPR_Exxx_BUCSR (0x3F5)
1804#define SPR_40x_IAC2 (0x3F5)
1805#define SPR_601_HID5 (0x3F5)
1806#define SPR_40x_DAC1 (0x3F6)
1807#define SPR_MSSCR0 (0x3F6)
1808#define SPR_970_HID5 (0x3F6)
1809#define SPR_MSSSR0 (0x3F7)
4e777442 1810#define SPR_MSSCR1 (0x3F7)
80d11f44
JM		 1811#define SPR_DABRX (0x3F7)
1812#define SPR_40x_DAC2 (0x3F7)
1813#define SPR_MMUCFG (0x3F7)
1814#define SPR_LDSTCR (0x3F8)
1815#define SPR_L2PMCR (0x3F8)
bd928eba 1816#define SPR_750FX_HID2 (0x3F8)
80d11f44
JM		 1817#define SPR_Exxx_L1FINV0 (0x3F8)
1818#define SPR_L2CR (0x3F9)
80d11f44 1819#define SPR_L3CR (0x3FA)
bd928eba 1820#define SPR_750_TDCH (0x3FA)
80d11f44
JM		 1821#define SPR_IABR2 (0x3FA)
1822#define SPR_40x_DCCR (0x3FA)
1823#define SPR_ICTC (0x3FB)
1824#define SPR_40x_ICCR (0x3FB)
1825#define SPR_THRM1 (0x3FC)
1826#define SPR_403_PBL1 (0x3FC)
1827#define SPR_SP (0x3FD)
1828#define SPR_THRM2 (0x3FD)
1829#define SPR_403_PBU1 (0x3FD)
1830#define SPR_604_HID13 (0x3FD)
1831#define SPR_LT (0x3FE)
1832#define SPR_THRM3 (0x3FE)
1833#define SPR_RCPU_FPECR (0x3FE)
1834#define SPR_403_PBL2 (0x3FE)
1835#define SPR_PIR (0x3FF)
1836#define SPR_403_PBU2 (0x3FF)
1837#define SPR_601_HID15 (0x3FF)
1838#define SPR_604_HID15 (0x3FF)
1839#define SPR_E500_SVR (0x3FF)
79aceca5 1840
84755ed5
AG		 1841/* Disable MAS Interrupt Updates for Hypervisor */
1842#define EPCR_DMIUH (1 << 22)
1843/* Disable Guest TLB Management Instructions */
1844#define EPCR_DGTMI (1 << 23)
1845/* Guest Interrupt Computation Mode */
1846#define EPCR_GICM (1 << 24)
1847/* Interrupt Computation Mode */
1848#define EPCR_ICM (1 << 25)
1849/* Disable Embedded Hypervisor Debug */
1850#define EPCR_DUVD (1 << 26)
1851/* Instruction Storage Interrupt Directed to Guest State */
1852#define EPCR_ISIGS (1 << 27)
1853/* Data Storage Interrupt Directed to Guest State */
1854#define EPCR_DSIGS (1 << 28)
1855/* Instruction TLB Error Interrupt Directed to Guest State */
1856#define EPCR_ITLBGS (1 << 29)
1857/* Data TLB Error Interrupt Directed to Guest State */
1858#define EPCR_DTLBGS (1 << 30)
1859/* External Input Interrupt Directed to Guest State */
1860#define EPCR_EXTGS (1 << 31)
1861
ea71258d
AG		 1862#define L1CSR0_CPE 0x00010000 /* Data Cache Parity Enable */
1863#define L1CSR0_CUL 0x00000400 /* (D-)Cache Unable to Lock */
1864#define L1CSR0_DCLFR 0x00000100 /* D-Cache Lock Flash Reset */
1865#define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */
1866#define L1CSR0_DCE 0x00000001 /* Data Cache Enable */
1867
1868#define L1CSR1_CPE 0x00010000 /* Instruction Cache Parity Enable */
1869#define L1CSR1_ICUL 0x00000400 /* I-Cache Unable to Lock */
1870#define L1CSR1_ICLFR 0x00000100 /* I-Cache Lock Flash Reset */
1871#define L1CSR1_ICFI 0x00000002 /* Instruction Cache Flash Invalidate */
1872#define L1CSR1_ICE 0x00000001 /* Instruction Cache Enable */
1873
bbc01ca7
AK		 1874/* HID0 bits */
1875#define HID0_DEEPNAP (1 << 24)
1876#define HID0_DOZE (1 << 23)
1877#define HID0_NAP (1 << 22)
1878
c29b735c
NF		 1879/*****************************************************************************/
1880/* PowerPC Instructions types definitions */
1881enum {
1882 PPC_NONE = 0x0000000000000000ULL,
1883 /* PowerPC base instructions set */
1884 PPC_INSNS_BASE = 0x0000000000000001ULL,
1885 /* integer operations instructions */
1886#define PPC_INTEGER PPC_INSNS_BASE
1887 /* flow control instructions */
1888#define PPC_FLOW PPC_INSNS_BASE
1889 /* virtual memory instructions */
1890#define PPC_MEM PPC_INSNS_BASE
1891 /* ld/st with reservation instructions */
1892#define PPC_RES PPC_INSNS_BASE
1893 /* spr/msr access instructions */
1894#define PPC_MISC PPC_INSNS_BASE
1895 /* Deprecated instruction sets */
1896 /* Original POWER instruction set */
1897 PPC_POWER = 0x0000000000000002ULL,
1898 /* POWER2 instruction set extension */
1899 PPC_POWER2 = 0x0000000000000004ULL,
1900 /* Power RTC support */
1901 PPC_POWER_RTC = 0x0000000000000008ULL,
1902 /* Power-to-PowerPC bridge (601) */
1903 PPC_POWER_BR = 0x0000000000000010ULL,
1904 /* 64 bits PowerPC instruction set */
1905 PPC_64B = 0x0000000000000020ULL,
1906 /* New 64 bits extensions (PowerPC 2.0x) */
1907 PPC_64BX = 0x0000000000000040ULL,
1908 /* 64 bits hypervisor extensions */
1909 PPC_64H = 0x0000000000000080ULL,
1910 /* New wait instruction (PowerPC 2.0x) */
1911 PPC_WAIT = 0x0000000000000100ULL,
1912 /* Time base mftb instruction */
1913 PPC_MFTB = 0x0000000000000200ULL,
1914
1915 /* Fixed-point unit extensions */
1916 /* PowerPC 602 specific */
1917 PPC_602_SPEC = 0x0000000000000400ULL,
1918 /* isel instruction */
1919 PPC_ISEL = 0x0000000000000800ULL,
1920 /* popcntb instruction */
1921 PPC_POPCNTB = 0x0000000000001000ULL,
1922 /* string load / store */
1923 PPC_STRING = 0x0000000000002000ULL,
1924
1925 /* Floating-point unit extensions */
1926 /* Optional floating point instructions */
1927 PPC_FLOAT = 0x0000000000010000ULL,
1928 /* New floating-point extensions (PowerPC 2.0x) */
1929 PPC_FLOAT_EXT = 0x0000000000020000ULL,
1930 PPC_FLOAT_FSQRT = 0x0000000000040000ULL,
1931 PPC_FLOAT_FRES = 0x0000000000080000ULL,
1932 PPC_FLOAT_FRSQRTE = 0x0000000000100000ULL,
1933 PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
1934 PPC_FLOAT_FSEL = 0x0000000000400000ULL,
1935 PPC_FLOAT_STFIWX = 0x0000000000800000ULL,
1936
1937 /* Vector/SIMD extensions */
1938 /* Altivec support */
1939 PPC_ALTIVEC = 0x0000000001000000ULL,
1940 /* PowerPC 2.03 SPE extension */
1941 PPC_SPE = 0x0000000002000000ULL,
1942 /* PowerPC 2.03 SPE single-precision floating-point extension */
1943 PPC_SPE_SINGLE = 0x0000000004000000ULL,
1944 /* PowerPC 2.03 SPE double-precision floating-point extension */
1945 PPC_SPE_DOUBLE = 0x0000000008000000ULL,
1946
1947 /* Optional memory control instructions */
1948 PPC_MEM_TLBIA = 0x0000000010000000ULL,
1949 PPC_MEM_TLBIE = 0x0000000020000000ULL,
1950 PPC_MEM_TLBSYNC = 0x0000000040000000ULL,
1951 /* sync instruction */
1952 PPC_MEM_SYNC = 0x0000000080000000ULL,
1953 /* eieio instruction */
1954 PPC_MEM_EIEIO = 0x0000000100000000ULL,
1955
1956 /* Cache control instructions */
1957 PPC_CACHE = 0x0000000200000000ULL,
1958 /* icbi instruction */
1959 PPC_CACHE_ICBI = 0x0000000400000000ULL,
8e33944f 1960 /* dcbz instruction */
c29b735c 1961 PPC_CACHE_DCBZ = 0x0000000800000000ULL,
c29b735c
NF		 1962 /* dcba instruction */
1963 PPC_CACHE_DCBA = 0x0000002000000000ULL,
1964 /* Freescale cache locking instructions */
1965 PPC_CACHE_LOCK = 0x0000004000000000ULL,
1966
1967 /* MMU related extensions */
1968 /* external control instructions */
1969 PPC_EXTERN = 0x0000010000000000ULL,
1970 /* segment register access instructions */
1971 PPC_SEGMENT = 0x0000020000000000ULL,
1972 /* PowerPC 6xx TLB management instructions */
1973 PPC_6xx_TLB = 0x0000040000000000ULL,
1974 /* PowerPC 74xx TLB management instructions */
1975 PPC_74xx_TLB = 0x0000080000000000ULL,
1976 /* PowerPC 40x TLB management instructions */
1977 PPC_40x_TLB = 0x0000100000000000ULL,
1978 /* segment register access instructions for PowerPC 64 "bridge" */
1979 PPC_SEGMENT_64B = 0x0000200000000000ULL,
1980 /* SLB management */
1981 PPC_SLBI = 0x0000400000000000ULL,
1982
1983 /* Embedded PowerPC dedicated instructions */
1984 PPC_WRTEE = 0x0001000000000000ULL,
1985 /* PowerPC 40x exception model */
1986 PPC_40x_EXCP = 0x0002000000000000ULL,
1987 /* PowerPC 405 Mac instructions */
1988 PPC_405_MAC = 0x0004000000000000ULL,
1989 /* PowerPC 440 specific instructions */
1990 PPC_440_SPEC = 0x0008000000000000ULL,
1991 /* BookE (embedded) PowerPC specification */
1992 PPC_BOOKE = 0x0010000000000000ULL,
1993 /* mfapidi instruction */
1994 PPC_MFAPIDI = 0x0020000000000000ULL,
1995 /* tlbiva instruction */
1996 PPC_TLBIVA = 0x0040000000000000ULL,
1997 /* tlbivax instruction */
1998 PPC_TLBIVAX = 0x0080000000000000ULL,
1999 /* PowerPC 4xx dedicated instructions */
2000 PPC_4xx_COMMON = 0x0100000000000000ULL,
2001 /* PowerPC 40x ibct instructions */
2002 PPC_40x_ICBT = 0x0200000000000000ULL,
2003 /* rfmci is not implemented in all BookE PowerPC */
2004 PPC_RFMCI = 0x0400000000000000ULL,
2005 /* rfdi instruction */
2006 PPC_RFDI = 0x0800000000000000ULL,
2007 /* DCR accesses */
2008 PPC_DCR = 0x1000000000000000ULL,
2009 /* DCR extended accesse */
2010 PPC_DCRX = 0x2000000000000000ULL,
2011 /* user-mode DCR access, implemented in PowerPC 460 */
2012 PPC_DCRUX = 0x4000000000000000ULL,
eaabeef2
DG		 2013 /* popcntw and popcntd instructions */
2014 PPC_POPCNTWD = 0x8000000000000000ULL,
01662f3e 2015
02d4eae4
DG		 2016#define PPC_TCG_INSNS (PPC_INSNS_BASE | PPC_POWER | PPC_POWER2 \
2017 | PPC_POWER_RTC | PPC_POWER_BR | PPC_64B \
2018 | PPC_64BX | PPC_64H | PPC_WAIT | PPC_MFTB \
2019 | PPC_602_SPEC | PPC_ISEL | PPC_POPCNTB \
2020 | PPC_STRING | PPC_FLOAT | PPC_FLOAT_EXT \
2021 | PPC_FLOAT_FSQRT | PPC_FLOAT_FRES \
2022 | PPC_FLOAT_FRSQRTE | PPC_FLOAT_FRSQRTES \
2023 | PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX \
2024 | PPC_ALTIVEC | PPC_SPE | PPC_SPE_SINGLE \
2025 | PPC_SPE_DOUBLE | PPC_MEM_TLBIA \
2026 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC \
2027 | PPC_MEM_SYNC | PPC_MEM_EIEIO \
2028 | PPC_CACHE | PPC_CACHE_ICBI \
8e33944f 2029 | PPC_CACHE_DCBZ \
02d4eae4
DG		 2030 | PPC_CACHE_DCBA | PPC_CACHE_LOCK \
2031 | PPC_EXTERN | PPC_SEGMENT | PPC_6xx_TLB \
2032 | PPC_74xx_TLB | PPC_40x_TLB | PPC_SEGMENT_64B \
2033 | PPC_SLBI | PPC_WRTEE | PPC_40x_EXCP \
2034 | PPC_405_MAC | PPC_440_SPEC | PPC_BOOKE \
2035 | PPC_MFAPIDI | PPC_TLBIVA | PPC_TLBIVAX \
2036 | PPC_4xx_COMMON | PPC_40x_ICBT | PPC_RFMCI \
2037 | PPC_RFDI | PPC_DCR | PPC_DCRX | PPC_DCRUX \
2038 | PPC_POPCNTWD)
2039
01662f3e
AG		 2040 /* extended type values */
2041
2042 /* BookE 2.06 PowerPC specification */
2043 PPC2_BOOKE206 = 0x0000000000000001ULL,
a7342588
DG		 2044 /* VSX (extensions to Altivec / VMX) */
2045 PPC2_VSX = 0x0000000000000002ULL,
2046 /* Decimal Floating Point (DFP) */
2047 PPC2_DFP = 0x0000000000000004ULL,
3f9f6a50
AG		 2048 /* Embedded.Processor Control */
2049 PPC2_PRCNTL = 0x0000000000000008ULL,
cd6e9320
TH		 2050 /* Byte-reversed, indexed, double-word load and store */
2051 PPC2_DBRX = 0x0000000000000010ULL,
9c2627b0
AJ		 2052 /* Book I 2.05 PowerPC specification */
2053 PPC2_ISA205 = 0x0000000000000020ULL,
dbcc48fa
TM		 2054 /* VSX additions in ISA 2.07 */
2055 PPC2_VSX207 = 0x0000000000000040ULL,
86ba37ed
TM		 2056 /* ISA 2.06B bpermd */
2057 PPC2_PERM_ISA206 = 0x0000000000000080ULL,
a824bc19
TM		 2058 /* ISA 2.06B divide extended variants */
2059 PPC2_DIVE_ISA206 = 0x0000000000000100ULL,
1fa6c533
TM		 2060 /* ISA 2.06B larx/stcx. instructions */
2061 PPC2_ATOMIC_ISA206 = 0x0000000000000200ULL,
1b0bd002
TM		 2062 /* ISA 2.06B floating point integer conversion */
2063 PPC2_FP_CVT_ISA206 = 0x0000000000000400ULL,
29a0e4e9
TM		 2064 /* ISA 2.06B floating point test instructions */
2065 PPC2_FP_TST_ISA206 = 0x0000000000000800ULL,
94840e07
TM		 2066 /* ISA 2.07 bctar instruction */
2067 PPC2_BCTAR_ISA207 = 0x0000000000001000ULL,
38a85337
TM		 2068 /* ISA 2.07 load/store quadword */
2069 PPC2_LSQ_ISA207 = 0x0000000000002000ULL,
32ea54ab
TM		 2070 /* ISA 2.07 Altivec */
2071 PPC2_ALTIVEC_207 = 0x0000000000004000ULL,
df99d30d
AK		 2072 /* PowerISA 2.07 Book3s specification */
2073 PPC2_ISA207S = 0x0000000000008000ULL,
4171853c
PM		 2074 /* Double precision floating point conversion for signed integer 64 */
2075 PPC2_FP_CVT_S64 = 0x0000000000010000ULL,
f90468b6
TM		 2076 /* Transactional Memory (ISA 2.07, Book II) */
2077 PPC2_TM = 0x0000000000020000ULL,
02d4eae4 2078
74f23997 2079#define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX | \
a824bc19 2080 PPC2_ISA205 | PPC2_VSX207 | PPC2_PERM_ISA206 | \
1b0bd002 2081 PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | \
94840e07 2082 PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | \
32ea54ab 2083 PPC2_BCTAR_ISA207 | PPC2_LSQ_ISA207 | \
4171853c 2084 PPC2_ALTIVEC_207 | PPC2_ISA207S | PPC2_DFP | \
f90468b6 2085 PPC2_FP_CVT_S64 | PPC2_TM)
c29b735c
NF		 2086};
2087
76a66253 2088/*****************************************************************************/
9a64fbe4
FB		 2089/* Memory access type :
2090 * may be needed for precise access rights control and precise exceptions.
2091 */
79aceca5 2092enum {
9a64fbe4
FB		 2093 /* 1 bit to define user level / supervisor access */
2094 ACCESS_USER = 0x00,
2095 ACCESS_SUPER = 0x01,
2096 /* Type of instruction that generated the access */
2097 ACCESS_CODE = 0x10, /* Code fetch access */
2098 ACCESS_INT = 0x20, /* Integer load/store access */
2099 ACCESS_FLOAT = 0x30, /* floating point load/store access */
2100 ACCESS_RES = 0x40, /* load/store with reservation */
2101 ACCESS_EXT = 0x50, /* external access */
2102 ACCESS_CACHE = 0x60, /* Cache manipulation */
2103};
2104
47103572
JM		 2105/* Hardware interruption sources:
2106 * all those exception can be raised simulteaneously
2107 */
e9df014c
JM		 2108/* Input pins definitions */
2109enum {
2110 /* 6xx bus input pins */
24be5ae3
JM		 2111 PPC6xx_INPUT_HRESET = 0,
2112 PPC6xx_INPUT_SRESET = 1,
2113 PPC6xx_INPUT_CKSTP_IN = 2,
2114 PPC6xx_INPUT_MCP = 3,
2115 PPC6xx_INPUT_SMI = 4,
2116 PPC6xx_INPUT_INT = 5,
d68f1306
JM		 2117 PPC6xx_INPUT_TBEN = 6,
2118 PPC6xx_INPUT_WAKEUP = 7,
2119 PPC6xx_INPUT_NB,
24be5ae3
JM		 2120};
2121
2122enum {
e9df014c 2123 /* Embedded PowerPC input pins */
24be5ae3
JM		 2124 PPCBookE_INPUT_HRESET = 0,
2125 PPCBookE_INPUT_SRESET = 1,
2126 PPCBookE_INPUT_CKSTP_IN = 2,
2127 PPCBookE_INPUT_MCP = 3,
2128 PPCBookE_INPUT_SMI = 4,
2129 PPCBookE_INPUT_INT = 5,
2130 PPCBookE_INPUT_CINT = 6,
d68f1306 2131 PPCBookE_INPUT_NB,
24be5ae3
JM		 2132};
2133
9fdc60bf
AJ		 2134enum {
2135 /* PowerPC E500 input pins */
2136 PPCE500_INPUT_RESET_CORE = 0,
2137 PPCE500_INPUT_MCK = 1,
2138 PPCE500_INPUT_CINT = 3,
2139 PPCE500_INPUT_INT = 4,
2140 PPCE500_INPUT_DEBUG = 6,
2141 PPCE500_INPUT_NB,
2142};
2143
a750fc0b 2144enum {
4e290a0b
JM		 2145 /* PowerPC 40x input pins */
2146 PPC40x_INPUT_RESET_CORE = 0,
2147 PPC40x_INPUT_RESET_CHIP = 1,
2148 PPC40x_INPUT_RESET_SYS = 2,
2149 PPC40x_INPUT_CINT = 3,
2150 PPC40x_INPUT_INT = 4,
2151 PPC40x_INPUT_HALT = 5,
2152 PPC40x_INPUT_DEBUG = 6,
2153 PPC40x_INPUT_NB,
e9df014c
JM		 2154};
2155
b4095fed
JM		 2156enum {
2157 /* RCPU input pins */
2158 PPCRCPU_INPUT_PORESET = 0,
2159 PPCRCPU_INPUT_HRESET = 1,
2160 PPCRCPU_INPUT_SRESET = 2,
2161 PPCRCPU_INPUT_IRQ0 = 3,
2162 PPCRCPU_INPUT_IRQ1 = 4,
2163 PPCRCPU_INPUT_IRQ2 = 5,
2164 PPCRCPU_INPUT_IRQ3 = 6,
2165 PPCRCPU_INPUT_IRQ4 = 7,
2166 PPCRCPU_INPUT_IRQ5 = 8,
2167 PPCRCPU_INPUT_IRQ6 = 9,
2168 PPCRCPU_INPUT_IRQ7 = 10,
2169 PPCRCPU_INPUT_NB,
2170};
2171
00af685f 2172#if defined(TARGET_PPC64)
d0dfae6e
JM		 2173enum {
2174 /* PowerPC 970 input pins */
2175 PPC970_INPUT_HRESET = 0,
2176 PPC970_INPUT_SRESET = 1,
2177 PPC970_INPUT_CKSTP = 2,
2178 PPC970_INPUT_TBEN = 3,
2179 PPC970_INPUT_MCP = 4,
2180 PPC970_INPUT_INT = 5,
2181 PPC970_INPUT_THINT = 6,
7b62a955 2182 PPC970_INPUT_NB,
9d52e907
DG		 2183};
2184
2185enum {
2186 /* POWER7 input pins */
2187 POWER7_INPUT_INT = 0,
2188 /* POWER7 probably has other inputs, but we don't care about them
2189 * for any existing machine. We can wire these up when we need
2190 * them */
2191 POWER7_INPUT_NB,
d0dfae6e 2192};
00af685f 2193#endif
d0dfae6e 2194
e9df014c 2195/* Hardware exceptions definitions */
47103572 2196enum {
e9df014c 2197 /* External hardware exception sources */
e1833e1f 2198 PPC_INTERRUPT_RESET = 0, /* Reset exception */
d68f1306
JM		 2199 PPC_INTERRUPT_WAKEUP, /* Wakeup exception */
2200 PPC_INTERRUPT_MCK, /* Machine check exception */
2201 PPC_INTERRUPT_EXT, /* External interrupt */
2202 PPC_INTERRUPT_SMI, /* System management interrupt */
2203 PPC_INTERRUPT_CEXT, /* Critical external interrupt */
2204 PPC_INTERRUPT_DEBUG, /* External debug exception */
2205 PPC_INTERRUPT_THERM, /* Thermal exception */
e9df014c 2206 /* Internal hardware exception sources */
d68f1306
JM		 2207 PPC_INTERRUPT_DECR, /* Decrementer exception */
2208 PPC_INTERRUPT_HDECR, /* Hypervisor decrementer exception */
2209 PPC_INTERRUPT_PIT, /* Programmable inteval timer interrupt */
2210 PPC_INTERRUPT_FIT, /* Fixed interval timer interrupt */
2211 PPC_INTERRUPT_WDT, /* Watchdog timer interrupt */
2212 PPC_INTERRUPT_CDOORBELL, /* Critical doorbell interrupt */
2213 PPC_INTERRUPT_DOORBELL, /* Doorbell interrupt */
2214 PPC_INTERRUPT_PERFM, /* Performance monitor interrupt */
47103572
JM		 2215};
2216
6d9412ea
AK		 2217/* Processor Compatibility mask (PCR) */
2218enum {
2219 PCR_COMPAT_2_05 = 1ull << (63-62),
2220 PCR_COMPAT_2_06 = 1ull << (63-61),
2221 PCR_VEC_DIS = 1ull << (63-0), /* Vec. disable (bit NA since POWER8) */
2222 PCR_VSX_DIS = 1ull << (63-1), /* VSX disable (bit NA since POWER8) */
2223 PCR_TM_DIS = 1ull << (63-2), /* Trans. memory disable (POWER8) */
2224};
2225
9a64fbe4
FB		 2226/*****************************************************************************/
2227
da91a00f
RH		 2228static inline target_ulong cpu_read_xer(CPUPPCState *env)
2229{
2230 return env->xer | (env->so << XER_SO) | (env->ov << XER_OV) | (env->ca << XER_CA);
2231}
2232
2233static inline void cpu_write_xer(CPUPPCState *env, target_ulong xer)
2234{
2235 env->so = (xer >> XER_SO) & 1;
2236 env->ov = (xer >> XER_OV) & 1;
2237 env->ca = (xer >> XER_CA) & 1;
2238 env->xer = xer & ~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA));
2239}
2240
1328c2bf 2241static inline void cpu_get_tb_cpu_state(CPUPPCState *env, target_ulong *pc,
6b917547
AL		 2242 target_ulong *cs_base, int *flags)
2243{
2244 *pc = env->nip;
2245 *cs_base = 0;
2246 *flags = env->hflags;
2247}
2248
01662f3e 2249#if !defined(CONFIG_USER_ONLY)
1328c2bf 2250static inline int booke206_tlbm_id(CPUPPCState *env, ppcmas_tlb_t *tlbm)
01662f3e 2251{
d1e256fe 2252 uintptr_t tlbml = (uintptr_t)tlbm;
1c53accc 2253 uintptr_t tlbl = (uintptr_t)env->tlb.tlbm;
01662f3e 2254
1c53accc 2255 return (tlbml - tlbl) / sizeof(env->tlb.tlbm[0]);
01662f3e
AG		 2256}
2257
1328c2bf 2258static inline int booke206_tlb_size(CPUPPCState *env, int tlbn)
01662f3e
AG		 2259{
2260 uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2261 int r = tlbncfg & TLBnCFG_N_ENTRY;
2262 return r;
2263}
2264
1328c2bf 2265static inline int booke206_tlb_ways(CPUPPCState *env, int tlbn)
01662f3e
AG		 2266{
2267 uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2268 int r = tlbncfg >> TLBnCFG_ASSOC_SHIFT;
2269 return r;
2270}
2271
1328c2bf 2272static inline int booke206_tlbm_to_tlbn(CPUPPCState *env, ppcmas_tlb_t *tlbm)
01662f3e 2273{
d1e256fe 2274 int id = booke206_tlbm_id(env, tlbm);
01662f3e
AG		 2275 int end = 0;
2276 int i;
2277
2278 for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
2279 end += booke206_tlb_size(env, i);
2280 if (id < end) {
2281 return i;
2282 }
2283 }
2284
a47dddd7 2285 cpu_abort(CPU(ppc_env_get_cpu(env)), "Unknown TLBe: %d\n", id);
01662f3e
AG		 2286 return 0;
2287}
2288
1328c2bf 2289static inline int booke206_tlbm_to_way(CPUPPCState *env, ppcmas_tlb_t *tlb)
01662f3e 2290{
d1e256fe
AG		 2291 int tlbn = booke206_tlbm_to_tlbn(env, tlb);
2292 int tlbid = booke206_tlbm_id(env, tlb);
01662f3e
AG		 2293 return tlbid & (booke206_tlb_ways(env, tlbn) - 1);
2294}
2295
1328c2bf 2296static inline ppcmas_tlb_t *booke206_get_tlbm(CPUPPCState *env, const int tlbn,
01662f3e
AG		 2297 target_ulong ea, int way)
2298{
2299 int r;
2300 uint32_t ways = booke206_tlb_ways(env, tlbn);
786a4ea8
SH		 2301 int ways_bits = ctz32(ways);
2302 int tlb_bits = ctz32(booke206_tlb_size(env, tlbn));
01662f3e
AG		 2303 int i;
2304
2305 way &= ways - 1;
2306 ea >>= MAS2_EPN_SHIFT;
2307 ea &= (1 << (tlb_bits - ways_bits)) - 1;
2308 r = (ea << ways_bits) | way;
2309
3f162d11
AG		 2310 if (r >= booke206_tlb_size(env, tlbn)) {
2311 return NULL;
2312 }
2313
01662f3e
AG		 2314 /* bump up to tlbn index */
2315 for (i = 0; i < tlbn; i++) {
2316 r += booke206_tlb_size(env, i);
2317 }
2318
1c53accc 2319 return &env->tlb.tlbm[r];
01662f3e
AG		 2320}
2321
a1ef618a 2322/* returns bitmap of supported page sizes for a given TLB */
1328c2bf 2323static inline uint32_t booke206_tlbnps(CPUPPCState *env, const int tlbn)
a1ef618a
AG		 2324{
2325 bool mav2 = false;
2326 uint32_t ret = 0;
2327
2328 if (mav2) {
2329 ret = env->spr[SPR_BOOKE_TLB0PS + tlbn];
2330 } else {
2331 uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2332 uint32_t min = (tlbncfg & TLBnCFG_MINSIZE) >> TLBnCFG_MINSIZE_SHIFT;
2333 uint32_t max = (tlbncfg & TLBnCFG_MAXSIZE) >> TLBnCFG_MAXSIZE_SHIFT;
2334 int i;
2335 for (i = min; i <= max; i++) {
2336 ret |= (1 << (i << 1));
2337 }
2338 }
2339
2340 return ret;
2341}
2342
01662f3e
AG		 2343#endif
2344
e42a61f1
AG		 2345static inline bool msr_is_64bit(CPUPPCState *env, target_ulong msr)
2346{
2347 if (env->mmu_model == POWERPC_MMU_BOOKE206) {
2348 return msr & (1ULL << MSR_CM);
2349 }
2350
2351 return msr & (1ULL << MSR_SF);
2352}
2353
1b14670a 2354extern void (*cpu_ppc_hypercall)(PowerPCCPU *);
d569956e 2355
022c62cb 2356#include "exec/exec-all.h"
f081c76c 2357
1328c2bf 2358void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env);
bebabbc7 2359
0ce470cd
AK		 2360/**
2361 * ppc_get_vcpu_dt_id:
2362 * @cs: a PowerPCCPU struct.
2363 *
2364 * Returns a device-tree ID for a CPU.
2365 */
2366int ppc_get_vcpu_dt_id(PowerPCCPU *cpu);
2367
2368/**
2369 * ppc_get_vcpu_by_dt_id:
2370 * @cpu_dt_id: a device tree id
2371 *
2372 * Searches for a CPU by @cpu_dt_id.
2373 *
2374 * Returns: a PowerPCCPU struct
2375 */
2376PowerPCCPU *ppc_get_vcpu_by_dt_id(int cpu_dt_id);
2377
376dbce0 2378void ppc_maybe_bswap_register(CPUPPCState *env, uint8_t *mem_buf, int len);
79aceca5 2379#endif /* !defined (__CPU_PPC_H__) */
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