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target/ppc: Eliminate htab_base and htab_mask variables
[qemu.git] / target / ppc / cpu.h
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79aceca5 1/*
3fc6c082 2 * PowerPC emulation cpu definitions for qemu.
5fafdf24 3 *
76a66253 4 * Copyright (c) 2003-2007 Jocelyn Mayer
79aceca5
FB		 5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
8167ee88 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
79aceca5 18 */
07f5a258
MA		 19
20#ifndef PPC_CPU_H
21#define PPC_CPU_H
79aceca5 22
9a78eead 23#include "qemu-common.h"
60caf221 24#include "qemu/int128.h"
3fc6c082 25
a4f30719
JM		 26//#define PPC_EMULATE_32BITS_HYPV
27
76a66253 28#if defined (TARGET_PPC64)
3cd7d1dd 29/* PowerPC 64 definitions */
d9d7210c 30#define TARGET_LONG_BITS 64
35cdaad6 31#define TARGET_PAGE_BITS 12
3cd7d1dd 32
52705890
RH		 33/* Note that the official physical address space bits is 62-M where M
34 is implementation dependent. I've not looked up M for the set of
35 cpus we emulate at the system level. */
36#define TARGET_PHYS_ADDR_SPACE_BITS 62
37
38/* Note that the PPC environment architecture talks about 80 bit virtual
39 addresses, with segmentation. Obviously that's not all visible to a
40 single process, which is all we're concerned with here. */
41#ifdef TARGET_ABI32
42# define TARGET_VIRT_ADDR_SPACE_BITS 32
43#else
44# define TARGET_VIRT_ADDR_SPACE_BITS 64
45#endif
46
ad3e67d0 47#define TARGET_PAGE_BITS_64K 16
81762d6d
DG		 48#define TARGET_PAGE_BITS_16M 24
49
3cd7d1dd
JM		 50#else /* defined (TARGET_PPC64) */
51/* PowerPC 32 definitions */
d9d7210c 52#define TARGET_LONG_BITS 32
3cd7d1dd
JM		 53
54#if defined(TARGET_PPCEMB)
55/* Specific definitions for PowerPC embedded */
56/* BookE have 36 bits physical address space */
3cd7d1dd
JM		 57#if defined(CONFIG_USER_ONLY)
58/* It looks like a lot of Linux programs assume page size
59 * is 4kB long. This is evil, but we have to deal with it...
60 */
35cdaad6 61#define TARGET_PAGE_BITS 12
3cd7d1dd
JM		 62#else /* defined(CONFIG_USER_ONLY) */
63/* Pages can be 1 kB small */
64#define TARGET_PAGE_BITS 10
65#endif /* defined(CONFIG_USER_ONLY) */
66#else /* defined(TARGET_PPCEMB) */
67/* "standard" PowerPC 32 definitions */
68#define TARGET_PAGE_BITS 12
69#endif /* defined(TARGET_PPCEMB) */
70
8b242eba 71#define TARGET_PHYS_ADDR_SPACE_BITS 36
52705890
RH		 72#define TARGET_VIRT_ADDR_SPACE_BITS 32
73
3cd7d1dd 74#endif /* defined (TARGET_PPC64) */
3cf1e035 75
9349b4f9 76#define CPUArchState struct CPUPPCState
c2764719 77
022c62cb 78#include "exec/cpu-defs.h"
2d34fe39 79#include "cpu-qom.h"
6b4c305c 80#include "fpu/softfloat.h"
4ecc3190 81
7f70c937 82#if defined (TARGET_PPC64)
4ecd4d16 83#define PPC_ELF_MACHINE EM_PPC64
76a66253 84#else
4ecd4d16 85#define PPC_ELF_MACHINE EM_PPC
76a66253 86#endif
9042c0e2 87
e1833e1f
JM		 88/*****************************************************************************/
89/* Exception vectors definitions */
90enum {
91 POWERPC_EXCP_NONE = -1,
92 /* The 64 first entries are used by the PowerPC embedded specification */
93 POWERPC_EXCP_CRITICAL = 0, /* Critical input */
94 POWERPC_EXCP_MCHECK = 1, /* Machine check exception */
95 POWERPC_EXCP_DSI = 2, /* Data storage exception */
96 POWERPC_EXCP_ISI = 3, /* Instruction storage exception */
97 POWERPC_EXCP_EXTERNAL = 4, /* External input */
98 POWERPC_EXCP_ALIGN = 5, /* Alignment exception */
99 POWERPC_EXCP_PROGRAM = 6, /* Program exception */
100 POWERPC_EXCP_FPU = 7, /* Floating-point unavailable exception */
101 POWERPC_EXCP_SYSCALL = 8, /* System call exception */
102 POWERPC_EXCP_APU = 9, /* Auxiliary processor unavailable */
103 POWERPC_EXCP_DECR = 10, /* Decrementer exception */
104 POWERPC_EXCP_FIT = 11, /* Fixed-interval timer interrupt */
105 POWERPC_EXCP_WDT = 12, /* Watchdog timer interrupt */
b4095fed
JM		 106 POWERPC_EXCP_DTLB = 13, /* Data TLB miss */
107 POWERPC_EXCP_ITLB = 14, /* Instruction TLB miss */
e1833e1f
JM		 108 POWERPC_EXCP_DEBUG = 15, /* Debug interrupt */
109 /* Vectors 16 to 31 are reserved */
e1833e1f
JM		 110 POWERPC_EXCP_SPEU = 32, /* SPE/embedded floating-point unavailable */
111 POWERPC_EXCP_EFPDI = 33, /* Embedded floating-point data interrupt */
112 POWERPC_EXCP_EFPRI = 34, /* Embedded floating-point round interrupt */
113 POWERPC_EXCP_EPERFM = 35, /* Embedded performance monitor interrupt */
114 POWERPC_EXCP_DOORI = 36, /* Embedded doorbell interrupt */
115 POWERPC_EXCP_DOORCI = 37, /* Embedded doorbell critical interrupt */
0ef654e3
AG		 116 POWERPC_EXCP_GDOORI = 38, /* Embedded guest doorbell interrupt */
117 POWERPC_EXCP_GDOORCI = 39, /* Embedded guest doorbell critical interrupt*/
118 POWERPC_EXCP_HYPPRIV = 41, /* Embedded hypervisor priv instruction */
119 /* Vectors 42 to 63 are reserved */
e1833e1f 120 /* Exceptions defined in the PowerPC server specification */
f03a1af5
BH		 121 /* Server doorbell variants */
122#define POWERPC_EXCP_SDOOR POWERPC_EXCP_GDOORI
123#define POWERPC_EXCP_SDOOR_HV POWERPC_EXCP_DOORI
e1833e1f 124 POWERPC_EXCP_RESET = 64, /* System reset exception */
e1833e1f
JM		 125 POWERPC_EXCP_DSEG = 65, /* Data segment exception */
126 POWERPC_EXCP_ISEG = 66, /* Instruction segment exception */
e1833e1f 127 POWERPC_EXCP_HDECR = 67, /* Hypervisor decrementer exception */
e1833e1f 128 POWERPC_EXCP_TRACE = 68, /* Trace exception */
e1833e1f
JM		 129 POWERPC_EXCP_HDSI = 69, /* Hypervisor data storage exception */
130 POWERPC_EXCP_HISI = 70, /* Hypervisor instruction storage exception */
131 POWERPC_EXCP_HDSEG = 71, /* Hypervisor data segment exception */
132 POWERPC_EXCP_HISEG = 72, /* Hypervisor instruction segment exception */
e1833e1f
JM		 133 POWERPC_EXCP_VPU = 73, /* Vector unavailable exception */
134 /* 40x specific exceptions */
135 POWERPC_EXCP_PIT = 74, /* Programmable interval timer interrupt */
136 /* 601 specific exceptions */
137 POWERPC_EXCP_IO = 75, /* IO error exception */
138 POWERPC_EXCP_RUNM = 76, /* Run mode exception */
139 /* 602 specific exceptions */
140 POWERPC_EXCP_EMUL = 77, /* Emulation trap exception */
141 /* 602/603 specific exceptions */
b4095fed 142 POWERPC_EXCP_IFTLB = 78, /* Instruction fetch TLB miss */
e1833e1f
JM		 143 POWERPC_EXCP_DLTLB = 79, /* Data load TLB miss */
144 POWERPC_EXCP_DSTLB = 80, /* Data store TLB miss */
145 /* Exceptions available on most PowerPC */
146 POWERPC_EXCP_FPA = 81, /* Floating-point assist exception */
b4095fed
JM		 147 POWERPC_EXCP_DABR = 82, /* Data address breakpoint */
148 POWERPC_EXCP_IABR = 83, /* Instruction address breakpoint */
149 POWERPC_EXCP_SMI = 84, /* System management interrupt */
150 POWERPC_EXCP_PERFM = 85, /* Embedded performance monitor interrupt */
e1833e1f 151 /* 7xx/74xx specific exceptions */
b4095fed 152 POWERPC_EXCP_THERM = 86, /* Thermal interrupt */
e1833e1f 153 /* 74xx specific exceptions */
b4095fed 154 POWERPC_EXCP_VPUA = 87, /* Vector assist exception */
e1833e1f 155 /* 970FX specific exceptions */
b4095fed
JM		 156 POWERPC_EXCP_SOFTP = 88, /* Soft patch exception */
157 POWERPC_EXCP_MAINT = 89, /* Maintenance exception */
5b46d07d 158 /* Freescale embedded cores specific exceptions */
b4095fed
JM		 159 POWERPC_EXCP_MEXTBR = 90, /* Maskable external breakpoint */
160 POWERPC_EXCP_NMEXTBR = 91, /* Non maskable external breakpoint */
161 POWERPC_EXCP_ITLBE = 92, /* Instruction TLB error */
162 POWERPC_EXCP_DTLBE = 93, /* Data TLB error */
1f29871c
TM		 163 /* VSX Unavailable (Power ISA 2.06 and later) */
164 POWERPC_EXCP_VSXU = 94, /* VSX Unavailable */
7019cb3d 165 POWERPC_EXCP_FU = 95, /* Facility Unavailable */
f03a1af5
BH		 166 /* Additional ISA 2.06 and later server exceptions */
167 POWERPC_EXCP_HV_EMU = 96, /* HV emulation assistance */
168 POWERPC_EXCP_HV_MAINT = 97, /* HMI */
169 POWERPC_EXCP_HV_FU = 98, /* Hypervisor Facility unavailable */
e1833e1f 170 /* EOL */
f03a1af5 171 POWERPC_EXCP_NB = 99,
5cbdb3a3 172 /* QEMU exceptions: used internally during code translation */
e1833e1f
JM		 173 POWERPC_EXCP_STOP = 0x200, /* stop translation */
174 POWERPC_EXCP_BRANCH = 0x201, /* branch instruction */
5cbdb3a3 175 /* QEMU exceptions: special cases we want to stop translation */
e1833e1f
JM		 176 POWERPC_EXCP_SYNC = 0x202, /* context synchronizing instruction */
177 POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only */
4425265b 178 POWERPC_EXCP_STCX = 0x204 /* Conditional stores in user mode */
e1833e1f
JM		 179};
180
e1833e1f
JM		 181/* Exceptions error codes */
182enum {
183 /* Exception subtypes for POWERPC_EXCP_ALIGN */
184 POWERPC_EXCP_ALIGN_FP = 0x01, /* FP alignment exception */
185 POWERPC_EXCP_ALIGN_LST = 0x02, /* Unaligned mult/extern load/store */
186 POWERPC_EXCP_ALIGN_LE = 0x03, /* Multiple little-endian access */
187 POWERPC_EXCP_ALIGN_PROT = 0x04, /* Access cross protection boundary */
188 POWERPC_EXCP_ALIGN_BAT = 0x05, /* Access cross a BAT/seg boundary */
189 POWERPC_EXCP_ALIGN_CACHE = 0x06, /* Impossible dcbz access */
190 /* Exception subtypes for POWERPC_EXCP_PROGRAM */
191 /* FP exceptions */
192 POWERPC_EXCP_FP = 0x10,
193 POWERPC_EXCP_FP_OX = 0x01, /* FP overflow */
194 POWERPC_EXCP_FP_UX = 0x02, /* FP underflow */
195 POWERPC_EXCP_FP_ZX = 0x03, /* FP divide by zero */
196 POWERPC_EXCP_FP_XX = 0x04, /* FP inexact */
7c58044c 197 POWERPC_EXCP_FP_VXSNAN = 0x05, /* FP invalid SNaN op */
e1833e1f
JM		 198 POWERPC_EXCP_FP_VXISI = 0x06, /* FP invalid infinite subtraction */
199 POWERPC_EXCP_FP_VXIDI = 0x07, /* FP invalid infinite divide */
200 POWERPC_EXCP_FP_VXZDZ = 0x08, /* FP invalid zero divide */
201 POWERPC_EXCP_FP_VXIMZ = 0x09, /* FP invalid infinite * zero */
202 POWERPC_EXCP_FP_VXVC = 0x0A, /* FP invalid compare */
203 POWERPC_EXCP_FP_VXSOFT = 0x0B, /* FP invalid operation */
204 POWERPC_EXCP_FP_VXSQRT = 0x0C, /* FP invalid square root */
205 POWERPC_EXCP_FP_VXCVI = 0x0D, /* FP invalid integer conversion */
206 /* Invalid instruction */
207 POWERPC_EXCP_INVAL = 0x20,
208 POWERPC_EXCP_INVAL_INVAL = 0x01, /* Invalid instruction */
209 POWERPC_EXCP_INVAL_LSWX = 0x02, /* Invalid lswx instruction */
210 POWERPC_EXCP_INVAL_SPR = 0x03, /* Invalid SPR access */
211 POWERPC_EXCP_INVAL_FP = 0x04, /* Unimplemented mandatory fp instr */
212 /* Privileged instruction */
213 POWERPC_EXCP_PRIV = 0x30,
214 POWERPC_EXCP_PRIV_OPC = 0x01, /* Privileged operation exception */
215 POWERPC_EXCP_PRIV_REG = 0x02, /* Privileged register exception */
216 /* Trap */
217 POWERPC_EXCP_TRAP = 0x40,
218};
219
a750fc0b 220#define PPC_INPUT(env) (env->bus_model)
3fc6c082 221
be147d08 222/*****************************************************************************/
c227f099 223typedef struct opc_handler_t opc_handler_t;
79aceca5 224
3fc6c082 225/*****************************************************************************/
7222b94a 226/* Types used to describe some PowerPC registers etc. */
69b058c8 227typedef struct DisasContext DisasContext;
c227f099 228typedef struct ppc_spr_t ppc_spr_t;
c227f099
AL		 229typedef union ppc_avr_t ppc_avr_t;
230typedef union ppc_tlb_t ppc_tlb_t;
1ad9f0a4 231typedef struct ppc_hash_pte64 ppc_hash_pte64_t;
76a66253 232
3fc6c082 233/* SPR access micro-ops generations callbacks */
c227f099 234struct ppc_spr_t {
69b058c8
PB		 235 void (*uea_read)(DisasContext *ctx, int gpr_num, int spr_num);
236 void (*uea_write)(DisasContext *ctx, int spr_num, int gpr_num);
76a66253 237#if !defined(CONFIG_USER_ONLY)
69b058c8
PB		 238 void (*oea_read)(DisasContext *ctx, int gpr_num, int spr_num);
239 void (*oea_write)(DisasContext *ctx, int spr_num, int gpr_num);
240 void (*hea_read)(DisasContext *ctx, int gpr_num, int spr_num);
241 void (*hea_write)(DisasContext *ctx, int spr_num, int gpr_num);
76a66253 242#endif
b55266b5 243 const char *name;
d197fdbc 244 target_ulong default_value;
d67d40ea
DG		 245#ifdef CONFIG_KVM
246 /* We (ab)use the fact that all the SPRs will have ids for the
247 * ONE_REG interface will have KVM_REG_PPC to use 0 as meaning,
248 * don't sync this */
249 uint64_t one_reg_id;
250#endif
3fc6c082
FB		 251};
252
253/* Altivec registers (128 bits) */
c227f099 254union ppc_avr_t {
0f6fbcbc 255 float32 f[4];
a9d9eb8f
JM		 256 uint8_t u8[16];
257 uint16_t u16[8];
258 uint32_t u32[4];
ab5f265d
AJ		 259 int8_t s8[16];
260 int16_t s16[8];
261 int32_t s32[4];
a9d9eb8f 262 uint64_t u64[2];
bb527533
TM		 263 int64_t s64[2];
264#ifdef CONFIG_INT128
265 __uint128_t u128;
266#endif
60caf221 267 Int128 s128;
3fc6c082 268};
9fddaa0c 269
3c7b48b7 270#if !defined(CONFIG_USER_ONLY)
3fc6c082 271/* Software TLB cache */
c227f099
AL		 272typedef struct ppc6xx_tlb_t ppc6xx_tlb_t;
273struct ppc6xx_tlb_t {
76a66253
JM		 274 target_ulong pte0;
275 target_ulong pte1;
276 target_ulong EPN;
1d0a48fb
JM		 277};
278
c227f099
AL		 279typedef struct ppcemb_tlb_t ppcemb_tlb_t;
280struct ppcemb_tlb_t {
b162d02e 281 uint64_t RPN;
1d0a48fb 282 target_ulong EPN;
76a66253 283 target_ulong PID;
c55e9aef
JM		 284 target_ulong size;
285 uint32_t prot;
286 uint32_t attr; /* Storage attributes */
1d0a48fb
JM		 287};
288
d1e256fe
AG		 289typedef struct ppcmas_tlb_t {
290 uint32_t mas8;
291 uint32_t mas1;
292 uint64_t mas2;
293 uint64_t mas7_3;
294} ppcmas_tlb_t;
295
c227f099 296union ppc_tlb_t {
1c53accc
AG		 297 ppc6xx_tlb_t *tlb6;
298 ppcemb_tlb_t *tlbe;
299 ppcmas_tlb_t *tlbm;
3fc6c082 300};
1c53accc
AG		 301
302/* possible TLB variants */
303#define TLB_NONE 0
304#define TLB_6XX 1
305#define TLB_EMB 2
306#define TLB_MAS 3
3c7b48b7 307#endif
3fc6c082 308
c227f099
AL		 309typedef struct ppc_slb_t ppc_slb_t;
310struct ppc_slb_t {
81762d6d
DG		 311 uint64_t esid;
312 uint64_t vsid;
cd6a9bb6 313 const struct ppc_one_seg_page_size *sps;
8eee0af9
BS		 314};
315
d83af167 316#define MAX_SLB_ENTRIES 64
81762d6d
DG		 317#define SEGMENT_SHIFT_256M 28
318#define SEGMENT_MASK_256M (~((1ULL << SEGMENT_SHIFT_256M) - 1))
319
cdaee006
DG		 320#define SEGMENT_SHIFT_1T 40
321#define SEGMENT_MASK_1T (~((1ULL << SEGMENT_SHIFT_1T) - 1))
322
323
3fc6c082
FB		 324/*****************************************************************************/
325/* Machine state register bits definition */
76a66253 326#define MSR_SF 63 /* Sixty-four-bit mode hflags */
bd928eba 327#define MSR_TAG 62 /* Tag-active mode (POWERx ?) */
3fc6c082 328#define MSR_ISF 61 /* Sixty-four-bit interrupt mode on 630 */
a4f30719 329#define MSR_SHV 60 /* hypervisor state hflags */
cdcdda27
AK		 330#define MSR_TS0 34 /* Transactional state, 2 bits (Book3s) */
331#define MSR_TS1 33
332#define MSR_TM 32 /* Transactional Memory Available (Book3s) */
363be49c
JM		 333#define MSR_CM 31 /* Computation mode for BookE hflags */
334#define MSR_ICM 30 /* Interrupt computation mode for BookE */
a4f30719 335#define MSR_THV 29 /* hypervisor state for 32 bits PowerPC hflags */
71afeb61 336#define MSR_GS 28 /* guest state for BookE */
363be49c 337#define MSR_UCLE 26 /* User-mode cache lock enable for BookE */
d26bfc9a
JM		 338#define MSR_VR 25 /* altivec available x hflags */
339#define MSR_SPE 25 /* SPE enable for BookE x hflags */
76a66253 340#define MSR_AP 23 /* Access privilege state on 602 hflags */
1f29871c 341#define MSR_VSX 23 /* Vector Scalar Extension (ISA 2.06 and later) x hflags */
76a66253 342#define MSR_SA 22 /* Supervisor access mode on 602 hflags */
3fc6c082 343#define MSR_KEY 19 /* key bit on 603e */
25ba3a68 344#define MSR_POW 18 /* Power management */
d26bfc9a
JM		 345#define MSR_TGPR 17 /* TGPR usage on 602/603 x */
346#define MSR_CE 17 /* Critical interrupt enable on embedded PowerPC x */
3fc6c082
FB		 347#define MSR_ILE 16 /* Interrupt little-endian mode */
348#define MSR_EE 15 /* External interrupt enable */
76a66253
JM		 349#define MSR_PR 14 /* Problem state hflags */
350#define MSR_FP 13 /* Floating point available hflags */
3fc6c082 351#define MSR_ME 12 /* Machine check interrupt enable */
76a66253 352#define MSR_FE0 11 /* Floating point exception mode 0 hflags */
d26bfc9a
JM		 353#define MSR_SE 10 /* Single-step trace enable x hflags */
354#define MSR_DWE 10 /* Debug wait enable on 405 x */
355#define MSR_UBLE 10 /* User BTB lock enable on e500 x */
356#define MSR_BE 9 /* Branch trace enable x hflags */
357#define MSR_DE 9 /* Debug interrupts enable on embedded PowerPC x */
76a66253 358#define MSR_FE1 8 /* Floating point exception mode 1 hflags */
3fc6c082 359#define MSR_AL 7 /* AL bit on POWER */
0411a972 360#define MSR_EP 6 /* Exception prefix on 601 */
3fc6c082 361#define MSR_IR 5 /* Instruction relocate */
3fc6c082 362#define MSR_DR 4 /* Data relocate */
9fb04491
BH		 363#define MSR_IS 5 /* Instruction address space (BookE) */
364#define MSR_DS 4 /* Data address space (BookE) */
25ba3a68 365#define MSR_PE 3 /* Protection enable on 403 */
d26bfc9a
JM		 366#define MSR_PX 2 /* Protection exclusive on 403 x */
367#define MSR_PMM 2 /* Performance monitor mark on POWER x */
368#define MSR_RI 1 /* Recoverable interrupt 1 */
369#define MSR_LE 0 /* Little-endian mode 1 hflags */
0411a972 370
1488270e
BH		 371/* LPCR bits */
372#define LPCR_VPM0 (1ull << (63 - 0))
373#define LPCR_VPM1 (1ull << (63 - 1))
374#define LPCR_ISL (1ull << (63 - 2))
375#define LPCR_KBV (1ull << (63 - 3))
88536935 376#define LPCR_DPFD_SHIFT (63 - 11)
7659ca1a 377#define LPCR_DPFD (0x7ull << LPCR_DPFD_SHIFT)
88536935
BH		 378#define LPCR_VRMASD_SHIFT (63 - 16)
379#define LPCR_VRMASD (0x1full << LPCR_VRMASD_SHIFT)
18aa49ec
SJS		 380/* P9: Power-saving mode Exit Cause Enable (Upper Section) Mask */
381#define LPCR_PECE_U_SHIFT (63 - 19)
382#define LPCR_PECE_U_MASK (0x7ull << LPCR_PECE_U_SHIFT)
383#define LPCR_HVEE (1ull << (63 - 17)) /* Hypervisor Virt Exit Enable */
88536935
BH		 384#define LPCR_RMLS_SHIFT (63 - 37)
385#define LPCR_RMLS (0xfull << LPCR_RMLS_SHIFT)
1488270e 386#define LPCR_ILE (1ull << (63 - 38))
1488270e
BH		 387#define LPCR_AIL_SHIFT (63 - 40) /* Alternate interrupt location */
388#define LPCR_AIL (3ull << LPCR_AIL_SHIFT)
18aa49ec
SJS		 389#define LPCR_UPRT (1ull << (63 - 41)) /* Use Process Table */
390#define LPCR_EVIRT (1ull << (63 - 42)) /* Enhanced Virtualisation */
88536935 391#define LPCR_ONL (1ull << (63 - 45))
18aa49ec 392#define LPCR_LD (1ull << (63 - 46)) /* Large Decrementer */
7778a575
BH		 393#define LPCR_P7_PECE0 (1ull << (63 - 49))
394#define LPCR_P7_PECE1 (1ull << (63 - 50))
395#define LPCR_P7_PECE2 (1ull << (63 - 51))
396#define LPCR_P8_PECE0 (1ull << (63 - 47))
397#define LPCR_P8_PECE1 (1ull << (63 - 48))
398#define LPCR_P8_PECE2 (1ull << (63 - 49))
399#define LPCR_P8_PECE3 (1ull << (63 - 50))
400#define LPCR_P8_PECE4 (1ull << (63 - 51))
18aa49ec
SJS		 401/* P9: Power-saving mode Exit Cause Enable (Lower Section) Mask */
402#define LPCR_PECE_L_SHIFT (63 - 51)
403#define LPCR_PECE_L_MASK (0x1full << LPCR_PECE_L_SHIFT)
404#define LPCR_PDEE (1ull << (63 - 47)) /* Privileged Doorbell Exit EN */
405#define LPCR_HDEE (1ull << (63 - 48)) /* Hyperv Doorbell Exit Enable */
406#define LPCR_EEE (1ull << (63 - 49)) /* External Exit Enable */
407#define LPCR_DEE (1ull << (63 - 50)) /* Decrementer Exit Enable */
408#define LPCR_OEE (1ull << (63 - 51)) /* Other Exit Enable */
88536935 409#define LPCR_MER (1ull << (63 - 52))
18aa49ec 410#define LPCR_GTSE (1ull << (63 - 53)) /* Guest Translation Shootdown */
88536935 411#define LPCR_TC (1ull << (63 - 54))
18aa49ec 412#define LPCR_HEIC (1ull << (63 - 59)) /* HV Extern Interrupt Control */
88536935
BH		 413#define LPCR_LPES0 (1ull << (63 - 60))
414#define LPCR_LPES1 (1ull << (63 - 61))
415#define LPCR_RMI (1ull << (63 - 62))
18aa49ec 416#define LPCR_HVICE (1ull << (63 - 62)) /* HV Virtualisation Int Enable */
88536935 417#define LPCR_HDICE (1ull << (63 - 63))
1e0c7e55 418
0411a972
JM		 419#define msr_sf ((env->msr >> MSR_SF) & 1)
420#define msr_isf ((env->msr >> MSR_ISF) & 1)
a4f30719 421#define msr_shv ((env->msr >> MSR_SHV) & 1)
0411a972
JM		 422#define msr_cm ((env->msr >> MSR_CM) & 1)
423#define msr_icm ((env->msr >> MSR_ICM) & 1)
a4f30719 424#define msr_thv ((env->msr >> MSR_THV) & 1)
71afeb61 425#define msr_gs ((env->msr >> MSR_GS) & 1)
0411a972
JM		 426#define msr_ucle ((env->msr >> MSR_UCLE) & 1)
427#define msr_vr ((env->msr >> MSR_VR) & 1)
f9320410 428#define msr_spe ((env->msr >> MSR_SPE) & 1)
0411a972 429#define msr_ap ((env->msr >> MSR_AP) & 1)
1f29871c 430#define msr_vsx ((env->msr >> MSR_VSX) & 1)
0411a972
JM		 431#define msr_sa ((env->msr >> MSR_SA) & 1)
432#define msr_key ((env->msr >> MSR_KEY) & 1)
433#define msr_pow ((env->msr >> MSR_POW) & 1)
434#define msr_tgpr ((env->msr >> MSR_TGPR) & 1)
435#define msr_ce ((env->msr >> MSR_CE) & 1)
436#define msr_ile ((env->msr >> MSR_ILE) & 1)
437#define msr_ee ((env->msr >> MSR_EE) & 1)
438#define msr_pr ((env->msr >> MSR_PR) & 1)
439#define msr_fp ((env->msr >> MSR_FP) & 1)
440#define msr_me ((env->msr >> MSR_ME) & 1)
441#define msr_fe0 ((env->msr >> MSR_FE0) & 1)
442#define msr_se ((env->msr >> MSR_SE) & 1)
443#define msr_dwe ((env->msr >> MSR_DWE) & 1)
444#define msr_uble ((env->msr >> MSR_UBLE) & 1)
445#define msr_be ((env->msr >> MSR_BE) & 1)
446#define msr_de ((env->msr >> MSR_DE) & 1)
447#define msr_fe1 ((env->msr >> MSR_FE1) & 1)
448#define msr_al ((env->msr >> MSR_AL) & 1)
449#define msr_ep ((env->msr >> MSR_EP) & 1)
450#define msr_ir ((env->msr >> MSR_IR) & 1)
451#define msr_dr ((env->msr >> MSR_DR) & 1)
9fb04491
BH		 452#define msr_is ((env->msr >> MSR_IS) & 1)
453#define msr_ds ((env->msr >> MSR_DS) & 1)
0411a972
JM		 454#define msr_pe ((env->msr >> MSR_PE) & 1)
455#define msr_px ((env->msr >> MSR_PX) & 1)
456#define msr_pmm ((env->msr >> MSR_PMM) & 1)
457#define msr_ri ((env->msr >> MSR_RI) & 1)
458#define msr_le ((env->msr >> MSR_LE) & 1)
cdcdda27
AK		 459#define msr_ts ((env->msr >> MSR_TS1) & 3)
460#define msr_tm ((env->msr >> MSR_TM) & 1)
461
a4f30719
JM		 462/* Hypervisor bit is more specific */
463#if defined(TARGET_PPC64)
464#define MSR_HVB (1ULL << MSR_SHV)
465#define msr_hv msr_shv
466#else
467#if defined(PPC_EMULATE_32BITS_HYPV)
468#define MSR_HVB (1ULL << MSR_THV)
469#define msr_hv msr_thv
a4f30719
JM		 470#else
471#define MSR_HVB (0ULL)
472#define msr_hv (0)
473#endif
474#endif
79aceca5 475
7019cb3d
AK		 476/* Facility Status and Control (FSCR) bits */
477#define FSCR_EBB (63 - 56) /* Event-Based Branch Facility */
478#define FSCR_TAR (63 - 55) /* Target Address Register */
479/* Interrupt cause mask and position in FSCR. HFSCR has the same format */
480#define FSCR_IC_MASK (0xFFULL)
481#define FSCR_IC_POS (63 - 7)
482#define FSCR_IC_DSCR_SPR3 2
483#define FSCR_IC_PMU 3
484#define FSCR_IC_BHRB 4
485#define FSCR_IC_TM 5
486#define FSCR_IC_EBB 7
487#define FSCR_IC_TAR 8
488
a586e548 489/* Exception state register bits definition */
542df9bf
AG		 490#define ESR_PIL (1 << (63 - 36)) /* Illegal Instruction */
491#define ESR_PPR (1 << (63 - 37)) /* Privileged Instruction */
492#define ESR_PTR (1 << (63 - 38)) /* Trap */
493#define ESR_FP (1 << (63 - 39)) /* Floating-Point Operation */
494#define ESR_ST (1 << (63 - 40)) /* Store Operation */
495#define ESR_AP (1 << (63 - 44)) /* Auxiliary Processor Operation */
496#define ESR_PUO (1 << (63 - 45)) /* Unimplemented Operation */
497#define ESR_BO (1 << (63 - 46)) /* Byte Ordering */
498#define ESR_PIE (1 << (63 - 47)) /* Imprecise exception */
499#define ESR_DATA (1 << (63 - 53)) /* Data Access (Embedded page table) */
500#define ESR_TLBI (1 << (63 - 54)) /* TLB Ineligible (Embedded page table) */
501#define ESR_PT (1 << (63 - 55)) /* Page Table (Embedded page table) */
502#define ESR_SPV (1 << (63 - 56)) /* SPE/VMX operation */
503#define ESR_EPID (1 << (63 - 57)) /* External Process ID operation */
504#define ESR_VLEMI (1 << (63 - 58)) /* VLE operation */
505#define ESR_MIF (1 << (63 - 62)) /* Misaligned instruction (VLE) */
a586e548 506
aac86237
TM		 507/* Transaction EXception And Summary Register bits */
508#define TEXASR_FAILURE_PERSISTENT (63 - 7)
509#define TEXASR_DISALLOWED (63 - 8)
510#define TEXASR_NESTING_OVERFLOW (63 - 9)
511#define TEXASR_FOOTPRINT_OVERFLOW (63 - 10)
512#define TEXASR_SELF_INDUCED_CONFLICT (63 - 11)
513#define TEXASR_NON_TRANSACTIONAL_CONFLICT (63 - 12)
514#define TEXASR_TRANSACTION_CONFLICT (63 - 13)
515#define TEXASR_TRANSLATION_INVALIDATION_CONFLICT (63 - 14)
516#define TEXASR_IMPLEMENTATION_SPECIFIC (63 - 15)
517#define TEXASR_INSTRUCTION_FETCH_CONFLICT (63 - 16)
518#define TEXASR_ABORT (63 - 31)
519#define TEXASR_SUSPENDED (63 - 32)
520#define TEXASR_PRIVILEGE_HV (63 - 34)
521#define TEXASR_PRIVILEGE_PR (63 - 35)
522#define TEXASR_FAILURE_SUMMARY (63 - 36)
523#define TEXASR_TFIAR_EXACT (63 - 37)
524#define TEXASR_ROT (63 - 38)
525#define TEXASR_TRANSACTION_LEVEL (63 - 52) /* 12 bits */
526
d26bfc9a 527enum {
4018bae9 528 POWERPC_FLAG_NONE = 0x00000000,
d26bfc9a 529 /* Flag for MSR bit 25 signification (VRE/SPE) */
4018bae9
JM		 530 POWERPC_FLAG_SPE = 0x00000001,
531 POWERPC_FLAG_VRE = 0x00000002,
d26bfc9a 532 /* Flag for MSR bit 17 signification (TGPR/CE) */
4018bae9
JM		 533 POWERPC_FLAG_TGPR = 0x00000004,
534 POWERPC_FLAG_CE = 0x00000008,
d26bfc9a 535 /* Flag for MSR bit 10 signification (SE/DWE/UBLE) */
4018bae9
JM		 536 POWERPC_FLAG_SE = 0x00000010,
537 POWERPC_FLAG_DWE = 0x00000020,
538 POWERPC_FLAG_UBLE = 0x00000040,
d26bfc9a 539 /* Flag for MSR bit 9 signification (BE/DE) */
4018bae9
JM		 540 POWERPC_FLAG_BE = 0x00000080,
541 POWERPC_FLAG_DE = 0x00000100,
a4f30719 542 /* Flag for MSR bit 2 signification (PX/PMM) */
4018bae9
JM		 543 POWERPC_FLAG_PX = 0x00000200,
544 POWERPC_FLAG_PMM = 0x00000400,
545 /* Flag for special features */
546 /* Decrementer clock: RTC clock (POWER, 601) or bus clock */
547 POWERPC_FLAG_RTC_CLK = 0x00010000,
548 POWERPC_FLAG_BUS_CLK = 0x00020000,
697ab892
DG		 549 /* Has CFAR */
550 POWERPC_FLAG_CFAR = 0x00040000,
74f23997
TM		 551 /* Has VSX */
552 POWERPC_FLAG_VSX = 0x00080000,
e43668a7
TM		 553 /* Has Transaction Memory (ISA 2.07) */
554 POWERPC_FLAG_TM = 0x00100000,
d26bfc9a
JM		 555};
556
7c58044c
JM		 557/*****************************************************************************/
558/* Floating point status and control register */
559#define FPSCR_FX 31 /* Floating-point exception summary */
560#define FPSCR_FEX 30 /* Floating-point enabled exception summary */
561#define FPSCR_VX 29 /* Floating-point invalid operation exception summ. */
562#define FPSCR_OX 28 /* Floating-point overflow exception */
563#define FPSCR_UX 27 /* Floating-point underflow exception */
564#define FPSCR_ZX 26 /* Floating-point zero divide exception */
565#define FPSCR_XX 25 /* Floating-point inexact exception */
566#define FPSCR_VXSNAN 24 /* Floating-point invalid operation exception (sNan) */
567#define FPSCR_VXISI 23 /* Floating-point invalid operation exception (inf) */
568#define FPSCR_VXIDI 22 /* Floating-point invalid operation exception (inf) */
569#define FPSCR_VXZDZ 21 /* Floating-point invalid operation exception (zero) */
570#define FPSCR_VXIMZ 20 /* Floating-point invalid operation exception (inf) */
571#define FPSCR_VXVC 19 /* Floating-point invalid operation exception (comp) */
572#define FPSCR_FR 18 /* Floating-point fraction rounded */
573#define FPSCR_FI 17 /* Floating-point fraction inexact */
574#define FPSCR_C 16 /* Floating-point result class descriptor */
575#define FPSCR_FL 15 /* Floating-point less than or negative */
576#define FPSCR_FG 14 /* Floating-point greater than or negative */
577#define FPSCR_FE 13 /* Floating-point equal or zero */
578#define FPSCR_FU 12 /* Floating-point unordered or NaN */
579#define FPSCR_FPCC 12 /* Floating-point condition code */
580#define FPSCR_FPRF 12 /* Floating-point result flags */
581#define FPSCR_VXSOFT 10 /* Floating-point invalid operation exception (soft) */
582#define FPSCR_VXSQRT 9 /* Floating-point invalid operation exception (sqrt) */
583#define FPSCR_VXCVI 8 /* Floating-point invalid operation exception (int) */
584#define FPSCR_VE 7 /* Floating-point invalid operation exception enable */
585#define FPSCR_OE 6 /* Floating-point overflow exception enable */
586#define FPSCR_UE 5 /* Floating-point undeflow exception enable */
587#define FPSCR_ZE 4 /* Floating-point zero divide exception enable */
588#define FPSCR_XE 3 /* Floating-point inexact exception enable */
589#define FPSCR_NI 2 /* Floating-point non-IEEE mode */
590#define FPSCR_RN1 1
591#define FPSCR_RN 0 /* Floating-point rounding control */
592#define fpscr_fex (((env->fpscr) >> FPSCR_FEX) & 0x1)
593#define fpscr_vx (((env->fpscr) >> FPSCR_VX) & 0x1)
594#define fpscr_ox (((env->fpscr) >> FPSCR_OX) & 0x1)
595#define fpscr_ux (((env->fpscr) >> FPSCR_UX) & 0x1)
596#define fpscr_zx (((env->fpscr) >> FPSCR_ZX) & 0x1)
597#define fpscr_xx (((env->fpscr) >> FPSCR_XX) & 0x1)
598#define fpscr_vxsnan (((env->fpscr) >> FPSCR_VXSNAN) & 0x1)
599#define fpscr_vxisi (((env->fpscr) >> FPSCR_VXISI) & 0x1)
600#define fpscr_vxidi (((env->fpscr) >> FPSCR_VXIDI) & 0x1)
601#define fpscr_vxzdz (((env->fpscr) >> FPSCR_VXZDZ) & 0x1)
602#define fpscr_vximz (((env->fpscr) >> FPSCR_VXIMZ) & 0x1)
603#define fpscr_vxvc (((env->fpscr) >> FPSCR_VXVC) & 0x1)
604#define fpscr_fpcc (((env->fpscr) >> FPSCR_FPCC) & 0xF)
605#define fpscr_vxsoft (((env->fpscr) >> FPSCR_VXSOFT) & 0x1)
606#define fpscr_vxsqrt (((env->fpscr) >> FPSCR_VXSQRT) & 0x1)
607#define fpscr_vxcvi (((env->fpscr) >> FPSCR_VXCVI) & 0x1)
608#define fpscr_ve (((env->fpscr) >> FPSCR_VE) & 0x1)
609#define fpscr_oe (((env->fpscr) >> FPSCR_OE) & 0x1)
610#define fpscr_ue (((env->fpscr) >> FPSCR_UE) & 0x1)
611#define fpscr_ze (((env->fpscr) >> FPSCR_ZE) & 0x1)
612#define fpscr_xe (((env->fpscr) >> FPSCR_XE) & 0x1)
613#define fpscr_ni (((env->fpscr) >> FPSCR_NI) & 0x1)
614#define fpscr_rn (((env->fpscr) >> FPSCR_RN) & 0x3)
615/* Invalid operation exception summary */
616#define fpscr_ix ((env->fpscr) & ((1 << FPSCR_VXSNAN) | (1 << FPSCR_VXISI) | \
617 (1 << FPSCR_VXIDI) | (1 << FPSCR_VXZDZ) | \
618 (1 << FPSCR_VXIMZ) | (1 << FPSCR_VXVC) | \
619 (1 << FPSCR_VXSOFT) | (1 << FPSCR_VXSQRT) | \
620 (1 << FPSCR_VXCVI)))
621/* exception summary */
622#define fpscr_ex (((env->fpscr) >> FPSCR_XX) & 0x1F)
623/* enabled exception summary */
624#define fpscr_eex (((env->fpscr) >> FPSCR_XX) & ((env->fpscr) >> FPSCR_XE) & \
625 0x1F)
626
dbdc13a1
MS		 627#define FP_FX (1ull << FPSCR_FX)
628#define FP_FEX (1ull << FPSCR_FEX)
fc03cfef 629#define FP_VX (1ull << FPSCR_VX)
dbdc13a1 630#define FP_OX (1ull << FPSCR_OX)
dbdc13a1 631#define FP_UX (1ull << FPSCR_UX)
dbdc13a1 632#define FP_ZX (1ull << FPSCR_ZX)
fc03cfef 633#define FP_XX (1ull << FPSCR_XX)
dbdc13a1
MS		 634#define FP_VXSNAN (1ull << FPSCR_VXSNAN)
635#define FP_VXISI (1ull << FPSCR_VXISI)
dbdc13a1 636#define FP_VXIDI (1ull << FPSCR_VXIDI)
fc03cfef
JC		 637#define FP_VXZDZ (1ull << FPSCR_VXZDZ)
638#define FP_VXIMZ (1ull << FPSCR_VXIMZ)
dbdc13a1 639#define FP_VXVC (1ull << FPSCR_VXVC)
fc03cfef
JC		 640#define FP_FR (1ull << FSPCR_FR)
641#define FP_FI (1ull << FPSCR_FI)
642#define FP_C (1ull << FPSCR_C)
643#define FP_FL (1ull << FPSCR_FL)
644#define FP_FG (1ull << FPSCR_FG)
645#define FP_FE (1ull << FPSCR_FE)
646#define FP_FU (1ull << FPSCR_FU)
647#define FP_FPCC (FP_FL | FP_FG | FP_FE | FP_FU)
648#define FP_FPRF (FP_C | FP_FL | FP_FG | FP_FE | FP_FU)
649#define FP_VXSOFT (1ull << FPSCR_VXSOFT)
650#define FP_VXSQRT (1ull << FPSCR_VXSQRT)
dbdc13a1
MS		 651#define FP_VXCVI (1ull << FPSCR_VXCVI)
652#define FP_VE (1ull << FPSCR_VE)
fc03cfef
JC		 653#define FP_OE (1ull << FPSCR_OE)
654#define FP_UE (1ull << FPSCR_UE)
655#define FP_ZE (1ull << FPSCR_ZE)
656#define FP_XE (1ull << FPSCR_XE)
657#define FP_NI (1ull << FPSCR_NI)
658#define FP_RN1 (1ull << FPSCR_RN1)
659#define FP_RN (1ull << FPSCR_RN)
dbdc13a1 660
d1277156
JC		 661/* the exception bits which can be cleared by mcrfs - includes FX */
662#define FP_EX_CLEAR_BITS (FP_FX | FP_OX | FP_UX | FP_ZX | \
663 FP_XX | FP_VXSNAN | FP_VXISI | FP_VXIDI | \
664 FP_VXZDZ | FP_VXIMZ | FP_VXVC | FP_VXSOFT | \
665 FP_VXSQRT | FP_VXCVI)
666
7c58044c 667/*****************************************************************************/
6fa724a3
AJ		 668/* Vector status and control register */
669#define VSCR_NJ 16 /* Vector non-java */
670#define VSCR_SAT 0 /* Vector saturation */
671#define vscr_nj (((env->vscr) >> VSCR_NJ) & 0x1)
672#define vscr_sat (((env->vscr) >> VSCR_SAT) & 0x1)
673
01662f3e
AG		 674/*****************************************************************************/
675/* BookE e500 MMU registers */
676
677#define MAS0_NV_SHIFT 0
678#define MAS0_NV_MASK (0xfff << MAS0_NV_SHIFT)
679
680#define MAS0_WQ_SHIFT 12
681#define MAS0_WQ_MASK (3 << MAS0_WQ_SHIFT)
682/* Write TLB entry regardless of reservation */
683#define MAS0_WQ_ALWAYS (0 << MAS0_WQ_SHIFT)
684/* Write TLB entry only already in use */
685#define MAS0_WQ_COND (1 << MAS0_WQ_SHIFT)
686/* Clear TLB entry */
687#define MAS0_WQ_CLR_RSRV (2 << MAS0_WQ_SHIFT)
688
689#define MAS0_HES_SHIFT 14
690#define MAS0_HES (1 << MAS0_HES_SHIFT)
691
692#define MAS0_ESEL_SHIFT 16
693#define MAS0_ESEL_MASK (0xfff << MAS0_ESEL_SHIFT)
694
695#define MAS0_TLBSEL_SHIFT 28
696#define MAS0_TLBSEL_MASK (3 << MAS0_TLBSEL_SHIFT)
697#define MAS0_TLBSEL_TLB0 (0 << MAS0_TLBSEL_SHIFT)
698#define MAS0_TLBSEL_TLB1 (1 << MAS0_TLBSEL_SHIFT)
699#define MAS0_TLBSEL_TLB2 (2 << MAS0_TLBSEL_SHIFT)
700#define MAS0_TLBSEL_TLB3 (3 << MAS0_TLBSEL_SHIFT)
701
702#define MAS0_ATSEL_SHIFT 31
703#define MAS0_ATSEL (1 << MAS0_ATSEL_SHIFT)
704#define MAS0_ATSEL_TLB 0
705#define MAS0_ATSEL_LRAT MAS0_ATSEL
706
2bd9543c
SW		 707#define MAS1_TSIZE_SHIFT 7
708#define MAS1_TSIZE_MASK (0x1f << MAS1_TSIZE_SHIFT)
01662f3e
AG		 709
710#define MAS1_TS_SHIFT 12
711#define MAS1_TS (1 << MAS1_TS_SHIFT)
712
713#define MAS1_IND_SHIFT 13
714#define MAS1_IND (1 << MAS1_IND_SHIFT)
715
716#define MAS1_TID_SHIFT 16
717#define MAS1_TID_MASK (0x3fff << MAS1_TID_SHIFT)
718
719#define MAS1_IPROT_SHIFT 30
720#define MAS1_IPROT (1 << MAS1_IPROT_SHIFT)
721
722#define MAS1_VALID_SHIFT 31
723#define MAS1_VALID 0x80000000
724
725#define MAS2_EPN_SHIFT 12
96091698 726#define MAS2_EPN_MASK (~0ULL << MAS2_EPN_SHIFT)
01662f3e
AG		 727
728#define MAS2_ACM_SHIFT 6
729#define MAS2_ACM (1 << MAS2_ACM_SHIFT)
730
731#define MAS2_VLE_SHIFT 5
732#define MAS2_VLE (1 << MAS2_VLE_SHIFT)
733
734#define MAS2_W_SHIFT 4
735#define MAS2_W (1 << MAS2_W_SHIFT)
736
737#define MAS2_I_SHIFT 3
738#define MAS2_I (1 << MAS2_I_SHIFT)
739
740#define MAS2_M_SHIFT 2
741#define MAS2_M (1 << MAS2_M_SHIFT)
742
743#define MAS2_G_SHIFT 1
744#define MAS2_G (1 << MAS2_G_SHIFT)
745
746#define MAS2_E_SHIFT 0
747#define MAS2_E (1 << MAS2_E_SHIFT)
748
749#define MAS3_RPN_SHIFT 12
750#define MAS3_RPN_MASK (0xfffff << MAS3_RPN_SHIFT)
751
752#define MAS3_U0 0x00000200
753#define MAS3_U1 0x00000100
754#define MAS3_U2 0x00000080
755#define MAS3_U3 0x00000040
756#define MAS3_UX 0x00000020
757#define MAS3_SX 0x00000010
758#define MAS3_UW 0x00000008
759#define MAS3_SW 0x00000004
760#define MAS3_UR 0x00000002
761#define MAS3_SR 0x00000001
762#define MAS3_SPSIZE_SHIFT 1
763#define MAS3_SPSIZE_MASK (0x3e << MAS3_SPSIZE_SHIFT)
764
765#define MAS4_TLBSELD_SHIFT MAS0_TLBSEL_SHIFT
766#define MAS4_TLBSELD_MASK MAS0_TLBSEL_MASK
767#define MAS4_TIDSELD_MASK 0x00030000
768#define MAS4_TIDSELD_PID0 0x00000000
769#define MAS4_TIDSELD_PID1 0x00010000
770#define MAS4_TIDSELD_PID2 0x00020000
771#define MAS4_TIDSELD_PIDZ 0x00030000
772#define MAS4_INDD 0x00008000 /* Default IND */
773#define MAS4_TSIZED_SHIFT MAS1_TSIZE_SHIFT
774#define MAS4_TSIZED_MASK MAS1_TSIZE_MASK
775#define MAS4_ACMD 0x00000040
776#define MAS4_VLED 0x00000020
777#define MAS4_WD 0x00000010
778#define MAS4_ID 0x00000008
779#define MAS4_MD 0x00000004
780#define MAS4_GD 0x00000002
781#define MAS4_ED 0x00000001
782#define MAS4_WIMGED_MASK 0x0000001f /* Default WIMGE */
783#define MAS4_WIMGED_SHIFT 0
784
785#define MAS5_SGS 0x80000000
786#define MAS5_SLPID_MASK 0x00000fff
787
788#define MAS6_SPID0 0x3fff0000
789#define MAS6_SPID1 0x00007ffe
790#define MAS6_ISIZE(x) MAS1_TSIZE(x)
791#define MAS6_SAS 0x00000001
792#define MAS6_SPID MAS6_SPID0
793#define MAS6_SIND 0x00000002 /* Indirect page */
794#define MAS6_SIND_SHIFT 1
795#define MAS6_SPID_MASK 0x3fff0000
796#define MAS6_SPID_SHIFT 16
797#define MAS6_ISIZE_MASK 0x00000f80
798#define MAS6_ISIZE_SHIFT 7
799
800#define MAS7_RPN 0xffffffff
801
802#define MAS8_TGS 0x80000000
803#define MAS8_VF 0x40000000
804#define MAS8_TLBPID 0x00000fff
805
806/* Bit definitions for MMUCFG */
807#define MMUCFG_MAVN 0x00000003 /* MMU Architecture Version Number */
808#define MMUCFG_MAVN_V1 0x00000000 /* v1.0 */
809#define MMUCFG_MAVN_V2 0x00000001 /* v2.0 */
810#define MMUCFG_NTLBS 0x0000000c /* Number of TLBs */
811#define MMUCFG_PIDSIZE 0x000007c0 /* PID Reg Size */
812#define MMUCFG_TWC 0x00008000 /* TLB Write Conditional (v2.0) */
813#define MMUCFG_LRAT 0x00010000 /* LRAT Supported (v2.0) */
814#define MMUCFG_RASIZE 0x00fe0000 /* Real Addr Size */
815#define MMUCFG_LPIDSIZE 0x0f000000 /* LPID Reg Size */
816
817/* Bit definitions for MMUCSR0 */
818#define MMUCSR0_TLB1FI 0x00000002 /* TLB1 Flash invalidate */
819#define MMUCSR0_TLB0FI 0x00000004 /* TLB0 Flash invalidate */
820#define MMUCSR0_TLB2FI 0x00000040 /* TLB2 Flash invalidate */
821#define MMUCSR0_TLB3FI 0x00000020 /* TLB3 Flash invalidate */
822#define MMUCSR0_TLBFI (MMUCSR0_TLB0FI | MMUCSR0_TLB1FI | \
823 MMUCSR0_TLB2FI | MMUCSR0_TLB3FI)
824#define MMUCSR0_TLB0PS 0x00000780 /* TLB0 Page Size */
825#define MMUCSR0_TLB1PS 0x00007800 /* TLB1 Page Size */
826#define MMUCSR0_TLB2PS 0x00078000 /* TLB2 Page Size */
827#define MMUCSR0_TLB3PS 0x00780000 /* TLB3 Page Size */
828
829/* TLBnCFG encoding */
830#define TLBnCFG_N_ENTRY 0x00000fff /* number of entries */
831#define TLBnCFG_HES 0x00002000 /* HW select supported */
832#define TLBnCFG_AVAIL 0x00004000 /* variable page size */
833#define TLBnCFG_IPROT 0x00008000 /* IPROT supported */
834#define TLBnCFG_GTWE 0x00010000 /* Guest can write */
835#define TLBnCFG_IND 0x00020000 /* IND entries supported */
836#define TLBnCFG_PT 0x00040000 /* Can load from page table */
837#define TLBnCFG_MINSIZE 0x00f00000 /* Minimum Page Size (v1.0) */
838#define TLBnCFG_MINSIZE_SHIFT 20
839#define TLBnCFG_MAXSIZE 0x000f0000 /* Maximum Page Size (v1.0) */
840#define TLBnCFG_MAXSIZE_SHIFT 16
841#define TLBnCFG_ASSOC 0xff000000 /* Associativity */
842#define TLBnCFG_ASSOC_SHIFT 24
843
844/* TLBnPS encoding */
845#define TLBnPS_4K 0x00000004
846#define TLBnPS_8K 0x00000008
847#define TLBnPS_16K 0x00000010
848#define TLBnPS_32K 0x00000020
849#define TLBnPS_64K 0x00000040
850#define TLBnPS_128K 0x00000080
851#define TLBnPS_256K 0x00000100
852#define TLBnPS_512K 0x00000200
853#define TLBnPS_1M 0x00000400
854#define TLBnPS_2M 0x00000800
855#define TLBnPS_4M 0x00001000
856#define TLBnPS_8M 0x00002000
857#define TLBnPS_16M 0x00004000
858#define TLBnPS_32M 0x00008000
859#define TLBnPS_64M 0x00010000
860#define TLBnPS_128M 0x00020000
861#define TLBnPS_256M 0x00040000
862#define TLBnPS_512M 0x00080000
863#define TLBnPS_1G 0x00100000
864#define TLBnPS_2G 0x00200000
865#define TLBnPS_4G 0x00400000
866#define TLBnPS_8G 0x00800000
867#define TLBnPS_16G 0x01000000
868#define TLBnPS_32G 0x02000000
869#define TLBnPS_64G 0x04000000
870#define TLBnPS_128G 0x08000000
871#define TLBnPS_256G 0x10000000
872
873/* tlbilx action encoding */
874#define TLBILX_T_ALL 0
875#define TLBILX_T_TID 1
876#define TLBILX_T_FULLMATCH 3
877#define TLBILX_T_CLASS0 4
878#define TLBILX_T_CLASS1 5
879#define TLBILX_T_CLASS2 6
880#define TLBILX_T_CLASS3 7
881
882/* BookE 2.06 helper defines */
883
884#define BOOKE206_FLUSH_TLB0 (1 << 0)
885#define BOOKE206_FLUSH_TLB1 (1 << 1)
886#define BOOKE206_FLUSH_TLB2 (1 << 2)
887#define BOOKE206_FLUSH_TLB3 (1 << 3)
888
889/* number of possible TLBs */
890#define BOOKE206_MAX_TLBN 4
891
58e00a24
AG		 892/*****************************************************************************/
893/* Embedded.Processor Control */
894
895#define DBELL_TYPE_SHIFT 27
896#define DBELL_TYPE_MASK (0x1f << DBELL_TYPE_SHIFT)
897#define DBELL_TYPE_DBELL (0x00 << DBELL_TYPE_SHIFT)
898#define DBELL_TYPE_DBELL_CRIT (0x01 << DBELL_TYPE_SHIFT)
899#define DBELL_TYPE_G_DBELL (0x02 << DBELL_TYPE_SHIFT)
900#define DBELL_TYPE_G_DBELL_CRIT (0x03 << DBELL_TYPE_SHIFT)
901#define DBELL_TYPE_G_DBELL_MC (0x04 << DBELL_TYPE_SHIFT)
902
903#define DBELL_BRDCAST (1 << 26)
904#define DBELL_LPIDTAG_SHIFT 14
905#define DBELL_LPIDTAG_MASK (0xfff << DBELL_LPIDTAG_SHIFT)
906#define DBELL_PIRTAG_MASK 0x3fff
907
4656e1f0
BH		 908/*****************************************************************************/
909/* Segment page size information, used by recent hash MMUs
910 * The format of this structure mirrors kvm_ppc_smmu_info
911 */
912
913#define PPC_PAGE_SIZES_MAX_SZ 8
914
915struct ppc_one_page_size {
916 uint32_t page_shift; /* Page shift (or 0) */
917 uint32_t pte_enc; /* Encoding in the HPTE (>>12) */
918};
919
920struct ppc_one_seg_page_size {
921 uint32_t page_shift; /* Base page shift of segment (or 0) */
922 uint32_t slb_enc; /* SLB encoding for BookS */
923 struct ppc_one_page_size enc[PPC_PAGE_SIZES_MAX_SZ];
924};
925
926struct ppc_segment_page_sizes {
927 struct ppc_one_seg_page_size sps[PPC_PAGE_SIZES_MAX_SZ];
928};
929
930
6fa724a3 931/*****************************************************************************/
7c58044c 932/* The whole PowerPC CPU context */
9fb04491 933#define NB_MMU_MODES 8
6ebbf390 934
54ff58bb
BR		 935#define PPC_CPU_OPCODES_LEN 0x40
936#define PPC_CPU_INDIRECT_OPCODES_LEN 0x20
b048960f 937
3fc6c082
FB		 938struct CPUPPCState {
939 /* First are the most commonly used resources
940 * during translated code execution
941 */
79aceca5 942 /* general purpose registers */
bd7d9a6d 943 target_ulong gpr[32];
3cd7d1dd 944 /* Storage for GPR MSB, used by the SPE extension */
bd7d9a6d 945 target_ulong gprh[32];
3fc6c082
FB		 946 /* LR */
947 target_ulong lr;
948 /* CTR */
949 target_ulong ctr;
950 /* condition register */
47e4661c 951 uint32_t crf[8];
697ab892
DG		 952#if defined(TARGET_PPC64)
953 /* CFAR */
954 target_ulong cfar;
955#endif
da91a00f 956 /* XER (with SO, OV, CA split out) */
3d7b417e 957 target_ulong xer;
da91a00f
RH		 958 target_ulong so;
959 target_ulong ov;
960 target_ulong ca;
79aceca5 961 /* Reservation address */
18b21a2f
NF		 962 target_ulong reserve_addr;
963 /* Reservation value */
964 target_ulong reserve_val;
9c294d5a 965 target_ulong reserve_val2;
4425265b
NF		 966 /* Reservation store address */
967 target_ulong reserve_ea;
968 /* Reserved store source register and size */
969 target_ulong reserve_info;
3fc6c082
FB		 970
971 /* Those ones are used in supervisor mode only */
79aceca5 972 /* machine state register */
0411a972 973 target_ulong msr;
3fc6c082 974 /* temporary general purpose registers */
bd7d9a6d 975 target_ulong tgpr[4]; /* Used to speed-up TLB assist handlers */
3fc6c082
FB		 976
977 /* Floating point execution context */
4ecc3190 978 float_status fp_status;
3fc6c082
FB		 979 /* floating point registers */
980 float64 fpr[32];
981 /* floating point status and control register */
30304420 982 target_ulong fpscr;
4ecc3190 983
cb2dbfc3
AJ		 984 /* Next instruction pointer */
985 target_ulong nip;
a316d335 986
ac9eb073
FB		 987 int access_type; /* when a memory exception occurs, the access
988 type is stored here */
a541f297 989
cb2dbfc3
AJ		 990 CPU_COMMON
991
f2e63a42
JM		 992 /* MMU context - only relevant for full system emulation */
993#if !defined(CONFIG_USER_ONLY)
994#if defined(TARGET_PPC64)
f2e63a42 995 /* PowerPC 64 SLB area */
d83af167 996 ppc_slb_t slb[MAX_SLB_ENTRIES];
a90db158 997 int32_t slb_nr;
cd0c6f47 998 /* tcg TLB needs flush (deferred slb inval instruction typically) */
f2e63a42 999#endif
3fc6c082 1000 /* segment registers */
74d37793 1001 target_ulong sr[32];
f43e3525
DG		 1002 /* externally stored hash table */
1003 uint8_t *external_htab;
3fc6c082 1004 /* BATs */
a90db158 1005 uint32_t nb_BATs;
3fc6c082
FB		 1006 target_ulong DBAT[2][8];
1007 target_ulong IBAT[2][8];
01662f3e 1008 /* PowerPC TLB registers (for 4xx, e500 and 60x software driven TLBs) */
a90db158 1009 int32_t nb_tlb; /* Total number of TLB */
f2e63a42
JM		 1010 int tlb_per_way; /* Speed-up helper: used to avoid divisions at run time */
1011 int nb_ways; /* Number of ways in the TLB set */
1012 int last_way; /* Last used way used to allocate TLB in a LRU way */
1013 int id_tlbs; /* If 1, MMU has separated TLBs for instructions & data */
1014 int nb_pids; /* Number of available PID registers */
1c53accc
AG		 1015 int tlb_type; /* Type of TLB we're dealing with */
1016 ppc_tlb_t tlb; /* TLB is optional. Allocate them only if needed */
f2e63a42
JM		 1017 /* 403 dedicated access protection registers */
1018 target_ulong pb[4];
93dd5e85
SW		 1019 bool tlb_dirty; /* Set to non-zero when modifying TLB */
1020 bool kvm_sw_tlb; /* non-zero if KVM SW TLB API is active */
c5a8d8f3 1021 uint32_t tlb_need_flush; /* Delayed flush needed */
a8a6d53e 1022#define TLB_NEED_LOCAL_FLUSH 0x1
d76ab5e1 1023#define TLB_NEED_GLOBAL_FLUSH 0x2
f2e63a42 1024#endif
9fddaa0c 1025
3fc6c082
FB		 1026 /* Other registers */
1027 /* Special purpose registers */
1028 target_ulong spr[1024];
c227f099 1029 ppc_spr_t spr_cb[1024];
3fc6c082 1030 /* Altivec registers */
c227f099 1031 ppc_avr_t avr[32];
3fc6c082 1032 uint32_t vscr;
30304420
DG		 1033 /* VSX registers */
1034 uint64_t vsr[32];
d9bce9d9 1035 /* SPE registers */
2231ef10 1036 uint64_t spe_acc;
d9bce9d9 1037 uint32_t spe_fscr;
fbd265b6
AJ		 1038 /* SPE and Altivec can share a status since they will never be used
1039 * simultaneously */
1040 float_status vec_status;
3fc6c082
FB		 1041
1042 /* Internal devices resources */
9fddaa0c 1043 /* Time base and decrementer */
c227f099 1044 ppc_tb_t *tb_env;
3fc6c082 1045 /* Device control registers */
c227f099 1046 ppc_dcr_t *dcr_env;
3fc6c082 1047
d63001d1
JM		 1048 int dcache_line_size;
1049 int icache_line_size;
1050
3fc6c082
FB		 1051 /* Those resources are used during exception processing */
1052 /* CPU model definition */
a750fc0b 1053 target_ulong msr_mask;
c227f099
AL		 1054 powerpc_mmu_t mmu_model;
1055 powerpc_excp_t excp_model;
1056 powerpc_input_t bus_model;
237c0af0 1057 int bfd_mach;
3fc6c082 1058 uint32_t flags;
c29b735c 1059 uint64_t insns_flags;
a5858d7a 1060 uint64_t insns_flags2;
4656e1f0
BH		 1061#if defined(TARGET_PPC64)
1062 struct ppc_segment_page_sizes sps;
912acdf4
BH		 1063 ppc_slb_t vrma_slb;
1064 target_ulong rmls;
90da0d5a 1065 bool ci_large_pages;
4656e1f0 1066#endif
3fc6c082 1067
ed120055 1068#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
ac7d12ba
DG		 1069 uint64_t vpa_addr;
1070 uint64_t slb_shadow_addr, slb_shadow_size;
1071 uint64_t dtl_addr, dtl_size;
ed120055
DG		 1072#endif /* TARGET_PPC64 */
1073
3fc6c082 1074 int error_code;
47103572 1075 uint32_t pending_interrupts;
e9df014c 1076#if !defined(CONFIG_USER_ONLY)
4abf79a4 1077 /* This is the IRQ controller, which is implementation dependent
e9df014c
JM		 1078 * and only relevant when emulating a complete machine.
1079 */
1080 uint32_t irq_input_state;
1081 void **irq_inputs;
e1833e1f
JM		 1082 /* Exception vectors */
1083 target_ulong excp_vectors[POWERPC_EXCP_NB];
1084 target_ulong excp_prefix;
1085 target_ulong ivor_mask;
1086 target_ulong ivpr_mask;
d63001d1 1087 target_ulong hreset_vector;
68c2dd70
AG		 1088 hwaddr mpic_iack;
1089 /* true when the external proxy facility mode is enabled */
1090 bool mpic_proxy;
932ccbdd
BH		 1091 /* set when the processor has an HV mode, thus HV priv
1092 * instructions and SPRs are diallowed if MSR:HV is 0
1093 */
1094 bool has_hv_mode;
7778a575
BH		 1095 /* On P7/P8, set when in PM state, we need to handle resume
1096 * in a special way (such as routing some resume causes to
1097 * 0x100), so flag this here.
1098 */
1099 bool in_pm_state;
e9df014c 1100#endif
3fc6c082
FB		 1101
1102 /* Those resources are used only during code translation */
3fc6c082 1103 /* opcode handlers */
b048960f 1104 opc_handler_t *opcodes[PPC_CPU_OPCODES_LEN];
3fc6c082 1105
5cbdb3a3 1106 /* Those resources are used only in QEMU core */
056401ea 1107 target_ulong hflags; /* hflags is a MSR & HFLAGS_MASK */
4abf79a4 1108 target_ulong hflags_nmsr; /* specific hflags, not coming from MSR */
9fb04491
BH		 1109 int immu_idx; /* precomputed MMU index to speed up insn access */
1110 int dmmu_idx; /* precomputed MMU index to speed up data accesses */
3fc6c082 1111
9fddaa0c 1112 /* Power management */
cd346349 1113 int (*check_pow)(CPUPPCState *env);
a541f297 1114
2c50e26e
EI		 1115#if !defined(CONFIG_USER_ONLY)
1116 void *load_info; /* Holds boot loading state. */
1117#endif
ddd1055b
FC		 1118
1119 /* booke timers */
1120
1121 /* Specifies bit locations of the Time Base used to signal a fixed timer
1122 * exception on a transition from 0 to 1. (watchdog or fixed-interval timer)
1123 *
1124 * 0 selects the least significant bit.
1125 * 63 selects the most significant bit.
1126 */
1127 uint8_t fit_period[4];
1128 uint8_t wdt_period[4];
80b3f79b
AK		 1129
1130 /* Transactional memory state */
1131 target_ulong tm_gpr[32];
1132 ppc_avr_t tm_vsr[64];
1133 uint64_t tm_cr;
1134 uint64_t tm_lr;
1135 uint64_t tm_ctr;
1136 uint64_t tm_fpscr;
1137 uint64_t tm_amr;
1138 uint64_t tm_ppr;
1139 uint64_t tm_vrsave;
1140 uint32_t tm_vscr;
1141 uint64_t tm_dscr;
1142 uint64_t tm_tar;
3fc6c082 1143};
79aceca5 1144
ddd1055b
FC		 1145#define SET_FIT_PERIOD(a_, b_, c_, d_) \
1146do { \
1147 env->fit_period[0] = (a_); \
1148 env->fit_period[1] = (b_); \
1149 env->fit_period[2] = (c_); \
1150 env->fit_period[3] = (d_); \
1151 } while (0)
1152
1153#define SET_WDT_PERIOD(a_, b_, c_, d_) \
1154do { \
1155 env->wdt_period[0] = (a_); \
1156 env->wdt_period[1] = (b_); \
1157 env->wdt_period[2] = (c_); \
1158 env->wdt_period[3] = (d_); \
1159 } while (0)
1160
1d1be34d
DG		 1161typedef struct PPCVirtualHypervisor PPCVirtualHypervisor;
1162typedef struct PPCVirtualHypervisorClass PPCVirtualHypervisorClass;
1163
2d34fe39
PB		 1164/**
1165 * PowerPCCPU:
1166 * @env: #CPUPPCState
1167 * @cpu_dt_id: CPU index used in the device tree. KVM uses this index too
1168 * @max_compat: Maximal supported logical PVR from the command line
d6e166c0 1169 * @compat_pvr: Current logical PVR, zero if in "raw" mode
2d34fe39
PB		 1170 *
1171 * A PowerPC CPU.
1172 */
1173struct PowerPCCPU {
1174 /*< private >*/
1175 CPUState parent_obj;
1176 /*< public >*/
1177
1178 CPUPPCState env;
1179 int cpu_dt_id;
1180 uint32_t max_compat;
d6e166c0 1181 uint32_t compat_pvr;
1d1be34d 1182 PPCVirtualHypervisor *vhyp;
16a2497b 1183
146c11f1
DG		 1184 /* Fields related to migration compatibility hacks */
1185 bool pre_2_8_migration;
16a2497b
DG		 1186 target_ulong mig_msr_mask;
1187 uint64_t mig_insns_flags;
1188 uint64_t mig_insns_flags2;
1189 uint32_t mig_nb_BATs;
2d34fe39
PB		 1190};
1191
1192static inline PowerPCCPU *ppc_env_get_cpu(CPUPPCState *env)
1193{
1194 return container_of(env, PowerPCCPU, env);
1195}
1196
1197#define ENV_GET_CPU(e) CPU(ppc_env_get_cpu(e))
1198
1199#define ENV_OFFSET offsetof(PowerPCCPU, env)
1200
1201PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr);
1202PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr);
1203
1d1be34d
DG		 1204struct PPCVirtualHypervisor {
1205 Object parent;
1206};
1207
1208struct PPCVirtualHypervisorClass {
1209 InterfaceClass parent;
1210 void (*hypercall)(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu);
1211};
1212
1213#define TYPE_PPC_VIRTUAL_HYPERVISOR "ppc-virtual-hypervisor"
1214#define PPC_VIRTUAL_HYPERVISOR(obj) \
1215 OBJECT_CHECK(PPCVirtualHypervisor, (obj), TYPE_PPC_VIRTUAL_HYPERVISOR)
1216#define PPC_VIRTUAL_HYPERVISOR_CLASS(klass) \
1217 OBJECT_CLASS_CHECK(PPCVirtualHypervisorClass, (klass), \
1218 TYPE_PPC_VIRTUAL_HYPERVISOR)
1219#define PPC_VIRTUAL_HYPERVISOR_GET_CLASS(obj) \
1220 OBJECT_GET_CLASS(PPCVirtualHypervisorClass, (obj), \
1221 TYPE_PPC_VIRTUAL_HYPERVISOR)
1222
2d34fe39
PB		 1223void ppc_cpu_do_interrupt(CPUState *cpu);
1224bool ppc_cpu_exec_interrupt(CPUState *cpu, int int_req);
1225void ppc_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
1226 int flags);
1227void ppc_cpu_dump_statistics(CPUState *cpu, FILE *f,
1228 fprintf_function cpu_fprintf, int flags);
2d34fe39
PB		 1229hwaddr ppc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
1230int ppc_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
1231int ppc_cpu_gdb_read_register_apple(CPUState *cpu, uint8_t *buf, int reg);
1232int ppc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
1233int ppc_cpu_gdb_write_register_apple(CPUState *cpu, uint8_t *buf, int reg);
1234int ppc64_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
1235 int cpuid, void *opaque);
1236#ifndef CONFIG_USER_ONLY
1237void ppc_cpu_do_system_reset(CPUState *cs);
1238extern const struct VMStateDescription vmstate_ppc_cpu;
1239#endif
1d0cb67d 1240
3fc6c082 1241/*****************************************************************************/
397b457d 1242PowerPCCPU *cpu_ppc_init(const char *cpu_model);
2e70f6ef 1243void ppc_translate_init(void);
caf6316d 1244const char *ppc_cpu_lookup_alias(const char *alias);
79aceca5
FB		 1245/* you can call this signal handler from your SIGBUS and SIGSEGV
1246 signal handlers to inform the virtual CPU of exceptions. non zero
1247 is returned if the signal was handled by the virtual CPU. */
36081602
JM		 1248int cpu_ppc_signal_handler (int host_signum, void *pinfo,
1249 void *puc);
cc8eae8a 1250#if defined(CONFIG_USER_ONLY)
7510454e
AF		 1251int ppc_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
1252 int mmu_idx);
cc8eae8a 1253#endif
a541f297 1254
76a66253 1255#if !defined(CONFIG_USER_ONLY)
45d827d2 1256void ppc_store_sdr1 (CPUPPCState *env, target_ulong value);
12de9a39 1257#endif /* !defined(CONFIG_USER_ONLY) */
0411a972 1258void ppc_store_msr (CPUPPCState *env, target_ulong value);
3fc6c082 1259
9a78eead 1260void ppc_cpu_list (FILE *f, fprintf_function cpu_fprintf);
eac4fba9 1261#if defined(TARGET_PPC64)
eac4fba9 1262#endif
aaed909a 1263
9fddaa0c
FB		 1264/* Time-base and decrementer management */
1265#ifndef NO_CPU_IO_DEFS
e3ea6529 1266uint64_t cpu_ppc_load_tbl (CPUPPCState *env);
9fddaa0c
FB		 1267uint32_t cpu_ppc_load_tbu (CPUPPCState *env);
1268void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value);
1269void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value);
b711de95 1270uint64_t cpu_ppc_load_atbl (CPUPPCState *env);
a062e36c
JM		 1271uint32_t cpu_ppc_load_atbu (CPUPPCState *env);
1272void cpu_ppc_store_atbl (CPUPPCState *env, uint32_t value);
1273void cpu_ppc_store_atbu (CPUPPCState *env, uint32_t value);
e81a982a 1274bool ppc_decr_clear_on_delivery(CPUPPCState *env);
9fddaa0c
FB		 1275uint32_t cpu_ppc_load_decr (CPUPPCState *env);
1276void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value);
58a7d328
JM		 1277uint32_t cpu_ppc_load_hdecr (CPUPPCState *env);
1278void cpu_ppc_store_hdecr (CPUPPCState *env, uint32_t value);
1279uint64_t cpu_ppc_load_purr (CPUPPCState *env);
d9bce9d9
JM		 1280uint32_t cpu_ppc601_load_rtcl (CPUPPCState *env);
1281uint32_t cpu_ppc601_load_rtcu (CPUPPCState *env);
1282#if !defined(CONFIG_USER_ONLY)
1283void cpu_ppc601_store_rtcl (CPUPPCState *env, uint32_t value);
1284void cpu_ppc601_store_rtcu (CPUPPCState *env, uint32_t value);
1285target_ulong load_40x_pit (CPUPPCState *env);
1286void store_40x_pit (CPUPPCState *env, target_ulong val);
8ecc7913 1287void store_40x_dbcr0 (CPUPPCState *env, uint32_t val);
c294fc58 1288void store_40x_sler (CPUPPCState *env, uint32_t val);
d9bce9d9
JM		 1289void store_booke_tcr (CPUPPCState *env, target_ulong val);
1290void store_booke_tsr (CPUPPCState *env, target_ulong val);
0a032cbe 1291void ppc_tlb_invalidate_all (CPUPPCState *env);
daf4f96e 1292void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr);
b7b0b1f1 1293void cpu_ppc_set_papr(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp);
d9bce9d9 1294#endif
9fddaa0c 1295#endif
79aceca5 1296
d6478bc7
FC		 1297void store_fpscr(CPUPPCState *env, uint64_t arg, uint32_t mask);
1298
636aa200 1299static inline uint64_t ppc_dump_gpr(CPUPPCState *env, int gprn)
6b542af7
JM		 1300{
1301 uint64_t gprv;
1302
1303 gprv = env->gpr[gprn];
6b542af7
JM		 1304 if (env->flags & POWERPC_FLAG_SPE) {
1305 /* If the CPU implements the SPE extension, we have to get the
1306 * high bits of the GPR from the gprh storage area
1307 */
1308 gprv &= 0xFFFFFFFFULL;
1309 gprv |= (uint64_t)env->gprh[gprn] << 32;
1310 }
6b542af7
JM		 1311
1312 return gprv;
1313}
1314
2e719ba3 1315/* Device control registers */
73b01960
AG		 1316int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp);
1317int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val);
2e719ba3 1318
2994fd96 1319#define cpu_init(cpu_model) CPU(cpu_ppc_init(cpu_model))
397b457d 1320
9467d44c 1321#define cpu_signal_handler cpu_ppc_signal_handler
c732abe2 1322#define cpu_list ppc_cpu_list
9467d44c 1323
6ebbf390 1324/* MMU modes definitions */
6ebbf390 1325#define MMU_USER_IDX 0
97ed5ccd 1326static inline int cpu_mmu_index (CPUPPCState *env, bool ifetch)
6ebbf390 1327{
9fb04491 1328 return ifetch ? env->immu_idx : env->dmmu_idx;
6ebbf390
JM		 1329}
1330
9d6f1065
DG		 1331/* Compatibility modes */
1332#if defined(TARGET_PPC64)
9d2179d6
DG		 1333bool ppc_check_compat(PowerPCCPU *cpu, uint32_t compat_pvr,
1334 uint32_t min_compat_pvr, uint32_t max_compat_pvr);
9d6f1065 1335void ppc_set_compat(PowerPCCPU *cpu, uint32_t compat_pvr, Error **errp);
f6f242c7
DG		 1336#if !defined(CONFIG_USER_ONLY)
1337void ppc_set_compat_all(uint32_t compat_pvr, Error **errp);
1338#endif
12dbeb16 1339int ppc_compat_max_threads(PowerPCCPU *cpu);
9d6f1065
DG		 1340#endif /* defined(TARGET_PPC64) */
1341
022c62cb 1342#include "exec/cpu-all.h"
79aceca5 1343
3fc6c082 1344/*****************************************************************************/
e1571908 1345/* CRF definitions */
efa73196
ND		 1346#define CRF_LT_BIT 3
1347#define CRF_GT_BIT 2
1348#define CRF_EQ_BIT 1
1349#define CRF_SO_BIT 0
1350#define CRF_LT (1 << CRF_LT_BIT)
1351#define CRF_GT (1 << CRF_GT_BIT)
1352#define CRF_EQ (1 << CRF_EQ_BIT)
1353#define CRF_SO (1 << CRF_SO_BIT)
1354/* For SPE extensions */
1355#define CRF_CH (1 << CRF_LT_BIT)
1356#define CRF_CL (1 << CRF_GT_BIT)
1357#define CRF_CH_OR_CL (1 << CRF_EQ_BIT)
1358#define CRF_CH_AND_CL (1 << CRF_SO_BIT)
e1571908
AJ		 1359
1360/* XER definitions */
3d7b417e
AJ		 1361#define XER_SO 31
1362#define XER_OV 30
1363#define XER_CA 29
1364#define XER_CMP 8
1365#define XER_BC 0
da91a00f
RH		 1366#define xer_so (env->so)
1367#define xer_ov (env->ov)
1368#define xer_ca (env->ca)
3d7b417e
AJ		 1369#define xer_cmp ((env->xer >> XER_CMP) & 0xFF)
1370#define xer_bc ((env->xer >> XER_BC) & 0x7F)
79aceca5 1371
3fc6c082 1372/* SPR definitions */
80d11f44
JM		 1373#define SPR_MQ (0x000)
1374#define SPR_XER (0x001)
1375#define SPR_601_VRTCU (0x004)
1376#define SPR_601_VRTCL (0x005)
1377#define SPR_601_UDECR (0x006)
1378#define SPR_LR (0x008)
1379#define SPR_CTR (0x009)
f80872e2 1380#define SPR_UAMR (0x00C)
697ab892 1381#define SPR_DSCR (0x011)
80d11f44
JM		 1382#define SPR_DSISR (0x012)
1383#define SPR_DAR (0x013) /* DAE for PowerPC 601 */
1384#define SPR_601_RTCU (0x014)
1385#define SPR_601_RTCL (0x015)
1386#define SPR_DECR (0x016)
1387#define SPR_SDR1 (0x019)
1388#define SPR_SRR0 (0x01A)
1389#define SPR_SRR1 (0x01B)
697ab892 1390#define SPR_CFAR (0x01C)
80d11f44 1391#define SPR_AMR (0x01D)
9c1cf38d 1392#define SPR_ACOP (0x01F)
80d11f44 1393#define SPR_BOOKE_PID (0x030)
9c1cf38d 1394#define SPR_BOOKS_PID (0x030)
80d11f44
JM		 1395#define SPR_BOOKE_DECAR (0x036)
1396#define SPR_BOOKE_CSRR0 (0x03A)
1397#define SPR_BOOKE_CSRR1 (0x03B)
1398#define SPR_BOOKE_DEAR (0x03D)
a6eabb9e 1399#define SPR_IAMR (0x03D)
80d11f44
JM		 1400#define SPR_BOOKE_ESR (0x03E)
1401#define SPR_BOOKE_IVPR (0x03F)
1402#define SPR_MPC_EIE (0x050)
1403#define SPR_MPC_EID (0x051)
1404#define SPR_MPC_NRI (0x052)
cdcdda27
AK		 1405#define SPR_TFHAR (0x080)
1406#define SPR_TFIAR (0x081)
1407#define SPR_TEXASR (0x082)
1408#define SPR_TEXASRU (0x083)
0bfe9299 1409#define SPR_UCTRL (0x088)
80d11f44
JM		 1410#define SPR_MPC_CMPA (0x090)
1411#define SPR_MPC_CMPB (0x091)
1412#define SPR_MPC_CMPC (0x092)
1413#define SPR_MPC_CMPD (0x093)
1414#define SPR_MPC_ECR (0x094)
1415#define SPR_MPC_DER (0x095)
1416#define SPR_MPC_COUNTA (0x096)
1417#define SPR_MPC_COUNTB (0x097)
0bfe9299 1418#define SPR_CTRL (0x098)
80d11f44
JM		 1419#define SPR_MPC_CMPE (0x098)
1420#define SPR_MPC_CMPF (0x099)
7019cb3d 1421#define SPR_FSCR (0x099)
80d11f44
JM		 1422#define SPR_MPC_CMPG (0x09A)
1423#define SPR_MPC_CMPH (0x09B)
1424#define SPR_MPC_LCTRL1 (0x09C)
1425#define SPR_MPC_LCTRL2 (0x09D)
f80872e2 1426#define SPR_UAMOR (0x09D)
80d11f44
JM		 1427#define SPR_MPC_ICTRL (0x09E)
1428#define SPR_MPC_BAR (0x09F)
d6f1445f 1429#define SPR_PSPB (0x09F)
1488270e
BH		 1430#define SPR_DAWR (0x0B4)
1431#define SPR_RPR (0x0BA)
eb5ceb4d 1432#define SPR_CIABR (0x0BB)
1488270e
BH		 1433#define SPR_DAWRX (0x0BC)
1434#define SPR_HFSCR (0x0BE)
80d11f44
JM		 1435#define SPR_VRSAVE (0x100)
1436#define SPR_USPRG0 (0x100)
1437#define SPR_USPRG1 (0x101)
1438#define SPR_USPRG2 (0x102)
1439#define SPR_USPRG3 (0x103)
1440#define SPR_USPRG4 (0x104)
1441#define SPR_USPRG5 (0x105)
1442#define SPR_USPRG6 (0x106)
1443#define SPR_USPRG7 (0x107)
1444#define SPR_VTBL (0x10C)
1445#define SPR_VTBU (0x10D)
1446#define SPR_SPRG0 (0x110)
1447#define SPR_SPRG1 (0x111)
1448#define SPR_SPRG2 (0x112)
1449#define SPR_SPRG3 (0x113)
1450#define SPR_SPRG4 (0x114)
1451#define SPR_SCOMC (0x114)
1452#define SPR_SPRG5 (0x115)
1453#define SPR_SCOMD (0x115)
1454#define SPR_SPRG6 (0x116)
1455#define SPR_SPRG7 (0x117)
1456#define SPR_ASR (0x118)
1457#define SPR_EAR (0x11A)
1458#define SPR_TBL (0x11C)
1459#define SPR_TBU (0x11D)
1460#define SPR_TBU40 (0x11E)
1461#define SPR_SVR (0x11E)
1462#define SPR_BOOKE_PIR (0x11E)
1463#define SPR_PVR (0x11F)
1464#define SPR_HSPRG0 (0x130)
1465#define SPR_BOOKE_DBSR (0x130)
1466#define SPR_HSPRG1 (0x131)
1467#define SPR_HDSISR (0x132)
1468#define SPR_HDAR (0x133)
90dc8812 1469#define SPR_BOOKE_EPCR (0x133)
9d52e907 1470#define SPR_SPURR (0x134)
80d11f44
JM		 1471#define SPR_BOOKE_DBCR0 (0x134)
1472#define SPR_IBCR (0x135)
1473#define SPR_PURR (0x135)
1474#define SPR_BOOKE_DBCR1 (0x135)
1475#define SPR_DBCR (0x136)
1476#define SPR_HDEC (0x136)
1477#define SPR_BOOKE_DBCR2 (0x136)
1478#define SPR_HIOR (0x137)
1479#define SPR_MBAR (0x137)
1480#define SPR_RMOR (0x138)
1481#define SPR_BOOKE_IAC1 (0x138)
1482#define SPR_HRMOR (0x139)
1483#define SPR_BOOKE_IAC2 (0x139)
1484#define SPR_HSRR0 (0x13A)
1485#define SPR_BOOKE_IAC3 (0x13A)
1486#define SPR_HSRR1 (0x13B)
1487#define SPR_BOOKE_IAC4 (0x13B)
80d11f44 1488#define SPR_BOOKE_DAC1 (0x13C)
1488270e 1489#define SPR_MMCRH (0x13C)
80d11f44
JM		 1490#define SPR_DABR2 (0x13D)
1491#define SPR_BOOKE_DAC2 (0x13D)
1488270e 1492#define SPR_TFMR (0x13D)
80d11f44 1493#define SPR_BOOKE_DVC1 (0x13E)
6475c9f0 1494#define SPR_LPCR (0x13E)
80d11f44 1495#define SPR_BOOKE_DVC2 (0x13F)
1488270e 1496#define SPR_LPIDR (0x13F)
80d11f44 1497#define SPR_BOOKE_TSR (0x150)
1488270e
BH		 1498#define SPR_HMER (0x150)
1499#define SPR_HMEER (0x151)
6d9412ea 1500#define SPR_PCR (0x152)
1488270e 1501#define SPR_BOOKE_LPIDR (0x152)
80d11f44 1502#define SPR_BOOKE_TCR (0x154)
a1ef618a
AG		 1503#define SPR_BOOKE_TLB0PS (0x158)
1504#define SPR_BOOKE_TLB1PS (0x159)
1505#define SPR_BOOKE_TLB2PS (0x15A)
1506#define SPR_BOOKE_TLB3PS (0x15B)
1488270e 1507#define SPR_AMOR (0x15D)
84755ed5 1508#define SPR_BOOKE_MAS7_MAS3 (0x174)
80d11f44
JM		 1509#define SPR_BOOKE_IVOR0 (0x190)
1510#define SPR_BOOKE_IVOR1 (0x191)
1511#define SPR_BOOKE_IVOR2 (0x192)
1512#define SPR_BOOKE_IVOR3 (0x193)
1513#define SPR_BOOKE_IVOR4 (0x194)
1514#define SPR_BOOKE_IVOR5 (0x195)
1515#define SPR_BOOKE_IVOR6 (0x196)
1516#define SPR_BOOKE_IVOR7 (0x197)
1517#define SPR_BOOKE_IVOR8 (0x198)
1518#define SPR_BOOKE_IVOR9 (0x199)
1519#define SPR_BOOKE_IVOR10 (0x19A)
1520#define SPR_BOOKE_IVOR11 (0x19B)
1521#define SPR_BOOKE_IVOR12 (0x19C)
1522#define SPR_BOOKE_IVOR13 (0x19D)
1523#define SPR_BOOKE_IVOR14 (0x19E)
1524#define SPR_BOOKE_IVOR15 (0x19F)
e9205258
AG		 1525#define SPR_BOOKE_IVOR38 (0x1B0)
1526#define SPR_BOOKE_IVOR39 (0x1B1)
1527#define SPR_BOOKE_IVOR40 (0x1B2)
1528#define SPR_BOOKE_IVOR41 (0x1B3)
1529#define SPR_BOOKE_IVOR42 (0x1B4)
45eb5611
AG		 1530#define SPR_BOOKE_GIVOR2 (0x1B8)
1531#define SPR_BOOKE_GIVOR3 (0x1B9)
1532#define SPR_BOOKE_GIVOR4 (0x1BA)
1533#define SPR_BOOKE_GIVOR8 (0x1BB)
1534#define SPR_BOOKE_GIVOR13 (0x1BC)
1535#define SPR_BOOKE_GIVOR14 (0x1BD)
d1a721ab 1536#define SPR_TIR (0x1BE)
80d11f44
JM		 1537#define SPR_BOOKE_SPEFSCR (0x200)
1538#define SPR_Exxx_BBEAR (0x201)
1539#define SPR_Exxx_BBTAR (0x202)
1540#define SPR_Exxx_L1CFG0 (0x203)
d2ea2bf7 1541#define SPR_Exxx_L1CFG1 (0x204)
80d11f44
JM		 1542#define SPR_Exxx_NPIDR (0x205)
1543#define SPR_ATBL (0x20E)
1544#define SPR_ATBU (0x20F)
1545#define SPR_IBAT0U (0x210)
1546#define SPR_BOOKE_IVOR32 (0x210)
1547#define SPR_RCPU_MI_GRA (0x210)
1548#define SPR_IBAT0L (0x211)
1549#define SPR_BOOKE_IVOR33 (0x211)
1550#define SPR_IBAT1U (0x212)
1551#define SPR_BOOKE_IVOR34 (0x212)
1552#define SPR_IBAT1L (0x213)
1553#define SPR_BOOKE_IVOR35 (0x213)
1554#define SPR_IBAT2U (0x214)
1555#define SPR_BOOKE_IVOR36 (0x214)
1556#define SPR_IBAT2L (0x215)
1557#define SPR_BOOKE_IVOR37 (0x215)
1558#define SPR_IBAT3U (0x216)
1559#define SPR_IBAT3L (0x217)
1560#define SPR_DBAT0U (0x218)
1561#define SPR_RCPU_L2U_GRA (0x218)
1562#define SPR_DBAT0L (0x219)
1563#define SPR_DBAT1U (0x21A)
1564#define SPR_DBAT1L (0x21B)
1565#define SPR_DBAT2U (0x21C)
1566#define SPR_DBAT2L (0x21D)
1567#define SPR_DBAT3U (0x21E)
1568#define SPR_DBAT3L (0x21F)
1569#define SPR_IBAT4U (0x230)
1570#define SPR_RPCU_BBCMCR (0x230)
1571#define SPR_MPC_IC_CST (0x230)
1572#define SPR_Exxx_CTXCR (0x230)
1573#define SPR_IBAT4L (0x231)
1574#define SPR_MPC_IC_ADR (0x231)
1575#define SPR_Exxx_DBCR3 (0x231)
1576#define SPR_IBAT5U (0x232)
1577#define SPR_MPC_IC_DAT (0x232)
1578#define SPR_Exxx_DBCNT (0x232)
1579#define SPR_IBAT5L (0x233)
1580#define SPR_IBAT6U (0x234)
1581#define SPR_IBAT6L (0x235)
1582#define SPR_IBAT7U (0x236)
1583#define SPR_IBAT7L (0x237)
1584#define SPR_DBAT4U (0x238)
1585#define SPR_RCPU_L2U_MCR (0x238)
1586#define SPR_MPC_DC_CST (0x238)
1587#define SPR_Exxx_ALTCTXCR (0x238)
1588#define SPR_DBAT4L (0x239)
1589#define SPR_MPC_DC_ADR (0x239)
1590#define SPR_DBAT5U (0x23A)
1591#define SPR_BOOKE_MCSRR0 (0x23A)
1592#define SPR_MPC_DC_DAT (0x23A)
1593#define SPR_DBAT5L (0x23B)
1594#define SPR_BOOKE_MCSRR1 (0x23B)
1595#define SPR_DBAT6U (0x23C)
1596#define SPR_BOOKE_MCSR (0x23C)
1597#define SPR_DBAT6L (0x23D)
1598#define SPR_Exxx_MCAR (0x23D)
1599#define SPR_DBAT7U (0x23E)
1600#define SPR_BOOKE_DSRR0 (0x23E)
1601#define SPR_DBAT7L (0x23F)
1602#define SPR_BOOKE_DSRR1 (0x23F)
1603#define SPR_BOOKE_SPRG8 (0x25C)
1604#define SPR_BOOKE_SPRG9 (0x25D)
1605#define SPR_BOOKE_MAS0 (0x270)
1606#define SPR_BOOKE_MAS1 (0x271)
1607#define SPR_BOOKE_MAS2 (0x272)
1608#define SPR_BOOKE_MAS3 (0x273)
1609#define SPR_BOOKE_MAS4 (0x274)
1610#define SPR_BOOKE_MAS5 (0x275)
1611#define SPR_BOOKE_MAS6 (0x276)
1612#define SPR_BOOKE_PID1 (0x279)
1613#define SPR_BOOKE_PID2 (0x27A)
1614#define SPR_MPC_DPDR (0x280)
1615#define SPR_MPC_IMMR (0x288)
1616#define SPR_BOOKE_TLB0CFG (0x2B0)
1617#define SPR_BOOKE_TLB1CFG (0x2B1)
1618#define SPR_BOOKE_TLB2CFG (0x2B2)
1619#define SPR_BOOKE_TLB3CFG (0x2B3)
1620#define SPR_BOOKE_EPR (0x2BE)
1621#define SPR_PERF0 (0x300)
1622#define SPR_RCPU_MI_RBA0 (0x300)
1623#define SPR_MPC_MI_CTR (0x300)
14646457 1624#define SPR_POWER_USIER (0x300)
80d11f44
JM		 1625#define SPR_PERF1 (0x301)
1626#define SPR_RCPU_MI_RBA1 (0x301)
70c53407 1627#define SPR_POWER_UMMCR2 (0x301)
80d11f44
JM		 1628#define SPR_PERF2 (0x302)
1629#define SPR_RCPU_MI_RBA2 (0x302)
1630#define SPR_MPC_MI_AP (0x302)
75b9c321 1631#define SPR_POWER_UMMCRA (0x302)
80d11f44
JM		 1632#define SPR_PERF3 (0x303)
1633#define SPR_RCPU_MI_RBA3 (0x303)
1634#define SPR_MPC_MI_EPN (0x303)
fd51ff63 1635#define SPR_POWER_UPMC1 (0x303)
80d11f44 1636#define SPR_PERF4 (0x304)
fd51ff63 1637#define SPR_POWER_UPMC2 (0x304)
80d11f44
JM		 1638#define SPR_PERF5 (0x305)
1639#define SPR_MPC_MI_TWC (0x305)
fd51ff63 1640#define SPR_POWER_UPMC3 (0x305)
80d11f44
JM		 1641#define SPR_PERF6 (0x306)
1642#define SPR_MPC_MI_RPN (0x306)
fd51ff63 1643#define SPR_POWER_UPMC4 (0x306)
80d11f44 1644#define SPR_PERF7 (0x307)
fd51ff63 1645#define SPR_POWER_UPMC5 (0x307)
80d11f44
JM		 1646#define SPR_PERF8 (0x308)
1647#define SPR_RCPU_L2U_RBA0 (0x308)
1648#define SPR_MPC_MD_CTR (0x308)
fd51ff63 1649#define SPR_POWER_UPMC6 (0x308)
80d11f44
JM		 1650#define SPR_PERF9 (0x309)
1651#define SPR_RCPU_L2U_RBA1 (0x309)
1652#define SPR_MPC_MD_CASID (0x309)
c36c97f8 1653#define SPR_970_UPMC7 (0X309)
80d11f44
JM		 1654#define SPR_PERFA (0x30A)
1655#define SPR_RCPU_L2U_RBA2 (0x30A)
1656#define SPR_MPC_MD_AP (0x30A)
c36c97f8 1657#define SPR_970_UPMC8 (0X30A)
80d11f44
JM		 1658#define SPR_PERFB (0x30B)
1659#define SPR_RCPU_L2U_RBA3 (0x30B)
1660#define SPR_MPC_MD_EPN (0x30B)
fd51ff63 1661#define SPR_POWER_UMMCR0 (0X30B)
80d11f44
JM		 1662#define SPR_PERFC (0x30C)
1663#define SPR_MPC_MD_TWB (0x30C)
fd51ff63 1664#define SPR_POWER_USIAR (0X30C)
80d11f44
JM		 1665#define SPR_PERFD (0x30D)
1666#define SPR_MPC_MD_TWC (0x30D)
fd51ff63 1667#define SPR_POWER_USDAR (0X30D)
80d11f44
JM		 1668#define SPR_PERFE (0x30E)
1669#define SPR_MPC_MD_RPN (0x30E)
fd51ff63 1670#define SPR_POWER_UMMCR1 (0X30E)
80d11f44
JM		 1671#define SPR_PERFF (0x30F)
1672#define SPR_MPC_MD_TW (0x30F)
1673#define SPR_UPERF0 (0x310)
14646457 1674#define SPR_POWER_SIER (0x310)
80d11f44 1675#define SPR_UPERF1 (0x311)
70c53407 1676#define SPR_POWER_MMCR2 (0x311)
80d11f44 1677#define SPR_UPERF2 (0x312)
75b9c321 1678#define SPR_POWER_MMCRA (0X312)
80d11f44 1679#define SPR_UPERF3 (0x313)
fd51ff63 1680#define SPR_POWER_PMC1 (0X313)
80d11f44 1681#define SPR_UPERF4 (0x314)
fd51ff63 1682#define SPR_POWER_PMC2 (0X314)
80d11f44 1683#define SPR_UPERF5 (0x315)
fd51ff63 1684#define SPR_POWER_PMC3 (0X315)
80d11f44 1685#define SPR_UPERF6 (0x316)
fd51ff63 1686#define SPR_POWER_PMC4 (0X316)
80d11f44 1687#define SPR_UPERF7 (0x317)
fd51ff63 1688#define SPR_POWER_PMC5 (0X317)
80d11f44 1689#define SPR_UPERF8 (0x318)
fd51ff63 1690#define SPR_POWER_PMC6 (0X318)
80d11f44 1691#define SPR_UPERF9 (0x319)
c36c97f8 1692#define SPR_970_PMC7 (0X319)
80d11f44 1693#define SPR_UPERFA (0x31A)
c36c97f8 1694#define SPR_970_PMC8 (0X31A)
80d11f44 1695#define SPR_UPERFB (0x31B)
fd51ff63 1696#define SPR_POWER_MMCR0 (0X31B)
80d11f44 1697#define SPR_UPERFC (0x31C)
fd51ff63 1698#define SPR_POWER_SIAR (0X31C)
80d11f44 1699#define SPR_UPERFD (0x31D)
fd51ff63 1700#define SPR_POWER_SDAR (0X31D)
80d11f44 1701#define SPR_UPERFE (0x31E)
fd51ff63 1702#define SPR_POWER_MMCR1 (0X31E)
80d11f44
JM		 1703#define SPR_UPERFF (0x31F)
1704#define SPR_RCPU_MI_RA0 (0x320)
1705#define SPR_MPC_MI_DBCAM (0x320)
4ee4a03b 1706#define SPR_BESCRS (0x320)
80d11f44
JM		 1707#define SPR_RCPU_MI_RA1 (0x321)
1708#define SPR_MPC_MI_DBRAM0 (0x321)
4ee4a03b 1709#define SPR_BESCRSU (0x321)
80d11f44
JM		 1710#define SPR_RCPU_MI_RA2 (0x322)
1711#define SPR_MPC_MI_DBRAM1 (0x322)
4ee4a03b 1712#define SPR_BESCRR (0x322)
80d11f44 1713#define SPR_RCPU_MI_RA3 (0x323)
4ee4a03b
AK		 1714#define SPR_BESCRRU (0x323)
1715#define SPR_EBBHR (0x324)
1716#define SPR_EBBRR (0x325)
1717#define SPR_BESCR (0x326)
80d11f44
JM		 1718#define SPR_RCPU_L2U_RA0 (0x328)
1719#define SPR_MPC_MD_DBCAM (0x328)
1720#define SPR_RCPU_L2U_RA1 (0x329)
1721#define SPR_MPC_MD_DBRAM0 (0x329)
1722#define SPR_RCPU_L2U_RA2 (0x32A)
1723#define SPR_MPC_MD_DBRAM1 (0x32A)
1724#define SPR_RCPU_L2U_RA3 (0x32B)
60511041 1725#define SPR_TAR (0x32F)
21a558be 1726#define SPR_IC (0x350)
3ba55e39 1727#define SPR_VTB (0x351)
1488270e 1728#define SPR_MMCRC (0x353)
80d11f44
JM		 1729#define SPR_440_INV0 (0x370)
1730#define SPR_440_INV1 (0x371)
1731#define SPR_440_INV2 (0x372)
1732#define SPR_440_INV3 (0x373)
1733#define SPR_440_ITV0 (0x374)
1734#define SPR_440_ITV1 (0x375)
1735#define SPR_440_ITV2 (0x376)
1736#define SPR_440_ITV3 (0x377)
1737#define SPR_440_CCR1 (0x378)
14646457
BH		 1738#define SPR_TACR (0x378)
1739#define SPR_TCSCR (0x379)
1740#define SPR_CSIGR (0x37a)
80d11f44 1741#define SPR_DCRIPR (0x37B)
14646457
BH		 1742#define SPR_POWER_SPMC1 (0x37C)
1743#define SPR_POWER_SPMC2 (0x37D)
70c53407 1744#define SPR_POWER_MMCRS (0x37E)
9c1cf38d 1745#define SPR_WORT (0x37F)
80d11f44 1746#define SPR_PPR (0x380)
bd928eba 1747#define SPR_750_GQR0 (0x390)
80d11f44 1748#define SPR_440_DNV0 (0x390)
bd928eba 1749#define SPR_750_GQR1 (0x391)
80d11f44 1750#define SPR_440_DNV1 (0x391)
bd928eba 1751#define SPR_750_GQR2 (0x392)
80d11f44 1752#define SPR_440_DNV2 (0x392)
bd928eba 1753#define SPR_750_GQR3 (0x393)
80d11f44 1754#define SPR_440_DNV3 (0x393)
bd928eba 1755#define SPR_750_GQR4 (0x394)
80d11f44 1756#define SPR_440_DTV0 (0x394)
bd928eba 1757#define SPR_750_GQR5 (0x395)
80d11f44 1758#define SPR_440_DTV1 (0x395)
bd928eba 1759#define SPR_750_GQR6 (0x396)
80d11f44 1760#define SPR_440_DTV2 (0x396)
bd928eba 1761#define SPR_750_GQR7 (0x397)
80d11f44 1762#define SPR_440_DTV3 (0x397)
bd928eba
JM		 1763#define SPR_750_THRM4 (0x398)
1764#define SPR_750CL_HID2 (0x398)
80d11f44 1765#define SPR_440_DVLIM (0x398)
bd928eba 1766#define SPR_750_WPAR (0x399)
80d11f44 1767#define SPR_440_IVLIM (0x399)
1488270e 1768#define SPR_TSCR (0x399)
bd928eba
JM		 1769#define SPR_750_DMAU (0x39A)
1770#define SPR_750_DMAL (0x39B)
80d11f44
JM		 1771#define SPR_440_RSTCFG (0x39B)
1772#define SPR_BOOKE_DCDBTRL (0x39C)
1773#define SPR_BOOKE_DCDBTRH (0x39D)
1774#define SPR_BOOKE_ICDBTRL (0x39E)
1775#define SPR_BOOKE_ICDBTRH (0x39F)
cb8b8bf8
AK		 1776#define SPR_74XX_UMMCR2 (0x3A0)
1777#define SPR_7XX_UPMC5 (0x3A1)
1778#define SPR_7XX_UPMC6 (0x3A2)
80d11f44 1779#define SPR_UBAMR (0x3A7)
cb8b8bf8
AK		 1780#define SPR_7XX_UMMCR0 (0x3A8)
1781#define SPR_7XX_UPMC1 (0x3A9)
1782#define SPR_7XX_UPMC2 (0x3AA)
1783#define SPR_7XX_USIAR (0x3AB)
1784#define SPR_7XX_UMMCR1 (0x3AC)
1785#define SPR_7XX_UPMC3 (0x3AD)
1786#define SPR_7XX_UPMC4 (0x3AE)
80d11f44
JM		 1787#define SPR_USDA (0x3AF)
1788#define SPR_40x_ZPR (0x3B0)
1789#define SPR_BOOKE_MAS7 (0x3B0)
cb8b8bf8
AK		 1790#define SPR_74XX_MMCR2 (0x3B0)
1791#define SPR_7XX_PMC5 (0x3B1)
80d11f44 1792#define SPR_40x_PID (0x3B1)
cb8b8bf8 1793#define SPR_7XX_PMC6 (0x3B2)
80d11f44 1794#define SPR_440_MMUCR (0x3B2)
80d11f44
JM		 1795#define SPR_4xx_CCR0 (0x3B3)
1796#define SPR_BOOKE_EPLC (0x3B3)
80d11f44
JM		 1797#define SPR_405_IAC3 (0x3B4)
1798#define SPR_BOOKE_EPSC (0x3B4)
80d11f44 1799#define SPR_405_IAC4 (0x3B5)
80d11f44 1800#define SPR_405_DVC1 (0x3B6)
80d11f44 1801#define SPR_405_DVC2 (0x3B7)
80d11f44 1802#define SPR_BAMR (0x3B7)
cb8b8bf8
AK		 1803#define SPR_7XX_MMCR0 (0x3B8)
1804#define SPR_7XX_PMC1 (0x3B9)
80d11f44 1805#define SPR_40x_SGR (0x3B9)
cb8b8bf8 1806#define SPR_7XX_PMC2 (0x3BA)
80d11f44 1807#define SPR_40x_DCWR (0x3BA)
cb8b8bf8 1808#define SPR_7XX_SIAR (0x3BB)
80d11f44 1809#define SPR_405_SLER (0x3BB)
cb8b8bf8 1810#define SPR_7XX_MMCR1 (0x3BC)
80d11f44 1811#define SPR_405_SU0R (0x3BC)
80d11f44 1812#define SPR_401_SKR (0x3BC)
cb8b8bf8 1813#define SPR_7XX_PMC3 (0x3BD)
80d11f44 1814#define SPR_405_DBCR1 (0x3BD)
cb8b8bf8 1815#define SPR_7XX_PMC4 (0x3BE)
80d11f44 1816#define SPR_SDA (0x3BF)
80d11f44
JM		 1817#define SPR_403_VTBL (0x3CC)
1818#define SPR_403_VTBU (0x3CD)
1819#define SPR_DMISS (0x3D0)
1820#define SPR_DCMP (0x3D1)
1821#define SPR_HASH1 (0x3D2)
1822#define SPR_HASH2 (0x3D3)
1823#define SPR_BOOKE_ICDBDR (0x3D3)
1824#define SPR_TLBMISS (0x3D4)
1825#define SPR_IMISS (0x3D4)
1826#define SPR_40x_ESR (0x3D4)
1827#define SPR_PTEHI (0x3D5)
1828#define SPR_ICMP (0x3D5)
1829#define SPR_40x_DEAR (0x3D5)
1830#define SPR_PTELO (0x3D6)
1831#define SPR_RPA (0x3D6)
1832#define SPR_40x_EVPR (0x3D6)
1833#define SPR_L3PM (0x3D7)
1834#define SPR_403_CDBCR (0x3D7)
4e777442 1835#define SPR_L3ITCR0 (0x3D8)
80d11f44
JM		 1836#define SPR_TCR (0x3D8)
1837#define SPR_40x_TSR (0x3D8)
1838#define SPR_IBR (0x3DA)
1839#define SPR_40x_TCR (0x3DA)
1840#define SPR_ESASRR (0x3DB)
1841#define SPR_40x_PIT (0x3DB)
1842#define SPR_403_TBL (0x3DC)
1843#define SPR_403_TBU (0x3DD)
1844#define SPR_SEBR (0x3DE)
1845#define SPR_40x_SRR2 (0x3DE)
1846#define SPR_SER (0x3DF)
1847#define SPR_40x_SRR3 (0x3DF)
4e777442 1848#define SPR_L3OHCR (0x3E8)
80d11f44
JM		 1849#define SPR_L3ITCR1 (0x3E9)
1850#define SPR_L3ITCR2 (0x3EA)
1851#define SPR_L3ITCR3 (0x3EB)
1852#define SPR_HID0 (0x3F0)
1853#define SPR_40x_DBSR (0x3F0)
1854#define SPR_HID1 (0x3F1)
1855#define SPR_IABR (0x3F2)
1856#define SPR_40x_DBCR0 (0x3F2)
1857#define SPR_601_HID2 (0x3F2)
1858#define SPR_Exxx_L1CSR0 (0x3F2)
1859#define SPR_ICTRL (0x3F3)
1860#define SPR_HID2 (0x3F3)
bd928eba 1861#define SPR_750CL_HID4 (0x3F3)
80d11f44
JM		 1862#define SPR_Exxx_L1CSR1 (0x3F3)
1863#define SPR_440_DBDR (0x3F3)
1864#define SPR_LDSTDB (0x3F4)
bd928eba 1865#define SPR_750_TDCL (0x3F4)
80d11f44
JM		 1866#define SPR_40x_IAC1 (0x3F4)
1867#define SPR_MMUCSR0 (0x3F4)
ba881002 1868#define SPR_970_HID4 (0x3F4)
80d11f44 1869#define SPR_DABR (0x3F5)
3fc6c082 1870#define DABR_MASK (~(target_ulong)0x7)
80d11f44
JM		 1871#define SPR_Exxx_BUCSR (0x3F5)
1872#define SPR_40x_IAC2 (0x3F5)
1873#define SPR_601_HID5 (0x3F5)
1874#define SPR_40x_DAC1 (0x3F6)
1875#define SPR_MSSCR0 (0x3F6)
1876#define SPR_970_HID5 (0x3F6)
1877#define SPR_MSSSR0 (0x3F7)
4e777442 1878#define SPR_MSSCR1 (0x3F7)
80d11f44
JM		 1879#define SPR_DABRX (0x3F7)
1880#define SPR_40x_DAC2 (0x3F7)
1881#define SPR_MMUCFG (0x3F7)
1882#define SPR_LDSTCR (0x3F8)
1883#define SPR_L2PMCR (0x3F8)
bd928eba 1884#define SPR_750FX_HID2 (0x3F8)
80d11f44
JM		 1885#define SPR_Exxx_L1FINV0 (0x3F8)
1886#define SPR_L2CR (0x3F9)
80d11f44 1887#define SPR_L3CR (0x3FA)
bd928eba 1888#define SPR_750_TDCH (0x3FA)
80d11f44
JM		 1889#define SPR_IABR2 (0x3FA)
1890#define SPR_40x_DCCR (0x3FA)
1891#define SPR_ICTC (0x3FB)
1892#define SPR_40x_ICCR (0x3FB)
1893#define SPR_THRM1 (0x3FC)
1894#define SPR_403_PBL1 (0x3FC)
1895#define SPR_SP (0x3FD)
1896#define SPR_THRM2 (0x3FD)
1897#define SPR_403_PBU1 (0x3FD)
1898#define SPR_604_HID13 (0x3FD)
1899#define SPR_LT (0x3FE)
1900#define SPR_THRM3 (0x3FE)
1901#define SPR_RCPU_FPECR (0x3FE)
1902#define SPR_403_PBL2 (0x3FE)
1903#define SPR_PIR (0x3FF)
1904#define SPR_403_PBU2 (0x3FF)
1905#define SPR_601_HID15 (0x3FF)
1906#define SPR_604_HID15 (0x3FF)
1907#define SPR_E500_SVR (0x3FF)
79aceca5 1908
84755ed5
AG		 1909/* Disable MAS Interrupt Updates for Hypervisor */
1910#define EPCR_DMIUH (1 << 22)
1911/* Disable Guest TLB Management Instructions */
1912#define EPCR_DGTMI (1 << 23)
1913/* Guest Interrupt Computation Mode */
1914#define EPCR_GICM (1 << 24)
1915/* Interrupt Computation Mode */
1916#define EPCR_ICM (1 << 25)
1917/* Disable Embedded Hypervisor Debug */
1918#define EPCR_DUVD (1 << 26)
1919/* Instruction Storage Interrupt Directed to Guest State */
1920#define EPCR_ISIGS (1 << 27)
1921/* Data Storage Interrupt Directed to Guest State */
1922#define EPCR_DSIGS (1 << 28)
1923/* Instruction TLB Error Interrupt Directed to Guest State */
1924#define EPCR_ITLBGS (1 << 29)
1925/* Data TLB Error Interrupt Directed to Guest State */
1926#define EPCR_DTLBGS (1 << 30)
1927/* External Input Interrupt Directed to Guest State */
1928#define EPCR_EXTGS (1 << 31)
1929
ea71258d
AG		 1930#define L1CSR0_CPE 0x00010000 /* Data Cache Parity Enable */
1931#define L1CSR0_CUL 0x00000400 /* (D-)Cache Unable to Lock */
1932#define L1CSR0_DCLFR 0x00000100 /* D-Cache Lock Flash Reset */
1933#define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */
1934#define L1CSR0_DCE 0x00000001 /* Data Cache Enable */
1935
1936#define L1CSR1_CPE 0x00010000 /* Instruction Cache Parity Enable */
1937#define L1CSR1_ICUL 0x00000400 /* I-Cache Unable to Lock */
1938#define L1CSR1_ICLFR 0x00000100 /* I-Cache Lock Flash Reset */
1939#define L1CSR1_ICFI 0x00000002 /* Instruction Cache Flash Invalidate */
1940#define L1CSR1_ICE 0x00000001 /* Instruction Cache Enable */
1941
bbc01ca7 1942/* HID0 bits */
1488270e
BH		 1943#define HID0_DEEPNAP (1 << 24) /* pre-2.06 */
1944#define HID0_DOZE (1 << 23) /* pre-2.06 */
1945#define HID0_NAP (1 << 22) /* pre-2.06 */
1946#define HID0_HILE (1ull << (63 - 19)) /* POWER8 */
bbc01ca7 1947
c29b735c
NF		 1948/*****************************************************************************/
1949/* PowerPC Instructions types definitions */
1950enum {
1951 PPC_NONE = 0x0000000000000000ULL,
1952 /* PowerPC base instructions set */
1953 PPC_INSNS_BASE = 0x0000000000000001ULL,
1954 /* integer operations instructions */
1955#define PPC_INTEGER PPC_INSNS_BASE
1956 /* flow control instructions */
1957#define PPC_FLOW PPC_INSNS_BASE
1958 /* virtual memory instructions */
1959#define PPC_MEM PPC_INSNS_BASE
1960 /* ld/st with reservation instructions */
1961#define PPC_RES PPC_INSNS_BASE
1962 /* spr/msr access instructions */
1963#define PPC_MISC PPC_INSNS_BASE
1964 /* Deprecated instruction sets */
1965 /* Original POWER instruction set */
1966 PPC_POWER = 0x0000000000000002ULL,
1967 /* POWER2 instruction set extension */
1968 PPC_POWER2 = 0x0000000000000004ULL,
1969 /* Power RTC support */
1970 PPC_POWER_RTC = 0x0000000000000008ULL,
1971 /* Power-to-PowerPC bridge (601) */
1972 PPC_POWER_BR = 0x0000000000000010ULL,
1973 /* 64 bits PowerPC instruction set */
1974 PPC_64B = 0x0000000000000020ULL,
1975 /* New 64 bits extensions (PowerPC 2.0x) */
1976 PPC_64BX = 0x0000000000000040ULL,
1977 /* 64 bits hypervisor extensions */
1978 PPC_64H = 0x0000000000000080ULL,
1979 /* New wait instruction (PowerPC 2.0x) */
1980 PPC_WAIT = 0x0000000000000100ULL,
1981 /* Time base mftb instruction */
1982 PPC_MFTB = 0x0000000000000200ULL,
1983
1984 /* Fixed-point unit extensions */
1985 /* PowerPC 602 specific */
1986 PPC_602_SPEC = 0x0000000000000400ULL,
1987 /* isel instruction */
1988 PPC_ISEL = 0x0000000000000800ULL,
1989 /* popcntb instruction */
1990 PPC_POPCNTB = 0x0000000000001000ULL,
1991 /* string load / store */
1992 PPC_STRING = 0x0000000000002000ULL,
b7815375
BH		 1993 /* real mode cache inhibited load / store */
1994 PPC_CILDST = 0x0000000000004000ULL,
c29b735c
NF		 1995
1996 /* Floating-point unit extensions */
1997 /* Optional floating point instructions */
1998 PPC_FLOAT = 0x0000000000010000ULL,
1999 /* New floating-point extensions (PowerPC 2.0x) */
2000 PPC_FLOAT_EXT = 0x0000000000020000ULL,
2001 PPC_FLOAT_FSQRT = 0x0000000000040000ULL,
2002 PPC_FLOAT_FRES = 0x0000000000080000ULL,
2003 PPC_FLOAT_FRSQRTE = 0x0000000000100000ULL,
2004 PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
2005 PPC_FLOAT_FSEL = 0x0000000000400000ULL,
2006 PPC_FLOAT_STFIWX = 0x0000000000800000ULL,
2007
2008 /* Vector/SIMD extensions */
2009 /* Altivec support */
2010 PPC_ALTIVEC = 0x0000000001000000ULL,
2011 /* PowerPC 2.03 SPE extension */
2012 PPC_SPE = 0x0000000002000000ULL,
2013 /* PowerPC 2.03 SPE single-precision floating-point extension */
2014 PPC_SPE_SINGLE = 0x0000000004000000ULL,
2015 /* PowerPC 2.03 SPE double-precision floating-point extension */
2016 PPC_SPE_DOUBLE = 0x0000000008000000ULL,
2017
2018 /* Optional memory control instructions */
2019 PPC_MEM_TLBIA = 0x0000000010000000ULL,
2020 PPC_MEM_TLBIE = 0x0000000020000000ULL,
2021 PPC_MEM_TLBSYNC = 0x0000000040000000ULL,
2022 /* sync instruction */
2023 PPC_MEM_SYNC = 0x0000000080000000ULL,
2024 /* eieio instruction */
2025 PPC_MEM_EIEIO = 0x0000000100000000ULL,
2026
2027 /* Cache control instructions */
2028 PPC_CACHE = 0x0000000200000000ULL,
2029 /* icbi instruction */
2030 PPC_CACHE_ICBI = 0x0000000400000000ULL,
8e33944f 2031 /* dcbz instruction */
c29b735c 2032 PPC_CACHE_DCBZ = 0x0000000800000000ULL,
c29b735c
NF		 2033 /* dcba instruction */
2034 PPC_CACHE_DCBA = 0x0000002000000000ULL,
2035 /* Freescale cache locking instructions */
2036 PPC_CACHE_LOCK = 0x0000004000000000ULL,
2037
2038 /* MMU related extensions */
2039 /* external control instructions */
2040 PPC_EXTERN = 0x0000010000000000ULL,
2041 /* segment register access instructions */
2042 PPC_SEGMENT = 0x0000020000000000ULL,
2043 /* PowerPC 6xx TLB management instructions */
2044 PPC_6xx_TLB = 0x0000040000000000ULL,
2045 /* PowerPC 74xx TLB management instructions */
2046 PPC_74xx_TLB = 0x0000080000000000ULL,
2047 /* PowerPC 40x TLB management instructions */
2048 PPC_40x_TLB = 0x0000100000000000ULL,
2049 /* segment register access instructions for PowerPC 64 "bridge" */
2050 PPC_SEGMENT_64B = 0x0000200000000000ULL,
2051 /* SLB management */
2052 PPC_SLBI = 0x0000400000000000ULL,
2053
2054 /* Embedded PowerPC dedicated instructions */
2055 PPC_WRTEE = 0x0001000000000000ULL,
2056 /* PowerPC 40x exception model */
2057 PPC_40x_EXCP = 0x0002000000000000ULL,
2058 /* PowerPC 405 Mac instructions */
2059 PPC_405_MAC = 0x0004000000000000ULL,
2060 /* PowerPC 440 specific instructions */
2061 PPC_440_SPEC = 0x0008000000000000ULL,
2062 /* BookE (embedded) PowerPC specification */
2063 PPC_BOOKE = 0x0010000000000000ULL,
2064 /* mfapidi instruction */
2065 PPC_MFAPIDI = 0x0020000000000000ULL,
2066 /* tlbiva instruction */
2067 PPC_TLBIVA = 0x0040000000000000ULL,
2068 /* tlbivax instruction */
2069 PPC_TLBIVAX = 0x0080000000000000ULL,
2070 /* PowerPC 4xx dedicated instructions */
2071 PPC_4xx_COMMON = 0x0100000000000000ULL,
2072 /* PowerPC 40x ibct instructions */
2073 PPC_40x_ICBT = 0x0200000000000000ULL,
2074 /* rfmci is not implemented in all BookE PowerPC */
2075 PPC_RFMCI = 0x0400000000000000ULL,
2076 /* rfdi instruction */
2077 PPC_RFDI = 0x0800000000000000ULL,
2078 /* DCR accesses */
2079 PPC_DCR = 0x1000000000000000ULL,
2080 /* DCR extended accesse */
2081 PPC_DCRX = 0x2000000000000000ULL,
2082 /* user-mode DCR access, implemented in PowerPC 460 */
2083 PPC_DCRUX = 0x4000000000000000ULL,
eaabeef2
DG		 2084 /* popcntw and popcntd instructions */
2085 PPC_POPCNTWD = 0x8000000000000000ULL,
01662f3e 2086
02d4eae4
DG		 2087#define PPC_TCG_INSNS (PPC_INSNS_BASE | PPC_POWER | PPC_POWER2 \
2088 | PPC_POWER_RTC | PPC_POWER_BR | PPC_64B \
2089 | PPC_64BX | PPC_64H | PPC_WAIT | PPC_MFTB \
2090 | PPC_602_SPEC | PPC_ISEL | PPC_POPCNTB \
2091 | PPC_STRING | PPC_FLOAT | PPC_FLOAT_EXT \
2092 | PPC_FLOAT_FSQRT | PPC_FLOAT_FRES \
2093 | PPC_FLOAT_FRSQRTE | PPC_FLOAT_FRSQRTES \
2094 | PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX \
2095 | PPC_ALTIVEC | PPC_SPE | PPC_SPE_SINGLE \
2096 | PPC_SPE_DOUBLE | PPC_MEM_TLBIA \
2097 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC \
2098 | PPC_MEM_SYNC | PPC_MEM_EIEIO \
2099 | PPC_CACHE | PPC_CACHE_ICBI \
8e33944f 2100 | PPC_CACHE_DCBZ \
02d4eae4
DG		 2101 | PPC_CACHE_DCBA | PPC_CACHE_LOCK \
2102 | PPC_EXTERN | PPC_SEGMENT | PPC_6xx_TLB \
2103 | PPC_74xx_TLB | PPC_40x_TLB | PPC_SEGMENT_64B \
2104 | PPC_SLBI | PPC_WRTEE | PPC_40x_EXCP \
2105 | PPC_405_MAC | PPC_440_SPEC | PPC_BOOKE \
2106 | PPC_MFAPIDI | PPC_TLBIVA | PPC_TLBIVAX \
2107 | PPC_4xx_COMMON | PPC_40x_ICBT | PPC_RFMCI \
2108 | PPC_RFDI | PPC_DCR | PPC_DCRX | PPC_DCRUX \
b7815375 2109 | PPC_POPCNTWD | PPC_CILDST)
02d4eae4 2110
01662f3e
AG		 2111 /* extended type values */
2112
2113 /* BookE 2.06 PowerPC specification */
2114 PPC2_BOOKE206 = 0x0000000000000001ULL,
a7342588
DG		 2115 /* VSX (extensions to Altivec / VMX) */
2116 PPC2_VSX = 0x0000000000000002ULL,
2117 /* Decimal Floating Point (DFP) */
2118 PPC2_DFP = 0x0000000000000004ULL,
3f9f6a50
AG		 2119 /* Embedded.Processor Control */
2120 PPC2_PRCNTL = 0x0000000000000008ULL,
cd6e9320
TH		 2121 /* Byte-reversed, indexed, double-word load and store */
2122 PPC2_DBRX = 0x0000000000000010ULL,
9c2627b0
AJ		 2123 /* Book I 2.05 PowerPC specification */
2124 PPC2_ISA205 = 0x0000000000000020ULL,
dbcc48fa
TM		 2125 /* VSX additions in ISA 2.07 */
2126 PPC2_VSX207 = 0x0000000000000040ULL,
86ba37ed
TM		 2127 /* ISA 2.06B bpermd */
2128 PPC2_PERM_ISA206 = 0x0000000000000080ULL,
a824bc19
TM		 2129 /* ISA 2.06B divide extended variants */
2130 PPC2_DIVE_ISA206 = 0x0000000000000100ULL,
1fa6c533
TM		 2131 /* ISA 2.06B larx/stcx. instructions */
2132 PPC2_ATOMIC_ISA206 = 0x0000000000000200ULL,
1b0bd002
TM		 2133 /* ISA 2.06B floating point integer conversion */
2134 PPC2_FP_CVT_ISA206 = 0x0000000000000400ULL,
29a0e4e9
TM		 2135 /* ISA 2.06B floating point test instructions */
2136 PPC2_FP_TST_ISA206 = 0x0000000000000800ULL,
94840e07
TM		 2137 /* ISA 2.07 bctar instruction */
2138 PPC2_BCTAR_ISA207 = 0x0000000000001000ULL,
38a85337
TM		 2139 /* ISA 2.07 load/store quadword */
2140 PPC2_LSQ_ISA207 = 0x0000000000002000ULL,
32ea54ab
TM		 2141 /* ISA 2.07 Altivec */
2142 PPC2_ALTIVEC_207 = 0x0000000000004000ULL,
df99d30d
AK		 2143 /* PowerISA 2.07 Book3s specification */
2144 PPC2_ISA207S = 0x0000000000008000ULL,
4171853c
PM		 2145 /* Double precision floating point conversion for signed integer 64 */
2146 PPC2_FP_CVT_S64 = 0x0000000000010000ULL,
f90468b6
TM		 2147 /* Transactional Memory (ISA 2.07, Book II) */
2148 PPC2_TM = 0x0000000000020000ULL,
7778a575
BH		 2149 /* Server PM instructgions (ISA 2.06, Book III) */
2150 PPC2_PM_ISA206 = 0x0000000000040000ULL,
eb640b13
ND		 2151 /* POWER ISA 3.0 */
2152 PPC2_ISA300 = 0x0000000000080000ULL,
02d4eae4 2153
74f23997 2154#define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX | \
a824bc19 2155 PPC2_ISA205 | PPC2_VSX207 | PPC2_PERM_ISA206 | \
1b0bd002 2156 PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | \
94840e07 2157 PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | \
32ea54ab 2158 PPC2_BCTAR_ISA207 | PPC2_LSQ_ISA207 | \
4171853c 2159 PPC2_ALTIVEC_207 | PPC2_ISA207S | PPC2_DFP | \
eb640b13
ND		 2160 PPC2_FP_CVT_S64 | PPC2_TM | PPC2_PM_ISA206 | \
2161 PPC2_ISA300)
c29b735c
NF		 2162};
2163
76a66253 2164/*****************************************************************************/
9a64fbe4
FB		 2165/* Memory access type :
2166 * may be needed for precise access rights control and precise exceptions.
2167 */
79aceca5 2168enum {
9a64fbe4
FB		 2169 /* 1 bit to define user level / supervisor access */
2170 ACCESS_USER = 0x00,
2171 ACCESS_SUPER = 0x01,
2172 /* Type of instruction that generated the access */
2173 ACCESS_CODE = 0x10, /* Code fetch access */
2174 ACCESS_INT = 0x20, /* Integer load/store access */
2175 ACCESS_FLOAT = 0x30, /* floating point load/store access */
2176 ACCESS_RES = 0x40, /* load/store with reservation */
2177 ACCESS_EXT = 0x50, /* external access */
2178 ACCESS_CACHE = 0x60, /* Cache manipulation */
2179};
2180
47103572
JM		 2181/* Hardware interruption sources:
2182 * all those exception can be raised simulteaneously
2183 */
e9df014c
JM		 2184/* Input pins definitions */
2185enum {
2186 /* 6xx bus input pins */
24be5ae3
JM		 2187 PPC6xx_INPUT_HRESET = 0,
2188 PPC6xx_INPUT_SRESET = 1,
2189 PPC6xx_INPUT_CKSTP_IN = 2,
2190 PPC6xx_INPUT_MCP = 3,
2191 PPC6xx_INPUT_SMI = 4,
2192 PPC6xx_INPUT_INT = 5,
d68f1306
JM		 2193 PPC6xx_INPUT_TBEN = 6,
2194 PPC6xx_INPUT_WAKEUP = 7,
2195 PPC6xx_INPUT_NB,
24be5ae3
JM		 2196};
2197
2198enum {
e9df014c 2199 /* Embedded PowerPC input pins */
24be5ae3
JM		 2200 PPCBookE_INPUT_HRESET = 0,
2201 PPCBookE_INPUT_SRESET = 1,
2202 PPCBookE_INPUT_CKSTP_IN = 2,
2203 PPCBookE_INPUT_MCP = 3,
2204 PPCBookE_INPUT_SMI = 4,
2205 PPCBookE_INPUT_INT = 5,
2206 PPCBookE_INPUT_CINT = 6,
d68f1306 2207 PPCBookE_INPUT_NB,
24be5ae3
JM		 2208};
2209
9fdc60bf
AJ		 2210enum {
2211 /* PowerPC E500 input pins */
2212 PPCE500_INPUT_RESET_CORE = 0,
2213 PPCE500_INPUT_MCK = 1,
2214 PPCE500_INPUT_CINT = 3,
2215 PPCE500_INPUT_INT = 4,
2216 PPCE500_INPUT_DEBUG = 6,
2217 PPCE500_INPUT_NB,
2218};
2219
a750fc0b 2220enum {
4e290a0b
JM		 2221 /* PowerPC 40x input pins */
2222 PPC40x_INPUT_RESET_CORE = 0,
2223 PPC40x_INPUT_RESET_CHIP = 1,
2224 PPC40x_INPUT_RESET_SYS = 2,
2225 PPC40x_INPUT_CINT = 3,
2226 PPC40x_INPUT_INT = 4,
2227 PPC40x_INPUT_HALT = 5,
2228 PPC40x_INPUT_DEBUG = 6,
2229 PPC40x_INPUT_NB,
e9df014c
JM		 2230};
2231
b4095fed
JM		 2232enum {
2233 /* RCPU input pins */
2234 PPCRCPU_INPUT_PORESET = 0,
2235 PPCRCPU_INPUT_HRESET = 1,
2236 PPCRCPU_INPUT_SRESET = 2,
2237 PPCRCPU_INPUT_IRQ0 = 3,
2238 PPCRCPU_INPUT_IRQ1 = 4,
2239 PPCRCPU_INPUT_IRQ2 = 5,
2240 PPCRCPU_INPUT_IRQ3 = 6,
2241 PPCRCPU_INPUT_IRQ4 = 7,
2242 PPCRCPU_INPUT_IRQ5 = 8,
2243 PPCRCPU_INPUT_IRQ6 = 9,
2244 PPCRCPU_INPUT_IRQ7 = 10,
2245 PPCRCPU_INPUT_NB,
2246};
2247
00af685f 2248#if defined(TARGET_PPC64)
d0dfae6e
JM		 2249enum {
2250 /* PowerPC 970 input pins */
2251 PPC970_INPUT_HRESET = 0,
2252 PPC970_INPUT_SRESET = 1,
2253 PPC970_INPUT_CKSTP = 2,
2254 PPC970_INPUT_TBEN = 3,
2255 PPC970_INPUT_MCP = 4,
2256 PPC970_INPUT_INT = 5,
2257 PPC970_INPUT_THINT = 6,
7b62a955 2258 PPC970_INPUT_NB,
9d52e907
DG		 2259};
2260
2261enum {
2262 /* POWER7 input pins */
2263 POWER7_INPUT_INT = 0,
2264 /* POWER7 probably has other inputs, but we don't care about them
2265 * for any existing machine. We can wire these up when we need
2266 * them */
2267 POWER7_INPUT_NB,
d0dfae6e 2268};
00af685f 2269#endif
d0dfae6e 2270
e9df014c 2271/* Hardware exceptions definitions */
47103572 2272enum {
e9df014c 2273 /* External hardware exception sources */
e1833e1f 2274 PPC_INTERRUPT_RESET = 0, /* Reset exception */
d68f1306
JM		 2275 PPC_INTERRUPT_WAKEUP, /* Wakeup exception */
2276 PPC_INTERRUPT_MCK, /* Machine check exception */
2277 PPC_INTERRUPT_EXT, /* External interrupt */
2278 PPC_INTERRUPT_SMI, /* System management interrupt */
2279 PPC_INTERRUPT_CEXT, /* Critical external interrupt */
2280 PPC_INTERRUPT_DEBUG, /* External debug exception */
2281 PPC_INTERRUPT_THERM, /* Thermal exception */
e9df014c 2282 /* Internal hardware exception sources */
d68f1306
JM		 2283 PPC_INTERRUPT_DECR, /* Decrementer exception */
2284 PPC_INTERRUPT_HDECR, /* Hypervisor decrementer exception */
2285 PPC_INTERRUPT_PIT, /* Programmable inteval timer interrupt */
2286 PPC_INTERRUPT_FIT, /* Fixed interval timer interrupt */
2287 PPC_INTERRUPT_WDT, /* Watchdog timer interrupt */
2288 PPC_INTERRUPT_CDOORBELL, /* Critical doorbell interrupt */
2289 PPC_INTERRUPT_DOORBELL, /* Doorbell interrupt */
2290 PPC_INTERRUPT_PERFM, /* Performance monitor interrupt */
f03a1af5
BH		 2291 PPC_INTERRUPT_HMI, /* Hypervisor Maintainance interrupt */
2292 PPC_INTERRUPT_HDOORBELL, /* Hypervisor Doorbell interrupt */
47103572
JM		 2293};
2294
6d9412ea
AK		 2295/* Processor Compatibility mask (PCR) */
2296enum {
2297 PCR_COMPAT_2_05 = 1ull << (63-62),
2298 PCR_COMPAT_2_06 = 1ull << (63-61),
8cd2ce7a 2299 PCR_COMPAT_2_07 = 1ull << (63-60),
216c944e 2300 PCR_COMPAT_3_00 = 1ull << (63-59),
6d9412ea
AK		 2301 PCR_VEC_DIS = 1ull << (63-0), /* Vec. disable (bit NA since POWER8) */
2302 PCR_VSX_DIS = 1ull << (63-1), /* VSX disable (bit NA since POWER8) */
2303 PCR_TM_DIS = 1ull << (63-2), /* Trans. memory disable (POWER8) */
2304};
2305
1488270e
BH		 2306/* HMER/HMEER */
2307enum {
2308 HMER_MALFUNCTION_ALERT = 1ull << (63 - 0),
2309 HMER_PROC_RECV_DONE = 1ull << (63 - 2),
2310 HMER_PROC_RECV_ERROR_MASKED = 1ull << (63 - 3),
2311 HMER_TFAC_ERROR = 1ull << (63 - 4),
2312 HMER_TFMR_PARITY_ERROR = 1ull << (63 - 5),
2313 HMER_XSCOM_FAIL = 1ull << (63 - 8),
2314 HMER_XSCOM_DONE = 1ull << (63 - 9),
2315 HMER_PROC_RECV_AGAIN = 1ull << (63 - 11),
2316 HMER_WARN_RISE = 1ull << (63 - 14),
2317 HMER_WARN_FALL = 1ull << (63 - 15),
2318 HMER_SCOM_FIR_HMI = 1ull << (63 - 16),
2319 HMER_TRIG_FIR_HMI = 1ull << (63 - 17),
2320 HMER_HYP_RESOURCE_ERR = 1ull << (63 - 20),
2321 HMER_XSCOM_STATUS_MASK = 7ull << (63 - 23),
2322 HMER_XSCOM_STATUS_LSH = (63 - 23),
2323};
2324
5c94b2a5
CLG		 2325/* Alternate Interrupt Location (AIL) */
2326enum {
2327 AIL_NONE = 0,
2328 AIL_RESERVED = 1,
2329 AIL_0001_8000 = 2,
2330 AIL_C000_0000_0000_4000 = 3,
2331};
2332
9a64fbe4
FB		 2333/*****************************************************************************/
2334
00b70788
ND		 2335target_ulong cpu_read_xer(CPUPPCState *env);
2336void cpu_write_xer(CPUPPCState *env, target_ulong xer);
da91a00f 2337
1328c2bf 2338static inline void cpu_get_tb_cpu_state(CPUPPCState *env, target_ulong *pc,
89fee74a 2339 target_ulong *cs_base, uint32_t *flags)
6b917547
AL		 2340{
2341 *pc = env->nip;
2342 *cs_base = 0;
2343 *flags = env->hflags;
2344}
2345
db789c6c
BH		 2346void QEMU_NORETURN raise_exception(CPUPPCState *env, uint32_t exception);
2347void QEMU_NORETURN raise_exception_ra(CPUPPCState *env, uint32_t exception,
2348 uintptr_t raddr);
2349void QEMU_NORETURN raise_exception_err(CPUPPCState *env, uint32_t exception,
2350 uint32_t error_code);
2351void QEMU_NORETURN raise_exception_err_ra(CPUPPCState *env, uint32_t exception,
2352 uint32_t error_code, uintptr_t raddr);
2353
01662f3e 2354#if !defined(CONFIG_USER_ONLY)
1328c2bf 2355static inline int booke206_tlbm_id(CPUPPCState *env, ppcmas_tlb_t *tlbm)
01662f3e 2356{
d1e256fe 2357 uintptr_t tlbml = (uintptr_t)tlbm;
1c53accc 2358 uintptr_t tlbl = (uintptr_t)env->tlb.tlbm;
01662f3e 2359
1c53accc 2360 return (tlbml - tlbl) / sizeof(env->tlb.tlbm[0]);
01662f3e
AG		 2361}
2362
1328c2bf 2363static inline int booke206_tlb_size(CPUPPCState *env, int tlbn)
01662f3e
AG		 2364{
2365 uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2366 int r = tlbncfg & TLBnCFG_N_ENTRY;
2367 return r;
2368}
2369
1328c2bf 2370static inline int booke206_tlb_ways(CPUPPCState *env, int tlbn)
01662f3e
AG		 2371{
2372 uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2373 int r = tlbncfg >> TLBnCFG_ASSOC_SHIFT;
2374 return r;
2375}
2376
1328c2bf 2377static inline int booke206_tlbm_to_tlbn(CPUPPCState *env, ppcmas_tlb_t *tlbm)
01662f3e 2378{
d1e256fe 2379 int id = booke206_tlbm_id(env, tlbm);
01662f3e
AG		 2380 int end = 0;
2381 int i;
2382
2383 for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
2384 end += booke206_tlb_size(env, i);
2385 if (id < end) {
2386 return i;
2387 }
2388 }
2389
a47dddd7 2390 cpu_abort(CPU(ppc_env_get_cpu(env)), "Unknown TLBe: %d\n", id);
01662f3e
AG		 2391 return 0;
2392}
2393
1328c2bf 2394static inline int booke206_tlbm_to_way(CPUPPCState *env, ppcmas_tlb_t *tlb)
01662f3e 2395{
d1e256fe
AG		 2396 int tlbn = booke206_tlbm_to_tlbn(env, tlb);
2397 int tlbid = booke206_tlbm_id(env, tlb);
01662f3e
AG		 2398 return tlbid & (booke206_tlb_ways(env, tlbn) - 1);
2399}
2400
1328c2bf 2401static inline ppcmas_tlb_t *booke206_get_tlbm(CPUPPCState *env, const int tlbn,
01662f3e
AG		 2402 target_ulong ea, int way)
2403{
2404 int r;
2405 uint32_t ways = booke206_tlb_ways(env, tlbn);
786a4ea8
SH		 2406 int ways_bits = ctz32(ways);
2407 int tlb_bits = ctz32(booke206_tlb_size(env, tlbn));
01662f3e
AG		 2408 int i;
2409
2410 way &= ways - 1;
2411 ea >>= MAS2_EPN_SHIFT;
2412 ea &= (1 << (tlb_bits - ways_bits)) - 1;
2413 r = (ea << ways_bits) | way;
2414
3f162d11
AG		 2415 if (r >= booke206_tlb_size(env, tlbn)) {
2416 return NULL;
2417 }
2418
01662f3e
AG		 2419 /* bump up to tlbn index */
2420 for (i = 0; i < tlbn; i++) {
2421 r += booke206_tlb_size(env, i);
2422 }
2423
1c53accc 2424 return &env->tlb.tlbm[r];
01662f3e
AG		 2425}
2426
a1ef618a 2427/* returns bitmap of supported page sizes for a given TLB */
1328c2bf 2428static inline uint32_t booke206_tlbnps(CPUPPCState *env, const int tlbn)
a1ef618a
AG		 2429{
2430 bool mav2 = false;
2431 uint32_t ret = 0;
2432
2433 if (mav2) {
2434 ret = env->spr[SPR_BOOKE_TLB0PS + tlbn];
2435 } else {
2436 uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2437 uint32_t min = (tlbncfg & TLBnCFG_MINSIZE) >> TLBnCFG_MINSIZE_SHIFT;
2438 uint32_t max = (tlbncfg & TLBnCFG_MAXSIZE) >> TLBnCFG_MAXSIZE_SHIFT;
2439 int i;
2440 for (i = min; i <= max; i++) {
2441 ret |= (1 << (i << 1));
2442 }
2443 }
2444
2445 return ret;
2446}
2447
01662f3e
AG		 2448#endif
2449
e42a61f1
AG		 2450static inline bool msr_is_64bit(CPUPPCState *env, target_ulong msr)
2451{
2452 if (env->mmu_model == POWERPC_MMU_BOOKE206) {
2453 return msr & (1ULL << MSR_CM);
2454 }
2455
2456 return msr & (1ULL << MSR_SF);
2457}
2458
afbee712
TH		 2459/**
2460 * Check whether register rx is in the range between start and
2461 * start + nregs (as needed by the LSWX and LSWI instructions)
2462 */
2463static inline bool lsw_reg_in_range(int start, int nregs, int rx)
2464{
2465 return (start + nregs <= 32 && rx >= start && rx < start + nregs) ||
2466 (start + nregs > 32 && (rx >= start || rx < start + nregs - 32));
2467}
2468
1328c2bf 2469void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env);
bebabbc7 2470
0ce470cd
AK		 2471/**
2472 * ppc_get_vcpu_dt_id:
2473 * @cs: a PowerPCCPU struct.
2474 *
2475 * Returns a device-tree ID for a CPU.
2476 */
2477int ppc_get_vcpu_dt_id(PowerPCCPU *cpu);
2478
2479/**
2480 * ppc_get_vcpu_by_dt_id:
2481 * @cpu_dt_id: a device tree id
2482 *
2483 * Searches for a CPU by @cpu_dt_id.
2484 *
2485 * Returns: a PowerPCCPU struct
2486 */
2487PowerPCCPU *ppc_get_vcpu_by_dt_id(int cpu_dt_id);
2488
376dbce0 2489void ppc_maybe_bswap_register(CPUPPCState *env, uint8_t *mem_buf, int len);
07f5a258 2490#endif /* PPC_CPU_H */
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