[J-u-boot.git] / arch / powerpc / cpu / mpc83xx / speed.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * (C) Copyright 2000-2002
 * Wolfgang Denk, DENX Software Engineering, [email protected].
 *
 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
 */

#ifndef CONFIG_CLK_MPC83XX

#include <common.h>
#include <clock_legacy.h>
#include <mpc83xx.h>
#include <command.h>
#include <vsprintf.h>
#include <asm/global_data.h>
#include <asm/processor.h>

DECLARE_GLOBAL_DATA_PTR;

/* ----------------------------------------------------------------- */

typedef enum {
	_unk,
	_off,
	_byp,
	_x8,
	_x4,
	_x2,
	_x1,
	_1x,
	_1_5x,
	_2x,
	_2_5x,
	_3x
} mult_t;

typedef struct {
	mult_t core_csb_ratio;
	mult_t vco_divider;
} corecnf_t;

static corecnf_t corecnf_tab[] = {
	{_byp, _byp},		/* 0x00 */
	{_byp, _byp},		/* 0x01 */
	{_byp, _byp},		/* 0x02 */
	{_byp, _byp},		/* 0x03 */
	{_byp, _byp},		/* 0x04 */
	{_byp, _byp},		/* 0x05 */
	{_byp, _byp},		/* 0x06 */
	{_byp, _byp},		/* 0x07 */
	{_1x, _x2},		/* 0x08 */
	{_1x, _x4},		/* 0x09 */
	{_1x, _x8},		/* 0x0A */
	{_1x, _x8},		/* 0x0B */
	{_1_5x, _x2},		/* 0x0C */
	{_1_5x, _x4},		/* 0x0D */
	{_1_5x, _x8},		/* 0x0E */
	{_1_5x, _x8},		/* 0x0F */
	{_2x, _x2},		/* 0x10 */
	{_2x, _x4},		/* 0x11 */
	{_2x, _x8},		/* 0x12 */
	{_2x, _x8},		/* 0x13 */
	{_2_5x, _x2},		/* 0x14 */
	{_2_5x, _x4},		/* 0x15 */
	{_2_5x, _x8},		/* 0x16 */
	{_2_5x, _x8},		/* 0x17 */
	{_3x, _x2},		/* 0x18 */
	{_3x, _x4},		/* 0x19 */
	{_3x, _x8},		/* 0x1A */
	{_3x, _x8},		/* 0x1B */
};

/* ----------------------------------------------------------------- */

/*
 *
 */
int get_clocks(void)
{
	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
	u32 pci_sync_in;
	u8 spmf;
	u8 clkin_div;
	u32 sccr;
	u32 corecnf_tab_index;
	u8 corepll;
	u32 lcrr;

	u32 csb_clk;
#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
	defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
	u32 tsec1_clk;
	u32 tsec2_clk;
	u32 usbdr_clk;
#endif
#ifdef CONFIG_ARCH_MPC834X
	u32 usbmph_clk;
#endif
	u32 core_clk;
	u32 i2c1_clk;
#if !defined(CONFIG_ARCH_MPC832X)
	u32 i2c2_clk;
#endif
#if defined(CONFIG_FSL_ESDHC)
	u32 sdhc_clk;
#endif
	u32 enc_clk;
	u32 lbiu_clk;
	u32 lclk_clk;
	u32 mem_clk;
#if defined(CONFIG_ARCH_MPC8360)
	u32 mem_sec_clk;
#endif
#if defined(CONFIG_QE)
	u32 qepmf;
	u32 qepdf;
	u32 qe_clk;
	u32 brg_clk;
#endif
#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
	defined(CONFIG_ARCH_MPC837X)
	u32 pciexp1_clk;
	u32 pciexp2_clk;
#endif
#if defined(CONFIG_ARCH_MPC837X)
	u32 sata_clk;
#endif

	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
		return -1;

	clkin_div = ((im->clk.spmr & SPMR_CKID) >> SPMR_CKID_SHIFT);

	if (im->reset.rcwh & HRCWH_PCI_HOST) {
#if CONFIG_SYS_CLK_FREQ != 0
		pci_sync_in = get_board_sys_clk() / (1 + clkin_div);
#else
		pci_sync_in = 0xDEADBEEF;
#endif
	} else {
#if defined(CONFIG_83XX_PCICLK)
		pci_sync_in = CONFIG_83XX_PCICLK;
#else
		pci_sync_in = 0xDEADBEEF;
#endif
	}

	spmf = (im->clk.spmr & SPMR_SPMF) >> SPMR_SPMF_SHIFT;
	csb_clk = pci_sync_in * (1 + clkin_div) * spmf;

	sccr = im->clk.sccr;

#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
	defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
	switch ((sccr & SCCR_TSEC1CM) >> SCCR_TSEC1CM_SHIFT) {
	case 0:
		tsec1_clk = 0;
		break;
	case 1:
		tsec1_clk = csb_clk;
		break;
	case 2:
		tsec1_clk = csb_clk / 2;
		break;
	case 3:
		tsec1_clk = csb_clk / 3;
		break;
	default:
		/* unknown SCCR_TSEC1CM value */
		return -2;
	}
#endif

#if defined(CONFIG_ARCH_MPC830X) || defined(CONFIG_ARCH_MPC831X) || \
	defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
	switch ((sccr & SCCR_USBDRCM) >> SCCR_USBDRCM_SHIFT) {
	case 0:
		usbdr_clk = 0;
		break;
	case 1:
		usbdr_clk = csb_clk;
		break;
	case 2:
		usbdr_clk = csb_clk / 2;
		break;
	case 3:
		usbdr_clk = csb_clk / 3;
		break;
	default:
		/* unknown SCCR_USBDRCM value */
		return -3;
	}
#endif

#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC834X) || \
	defined(CONFIG_ARCH_MPC837X)
	switch ((sccr & SCCR_TSEC2CM) >> SCCR_TSEC2CM_SHIFT) {
	case 0:
		tsec2_clk = 0;
		break;
	case 1:
		tsec2_clk = csb_clk;
		break;
	case 2:
		tsec2_clk = csb_clk / 2;
		break;
	case 3:
		tsec2_clk = csb_clk / 3;
		break;
	default:
		/* unknown SCCR_TSEC2CM value */
		return -4;
	}
#elif defined(CONFIG_ARCH_MPC8313)
	tsec2_clk = tsec1_clk;

	if (!(sccr & SCCR_TSEC1ON))
		tsec1_clk = 0;
	if (!(sccr & SCCR_TSEC2ON))
		tsec2_clk = 0;
#endif

#if defined(CONFIG_ARCH_MPC834X)
	switch ((sccr & SCCR_USBMPHCM) >> SCCR_USBMPHCM_SHIFT) {
	case 0:
		usbmph_clk = 0;
		break;
	case 1:
		usbmph_clk = csb_clk;
		break;
	case 2:
		usbmph_clk = csb_clk / 2;
		break;
	case 3:
		usbmph_clk = csb_clk / 3;
		break;
	default:
		/* unknown SCCR_USBMPHCM value */
		return -5;
	}

	if (usbmph_clk != 0 && usbdr_clk != 0 && usbmph_clk != usbdr_clk) {
		/* if USB MPH clock is not disabled and
		 * USB DR clock is not disabled then
		 * USB MPH & USB DR must have the same rate
		 */
		return -6;
	}
#endif
	switch ((sccr & SCCR_ENCCM) >> SCCR_ENCCM_SHIFT) {
	case 0:
		enc_clk = 0;
		break;
	case 1:
		enc_clk = csb_clk;
		break;
	case 2:
		enc_clk = csb_clk / 2;
		break;
	case 3:
		enc_clk = csb_clk / 3;
		break;
	default:
		/* unknown SCCR_ENCCM value */
		return -7;
	}

#if defined(CONFIG_FSL_ESDHC)
	switch ((sccr & SCCR_SDHCCM) >> SCCR_SDHCCM_SHIFT) {
	case 0:
		sdhc_clk = 0;
		break;
	case 1:
		sdhc_clk = csb_clk;
		break;
	case 2:
		sdhc_clk = csb_clk / 2;
		break;
	case 3:
		sdhc_clk = csb_clk / 3;
		break;
	default:
		/* unknown SCCR_SDHCCM value */
		return -8;
	}
#endif

#if defined(CONFIG_ARCH_MPC834X)
	i2c1_clk = tsec2_clk;
#elif defined(CONFIG_ARCH_MPC8360)
	i2c1_clk = csb_clk;
#elif defined(CONFIG_ARCH_MPC832X)
	i2c1_clk = enc_clk;
#elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X)
	i2c1_clk = enc_clk;
#elif defined(CONFIG_FSL_ESDHC)
	i2c1_clk = sdhc_clk;
#elif defined(CONFIG_ARCH_MPC837X)
	i2c1_clk = enc_clk;
#endif
#if !defined(CONFIG_ARCH_MPC832X)
	i2c2_clk = csb_clk; /* i2c-2 clk is equal to csb clk */
#endif

#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
	defined(CONFIG_ARCH_MPC837X)
	switch ((sccr & SCCR_PCIEXP1CM) >> SCCR_PCIEXP1CM_SHIFT) {
	case 0:
		pciexp1_clk = 0;
		break;
	case 1:
		pciexp1_clk = csb_clk;
		break;
	case 2:
		pciexp1_clk = csb_clk / 2;
		break;
	case 3:
		pciexp1_clk = csb_clk / 3;
		break;
	default:
		/* unknown SCCR_PCIEXP1CM value */
		return -9;
	}

	switch ((sccr & SCCR_PCIEXP2CM) >> SCCR_PCIEXP2CM_SHIFT) {
	case 0:
		pciexp2_clk = 0;
		break;
	case 1:
		pciexp2_clk = csb_clk;
		break;
	case 2:
		pciexp2_clk = csb_clk / 2;
		break;
	case 3:
		pciexp2_clk = csb_clk / 3;
		break;
	default:
		/* unknown SCCR_PCIEXP2CM value */
		return -10;
	}
#endif

#if defined(CONFIG_ARCH_MPC837X)
	switch ((sccr & SCCR_SATA1CM) >> SCCR_SATA1CM_SHIFT) {
	case 0:
		sata_clk = 0;
		break;
	case 1:
		sata_clk = csb_clk;
		break;
	case 2:
		sata_clk = csb_clk / 2;
		break;
	case 3:
		sata_clk = csb_clk / 3;
		break;
	default:
		/* unknown SCCR_SATA1CM value */
		return -11;
	}
#endif

	lbiu_clk = csb_clk *
		   (1 + ((im->clk.spmr & SPMR_LBIUCM) >> SPMR_LBIUCM_SHIFT));
	lcrr = (im->im_lbc.lcrr & LCRR_CLKDIV) >> LCRR_CLKDIV_SHIFT;
	switch (lcrr) {
	case 2:
	case 4:
	case 8:
		lclk_clk = lbiu_clk / lcrr;
		break;
	default:
		/* unknown lcrr */
		return -12;
	}

	mem_clk = csb_clk *
		  (1 + ((im->clk.spmr & SPMR_DDRCM) >> SPMR_DDRCM_SHIFT));
	corepll = (im->clk.spmr & SPMR_COREPLL) >> SPMR_COREPLL_SHIFT;

#if defined(CONFIG_ARCH_MPC8360)
	mem_sec_clk = csb_clk * (1 +
		       ((im->clk.spmr & SPMR_LBIUCM) >> SPMR_LBIUCM_SHIFT));
#endif

	corecnf_tab_index = ((corepll & 0x1F) << 2) | ((corepll & 0x60) >> 5);
	if (corecnf_tab_index > (ARRAY_SIZE(corecnf_tab))) {
		/* corecnf_tab_index is too high, possibly wrong value */
		return -11;
	}
	switch (corecnf_tab[corecnf_tab_index].core_csb_ratio) {
	case _byp:
	case _x1:
	case _1x:
		core_clk = csb_clk;
		break;
	case _1_5x:
		core_clk = (3 * csb_clk) / 2;
		break;
	case _2x:
		core_clk = 2 * csb_clk;
		break;
	case _2_5x:
		core_clk = (5 * csb_clk) / 2;
		break;
	case _3x:
		core_clk = 3 * csb_clk;
		break;
	default:
		/* unknown core to csb ratio */
		return -13;
	}

#if defined(CONFIG_QE)
	qepmf = (im->clk.spmr & SPMR_CEPMF) >> SPMR_CEPMF_SHIFT;
	qepdf = (im->clk.spmr & SPMR_CEPDF) >> SPMR_CEPDF_SHIFT;
	qe_clk = (pci_sync_in * qepmf) / (1 + qepdf);
	brg_clk = qe_clk / 2;
#endif

	gd->arch.csb_clk = csb_clk;
#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
	defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
	gd->arch.tsec1_clk = tsec1_clk;
	gd->arch.tsec2_clk = tsec2_clk;
	gd->arch.usbdr_clk = usbdr_clk;
#endif
#if defined(CONFIG_ARCH_MPC834X)
	gd->arch.usbmph_clk = usbmph_clk;
#endif
#if defined(CONFIG_FSL_ESDHC)
	gd->arch.sdhc_clk = sdhc_clk;
#endif
	gd->arch.core_clk = core_clk;
	gd->arch.i2c1_clk = i2c1_clk;
#if !defined(CONFIG_ARCH_MPC832X)
	gd->arch.i2c2_clk = i2c2_clk;
#endif
	gd->arch.enc_clk = enc_clk;
	gd->arch.lbiu_clk = lbiu_clk;
	gd->arch.lclk_clk = lclk_clk;
	gd->mem_clk = mem_clk;
#if defined(CONFIG_ARCH_MPC8360)
	gd->arch.mem_sec_clk = mem_sec_clk;
#endif
#if defined(CONFIG_QE)
	gd->arch.qe_clk = qe_clk;
	gd->arch.brg_clk = brg_clk;
#endif
#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
	defined(CONFIG_ARCH_MPC837X)
	gd->arch.pciexp1_clk = pciexp1_clk;
	gd->arch.pciexp2_clk = pciexp2_clk;
#endif
#if defined(CONFIG_ARCH_MPC837X)
	gd->arch.sata_clk = sata_clk;
#endif
	gd->pci_clk = pci_sync_in;
	gd->cpu_clk = gd->arch.core_clk;
	gd->bus_clk = gd->arch.csb_clk;
	return 0;

}

/********************************************
 * get_bus_freq
 * return system bus freq in Hz
 *********************************************/
ulong get_bus_freq(ulong dummy)
{
	return gd->arch.csb_clk;
}

/********************************************
 * get_ddr_freq
 * return ddr bus freq in Hz
 *********************************************/
ulong get_ddr_freq(ulong dummy)
{
	return gd->mem_clk;
}

int get_serial_clock(void)
{
	return get_bus_freq(0);
}

static int do_clocks(struct cmd_tbl *cmdtp, int flag, int argc,
		     char *const argv[])
{
	char buf[32];

	printf("Clock configuration:\n");
	printf("  Core:                %-4s MHz\n",
	       strmhz(buf, gd->arch.core_clk));
	printf("  Coherent System Bus: %-4s MHz\n",
	       strmhz(buf, gd->arch.csb_clk));
#if defined(CONFIG_QE)
	printf("  QE:                  %-4s MHz\n",
	       strmhz(buf, gd->arch.qe_clk));
	printf("  BRG:                 %-4s MHz\n",
	       strmhz(buf, gd->arch.brg_clk));
#endif
	printf("  Local Bus Controller:%-4s MHz\n",
	       strmhz(buf, gd->arch.lbiu_clk));
	printf("  Local Bus:           %-4s MHz\n",
	       strmhz(buf, gd->arch.lclk_clk));
	printf("  DDR:                 %-4s MHz\n", strmhz(buf, gd->mem_clk));
#if defined(CONFIG_ARCH_MPC8360)
	printf("  DDR Secondary:       %-4s MHz\n",
	       strmhz(buf, gd->arch.mem_sec_clk));
#endif
	printf("  SEC:                 %-4s MHz\n",
	       strmhz(buf, gd->arch.enc_clk));
	printf("  I2C1:                %-4s MHz\n",
	       strmhz(buf, gd->arch.i2c1_clk));
#if !defined(CONFIG_ARCH_MPC832X)
	printf("  I2C2:                %-4s MHz\n",
	       strmhz(buf, gd->arch.i2c2_clk));
#endif
#if defined(CONFIG_FSL_ESDHC)
	printf("  SDHC:                %-4s MHz\n",
	       strmhz(buf, gd->arch.sdhc_clk));
#endif
#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
	defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
	printf("  TSEC1:               %-4s MHz\n",
	       strmhz(buf, gd->arch.tsec1_clk));
	printf("  TSEC2:               %-4s MHz\n",
	       strmhz(buf, gd->arch.tsec2_clk));
	printf("  USB DR:              %-4s MHz\n",
	       strmhz(buf, gd->arch.usbdr_clk));
#endif
#if defined(CONFIG_ARCH_MPC834X)
	printf("  USB MPH:             %-4s MHz\n",
	       strmhz(buf, gd->arch.usbmph_clk));
#endif
#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
	defined(CONFIG_ARCH_MPC837X)
	printf("  PCIEXP1:             %-4s MHz\n",
	       strmhz(buf, gd->arch.pciexp1_clk));
	printf("  PCIEXP2:             %-4s MHz\n",
	       strmhz(buf, gd->arch.pciexp2_clk));
#endif
#if defined(CONFIG_ARCH_MPC837X)
	printf("  SATA:                %-4s MHz\n",
	       strmhz(buf, gd->arch.sata_clk));
#endif
	return 0;
}

U_BOOT_CMD(clocks, 1, 0, do_clocks,
	"print clock configuration",
	"    clocks"
);

#endif
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
f046ccd1 EL	2	/*
	3	* (C) Copyright 2000-2002
	4	* Wolfgang Denk, DENX Software Engineering, [email protected].
	5	*
03051c3d	6	* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
f046ccd1 EL	7	*/
f046ccd1 EL	8
07d538d2 MS	9	#ifndef CONFIG_CLK_MPC83XX
07d538d2 MS	10
d678a59d	11	#include <common.h>
d96c2604	12	#include <clock_legacy.h>
f046ccd1	13	#include <mpc83xx.h>
54b2d434	14	#include <command.h>
2189d5f1	15	#include <vsprintf.h>
401d1c4f	16	#include <asm/global_data.h>
f046ccd1 EL	17	#include <asm/processor.h>
f046ccd1 EL	18
d87080b7 WD	19	DECLARE_GLOBAL_DATA_PTR;
d87080b7 WD	20
f046ccd1 EL	21	/* ----------------------------------------------------------------- */
	22
	23	typedef enum {
	24	_unk,
	25	_off,
	26	_byp,
	27	_x8,
	28	_x4,
	29	_x2,
	30	_x1,
	31	_1x,
	32	_1_5x,
	33	_2x,
	34	_2_5x,
	35	_3x
	36	} mult_t;
	37
	38	typedef struct {
	39	mult_t core_csb_ratio;
f7fb2e70	40	mult_t vco_divider;
f046ccd1 EL	41	} corecnf_t;
f046ccd1 EL	42
a2873bde	43	static corecnf_t corecnf_tab[] = {
f7fb2e70 KP	44	{_byp, _byp}, /* 0x00 */
	45	{_byp, _byp}, /* 0x01 */
	46	{_byp, _byp}, /* 0x02 */
	47	{_byp, _byp}, /* 0x03 */
	48	{_byp, _byp}, /* 0x04 */
	49	{_byp, _byp}, /* 0x05 */
	50	{_byp, _byp}, /* 0x06 */
	51	{_byp, _byp}, /* 0x07 */
	52	{_1x, _x2}, /* 0x08 */
	53	{_1x, _x4}, /* 0x09 */
	54	{_1x, _x8}, /* 0x0A */
	55	{_1x, _x8}, /* 0x0B */
	56	{_1_5x, _x2}, /* 0x0C */
	57	{_1_5x, _x4}, /* 0x0D */
	58	{_1_5x, _x8}, /* 0x0E */
	59	{_1_5x, _x8}, /* 0x0F */
	60	{_2x, _x2}, /* 0x10 */
	61	{_2x, _x4}, /* 0x11 */
	62	{_2x, _x8}, /* 0x12 */
	63	{_2x, _x8}, /* 0x13 */
	64	{_2_5x, _x2}, /* 0x14 */
	65	{_2_5x, _x4}, /* 0x15 */
	66	{_2_5x, _x8}, /* 0x16 */
	67	{_2_5x, _x8}, /* 0x17 */
	68	{_3x, _x2}, /* 0x18 */
	69	{_3x, _x4}, /* 0x19 */
	70	{_3x, _x8}, /* 0x1A */
	71	{_3x, _x8}, /* 0x1B */
f046ccd1 EL	72	};
	73
	74	/* ----------------------------------------------------------------- */
	75
	76	/*
	77	*
	78	*/
f7fb2e70	79	int get_clocks(void)
f046ccd1	80	{
6d0f6bcf	81	volatile immap_t im = (immap_t ) CONFIG_SYS_IMMR;
f046ccd1	82	u32 pci_sync_in;
f7fb2e70 KP	83	u8 spmf;
f7fb2e70 KP	84	u8 clkin_div;
f046ccd1 EL	85	u32 sccr;
f046ccd1 EL	86	u32 corecnf_tab_index;
f7fb2e70	87	u8 corepll;
f046ccd1	88	u32 lcrr;
de1d0a69	89
f046ccd1	90	u32 csb_clk;
9403fc41	91	#if defined(CONFIG_ARCH_MPC8308) \|\| defined(CONFIG_ARCH_MPC831X) \|\| \
8439e99d	92	defined(CONFIG_ARCH_MPC834X) \|\| defined(CONFIG_ARCH_MPC837X)
f046ccd1 EL	93	u32 tsec1_clk;
f046ccd1 EL	94	u32 tsec2_clk;
f046ccd1	95	u32 usbdr_clk;
7c98e519	96	#endif
d5cfa4aa	97	#ifdef CONFIG_ARCH_MPC834X
7c98e519	98	u32 usbmph_clk;
5f820439 DL	99	#endif
	100	u32 core_clk;
	101	u32 i2c1_clk;
bd3b867e	102	#if !defined(CONFIG_ARCH_MPC832X)
5f820439	103	u32 i2c2_clk;
03051c3d	104	#endif
27ef578d	105	#if defined(CONFIG_FSL_ESDHC)
03051c3d	106	u32 sdhc_clk;
24c3aca3	107	#endif
f046ccd1 EL	108	u32 enc_clk;
	109	u32 lbiu_clk;
	110	u32 lclk_clk;
35cf155c	111	u32 mem_clk;
61abced7	112	#if defined(CONFIG_ARCH_MPC8360)
35cf155c	113	u32 mem_sec_clk;
24c3aca3	114	#endif
4b5282de	115	#if defined(CONFIG_QE)
5f820439 DL	116	u32 qepmf;
5f820439 DL	117	u32 qepdf;
5f820439 DL	118	u32 qe_clk;
	119	u32 brg_clk;
	120	#endif
9403fc41	121	#if defined(CONFIG_ARCH_MPC8308) \|\| defined(CONFIG_ARCH_MPC831X) \|\| \
8439e99d	122	defined(CONFIG_ARCH_MPC837X)
03051c3d DL	123	u32 pciexp1_clk;
03051c3d DL	124	u32 pciexp2_clk;
555da617	125	#endif
139ff3be	126	#if defined(CONFIG_ARCH_MPC837X)
03051c3d DL	127	u32 sata_clk;
03051c3d DL	128	#endif
de1d0a69	129
f7fb2e70	130	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
f046ccd1	131	return -1;
de1d0a69	132
5f820439	133	clkin_div = ((im->clk.spmr & SPMR_CKID) >> SPMR_CKID_SHIFT);
e6f2e902	134
5f820439	135	if (im->reset.rcwh & HRCWH_PCI_HOST) {
2f8a6db5 TR	136	#if CONFIG_SYS_CLK_FREQ != 0
2f8a6db5 TR	137	pci_sync_in = get_board_sys_clk() / (1 + clkin_div);
5f820439 DL	138	#else
	139	pci_sync_in = 0xDEADBEEF;
	140	#endif
	141	} else {
	142	#if defined(CONFIG_83XX_PCICLK)
	143	pci_sync_in = CONFIG_83XX_PCICLK;
	144	#else
	145	pci_sync_in = 0xDEADBEEF;
	146	#endif
f046ccd1	147	}
f046ccd1	148
26e5f794	149	spmf = (im->clk.spmr & SPMR_SPMF) >> SPMR_SPMF_SHIFT;
5f820439	150	csb_clk = pci_sync_in * (1 + clkin_div) * spmf;
de1d0a69	151
f046ccd1	152	sccr = im->clk.sccr;
5f820439	153
9403fc41	154	#if defined(CONFIG_ARCH_MPC8308) \|\| defined(CONFIG_ARCH_MPC831X) \|\| \
8439e99d	155	defined(CONFIG_ARCH_MPC834X) \|\| defined(CONFIG_ARCH_MPC837X)
f046ccd1 EL	156	switch ((sccr & SCCR_TSEC1CM) >> SCCR_TSEC1CM_SHIFT) {
	157	case 0:
	158	tsec1_clk = 0;
	159	break;
	160	case 1:
	161	tsec1_clk = csb_clk;
	162	break;
	163	case 2:
	164	tsec1_clk = csb_clk / 2;
	165	break;
	166	case 3:
	167	tsec1_clk = csb_clk / 3;
	168	break;
	169	default:
d7b4ca2b	170	/* unknown SCCR_TSEC1CM value */
03051c3d	171	return -2;
f046ccd1	172	}
8afad91f	173	#endif
de1d0a69	174
9403fc41	175	#if defined(CONFIG_ARCH_MPC830X) \|\| defined(CONFIG_ARCH_MPC831X) \|\| \
8439e99d	176	defined(CONFIG_ARCH_MPC834X) \|\| defined(CONFIG_ARCH_MPC837X)
7c98e519 SW	177	switch ((sccr & SCCR_USBDRCM) >> SCCR_USBDRCM_SHIFT) {
	178	case 0:
	179	usbdr_clk = 0;
	180	break;
	181	case 1:
	182	usbdr_clk = csb_clk;
	183	break;
	184	case 2:
	185	usbdr_clk = csb_clk / 2;
	186	break;
	187	case 3:
	188	usbdr_clk = csb_clk / 3;
	189	break;
	190	default:
d7b4ca2b	191	/* unknown SCCR_USBDRCM value */
03051c3d	192	return -3;
7c98e519 SW	193	}
	194	#endif
	195
139ff3be TR	196	#if defined(CONFIG_ARCH_MPC8308) \|\| defined(CONFIG_ARCH_MPC834X) \|\| \
139ff3be TR	197	defined(CONFIG_ARCH_MPC837X)
f046ccd1 EL	198	switch ((sccr & SCCR_TSEC2CM) >> SCCR_TSEC2CM_SHIFT) {
	199	case 0:
	200	tsec2_clk = 0;
	201	break;
	202	case 1:
	203	tsec2_clk = csb_clk;
	204	break;
	205	case 2:
	206	tsec2_clk = csb_clk / 2;
	207	break;
	208	case 3:
	209	tsec2_clk = csb_clk / 3;
	210	break;
	211	default:
d7b4ca2b	212	/* unknown SCCR_TSEC2CM value */
03051c3d	213	return -4;
f046ccd1	214	}
9403fc41	215	#elif defined(CONFIG_ARCH_MPC8313)
03051c3d	216	tsec2_clk = tsec1_clk;
de1d0a69	217
03051c3d DL	218	if (!(sccr & SCCR_TSEC1ON))
	219	tsec1_clk = 0;
	220	if (!(sccr & SCCR_TSEC2ON))
	221	tsec2_clk = 0;
	222	#endif
de1d0a69	223
d5cfa4aa	224	#if defined(CONFIG_ARCH_MPC834X)
f046ccd1 EL	225	switch ((sccr & SCCR_USBMPHCM) >> SCCR_USBMPHCM_SHIFT) {
	226	case 0:
	227	usbmph_clk = 0;
	228	break;
	229	case 1:
	230	usbmph_clk = csb_clk;
	231	break;
	232	case 2:
	233	usbmph_clk = csb_clk / 2;
	234	break;
	235	case 3:
	236	usbmph_clk = csb_clk / 3;
	237	break;
	238	default:
d7b4ca2b	239	/* unknown SCCR_USBMPHCM value */
03051c3d	240	return -5;
f046ccd1 EL	241	}
f046ccd1 EL	242
f7fb2e70 KP	243	if (usbmph_clk != 0 && usbdr_clk != 0 && usbmph_clk != usbdr_clk) {
	244	/* if USB MPH clock is not disabled and
	245	* USB DR clock is not disabled then
	246	* USB MPH & USB DR must have the same rate
	247	*/
03051c3d DL	248	return -6;
	249	}
	250	#endif
	251	switch ((sccr & SCCR_ENCCM) >> SCCR_ENCCM_SHIFT) {
	252	case 0:
	253	enc_clk = 0;
	254	break;
	255	case 1:
	256	enc_clk = csb_clk;
	257	break;
	258	case 2:
	259	enc_clk = csb_clk / 2;
	260	break;
	261	case 3:
	262	enc_clk = csb_clk / 3;
	263	break;
	264	default:
d7b4ca2b	265	/* unknown SCCR_ENCCM value */
03051c3d	266	return -7;
f046ccd1	267	}
7c98e519	268
27ef578d	269	#if defined(CONFIG_FSL_ESDHC)
03051c3d DL	270	switch ((sccr & SCCR_SDHCCM) >> SCCR_SDHCCM_SHIFT) {
	271	case 0:
	272	sdhc_clk = 0;
	273	break;
	274	case 1:
	275	sdhc_clk = csb_clk;
	276	break;
	277	case 2:
	278	sdhc_clk = csb_clk / 2;
	279	break;
	280	case 3:
	281	sdhc_clk = csb_clk / 3;
	282	break;
	283	default:
d7b4ca2b	284	/* unknown SCCR_SDHCCM value */
03051c3d DL	285	return -8;
03051c3d DL	286	}
5f820439	287	#endif
7c98e519	288
d5cfa4aa	289	#if defined(CONFIG_ARCH_MPC834X)
03051c3d	290	i2c1_clk = tsec2_clk;
61abced7	291	#elif defined(CONFIG_ARCH_MPC8360)
5f820439	292	i2c1_clk = csb_clk;
bd3b867e	293	#elif defined(CONFIG_ARCH_MPC832X)
03051c3d	294	i2c1_clk = enc_clk;
9403fc41	295	#elif defined(CONFIG_ARCH_MPC8308) \|\| defined(CONFIG_ARCH_MPC831X)
03051c3d	296	i2c1_clk = enc_clk;
27ef578d	297	#elif defined(CONFIG_FSL_ESDHC)
03051c3d	298	i2c1_clk = sdhc_clk;
8439e99d	299	#elif defined(CONFIG_ARCH_MPC837X)
1bda1624	300	i2c1_clk = enc_clk;
5f820439	301	#endif
bd3b867e	302	#if !defined(CONFIG_ARCH_MPC832X)
03051c3d	303	i2c2_clk = csb_clk; /* i2c-2 clk is equal to csb clk */
24c3aca3	304	#endif
de1d0a69	305
9403fc41	306	#if defined(CONFIG_ARCH_MPC8308) \|\| defined(CONFIG_ARCH_MPC831X) \|\| \
8439e99d	307	defined(CONFIG_ARCH_MPC837X)
03051c3d	308	switch ((sccr & SCCR_PCIEXP1CM) >> SCCR_PCIEXP1CM_SHIFT) {
5f820439	309	case 0:
03051c3d	310	pciexp1_clk = 0;
5f820439 DL	311	break;
5f820439 DL	312	case 1:
03051c3d	313	pciexp1_clk = csb_clk;
5f820439 DL	314	break;
5f820439 DL	315	case 2:
03051c3d	316	pciexp1_clk = csb_clk / 2;
5f820439 DL	317	break;
5f820439 DL	318	case 3:
03051c3d	319	pciexp1_clk = csb_clk / 3;
5f820439 DL	320	break;
5f820439 DL	321	default:
d7b4ca2b	322	/* unknown SCCR_PCIEXP1CM value */
03051c3d	323	return -9;
5f820439	324	}
24c3aca3	325
03051c3d DL	326	switch ((sccr & SCCR_PCIEXP2CM) >> SCCR_PCIEXP2CM_SHIFT) {
	327	case 0:
	328	pciexp2_clk = 0;
	329	break;
	330	case 1:
	331	pciexp2_clk = csb_clk;
	332	break;
	333	case 2:
	334	pciexp2_clk = csb_clk / 2;
	335	break;
	336	case 3:
	337	pciexp2_clk = csb_clk / 3;
	338	break;
	339	default:
d7b4ca2b	340	/* unknown SCCR_PCIEXP2CM value */
03051c3d DL	341	return -10;
	342	}
	343	#endif
	344
139ff3be	345	#if defined(CONFIG_ARCH_MPC837X)
a8cb43a8 DL	346	switch ((sccr & SCCR_SATA1CM) >> SCCR_SATA1CM_SHIFT) {
a8cb43a8 DL	347	case 0:
03051c3d DL	348	sata_clk = 0;
03051c3d DL	349	break;
a8cb43a8	350	case 1:
03051c3d DL	351	sata_clk = csb_clk;
03051c3d DL	352	break;
a8cb43a8	353	case 2:
03051c3d DL	354	sata_clk = csb_clk / 2;
03051c3d DL	355	break;
a8cb43a8	356	case 3:
03051c3d DL	357	sata_clk = csb_clk / 3;
	358	break;
	359	default:
d7b4ca2b	360	/* unknown SCCR_SATA1CM value */
03051c3d DL	361	return -11;
	362	}
	363	#endif
	364
f7fb2e70	365	lbiu_clk = csb_clk *
26e5f794	366	(1 + ((im->clk.spmr & SPMR_LBIUCM) >> SPMR_LBIUCM_SHIFT));
f51cdaf1	367	lcrr = (im->im_lbc.lcrr & LCRR_CLKDIV) >> LCRR_CLKDIV_SHIFT;
f046ccd1 EL	368	switch (lcrr) {
	369	case 2:
	370	case 4:
	371	case 8:
	372	lclk_clk = lbiu_clk / lcrr;
	373	break;
	374	default:
	375	/* unknown lcrr */
03051c3d	376	return -12;
f046ccd1	377	}
24c3aca3	378
35cf155c	379	mem_clk = csb_clk *
26e5f794 JT	380	(1 + ((im->clk.spmr & SPMR_DDRCM) >> SPMR_DDRCM_SHIFT));
	381	corepll = (im->clk.spmr & SPMR_COREPLL) >> SPMR_COREPLL_SHIFT;
	382
61abced7	383	#if defined(CONFIG_ARCH_MPC8360)
35cf155c	384	mem_sec_clk = csb_clk * (1 +
26e5f794	385	((im->clk.spmr & SPMR_LBIUCM) >> SPMR_LBIUCM_SHIFT));
5f820439 DL	386	#endif
5f820439 DL	387
f046ccd1	388	corecnf_tab_index = ((corepll & 0x1F) << 2) \| ((corepll & 0x60) >> 5);
b7707b04	389	if (corecnf_tab_index > (ARRAY_SIZE(corecnf_tab))) {
d7b4ca2b	390	/* corecnf_tab_index is too high, possibly wrong value */
f046ccd1 EL	391	return -11;
	392	}
	393	switch (corecnf_tab[corecnf_tab_index].core_csb_ratio) {
	394	case _byp:
	395	case _x1:
	396	case _1x:
	397	core_clk = csb_clk;
	398	break;
	399	case _1_5x:
	400	core_clk = (3 * csb_clk) / 2;
	401	break;
	402	case _2x:
	403	core_clk = 2 * csb_clk;
	404	break;
	405	case _2_5x:
f7fb2e70	406	core_clk = (5 * csb_clk) / 2;
f046ccd1 EL	407	break;
	408	case _3x:
	409	core_clk = 3 * csb_clk;
	410	break;
	411	default:
d7b4ca2b	412	/* unknown core to csb ratio */
03051c3d	413	return -13;
f046ccd1	414	}
de1d0a69	415
4b5282de	416	#if defined(CONFIG_QE)
26e5f794 JT	417	qepmf = (im->clk.spmr & SPMR_CEPMF) >> SPMR_CEPMF_SHIFT;
26e5f794 JT	418	qepdf = (im->clk.spmr & SPMR_CEPDF) >> SPMR_CEPDF_SHIFT;
f7fb2e70	419	qe_clk = (pci_sync_in * qepmf) / (1 + qepdf);
5f820439 DL	420	brg_clk = qe_clk / 2;
	421	#endif
	422
c6731fe2	423	gd->arch.csb_clk = csb_clk;
9403fc41	424	#if defined(CONFIG_ARCH_MPC8308) \|\| defined(CONFIG_ARCH_MPC831X) \|\| \
8439e99d	425	defined(CONFIG_ARCH_MPC834X) \|\| defined(CONFIG_ARCH_MPC837X)
c6731fe2 SG	426	gd->arch.tsec1_clk = tsec1_clk;
	427	gd->arch.tsec2_clk = tsec2_clk;
	428	gd->arch.usbdr_clk = usbdr_clk;
7c98e519	429	#endif
d5cfa4aa	430	#if defined(CONFIG_ARCH_MPC834X)
c6731fe2	431	gd->arch.usbmph_clk = usbmph_clk;
03051c3d	432	#endif
27ef578d	433	#if defined(CONFIG_FSL_ESDHC)
e9adeca3	434	gd->arch.sdhc_clk = sdhc_clk;
5f820439	435	#endif
c6731fe2	436	gd->arch.core_clk = core_clk;
609e6ec3	437	gd->arch.i2c1_clk = i2c1_clk;
bd3b867e	438	#if !defined(CONFIG_ARCH_MPC832X)
609e6ec3	439	gd->arch.i2c2_clk = i2c2_clk;
24c3aca3	440	#endif
c6731fe2	441	gd->arch.enc_clk = enc_clk;
c6731fe2 SG	442	gd->arch.lbiu_clk = lbiu_clk;
c6731fe2 SG	443	gd->arch.lclk_clk = lclk_clk;
35cf155c	444	gd->mem_clk = mem_clk;
61abced7	445	#if defined(CONFIG_ARCH_MPC8360)
c6731fe2	446	gd->arch.mem_sec_clk = mem_sec_clk;
24c3aca3	447	#endif
4b5282de	448	#if defined(CONFIG_QE)
45bae2e3	449	gd->arch.qe_clk = qe_clk;
1206c184	450	gd->arch.brg_clk = brg_clk;
03051c3d	451	#endif
9403fc41	452	#if defined(CONFIG_ARCH_MPC8308) \|\| defined(CONFIG_ARCH_MPC831X) \|\| \
8439e99d	453	defined(CONFIG_ARCH_MPC837X)
c6731fe2 SG	454	gd->arch.pciexp1_clk = pciexp1_clk;
c6731fe2 SG	455	gd->arch.pciexp2_clk = pciexp2_clk;
555da617	456	#endif
139ff3be	457	#if defined(CONFIG_ARCH_MPC837X)
c6731fe2	458	gd->arch.sata_clk = sata_clk;
5f820439	459	#endif
8f9e0e9f	460	gd->pci_clk = pci_sync_in;
c6731fe2 SG	461	gd->cpu_clk = gd->arch.core_clk;
c6731fe2 SG	462	gd->bus_clk = gd->arch.csb_clk;
f046ccd1	463	return 0;
5f820439	464
f046ccd1 EL	465	}
	466
	467	/********************************************
	468	* get_bus_freq
	469	* return system bus freq in Hz
	470	*********************************************/
f7fb2e70	471	ulong get_bus_freq(ulong dummy)
f046ccd1	472	{
c6731fe2	473	return gd->arch.csb_clk;
f046ccd1 EL	474	}
f046ccd1 EL	475
d29d17d7 YS	476	/********************************************
	477	* get_ddr_freq
	478	* return ddr bus freq in Hz
	479	*********************************************/
	480	ulong get_ddr_freq(ulong dummy)
	481	{
	482	return gd->mem_clk;
	483	}
	484
ac016c94 MS	485	int get_serial_clock(void)
	486	{
	487	return get_bus_freq(0);
	488	}
	489
09140113 SG	490	static int do_clocks(struct cmd_tbl *cmdtp, int flag, int argc,
09140113 SG	491	char *const argv[])
f046ccd1	492	{
08ef89ec WD	493	char buf[32];
08ef89ec WD	494
f046ccd1	495	printf("Clock configuration:\n");
c6731fe2 SG	496	printf(" Core: %-4s MHz\n",
	497	strmhz(buf, gd->arch.core_clk));
	498	printf(" Coherent System Bus: %-4s MHz\n",
	499	strmhz(buf, gd->arch.csb_clk));
4b5282de	500	#if defined(CONFIG_QE)
45bae2e3 SG	501	printf(" QE: %-4s MHz\n",
45bae2e3 SG	502	strmhz(buf, gd->arch.qe_clk));
1206c184 SG	503	printf(" BRG: %-4s MHz\n",
1206c184 SG	504	strmhz(buf, gd->arch.brg_clk));
5f820439	505	#endif
c6731fe2 SG	506	printf(" Local Bus Controller:%-4s MHz\n",
	507	strmhz(buf, gd->arch.lbiu_clk));
	508	printf(" Local Bus: %-4s MHz\n",
	509	strmhz(buf, gd->arch.lclk_clk));
08ef89ec	510	printf(" DDR: %-4s MHz\n", strmhz(buf, gd->mem_clk));
61abced7	511	#if defined(CONFIG_ARCH_MPC8360)
c6731fe2 SG	512	printf(" DDR Secondary: %-4s MHz\n",
c6731fe2 SG	513	strmhz(buf, gd->arch.mem_sec_clk));
5f820439	514	#endif
c6731fe2 SG	515	printf(" SEC: %-4s MHz\n",
c6731fe2 SG	516	strmhz(buf, gd->arch.enc_clk));
609e6ec3 SG	517	printf(" I2C1: %-4s MHz\n",
609e6ec3 SG	518	strmhz(buf, gd->arch.i2c1_clk));
bd3b867e	519	#if !defined(CONFIG_ARCH_MPC832X)
609e6ec3 SG	520	printf(" I2C2: %-4s MHz\n",
609e6ec3 SG	521	strmhz(buf, gd->arch.i2c2_clk));
24c3aca3	522	#endif
27ef578d	523	#if defined(CONFIG_FSL_ESDHC)
e9adeca3 SG	524	printf(" SDHC: %-4s MHz\n",
e9adeca3 SG	525	strmhz(buf, gd->arch.sdhc_clk));
03051c3d	526	#endif
9403fc41	527	#if defined(CONFIG_ARCH_MPC8308) \|\| defined(CONFIG_ARCH_MPC831X) \|\| \
8439e99d	528	defined(CONFIG_ARCH_MPC834X) \|\| defined(CONFIG_ARCH_MPC837X)
c6731fe2 SG	529	printf(" TSEC1: %-4s MHz\n",
	530	strmhz(buf, gd->arch.tsec1_clk));
	531	printf(" TSEC2: %-4s MHz\n",
	532	strmhz(buf, gd->arch.tsec2_clk));
	533	printf(" USB DR: %-4s MHz\n",
	534	strmhz(buf, gd->arch.usbdr_clk));
7c98e519	535	#endif
d5cfa4aa	536	#if defined(CONFIG_ARCH_MPC834X)
c6731fe2 SG	537	printf(" USB MPH: %-4s MHz\n",
c6731fe2 SG	538	strmhz(buf, gd->arch.usbmph_clk));
03051c3d	539	#endif
9403fc41	540	#if defined(CONFIG_ARCH_MPC8308) \|\| defined(CONFIG_ARCH_MPC831X) \|\| \
8439e99d	541	defined(CONFIG_ARCH_MPC837X)
c6731fe2 SG	542	printf(" PCIEXP1: %-4s MHz\n",
	543	strmhz(buf, gd->arch.pciexp1_clk));
	544	printf(" PCIEXP2: %-4s MHz\n",
	545	strmhz(buf, gd->arch.pciexp2_clk));
555da617	546	#endif
139ff3be	547	#if defined(CONFIG_ARCH_MPC837X)
c6731fe2 SG	548	printf(" SATA: %-4s MHz\n",
c6731fe2 SG	549	strmhz(buf, gd->arch.sata_clk));
5f820439	550	#endif
de1d0a69	551	return 0;
f046ccd1	552	}
54b2d434 KP	553
54b2d434 KP	554	U_BOOT_CMD(clocks, 1, 0, do_clocks,
2fb2604d	555	"print clock configuration",
a89c33db	556	" clocks"
54b2d434	557	);
07d538d2 MS	558
07d538d2 MS	559	#endif