[J-u-boot.git] / arch / powerpc / cpu / mpc83xx / speed.c

/*
 * (C) Copyright 2000-2002
 * Wolfgang Denk, DENX Software Engineering, [email protected].
 *
 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <mpc83xx.h>
#include <command.h>
#include <asm/processor.h>

DECLARE_GLOBAL_DATA_PTR;

/* ----------------------------------------------------------------- */

typedef enum {
	_unk,
	_off,
	_byp,
	_x8,
	_x4,
	_x2,
	_x1,
	_1x,
	_1_5x,
	_2x,
	_2_5x,
	_3x
} mult_t;

typedef struct {
	mult_t core_csb_ratio;
	mult_t vco_divider;
} corecnf_t;

corecnf_t corecnf_tab[] = {
	{_byp, _byp},		/* 0x00 */
	{_byp, _byp},		/* 0x01 */
	{_byp, _byp},		/* 0x02 */
	{_byp, _byp},		/* 0x03 */
	{_byp, _byp},		/* 0x04 */
	{_byp, _byp},		/* 0x05 */
	{_byp, _byp},		/* 0x06 */
	{_byp, _byp},		/* 0x07 */
	{_1x, _x2},		/* 0x08 */
	{_1x, _x4},		/* 0x09 */
	{_1x, _x8},		/* 0x0A */
	{_1x, _x8},		/* 0x0B */
	{_1_5x, _x2},		/* 0x0C */
	{_1_5x, _x4},		/* 0x0D */
	{_1_5x, _x8},		/* 0x0E */
	{_1_5x, _x8},		/* 0x0F */
	{_2x, _x2},		/* 0x10 */
	{_2x, _x4},		/* 0x11 */
	{_2x, _x8},		/* 0x12 */
	{_2x, _x8},		/* 0x13 */
	{_2_5x, _x2},		/* 0x14 */
	{_2_5x, _x4},		/* 0x15 */
	{_2_5x, _x8},		/* 0x16 */
	{_2_5x, _x8},		/* 0x17 */
	{_3x, _x2},		/* 0x18 */
	{_3x, _x4},		/* 0x19 */
	{_3x, _x8},		/* 0x1A */
	{_3x, _x8},		/* 0x1B */
};

/* ----------------------------------------------------------------- */

/*
 *
 */
int get_clocks(void)
{
	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
	u32 pci_sync_in;
	u8 spmf;
	u8 clkin_div;
	u32 sccr;
	u32 corecnf_tab_index;
	u8 corepll;
	u32 lcrr;

	u32 csb_clk;
#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
	defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
	u32 tsec1_clk;
	u32 tsec2_clk;
	u32 usbdr_clk;
#elif defined(CONFIG_MPC8309)
	u32 usbdr_clk;
#endif
#ifdef CONFIG_MPC834x
	u32 usbmph_clk;
#endif
	u32 core_clk;
	u32 i2c1_clk;
#if !defined(CONFIG_MPC832x)
	u32 i2c2_clk;
#endif
#if defined(CONFIG_MPC8315)
	u32 tdm_clk;
#endif
#if defined(CONFIG_FSL_ESDHC)
	u32 sdhc_clk;
#endif
#if !defined(CONFIG_MPC8309)
	u32 enc_clk;
#endif
	u32 lbiu_clk;
	u32 lclk_clk;
	u32 mem_clk;
#if defined(CONFIG_MPC8360)
	u32 mem_sec_clk;
#endif
#if defined(CONFIG_QE)
	u32 qepmf;
	u32 qepdf;
	u32 qe_clk;
	u32 brg_clk;
#endif
#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
	defined(CONFIG_MPC837x)
	u32 pciexp1_clk;
	u32 pciexp2_clk;
#endif
#if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315)
	u32 sata_clk;
#endif

	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
		return -1;

	clkin_div = ((im->clk.spmr & SPMR_CKID) >> SPMR_CKID_SHIFT);

	if (im->reset.rcwh & HRCWH_PCI_HOST) {
#if defined(CONFIG_83XX_CLKIN)
		pci_sync_in = CONFIG_83XX_CLKIN / (1 + clkin_div);
#else
		pci_sync_in = 0xDEADBEEF;
#endif
	} else {
#if defined(CONFIG_83XX_PCICLK)
		pci_sync_in = CONFIG_83XX_PCICLK;
#else
		pci_sync_in = 0xDEADBEEF;
#endif
	}

	spmf = (im->clk.spmr & SPMR_SPMF) >> SPMR_SPMF_SHIFT;
	csb_clk = pci_sync_in * (1 + clkin_div) * spmf;

	sccr = im->clk.sccr;

#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
	defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
	switch ((sccr & SCCR_TSEC1CM) >> SCCR_TSEC1CM_SHIFT) {
	case 0:
		tsec1_clk = 0;
		break;
	case 1:
		tsec1_clk = csb_clk;
		break;
	case 2:
		tsec1_clk = csb_clk / 2;
		break;
	case 3:
		tsec1_clk = csb_clk / 3;
		break;
	default:
		/* unkown SCCR_TSEC1CM value */
		return -2;
	}
#endif

#if defined(CONFIG_MPC830x) || defined(CONFIG_MPC831x) || \
	defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
	switch ((sccr & SCCR_USBDRCM) >> SCCR_USBDRCM_SHIFT) {
	case 0:
		usbdr_clk = 0;
		break;
	case 1:
		usbdr_clk = csb_clk;
		break;
	case 2:
		usbdr_clk = csb_clk / 2;
		break;
	case 3:
		usbdr_clk = csb_clk / 3;
		break;
	default:
		/* unkown SCCR_USBDRCM value */
		return -3;
	}
#endif

#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC8315) || \
	defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
	switch ((sccr & SCCR_TSEC2CM) >> SCCR_TSEC2CM_SHIFT) {
	case 0:
		tsec2_clk = 0;
		break;
	case 1:
		tsec2_clk = csb_clk;
		break;
	case 2:
		tsec2_clk = csb_clk / 2;
		break;
	case 3:
		tsec2_clk = csb_clk / 3;
		break;
	default:
		/* unkown SCCR_TSEC2CM value */
		return -4;
	}
#elif defined(CONFIG_MPC8313)
	tsec2_clk = tsec1_clk;

	if (!(sccr & SCCR_TSEC1ON))
		tsec1_clk = 0;
	if (!(sccr & SCCR_TSEC2ON))
		tsec2_clk = 0;
#endif

#if defined(CONFIG_MPC834x)
	switch ((sccr & SCCR_USBMPHCM) >> SCCR_USBMPHCM_SHIFT) {
	case 0:
		usbmph_clk = 0;
		break;
	case 1:
		usbmph_clk = csb_clk;
		break;
	case 2:
		usbmph_clk = csb_clk / 2;
		break;
	case 3:
		usbmph_clk = csb_clk / 3;
		break;
	default:
		/* unkown SCCR_USBMPHCM value */
		return -5;
	}

	if (usbmph_clk != 0 && usbdr_clk != 0 && usbmph_clk != usbdr_clk) {
		/* if USB MPH clock is not disabled and
		 * USB DR clock is not disabled then
		 * USB MPH & USB DR must have the same rate
		 */
		return -6;
	}
#endif
#if !defined(CONFIG_MPC8309)
	switch ((sccr & SCCR_ENCCM) >> SCCR_ENCCM_SHIFT) {
	case 0:
		enc_clk = 0;
		break;
	case 1:
		enc_clk = csb_clk;
		break;
	case 2:
		enc_clk = csb_clk / 2;
		break;
	case 3:
		enc_clk = csb_clk / 3;
		break;
	default:
		/* unkown SCCR_ENCCM value */
		return -7;
	}
#endif

#if defined(CONFIG_FSL_ESDHC)
	switch ((sccr & SCCR_SDHCCM) >> SCCR_SDHCCM_SHIFT) {
	case 0:
		sdhc_clk = 0;
		break;
	case 1:
		sdhc_clk = csb_clk;
		break;
	case 2:
		sdhc_clk = csb_clk / 2;
		break;
	case 3:
		sdhc_clk = csb_clk / 3;
		break;
	default:
		/* unkown SCCR_SDHCCM value */
		return -8;
	}
#endif
#if defined(CONFIG_MPC8315)
	switch ((sccr & SCCR_TDMCM) >> SCCR_TDMCM_SHIFT) {
	case 0:
		tdm_clk = 0;
		break;
	case 1:
		tdm_clk = csb_clk;
		break;
	case 2:
		tdm_clk = csb_clk / 2;
		break;
	case 3:
		tdm_clk = csb_clk / 3;
		break;
	default:
		/* unkown SCCR_TDMCM value */
		return -8;
	}
#endif

#if defined(CONFIG_MPC834x)
	i2c1_clk = tsec2_clk;
#elif defined(CONFIG_MPC8360)
	i2c1_clk = csb_clk;
#elif defined(CONFIG_MPC832x)
	i2c1_clk = enc_clk;
#elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x)
	i2c1_clk = enc_clk;
#elif defined(CONFIG_FSL_ESDHC)
	i2c1_clk = sdhc_clk;
#elif defined(CONFIG_MPC837x)
	i2c1_clk = enc_clk;
#elif defined(CONFIG_MPC8309)
	i2c1_clk = csb_clk;
#endif
#if !defined(CONFIG_MPC832x)
	i2c2_clk = csb_clk; /* i2c-2 clk is equal to csb clk */
#endif

#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
	defined(CONFIG_MPC837x)
	switch ((sccr & SCCR_PCIEXP1CM) >> SCCR_PCIEXP1CM_SHIFT) {
	case 0:
		pciexp1_clk = 0;
		break;
	case 1:
		pciexp1_clk = csb_clk;
		break;
	case 2:
		pciexp1_clk = csb_clk / 2;
		break;
	case 3:
		pciexp1_clk = csb_clk / 3;
		break;
	default:
		/* unkown SCCR_PCIEXP1CM value */
		return -9;
	}

	switch ((sccr & SCCR_PCIEXP2CM) >> SCCR_PCIEXP2CM_SHIFT) {
	case 0:
		pciexp2_clk = 0;
		break;
	case 1:
		pciexp2_clk = csb_clk;
		break;
	case 2:
		pciexp2_clk = csb_clk / 2;
		break;
	case 3:
		pciexp2_clk = csb_clk / 3;
		break;
	default:
		/* unkown SCCR_PCIEXP2CM value */
		return -10;
	}
#endif

#if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315)
	switch ((sccr & SCCR_SATA1CM) >> SCCR_SATA1CM_SHIFT) {
	case 0:
		sata_clk = 0;
		break;
	case 1:
		sata_clk = csb_clk;
		break;
	case 2:
		sata_clk = csb_clk / 2;
		break;
	case 3:
		sata_clk = csb_clk / 3;
		break;
	default:
		/* unkown SCCR_SATACM value */
		return -11;
	}
#endif

	lbiu_clk = csb_clk *
		   (1 + ((im->clk.spmr & SPMR_LBIUCM) >> SPMR_LBIUCM_SHIFT));
	lcrr = (im->im_lbc.lcrr & LCRR_CLKDIV) >> LCRR_CLKDIV_SHIFT;
	switch (lcrr) {
	case 2:
	case 4:
	case 8:
		lclk_clk = lbiu_clk / lcrr;
		break;
	default:
		/* unknown lcrr */
		return -12;
	}

	mem_clk = csb_clk *
		  (1 + ((im->clk.spmr & SPMR_DDRCM) >> SPMR_DDRCM_SHIFT));
	corepll = (im->clk.spmr & SPMR_COREPLL) >> SPMR_COREPLL_SHIFT;

#if defined(CONFIG_MPC8360)
	mem_sec_clk = csb_clk * (1 +
		       ((im->clk.spmr & SPMR_LBIUCM) >> SPMR_LBIUCM_SHIFT));
#endif

	corecnf_tab_index = ((corepll & 0x1F) << 2) | ((corepll & 0x60) >> 5);
	if (corecnf_tab_index > (sizeof(corecnf_tab) / sizeof(corecnf_t))) {
		/* corecnf_tab_index is too high, possibly worng value */
		return -11;
	}
	switch (corecnf_tab[corecnf_tab_index].core_csb_ratio) {
	case _byp:
	case _x1:
	case _1x:
		core_clk = csb_clk;
		break;
	case _1_5x:
		core_clk = (3 * csb_clk) / 2;
		break;
	case _2x:
		core_clk = 2 * csb_clk;
		break;
	case _2_5x:
		core_clk = (5 * csb_clk) / 2;
		break;
	case _3x:
		core_clk = 3 * csb_clk;
		break;
	default:
		/* unkown core to csb ratio */
		return -13;
	}

#if defined(CONFIG_QE)
	qepmf = (im->clk.spmr & SPMR_CEPMF) >> SPMR_CEPMF_SHIFT;
	qepdf = (im->clk.spmr & SPMR_CEPDF) >> SPMR_CEPDF_SHIFT;
	qe_clk = (pci_sync_in * qepmf) / (1 + qepdf);
	brg_clk = qe_clk / 2;
#endif

	gd->csb_clk = csb_clk;
#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
	defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
	gd->tsec1_clk = tsec1_clk;
	gd->tsec2_clk = tsec2_clk;
	gd->usbdr_clk = usbdr_clk;
#elif defined(CONFIG_MPC8309)
	gd->usbdr_clk = usbdr_clk;
#endif
#if defined(CONFIG_MPC834x)
	gd->usbmph_clk = usbmph_clk;
#endif
#if defined(CONFIG_MPC8315)
	gd->tdm_clk = tdm_clk;
#endif
#if defined(CONFIG_FSL_ESDHC)
	gd->sdhc_clk = sdhc_clk;
#endif
	gd->core_clk = core_clk;
	gd->i2c1_clk = i2c1_clk;
#if !defined(CONFIG_MPC832x)
	gd->i2c2_clk = i2c2_clk;
#endif
#if !defined(CONFIG_MPC8309)
	gd->enc_clk = enc_clk;
#endif
	gd->lbiu_clk = lbiu_clk;
	gd->lclk_clk = lclk_clk;
	gd->mem_clk = mem_clk;
#if defined(CONFIG_MPC8360)
	gd->mem_sec_clk = mem_sec_clk;
#endif
#if defined(CONFIG_QE)
	gd->qe_clk = qe_clk;
	gd->brg_clk = brg_clk;
#endif
#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
	defined(CONFIG_MPC837x)
	gd->pciexp1_clk = pciexp1_clk;
	gd->pciexp2_clk = pciexp2_clk;
#endif
#if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315)
	gd->sata_clk = sata_clk;
#endif
	gd->pci_clk = pci_sync_in;
	gd->cpu_clk = gd->core_clk;
	gd->bus_clk = gd->csb_clk;
	return 0;

}

/********************************************
 * get_bus_freq
 * return system bus freq in Hz
 *********************************************/
ulong get_bus_freq(ulong dummy)
{
	return gd->csb_clk;
}

/********************************************
 * get_ddr_freq
 * return ddr bus freq in Hz
 *********************************************/
ulong get_ddr_freq(ulong dummy)
{
	return gd->mem_clk;
}

int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
{
	char buf[32];

	printf("Clock configuration:\n");
	printf("  Core:                %-4s MHz\n", strmhz(buf, gd->core_clk));
	printf("  Coherent System Bus: %-4s MHz\n", strmhz(buf, gd->csb_clk));
#if defined(CONFIG_QE)
	printf("  QE:                  %-4s MHz\n", strmhz(buf, gd->qe_clk));
	printf("  BRG:                 %-4s MHz\n", strmhz(buf, gd->brg_clk));
#endif
	printf("  Local Bus Controller:%-4s MHz\n", strmhz(buf, gd->lbiu_clk));
	printf("  Local Bus:           %-4s MHz\n", strmhz(buf, gd->lclk_clk));
	printf("  DDR:                 %-4s MHz\n", strmhz(buf, gd->mem_clk));
#if defined(CONFIG_MPC8360)
	printf("  DDR Secondary:       %-4s MHz\n", strmhz(buf, gd->mem_sec_clk));
#endif
#if !defined(CONFIG_MPC8309)
	printf("  SEC:                 %-4s MHz\n", strmhz(buf, gd->enc_clk));
#endif
	printf("  I2C1:                %-4s MHz\n", strmhz(buf, gd->i2c1_clk));
#if !defined(CONFIG_MPC832x)
	printf("  I2C2:                %-4s MHz\n", strmhz(buf, gd->i2c2_clk));
#endif
#if defined(CONFIG_MPC8315)
	printf("  TDM:                 %-4s MHz\n", strmhz(buf, gd->tdm_clk));
#endif
#if defined(CONFIG_FSL_ESDHC)
	printf("  SDHC:                %-4s MHz\n", strmhz(buf, gd->sdhc_clk));
#endif
#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
	defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
	printf("  TSEC1:               %-4s MHz\n", strmhz(buf, gd->tsec1_clk));
	printf("  TSEC2:               %-4s MHz\n", strmhz(buf, gd->tsec2_clk));
	printf("  USB DR:              %-4s MHz\n", strmhz(buf, gd->usbdr_clk));
#elif defined(CONFIG_MPC8309)
	printf("  USB DR:              %-4s MHz\n", strmhz(buf, gd->usbdr_clk));
#endif
#if defined(CONFIG_MPC834x)
	printf("  USB MPH:             %-4s MHz\n", strmhz(buf, gd->usbmph_clk));
#endif
#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
	defined(CONFIG_MPC837x)
	printf("  PCIEXP1:             %-4s MHz\n", strmhz(buf, gd->pciexp1_clk));
	printf("  PCIEXP2:             %-4s MHz\n", strmhz(buf, gd->pciexp2_clk));
#endif
#if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315)
	printf("  SATA:                %-4s MHz\n", strmhz(buf, gd->sata_clk));
#endif
	return 0;
}

U_BOOT_CMD(clocks, 1, 0, do_clocks,
	"print clock configuration",
	"    clocks"
);
Commit	Line	Data
f046ccd1 EL	1	/*
	2	* (C) Copyright 2000-2002
	3	* Wolfgang Denk, DENX Software Engineering, [email protected].
	4	*
03051c3d	5	* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
f046ccd1 EL	6	*
	7	* See file CREDITS for list of people who contributed to this
	8	* project.
	9	*
	10	* This program is free software; you can redistribute it and/or
	11	* modify it under the terms of the GNU General Public License as
	12	* published by the Free Software Foundation; either version 2 of
	13	* the License, or (at your option) any later version.
	14	*
	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	* GNU General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	23	* MA 02111-1307 USA
f046ccd1 EL	24	*/
	25
	26	#include <common.h>
	27	#include <mpc83xx.h>
54b2d434	28	#include <command.h>
f046ccd1 EL	29	#include <asm/processor.h>
f046ccd1 EL	30
d87080b7 WD	31	DECLARE_GLOBAL_DATA_PTR;
d87080b7 WD	32
f046ccd1 EL	33	/* ----------------------------------------------------------------- */
	34
	35	typedef enum {
	36	_unk,
	37	_off,
	38	_byp,
	39	_x8,
	40	_x4,
	41	_x2,
	42	_x1,
	43	_1x,
	44	_1_5x,
	45	_2x,
	46	_2_5x,
	47	_3x
	48	} mult_t;
	49
	50	typedef struct {
	51	mult_t core_csb_ratio;
f7fb2e70	52	mult_t vco_divider;
f046ccd1 EL	53	} corecnf_t;
	54
	55	corecnf_t corecnf_tab[] = {
f7fb2e70 KP	56	{_byp, _byp}, /* 0x00 */
	57	{_byp, _byp}, /* 0x01 */
	58	{_byp, _byp}, /* 0x02 */
	59	{_byp, _byp}, /* 0x03 */
	60	{_byp, _byp}, /* 0x04 */
	61	{_byp, _byp}, /* 0x05 */
	62	{_byp, _byp}, /* 0x06 */
	63	{_byp, _byp}, /* 0x07 */
	64	{_1x, _x2}, /* 0x08 */
	65	{_1x, _x4}, /* 0x09 */
	66	{_1x, _x8}, /* 0x0A */
	67	{_1x, _x8}, /* 0x0B */
	68	{_1_5x, _x2}, /* 0x0C */
	69	{_1_5x, _x4}, /* 0x0D */
	70	{_1_5x, _x8}, /* 0x0E */
	71	{_1_5x, _x8}, /* 0x0F */
	72	{_2x, _x2}, /* 0x10 */
	73	{_2x, _x4}, /* 0x11 */
	74	{_2x, _x8}, /* 0x12 */
	75	{_2x, _x8}, /* 0x13 */
	76	{_2_5x, _x2}, /* 0x14 */
	77	{_2_5x, _x4}, /* 0x15 */
	78	{_2_5x, _x8}, /* 0x16 */
	79	{_2_5x, _x8}, /* 0x17 */
	80	{_3x, _x2}, /* 0x18 */
	81	{_3x, _x4}, /* 0x19 */
	82	{_3x, _x8}, /* 0x1A */
	83	{_3x, _x8}, /* 0x1B */
f046ccd1 EL	84	};
	85
	86	/* ----------------------------------------------------------------- */
	87
	88	/*
	89	*
	90	*/
f7fb2e70	91	int get_clocks(void)
f046ccd1	92	{
6d0f6bcf	93	volatile immap_t im = (immap_t ) CONFIG_SYS_IMMR;
f046ccd1	94	u32 pci_sync_in;
f7fb2e70 KP	95	u8 spmf;
f7fb2e70 KP	96	u8 clkin_div;
f046ccd1 EL	97	u32 sccr;
f046ccd1 EL	98	u32 corecnf_tab_index;
f7fb2e70	99	u8 corepll;
f046ccd1	100	u32 lcrr;
de1d0a69	101
f046ccd1	102	u32 csb_clk;
7c619ddc IY	103	#if defined(CONFIG_MPC8308) \|\| defined(CONFIG_MPC831x) \|\| \
7c619ddc IY	104	defined(CONFIG_MPC834x) \|\| defined(CONFIG_MPC837x)
f046ccd1 EL	105	u32 tsec1_clk;
f046ccd1 EL	106	u32 tsec2_clk;
f046ccd1	107	u32 usbdr_clk;
a88731a6 GF	108	#elif defined(CONFIG_MPC8309)
a88731a6 GF	109	u32 usbdr_clk;
7c98e519	110	#endif
2c7920af	111	#ifdef CONFIG_MPC834x
7c98e519	112	u32 usbmph_clk;
5f820439 DL	113	#endif
	114	u32 core_clk;
	115	u32 i2c1_clk;
2c7920af	116	#if !defined(CONFIG_MPC832x)
5f820439	117	u32 i2c2_clk;
03051c3d	118	#endif
555da617 DL	119	#if defined(CONFIG_MPC8315)
	120	u32 tdm_clk;
	121	#endif
27ef578d	122	#if defined(CONFIG_FSL_ESDHC)
03051c3d	123	u32 sdhc_clk;
24c3aca3	124	#endif
a88731a6	125	#if !defined(CONFIG_MPC8309)
f046ccd1	126	u32 enc_clk;
a88731a6	127	#endif
f046ccd1 EL	128	u32 lbiu_clk;
f046ccd1 EL	129	u32 lclk_clk;
35cf155c	130	u32 mem_clk;
24c3aca3	131	#if defined(CONFIG_MPC8360)
35cf155c	132	u32 mem_sec_clk;
24c3aca3	133	#endif
4b5282de	134	#if defined(CONFIG_QE)
5f820439 DL	135	u32 qepmf;
5f820439 DL	136	u32 qepdf;
5f820439 DL	137	u32 qe_clk;
	138	u32 brg_clk;
	139	#endif
7c619ddc IY	140	#if defined(CONFIG_MPC8308) \|\| defined(CONFIG_MPC831x) \|\| \
7c619ddc IY	141	defined(CONFIG_MPC837x)
03051c3d DL	142	u32 pciexp1_clk;
03051c3d DL	143	u32 pciexp2_clk;
555da617	144	#endif
2c7920af	145	#if defined(CONFIG_MPC837x) \|\| defined(CONFIG_MPC8315)
03051c3d DL	146	u32 sata_clk;
03051c3d DL	147	#endif
de1d0a69	148
f7fb2e70	149	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
f046ccd1	150	return -1;
de1d0a69	151
5f820439	152	clkin_div = ((im->clk.spmr & SPMR_CKID) >> SPMR_CKID_SHIFT);
e6f2e902	153
5f820439 DL	154	if (im->reset.rcwh & HRCWH_PCI_HOST) {
	155	#if defined(CONFIG_83XX_CLKIN)
	156	pci_sync_in = CONFIG_83XX_CLKIN / (1 + clkin_div);
	157	#else
	158	pci_sync_in = 0xDEADBEEF;
	159	#endif
	160	} else {
	161	#if defined(CONFIG_83XX_PCICLK)
	162	pci_sync_in = CONFIG_83XX_PCICLK;
	163	#else
	164	pci_sync_in = 0xDEADBEEF;
	165	#endif
f046ccd1	166	}
f046ccd1	167
26e5f794	168	spmf = (im->clk.spmr & SPMR_SPMF) >> SPMR_SPMF_SHIFT;
5f820439	169	csb_clk = pci_sync_in * (1 + clkin_div) * spmf;
de1d0a69	170
f046ccd1	171	sccr = im->clk.sccr;
5f820439	172
7c619ddc IY	173	#if defined(CONFIG_MPC8308) \|\| defined(CONFIG_MPC831x) \|\| \
7c619ddc IY	174	defined(CONFIG_MPC834x) \|\| defined(CONFIG_MPC837x)
f046ccd1 EL	175	switch ((sccr & SCCR_TSEC1CM) >> SCCR_TSEC1CM_SHIFT) {
	176	case 0:
	177	tsec1_clk = 0;
	178	break;
	179	case 1:
	180	tsec1_clk = csb_clk;
	181	break;
	182	case 2:
	183	tsec1_clk = csb_clk / 2;
	184	break;
	185	case 3:
	186	tsec1_clk = csb_clk / 3;
	187	break;
	188	default:
	189	/* unkown SCCR_TSEC1CM value */
03051c3d	190	return -2;
f046ccd1	191	}
8afad91f	192	#endif
de1d0a69	193
8afad91f GF	194	#if defined(CONFIG_MPC830x) \|\| defined(CONFIG_MPC831x) \|\| \
8afad91f GF	195	defined(CONFIG_MPC834x) \|\| defined(CONFIG_MPC837x)
7c98e519 SW	196	switch ((sccr & SCCR_USBDRCM) >> SCCR_USBDRCM_SHIFT) {
	197	case 0:
	198	usbdr_clk = 0;
	199	break;
	200	case 1:
	201	usbdr_clk = csb_clk;
	202	break;
	203	case 2:
	204	usbdr_clk = csb_clk / 2;
	205	break;
	206	case 3:
	207	usbdr_clk = csb_clk / 3;
	208	break;
	209	default:
	210	/* unkown SCCR_USBDRCM value */
03051c3d	211	return -3;
7c98e519 SW	212	}
	213	#endif
	214
7c619ddc IY	215	#if defined(CONFIG_MPC8308) \|\| defined(CONFIG_MPC8315) \|\| \
7c619ddc IY	216	defined(CONFIG_MPC834x) \|\| defined(CONFIG_MPC837x)
f046ccd1 EL	217	switch ((sccr & SCCR_TSEC2CM) >> SCCR_TSEC2CM_SHIFT) {
	218	case 0:
	219	tsec2_clk = 0;
	220	break;
	221	case 1:
	222	tsec2_clk = csb_clk;
	223	break;
	224	case 2:
	225	tsec2_clk = csb_clk / 2;
	226	break;
	227	case 3:
	228	tsec2_clk = csb_clk / 3;
	229	break;
	230	default:
	231	/* unkown SCCR_TSEC2CM value */
03051c3d	232	return -4;
f046ccd1	233	}
555da617	234	#elif defined(CONFIG_MPC8313)
03051c3d	235	tsec2_clk = tsec1_clk;
de1d0a69	236
03051c3d DL	237	if (!(sccr & SCCR_TSEC1ON))
	238	tsec1_clk = 0;
	239	if (!(sccr & SCCR_TSEC2ON))
	240	tsec2_clk = 0;
	241	#endif
de1d0a69	242
2c7920af	243	#if defined(CONFIG_MPC834x)
f046ccd1 EL	244	switch ((sccr & SCCR_USBMPHCM) >> SCCR_USBMPHCM_SHIFT) {
	245	case 0:
	246	usbmph_clk = 0;
	247	break;
	248	case 1:
	249	usbmph_clk = csb_clk;
	250	break;
	251	case 2:
	252	usbmph_clk = csb_clk / 2;
	253	break;
	254	case 3:
	255	usbmph_clk = csb_clk / 3;
	256	break;
	257	default:
	258	/* unkown SCCR_USBMPHCM value */
03051c3d	259	return -5;
f046ccd1 EL	260	}
f046ccd1 EL	261
f7fb2e70 KP	262	if (usbmph_clk != 0 && usbdr_clk != 0 && usbmph_clk != usbdr_clk) {
	263	/* if USB MPH clock is not disabled and
	264	* USB DR clock is not disabled then
	265	* USB MPH & USB DR must have the same rate
	266	*/
03051c3d DL	267	return -6;
	268	}
	269	#endif
a88731a6	270	#if !defined(CONFIG_MPC8309)
03051c3d DL	271	switch ((sccr & SCCR_ENCCM) >> SCCR_ENCCM_SHIFT) {
	272	case 0:
	273	enc_clk = 0;
	274	break;
	275	case 1:
	276	enc_clk = csb_clk;
	277	break;
	278	case 2:
	279	enc_clk = csb_clk / 2;
	280	break;
	281	case 3:
	282	enc_clk = csb_clk / 3;
	283	break;
	284	default:
	285	/* unkown SCCR_ENCCM value */
	286	return -7;
f046ccd1	287	}
a88731a6	288	#endif
7c98e519	289
27ef578d	290	#if defined(CONFIG_FSL_ESDHC)
03051c3d DL	291	switch ((sccr & SCCR_SDHCCM) >> SCCR_SDHCCM_SHIFT) {
	292	case 0:
	293	sdhc_clk = 0;
	294	break;
	295	case 1:
	296	sdhc_clk = csb_clk;
	297	break;
	298	case 2:
	299	sdhc_clk = csb_clk / 2;
	300	break;
	301	case 3:
	302	sdhc_clk = csb_clk / 3;
	303	break;
	304	default:
	305	/* unkown SCCR_SDHCCM value */
	306	return -8;
	307	}
5f820439	308	#endif
555da617 DL	309	#if defined(CONFIG_MPC8315)
	310	switch ((sccr & SCCR_TDMCM) >> SCCR_TDMCM_SHIFT) {
	311	case 0:
	312	tdm_clk = 0;
	313	break;
	314	case 1:
	315	tdm_clk = csb_clk;
	316	break;
	317	case 2:
	318	tdm_clk = csb_clk / 2;
	319	break;
	320	case 3:
	321	tdm_clk = csb_clk / 3;
	322	break;
	323	default:
	324	/* unkown SCCR_TDMCM value */
	325	return -8;
	326	}
	327	#endif
7c98e519	328
2c7920af	329	#if defined(CONFIG_MPC834x)
03051c3d DL	330	i2c1_clk = tsec2_clk;
03051c3d DL	331	#elif defined(CONFIG_MPC8360)
5f820439	332	i2c1_clk = csb_clk;
2c7920af	333	#elif defined(CONFIG_MPC832x)
03051c3d	334	i2c1_clk = enc_clk;
7c619ddc	335	#elif defined(CONFIG_MPC8308) \|\| defined(CONFIG_MPC831x)
03051c3d	336	i2c1_clk = enc_clk;
27ef578d	337	#elif defined(CONFIG_FSL_ESDHC)
03051c3d	338	i2c1_clk = sdhc_clk;
1bda1624 AS	339	#elif defined(CONFIG_MPC837x)
1bda1624 AS	340	i2c1_clk = enc_clk;
a88731a6 GF	341	#elif defined(CONFIG_MPC8309)
a88731a6 GF	342	i2c1_clk = csb_clk;
5f820439	343	#endif
2c7920af	344	#if !defined(CONFIG_MPC832x)
03051c3d	345	i2c2_clk = csb_clk; /* i2c-2 clk is equal to csb clk */
24c3aca3	346	#endif
de1d0a69	347
7c619ddc IY	348	#if defined(CONFIG_MPC8308) \|\| defined(CONFIG_MPC831x) \|\| \
7c619ddc IY	349	defined(CONFIG_MPC837x)
03051c3d	350	switch ((sccr & SCCR_PCIEXP1CM) >> SCCR_PCIEXP1CM_SHIFT) {
5f820439	351	case 0:
03051c3d	352	pciexp1_clk = 0;
5f820439 DL	353	break;
5f820439 DL	354	case 1:
03051c3d	355	pciexp1_clk = csb_clk;
5f820439 DL	356	break;
5f820439 DL	357	case 2:
03051c3d	358	pciexp1_clk = csb_clk / 2;
5f820439 DL	359	break;
5f820439 DL	360	case 3:
03051c3d	361	pciexp1_clk = csb_clk / 3;
5f820439 DL	362	break;
5f820439 DL	363	default:
03051c3d DL	364	/* unkown SCCR_PCIEXP1CM value */
03051c3d DL	365	return -9;
5f820439	366	}
24c3aca3	367
03051c3d DL	368	switch ((sccr & SCCR_PCIEXP2CM) >> SCCR_PCIEXP2CM_SHIFT) {
	369	case 0:
	370	pciexp2_clk = 0;
	371	break;
	372	case 1:
	373	pciexp2_clk = csb_clk;
	374	break;
	375	case 2:
	376	pciexp2_clk = csb_clk / 2;
	377	break;
	378	case 3:
	379	pciexp2_clk = csb_clk / 3;
	380	break;
	381	default:
	382	/* unkown SCCR_PCIEXP2CM value */
	383	return -10;
	384	}
	385	#endif
	386
2c7920af	387	#if defined(CONFIG_MPC837x) \|\| defined(CONFIG_MPC8315)
a8cb43a8 DL	388	switch ((sccr & SCCR_SATA1CM) >> SCCR_SATA1CM_SHIFT) {
a8cb43a8 DL	389	case 0:
03051c3d DL	390	sata_clk = 0;
03051c3d DL	391	break;
a8cb43a8	392	case 1:
03051c3d DL	393	sata_clk = csb_clk;
03051c3d DL	394	break;
a8cb43a8	395	case 2:
03051c3d DL	396	sata_clk = csb_clk / 2;
03051c3d DL	397	break;
a8cb43a8	398	case 3:
03051c3d DL	399	sata_clk = csb_clk / 3;
	400	break;
	401	default:
9e896478	402	/* unkown SCCR_SATACM value */
03051c3d DL	403	return -11;
	404	}
	405	#endif
	406
f7fb2e70	407	lbiu_clk = csb_clk *
26e5f794	408	(1 + ((im->clk.spmr & SPMR_LBIUCM) >> SPMR_LBIUCM_SHIFT));
f51cdaf1	409	lcrr = (im->im_lbc.lcrr & LCRR_CLKDIV) >> LCRR_CLKDIV_SHIFT;
f046ccd1 EL	410	switch (lcrr) {
	411	case 2:
	412	case 4:
	413	case 8:
	414	lclk_clk = lbiu_clk / lcrr;
	415	break;
	416	default:
	417	/* unknown lcrr */
03051c3d	418	return -12;
f046ccd1	419	}
24c3aca3	420
35cf155c	421	mem_clk = csb_clk *
26e5f794 JT	422	(1 + ((im->clk.spmr & SPMR_DDRCM) >> SPMR_DDRCM_SHIFT));
	423	corepll = (im->clk.spmr & SPMR_COREPLL) >> SPMR_COREPLL_SHIFT;
	424
24c3aca3	425	#if defined(CONFIG_MPC8360)
35cf155c	426	mem_sec_clk = csb_clk * (1 +
26e5f794	427	((im->clk.spmr & SPMR_LBIUCM) >> SPMR_LBIUCM_SHIFT));
5f820439 DL	428	#endif
5f820439 DL	429
f046ccd1	430	corecnf_tab_index = ((corepll & 0x1F) << 2) \| ((corepll & 0x60) >> 5);
f7fb2e70	431	if (corecnf_tab_index > (sizeof(corecnf_tab) / sizeof(corecnf_t))) {
f046ccd1 EL	432	/* corecnf_tab_index is too high, possibly worng value */
	433	return -11;
	434	}
	435	switch (corecnf_tab[corecnf_tab_index].core_csb_ratio) {
	436	case _byp:
	437	case _x1:
	438	case _1x:
	439	core_clk = csb_clk;
	440	break;
	441	case _1_5x:
	442	core_clk = (3 * csb_clk) / 2;
	443	break;
	444	case _2x:
	445	core_clk = 2 * csb_clk;
	446	break;
	447	case _2_5x:
f7fb2e70	448	core_clk = (5 * csb_clk) / 2;
f046ccd1 EL	449	break;
	450	case _3x:
	451	core_clk = 3 * csb_clk;
	452	break;
	453	default:
	454	/* unkown core to csb ratio */
03051c3d	455	return -13;
f046ccd1	456	}
de1d0a69	457
4b5282de	458	#if defined(CONFIG_QE)
26e5f794 JT	459	qepmf = (im->clk.spmr & SPMR_CEPMF) >> SPMR_CEPMF_SHIFT;
26e5f794 JT	460	qepdf = (im->clk.spmr & SPMR_CEPDF) >> SPMR_CEPDF_SHIFT;
f7fb2e70	461	qe_clk = (pci_sync_in * qepmf) / (1 + qepdf);
5f820439 DL	462	brg_clk = qe_clk / 2;
	463	#endif
	464
f7fb2e70	465	gd->csb_clk = csb_clk;
7c619ddc IY	466	#if defined(CONFIG_MPC8308) \|\| defined(CONFIG_MPC831x) \|\| \
7c619ddc IY	467	defined(CONFIG_MPC834x) \|\| defined(CONFIG_MPC837x)
f7fb2e70 KP	468	gd->tsec1_clk = tsec1_clk;
f7fb2e70 KP	469	gd->tsec2_clk = tsec2_clk;
f7fb2e70	470	gd->usbdr_clk = usbdr_clk;
a88731a6 GF	471	#elif defined(CONFIG_MPC8309)
a88731a6 GF	472	gd->usbdr_clk = usbdr_clk;
7c98e519	473	#endif
2c7920af	474	#if defined(CONFIG_MPC834x)
7c98e519	475	gd->usbmph_clk = usbmph_clk;
03051c3d	476	#endif
555da617 DL	477	#if defined(CONFIG_MPC8315)
	478	gd->tdm_clk = tdm_clk;
	479	#endif
27ef578d	480	#if defined(CONFIG_FSL_ESDHC)
03051c3d	481	gd->sdhc_clk = sdhc_clk;
5f820439	482	#endif
f7fb2e70 KP	483	gd->core_clk = core_clk;
f7fb2e70 KP	484	gd->i2c1_clk = i2c1_clk;
2c7920af	485	#if !defined(CONFIG_MPC832x)
f7fb2e70	486	gd->i2c2_clk = i2c2_clk;
24c3aca3	487	#endif
a88731a6	488	#if !defined(CONFIG_MPC8309)
f7fb2e70	489	gd->enc_clk = enc_clk;
a88731a6	490	#endif
f7fb2e70 KP	491	gd->lbiu_clk = lbiu_clk;
f7fb2e70 KP	492	gd->lclk_clk = lclk_clk;
35cf155c	493	gd->mem_clk = mem_clk;
24c3aca3	494	#if defined(CONFIG_MPC8360)
35cf155c	495	gd->mem_sec_clk = mem_sec_clk;
24c3aca3	496	#endif
4b5282de	497	#if defined(CONFIG_QE)
f7fb2e70 KP	498	gd->qe_clk = qe_clk;
f7fb2e70 KP	499	gd->brg_clk = brg_clk;
03051c3d	500	#endif
810cb190 BC	501	#if defined(CONFIG_MPC8308) \|\| defined(CONFIG_MPC831x) \|\| \
810cb190 BC	502	defined(CONFIG_MPC837x)
03051c3d DL	503	gd->pciexp1_clk = pciexp1_clk;
03051c3d DL	504	gd->pciexp2_clk = pciexp2_clk;
555da617	505	#endif
2c7920af	506	#if defined(CONFIG_MPC837x) \|\| defined(CONFIG_MPC8315)
03051c3d	507	gd->sata_clk = sata_clk;
5f820439	508	#endif
8f9e0e9f	509	gd->pci_clk = pci_sync_in;
f7fb2e70 KP	510	gd->cpu_clk = gd->core_clk;
f7fb2e70 KP	511	gd->bus_clk = gd->csb_clk;
f046ccd1	512	return 0;
5f820439	513
f046ccd1 EL	514	}
	515
	516	/********************************************
	517	* get_bus_freq
	518	* return system bus freq in Hz
	519	*********************************************/
f7fb2e70	520	ulong get_bus_freq(ulong dummy)
f046ccd1	521	{
f046ccd1 EL	522	return gd->csb_clk;
	523	}
	524
d29d17d7 YS	525	/********************************************
	526	* get_ddr_freq
	527	* return ddr bus freq in Hz
	528	*********************************************/
	529	ulong get_ddr_freq(ulong dummy)
	530	{
	531	return gd->mem_clk;
	532	}
	533
54841ab5	534	int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
f046ccd1	535	{
08ef89ec WD	536	char buf[32];
08ef89ec WD	537
f046ccd1	538	printf("Clock configuration:\n");
08ef89ec WD	539	printf(" Core: %-4s MHz\n", strmhz(buf, gd->core_clk));
08ef89ec WD	540	printf(" Coherent System Bus: %-4s MHz\n", strmhz(buf, gd->csb_clk));
4b5282de	541	#if defined(CONFIG_QE)
08ef89ec WD	542	printf(" QE: %-4s MHz\n", strmhz(buf, gd->qe_clk));
08ef89ec WD	543	printf(" BRG: %-4s MHz\n", strmhz(buf, gd->brg_clk));
5f820439	544	#endif
08ef89ec WD	545	printf(" Local Bus Controller:%-4s MHz\n", strmhz(buf, gd->lbiu_clk));
	546	printf(" Local Bus: %-4s MHz\n", strmhz(buf, gd->lclk_clk));
	547	printf(" DDR: %-4s MHz\n", strmhz(buf, gd->mem_clk));
24c3aca3	548	#if defined(CONFIG_MPC8360)
08ef89ec	549	printf(" DDR Secondary: %-4s MHz\n", strmhz(buf, gd->mem_sec_clk));
5f820439	550	#endif
a88731a6	551	#if !defined(CONFIG_MPC8309)
08ef89ec	552	printf(" SEC: %-4s MHz\n", strmhz(buf, gd->enc_clk));
a88731a6	553	#endif
08ef89ec	554	printf(" I2C1: %-4s MHz\n", strmhz(buf, gd->i2c1_clk));
2c7920af	555	#if !defined(CONFIG_MPC832x)
08ef89ec	556	printf(" I2C2: %-4s MHz\n", strmhz(buf, gd->i2c2_clk));
24c3aca3	557	#endif
555da617	558	#if defined(CONFIG_MPC8315)
08ef89ec	559	printf(" TDM: %-4s MHz\n", strmhz(buf, gd->tdm_clk));
555da617	560	#endif
27ef578d	561	#if defined(CONFIG_FSL_ESDHC)
08ef89ec	562	printf(" SDHC: %-4s MHz\n", strmhz(buf, gd->sdhc_clk));
03051c3d	563	#endif
7c619ddc IY	564	#if defined(CONFIG_MPC8308) \|\| defined(CONFIG_MPC831x) \|\| \
7c619ddc IY	565	defined(CONFIG_MPC834x) \|\| defined(CONFIG_MPC837x)
08ef89ec WD	566	printf(" TSEC1: %-4s MHz\n", strmhz(buf, gd->tsec1_clk));
	567	printf(" TSEC2: %-4s MHz\n", strmhz(buf, gd->tsec2_clk));
	568	printf(" USB DR: %-4s MHz\n", strmhz(buf, gd->usbdr_clk));
a88731a6 GF	569	#elif defined(CONFIG_MPC8309)
a88731a6 GF	570	printf(" USB DR: %-4s MHz\n", strmhz(buf, gd->usbdr_clk));
7c98e519	571	#endif
2c7920af	572	#if defined(CONFIG_MPC834x)
08ef89ec	573	printf(" USB MPH: %-4s MHz\n", strmhz(buf, gd->usbmph_clk));
03051c3d	574	#endif
810cb190 BC	575	#if defined(CONFIG_MPC8308) \|\| defined(CONFIG_MPC831x) \|\| \
810cb190 BC	576	defined(CONFIG_MPC837x)
08ef89ec WD	577	printf(" PCIEXP1: %-4s MHz\n", strmhz(buf, gd->pciexp1_clk));
08ef89ec WD	578	printf(" PCIEXP2: %-4s MHz\n", strmhz(buf, gd->pciexp2_clk));
555da617	579	#endif
2c7920af	580	#if defined(CONFIG_MPC837x) \|\| defined(CONFIG_MPC8315)
08ef89ec	581	printf(" SATA: %-4s MHz\n", strmhz(buf, gd->sata_clk));
5f820439	582	#endif
de1d0a69	583	return 0;
f046ccd1	584	}
54b2d434 KP	585
54b2d434 KP	586	U_BOOT_CMD(clocks, 1, 0, do_clocks,
2fb2604d	587	"print clock configuration",
a89c33db	588	" clocks"
54b2d434	589	);