[J-u-boot.git] / arch / powerpc / cpu / mpc83xx / speed.c

/*
 * (C) Copyright 2000-2002
 * Wolfgang Denk, DENX Software Engineering, [email protected].
 *
 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <mpc83xx.h>
#include <command.h>
#include <asm/processor.h>

DECLARE_GLOBAL_DATA_PTR;

/* ----------------------------------------------------------------- */

typedef enum {
	_unk,
	_off,
	_byp,
	_x8,
	_x4,
	_x2,
	_x1,
	_1x,
	_1_5x,
	_2x,
	_2_5x,
	_3x
} mult_t;

typedef struct {
	mult_t core_csb_ratio;
	mult_t vco_divider;
} corecnf_t;

corecnf_t corecnf_tab[] = {
	{_byp, _byp},		/* 0x00 */
	{_byp, _byp},		/* 0x01 */
	{_byp, _byp},		/* 0x02 */
	{_byp, _byp},		/* 0x03 */
	{_byp, _byp},		/* 0x04 */
	{_byp, _byp},		/* 0x05 */
	{_byp, _byp},		/* 0x06 */
	{_byp, _byp},		/* 0x07 */
	{_1x, _x2},		/* 0x08 */
	{_1x, _x4},		/* 0x09 */
	{_1x, _x8},		/* 0x0A */
	{_1x, _x8},		/* 0x0B */
	{_1_5x, _x2},		/* 0x0C */
	{_1_5x, _x4},		/* 0x0D */
	{_1_5x, _x8},		/* 0x0E */
	{_1_5x, _x8},		/* 0x0F */
	{_2x, _x2},		/* 0x10 */
	{_2x, _x4},		/* 0x11 */
	{_2x, _x8},		/* 0x12 */
	{_2x, _x8},		/* 0x13 */
	{_2_5x, _x2},		/* 0x14 */
	{_2_5x, _x4},		/* 0x15 */
	{_2_5x, _x8},		/* 0x16 */
	{_2_5x, _x8},		/* 0x17 */
	{_3x, _x2},		/* 0x18 */
	{_3x, _x4},		/* 0x19 */
	{_3x, _x8},		/* 0x1A */
	{_3x, _x8},		/* 0x1B */
};

/* ----------------------------------------------------------------- */

/*
 *
 */
int get_clocks(void)
{
	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
	u32 pci_sync_in;
	u8 spmf;
	u8 clkin_div;
	u32 sccr;
	u32 corecnf_tab_index;
	u8 corepll;
	u32 lcrr;

	u32 csb_clk;
#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
	defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
	u32 tsec1_clk;
	u32 tsec2_clk;
	u32 usbdr_clk;
#endif
#ifdef CONFIG_MPC834x
	u32 usbmph_clk;
#endif
	u32 core_clk;
	u32 i2c1_clk;
#if !defined(CONFIG_MPC832x)
	u32 i2c2_clk;
#endif
#if defined(CONFIG_MPC8315)
	u32 tdm_clk;
#endif
#if defined(CONFIG_FSL_ESDHC)
	u32 sdhc_clk;
#endif
	u32 enc_clk;
	u32 lbiu_clk;
	u32 lclk_clk;
	u32 mem_clk;
#if defined(CONFIG_MPC8360)
	u32 mem_sec_clk;
#endif
#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832x)
	u32 qepmf;
	u32 qepdf;
	u32 qe_clk;
	u32 brg_clk;
#endif
#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
	defined(CONFIG_MPC837x)
	u32 pciexp1_clk;
	u32 pciexp2_clk;
#endif
#if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315)
	u32 sata_clk;
#endif

	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
		return -1;

	clkin_div = ((im->clk.spmr & SPMR_CKID) >> SPMR_CKID_SHIFT);

	if (im->reset.rcwh & HRCWH_PCI_HOST) {
#if defined(CONFIG_83XX_CLKIN)
		pci_sync_in = CONFIG_83XX_CLKIN / (1 + clkin_div);
#else
		pci_sync_in = 0xDEADBEEF;
#endif
	} else {
#if defined(CONFIG_83XX_PCICLK)
		pci_sync_in = CONFIG_83XX_PCICLK;
#else
		pci_sync_in = 0xDEADBEEF;
#endif
	}

	spmf = ((im->reset.rcwl & HRCWL_SPMF) >> HRCWL_SPMF_SHIFT);
	csb_clk = pci_sync_in * (1 + clkin_div) * spmf;

	sccr = im->clk.sccr;

#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
	defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
	switch ((sccr & SCCR_TSEC1CM) >> SCCR_TSEC1CM_SHIFT) {
	case 0:
		tsec1_clk = 0;
		break;
	case 1:
		tsec1_clk = csb_clk;
		break;
	case 2:
		tsec1_clk = csb_clk / 2;
		break;
	case 3:
		tsec1_clk = csb_clk / 3;
		break;
	default:
		/* unkown SCCR_TSEC1CM value */
		return -2;
	}

	switch ((sccr & SCCR_USBDRCM) >> SCCR_USBDRCM_SHIFT) {
	case 0:
		usbdr_clk = 0;
		break;
	case 1:
		usbdr_clk = csb_clk;
		break;
	case 2:
		usbdr_clk = csb_clk / 2;
		break;
	case 3:
		usbdr_clk = csb_clk / 3;
		break;
	default:
		/* unkown SCCR_USBDRCM value */
		return -3;
	}
#endif

#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC8315) || \
	defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
	switch ((sccr & SCCR_TSEC2CM) >> SCCR_TSEC2CM_SHIFT) {
	case 0:
		tsec2_clk = 0;
		break;
	case 1:
		tsec2_clk = csb_clk;
		break;
	case 2:
		tsec2_clk = csb_clk / 2;
		break;
	case 3:
		tsec2_clk = csb_clk / 3;
		break;
	default:
		/* unkown SCCR_TSEC2CM value */
		return -4;
	}
#elif defined(CONFIG_MPC8313)
	tsec2_clk = tsec1_clk;

	if (!(sccr & SCCR_TSEC1ON))
		tsec1_clk = 0;
	if (!(sccr & SCCR_TSEC2ON))
		tsec2_clk = 0;
#endif

#if defined(CONFIG_MPC834x)
	switch ((sccr & SCCR_USBMPHCM) >> SCCR_USBMPHCM_SHIFT) {
	case 0:
		usbmph_clk = 0;
		break;
	case 1:
		usbmph_clk = csb_clk;
		break;
	case 2:
		usbmph_clk = csb_clk / 2;
		break;
	case 3:
		usbmph_clk = csb_clk / 3;
		break;
	default:
		/* unkown SCCR_USBMPHCM value */
		return -5;
	}

	if (usbmph_clk != 0 && usbdr_clk != 0 && usbmph_clk != usbdr_clk) {
		/* if USB MPH clock is not disabled and
		 * USB DR clock is not disabled then
		 * USB MPH & USB DR must have the same rate
		 */
		return -6;
	}
#endif
	switch ((sccr & SCCR_ENCCM) >> SCCR_ENCCM_SHIFT) {
	case 0:
		enc_clk = 0;
		break;
	case 1:
		enc_clk = csb_clk;
		break;
	case 2:
		enc_clk = csb_clk / 2;
		break;
	case 3:
		enc_clk = csb_clk / 3;
		break;
	default:
		/* unkown SCCR_ENCCM value */
		return -7;
	}

#if defined(CONFIG_FSL_ESDHC)
	switch ((sccr & SCCR_SDHCCM) >> SCCR_SDHCCM_SHIFT) {
	case 0:
		sdhc_clk = 0;
		break;
	case 1:
		sdhc_clk = csb_clk;
		break;
	case 2:
		sdhc_clk = csb_clk / 2;
		break;
	case 3:
		sdhc_clk = csb_clk / 3;
		break;
	default:
		/* unkown SCCR_SDHCCM value */
		return -8;
	}
#endif
#if defined(CONFIG_MPC8315)
	switch ((sccr & SCCR_TDMCM) >> SCCR_TDMCM_SHIFT) {
	case 0:
		tdm_clk = 0;
		break;
	case 1:
		tdm_clk = csb_clk;
		break;
	case 2:
		tdm_clk = csb_clk / 2;
		break;
	case 3:
		tdm_clk = csb_clk / 3;
		break;
	default:
		/* unkown SCCR_TDMCM value */
		return -8;
	}
#endif

#if defined(CONFIG_MPC834x)
	i2c1_clk = tsec2_clk;
#elif defined(CONFIG_MPC8360)
	i2c1_clk = csb_clk;
#elif defined(CONFIG_MPC832x)
	i2c1_clk = enc_clk;
#elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x)
	i2c1_clk = enc_clk;
#elif defined(CONFIG_FSL_ESDHC)
	i2c1_clk = sdhc_clk;
#endif
#if !defined(CONFIG_MPC832x)
	i2c2_clk = csb_clk; /* i2c-2 clk is equal to csb clk */
#endif

#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
	defined(CONFIG_MPC837x)
	switch ((sccr & SCCR_PCIEXP1CM) >> SCCR_PCIEXP1CM_SHIFT) {
	case 0:
		pciexp1_clk = 0;
		break;
	case 1:
		pciexp1_clk = csb_clk;
		break;
	case 2:
		pciexp1_clk = csb_clk / 2;
		break;
	case 3:
		pciexp1_clk = csb_clk / 3;
		break;
	default:
		/* unkown SCCR_PCIEXP1CM value */
		return -9;
	}

	switch ((sccr & SCCR_PCIEXP2CM) >> SCCR_PCIEXP2CM_SHIFT) {
	case 0:
		pciexp2_clk = 0;
		break;
	case 1:
		pciexp2_clk = csb_clk;
		break;
	case 2:
		pciexp2_clk = csb_clk / 2;
		break;
	case 3:
		pciexp2_clk = csb_clk / 3;
		break;
	default:
		/* unkown SCCR_PCIEXP2CM value */
		return -10;
	}
#endif

#if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315)
	switch ((sccr & SCCR_SATA1CM) >> SCCR_SATA1CM_SHIFT) {
	case 0:
		sata_clk = 0;
		break;
	case 1:
		sata_clk = csb_clk;
		break;
	case 2:
		sata_clk = csb_clk / 2;
		break;
	case 3:
		sata_clk = csb_clk / 3;
		break;
	default:
		/* unkown SCCR_SATACM value */
		return -11;
	}
#endif

	lbiu_clk = csb_clk *
	           (1 + ((im->reset.rcwl & HRCWL_LBIUCM) >> HRCWL_LBIUCM_SHIFT));
	lcrr = (im->im_lbc.lcrr & LCRR_CLKDIV) >> LCRR_CLKDIV_SHIFT;
	switch (lcrr) {
	case 2:
	case 4:
	case 8:
		lclk_clk = lbiu_clk / lcrr;
		break;
	default:
		/* unknown lcrr */
		return -12;
	}

	mem_clk = csb_clk *
		  (1 + ((im->reset.rcwl & HRCWL_DDRCM) >> HRCWL_DDRCM_SHIFT));
	corepll = (im->reset.rcwl & HRCWL_COREPLL) >> HRCWL_COREPLL_SHIFT;
#if defined(CONFIG_MPC8360)
	mem_sec_clk = csb_clk * (1 +
		       ((im->reset.rcwl & HRCWL_LBIUCM) >> HRCWL_LBIUCM_SHIFT));
#endif

	corecnf_tab_index = ((corepll & 0x1F) << 2) | ((corepll & 0x60) >> 5);
	if (corecnf_tab_index > (sizeof(corecnf_tab) / sizeof(corecnf_t))) {
		/* corecnf_tab_index is too high, possibly worng value */
		return -11;
	}
	switch (corecnf_tab[corecnf_tab_index].core_csb_ratio) {
	case _byp:
	case _x1:
	case _1x:
		core_clk = csb_clk;
		break;
	case _1_5x:
		core_clk = (3 * csb_clk) / 2;
		break;
	case _2x:
		core_clk = 2 * csb_clk;
		break;
	case _2_5x:
		core_clk = (5 * csb_clk) / 2;
		break;
	case _3x:
		core_clk = 3 * csb_clk;
		break;
	default:
		/* unkown core to csb ratio */
		return -13;
	}

#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832x)
	qepmf = (im->reset.rcwl & HRCWL_CEPMF) >> HRCWL_CEPMF_SHIFT;
	qepdf = (im->reset.rcwl & HRCWL_CEPDF) >> HRCWL_CEPDF_SHIFT;
	qe_clk = (pci_sync_in * qepmf) / (1 + qepdf);
	brg_clk = qe_clk / 2;
#endif

	gd->csb_clk = csb_clk;
#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
	defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
	gd->tsec1_clk = tsec1_clk;
	gd->tsec2_clk = tsec2_clk;
	gd->usbdr_clk = usbdr_clk;
#endif
#if defined(CONFIG_MPC834x)
	gd->usbmph_clk = usbmph_clk;
#endif
#if defined(CONFIG_MPC8315)
	gd->tdm_clk = tdm_clk;
#endif
#if defined(CONFIG_FSL_ESDHC)
	gd->sdhc_clk = sdhc_clk;
#endif
	gd->core_clk = core_clk;
	gd->i2c1_clk = i2c1_clk;
#if !defined(CONFIG_MPC832x)
	gd->i2c2_clk = i2c2_clk;
#endif
	gd->enc_clk = enc_clk;
	gd->lbiu_clk = lbiu_clk;
	gd->lclk_clk = lclk_clk;
	gd->mem_clk = mem_clk;
#if defined(CONFIG_MPC8360)
	gd->mem_sec_clk = mem_sec_clk;
#endif
#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832x)
	gd->qe_clk = qe_clk;
	gd->brg_clk = brg_clk;
#endif
#if defined(CONFIG_MPC837x)
	gd->pciexp1_clk = pciexp1_clk;
	gd->pciexp2_clk = pciexp2_clk;
#endif
#if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315)
	gd->sata_clk = sata_clk;
#endif
	gd->pci_clk = pci_sync_in;
	gd->cpu_clk = gd->core_clk;
	gd->bus_clk = gd->csb_clk;
	return 0;

}

/********************************************
 * get_bus_freq
 * return system bus freq in Hz
 *********************************************/
ulong get_bus_freq(ulong dummy)
{
	return gd->csb_clk;
}

int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
{
	char buf[32];

	printf("Clock configuration:\n");
	printf("  Core:                %-4s MHz\n", strmhz(buf, gd->core_clk));
	printf("  Coherent System Bus: %-4s MHz\n", strmhz(buf, gd->csb_clk));
#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832x)
	printf("  QE:                  %-4s MHz\n", strmhz(buf, gd->qe_clk));
	printf("  BRG:                 %-4s MHz\n", strmhz(buf, gd->brg_clk));
#endif
	printf("  Local Bus Controller:%-4s MHz\n", strmhz(buf, gd->lbiu_clk));
	printf("  Local Bus:           %-4s MHz\n", strmhz(buf, gd->lclk_clk));
	printf("  DDR:                 %-4s MHz\n", strmhz(buf, gd->mem_clk));
#if defined(CONFIG_MPC8360)
	printf("  DDR Secondary:       %-4s MHz\n", strmhz(buf, gd->mem_sec_clk));
#endif
	printf("  SEC:                 %-4s MHz\n", strmhz(buf, gd->enc_clk));
	printf("  I2C1:                %-4s MHz\n", strmhz(buf, gd->i2c1_clk));
#if !defined(CONFIG_MPC832x)
	printf("  I2C2:                %-4s MHz\n", strmhz(buf, gd->i2c2_clk));
#endif
#if defined(CONFIG_MPC8315)
	printf("  TDM:                 %-4s MHz\n", strmhz(buf, gd->tdm_clk));
#endif
#if defined(CONFIG_FSL_ESDHC)
	printf("  SDHC:                %-4s MHz\n", strmhz(buf, gd->sdhc_clk));
#endif
#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
	defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
	printf("  TSEC1:               %-4s MHz\n", strmhz(buf, gd->tsec1_clk));
	printf("  TSEC2:               %-4s MHz\n", strmhz(buf, gd->tsec2_clk));
	printf("  USB DR:              %-4s MHz\n", strmhz(buf, gd->usbdr_clk));
#endif
#if defined(CONFIG_MPC834x)
	printf("  USB MPH:             %-4s MHz\n", strmhz(buf, gd->usbmph_clk));
#endif
#if defined(CONFIG_MPC837x)
	printf("  PCIEXP1:             %-4s MHz\n", strmhz(buf, gd->pciexp1_clk));
	printf("  PCIEXP2:             %-4s MHz\n", strmhz(buf, gd->pciexp2_clk));
#endif
#if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315)
	printf("  SATA:                %-4s MHz\n", strmhz(buf, gd->sata_clk));
#endif
	return 0;
}

U_BOOT_CMD(clocks, 1, 0, do_clocks,
	"print clock configuration",
	"    clocks"
);
Commit	Line	Data
f046ccd1 EL	1	/*
	2	* (C) Copyright 2000-2002
	3	* Wolfgang Denk, DENX Software Engineering, [email protected].
	4	*
03051c3d	5	* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
f046ccd1 EL	6	*
	7	* See file CREDITS for list of people who contributed to this
	8	* project.
	9	*
	10	* This program is free software; you can redistribute it and/or
	11	* modify it under the terms of the GNU General Public License as
	12	* published by the Free Software Foundation; either version 2 of
	13	* the License, or (at your option) any later version.
	14	*
	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	* GNU General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	23	* MA 02111-1307 USA
f046ccd1 EL	24	*/
	25
	26	#include <common.h>
	27	#include <mpc83xx.h>
54b2d434	28	#include <command.h>
f046ccd1 EL	29	#include <asm/processor.h>
f046ccd1 EL	30
d87080b7 WD	31	DECLARE_GLOBAL_DATA_PTR;
d87080b7 WD	32
f046ccd1 EL	33	/* ----------------------------------------------------------------- */
	34
	35	typedef enum {
	36	_unk,
	37	_off,
	38	_byp,
	39	_x8,
	40	_x4,
	41	_x2,
	42	_x1,
	43	_1x,
	44	_1_5x,
	45	_2x,
	46	_2_5x,
	47	_3x
	48	} mult_t;
	49
	50	typedef struct {
	51	mult_t core_csb_ratio;
f7fb2e70	52	mult_t vco_divider;
f046ccd1 EL	53	} corecnf_t;
	54
	55	corecnf_t corecnf_tab[] = {
f7fb2e70 KP	56	{_byp, _byp}, /* 0x00 */
	57	{_byp, _byp}, /* 0x01 */
	58	{_byp, _byp}, /* 0x02 */
	59	{_byp, _byp}, /* 0x03 */
	60	{_byp, _byp}, /* 0x04 */
	61	{_byp, _byp}, /* 0x05 */
	62	{_byp, _byp}, /* 0x06 */
	63	{_byp, _byp}, /* 0x07 */
	64	{_1x, _x2}, /* 0x08 */
	65	{_1x, _x4}, /* 0x09 */
	66	{_1x, _x8}, /* 0x0A */
	67	{_1x, _x8}, /* 0x0B */
	68	{_1_5x, _x2}, /* 0x0C */
	69	{_1_5x, _x4}, /* 0x0D */
	70	{_1_5x, _x8}, /* 0x0E */
	71	{_1_5x, _x8}, /* 0x0F */
	72	{_2x, _x2}, /* 0x10 */
	73	{_2x, _x4}, /* 0x11 */
	74	{_2x, _x8}, /* 0x12 */
	75	{_2x, _x8}, /* 0x13 */
	76	{_2_5x, _x2}, /* 0x14 */
	77	{_2_5x, _x4}, /* 0x15 */
	78	{_2_5x, _x8}, /* 0x16 */
	79	{_2_5x, _x8}, /* 0x17 */
	80	{_3x, _x2}, /* 0x18 */
	81	{_3x, _x4}, /* 0x19 */
	82	{_3x, _x8}, /* 0x1A */
	83	{_3x, _x8}, /* 0x1B */
f046ccd1 EL	84	};
	85
	86	/* ----------------------------------------------------------------- */
	87
	88	/*
	89	*
	90	*/
f7fb2e70	91	int get_clocks(void)
f046ccd1	92	{
6d0f6bcf	93	volatile immap_t im = (immap_t ) CONFIG_SYS_IMMR;
f046ccd1	94	u32 pci_sync_in;
f7fb2e70 KP	95	u8 spmf;
f7fb2e70 KP	96	u8 clkin_div;
f046ccd1 EL	97	u32 sccr;
f046ccd1 EL	98	u32 corecnf_tab_index;
f7fb2e70	99	u8 corepll;
f046ccd1	100	u32 lcrr;
de1d0a69	101
f046ccd1	102	u32 csb_clk;
7c619ddc IY	103	#if defined(CONFIG_MPC8308) \|\| defined(CONFIG_MPC831x) \|\| \
7c619ddc IY	104	defined(CONFIG_MPC834x) \|\| defined(CONFIG_MPC837x)
f046ccd1 EL	105	u32 tsec1_clk;
f046ccd1 EL	106	u32 tsec2_clk;
f046ccd1	107	u32 usbdr_clk;
7c98e519	108	#endif
2c7920af	109	#ifdef CONFIG_MPC834x
7c98e519	110	u32 usbmph_clk;
5f820439 DL	111	#endif
	112	u32 core_clk;
	113	u32 i2c1_clk;
2c7920af	114	#if !defined(CONFIG_MPC832x)
5f820439	115	u32 i2c2_clk;
03051c3d	116	#endif
555da617 DL	117	#if defined(CONFIG_MPC8315)
	118	u32 tdm_clk;
	119	#endif
27ef578d	120	#if defined(CONFIG_FSL_ESDHC)
03051c3d	121	u32 sdhc_clk;
24c3aca3	122	#endif
f046ccd1 EL	123	u32 enc_clk;
	124	u32 lbiu_clk;
	125	u32 lclk_clk;
35cf155c	126	u32 mem_clk;
24c3aca3	127	#if defined(CONFIG_MPC8360)
35cf155c	128	u32 mem_sec_clk;
24c3aca3	129	#endif
2c7920af	130	#if defined(CONFIG_MPC8360) \|\| defined(CONFIG_MPC832x)
5f820439 DL	131	u32 qepmf;
5f820439 DL	132	u32 qepdf;
5f820439 DL	133	u32 qe_clk;
	134	u32 brg_clk;
	135	#endif
7c619ddc IY	136	#if defined(CONFIG_MPC8308) \|\| defined(CONFIG_MPC831x) \|\| \
7c619ddc IY	137	defined(CONFIG_MPC837x)
03051c3d DL	138	u32 pciexp1_clk;
03051c3d DL	139	u32 pciexp2_clk;
555da617	140	#endif
2c7920af	141	#if defined(CONFIG_MPC837x) \|\| defined(CONFIG_MPC8315)
03051c3d DL	142	u32 sata_clk;
03051c3d DL	143	#endif
de1d0a69	144
f7fb2e70	145	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
f046ccd1	146	return -1;
de1d0a69	147
5f820439	148	clkin_div = ((im->clk.spmr & SPMR_CKID) >> SPMR_CKID_SHIFT);
e6f2e902	149
5f820439 DL	150	if (im->reset.rcwh & HRCWH_PCI_HOST) {
	151	#if defined(CONFIG_83XX_CLKIN)
	152	pci_sync_in = CONFIG_83XX_CLKIN / (1 + clkin_div);
	153	#else
	154	pci_sync_in = 0xDEADBEEF;
	155	#endif
	156	} else {
	157	#if defined(CONFIG_83XX_PCICLK)
	158	pci_sync_in = CONFIG_83XX_PCICLK;
	159	#else
	160	pci_sync_in = 0xDEADBEEF;
	161	#endif
f046ccd1	162	}
f046ccd1	163
e080313c	164	spmf = ((im->reset.rcwl & HRCWL_SPMF) >> HRCWL_SPMF_SHIFT);
5f820439	165	csb_clk = pci_sync_in * (1 + clkin_div) * spmf;
de1d0a69	166
f046ccd1	167	sccr = im->clk.sccr;
5f820439	168
7c619ddc IY	169	#if defined(CONFIG_MPC8308) \|\| defined(CONFIG_MPC831x) \|\| \
7c619ddc IY	170	defined(CONFIG_MPC834x) \|\| defined(CONFIG_MPC837x)
f046ccd1 EL	171	switch ((sccr & SCCR_TSEC1CM) >> SCCR_TSEC1CM_SHIFT) {
	172	case 0:
	173	tsec1_clk = 0;
	174	break;
	175	case 1:
	176	tsec1_clk = csb_clk;
	177	break;
	178	case 2:
	179	tsec1_clk = csb_clk / 2;
	180	break;
	181	case 3:
	182	tsec1_clk = csb_clk / 3;
	183	break;
	184	default:
	185	/* unkown SCCR_TSEC1CM value */
03051c3d	186	return -2;
f046ccd1	187	}
de1d0a69	188
7c98e519 SW	189	switch ((sccr & SCCR_USBDRCM) >> SCCR_USBDRCM_SHIFT) {
	190	case 0:
	191	usbdr_clk = 0;
	192	break;
	193	case 1:
	194	usbdr_clk = csb_clk;
	195	break;
	196	case 2:
	197	usbdr_clk = csb_clk / 2;
	198	break;
	199	case 3:
	200	usbdr_clk = csb_clk / 3;
	201	break;
	202	default:
	203	/* unkown SCCR_USBDRCM value */
03051c3d	204	return -3;
7c98e519 SW	205	}
	206	#endif
	207
7c619ddc IY	208	#if defined(CONFIG_MPC8308) \|\| defined(CONFIG_MPC8315) \|\| \
7c619ddc IY	209	defined(CONFIG_MPC834x) \|\| defined(CONFIG_MPC837x)
f046ccd1 EL	210	switch ((sccr & SCCR_TSEC2CM) >> SCCR_TSEC2CM_SHIFT) {
	211	case 0:
	212	tsec2_clk = 0;
	213	break;
	214	case 1:
	215	tsec2_clk = csb_clk;
	216	break;
	217	case 2:
	218	tsec2_clk = csb_clk / 2;
	219	break;
	220	case 3:
	221	tsec2_clk = csb_clk / 3;
	222	break;
	223	default:
	224	/* unkown SCCR_TSEC2CM value */
03051c3d	225	return -4;
f046ccd1	226	}
555da617	227	#elif defined(CONFIG_MPC8313)
03051c3d	228	tsec2_clk = tsec1_clk;
de1d0a69	229
03051c3d DL	230	if (!(sccr & SCCR_TSEC1ON))
	231	tsec1_clk = 0;
	232	if (!(sccr & SCCR_TSEC2ON))
	233	tsec2_clk = 0;
	234	#endif
de1d0a69	235
2c7920af	236	#if defined(CONFIG_MPC834x)
f046ccd1 EL	237	switch ((sccr & SCCR_USBMPHCM) >> SCCR_USBMPHCM_SHIFT) {
	238	case 0:
	239	usbmph_clk = 0;
	240	break;
	241	case 1:
	242	usbmph_clk = csb_clk;
	243	break;
	244	case 2:
	245	usbmph_clk = csb_clk / 2;
	246	break;
	247	case 3:
	248	usbmph_clk = csb_clk / 3;
	249	break;
	250	default:
	251	/* unkown SCCR_USBMPHCM value */
03051c3d	252	return -5;
f046ccd1 EL	253	}
f046ccd1 EL	254
f7fb2e70 KP	255	if (usbmph_clk != 0 && usbdr_clk != 0 && usbmph_clk != usbdr_clk) {
	256	/* if USB MPH clock is not disabled and
	257	* USB DR clock is not disabled then
	258	* USB MPH & USB DR must have the same rate
	259	*/
03051c3d DL	260	return -6;
	261	}
	262	#endif
	263	switch ((sccr & SCCR_ENCCM) >> SCCR_ENCCM_SHIFT) {
	264	case 0:
	265	enc_clk = 0;
	266	break;
	267	case 1:
	268	enc_clk = csb_clk;
	269	break;
	270	case 2:
	271	enc_clk = csb_clk / 2;
	272	break;
	273	case 3:
	274	enc_clk = csb_clk / 3;
	275	break;
	276	default:
	277	/* unkown SCCR_ENCCM value */
	278	return -7;
f046ccd1	279	}
7c98e519	280
27ef578d	281	#if defined(CONFIG_FSL_ESDHC)
03051c3d DL	282	switch ((sccr & SCCR_SDHCCM) >> SCCR_SDHCCM_SHIFT) {
	283	case 0:
	284	sdhc_clk = 0;
	285	break;
	286	case 1:
	287	sdhc_clk = csb_clk;
	288	break;
	289	case 2:
	290	sdhc_clk = csb_clk / 2;
	291	break;
	292	case 3:
	293	sdhc_clk = csb_clk / 3;
	294	break;
	295	default:
	296	/* unkown SCCR_SDHCCM value */
	297	return -8;
	298	}
5f820439	299	#endif
555da617 DL	300	#if defined(CONFIG_MPC8315)
	301	switch ((sccr & SCCR_TDMCM) >> SCCR_TDMCM_SHIFT) {
	302	case 0:
	303	tdm_clk = 0;
	304	break;
	305	case 1:
	306	tdm_clk = csb_clk;
	307	break;
	308	case 2:
	309	tdm_clk = csb_clk / 2;
	310	break;
	311	case 3:
	312	tdm_clk = csb_clk / 3;
	313	break;
	314	default:
	315	/* unkown SCCR_TDMCM value */
	316	return -8;
	317	}
	318	#endif
7c98e519	319
2c7920af	320	#if defined(CONFIG_MPC834x)
03051c3d DL	321	i2c1_clk = tsec2_clk;
03051c3d DL	322	#elif defined(CONFIG_MPC8360)
5f820439	323	i2c1_clk = csb_clk;
2c7920af	324	#elif defined(CONFIG_MPC832x)
03051c3d	325	i2c1_clk = enc_clk;
7c619ddc	326	#elif defined(CONFIG_MPC8308) \|\| defined(CONFIG_MPC831x)
03051c3d	327	i2c1_clk = enc_clk;
27ef578d	328	#elif defined(CONFIG_FSL_ESDHC)
03051c3d	329	i2c1_clk = sdhc_clk;
5f820439	330	#endif
2c7920af	331	#if !defined(CONFIG_MPC832x)
03051c3d	332	i2c2_clk = csb_clk; /* i2c-2 clk is equal to csb clk */
24c3aca3	333	#endif
de1d0a69	334
7c619ddc IY	335	#if defined(CONFIG_MPC8308) \|\| defined(CONFIG_MPC831x) \|\| \
7c619ddc IY	336	defined(CONFIG_MPC837x)
03051c3d	337	switch ((sccr & SCCR_PCIEXP1CM) >> SCCR_PCIEXP1CM_SHIFT) {
5f820439	338	case 0:
03051c3d	339	pciexp1_clk = 0;
5f820439 DL	340	break;
5f820439 DL	341	case 1:
03051c3d	342	pciexp1_clk = csb_clk;
5f820439 DL	343	break;
5f820439 DL	344	case 2:
03051c3d	345	pciexp1_clk = csb_clk / 2;
5f820439 DL	346	break;
5f820439 DL	347	case 3:
03051c3d	348	pciexp1_clk = csb_clk / 3;
5f820439 DL	349	break;
5f820439 DL	350	default:
03051c3d DL	351	/* unkown SCCR_PCIEXP1CM value */
03051c3d DL	352	return -9;
5f820439	353	}
24c3aca3	354
03051c3d DL	355	switch ((sccr & SCCR_PCIEXP2CM) >> SCCR_PCIEXP2CM_SHIFT) {
	356	case 0:
	357	pciexp2_clk = 0;
	358	break;
	359	case 1:
	360	pciexp2_clk = csb_clk;
	361	break;
	362	case 2:
	363	pciexp2_clk = csb_clk / 2;
	364	break;
	365	case 3:
	366	pciexp2_clk = csb_clk / 3;
	367	break;
	368	default:
	369	/* unkown SCCR_PCIEXP2CM value */
	370	return -10;
	371	}
	372	#endif
	373
2c7920af	374	#if defined(CONFIG_MPC837x) \|\| defined(CONFIG_MPC8315)
a8cb43a8 DL	375	switch ((sccr & SCCR_SATA1CM) >> SCCR_SATA1CM_SHIFT) {
a8cb43a8 DL	376	case 0:
03051c3d DL	377	sata_clk = 0;
03051c3d DL	378	break;
a8cb43a8	379	case 1:
03051c3d DL	380	sata_clk = csb_clk;
03051c3d DL	381	break;
a8cb43a8	382	case 2:
03051c3d DL	383	sata_clk = csb_clk / 2;
03051c3d DL	384	break;
a8cb43a8	385	case 3:
03051c3d DL	386	sata_clk = csb_clk / 3;
	387	break;
	388	default:
9e896478	389	/* unkown SCCR_SATACM value */
03051c3d DL	390	return -11;
	391	}
	392	#endif
	393
f7fb2e70	394	lbiu_clk = csb_clk *
e080313c	395	(1 + ((im->reset.rcwl & HRCWL_LBIUCM) >> HRCWL_LBIUCM_SHIFT));
f51cdaf1	396	lcrr = (im->im_lbc.lcrr & LCRR_CLKDIV) >> LCRR_CLKDIV_SHIFT;
f046ccd1 EL	397	switch (lcrr) {
	398	case 2:
	399	case 4:
	400	case 8:
	401	lclk_clk = lbiu_clk / lcrr;
	402	break;
	403	default:
	404	/* unknown lcrr */
03051c3d	405	return -12;
f046ccd1	406	}
24c3aca3	407
35cf155c	408	mem_clk = csb_clk *
e080313c DL	409	(1 + ((im->reset.rcwl & HRCWL_DDRCM) >> HRCWL_DDRCM_SHIFT));
e080313c DL	410	corepll = (im->reset.rcwl & HRCWL_COREPLL) >> HRCWL_COREPLL_SHIFT;
24c3aca3	411	#if defined(CONFIG_MPC8360)
35cf155c	412	mem_sec_clk = csb_clk * (1 +
e080313c	413	((im->reset.rcwl & HRCWL_LBIUCM) >> HRCWL_LBIUCM_SHIFT));
5f820439 DL	414	#endif
5f820439 DL	415
f046ccd1	416	corecnf_tab_index = ((corepll & 0x1F) << 2) \| ((corepll & 0x60) >> 5);
f7fb2e70	417	if (corecnf_tab_index > (sizeof(corecnf_tab) / sizeof(corecnf_t))) {
f046ccd1 EL	418	/* corecnf_tab_index is too high, possibly worng value */
	419	return -11;
	420	}
	421	switch (corecnf_tab[corecnf_tab_index].core_csb_ratio) {
	422	case _byp:
	423	case _x1:
	424	case _1x:
	425	core_clk = csb_clk;
	426	break;
	427	case _1_5x:
	428	core_clk = (3 * csb_clk) / 2;
	429	break;
	430	case _2x:
	431	core_clk = 2 * csb_clk;
	432	break;
	433	case _2_5x:
f7fb2e70	434	core_clk = (5 * csb_clk) / 2;
f046ccd1 EL	435	break;
	436	case _3x:
	437	core_clk = 3 * csb_clk;
	438	break;
	439	default:
	440	/* unkown core to csb ratio */
03051c3d	441	return -13;
f046ccd1	442	}
de1d0a69	443
2c7920af	444	#if defined(CONFIG_MPC8360) \|\| defined(CONFIG_MPC832x)
e080313c DL	445	qepmf = (im->reset.rcwl & HRCWL_CEPMF) >> HRCWL_CEPMF_SHIFT;
e080313c DL	446	qepdf = (im->reset.rcwl & HRCWL_CEPDF) >> HRCWL_CEPDF_SHIFT;
f7fb2e70	447	qe_clk = (pci_sync_in * qepmf) / (1 + qepdf);
5f820439 DL	448	brg_clk = qe_clk / 2;
	449	#endif
	450
f7fb2e70	451	gd->csb_clk = csb_clk;
7c619ddc IY	452	#if defined(CONFIG_MPC8308) \|\| defined(CONFIG_MPC831x) \|\| \
7c619ddc IY	453	defined(CONFIG_MPC834x) \|\| defined(CONFIG_MPC837x)
f7fb2e70 KP	454	gd->tsec1_clk = tsec1_clk;
f7fb2e70 KP	455	gd->tsec2_clk = tsec2_clk;
f7fb2e70	456	gd->usbdr_clk = usbdr_clk;
7c98e519	457	#endif
2c7920af	458	#if defined(CONFIG_MPC834x)
7c98e519	459	gd->usbmph_clk = usbmph_clk;
03051c3d	460	#endif
555da617 DL	461	#if defined(CONFIG_MPC8315)
	462	gd->tdm_clk = tdm_clk;
	463	#endif
27ef578d	464	#if defined(CONFIG_FSL_ESDHC)
03051c3d	465	gd->sdhc_clk = sdhc_clk;
5f820439	466	#endif
f7fb2e70 KP	467	gd->core_clk = core_clk;
f7fb2e70 KP	468	gd->i2c1_clk = i2c1_clk;
2c7920af	469	#if !defined(CONFIG_MPC832x)
f7fb2e70	470	gd->i2c2_clk = i2c2_clk;
24c3aca3	471	#endif
f7fb2e70 KP	472	gd->enc_clk = enc_clk;
	473	gd->lbiu_clk = lbiu_clk;
	474	gd->lclk_clk = lclk_clk;
35cf155c	475	gd->mem_clk = mem_clk;
24c3aca3	476	#if defined(CONFIG_MPC8360)
35cf155c	477	gd->mem_sec_clk = mem_sec_clk;
24c3aca3	478	#endif
2c7920af	479	#if defined(CONFIG_MPC8360) \|\| defined(CONFIG_MPC832x)
f7fb2e70 KP	480	gd->qe_clk = qe_clk;
f7fb2e70 KP	481	gd->brg_clk = brg_clk;
03051c3d	482	#endif
2c7920af	483	#if defined(CONFIG_MPC837x)
03051c3d DL	484	gd->pciexp1_clk = pciexp1_clk;
03051c3d DL	485	gd->pciexp2_clk = pciexp2_clk;
555da617	486	#endif
2c7920af	487	#if defined(CONFIG_MPC837x) \|\| defined(CONFIG_MPC8315)
03051c3d	488	gd->sata_clk = sata_clk;
5f820439	489	#endif
8f9e0e9f	490	gd->pci_clk = pci_sync_in;
f7fb2e70 KP	491	gd->cpu_clk = gd->core_clk;
f7fb2e70 KP	492	gd->bus_clk = gd->csb_clk;
f046ccd1	493	return 0;
5f820439	494
f046ccd1 EL	495	}
	496
	497	/********************************************
	498	* get_bus_freq
	499	* return system bus freq in Hz
	500	*********************************************/
f7fb2e70	501	ulong get_bus_freq(ulong dummy)
f046ccd1	502	{
f046ccd1 EL	503	return gd->csb_clk;
	504	}
	505
54841ab5	506	int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
f046ccd1	507	{
08ef89ec WD	508	char buf[32];
08ef89ec WD	509
f046ccd1	510	printf("Clock configuration:\n");
08ef89ec WD	511	printf(" Core: %-4s MHz\n", strmhz(buf, gd->core_clk));
08ef89ec WD	512	printf(" Coherent System Bus: %-4s MHz\n", strmhz(buf, gd->csb_clk));
2c7920af	513	#if defined(CONFIG_MPC8360) \|\| defined(CONFIG_MPC832x)
08ef89ec WD	514	printf(" QE: %-4s MHz\n", strmhz(buf, gd->qe_clk));
08ef89ec WD	515	printf(" BRG: %-4s MHz\n", strmhz(buf, gd->brg_clk));
5f820439	516	#endif
08ef89ec WD	517	printf(" Local Bus Controller:%-4s MHz\n", strmhz(buf, gd->lbiu_clk));
	518	printf(" Local Bus: %-4s MHz\n", strmhz(buf, gd->lclk_clk));
	519	printf(" DDR: %-4s MHz\n", strmhz(buf, gd->mem_clk));
24c3aca3	520	#if defined(CONFIG_MPC8360)
08ef89ec	521	printf(" DDR Secondary: %-4s MHz\n", strmhz(buf, gd->mem_sec_clk));
5f820439	522	#endif
08ef89ec WD	523	printf(" SEC: %-4s MHz\n", strmhz(buf, gd->enc_clk));
08ef89ec WD	524	printf(" I2C1: %-4s MHz\n", strmhz(buf, gd->i2c1_clk));
2c7920af	525	#if !defined(CONFIG_MPC832x)
08ef89ec	526	printf(" I2C2: %-4s MHz\n", strmhz(buf, gd->i2c2_clk));
24c3aca3	527	#endif
555da617	528	#if defined(CONFIG_MPC8315)
08ef89ec	529	printf(" TDM: %-4s MHz\n", strmhz(buf, gd->tdm_clk));
555da617	530	#endif
27ef578d	531	#if defined(CONFIG_FSL_ESDHC)
08ef89ec	532	printf(" SDHC: %-4s MHz\n", strmhz(buf, gd->sdhc_clk));
03051c3d	533	#endif
7c619ddc IY	534	#if defined(CONFIG_MPC8308) \|\| defined(CONFIG_MPC831x) \|\| \
7c619ddc IY	535	defined(CONFIG_MPC834x) \|\| defined(CONFIG_MPC837x)
08ef89ec WD	536	printf(" TSEC1: %-4s MHz\n", strmhz(buf, gd->tsec1_clk));
	537	printf(" TSEC2: %-4s MHz\n", strmhz(buf, gd->tsec2_clk));
	538	printf(" USB DR: %-4s MHz\n", strmhz(buf, gd->usbdr_clk));
7c98e519	539	#endif
2c7920af	540	#if defined(CONFIG_MPC834x)
08ef89ec	541	printf(" USB MPH: %-4s MHz\n", strmhz(buf, gd->usbmph_clk));
03051c3d	542	#endif
2c7920af	543	#if defined(CONFIG_MPC837x)
08ef89ec WD	544	printf(" PCIEXP1: %-4s MHz\n", strmhz(buf, gd->pciexp1_clk));
08ef89ec WD	545	printf(" PCIEXP2: %-4s MHz\n", strmhz(buf, gd->pciexp2_clk));
555da617	546	#endif
2c7920af	547	#if defined(CONFIG_MPC837x) \|\| defined(CONFIG_MPC8315)
08ef89ec	548	printf(" SATA: %-4s MHz\n", strmhz(buf, gd->sata_clk));
5f820439	549	#endif
de1d0a69	550	return 0;
f046ccd1	551	}
54b2d434 KP	552
54b2d434 KP	553	U_BOOT_CMD(clocks, 1, 0, do_clocks,
2fb2604d	554	"print clock configuration",
a89c33db	555	" clocks"
54b2d434	556	);