[J-u-boot.git] / arch / powerpc / cpu / mpc83xx / speed.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * (C) Copyright 2000-2002
 * Wolfgang Denk, DENX Software Engineering, [email protected].
 *
 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
 */

#ifndef CONFIG_CLK_MPC83XX

#include <common.h>
#include <clock_legacy.h>
#include <mpc83xx.h>
#include <command.h>
#include <vsprintf.h>
#include <asm/global_data.h>
#include <asm/processor.h>

DECLARE_GLOBAL_DATA_PTR;

/* ----------------------------------------------------------------- */

typedef enum {
	_unk,
	_off,
	_byp,
	_x8,
	_x4,
	_x2,
	_x1,
	_1x,
	_1_5x,
	_2x,
	_2_5x,
	_3x
} mult_t;

typedef struct {
	mult_t core_csb_ratio;
	mult_t vco_divider;
} corecnf_t;

static corecnf_t corecnf_tab[] = {
	{_byp, _byp},		/* 0x00 */
	{_byp, _byp},		/* 0x01 */
	{_byp, _byp},		/* 0x02 */
	{_byp, _byp},		/* 0x03 */
	{_byp, _byp},		/* 0x04 */
	{_byp, _byp},		/* 0x05 */
	{_byp, _byp},		/* 0x06 */
	{_byp, _byp},		/* 0x07 */
	{_1x, _x2},		/* 0x08 */
	{_1x, _x4},		/* 0x09 */
	{_1x, _x8},		/* 0x0A */
	{_1x, _x8},		/* 0x0B */
	{_1_5x, _x2},		/* 0x0C */
	{_1_5x, _x4},		/* 0x0D */
	{_1_5x, _x8},		/* 0x0E */
	{_1_5x, _x8},		/* 0x0F */
	{_2x, _x2},		/* 0x10 */
	{_2x, _x4},		/* 0x11 */
	{_2x, _x8},		/* 0x12 */
	{_2x, _x8},		/* 0x13 */
	{_2_5x, _x2},		/* 0x14 */
	{_2_5x, _x4},		/* 0x15 */
	{_2_5x, _x8},		/* 0x16 */
	{_2_5x, _x8},		/* 0x17 */
	{_3x, _x2},		/* 0x18 */
	{_3x, _x4},		/* 0x19 */
	{_3x, _x8},		/* 0x1A */
	{_3x, _x8},		/* 0x1B */
};

/* ----------------------------------------------------------------- */

/*
 *
 */
int get_clocks(void)
{
	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
	u32 pci_sync_in;
	u8 spmf;
	u8 clkin_div;
	u32 sccr;
	u32 corecnf_tab_index;
	u8 corepll;
	u32 lcrr;

	u32 csb_clk;
#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
	defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
	u32 tsec1_clk;
	u32 tsec2_clk;
	u32 usbdr_clk;
#elif defined(CONFIG_ARCH_MPC8309)
	u32 usbdr_clk;
#endif
#ifdef CONFIG_ARCH_MPC834X
	u32 usbmph_clk;
#endif
	u32 core_clk;
	u32 i2c1_clk;
#if !defined(CONFIG_ARCH_MPC832X)
	u32 i2c2_clk;
#endif
#if defined(CONFIG_FSL_ESDHC)
	u32 sdhc_clk;
#endif
#if !defined(CONFIG_ARCH_MPC8309)
	u32 enc_clk;
#endif
	u32 lbiu_clk;
	u32 lclk_clk;
	u32 mem_clk;
#if defined(CONFIG_ARCH_MPC8360)
	u32 mem_sec_clk;
#endif
#if defined(CONFIG_QE)
	u32 qepmf;
	u32 qepdf;
	u32 qe_clk;
	u32 brg_clk;
#endif
#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
	defined(CONFIG_ARCH_MPC837X)
	u32 pciexp1_clk;
	u32 pciexp2_clk;
#endif
#if defined(CONFIG_ARCH_MPC837X)
	u32 sata_clk;
#endif

	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
		return -1;

	clkin_div = ((im->clk.spmr & SPMR_CKID) >> SPMR_CKID_SHIFT);

	if (im->reset.rcwh & HRCWH_PCI_HOST) {
#if defined(CONFIG_SYS_CLK_FREQ)
		pci_sync_in = CONFIG_SYS_CLK_FREQ / (1 + clkin_div);
#else
		pci_sync_in = 0xDEADBEEF;
#endif
	} else {
#if defined(CONFIG_83XX_PCICLK)
		pci_sync_in = CONFIG_83XX_PCICLK;
#else
		pci_sync_in = 0xDEADBEEF;
#endif
	}

	spmf = (im->clk.spmr & SPMR_SPMF) >> SPMR_SPMF_SHIFT;
	csb_clk = pci_sync_in * (1 + clkin_div) * spmf;

	sccr = im->clk.sccr;

#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
	defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
	switch ((sccr & SCCR_TSEC1CM) >> SCCR_TSEC1CM_SHIFT) {
	case 0:
		tsec1_clk = 0;
		break;
	case 1:
		tsec1_clk = csb_clk;
		break;
	case 2:
		tsec1_clk = csb_clk / 2;
		break;
	case 3:
		tsec1_clk = csb_clk / 3;
		break;
	default:
		/* unknown SCCR_TSEC1CM value */
		return -2;
	}
#endif

#if defined(CONFIG_ARCH_MPC830X) || defined(CONFIG_ARCH_MPC831X) || \
	defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
	switch ((sccr & SCCR_USBDRCM) >> SCCR_USBDRCM_SHIFT) {
	case 0:
		usbdr_clk = 0;
		break;
	case 1:
		usbdr_clk = csb_clk;
		break;
	case 2:
		usbdr_clk = csb_clk / 2;
		break;
	case 3:
		usbdr_clk = csb_clk / 3;
		break;
	default:
		/* unknown SCCR_USBDRCM value */
		return -3;
	}
#endif

#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC834X) || \
	defined(CONFIG_ARCH_MPC837X)
	switch ((sccr & SCCR_TSEC2CM) >> SCCR_TSEC2CM_SHIFT) {
	case 0:
		tsec2_clk = 0;
		break;
	case 1:
		tsec2_clk = csb_clk;
		break;
	case 2:
		tsec2_clk = csb_clk / 2;
		break;
	case 3:
		tsec2_clk = csb_clk / 3;
		break;
	default:
		/* unknown SCCR_TSEC2CM value */
		return -4;
	}
#elif defined(CONFIG_ARCH_MPC8313)
	tsec2_clk = tsec1_clk;

	if (!(sccr & SCCR_TSEC1ON))
		tsec1_clk = 0;
	if (!(sccr & SCCR_TSEC2ON))
		tsec2_clk = 0;
#endif

#if defined(CONFIG_ARCH_MPC834X)
	switch ((sccr & SCCR_USBMPHCM) >> SCCR_USBMPHCM_SHIFT) {
	case 0:
		usbmph_clk = 0;
		break;
	case 1:
		usbmph_clk = csb_clk;
		break;
	case 2:
		usbmph_clk = csb_clk / 2;
		break;
	case 3:
		usbmph_clk = csb_clk / 3;
		break;
	default:
		/* unknown SCCR_USBMPHCM value */
		return -5;
	}

	if (usbmph_clk != 0 && usbdr_clk != 0 && usbmph_clk != usbdr_clk) {
		/* if USB MPH clock is not disabled and
		 * USB DR clock is not disabled then
		 * USB MPH & USB DR must have the same rate
		 */
		return -6;
	}
#endif
#if !defined(CONFIG_ARCH_MPC8309)
	switch ((sccr & SCCR_ENCCM) >> SCCR_ENCCM_SHIFT) {
	case 0:
		enc_clk = 0;
		break;
	case 1:
		enc_clk = csb_clk;
		break;
	case 2:
		enc_clk = csb_clk / 2;
		break;
	case 3:
		enc_clk = csb_clk / 3;
		break;
	default:
		/* unknown SCCR_ENCCM value */
		return -7;
	}
#endif

#if defined(CONFIG_FSL_ESDHC)
	switch ((sccr & SCCR_SDHCCM) >> SCCR_SDHCCM_SHIFT) {
	case 0:
		sdhc_clk = 0;
		break;
	case 1:
		sdhc_clk = csb_clk;
		break;
	case 2:
		sdhc_clk = csb_clk / 2;
		break;
	case 3:
		sdhc_clk = csb_clk / 3;
		break;
	default:
		/* unknown SCCR_SDHCCM value */
		return -8;
	}
#endif

#if defined(CONFIG_ARCH_MPC834X)
	i2c1_clk = tsec2_clk;
#elif defined(CONFIG_ARCH_MPC8360)
	i2c1_clk = csb_clk;
#elif defined(CONFIG_ARCH_MPC832X)
	i2c1_clk = enc_clk;
#elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X)
	i2c1_clk = enc_clk;
#elif defined(CONFIG_FSL_ESDHC)
	i2c1_clk = sdhc_clk;
#elif defined(CONFIG_ARCH_MPC837X)
	i2c1_clk = enc_clk;
#elif defined(CONFIG_ARCH_MPC8309)
	i2c1_clk = csb_clk;
#endif
#if !defined(CONFIG_ARCH_MPC832X)
	i2c2_clk = csb_clk; /* i2c-2 clk is equal to csb clk */
#endif

#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
	defined(CONFIG_ARCH_MPC837X)
	switch ((sccr & SCCR_PCIEXP1CM) >> SCCR_PCIEXP1CM_SHIFT) {
	case 0:
		pciexp1_clk = 0;
		break;
	case 1:
		pciexp1_clk = csb_clk;
		break;
	case 2:
		pciexp1_clk = csb_clk / 2;
		break;
	case 3:
		pciexp1_clk = csb_clk / 3;
		break;
	default:
		/* unknown SCCR_PCIEXP1CM value */
		return -9;
	}

	switch ((sccr & SCCR_PCIEXP2CM) >> SCCR_PCIEXP2CM_SHIFT) {
	case 0:
		pciexp2_clk = 0;
		break;
	case 1:
		pciexp2_clk = csb_clk;
		break;
	case 2:
		pciexp2_clk = csb_clk / 2;
		break;
	case 3:
		pciexp2_clk = csb_clk / 3;
		break;
	default:
		/* unknown SCCR_PCIEXP2CM value */
		return -10;
	}
#endif

#if defined(CONFIG_ARCH_MPC837X)
	switch ((sccr & SCCR_SATA1CM) >> SCCR_SATA1CM_SHIFT) {
	case 0:
		sata_clk = 0;
		break;
	case 1:
		sata_clk = csb_clk;
		break;
	case 2:
		sata_clk = csb_clk / 2;
		break;
	case 3:
		sata_clk = csb_clk / 3;
		break;
	default:
		/* unknown SCCR_SATA1CM value */
		return -11;
	}
#endif

	lbiu_clk = csb_clk *
		   (1 + ((im->clk.spmr & SPMR_LBIUCM) >> SPMR_LBIUCM_SHIFT));
	lcrr = (im->im_lbc.lcrr & LCRR_CLKDIV) >> LCRR_CLKDIV_SHIFT;
	switch (lcrr) {
	case 2:
	case 4:
	case 8:
		lclk_clk = lbiu_clk / lcrr;
		break;
	default:
		/* unknown lcrr */
		return -12;
	}

	mem_clk = csb_clk *
		  (1 + ((im->clk.spmr & SPMR_DDRCM) >> SPMR_DDRCM_SHIFT));
	corepll = (im->clk.spmr & SPMR_COREPLL) >> SPMR_COREPLL_SHIFT;

#if defined(CONFIG_ARCH_MPC8360)
	mem_sec_clk = csb_clk * (1 +
		       ((im->clk.spmr & SPMR_LBIUCM) >> SPMR_LBIUCM_SHIFT));
#endif

	corecnf_tab_index = ((corepll & 0x1F) << 2) | ((corepll & 0x60) >> 5);
	if (corecnf_tab_index > (ARRAY_SIZE(corecnf_tab))) {
		/* corecnf_tab_index is too high, possibly wrong value */
		return -11;
	}
	switch (corecnf_tab[corecnf_tab_index].core_csb_ratio) {
	case _byp:
	case _x1:
	case _1x:
		core_clk = csb_clk;
		break;
	case _1_5x:
		core_clk = (3 * csb_clk) / 2;
		break;
	case _2x:
		core_clk = 2 * csb_clk;
		break;
	case _2_5x:
		core_clk = (5 * csb_clk) / 2;
		break;
	case _3x:
		core_clk = 3 * csb_clk;
		break;
	default:
		/* unknown core to csb ratio */
		return -13;
	}

#if defined(CONFIG_QE)
	qepmf = (im->clk.spmr & SPMR_CEPMF) >> SPMR_CEPMF_SHIFT;
	qepdf = (im->clk.spmr & SPMR_CEPDF) >> SPMR_CEPDF_SHIFT;
	qe_clk = (pci_sync_in * qepmf) / (1 + qepdf);
	brg_clk = qe_clk / 2;
#endif

	gd->arch.csb_clk = csb_clk;
#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
	defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
	gd->arch.tsec1_clk = tsec1_clk;
	gd->arch.tsec2_clk = tsec2_clk;
	gd->arch.usbdr_clk = usbdr_clk;
#elif defined(CONFIG_ARCH_MPC8309)
	gd->arch.usbdr_clk = usbdr_clk;
#endif
#if defined(CONFIG_ARCH_MPC834X)
	gd->arch.usbmph_clk = usbmph_clk;
#endif
#if defined(CONFIG_FSL_ESDHC)
	gd->arch.sdhc_clk = sdhc_clk;
#endif
	gd->arch.core_clk = core_clk;
	gd->arch.i2c1_clk = i2c1_clk;
#if !defined(CONFIG_ARCH_MPC832X)
	gd->arch.i2c2_clk = i2c2_clk;
#endif
#if !defined(CONFIG_ARCH_MPC8309)
	gd->arch.enc_clk = enc_clk;
#endif
	gd->arch.lbiu_clk = lbiu_clk;
	gd->arch.lclk_clk = lclk_clk;
	gd->mem_clk = mem_clk;
#if defined(CONFIG_ARCH_MPC8360)
	gd->arch.mem_sec_clk = mem_sec_clk;
#endif
#if defined(CONFIG_QE)
	gd->arch.qe_clk = qe_clk;
	gd->arch.brg_clk = brg_clk;
#endif
#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
	defined(CONFIG_ARCH_MPC837X)
	gd->arch.pciexp1_clk = pciexp1_clk;
	gd->arch.pciexp2_clk = pciexp2_clk;
#endif
#if defined(CONFIG_ARCH_MPC837X)
	gd->arch.sata_clk = sata_clk;
#endif
	gd->pci_clk = pci_sync_in;
	gd->cpu_clk = gd->arch.core_clk;
	gd->bus_clk = gd->arch.csb_clk;
	return 0;

}

/********************************************
 * get_bus_freq
 * return system bus freq in Hz
 *********************************************/
ulong get_bus_freq(ulong dummy)
{
	return gd->arch.csb_clk;
}

/********************************************
 * get_ddr_freq
 * return ddr bus freq in Hz
 *********************************************/
ulong get_ddr_freq(ulong dummy)
{
	return gd->mem_clk;
}

int get_serial_clock(void)
{
	return get_bus_freq(0);
}

static int do_clocks(struct cmd_tbl *cmdtp, int flag, int argc,
		     char *const argv[])
{
	char buf[32];

	printf("Clock configuration:\n");
	printf("  Core:                %-4s MHz\n",
	       strmhz(buf, gd->arch.core_clk));
	printf("  Coherent System Bus: %-4s MHz\n",
	       strmhz(buf, gd->arch.csb_clk));
#if defined(CONFIG_QE)
	printf("  QE:                  %-4s MHz\n",
	       strmhz(buf, gd->arch.qe_clk));
	printf("  BRG:                 %-4s MHz\n",
	       strmhz(buf, gd->arch.brg_clk));
#endif
	printf("  Local Bus Controller:%-4s MHz\n",
	       strmhz(buf, gd->arch.lbiu_clk));
	printf("  Local Bus:           %-4s MHz\n",
	       strmhz(buf, gd->arch.lclk_clk));
	printf("  DDR:                 %-4s MHz\n", strmhz(buf, gd->mem_clk));
#if defined(CONFIG_ARCH_MPC8360)
	printf("  DDR Secondary:       %-4s MHz\n",
	       strmhz(buf, gd->arch.mem_sec_clk));
#endif
#if !defined(CONFIG_ARCH_MPC8309)
	printf("  SEC:                 %-4s MHz\n",
	       strmhz(buf, gd->arch.enc_clk));
#endif
	printf("  I2C1:                %-4s MHz\n",
	       strmhz(buf, gd->arch.i2c1_clk));
#if !defined(CONFIG_ARCH_MPC832X)
	printf("  I2C2:                %-4s MHz\n",
	       strmhz(buf, gd->arch.i2c2_clk));
#endif
#if defined(CONFIG_FSL_ESDHC)
	printf("  SDHC:                %-4s MHz\n",
	       strmhz(buf, gd->arch.sdhc_clk));
#endif
#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
	defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
	printf("  TSEC1:               %-4s MHz\n",
	       strmhz(buf, gd->arch.tsec1_clk));
	printf("  TSEC2:               %-4s MHz\n",
	       strmhz(buf, gd->arch.tsec2_clk));
	printf("  USB DR:              %-4s MHz\n",
	       strmhz(buf, gd->arch.usbdr_clk));
#elif defined(CONFIG_ARCH_MPC8309)
	printf("  USB DR:              %-4s MHz\n",
	       strmhz(buf, gd->arch.usbdr_clk));
#endif
#if defined(CONFIG_ARCH_MPC834X)
	printf("  USB MPH:             %-4s MHz\n",
	       strmhz(buf, gd->arch.usbmph_clk));
#endif
#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
	defined(CONFIG_ARCH_MPC837X)
	printf("  PCIEXP1:             %-4s MHz\n",
	       strmhz(buf, gd->arch.pciexp1_clk));
	printf("  PCIEXP2:             %-4s MHz\n",
	       strmhz(buf, gd->arch.pciexp2_clk));
#endif
#if defined(CONFIG_ARCH_MPC837X)
	printf("  SATA:                %-4s MHz\n",
	       strmhz(buf, gd->arch.sata_clk));
#endif
	return 0;
}

U_BOOT_CMD(clocks, 1, 0, do_clocks,
	"print clock configuration",
	"    clocks"
);

#endif
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
f046ccd1 EL	2	/*
	3	* (C) Copyright 2000-2002
	4	* Wolfgang Denk, DENX Software Engineering, [email protected].
	5	*
03051c3d	6	* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
f046ccd1 EL	7	*/
f046ccd1 EL	8
07d538d2 MS	9	#ifndef CONFIG_CLK_MPC83XX
07d538d2 MS	10
f046ccd1	11	#include <common.h>
d96c2604	12	#include <clock_legacy.h>
f046ccd1	13	#include <mpc83xx.h>
54b2d434	14	#include <command.h>
2189d5f1	15	#include <vsprintf.h>
401d1c4f	16	#include <asm/global_data.h>
f046ccd1 EL	17	#include <asm/processor.h>
f046ccd1 EL	18
d87080b7 WD	19	DECLARE_GLOBAL_DATA_PTR;
d87080b7 WD	20
f046ccd1 EL	21	/* ----------------------------------------------------------------- */
	22
	23	typedef enum {
	24	_unk,
	25	_off,
	26	_byp,
	27	_x8,
	28	_x4,
	29	_x2,
	30	_x1,
	31	_1x,
	32	_1_5x,
	33	_2x,
	34	_2_5x,
	35	_3x
	36	} mult_t;
	37
	38	typedef struct {
	39	mult_t core_csb_ratio;
f7fb2e70	40	mult_t vco_divider;
f046ccd1 EL	41	} corecnf_t;
f046ccd1 EL	42
a2873bde	43	static corecnf_t corecnf_tab[] = {
f7fb2e70 KP	44	{_byp, _byp}, /* 0x00 */
	45	{_byp, _byp}, /* 0x01 */
	46	{_byp, _byp}, /* 0x02 */
	47	{_byp, _byp}, /* 0x03 */
	48	{_byp, _byp}, /* 0x04 */
	49	{_byp, _byp}, /* 0x05 */
	50	{_byp, _byp}, /* 0x06 */
	51	{_byp, _byp}, /* 0x07 */
	52	{_1x, _x2}, /* 0x08 */
	53	{_1x, _x4}, /* 0x09 */
	54	{_1x, _x8}, /* 0x0A */
	55	{_1x, _x8}, /* 0x0B */
	56	{_1_5x, _x2}, /* 0x0C */
	57	{_1_5x, _x4}, /* 0x0D */
	58	{_1_5x, _x8}, /* 0x0E */
	59	{_1_5x, _x8}, /* 0x0F */
	60	{_2x, _x2}, /* 0x10 */
	61	{_2x, _x4}, /* 0x11 */
	62	{_2x, _x8}, /* 0x12 */
	63	{_2x, _x8}, /* 0x13 */
	64	{_2_5x, _x2}, /* 0x14 */
	65	{_2_5x, _x4}, /* 0x15 */
	66	{_2_5x, _x8}, /* 0x16 */
	67	{_2_5x, _x8}, /* 0x17 */
	68	{_3x, _x2}, /* 0x18 */
	69	{_3x, _x4}, /* 0x19 */
	70	{_3x, _x8}, /* 0x1A */
	71	{_3x, _x8}, /* 0x1B */
f046ccd1 EL	72	};
	73
	74	/* ----------------------------------------------------------------- */
	75
	76	/*
	77	*
	78	*/
f7fb2e70	79	int get_clocks(void)
f046ccd1	80	{
6d0f6bcf	81	volatile immap_t im = (immap_t ) CONFIG_SYS_IMMR;
f046ccd1	82	u32 pci_sync_in;
f7fb2e70 KP	83	u8 spmf;
f7fb2e70 KP	84	u8 clkin_div;
f046ccd1 EL	85	u32 sccr;
f046ccd1 EL	86	u32 corecnf_tab_index;
f7fb2e70	87	u8 corepll;
f046ccd1	88	u32 lcrr;
de1d0a69	89
f046ccd1	90	u32 csb_clk;
9403fc41	91	#if defined(CONFIG_ARCH_MPC8308) \|\| defined(CONFIG_ARCH_MPC831X) \|\| \
8439e99d	92	defined(CONFIG_ARCH_MPC834X) \|\| defined(CONFIG_ARCH_MPC837X)
f046ccd1 EL	93	u32 tsec1_clk;
f046ccd1 EL	94	u32 tsec2_clk;
f046ccd1	95	u32 usbdr_clk;
4bc97a3b	96	#elif defined(CONFIG_ARCH_MPC8309)
a88731a6	97	u32 usbdr_clk;
7c98e519	98	#endif
d5cfa4aa	99	#ifdef CONFIG_ARCH_MPC834X
7c98e519	100	u32 usbmph_clk;
5f820439 DL	101	#endif
	102	u32 core_clk;
	103	u32 i2c1_clk;
bd3b867e	104	#if !defined(CONFIG_ARCH_MPC832X)
5f820439	105	u32 i2c2_clk;
03051c3d	106	#endif
27ef578d	107	#if defined(CONFIG_FSL_ESDHC)
03051c3d	108	u32 sdhc_clk;
24c3aca3	109	#endif
4bc97a3b	110	#if !defined(CONFIG_ARCH_MPC8309)
f046ccd1	111	u32 enc_clk;
a88731a6	112	#endif
f046ccd1 EL	113	u32 lbiu_clk;
f046ccd1 EL	114	u32 lclk_clk;
35cf155c	115	u32 mem_clk;
61abced7	116	#if defined(CONFIG_ARCH_MPC8360)
35cf155c	117	u32 mem_sec_clk;
24c3aca3	118	#endif
4b5282de	119	#if defined(CONFIG_QE)
5f820439 DL	120	u32 qepmf;
5f820439 DL	121	u32 qepdf;
5f820439 DL	122	u32 qe_clk;
	123	u32 brg_clk;
	124	#endif
9403fc41	125	#if defined(CONFIG_ARCH_MPC8308) \|\| defined(CONFIG_ARCH_MPC831X) \|\| \
8439e99d	126	defined(CONFIG_ARCH_MPC837X)
03051c3d DL	127	u32 pciexp1_clk;
03051c3d DL	128	u32 pciexp2_clk;
555da617	129	#endif
139ff3be	130	#if defined(CONFIG_ARCH_MPC837X)
03051c3d DL	131	u32 sata_clk;
03051c3d DL	132	#endif
de1d0a69	133
f7fb2e70	134	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
f046ccd1	135	return -1;
de1d0a69	136
5f820439	137	clkin_div = ((im->clk.spmr & SPMR_CKID) >> SPMR_CKID_SHIFT);
e6f2e902	138
5f820439	139	if (im->reset.rcwh & HRCWH_PCI_HOST) {
ff3bb0c4 MS	140	#if defined(CONFIG_SYS_CLK_FREQ)
ff3bb0c4 MS	141	pci_sync_in = CONFIG_SYS_CLK_FREQ / (1 + clkin_div);
5f820439 DL	142	#else
	143	pci_sync_in = 0xDEADBEEF;
	144	#endif
	145	} else {
	146	#if defined(CONFIG_83XX_PCICLK)
	147	pci_sync_in = CONFIG_83XX_PCICLK;
	148	#else
	149	pci_sync_in = 0xDEADBEEF;
	150	#endif
f046ccd1	151	}
f046ccd1	152
26e5f794	153	spmf = (im->clk.spmr & SPMR_SPMF) >> SPMR_SPMF_SHIFT;
5f820439	154	csb_clk = pci_sync_in * (1 + clkin_div) * spmf;
de1d0a69	155
f046ccd1	156	sccr = im->clk.sccr;
5f820439	157
9403fc41	158	#if defined(CONFIG_ARCH_MPC8308) \|\| defined(CONFIG_ARCH_MPC831X) \|\| \
8439e99d	159	defined(CONFIG_ARCH_MPC834X) \|\| defined(CONFIG_ARCH_MPC837X)
f046ccd1 EL	160	switch ((sccr & SCCR_TSEC1CM) >> SCCR_TSEC1CM_SHIFT) {
	161	case 0:
	162	tsec1_clk = 0;
	163	break;
	164	case 1:
	165	tsec1_clk = csb_clk;
	166	break;
	167	case 2:
	168	tsec1_clk = csb_clk / 2;
	169	break;
	170	case 3:
	171	tsec1_clk = csb_clk / 3;
	172	break;
	173	default:
d7b4ca2b	174	/* unknown SCCR_TSEC1CM value */
03051c3d	175	return -2;
f046ccd1	176	}
8afad91f	177	#endif
de1d0a69	178
9403fc41	179	#if defined(CONFIG_ARCH_MPC830X) \|\| defined(CONFIG_ARCH_MPC831X) \|\| \
8439e99d	180	defined(CONFIG_ARCH_MPC834X) \|\| defined(CONFIG_ARCH_MPC837X)
7c98e519 SW	181	switch ((sccr & SCCR_USBDRCM) >> SCCR_USBDRCM_SHIFT) {
	182	case 0:
	183	usbdr_clk = 0;
	184	break;
	185	case 1:
	186	usbdr_clk = csb_clk;
	187	break;
	188	case 2:
	189	usbdr_clk = csb_clk / 2;
	190	break;
	191	case 3:
	192	usbdr_clk = csb_clk / 3;
	193	break;
	194	default:
d7b4ca2b	195	/* unknown SCCR_USBDRCM value */
03051c3d	196	return -3;
7c98e519 SW	197	}
	198	#endif
	199
139ff3be TR	200	#if defined(CONFIG_ARCH_MPC8308) \|\| defined(CONFIG_ARCH_MPC834X) \|\| \
139ff3be TR	201	defined(CONFIG_ARCH_MPC837X)
f046ccd1 EL	202	switch ((sccr & SCCR_TSEC2CM) >> SCCR_TSEC2CM_SHIFT) {
	203	case 0:
	204	tsec2_clk = 0;
	205	break;
	206	case 1:
	207	tsec2_clk = csb_clk;
	208	break;
	209	case 2:
	210	tsec2_clk = csb_clk / 2;
	211	break;
	212	case 3:
	213	tsec2_clk = csb_clk / 3;
	214	break;
	215	default:
d7b4ca2b	216	/* unknown SCCR_TSEC2CM value */
03051c3d	217	return -4;
f046ccd1	218	}
9403fc41	219	#elif defined(CONFIG_ARCH_MPC8313)
03051c3d	220	tsec2_clk = tsec1_clk;
de1d0a69	221
03051c3d DL	222	if (!(sccr & SCCR_TSEC1ON))
	223	tsec1_clk = 0;
	224	if (!(sccr & SCCR_TSEC2ON))
	225	tsec2_clk = 0;
	226	#endif
de1d0a69	227
d5cfa4aa	228	#if defined(CONFIG_ARCH_MPC834X)
f046ccd1 EL	229	switch ((sccr & SCCR_USBMPHCM) >> SCCR_USBMPHCM_SHIFT) {
	230	case 0:
	231	usbmph_clk = 0;
	232	break;
	233	case 1:
	234	usbmph_clk = csb_clk;
	235	break;
	236	case 2:
	237	usbmph_clk = csb_clk / 2;
	238	break;
	239	case 3:
	240	usbmph_clk = csb_clk / 3;
	241	break;
	242	default:
d7b4ca2b	243	/* unknown SCCR_USBMPHCM value */
03051c3d	244	return -5;
f046ccd1 EL	245	}
f046ccd1 EL	246
f7fb2e70 KP	247	if (usbmph_clk != 0 && usbdr_clk != 0 && usbmph_clk != usbdr_clk) {
	248	/* if USB MPH clock is not disabled and
	249	* USB DR clock is not disabled then
	250	* USB MPH & USB DR must have the same rate
	251	*/
03051c3d DL	252	return -6;
	253	}
	254	#endif
4bc97a3b	255	#if !defined(CONFIG_ARCH_MPC8309)
03051c3d DL	256	switch ((sccr & SCCR_ENCCM) >> SCCR_ENCCM_SHIFT) {
	257	case 0:
	258	enc_clk = 0;
	259	break;
	260	case 1:
	261	enc_clk = csb_clk;
	262	break;
	263	case 2:
	264	enc_clk = csb_clk / 2;
	265	break;
	266	case 3:
	267	enc_clk = csb_clk / 3;
	268	break;
	269	default:
d7b4ca2b	270	/* unknown SCCR_ENCCM value */
03051c3d	271	return -7;
f046ccd1	272	}
a88731a6	273	#endif
7c98e519	274
27ef578d	275	#if defined(CONFIG_FSL_ESDHC)
03051c3d DL	276	switch ((sccr & SCCR_SDHCCM) >> SCCR_SDHCCM_SHIFT) {
	277	case 0:
	278	sdhc_clk = 0;
	279	break;
	280	case 1:
	281	sdhc_clk = csb_clk;
	282	break;
	283	case 2:
	284	sdhc_clk = csb_clk / 2;
	285	break;
	286	case 3:
	287	sdhc_clk = csb_clk / 3;
	288	break;
	289	default:
d7b4ca2b	290	/* unknown SCCR_SDHCCM value */
03051c3d DL	291	return -8;
03051c3d DL	292	}
5f820439	293	#endif
7c98e519	294
d5cfa4aa	295	#if defined(CONFIG_ARCH_MPC834X)
03051c3d	296	i2c1_clk = tsec2_clk;
61abced7	297	#elif defined(CONFIG_ARCH_MPC8360)
5f820439	298	i2c1_clk = csb_clk;
bd3b867e	299	#elif defined(CONFIG_ARCH_MPC832X)
03051c3d	300	i2c1_clk = enc_clk;
9403fc41	301	#elif defined(CONFIG_ARCH_MPC8308) \|\| defined(CONFIG_ARCH_MPC831X)
03051c3d	302	i2c1_clk = enc_clk;
27ef578d	303	#elif defined(CONFIG_FSL_ESDHC)
03051c3d	304	i2c1_clk = sdhc_clk;
8439e99d	305	#elif defined(CONFIG_ARCH_MPC837X)
1bda1624	306	i2c1_clk = enc_clk;
4bc97a3b	307	#elif defined(CONFIG_ARCH_MPC8309)
a88731a6	308	i2c1_clk = csb_clk;
5f820439	309	#endif
bd3b867e	310	#if !defined(CONFIG_ARCH_MPC832X)
03051c3d	311	i2c2_clk = csb_clk; /* i2c-2 clk is equal to csb clk */
24c3aca3	312	#endif
de1d0a69	313
9403fc41	314	#if defined(CONFIG_ARCH_MPC8308) \|\| defined(CONFIG_ARCH_MPC831X) \|\| \
8439e99d	315	defined(CONFIG_ARCH_MPC837X)
03051c3d	316	switch ((sccr & SCCR_PCIEXP1CM) >> SCCR_PCIEXP1CM_SHIFT) {
5f820439	317	case 0:
03051c3d	318	pciexp1_clk = 0;
5f820439 DL	319	break;
5f820439 DL	320	case 1:
03051c3d	321	pciexp1_clk = csb_clk;
5f820439 DL	322	break;
5f820439 DL	323	case 2:
03051c3d	324	pciexp1_clk = csb_clk / 2;
5f820439 DL	325	break;
5f820439 DL	326	case 3:
03051c3d	327	pciexp1_clk = csb_clk / 3;
5f820439 DL	328	break;
5f820439 DL	329	default:
d7b4ca2b	330	/* unknown SCCR_PCIEXP1CM value */
03051c3d	331	return -9;
5f820439	332	}
24c3aca3	333
03051c3d DL	334	switch ((sccr & SCCR_PCIEXP2CM) >> SCCR_PCIEXP2CM_SHIFT) {
	335	case 0:
	336	pciexp2_clk = 0;
	337	break;
	338	case 1:
	339	pciexp2_clk = csb_clk;
	340	break;
	341	case 2:
	342	pciexp2_clk = csb_clk / 2;
	343	break;
	344	case 3:
	345	pciexp2_clk = csb_clk / 3;
	346	break;
	347	default:
d7b4ca2b	348	/* unknown SCCR_PCIEXP2CM value */
03051c3d DL	349	return -10;
	350	}
	351	#endif
	352
139ff3be	353	#if defined(CONFIG_ARCH_MPC837X)
a8cb43a8 DL	354	switch ((sccr & SCCR_SATA1CM) >> SCCR_SATA1CM_SHIFT) {
a8cb43a8 DL	355	case 0:
03051c3d DL	356	sata_clk = 0;
03051c3d DL	357	break;
a8cb43a8	358	case 1:
03051c3d DL	359	sata_clk = csb_clk;
03051c3d DL	360	break;
a8cb43a8	361	case 2:
03051c3d DL	362	sata_clk = csb_clk / 2;
03051c3d DL	363	break;
a8cb43a8	364	case 3:
03051c3d DL	365	sata_clk = csb_clk / 3;
	366	break;
	367	default:
d7b4ca2b	368	/* unknown SCCR_SATA1CM value */
03051c3d DL	369	return -11;
	370	}
	371	#endif
	372
f7fb2e70	373	lbiu_clk = csb_clk *
26e5f794	374	(1 + ((im->clk.spmr & SPMR_LBIUCM) >> SPMR_LBIUCM_SHIFT));
f51cdaf1	375	lcrr = (im->im_lbc.lcrr & LCRR_CLKDIV) >> LCRR_CLKDIV_SHIFT;
f046ccd1 EL	376	switch (lcrr) {
	377	case 2:
	378	case 4:
	379	case 8:
	380	lclk_clk = lbiu_clk / lcrr;
	381	break;
	382	default:
	383	/* unknown lcrr */
03051c3d	384	return -12;
f046ccd1	385	}
24c3aca3	386
35cf155c	387	mem_clk = csb_clk *
26e5f794 JT	388	(1 + ((im->clk.spmr & SPMR_DDRCM) >> SPMR_DDRCM_SHIFT));
	389	corepll = (im->clk.spmr & SPMR_COREPLL) >> SPMR_COREPLL_SHIFT;
	390
61abced7	391	#if defined(CONFIG_ARCH_MPC8360)
35cf155c	392	mem_sec_clk = csb_clk * (1 +
26e5f794	393	((im->clk.spmr & SPMR_LBIUCM) >> SPMR_LBIUCM_SHIFT));
5f820439 DL	394	#endif
5f820439 DL	395
f046ccd1	396	corecnf_tab_index = ((corepll & 0x1F) << 2) \| ((corepll & 0x60) >> 5);
b7707b04	397	if (corecnf_tab_index > (ARRAY_SIZE(corecnf_tab))) {
d7b4ca2b	398	/* corecnf_tab_index is too high, possibly wrong value */
f046ccd1 EL	399	return -11;
	400	}
	401	switch (corecnf_tab[corecnf_tab_index].core_csb_ratio) {
	402	case _byp:
	403	case _x1:
	404	case _1x:
	405	core_clk = csb_clk;
	406	break;
	407	case _1_5x:
	408	core_clk = (3 * csb_clk) / 2;
	409	break;
	410	case _2x:
	411	core_clk = 2 * csb_clk;
	412	break;
	413	case _2_5x:
f7fb2e70	414	core_clk = (5 * csb_clk) / 2;
f046ccd1 EL	415	break;
	416	case _3x:
	417	core_clk = 3 * csb_clk;
	418	break;
	419	default:
d7b4ca2b	420	/* unknown core to csb ratio */
03051c3d	421	return -13;
f046ccd1	422	}
de1d0a69	423
4b5282de	424	#if defined(CONFIG_QE)
26e5f794 JT	425	qepmf = (im->clk.spmr & SPMR_CEPMF) >> SPMR_CEPMF_SHIFT;
26e5f794 JT	426	qepdf = (im->clk.spmr & SPMR_CEPDF) >> SPMR_CEPDF_SHIFT;
f7fb2e70	427	qe_clk = (pci_sync_in * qepmf) / (1 + qepdf);
5f820439 DL	428	brg_clk = qe_clk / 2;
	429	#endif
	430
c6731fe2	431	gd->arch.csb_clk = csb_clk;
9403fc41	432	#if defined(CONFIG_ARCH_MPC8308) \|\| defined(CONFIG_ARCH_MPC831X) \|\| \
8439e99d	433	defined(CONFIG_ARCH_MPC834X) \|\| defined(CONFIG_ARCH_MPC837X)
c6731fe2 SG	434	gd->arch.tsec1_clk = tsec1_clk;
	435	gd->arch.tsec2_clk = tsec2_clk;
	436	gd->arch.usbdr_clk = usbdr_clk;
4bc97a3b	437	#elif defined(CONFIG_ARCH_MPC8309)
c6731fe2	438	gd->arch.usbdr_clk = usbdr_clk;
7c98e519	439	#endif
d5cfa4aa	440	#if defined(CONFIG_ARCH_MPC834X)
c6731fe2	441	gd->arch.usbmph_clk = usbmph_clk;
03051c3d	442	#endif
27ef578d	443	#if defined(CONFIG_FSL_ESDHC)
e9adeca3	444	gd->arch.sdhc_clk = sdhc_clk;
5f820439	445	#endif
c6731fe2	446	gd->arch.core_clk = core_clk;
609e6ec3	447	gd->arch.i2c1_clk = i2c1_clk;
bd3b867e	448	#if !defined(CONFIG_ARCH_MPC832X)
609e6ec3	449	gd->arch.i2c2_clk = i2c2_clk;
24c3aca3	450	#endif
4bc97a3b	451	#if !defined(CONFIG_ARCH_MPC8309)
c6731fe2	452	gd->arch.enc_clk = enc_clk;
a88731a6	453	#endif
c6731fe2 SG	454	gd->arch.lbiu_clk = lbiu_clk;
c6731fe2 SG	455	gd->arch.lclk_clk = lclk_clk;
35cf155c	456	gd->mem_clk = mem_clk;
61abced7	457	#if defined(CONFIG_ARCH_MPC8360)
c6731fe2	458	gd->arch.mem_sec_clk = mem_sec_clk;
24c3aca3	459	#endif
4b5282de	460	#if defined(CONFIG_QE)
45bae2e3	461	gd->arch.qe_clk = qe_clk;
1206c184	462	gd->arch.brg_clk = brg_clk;
03051c3d	463	#endif
9403fc41	464	#if defined(CONFIG_ARCH_MPC8308) \|\| defined(CONFIG_ARCH_MPC831X) \|\| \
8439e99d	465	defined(CONFIG_ARCH_MPC837X)
c6731fe2 SG	466	gd->arch.pciexp1_clk = pciexp1_clk;
c6731fe2 SG	467	gd->arch.pciexp2_clk = pciexp2_clk;
555da617	468	#endif
139ff3be	469	#if defined(CONFIG_ARCH_MPC837X)
c6731fe2	470	gd->arch.sata_clk = sata_clk;
5f820439	471	#endif
8f9e0e9f	472	gd->pci_clk = pci_sync_in;
c6731fe2 SG	473	gd->cpu_clk = gd->arch.core_clk;
c6731fe2 SG	474	gd->bus_clk = gd->arch.csb_clk;
f046ccd1	475	return 0;
5f820439	476
f046ccd1 EL	477	}
	478
	479	/********************************************
	480	* get_bus_freq
	481	* return system bus freq in Hz
	482	*********************************************/
f7fb2e70	483	ulong get_bus_freq(ulong dummy)
f046ccd1	484	{
c6731fe2	485	return gd->arch.csb_clk;
f046ccd1 EL	486	}
f046ccd1 EL	487
d29d17d7 YS	488	/********************************************
	489	* get_ddr_freq
	490	* return ddr bus freq in Hz
	491	*********************************************/
	492	ulong get_ddr_freq(ulong dummy)
	493	{
	494	return gd->mem_clk;
	495	}
	496
ac016c94 MS	497	int get_serial_clock(void)
	498	{
	499	return get_bus_freq(0);
	500	}
	501
09140113 SG	502	static int do_clocks(struct cmd_tbl *cmdtp, int flag, int argc,
09140113 SG	503	char *const argv[])
f046ccd1	504	{
08ef89ec WD	505	char buf[32];
08ef89ec WD	506
f046ccd1	507	printf("Clock configuration:\n");
c6731fe2 SG	508	printf(" Core: %-4s MHz\n",
	509	strmhz(buf, gd->arch.core_clk));
	510	printf(" Coherent System Bus: %-4s MHz\n",
	511	strmhz(buf, gd->arch.csb_clk));
4b5282de	512	#if defined(CONFIG_QE)
45bae2e3 SG	513	printf(" QE: %-4s MHz\n",
45bae2e3 SG	514	strmhz(buf, gd->arch.qe_clk));
1206c184 SG	515	printf(" BRG: %-4s MHz\n",
1206c184 SG	516	strmhz(buf, gd->arch.brg_clk));
5f820439	517	#endif
c6731fe2 SG	518	printf(" Local Bus Controller:%-4s MHz\n",
	519	strmhz(buf, gd->arch.lbiu_clk));
	520	printf(" Local Bus: %-4s MHz\n",
	521	strmhz(buf, gd->arch.lclk_clk));
08ef89ec	522	printf(" DDR: %-4s MHz\n", strmhz(buf, gd->mem_clk));
61abced7	523	#if defined(CONFIG_ARCH_MPC8360)
c6731fe2 SG	524	printf(" DDR Secondary: %-4s MHz\n",
c6731fe2 SG	525	strmhz(buf, gd->arch.mem_sec_clk));
5f820439	526	#endif
4bc97a3b	527	#if !defined(CONFIG_ARCH_MPC8309)
c6731fe2 SG	528	printf(" SEC: %-4s MHz\n",
c6731fe2 SG	529	strmhz(buf, gd->arch.enc_clk));
a88731a6	530	#endif
609e6ec3 SG	531	printf(" I2C1: %-4s MHz\n",
609e6ec3 SG	532	strmhz(buf, gd->arch.i2c1_clk));
bd3b867e	533	#if !defined(CONFIG_ARCH_MPC832X)
609e6ec3 SG	534	printf(" I2C2: %-4s MHz\n",
609e6ec3 SG	535	strmhz(buf, gd->arch.i2c2_clk));
24c3aca3	536	#endif
27ef578d	537	#if defined(CONFIG_FSL_ESDHC)
e9adeca3 SG	538	printf(" SDHC: %-4s MHz\n",
e9adeca3 SG	539	strmhz(buf, gd->arch.sdhc_clk));
03051c3d	540	#endif
9403fc41	541	#if defined(CONFIG_ARCH_MPC8308) \|\| defined(CONFIG_ARCH_MPC831X) \|\| \
8439e99d	542	defined(CONFIG_ARCH_MPC834X) \|\| defined(CONFIG_ARCH_MPC837X)
c6731fe2 SG	543	printf(" TSEC1: %-4s MHz\n",
	544	strmhz(buf, gd->arch.tsec1_clk));
	545	printf(" TSEC2: %-4s MHz\n",
	546	strmhz(buf, gd->arch.tsec2_clk));
	547	printf(" USB DR: %-4s MHz\n",
	548	strmhz(buf, gd->arch.usbdr_clk));
4bc97a3b	549	#elif defined(CONFIG_ARCH_MPC8309)
c6731fe2 SG	550	printf(" USB DR: %-4s MHz\n",
c6731fe2 SG	551	strmhz(buf, gd->arch.usbdr_clk));
7c98e519	552	#endif
d5cfa4aa	553	#if defined(CONFIG_ARCH_MPC834X)
c6731fe2 SG	554	printf(" USB MPH: %-4s MHz\n",
c6731fe2 SG	555	strmhz(buf, gd->arch.usbmph_clk));
03051c3d	556	#endif
9403fc41	557	#if defined(CONFIG_ARCH_MPC8308) \|\| defined(CONFIG_ARCH_MPC831X) \|\| \
8439e99d	558	defined(CONFIG_ARCH_MPC837X)
c6731fe2 SG	559	printf(" PCIEXP1: %-4s MHz\n",
	560	strmhz(buf, gd->arch.pciexp1_clk));
	561	printf(" PCIEXP2: %-4s MHz\n",
	562	strmhz(buf, gd->arch.pciexp2_clk));
555da617	563	#endif
139ff3be	564	#if defined(CONFIG_ARCH_MPC837X)
c6731fe2 SG	565	printf(" SATA: %-4s MHz\n",
c6731fe2 SG	566	strmhz(buf, gd->arch.sata_clk));
5f820439	567	#endif
de1d0a69	568	return 0;
f046ccd1	569	}
54b2d434 KP	570
54b2d434 KP	571	U_BOOT_CMD(clocks, 1, 0, do_clocks,
2fb2604d	572	"print clock configuration",
a89c33db	573	" clocks"
54b2d434	574	);
07d538d2 MS	575
07d538d2 MS	576	#endif