]> Git Repo - J-u-boot.git/blame - board/toradex/colibri_imx6/colibri_imx6.c
projects / J-u-boot.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge branch '2021-03-03-assorted-improvements' into next
[J-u-boot.git] / board / toradex / colibri_imx6 / colibri_imx6.c
CommitLineData
83d290c5 1// SPDX-License-Identifier: GPL-2.0+
a02d517b
MK		 2/*
3 * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
4 * Copyright (C) 2013, Boundary Devices <[email protected]>
e7cf5349 5 * Copyright (C) 2014-2019, Toradex AG
a02d517b 6 * copied from nitrogen6x
a02d517b
MK		 7 */
8
9#include <common.h>
9a3b4ceb 10#include <cpu_func.h>
9d922450 11#include <dm.h>
9eef56db 12#include <env.h>
5255932f 13#include <init.h>
90526e9f 14#include <net.h>
401d1c4f 15#include <asm/global_data.h>
cd93d625 16#include <linux/bitops.h>
c05ed00a 17#include <linux/delay.h>
e7cf5349 18
a02d517b
MK		 19#include <asm/arch/clock.h>
20#include <asm/arch/crm_regs.h>
21#include <asm/arch/imx-regs.h>
a02d517b 22#include <asm/arch/mx6-ddr.h>
e7cf5349 23#include <asm/arch/mx6-pins.h>
a02d517b
MK		 24#include <asm/arch/mxc_hdmi.h>
25#include <asm/arch/sys_proto.h>
26#include <asm/bootm.h>
27#include <asm/gpio.h>
e7cf5349 28#include <asm/mach-imx/boot_mode.h>
552a848e 29#include <asm/mach-imx/iomux-v3.h>
552a848e 30#include <asm/mach-imx/sata.h>
552a848e 31#include <asm/mach-imx/video.h>
bee73083 32#include <cpu.h>
a02d517b 33#include <dm/platform_data/serial_mxc.h>
e37ac717 34#include <fsl_esdhc_imx.h>
a02d517b 35#include <imx_thermal.h>
a02d517b 36#include <miiphy.h>
a02d517b 37#include <netdev.h>
82029bf5 38#include <cpu.h>
a02d517b
MK		 39
40#include "../common/tdx-cfg-block.h"
41#ifdef CONFIG_TDX_CMD_IMX_MFGR
42#include "pf0100.h"
43#endif
44
45DECLARE_GLOBAL_DATA_PTR;
46
47#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
48 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
49 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
50
51#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
eaa50e08
MK		 52 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm | \
53 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
54
55#define USDHC_EMMC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
a02d517b
MK		 56 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
57 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
58
a02d517b
MK		 59#define WEAK_PULLUP (PAD_CTL_PUS_100K_UP | \
60 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
61 PAD_CTL_SRE_SLOW)
62
63#define NO_PULLUP ( \
64 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
65 PAD_CTL_SRE_SLOW)
66
67#define WEAK_PULLDOWN (PAD_CTL_PUS_100K_DOWN | \
68 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
69 PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
70
a02d517b
MK		 71#define OUTPUT_RGB (PAD_CTL_SPEED_MED|PAD_CTL_DSE_60ohm|PAD_CTL_SRE_FAST)
72
73int dram_init(void)
74{
75 /* use the DDR controllers configured size */
76 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
77 (ulong)imx_ddr_size());
78
79 return 0;
80}
81
82/* Colibri UARTA */
83iomux_v3_cfg_t const uart1_pads[] = {
84 MX6_PAD_CSI0_DAT10__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
85 MX6_PAD_CSI0_DAT11__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
86};
87
bfeaea7d 88#if defined(CONFIG_FSL_ESDHC_IMX) && defined(CONFIG_SPL_BUILD)
6eea69bd 89/* Colibri MMC */
a02d517b
MK		 90iomux_v3_cfg_t const usdhc1_pads[] = {
91 MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
92 MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
93 MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
94 MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
95 MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
96 MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
97 MX6_PAD_NANDF_D5__GPIO2_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
98# define GPIO_MMC_CD IMX_GPIO_NR(2, 5)
99};
100
101/* eMMC */
102iomux_v3_cfg_t const usdhc3_pads[] = {
eaa50e08
MK		 103 MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
104 MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
105 MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
106 MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
107 MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
108 MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
109 MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
110 MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
111 MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
112 MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
a02d517b
MK		 113 MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL),
114};
e37ac717 115#endif /* CONFIG_FSL_ESDHC_IMX & CONFIG_SPL_BUILD */
a02d517b 116
a02d517b
MK		 117/* mux auxiliary pins to GPIO, so they can be used from the U-Boot cmdline */
118iomux_v3_cfg_t const gpio_pads[] = {
119 /* ADDRESS[17:18] [25] used as GPIO */
e7cf5349
MZ		 120 MX6_PAD_KEY_ROW2__GPIO4_IO11 | MUX_PAD_CTRL(WEAK_PULLUP) |
121 MUX_MODE_SION,
122 MX6_PAD_KEY_COL2__GPIO4_IO10 | MUX_PAD_CTRL(WEAK_PULLUP) |
123 MUX_MODE_SION,
124 MX6_PAD_NANDF_D1__GPIO2_IO01 | MUX_PAD_CTRL(WEAK_PULLUP) |
125 MUX_MODE_SION,
a02d517b 126 /* ADDRESS[19:24] used as GPIO */
e7cf5349
MZ		 127 MX6_PAD_DISP0_DAT23__GPIO5_IO17 | MUX_PAD_CTRL(WEAK_PULLUP) |
128 MUX_MODE_SION,
129 MX6_PAD_DISP0_DAT22__GPIO5_IO16 | MUX_PAD_CTRL(WEAK_PULLUP) |
130 MUX_MODE_SION,
131 MX6_PAD_DISP0_DAT21__GPIO5_IO15 | MUX_PAD_CTRL(WEAK_PULLUP) |
132 MUX_MODE_SION,
133 MX6_PAD_DISP0_DAT20__GPIO5_IO14 | MUX_PAD_CTRL(WEAK_PULLUP) |
134 MUX_MODE_SION,
135 MX6_PAD_DISP0_DAT19__GPIO5_IO13 | MUX_PAD_CTRL(WEAK_PULLUP) |
136 MUX_MODE_SION,
137 MX6_PAD_DISP0_DAT18__GPIO5_IO12 | MUX_PAD_CTRL(WEAK_PULLUP) |
138 MUX_MODE_SION,
a02d517b 139 /* DATA[16:29] [31] used as GPIO */
e7cf5349
MZ		 140 MX6_PAD_EIM_LBA__GPIO2_IO27 | MUX_PAD_CTRL(WEAK_PULLUP) |
141 MUX_MODE_SION,
142 MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(WEAK_PULLUP) |
143 MUX_MODE_SION,
144 MX6_PAD_NANDF_CS3__GPIO6_IO16 | MUX_PAD_CTRL(WEAK_PULLUP) |
145 MUX_MODE_SION,
146 MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(WEAK_PULLUP) |
147 MUX_MODE_SION,
148 MX6_PAD_NANDF_RB0__GPIO6_IO10 | MUX_PAD_CTRL(WEAK_PULLUP) |
149 MUX_MODE_SION,
150 MX6_PAD_NANDF_ALE__GPIO6_IO08 | MUX_PAD_CTRL(WEAK_PULLUP) |
151 MUX_MODE_SION,
152 MX6_PAD_NANDF_WP_B__GPIO6_IO09 | MUX_PAD_CTRL(WEAK_PULLUP) |
153 MUX_MODE_SION,
154 MX6_PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(WEAK_PULLUP) |
155 MUX_MODE_SION,
156 MX6_PAD_NANDF_CLE__GPIO6_IO07 | MUX_PAD_CTRL(WEAK_PULLUP) |
157 MUX_MODE_SION,
158 MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(WEAK_PULLUP) |
159 MUX_MODE_SION,
160 MX6_PAD_CSI0_MCLK__GPIO5_IO19 | MUX_PAD_CTRL(WEAK_PULLUP) |
161 MUX_MODE_SION,
162 MX6_PAD_CSI0_PIXCLK__GPIO5_IO18 | MUX_PAD_CTRL(WEAK_PULLUP) |
163 MUX_MODE_SION,
164 MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(WEAK_PULLUP) |
165 MUX_MODE_SION,
166 MX6_PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(WEAK_PULLUP) |
167 MUX_MODE_SION,
168 MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(WEAK_PULLUP) |
169 MUX_MODE_SION,
a02d517b 170 /* DQM[0:3] used as GPIO */
e7cf5349
MZ		 171 MX6_PAD_EIM_EB0__GPIO2_IO28 | MUX_PAD_CTRL(WEAK_PULLUP) |
172 MUX_MODE_SION,
173 MX6_PAD_EIM_EB1__GPIO2_IO29 | MUX_PAD_CTRL(WEAK_PULLUP) |
174 MUX_MODE_SION,
175 MX6_PAD_SD2_DAT2__GPIO1_IO13 | MUX_PAD_CTRL(WEAK_PULLUP) |
176 MUX_MODE_SION,
177 MX6_PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(WEAK_PULLUP) |
178 MUX_MODE_SION,
a02d517b 179 /* RDY used as GPIO */
e7cf5349
MZ		 180 MX6_PAD_EIM_WAIT__GPIO5_IO00 | MUX_PAD_CTRL(WEAK_PULLUP) |
181 MUX_MODE_SION,
a02d517b 182 /* ADDRESS[16] DATA[30] used as GPIO */
e7cf5349
MZ		 183 MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(WEAK_PULLDOWN) |
184 MUX_MODE_SION,
185 MX6_PAD_KEY_COL4__GPIO4_IO14 | MUX_PAD_CTRL(WEAK_PULLUP) |
186 MUX_MODE_SION,
a02d517b 187 /* CSI pins used as GPIO */
e7cf5349
MZ		 188 MX6_PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(WEAK_PULLUP) |
189 MUX_MODE_SION,
190 MX6_PAD_SD2_CMD__GPIO1_IO11 | MUX_PAD_CTRL(WEAK_PULLUP) |
191 MUX_MODE_SION,
192 MX6_PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(WEAK_PULLUP) |
193 MUX_MODE_SION,
194 MX6_PAD_EIM_D18__GPIO3_IO18 | MUX_PAD_CTRL(WEAK_PULLUP) |
195 MUX_MODE_SION,
196 MX6_PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(WEAK_PULLUP) |
197 MUX_MODE_SION,
198 MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(WEAK_PULLDOWN) |
199 MUX_MODE_SION,
200 MX6_PAD_EIM_A23__GPIO6_IO06 | MUX_PAD_CTRL(WEAK_PULLUP) |
201 MUX_MODE_SION,
202 MX6_PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(WEAK_PULLUP) |
203 MUX_MODE_SION,
204 MX6_PAD_EIM_A17__GPIO2_IO21 | MUX_PAD_CTRL(WEAK_PULLUP) |
205 MUX_MODE_SION,
206 MX6_PAD_EIM_A18__GPIO2_IO20 | MUX_PAD_CTRL(WEAK_PULLUP) |
207 MUX_MODE_SION,
208 MX6_PAD_EIM_EB3__GPIO2_IO31 | MUX_PAD_CTRL(WEAK_PULLUP) |
209 MUX_MODE_SION,
210 MX6_PAD_EIM_D17__GPIO3_IO17 | MUX_PAD_CTRL(WEAK_PULLUP) |
211 MUX_MODE_SION,
212 MX6_PAD_SD2_DAT0__GPIO1_IO15 | MUX_PAD_CTRL(WEAK_PULLUP) |
213 MUX_MODE_SION,
a02d517b 214 /* GPIO */
e7cf5349
MZ		 215 MX6_PAD_EIM_D26__GPIO3_IO26 | MUX_PAD_CTRL(WEAK_PULLUP) |
216 MUX_MODE_SION,
217 MX6_PAD_EIM_D27__GPIO3_IO27 | MUX_PAD_CTRL(WEAK_PULLUP) |
218 MUX_MODE_SION,
219 MX6_PAD_NANDF_D6__GPIO2_IO06 | MUX_PAD_CTRL(WEAK_PULLUP) |
220 MUX_MODE_SION,
221 MX6_PAD_NANDF_D3__GPIO2_IO03 | MUX_PAD_CTRL(WEAK_PULLUP) |
222 MUX_MODE_SION,
223 MX6_PAD_ENET_REF_CLK__GPIO1_IO23 | MUX_PAD_CTRL(WEAK_PULLUP) |
224 MUX_MODE_SION,
225 MX6_PAD_DI0_PIN4__GPIO4_IO20 | MUX_PAD_CTRL(WEAK_PULLUP) |
226 MUX_MODE_SION,
227 MX6_PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(WEAK_PULLUP) |
228 MUX_MODE_SION,
229 MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(WEAK_PULLUP) |
230 MUX_MODE_SION,
231 MX6_PAD_SD4_DAT0__GPIO2_IO08 | MUX_PAD_CTRL(WEAK_PULLUP) |
232 MUX_MODE_SION,
233 MX6_PAD_GPIO_7__GPIO1_IO07 | MUX_PAD_CTRL(WEAK_PULLUP) |
234 MUX_MODE_SION,
235 MX6_PAD_GPIO_8__GPIO1_IO08 | MUX_PAD_CTRL(WEAK_PULLUP) |
236 MUX_MODE_SION,
a02d517b
MK		 237 /* USBH_OC */
238 MX6_PAD_EIM_D30__GPIO3_IO30 | MUX_PAD_CTRL(WEAK_PULLUP),
239 /* USBC_ID */
240 MX6_PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(WEAK_PULLUP),
241 /* USBC_DET */
242 MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(WEAK_PULLUP),
243};
244
245static void setup_iomux_gpio(void)
246{
247 imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads));
248}
249
250iomux_v3_cfg_t const usb_pads[] = {
e7cf5349
MZ		 251 /* USBH_PEN */
252 MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL) | MUX_MODE_SION,
a02d517b
MK		 253# define GPIO_USBH_EN IMX_GPIO_NR(3, 31)
254};
255
256/*
257 * UARTs are used in DTE mode, switch the mode on all UARTs before
258 * any pinmuxing connects a (DCE) output to a transceiver output.
259 */
08621424
MK		 260#define UCR3 0x88 /* FIFO Control Register */
261#define UCR3_RI BIT(8) /* RIDELT DTE mode */
262#define UCR3_DCD BIT(9) /* DCDDELT DTE mode */
a02d517b 263#define UFCR 0x90 /* FIFO Control Register */
08621424 264#define UFCR_DCEDTE BIT(6) /* DCE=0 */
a02d517b
MK		 265
266static void setup_dtemode_uart(void)
267{
268 setbits_le32((u32 *)(UART1_BASE + UFCR), UFCR_DCEDTE);
269 setbits_le32((u32 *)(UART2_BASE + UFCR), UFCR_DCEDTE);
270 setbits_le32((u32 *)(UART3_BASE + UFCR), UFCR_DCEDTE);
08621424
MK		 271
272 clrbits_le32((u32 *)(UART1_BASE + UCR3), UCR3_DCD | UCR3_RI);
273 clrbits_le32((u32 *)(UART2_BASE + UCR3), UCR3_DCD | UCR3_RI);
274 clrbits_le32((u32 *)(UART3_BASE + UCR3), UCR3_DCD | UCR3_RI);
a02d517b
MK		 275}
276
277static void setup_iomux_uart(void)
278{
279 setup_dtemode_uart();
280 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
281}
282
283#ifdef CONFIG_USB_EHCI_MX6
284int board_ehci_hcd_init(int port)
285{
286 imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
287 return 0;
288}
7b726c09 289#endif
a02d517b 290
bfeaea7d 291#if defined(CONFIG_FSL_ESDHC_IMX) && defined(CONFIG_SPL_BUILD)
a02d517b
MK		 292/* use the following sequence: eMMC, MMC */
293struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = {
294 {USDHC3_BASE_ADDR},
295 {USDHC1_BASE_ADDR},
296};
297
298int board_mmc_getcd(struct mmc *mmc)
299{
300 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
301 int ret = true; /* default: assume inserted */
302
303 switch (cfg->esdhc_base) {
304 case USDHC1_BASE_ADDR:
e7cf5349 305 gpio_request(GPIO_MMC_CD, "MMC_CD");
a02d517b
MK		 306 gpio_direction_input(GPIO_MMC_CD);
307 ret = !gpio_get_value(GPIO_MMC_CD);
308 break;
309 }
310
311 return ret;
312}
313
b75d8dc5 314int board_mmc_init(struct bd_info *bis)
a02d517b 315{
a02d517b
MK		 316 struct src *psrc = (struct src *)SRC_BASE_ADDR;
317 unsigned reg = readl(&psrc->sbmr1) >> 11;
318 /*
319 * Upon reading BOOT_CFG register the following map is done:
320 * Bit 11 and 12 of BOOT_CFG register can determine the current
321 * mmc port
322 * 0x1 SD1
323 * 0x2 SD2
324 * 0x3 SD4
325 */
326
327 switch (reg & 0x3) {
328 case 0x0:
329 imx_iomux_v3_setup_multiple_pads(
330 usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
331 usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR;
332 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
333 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
334 break;
335 case 0x2:
336 imx_iomux_v3_setup_multiple_pads(
337 usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
338 usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
339 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
340 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
341 break;
342 default:
343 puts("MMC boot device not available");
344 }
345
346 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
a02d517b 347}
e37ac717 348#endif /* CONFIG_FSL_ESDHC_IMX & CONFIG_SPL_BUILD */
a02d517b
MK		 349
350int board_phy_config(struct phy_device *phydev)
351{
352 if (phydev->drv->config)
353 phydev->drv->config(phydev);
354
355 return 0;
356}
357
431cd76d 358int setup_fec(void)
a02d517b 359{
a02d517b 360 int ret;
1efb80c4 361 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
a02d517b
MK		 362
363 /* provide the PHY clock from the i.MX 6 */
364 ret = enable_fec_anatop_clock(0, ENET_50MHZ);
365 if (ret)
366 return ret;
e7cf5349 367
1efb80c4
IO		 368 setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
369
a02d517b
MK		 370 return 0;
371}
372
373static iomux_v3_cfg_t const pwr_intb_pads[] = {
374 /*
375 * the bootrom sets the iomux to vselect, potentially connecting
376 * two outputs. Set this back to GPIO
377 */
378 MX6_PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL)
379};
380
381#if defined(CONFIG_VIDEO_IPUV3)
382
383static iomux_v3_cfg_t const backlight_pads[] = {
384 /* Backlight On */
e7cf5349 385 MX6_PAD_EIM_D26__GPIO3_IO26 | MUX_PAD_CTRL(NO_PAD_CTRL) | MUX_MODE_SION,
a02d517b
MK		 386#define RGB_BACKLIGHT_GP IMX_GPIO_NR(3, 26)
387 /* Backlight PWM, used as GPIO in U-Boot */
388 MX6_PAD_EIM_A22__GPIO2_IO16 | MUX_PAD_CTRL(NO_PULLUP),
e7cf5349
MZ		 389 MX6_PAD_SD4_DAT1__GPIO2_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL) |
390 MUX_MODE_SION,
a02d517b
MK		 391#define RGB_BACKLIGHTPWM_GP IMX_GPIO_NR(2, 9)
392};
393
394static iomux_v3_cfg_t const rgb_pads[] = {
395 MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(OUTPUT_RGB),
396 MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 | MUX_PAD_CTRL(OUTPUT_RGB),
397 MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02 | MUX_PAD_CTRL(OUTPUT_RGB),
398 MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03 | MUX_PAD_CTRL(OUTPUT_RGB),
399 MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 | MUX_PAD_CTRL(OUTPUT_RGB),
400 MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 | MUX_PAD_CTRL(OUTPUT_RGB),
401 MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 | MUX_PAD_CTRL(OUTPUT_RGB),
402 MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 | MUX_PAD_CTRL(OUTPUT_RGB),
403 MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 | MUX_PAD_CTRL(OUTPUT_RGB),
404 MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 | MUX_PAD_CTRL(OUTPUT_RGB),
405 MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 | MUX_PAD_CTRL(OUTPUT_RGB),
406 MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 | MUX_PAD_CTRL(OUTPUT_RGB),
407 MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 | MUX_PAD_CTRL(OUTPUT_RGB),
408 MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 | MUX_PAD_CTRL(OUTPUT_RGB),
409 MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 | MUX_PAD_CTRL(OUTPUT_RGB),
410 MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 | MUX_PAD_CTRL(OUTPUT_RGB),
411 MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 | MUX_PAD_CTRL(OUTPUT_RGB),
412 MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 | MUX_PAD_CTRL(OUTPUT_RGB),
413 MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 | MUX_PAD_CTRL(OUTPUT_RGB),
414 MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 | MUX_PAD_CTRL(OUTPUT_RGB),
415 MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 | MUX_PAD_CTRL(OUTPUT_RGB),
416 MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 | MUX_PAD_CTRL(OUTPUT_RGB),
417};
418
419static void do_enable_hdmi(struct display_info_t const *dev)
420{
421 imx_enable_hdmi_phy();
422}
423
424static void enable_rgb(struct display_info_t const *dev)
425{
426 imx_iomux_v3_setup_multiple_pads(
427 rgb_pads,
428 ARRAY_SIZE(rgb_pads));
429 gpio_direction_output(RGB_BACKLIGHT_GP, 1);
430 gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
431}
432
433static int detect_default(struct display_info_t const *dev)
434{
435 (void) dev;
436 return 1;
437}
438
439struct display_info_t const displays[] = {{
440 .bus = -1,
441 .addr = 0,
442 .pixfmt = IPU_PIX_FMT_RGB24,
443 .detect = detect_hdmi,
444 .enable = do_enable_hdmi,
445 .mode = {
446 .name = "HDMI",
447 .refresh = 60,
448 .xres = 1024,
449 .yres = 768,
450 .pixclock = 15385,
451 .left_margin = 220,
452 .right_margin = 40,
453 .upper_margin = 21,
454 .lower_margin = 7,
455 .hsync_len = 60,
456 .vsync_len = 10,
457 .sync = FB_SYNC_EXT,
458 .vmode = FB_VMODE_NONINTERLACED
459} }, {
460 .bus = -1,
461 .addr = 0,
462 .pixfmt = IPU_PIX_FMT_RGB666,
463 .detect = detect_default,
464 .enable = enable_rgb,
465 .mode = {
466 .name = "vga-rgb",
467 .refresh = 60,
468 .xres = 640,
469 .yres = 480,
470 .pixclock = 33000,
471 .left_margin = 48,
472 .right_margin = 16,
473 .upper_margin = 31,
474 .lower_margin = 11,
475 .hsync_len = 96,
476 .vsync_len = 2,
477 .sync = 0,
478 .vmode = FB_VMODE_NONINTERLACED
479} }, {
480 .bus = -1,
481 .addr = 0,
482 .pixfmt = IPU_PIX_FMT_RGB666,
483 .enable = enable_rgb,
484 .mode = {
485 .name = "wvga-rgb",
486 .refresh = 60,
487 .xres = 800,
488 .yres = 480,
489 .pixclock = 25000,
490 .left_margin = 40,
491 .right_margin = 88,
492 .upper_margin = 33,
493 .lower_margin = 10,
494 .hsync_len = 128,
495 .vsync_len = 2,
496 .sync = 0,
497 .vmode = FB_VMODE_NONINTERLACED
498} } };
499size_t display_count = ARRAY_SIZE(displays);
500
501static void setup_display(void)
502{
503 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
504 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
505 int reg;
506
507 enable_ipu_clock();
508 imx_setup_hdmi();
509 /* Turn on LDB0,IPU,IPU DI0 clocks */
510 reg = __raw_readl(&mxc_ccm->CCGR3);
511 reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
512 writel(reg, &mxc_ccm->CCGR3);
513
514 /* set LDB0, LDB1 clk select to 011/011 */
515 reg = readl(&mxc_ccm->cs2cdr);
516 reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
517 |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
518 reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
519 |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
520 writel(reg, &mxc_ccm->cs2cdr);
521
522 reg = readl(&mxc_ccm->cscmr2);
523 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
524 writel(reg, &mxc_ccm->cscmr2);
525
526 reg = readl(&mxc_ccm->chsccdr);
527 reg |= (CHSCCDR_CLK_SEL_LDB_DI0
528 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
529 writel(reg, &mxc_ccm->chsccdr);
530
531 reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
532 |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
533 |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
534 |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
535 |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
536 |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
537 |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
538 |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
539 |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
540 writel(reg, &iomux->gpr[2]);
541
542 reg = readl(&iomux->gpr[3]);
543 reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK
544 |IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
545 | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
546 <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
547 writel(reg, &iomux->gpr[3]);
548
549 /* backlight unconditionally on for now */
550 imx_iomux_v3_setup_multiple_pads(backlight_pads,
551 ARRAY_SIZE(backlight_pads));
552 /* use 0 for EDT 7", use 1 for LG fullHD panel */
e7cf5349
MZ		 553 gpio_request(RGB_BACKLIGHTPWM_GP, "PWM<A>");
554 gpio_request(RGB_BACKLIGHT_GP, "BL_ON");
a02d517b
MK		 555 gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
556 gpio_direction_output(RGB_BACKLIGHT_GP, 1);
557}
a3c90217
GS		 558
559/*
560 * Backlight off before OS handover
561 */
562void board_preboot_os(void)
563{
564 gpio_direction_output(RGB_BACKLIGHTPWM_GP, 1);
565 gpio_direction_output(RGB_BACKLIGHT_GP, 0);
566}
a02d517b
MK		 567#endif /* defined(CONFIG_VIDEO_IPUV3) */
568
569int board_early_init_f(void)
570{
571 imx_iomux_v3_setup_multiple_pads(pwr_intb_pads,
572 ARRAY_SIZE(pwr_intb_pads));
573 setup_iomux_uart();
574
a02d517b
MK		 575 return 0;
576}
577
578/*
579 * Do not overwrite the console
580 * Use always serial for U-Boot console
581 */
582int overwrite_console(void)
583{
584 return 1;
585}
586
587int board_init(void)
588{
589 /* address of boot parameters */
590 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
431cd76d
IO		 591#if defined(CONFIG_FEC_MXC)
592 setup_fec();
593#endif
464c988a
FE		 594#if defined(CONFIG_VIDEO_IPUV3)
595 setup_display();
596#endif
597
a02d517b
MK		 598#ifdef CONFIG_TDX_CMD_IMX_MFGR
599 (void) pmic_init();
600#endif
601
10e40d54 602#ifdef CONFIG_SATA
a02d517b
MK		 603 setup_sata();
604#endif
605
606 setup_iomux_gpio();
607
608 return 0;
609}
610
611#ifdef CONFIG_BOARD_LATE_INIT
612int board_late_init(void)
613{
614#if defined(CONFIG_REVISION_TAG) && \
615 defined(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)
616 char env_str[256];
617 u32 rev;
618
619 rev = get_board_rev();
620 snprintf(env_str, ARRAY_SIZE(env_str), "%.4x", rev);
382bee57 621 env_set("board_rev", env_str);
a02d517b
MK		 622#endif
623
52084bfc
SA		 624#ifdef CONFIG_CMD_USB_SDP
625 if (is_boot_from_usb()) {
626 printf("Serial Downloader recovery mode, using sdp command\n");
627 env_set("bootdelay", "0");
628 env_set("bootcmd", "sdp 0");
629 }
630#endif /* CONFIG_CMD_USB_SDP */
631
a02d517b
MK		 632 return 0;
633}
634#endif /* CONFIG_BOARD_LATE_INIT */
635
a02d517b
MK		 636int checkboard(void)
637{
638 char it[] = " IT";
639 int minc, maxc;
640
641 switch (get_cpu_temp_grade(&minc, &maxc)) {
642 case TEMP_AUTOMOTIVE:
643 case TEMP_INDUSTRIAL:
644 break;
645 case TEMP_EXTCOMMERCIAL:
646 default:
647 it[0] = 0;
648 };
649 printf("Model: Toradex Colibri iMX6 %s %sMB%s\n",
650 is_cpu_type(MXC_CPU_MX6DL) ? "DualLite" : "Solo",
651 (gd->ram_size == 0x20000000) ? "512" : "256", it);
652 return 0;
653}
654
655#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
b75d8dc5 656int ft_board_setup(void *blob, struct bd_info *bd)
a02d517b 657{
bee73083
BD		 658 u32 cma_size;
659
660 ft_common_board_setup(blob, bd);
661
52084bfc 662 cma_size = env_get_ulong("cma-size", 10, 320 * 1024 * 1024);
bee73083
BD		 663 cma_size = min((u32)(gd->ram_size >> 1), cma_size);
664
665 fdt_setprop_u32(blob,
666 fdt_path_offset(blob, "/reserved-memory/linux,cma"),
667 "size",
668 cma_size);
669 return 0;
a02d517b
MK		 670}
671#endif
672
673#ifdef CONFIG_CMD_BMODE
674static const struct boot_mode board_boot_modes[] = {
675 {"mmc", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
676 {NULL, 0},
677};
678#endif
679
680int misc_init_r(void)
681{
682#ifdef CONFIG_CMD_BMODE
683 add_board_boot_modes(board_boot_modes);
684#endif
685 return 0;
686}
687
688#ifdef CONFIG_LDO_BYPASS_CHECK
689/* TODO, use external pmic, for now always ldo_enable */
690void ldo_mode_set(int ldo_bypass)
691{
692 return;
693}
694#endif
695
696#ifdef CONFIG_SPL_BUILD
697#include <spl.h>
b08c8c48 698#include <linux/libfdt.h>
a02d517b
MK		 699#include "asm/arch/mx6dl-ddr.h"
700#include "asm/arch/iomux.h"
701#include "asm/arch/crm_regs.h"
702
703static int mx6s_dcd_table[] = {
704/* ddr-setup.cfg */
705
706MX6_IOM_DRAM_SDQS0, 0x00000030,
707MX6_IOM_DRAM_SDQS1, 0x00000030,
708MX6_IOM_DRAM_SDQS2, 0x00000030,
709MX6_IOM_DRAM_SDQS3, 0x00000030,
710MX6_IOM_DRAM_SDQS4, 0x00000030,
711MX6_IOM_DRAM_SDQS5, 0x00000030,
712MX6_IOM_DRAM_SDQS6, 0x00000030,
713MX6_IOM_DRAM_SDQS7, 0x00000030,
714
715MX6_IOM_GRP_B0DS, 0x00000030,
716MX6_IOM_GRP_B1DS, 0x00000030,
717MX6_IOM_GRP_B2DS, 0x00000030,
718MX6_IOM_GRP_B3DS, 0x00000030,
719MX6_IOM_GRP_B4DS, 0x00000030,
720MX6_IOM_GRP_B5DS, 0x00000030,
721MX6_IOM_GRP_B6DS, 0x00000030,
722MX6_IOM_GRP_B7DS, 0x00000030,
723MX6_IOM_GRP_ADDDS, 0x00000030,
724/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
725MX6_IOM_GRP_CTLDS, 0x00000030,
726
727MX6_IOM_DRAM_DQM0, 0x00020030,
728MX6_IOM_DRAM_DQM1, 0x00020030,
729MX6_IOM_DRAM_DQM2, 0x00020030,
730MX6_IOM_DRAM_DQM3, 0x00020030,
731MX6_IOM_DRAM_DQM4, 0x00020030,
732MX6_IOM_DRAM_DQM5, 0x00020030,
733MX6_IOM_DRAM_DQM6, 0x00020030,
734MX6_IOM_DRAM_DQM7, 0x00020030,
735
736MX6_IOM_DRAM_CAS, 0x00020030,
737MX6_IOM_DRAM_RAS, 0x00020030,
738MX6_IOM_DRAM_SDCLK_0, 0x00020030,
739MX6_IOM_DRAM_SDCLK_1, 0x00020030,
740
741MX6_IOM_DRAM_RESET, 0x00020030,
742MX6_IOM_DRAM_SDCKE0, 0x00003000,
743MX6_IOM_DRAM_SDCKE1, 0x00003000,
744
745MX6_IOM_DRAM_SDODT0, 0x00003030,
746MX6_IOM_DRAM_SDODT1, 0x00003030,
747
748/* (differential input) */
749MX6_IOM_DDRMODE_CTL, 0x00020000,
750/* (differential input) */
751MX6_IOM_GRP_DDRMODE, 0x00020000,
752/* disable ddr pullups */
753MX6_IOM_GRP_DDRPKE, 0x00000000,
754MX6_IOM_DRAM_SDBA2, 0x00000000,
755/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
756MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
757
758/* Read data DQ Byte0-3 delay */
759MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
760MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
761MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
762MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
763MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333,
764MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333,
765MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333,
766MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333,
767
768/*
769 * MDMISC mirroring interleaved (row/bank/col)
770 */
771/* TODO: check what the RALAT field does */
772MX6_MMDC_P0_MDMISC, 0x00081740,
773
774/*
775 * MDSCR con_req
776 */
777MX6_MMDC_P0_MDSCR, 0x00008000,
778
779
780/* 800mhz_2x64mx16.cfg */
781
782MX6_MMDC_P0_MDPDC, 0x0002002D,
783MX6_MMDC_P0_MDCFG0, 0x2C305503,
784MX6_MMDC_P0_MDCFG1, 0xB66D8D63,
785MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
786MX6_MMDC_P0_MDRWD, 0x000026D2,
787MX6_MMDC_P0_MDOR, 0x00301023,
788MX6_MMDC_P0_MDOTC, 0x00333030,
789MX6_MMDC_P0_MDPDC, 0x0002556D,
790/* CS0 End: 7MSB of ((0x10000000, + 512M) -1) >> 25 */
791MX6_MMDC_P0_MDASP, 0x00000017,
792/* DDR3 DATA BUS SIZE: 64BIT */
793/* MX6_MMDC_P0_MDCTL, 0x821A0000, */
794/* DDR3 DATA BUS SIZE: 32BIT */
795MX6_MMDC_P0_MDCTL, 0x82190000,
796
797/* Write commands to DDR */
798/* Load Mode Registers */
799/* TODO Use Auto Self-Refresh mode (Extended Temperature)*/
800/* MX6_MMDC_P0_MDSCR, 0x04408032, */
801MX6_MMDC_P0_MDSCR, 0x04008032,
802MX6_MMDC_P0_MDSCR, 0x00008033,
803MX6_MMDC_P0_MDSCR, 0x00048031,
804MX6_MMDC_P0_MDSCR, 0x13208030,
805/* ZQ calibration */
806MX6_MMDC_P0_MDSCR, 0x04008040,
807
808MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
809MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003,
810MX6_MMDC_P0_MDREF, 0x00005800,
811
812MX6_MMDC_P0_MPODTCTRL, 0x00000000,
813MX6_MMDC_P1_MPODTCTRL, 0x00000000,
814
815MX6_MMDC_P0_MPDGCTRL0, 0x42360232,
816MX6_MMDC_P0_MPDGCTRL1, 0x021F022A,
817MX6_MMDC_P1_MPDGCTRL0, 0x421E0224,
818MX6_MMDC_P1_MPDGCTRL1, 0x02110218,
819
820MX6_MMDC_P0_MPRDDLCTL, 0x41434344,
821MX6_MMDC_P1_MPRDDLCTL, 0x4345423E,
822MX6_MMDC_P0_MPWRDLCTL, 0x39383339,
823MX6_MMDC_P1_MPWRDLCTL, 0x3E363930,
824
825MX6_MMDC_P0_MPWLDECTRL0, 0x00340039,
826MX6_MMDC_P0_MPWLDECTRL1, 0x002C002D,
827MX6_MMDC_P1_MPWLDECTRL0, 0x00120019,
828MX6_MMDC_P1_MPWLDECTRL1, 0x0012002D,
829
830MX6_MMDC_P0_MPMUR0, 0x00000800,
831MX6_MMDC_P1_MPMUR0, 0x00000800,
832MX6_MMDC_P0_MDSCR, 0x00000000,
833MX6_MMDC_P0_MAPSR, 0x00011006,
834};
835
836static int mx6dl_dcd_table[] = {
837/* ddr-setup.cfg */
838
839MX6_IOM_DRAM_SDQS0, 0x00000030,
840MX6_IOM_DRAM_SDQS1, 0x00000030,
841MX6_IOM_DRAM_SDQS2, 0x00000030,
842MX6_IOM_DRAM_SDQS3, 0x00000030,
843MX6_IOM_DRAM_SDQS4, 0x00000030,
844MX6_IOM_DRAM_SDQS5, 0x00000030,
845MX6_IOM_DRAM_SDQS6, 0x00000030,
846MX6_IOM_DRAM_SDQS7, 0x00000030,
847
848MX6_IOM_GRP_B0DS, 0x00000030,
849MX6_IOM_GRP_B1DS, 0x00000030,
850MX6_IOM_GRP_B2DS, 0x00000030,
851MX6_IOM_GRP_B3DS, 0x00000030,
852MX6_IOM_GRP_B4DS, 0x00000030,
853MX6_IOM_GRP_B5DS, 0x00000030,
854MX6_IOM_GRP_B6DS, 0x00000030,
855MX6_IOM_GRP_B7DS, 0x00000030,
856MX6_IOM_GRP_ADDDS, 0x00000030,
857/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
858MX6_IOM_GRP_CTLDS, 0x00000030,
859
860MX6_IOM_DRAM_DQM0, 0x00020030,
861MX6_IOM_DRAM_DQM1, 0x00020030,
862MX6_IOM_DRAM_DQM2, 0x00020030,
863MX6_IOM_DRAM_DQM3, 0x00020030,
864MX6_IOM_DRAM_DQM4, 0x00020030,
865MX6_IOM_DRAM_DQM5, 0x00020030,
866MX6_IOM_DRAM_DQM6, 0x00020030,
867MX6_IOM_DRAM_DQM7, 0x00020030,
868
869MX6_IOM_DRAM_CAS, 0x00020030,
870MX6_IOM_DRAM_RAS, 0x00020030,
871MX6_IOM_DRAM_SDCLK_0, 0x00020030,
872MX6_IOM_DRAM_SDCLK_1, 0x00020030,
873
874MX6_IOM_DRAM_RESET, 0x00020030,
875MX6_IOM_DRAM_SDCKE0, 0x00003000,
876MX6_IOM_DRAM_SDCKE1, 0x00003000,
877
878MX6_IOM_DRAM_SDODT0, 0x00003030,
879MX6_IOM_DRAM_SDODT1, 0x00003030,
880
881/* (differential input) */
882MX6_IOM_DDRMODE_CTL, 0x00020000,
883/* (differential input) */
884MX6_IOM_GRP_DDRMODE, 0x00020000,
885/* disable ddr pullups */
886MX6_IOM_GRP_DDRPKE, 0x00000000,
887MX6_IOM_DRAM_SDBA2, 0x00000000,
888/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
889MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
890
891/* Read data DQ Byte0-3 delay */
892MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
893MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
894MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
895MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
896MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333,
897MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333,
898MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333,
899MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333,
900
901/*
902 * MDMISC mirroring interleaved (row/bank/col)
903 */
904/* TODO: check what the RALAT field does */
905MX6_MMDC_P0_MDMISC, 0x00081740,
906
907/*
908 * MDSCR con_req
909 */
910MX6_MMDC_P0_MDSCR, 0x00008000,
911
912
913/* 800mhz_2x64mx16.cfg */
914
915MX6_MMDC_P0_MDPDC, 0x0002002D,
916MX6_MMDC_P0_MDCFG0, 0x2C305503,
917MX6_MMDC_P0_MDCFG1, 0xB66D8D63,
918MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
919MX6_MMDC_P0_MDRWD, 0x000026D2,
920MX6_MMDC_P0_MDOR, 0x00301023,
921MX6_MMDC_P0_MDOTC, 0x00333030,
922MX6_MMDC_P0_MDPDC, 0x0002556D,
923/* CS0 End: 7MSB of ((0x10000000, + 512M) -1) >> 25 */
924MX6_MMDC_P0_MDASP, 0x00000017,
925/* DDR3 DATA BUS SIZE: 64BIT */
926MX6_MMDC_P0_MDCTL, 0x821A0000,
927/* DDR3 DATA BUS SIZE: 32BIT */
928/* MX6_MMDC_P0_MDCTL, 0x82190000, */
929
930/* Write commands to DDR */
931/* Load Mode Registers */
932/* TODO Use Auto Self-Refresh mode (Extended Temperature)*/
933/* MX6_MMDC_P0_MDSCR, 0x04408032, */
934MX6_MMDC_P0_MDSCR, 0x04008032,
935MX6_MMDC_P0_MDSCR, 0x00008033,
936MX6_MMDC_P0_MDSCR, 0x00048031,
937MX6_MMDC_P0_MDSCR, 0x13208030,
938/* ZQ calibration */
939MX6_MMDC_P0_MDSCR, 0x04008040,
940
941MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
942MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003,
943MX6_MMDC_P0_MDREF, 0x00005800,
944
945MX6_MMDC_P0_MPODTCTRL, 0x00000000,
946MX6_MMDC_P1_MPODTCTRL, 0x00000000,
947
948MX6_MMDC_P0_MPDGCTRL0, 0x42360232,
949MX6_MMDC_P0_MPDGCTRL1, 0x021F022A,
950MX6_MMDC_P1_MPDGCTRL0, 0x421E0224,
951MX6_MMDC_P1_MPDGCTRL1, 0x02110218,
952
953MX6_MMDC_P0_MPRDDLCTL, 0x41434344,
954MX6_MMDC_P1_MPRDDLCTL, 0x4345423E,
955MX6_MMDC_P0_MPWRDLCTL, 0x39383339,
956MX6_MMDC_P1_MPWRDLCTL, 0x3E363930,
957
958MX6_MMDC_P0_MPWLDECTRL0, 0x00340039,
959MX6_MMDC_P0_MPWLDECTRL1, 0x002C002D,
960MX6_MMDC_P1_MPWLDECTRL0, 0x00120019,
961MX6_MMDC_P1_MPWLDECTRL1, 0x0012002D,
962
963MX6_MMDC_P0_MPMUR0, 0x00000800,
964MX6_MMDC_P1_MPMUR0, 0x00000800,
965MX6_MMDC_P0_MDSCR, 0x00000000,
966MX6_MMDC_P0_MAPSR, 0x00011006,
967};
968
969static void ccgr_init(void)
970{
971 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
972
973 writel(0x00C03F3F, &ccm->CCGR0);
974 writel(0x0030FC03, &ccm->CCGR1);
975 writel(0x0FFFFFF3, &ccm->CCGR2);
976 writel(0x3FF0300F, &ccm->CCGR3);
977 writel(0x00FFF300, &ccm->CCGR4);
978 writel(0x0F0000F3, &ccm->CCGR5);
979 writel(0x000003FF, &ccm->CCGR6);
980
981/*
982 * Setup CCM_CCOSR register as follows:
983 *
984 * cko1_en = 1 --> CKO1 enabled
985 * cko1_div = 111 --> divide by 8
986 * cko1_sel = 1011 --> ahb_clk_root
987 *
988 * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
989 */
990 writel(0x000000FB, &ccm->ccosr);
991}
992
a02d517b
MK		 993static void ddr_init(int *table, int size)
994{
995 int i;
996
997 for (i = 0; i < size / 2 ; i++)
998 writel(table[2 * i + 1], table[2 * i]);
999}
1000
1001static void spl_dram_init(void)
1002{
1003 int minc, maxc;
1004
1005 switch (get_cpu_temp_grade(&minc, &maxc)) {
1006 case TEMP_COMMERCIAL:
1007 case TEMP_EXTCOMMERCIAL:
1008 if (is_cpu_type(MXC_CPU_MX6DL)) {
1009 puts("Commercial temperature grade DDR3 timings, 64bit bus width.\n");
1010 ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table));
1011 } else {
1012 puts("Commercial temperature grade DDR3 timings, 32bit bus width.\n");
1013 ddr_init(mx6s_dcd_table, ARRAY_SIZE(mx6s_dcd_table));
1014 }
1015 break;
1016 case TEMP_INDUSTRIAL:
1017 case TEMP_AUTOMOTIVE:
1018 default:
1019 if (is_cpu_type(MXC_CPU_MX6DL)) {
2910c0a1 1020 puts("Industrial temperature grade DDR3 timings, 64bit bus width.\n");
a02d517b
MK		 1021 ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table));
1022 } else {
1023 puts("Industrial temperature grade DDR3 timings, 32bit bus width.\n");
1024 ddr_init(mx6s_dcd_table, ARRAY_SIZE(mx6s_dcd_table));
1025 }
1026 break;
1027 };
1028 udelay(100);
1029}
1030
82029bf5
GS		 1031static iomux_v3_cfg_t const gpio_reset_pad[] = {
1032 MX6_PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL) |
1033 MUX_MODE_SION
1034#define GPIO_NRESET IMX_GPIO_NR(6, 27)
1035};
1036
1037#define IMX_RESET_CAUSE_POR 0x00011
1038static void nreset_out(void)
1039{
1040 int reset_cause = get_imx_reset_cause();
1041
1042 if (reset_cause != IMX_RESET_CAUSE_POR) {
1043 imx_iomux_v3_setup_multiple_pads(gpio_reset_pad,
1044 ARRAY_SIZE(gpio_reset_pad));
1045 gpio_direction_output(GPIO_NRESET, 1);
1046 udelay(100);
1047 gpio_direction_output(GPIO_NRESET, 0);
1048 }
1049}
1050
a02d517b
MK		 1051void board_init_f(ulong dummy)
1052{
1053 /* setup AIPS and disable watchdog */
1054 arch_cpu_init();
1055
1056 ccgr_init();
1057 gpr_init();
1058
6eea69bd 1059 /* iomux */
a02d517b
MK		 1060 board_early_init_f();
1061
1062 /* setup GP timer */
1063 timer_init();
1064
1065 /* UART clocks enabled and gd valid - init serial console */
1066 preloader_console_init();
1067
1068 /* Make sure we use dte mode */
1069 setup_dtemode_uart();
1070
1071 /* DDR initialization */
1072 spl_dram_init();
1073
1074 /* Clear the BSS. */
1075 memset(__bss_start, 0, __bss_end - __bss_start);
1076
82029bf5
GS		 1077 /* Assert nReset_Out */
1078 nreset_out();
1079
a02d517b
MK		 1080 /* load/boot image from boot device */
1081 board_init_r(NULL, 0);
1082}
1083
35b65dd8 1084void reset_cpu(void)
a02d517b
MK		 1085{
1086}
1087
e7cf5349 1088#endif /* CONFIG_SPL_BUILD */
a02d517b 1089
8a8d24bd 1090static struct mxc_serial_plat mxc_serial_plat = {
a02d517b
MK		 1091 .reg = (struct mxc_uart *)UART1_BASE,
1092 .use_dte = true,
1093};
1094
20e442ab 1095U_BOOT_DRVINFO(mxc_serial) = {
a02d517b 1096 .name = "serial_mxc",
caa4daa2 1097 .plat = &mxc_serial_plat,
a02d517b 1098};
Empty description
This page took 0.375227 seconds and 4 git commands to generate.