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colibri_imx6: drop CONFIG_OF_SYSTEM_SETUP
[J-u-boot.git] / board / toradex / colibri_imx6 / colibri_imx6.c
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83d290c5 1// SPDX-License-Identifier: GPL-2.0+
a02d517b
MK		 2/*
3 * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
4 * Copyright (C) 2013, Boundary Devices <[email protected]>
e7cf5349 5 * Copyright (C) 2014-2019, Toradex AG
a02d517b 6 * copied from nitrogen6x
a02d517b
MK		 7 */
8
9#include <common.h>
9d922450 10#include <dm.h>
e7cf5349 11
a02d517b
MK		 12#include <asm/arch/clock.h>
13#include <asm/arch/crm_regs.h>
14#include <asm/arch/imx-regs.h>
a02d517b 15#include <asm/arch/mx6-ddr.h>
e7cf5349 16#include <asm/arch/mx6-pins.h>
a02d517b
MK		 17#include <asm/arch/mxc_hdmi.h>
18#include <asm/arch/sys_proto.h>
19#include <asm/bootm.h>
20#include <asm/gpio.h>
e7cf5349 21#include <asm/mach-imx/boot_mode.h>
552a848e 22#include <asm/mach-imx/iomux-v3.h>
552a848e 23#include <asm/mach-imx/sata.h>
552a848e 24#include <asm/mach-imx/video.h>
a02d517b 25#include <dm/platform_data/serial_mxc.h>
e7cf5349 26#include <environment.h>
a02d517b 27#include <fsl_esdhc.h>
a02d517b 28#include <imx_thermal.h>
a02d517b
MK		 29#include <micrel.h>
30#include <miiphy.h>
a02d517b
MK		 31#include <netdev.h>
32
33#include "../common/tdx-cfg-block.h"
34#ifdef CONFIG_TDX_CMD_IMX_MFGR
35#include "pf0100.h"
36#endif
37
38DECLARE_GLOBAL_DATA_PTR;
39
40#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
41 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
42 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
43
44#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
45 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
46 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
47
48#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
49 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
50
a02d517b
MK		 51#define WEAK_PULLUP (PAD_CTL_PUS_100K_UP | \
52 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
53 PAD_CTL_SRE_SLOW)
54
55#define NO_PULLUP ( \
56 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
57 PAD_CTL_SRE_SLOW)
58
59#define WEAK_PULLDOWN (PAD_CTL_PUS_100K_DOWN | \
60 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
61 PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
62
a02d517b
MK		 63#define OUTPUT_RGB (PAD_CTL_SPEED_MED|PAD_CTL_DSE_60ohm|PAD_CTL_SRE_FAST)
64
65int dram_init(void)
66{
67 /* use the DDR controllers configured size */
68 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
69 (ulong)imx_ddr_size());
70
71 return 0;
72}
73
74/* Colibri UARTA */
75iomux_v3_cfg_t const uart1_pads[] = {
76 MX6_PAD_CSI0_DAT10__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
77 MX6_PAD_CSI0_DAT11__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
78};
79
d141b75c 80#if defined(CONFIG_FSL_ESDHC) && defined(CONFIG_SPL_BUILD)
6eea69bd 81/* Colibri MMC */
a02d517b
MK		 82iomux_v3_cfg_t const usdhc1_pads[] = {
83 MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
84 MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
85 MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
86 MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
87 MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
88 MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
89 MX6_PAD_NANDF_D5__GPIO2_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
90# define GPIO_MMC_CD IMX_GPIO_NR(2, 5)
91};
92
93/* eMMC */
94iomux_v3_cfg_t const usdhc3_pads[] = {
95 MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
96 MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
97 MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
98 MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
99 MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
100 MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
101 MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
102 MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
103 MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
104 MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
105 MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL),
106};
d141b75c 107#endif /* CONFIG_FSL_ESDHC & CONFIG_SPL_BUILD */
a02d517b
MK		 108
109iomux_v3_cfg_t const enet_pads[] = {
110 MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
111 MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
112 MX6_PAD_ENET_RXD0__ENET_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
113 MX6_PAD_ENET_RXD1__ENET_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
114 MX6_PAD_ENET_RX_ER__ENET_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
115 MX6_PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
116 MX6_PAD_ENET_TXD0__ENET_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
117 MX6_PAD_ENET_TXD1__ENET_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
118 MX6_PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
119 MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
120};
121
122static void setup_iomux_enet(void)
123{
124 imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
125}
126
127/* mux auxiliary pins to GPIO, so they can be used from the U-Boot cmdline */
128iomux_v3_cfg_t const gpio_pads[] = {
129 /* ADDRESS[17:18] [25] used as GPIO */
e7cf5349
MZ		 130 MX6_PAD_KEY_ROW2__GPIO4_IO11 | MUX_PAD_CTRL(WEAK_PULLUP) |
131 MUX_MODE_SION,
132 MX6_PAD_KEY_COL2__GPIO4_IO10 | MUX_PAD_CTRL(WEAK_PULLUP) |
133 MUX_MODE_SION,
134 MX6_PAD_NANDF_D1__GPIO2_IO01 | MUX_PAD_CTRL(WEAK_PULLUP) |
135 MUX_MODE_SION,
a02d517b 136 /* ADDRESS[19:24] used as GPIO */
e7cf5349
MZ		 137 MX6_PAD_DISP0_DAT23__GPIO5_IO17 | MUX_PAD_CTRL(WEAK_PULLUP) |
138 MUX_MODE_SION,
139 MX6_PAD_DISP0_DAT22__GPIO5_IO16 | MUX_PAD_CTRL(WEAK_PULLUP) |
140 MUX_MODE_SION,
141 MX6_PAD_DISP0_DAT21__GPIO5_IO15 | MUX_PAD_CTRL(WEAK_PULLUP) |
142 MUX_MODE_SION,
143 MX6_PAD_DISP0_DAT20__GPIO5_IO14 | MUX_PAD_CTRL(WEAK_PULLUP) |
144 MUX_MODE_SION,
145 MX6_PAD_DISP0_DAT19__GPIO5_IO13 | MUX_PAD_CTRL(WEAK_PULLUP) |
146 MUX_MODE_SION,
147 MX6_PAD_DISP0_DAT18__GPIO5_IO12 | MUX_PAD_CTRL(WEAK_PULLUP) |
148 MUX_MODE_SION,
a02d517b 149 /* DATA[16:29] [31] used as GPIO */
e7cf5349
MZ		 150 MX6_PAD_EIM_LBA__GPIO2_IO27 | MUX_PAD_CTRL(WEAK_PULLUP) |
151 MUX_MODE_SION,
152 MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(WEAK_PULLUP) |
153 MUX_MODE_SION,
154 MX6_PAD_NANDF_CS3__GPIO6_IO16 | MUX_PAD_CTRL(WEAK_PULLUP) |
155 MUX_MODE_SION,
156 MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(WEAK_PULLUP) |
157 MUX_MODE_SION,
158 MX6_PAD_NANDF_RB0__GPIO6_IO10 | MUX_PAD_CTRL(WEAK_PULLUP) |
159 MUX_MODE_SION,
160 MX6_PAD_NANDF_ALE__GPIO6_IO08 | MUX_PAD_CTRL(WEAK_PULLUP) |
161 MUX_MODE_SION,
162 MX6_PAD_NANDF_WP_B__GPIO6_IO09 | MUX_PAD_CTRL(WEAK_PULLUP) |
163 MUX_MODE_SION,
164 MX6_PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(WEAK_PULLUP) |
165 MUX_MODE_SION,
166 MX6_PAD_NANDF_CLE__GPIO6_IO07 | MUX_PAD_CTRL(WEAK_PULLUP) |
167 MUX_MODE_SION,
168 MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(WEAK_PULLUP) |
169 MUX_MODE_SION,
170 MX6_PAD_CSI0_MCLK__GPIO5_IO19 | MUX_PAD_CTRL(WEAK_PULLUP) |
171 MUX_MODE_SION,
172 MX6_PAD_CSI0_PIXCLK__GPIO5_IO18 | MUX_PAD_CTRL(WEAK_PULLUP) |
173 MUX_MODE_SION,
174 MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(WEAK_PULLUP) |
175 MUX_MODE_SION,
176 MX6_PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(WEAK_PULLUP) |
177 MUX_MODE_SION,
178 MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(WEAK_PULLUP) |
179 MUX_MODE_SION,
a02d517b 180 /* DQM[0:3] used as GPIO */
e7cf5349
MZ		 181 MX6_PAD_EIM_EB0__GPIO2_IO28 | MUX_PAD_CTRL(WEAK_PULLUP) |
182 MUX_MODE_SION,
183 MX6_PAD_EIM_EB1__GPIO2_IO29 | MUX_PAD_CTRL(WEAK_PULLUP) |
184 MUX_MODE_SION,
185 MX6_PAD_SD2_DAT2__GPIO1_IO13 | MUX_PAD_CTRL(WEAK_PULLUP) |
186 MUX_MODE_SION,
187 MX6_PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(WEAK_PULLUP) |
188 MUX_MODE_SION,
a02d517b 189 /* RDY used as GPIO */
e7cf5349
MZ		 190 MX6_PAD_EIM_WAIT__GPIO5_IO00 | MUX_PAD_CTRL(WEAK_PULLUP) |
191 MUX_MODE_SION,
a02d517b 192 /* ADDRESS[16] DATA[30] used as GPIO */
e7cf5349
MZ		 193 MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(WEAK_PULLDOWN) |
194 MUX_MODE_SION,
195 MX6_PAD_KEY_COL4__GPIO4_IO14 | MUX_PAD_CTRL(WEAK_PULLUP) |
196 MUX_MODE_SION,
a02d517b 197 /* CSI pins used as GPIO */
e7cf5349
MZ		 198 MX6_PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(WEAK_PULLUP) |
199 MUX_MODE_SION,
200 MX6_PAD_SD2_CMD__GPIO1_IO11 | MUX_PAD_CTRL(WEAK_PULLUP) |
201 MUX_MODE_SION,
202 MX6_PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(WEAK_PULLUP) |
203 MUX_MODE_SION,
204 MX6_PAD_EIM_D18__GPIO3_IO18 | MUX_PAD_CTRL(WEAK_PULLUP) |
205 MUX_MODE_SION,
206 MX6_PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(WEAK_PULLUP) |
207 MUX_MODE_SION,
208 MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(WEAK_PULLDOWN) |
209 MUX_MODE_SION,
210 MX6_PAD_EIM_A23__GPIO6_IO06 | MUX_PAD_CTRL(WEAK_PULLUP) |
211 MUX_MODE_SION,
212 MX6_PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(WEAK_PULLUP) |
213 MUX_MODE_SION,
214 MX6_PAD_EIM_A17__GPIO2_IO21 | MUX_PAD_CTRL(WEAK_PULLUP) |
215 MUX_MODE_SION,
216 MX6_PAD_EIM_A18__GPIO2_IO20 | MUX_PAD_CTRL(WEAK_PULLUP) |
217 MUX_MODE_SION,
218 MX6_PAD_EIM_EB3__GPIO2_IO31 | MUX_PAD_CTRL(WEAK_PULLUP) |
219 MUX_MODE_SION,
220 MX6_PAD_EIM_D17__GPIO3_IO17 | MUX_PAD_CTRL(WEAK_PULLUP) |
221 MUX_MODE_SION,
222 MX6_PAD_SD2_DAT0__GPIO1_IO15 | MUX_PAD_CTRL(WEAK_PULLUP) |
223 MUX_MODE_SION,
a02d517b 224 /* GPIO */
e7cf5349
MZ		 225 MX6_PAD_EIM_D26__GPIO3_IO26 | MUX_PAD_CTRL(WEAK_PULLUP) |
226 MUX_MODE_SION,
227 MX6_PAD_EIM_D27__GPIO3_IO27 | MUX_PAD_CTRL(WEAK_PULLUP) |
228 MUX_MODE_SION,
229 MX6_PAD_NANDF_D6__GPIO2_IO06 | MUX_PAD_CTRL(WEAK_PULLUP) |
230 MUX_MODE_SION,
231 MX6_PAD_NANDF_D3__GPIO2_IO03 | MUX_PAD_CTRL(WEAK_PULLUP) |
232 MUX_MODE_SION,
233 MX6_PAD_ENET_REF_CLK__GPIO1_IO23 | MUX_PAD_CTRL(WEAK_PULLUP) |
234 MUX_MODE_SION,
235 MX6_PAD_DI0_PIN4__GPIO4_IO20 | MUX_PAD_CTRL(WEAK_PULLUP) |
236 MUX_MODE_SION,
237 MX6_PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(WEAK_PULLUP) |
238 MUX_MODE_SION,
239 MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(WEAK_PULLUP) |
240 MUX_MODE_SION,
241 MX6_PAD_SD4_DAT0__GPIO2_IO08 | MUX_PAD_CTRL(WEAK_PULLUP) |
242 MUX_MODE_SION,
243 MX6_PAD_GPIO_7__GPIO1_IO07 | MUX_PAD_CTRL(WEAK_PULLUP) |
244 MUX_MODE_SION,
245 MX6_PAD_GPIO_8__GPIO1_IO08 | MUX_PAD_CTRL(WEAK_PULLUP) |
246 MUX_MODE_SION,
a02d517b
MK		 247 /* USBH_OC */
248 MX6_PAD_EIM_D30__GPIO3_IO30 | MUX_PAD_CTRL(WEAK_PULLUP),
249 /* USBC_ID */
250 MX6_PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(WEAK_PULLUP),
251 /* USBC_DET */
252 MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(WEAK_PULLUP),
253};
254
255static void setup_iomux_gpio(void)
256{
257 imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads));
258}
259
260iomux_v3_cfg_t const usb_pads[] = {
e7cf5349
MZ		 261 /* USBH_PEN */
262 MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL) | MUX_MODE_SION,
a02d517b
MK		 263# define GPIO_USBH_EN IMX_GPIO_NR(3, 31)
264};
265
266/*
267 * UARTs are used in DTE mode, switch the mode on all UARTs before
268 * any pinmuxing connects a (DCE) output to a transceiver output.
269 */
270#define UFCR 0x90 /* FIFO Control Register */
271#define UFCR_DCEDTE (1<<6) /* DCE=0 */
272
273static void setup_dtemode_uart(void)
274{
275 setbits_le32((u32 *)(UART1_BASE + UFCR), UFCR_DCEDTE);
276 setbits_le32((u32 *)(UART2_BASE + UFCR), UFCR_DCEDTE);
277 setbits_le32((u32 *)(UART3_BASE + UFCR), UFCR_DCEDTE);
278}
279
280static void setup_iomux_uart(void)
281{
282 setup_dtemode_uart();
283 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
284}
285
286#ifdef CONFIG_USB_EHCI_MX6
287int board_ehci_hcd_init(int port)
288{
289 imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
290 return 0;
291}
7b726c09 292#endif
a02d517b 293
d141b75c 294#if defined(CONFIG_FSL_ESDHC) && defined(CONFIG_SPL_BUILD)
a02d517b
MK		 295/* use the following sequence: eMMC, MMC */
296struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = {
297 {USDHC3_BASE_ADDR},
298 {USDHC1_BASE_ADDR},
299};
300
301int board_mmc_getcd(struct mmc *mmc)
302{
303 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
304 int ret = true; /* default: assume inserted */
305
306 switch (cfg->esdhc_base) {
307 case USDHC1_BASE_ADDR:
e7cf5349 308 gpio_request(GPIO_MMC_CD, "MMC_CD");
a02d517b
MK		 309 gpio_direction_input(GPIO_MMC_CD);
310 ret = !gpio_get_value(GPIO_MMC_CD);
311 break;
312 }
313
314 return ret;
315}
316
317int board_mmc_init(bd_t *bis)
318{
a02d517b
MK		 319 struct src *psrc = (struct src *)SRC_BASE_ADDR;
320 unsigned reg = readl(&psrc->sbmr1) >> 11;
321 /*
322 * Upon reading BOOT_CFG register the following map is done:
323 * Bit 11 and 12 of BOOT_CFG register can determine the current
324 * mmc port
325 * 0x1 SD1
326 * 0x2 SD2
327 * 0x3 SD4
328 */
329
330 switch (reg & 0x3) {
331 case 0x0:
332 imx_iomux_v3_setup_multiple_pads(
333 usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
334 usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR;
335 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
336 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
337 break;
338 case 0x2:
339 imx_iomux_v3_setup_multiple_pads(
340 usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
341 usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
342 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
343 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
344 break;
345 default:
346 puts("MMC boot device not available");
347 }
348
349 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
a02d517b 350}
d141b75c 351#endif /* CONFIG_FSL_ESDHC & CONFIG_SPL_BUILD */
a02d517b
MK		 352
353int board_phy_config(struct phy_device *phydev)
354{
355 if (phydev->drv->config)
356 phydev->drv->config(phydev);
357
358 return 0;
359}
360
361int board_eth_init(bd_t *bis)
362{
363 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
364 uint32_t base = IMX_FEC_BASE;
365 struct mii_dev *bus = NULL;
366 struct phy_device *phydev = NULL;
367 int ret;
368
369 /* provide the PHY clock from the i.MX 6 */
370 ret = enable_fec_anatop_clock(0, ENET_50MHZ);
371 if (ret)
372 return ret;
e7cf5349 373
a02d517b
MK		 374 /* set gpr1[ENET_CLK_SEL] */
375 setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
376
377 setup_iomux_enet();
378
379#ifdef CONFIG_FEC_MXC
380 bus = fec_get_miibus(base, -1);
381 if (!bus)
382 return 0;
e7cf5349 383
a02d517b
MK		 384 /* scan PHY 1..7 */
385 phydev = phy_find_by_mask(bus, 0xff, PHY_INTERFACE_MODE_RMII);
386 if (!phydev) {
387 free(bus);
388 puts("no PHY found\n");
389 return 0;
390 }
e7cf5349 391
a02d517b
MK		 392 phy_reset(phydev);
393 printf("using PHY at %d\n", phydev->addr);
394 ret = fec_probe(bis, -1, base, bus, phydev);
395 if (ret) {
396 printf("FEC MXC: %s:failed\n", __func__);
397 free(phydev);
398 free(bus);
399 }
e7cf5349
MZ		 400#endif /* CONFIG_FEC_MXC */
401
a02d517b
MK		 402 return 0;
403}
404
405static iomux_v3_cfg_t const pwr_intb_pads[] = {
406 /*
407 * the bootrom sets the iomux to vselect, potentially connecting
408 * two outputs. Set this back to GPIO
409 */
410 MX6_PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL)
411};
412
413#if defined(CONFIG_VIDEO_IPUV3)
414
415static iomux_v3_cfg_t const backlight_pads[] = {
416 /* Backlight On */
e7cf5349 417 MX6_PAD_EIM_D26__GPIO3_IO26 | MUX_PAD_CTRL(NO_PAD_CTRL) | MUX_MODE_SION,
a02d517b
MK		 418#define RGB_BACKLIGHT_GP IMX_GPIO_NR(3, 26)
419 /* Backlight PWM, used as GPIO in U-Boot */
420 MX6_PAD_EIM_A22__GPIO2_IO16 | MUX_PAD_CTRL(NO_PULLUP),
e7cf5349
MZ		 421 MX6_PAD_SD4_DAT1__GPIO2_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL) |
422 MUX_MODE_SION,
a02d517b
MK		 423#define RGB_BACKLIGHTPWM_GP IMX_GPIO_NR(2, 9)
424};
425
426static iomux_v3_cfg_t const rgb_pads[] = {
427 MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(OUTPUT_RGB),
428 MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 | MUX_PAD_CTRL(OUTPUT_RGB),
429 MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02 | MUX_PAD_CTRL(OUTPUT_RGB),
430 MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03 | MUX_PAD_CTRL(OUTPUT_RGB),
431 MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 | MUX_PAD_CTRL(OUTPUT_RGB),
432 MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 | MUX_PAD_CTRL(OUTPUT_RGB),
433 MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 | MUX_PAD_CTRL(OUTPUT_RGB),
434 MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 | MUX_PAD_CTRL(OUTPUT_RGB),
435 MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 | MUX_PAD_CTRL(OUTPUT_RGB),
436 MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 | MUX_PAD_CTRL(OUTPUT_RGB),
437 MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 | MUX_PAD_CTRL(OUTPUT_RGB),
438 MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 | MUX_PAD_CTRL(OUTPUT_RGB),
439 MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 | MUX_PAD_CTRL(OUTPUT_RGB),
440 MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 | MUX_PAD_CTRL(OUTPUT_RGB),
441 MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 | MUX_PAD_CTRL(OUTPUT_RGB),
442 MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 | MUX_PAD_CTRL(OUTPUT_RGB),
443 MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 | MUX_PAD_CTRL(OUTPUT_RGB),
444 MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 | MUX_PAD_CTRL(OUTPUT_RGB),
445 MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 | MUX_PAD_CTRL(OUTPUT_RGB),
446 MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 | MUX_PAD_CTRL(OUTPUT_RGB),
447 MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 | MUX_PAD_CTRL(OUTPUT_RGB),
448 MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 | MUX_PAD_CTRL(OUTPUT_RGB),
449};
450
451static void do_enable_hdmi(struct display_info_t const *dev)
452{
453 imx_enable_hdmi_phy();
454}
455
456static void enable_rgb(struct display_info_t const *dev)
457{
458 imx_iomux_v3_setup_multiple_pads(
459 rgb_pads,
460 ARRAY_SIZE(rgb_pads));
461 gpio_direction_output(RGB_BACKLIGHT_GP, 1);
462 gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
463}
464
465static int detect_default(struct display_info_t const *dev)
466{
467 (void) dev;
468 return 1;
469}
470
471struct display_info_t const displays[] = {{
472 .bus = -1,
473 .addr = 0,
474 .pixfmt = IPU_PIX_FMT_RGB24,
475 .detect = detect_hdmi,
476 .enable = do_enable_hdmi,
477 .mode = {
478 .name = "HDMI",
479 .refresh = 60,
480 .xres = 1024,
481 .yres = 768,
482 .pixclock = 15385,
483 .left_margin = 220,
484 .right_margin = 40,
485 .upper_margin = 21,
486 .lower_margin = 7,
487 .hsync_len = 60,
488 .vsync_len = 10,
489 .sync = FB_SYNC_EXT,
490 .vmode = FB_VMODE_NONINTERLACED
491} }, {
492 .bus = -1,
493 .addr = 0,
494 .pixfmt = IPU_PIX_FMT_RGB666,
495 .detect = detect_default,
496 .enable = enable_rgb,
497 .mode = {
498 .name = "vga-rgb",
499 .refresh = 60,
500 .xres = 640,
501 .yres = 480,
502 .pixclock = 33000,
503 .left_margin = 48,
504 .right_margin = 16,
505 .upper_margin = 31,
506 .lower_margin = 11,
507 .hsync_len = 96,
508 .vsync_len = 2,
509 .sync = 0,
510 .vmode = FB_VMODE_NONINTERLACED
511} }, {
512 .bus = -1,
513 .addr = 0,
514 .pixfmt = IPU_PIX_FMT_RGB666,
515 .enable = enable_rgb,
516 .mode = {
517 .name = "wvga-rgb",
518 .refresh = 60,
519 .xres = 800,
520 .yres = 480,
521 .pixclock = 25000,
522 .left_margin = 40,
523 .right_margin = 88,
524 .upper_margin = 33,
525 .lower_margin = 10,
526 .hsync_len = 128,
527 .vsync_len = 2,
528 .sync = 0,
529 .vmode = FB_VMODE_NONINTERLACED
530} } };
531size_t display_count = ARRAY_SIZE(displays);
532
533static void setup_display(void)
534{
535 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
536 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
537 int reg;
538
539 enable_ipu_clock();
540 imx_setup_hdmi();
541 /* Turn on LDB0,IPU,IPU DI0 clocks */
542 reg = __raw_readl(&mxc_ccm->CCGR3);
543 reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
544 writel(reg, &mxc_ccm->CCGR3);
545
546 /* set LDB0, LDB1 clk select to 011/011 */
547 reg = readl(&mxc_ccm->cs2cdr);
548 reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
549 |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
550 reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
551 |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
552 writel(reg, &mxc_ccm->cs2cdr);
553
554 reg = readl(&mxc_ccm->cscmr2);
555 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
556 writel(reg, &mxc_ccm->cscmr2);
557
558 reg = readl(&mxc_ccm->chsccdr);
559 reg |= (CHSCCDR_CLK_SEL_LDB_DI0
560 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
561 writel(reg, &mxc_ccm->chsccdr);
562
563 reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
564 |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
565 |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
566 |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
567 |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
568 |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
569 |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
570 |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
571 |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
572 writel(reg, &iomux->gpr[2]);
573
574 reg = readl(&iomux->gpr[3]);
575 reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK
576 |IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
577 | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
578 <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
579 writel(reg, &iomux->gpr[3]);
580
581 /* backlight unconditionally on for now */
582 imx_iomux_v3_setup_multiple_pads(backlight_pads,
583 ARRAY_SIZE(backlight_pads));
584 /* use 0 for EDT 7", use 1 for LG fullHD panel */
e7cf5349
MZ		 585 gpio_request(RGB_BACKLIGHTPWM_GP, "PWM<A>");
586 gpio_request(RGB_BACKLIGHT_GP, "BL_ON");
a02d517b
MK		 587 gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
588 gpio_direction_output(RGB_BACKLIGHT_GP, 1);
589}
a3c90217
GS		 590
591/*
592 * Backlight off before OS handover
593 */
594void board_preboot_os(void)
595{
596 gpio_direction_output(RGB_BACKLIGHTPWM_GP, 1);
597 gpio_direction_output(RGB_BACKLIGHT_GP, 0);
598}
a02d517b
MK		 599#endif /* defined(CONFIG_VIDEO_IPUV3) */
600
601int board_early_init_f(void)
602{
603 imx_iomux_v3_setup_multiple_pads(pwr_intb_pads,
604 ARRAY_SIZE(pwr_intb_pads));
605 setup_iomux_uart();
606
a02d517b
MK		 607 return 0;
608}
609
610/*
611 * Do not overwrite the console
612 * Use always serial for U-Boot console
613 */
614int overwrite_console(void)
615{
616 return 1;
617}
618
619int board_init(void)
620{
621 /* address of boot parameters */
622 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
623
464c988a
FE		 624#if defined(CONFIG_VIDEO_IPUV3)
625 setup_display();
626#endif
627
a02d517b
MK		 628#ifdef CONFIG_TDX_CMD_IMX_MFGR
629 (void) pmic_init();
630#endif
631
10e40d54 632#ifdef CONFIG_SATA
a02d517b
MK		 633 setup_sata();
634#endif
635
636 setup_iomux_gpio();
637
638 return 0;
639}
640
641#ifdef CONFIG_BOARD_LATE_INIT
642int board_late_init(void)
643{
644#if defined(CONFIG_REVISION_TAG) && \
645 defined(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)
646 char env_str[256];
647 u32 rev;
648
649 rev = get_board_rev();
650 snprintf(env_str, ARRAY_SIZE(env_str), "%.4x", rev);
382bee57 651 env_set("board_rev", env_str);
a02d517b
MK		 652#endif
653
654 return 0;
655}
656#endif /* CONFIG_BOARD_LATE_INIT */
657
a02d517b
MK		 658int checkboard(void)
659{
660 char it[] = " IT";
661 int minc, maxc;
662
663 switch (get_cpu_temp_grade(&minc, &maxc)) {
664 case TEMP_AUTOMOTIVE:
665 case TEMP_INDUSTRIAL:
666 break;
667 case TEMP_EXTCOMMERCIAL:
668 default:
669 it[0] = 0;
670 };
671 printf("Model: Toradex Colibri iMX6 %s %sMB%s\n",
672 is_cpu_type(MXC_CPU_MX6DL) ? "DualLite" : "Solo",
673 (gd->ram_size == 0x20000000) ? "512" : "256", it);
674 return 0;
675}
676
677#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
678int ft_board_setup(void *blob, bd_t *bd)
679{
680 return ft_common_board_setup(blob, bd);
681}
682#endif
683
684#ifdef CONFIG_CMD_BMODE
685static const struct boot_mode board_boot_modes[] = {
686 {"mmc", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
687 {NULL, 0},
688};
689#endif
690
691int misc_init_r(void)
692{
693#ifdef CONFIG_CMD_BMODE
694 add_board_boot_modes(board_boot_modes);
695#endif
696 return 0;
697}
698
699#ifdef CONFIG_LDO_BYPASS_CHECK
700/* TODO, use external pmic, for now always ldo_enable */
701void ldo_mode_set(int ldo_bypass)
702{
703 return;
704}
705#endif
706
707#ifdef CONFIG_SPL_BUILD
708#include <spl.h>
b08c8c48 709#include <linux/libfdt.h>
a02d517b
MK		 710#include "asm/arch/mx6dl-ddr.h"
711#include "asm/arch/iomux.h"
712#include "asm/arch/crm_regs.h"
713
714static int mx6s_dcd_table[] = {
715/* ddr-setup.cfg */
716
717MX6_IOM_DRAM_SDQS0, 0x00000030,
718MX6_IOM_DRAM_SDQS1, 0x00000030,
719MX6_IOM_DRAM_SDQS2, 0x00000030,
720MX6_IOM_DRAM_SDQS3, 0x00000030,
721MX6_IOM_DRAM_SDQS4, 0x00000030,
722MX6_IOM_DRAM_SDQS5, 0x00000030,
723MX6_IOM_DRAM_SDQS6, 0x00000030,
724MX6_IOM_DRAM_SDQS7, 0x00000030,
725
726MX6_IOM_GRP_B0DS, 0x00000030,
727MX6_IOM_GRP_B1DS, 0x00000030,
728MX6_IOM_GRP_B2DS, 0x00000030,
729MX6_IOM_GRP_B3DS, 0x00000030,
730MX6_IOM_GRP_B4DS, 0x00000030,
731MX6_IOM_GRP_B5DS, 0x00000030,
732MX6_IOM_GRP_B6DS, 0x00000030,
733MX6_IOM_GRP_B7DS, 0x00000030,
734MX6_IOM_GRP_ADDDS, 0x00000030,
735/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
736MX6_IOM_GRP_CTLDS, 0x00000030,
737
738MX6_IOM_DRAM_DQM0, 0x00020030,
739MX6_IOM_DRAM_DQM1, 0x00020030,
740MX6_IOM_DRAM_DQM2, 0x00020030,
741MX6_IOM_DRAM_DQM3, 0x00020030,
742MX6_IOM_DRAM_DQM4, 0x00020030,
743MX6_IOM_DRAM_DQM5, 0x00020030,
744MX6_IOM_DRAM_DQM6, 0x00020030,
745MX6_IOM_DRAM_DQM7, 0x00020030,
746
747MX6_IOM_DRAM_CAS, 0x00020030,
748MX6_IOM_DRAM_RAS, 0x00020030,
749MX6_IOM_DRAM_SDCLK_0, 0x00020030,
750MX6_IOM_DRAM_SDCLK_1, 0x00020030,
751
752MX6_IOM_DRAM_RESET, 0x00020030,
753MX6_IOM_DRAM_SDCKE0, 0x00003000,
754MX6_IOM_DRAM_SDCKE1, 0x00003000,
755
756MX6_IOM_DRAM_SDODT0, 0x00003030,
757MX6_IOM_DRAM_SDODT1, 0x00003030,
758
759/* (differential input) */
760MX6_IOM_DDRMODE_CTL, 0x00020000,
761/* (differential input) */
762MX6_IOM_GRP_DDRMODE, 0x00020000,
763/* disable ddr pullups */
764MX6_IOM_GRP_DDRPKE, 0x00000000,
765MX6_IOM_DRAM_SDBA2, 0x00000000,
766/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
767MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
768
769/* Read data DQ Byte0-3 delay */
770MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
771MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
772MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
773MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
774MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333,
775MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333,
776MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333,
777MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333,
778
779/*
780 * MDMISC mirroring interleaved (row/bank/col)
781 */
782/* TODO: check what the RALAT field does */
783MX6_MMDC_P0_MDMISC, 0x00081740,
784
785/*
786 * MDSCR con_req
787 */
788MX6_MMDC_P0_MDSCR, 0x00008000,
789
790
791/* 800mhz_2x64mx16.cfg */
792
793MX6_MMDC_P0_MDPDC, 0x0002002D,
794MX6_MMDC_P0_MDCFG0, 0x2C305503,
795MX6_MMDC_P0_MDCFG1, 0xB66D8D63,
796MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
797MX6_MMDC_P0_MDRWD, 0x000026D2,
798MX6_MMDC_P0_MDOR, 0x00301023,
799MX6_MMDC_P0_MDOTC, 0x00333030,
800MX6_MMDC_P0_MDPDC, 0x0002556D,
801/* CS0 End: 7MSB of ((0x10000000, + 512M) -1) >> 25 */
802MX6_MMDC_P0_MDASP, 0x00000017,
803/* DDR3 DATA BUS SIZE: 64BIT */
804/* MX6_MMDC_P0_MDCTL, 0x821A0000, */
805/* DDR3 DATA BUS SIZE: 32BIT */
806MX6_MMDC_P0_MDCTL, 0x82190000,
807
808/* Write commands to DDR */
809/* Load Mode Registers */
810/* TODO Use Auto Self-Refresh mode (Extended Temperature)*/
811/* MX6_MMDC_P0_MDSCR, 0x04408032, */
812MX6_MMDC_P0_MDSCR, 0x04008032,
813MX6_MMDC_P0_MDSCR, 0x00008033,
814MX6_MMDC_P0_MDSCR, 0x00048031,
815MX6_MMDC_P0_MDSCR, 0x13208030,
816/* ZQ calibration */
817MX6_MMDC_P0_MDSCR, 0x04008040,
818
819MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
820MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003,
821MX6_MMDC_P0_MDREF, 0x00005800,
822
823MX6_MMDC_P0_MPODTCTRL, 0x00000000,
824MX6_MMDC_P1_MPODTCTRL, 0x00000000,
825
826MX6_MMDC_P0_MPDGCTRL0, 0x42360232,
827MX6_MMDC_P0_MPDGCTRL1, 0x021F022A,
828MX6_MMDC_P1_MPDGCTRL0, 0x421E0224,
829MX6_MMDC_P1_MPDGCTRL1, 0x02110218,
830
831MX6_MMDC_P0_MPRDDLCTL, 0x41434344,
832MX6_MMDC_P1_MPRDDLCTL, 0x4345423E,
833MX6_MMDC_P0_MPWRDLCTL, 0x39383339,
834MX6_MMDC_P1_MPWRDLCTL, 0x3E363930,
835
836MX6_MMDC_P0_MPWLDECTRL0, 0x00340039,
837MX6_MMDC_P0_MPWLDECTRL1, 0x002C002D,
838MX6_MMDC_P1_MPWLDECTRL0, 0x00120019,
839MX6_MMDC_P1_MPWLDECTRL1, 0x0012002D,
840
841MX6_MMDC_P0_MPMUR0, 0x00000800,
842MX6_MMDC_P1_MPMUR0, 0x00000800,
843MX6_MMDC_P0_MDSCR, 0x00000000,
844MX6_MMDC_P0_MAPSR, 0x00011006,
845};
846
847static int mx6dl_dcd_table[] = {
848/* ddr-setup.cfg */
849
850MX6_IOM_DRAM_SDQS0, 0x00000030,
851MX6_IOM_DRAM_SDQS1, 0x00000030,
852MX6_IOM_DRAM_SDQS2, 0x00000030,
853MX6_IOM_DRAM_SDQS3, 0x00000030,
854MX6_IOM_DRAM_SDQS4, 0x00000030,
855MX6_IOM_DRAM_SDQS5, 0x00000030,
856MX6_IOM_DRAM_SDQS6, 0x00000030,
857MX6_IOM_DRAM_SDQS7, 0x00000030,
858
859MX6_IOM_GRP_B0DS, 0x00000030,
860MX6_IOM_GRP_B1DS, 0x00000030,
861MX6_IOM_GRP_B2DS, 0x00000030,
862MX6_IOM_GRP_B3DS, 0x00000030,
863MX6_IOM_GRP_B4DS, 0x00000030,
864MX6_IOM_GRP_B5DS, 0x00000030,
865MX6_IOM_GRP_B6DS, 0x00000030,
866MX6_IOM_GRP_B7DS, 0x00000030,
867MX6_IOM_GRP_ADDDS, 0x00000030,
868/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
869MX6_IOM_GRP_CTLDS, 0x00000030,
870
871MX6_IOM_DRAM_DQM0, 0x00020030,
872MX6_IOM_DRAM_DQM1, 0x00020030,
873MX6_IOM_DRAM_DQM2, 0x00020030,
874MX6_IOM_DRAM_DQM3, 0x00020030,
875MX6_IOM_DRAM_DQM4, 0x00020030,
876MX6_IOM_DRAM_DQM5, 0x00020030,
877MX6_IOM_DRAM_DQM6, 0x00020030,
878MX6_IOM_DRAM_DQM7, 0x00020030,
879
880MX6_IOM_DRAM_CAS, 0x00020030,
881MX6_IOM_DRAM_RAS, 0x00020030,
882MX6_IOM_DRAM_SDCLK_0, 0x00020030,
883MX6_IOM_DRAM_SDCLK_1, 0x00020030,
884
885MX6_IOM_DRAM_RESET, 0x00020030,
886MX6_IOM_DRAM_SDCKE0, 0x00003000,
887MX6_IOM_DRAM_SDCKE1, 0x00003000,
888
889MX6_IOM_DRAM_SDODT0, 0x00003030,
890MX6_IOM_DRAM_SDODT1, 0x00003030,
891
892/* (differential input) */
893MX6_IOM_DDRMODE_CTL, 0x00020000,
894/* (differential input) */
895MX6_IOM_GRP_DDRMODE, 0x00020000,
896/* disable ddr pullups */
897MX6_IOM_GRP_DDRPKE, 0x00000000,
898MX6_IOM_DRAM_SDBA2, 0x00000000,
899/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
900MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
901
902/* Read data DQ Byte0-3 delay */
903MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
904MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
905MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
906MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
907MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333,
908MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333,
909MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333,
910MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333,
911
912/*
913 * MDMISC mirroring interleaved (row/bank/col)
914 */
915/* TODO: check what the RALAT field does */
916MX6_MMDC_P0_MDMISC, 0x00081740,
917
918/*
919 * MDSCR con_req
920 */
921MX6_MMDC_P0_MDSCR, 0x00008000,
922
923
924/* 800mhz_2x64mx16.cfg */
925
926MX6_MMDC_P0_MDPDC, 0x0002002D,
927MX6_MMDC_P0_MDCFG0, 0x2C305503,
928MX6_MMDC_P0_MDCFG1, 0xB66D8D63,
929MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
930MX6_MMDC_P0_MDRWD, 0x000026D2,
931MX6_MMDC_P0_MDOR, 0x00301023,
932MX6_MMDC_P0_MDOTC, 0x00333030,
933MX6_MMDC_P0_MDPDC, 0x0002556D,
934/* CS0 End: 7MSB of ((0x10000000, + 512M) -1) >> 25 */
935MX6_MMDC_P0_MDASP, 0x00000017,
936/* DDR3 DATA BUS SIZE: 64BIT */
937MX6_MMDC_P0_MDCTL, 0x821A0000,
938/* DDR3 DATA BUS SIZE: 32BIT */
939/* MX6_MMDC_P0_MDCTL, 0x82190000, */
940
941/* Write commands to DDR */
942/* Load Mode Registers */
943/* TODO Use Auto Self-Refresh mode (Extended Temperature)*/
944/* MX6_MMDC_P0_MDSCR, 0x04408032, */
945MX6_MMDC_P0_MDSCR, 0x04008032,
946MX6_MMDC_P0_MDSCR, 0x00008033,
947MX6_MMDC_P0_MDSCR, 0x00048031,
948MX6_MMDC_P0_MDSCR, 0x13208030,
949/* ZQ calibration */
950MX6_MMDC_P0_MDSCR, 0x04008040,
951
952MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
953MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003,
954MX6_MMDC_P0_MDREF, 0x00005800,
955
956MX6_MMDC_P0_MPODTCTRL, 0x00000000,
957MX6_MMDC_P1_MPODTCTRL, 0x00000000,
958
959MX6_MMDC_P0_MPDGCTRL0, 0x42360232,
960MX6_MMDC_P0_MPDGCTRL1, 0x021F022A,
961MX6_MMDC_P1_MPDGCTRL0, 0x421E0224,
962MX6_MMDC_P1_MPDGCTRL1, 0x02110218,
963
964MX6_MMDC_P0_MPRDDLCTL, 0x41434344,
965MX6_MMDC_P1_MPRDDLCTL, 0x4345423E,
966MX6_MMDC_P0_MPWRDLCTL, 0x39383339,
967MX6_MMDC_P1_MPWRDLCTL, 0x3E363930,
968
969MX6_MMDC_P0_MPWLDECTRL0, 0x00340039,
970MX6_MMDC_P0_MPWLDECTRL1, 0x002C002D,
971MX6_MMDC_P1_MPWLDECTRL0, 0x00120019,
972MX6_MMDC_P1_MPWLDECTRL1, 0x0012002D,
973
974MX6_MMDC_P0_MPMUR0, 0x00000800,
975MX6_MMDC_P1_MPMUR0, 0x00000800,
976MX6_MMDC_P0_MDSCR, 0x00000000,
977MX6_MMDC_P0_MAPSR, 0x00011006,
978};
979
980static void ccgr_init(void)
981{
982 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
983
984 writel(0x00C03F3F, &ccm->CCGR0);
985 writel(0x0030FC03, &ccm->CCGR1);
986 writel(0x0FFFFFF3, &ccm->CCGR2);
987 writel(0x3FF0300F, &ccm->CCGR3);
988 writel(0x00FFF300, &ccm->CCGR4);
989 writel(0x0F0000F3, &ccm->CCGR5);
990 writel(0x000003FF, &ccm->CCGR6);
991
992/*
993 * Setup CCM_CCOSR register as follows:
994 *
995 * cko1_en = 1 --> CKO1 enabled
996 * cko1_div = 111 --> divide by 8
997 * cko1_sel = 1011 --> ahb_clk_root
998 *
999 * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
1000 */
1001 writel(0x000000FB, &ccm->ccosr);
1002}
1003
a02d517b
MK		 1004static void ddr_init(int *table, int size)
1005{
1006 int i;
1007
1008 for (i = 0; i < size / 2 ; i++)
1009 writel(table[2 * i + 1], table[2 * i]);
1010}
1011
1012static void spl_dram_init(void)
1013{
1014 int minc, maxc;
1015
1016 switch (get_cpu_temp_grade(&minc, &maxc)) {
1017 case TEMP_COMMERCIAL:
1018 case TEMP_EXTCOMMERCIAL:
1019 if (is_cpu_type(MXC_CPU_MX6DL)) {
1020 puts("Commercial temperature grade DDR3 timings, 64bit bus width.\n");
1021 ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table));
1022 } else {
1023 puts("Commercial temperature grade DDR3 timings, 32bit bus width.\n");
1024 ddr_init(mx6s_dcd_table, ARRAY_SIZE(mx6s_dcd_table));
1025 }
1026 break;
1027 case TEMP_INDUSTRIAL:
1028 case TEMP_AUTOMOTIVE:
1029 default:
1030 if (is_cpu_type(MXC_CPU_MX6DL)) {
1031 ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table));
1032 } else {
1033 puts("Industrial temperature grade DDR3 timings, 32bit bus width.\n");
1034 ddr_init(mx6s_dcd_table, ARRAY_SIZE(mx6s_dcd_table));
1035 }
1036 break;
1037 };
1038 udelay(100);
1039}
1040
1041void board_init_f(ulong dummy)
1042{
1043 /* setup AIPS and disable watchdog */
1044 arch_cpu_init();
1045
1046 ccgr_init();
1047 gpr_init();
1048
6eea69bd 1049 /* iomux */
a02d517b
MK		 1050 board_early_init_f();
1051
1052 /* setup GP timer */
1053 timer_init();
1054
1055 /* UART clocks enabled and gd valid - init serial console */
1056 preloader_console_init();
1057
1058 /* Make sure we use dte mode */
1059 setup_dtemode_uart();
1060
1061 /* DDR initialization */
1062 spl_dram_init();
1063
1064 /* Clear the BSS. */
1065 memset(__bss_start, 0, __bss_end - __bss_start);
1066
1067 /* load/boot image from boot device */
1068 board_init_r(NULL, 0);
1069}
1070
1071void reset_cpu(ulong addr)
1072{
1073}
1074
e7cf5349 1075#endif /* CONFIG_SPL_BUILD */
a02d517b
MK		 1076
1077static struct mxc_serial_platdata mxc_serial_plat = {
1078 .reg = (struct mxc_uart *)UART1_BASE,
1079 .use_dte = true,
1080};
1081
1082U_BOOT_DEVICE(mxc_serial) = {
1083 .name = "serial_mxc",
1084 .platdata = &mxc_serial_plat,
1085};
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