]> Git Repo - J-u-boot.git/blame - board/toradex/colibri_imx6/colibri_imx6.c
projects / J-u-boot.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
colibri_imx6: enable pin control driver
[J-u-boot.git] / board / toradex / colibri_imx6 / colibri_imx6.c
CommitLineData
83d290c5 1// SPDX-License-Identifier: GPL-2.0+
a02d517b
MK		 2/*
3 * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
4 * Copyright (C) 2013, Boundary Devices <[email protected]>
e7cf5349 5 * Copyright (C) 2014-2019, Toradex AG
a02d517b 6 * copied from nitrogen6x
a02d517b
MK		 7 */
8
9#include <common.h>
9d922450 10#include <dm.h>
e7cf5349 11
a02d517b
MK		 12#include <asm/arch/clock.h>
13#include <asm/arch/crm_regs.h>
14#include <asm/arch/imx-regs.h>
a02d517b 15#include <asm/arch/mx6-ddr.h>
e7cf5349 16#include <asm/arch/mx6-pins.h>
a02d517b
MK		 17#include <asm/arch/mxc_hdmi.h>
18#include <asm/arch/sys_proto.h>
19#include <asm/bootm.h>
20#include <asm/gpio.h>
e7cf5349 21#include <asm/mach-imx/boot_mode.h>
552a848e
SB		 22#include <asm/mach-imx/iomux-v3.h>
23#include <asm/mach-imx/mxc_i2c.h>
24#include <asm/mach-imx/sata.h>
552a848e 25#include <asm/mach-imx/video.h>
a02d517b 26#include <dm/platform_data/serial_mxc.h>
e7cf5349 27#include <environment.h>
a02d517b
MK		 28#include <fsl_esdhc.h>
29#include <i2c.h>
30#include <imx_thermal.h>
a02d517b
MK		 31#include <micrel.h>
32#include <miiphy.h>
a02d517b
MK		 33#include <netdev.h>
34
35#include "../common/tdx-cfg-block.h"
36#ifdef CONFIG_TDX_CMD_IMX_MFGR
37#include "pf0100.h"
38#endif
39
40DECLARE_GLOBAL_DATA_PTR;
41
42#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
43 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
44 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
45
46#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
47 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
48 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
49
50#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
51 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
52
53#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
54 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
55
56#define BUTTON_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
57 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
58
59#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
60 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
61 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
62
63#define WEAK_PULLUP (PAD_CTL_PUS_100K_UP | \
64 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
65 PAD_CTL_SRE_SLOW)
66
67#define NO_PULLUP ( \
68 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
69 PAD_CTL_SRE_SLOW)
70
71#define WEAK_PULLDOWN (PAD_CTL_PUS_100K_DOWN | \
72 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
73 PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
74
75#define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm)
76
77#define OUTPUT_RGB (PAD_CTL_SPEED_MED|PAD_CTL_DSE_60ohm|PAD_CTL_SRE_FAST)
78
79int dram_init(void)
80{
81 /* use the DDR controllers configured size */
82 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
83 (ulong)imx_ddr_size());
84
85 return 0;
86}
87
88/* Colibri UARTA */
89iomux_v3_cfg_t const uart1_pads[] = {
90 MX6_PAD_CSI0_DAT10__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
91 MX6_PAD_CSI0_DAT11__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
92};
93
94#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
95/* Colibri I2C */
96struct i2c_pads_info i2c_pad_info1 = {
97 .scl = {
98 .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC,
99 .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | PC,
100 .gp = IMX_GPIO_NR(1, 3)
101 },
102 .sda = {
103 .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | PC,
104 .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | PC,
105 .gp = IMX_GPIO_NR(1, 6)
106 }
107};
108
109/* Colibri local, PMIC, SGTL5000, STMPE811 */
110struct i2c_pads_info i2c_pad_info_loc = {
111 .scl = {
112 .i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | PC,
113 .gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC,
114 .gp = IMX_GPIO_NR(2, 30)
115 },
116 .sda = {
117 .i2c_mode = MX6_PAD_EIM_D16__I2C2_SDA | PC,
118 .gpio_mode = MX6_PAD_EIM_D16__GPIO3_IO16 | PC,
119 .gp = IMX_GPIO_NR(3, 16)
120 }
121};
122
123/* Apalis MMC */
124iomux_v3_cfg_t const usdhc1_pads[] = {
125 MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
126 MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
127 MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
128 MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
129 MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
130 MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
131 MX6_PAD_NANDF_D5__GPIO2_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
132# define GPIO_MMC_CD IMX_GPIO_NR(2, 5)
133};
134
135/* eMMC */
136iomux_v3_cfg_t const usdhc3_pads[] = {
137 MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
138 MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
139 MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
140 MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
141 MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
142 MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
143 MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
144 MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
145 MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
146 MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
147 MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL),
148};
149
150iomux_v3_cfg_t const enet_pads[] = {
151 MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
152 MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
153 MX6_PAD_ENET_RXD0__ENET_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
154 MX6_PAD_ENET_RXD1__ENET_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
155 MX6_PAD_ENET_RX_ER__ENET_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
156 MX6_PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
157 MX6_PAD_ENET_TXD0__ENET_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
158 MX6_PAD_ENET_TXD1__ENET_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
159 MX6_PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
160 MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
161};
162
163static void setup_iomux_enet(void)
164{
165 imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
166}
167
168/* mux auxiliary pins to GPIO, so they can be used from the U-Boot cmdline */
169iomux_v3_cfg_t const gpio_pads[] = {
170 /* ADDRESS[17:18] [25] used as GPIO */
e7cf5349
MZ		 171 MX6_PAD_KEY_ROW2__GPIO4_IO11 | MUX_PAD_CTRL(WEAK_PULLUP) |
172 MUX_MODE_SION,
173 MX6_PAD_KEY_COL2__GPIO4_IO10 | MUX_PAD_CTRL(WEAK_PULLUP) |
174 MUX_MODE_SION,
175 MX6_PAD_NANDF_D1__GPIO2_IO01 | MUX_PAD_CTRL(WEAK_PULLUP) |
176 MUX_MODE_SION,
a02d517b 177 /* ADDRESS[19:24] used as GPIO */
e7cf5349
MZ		 178 MX6_PAD_DISP0_DAT23__GPIO5_IO17 | MUX_PAD_CTRL(WEAK_PULLUP) |
179 MUX_MODE_SION,
180 MX6_PAD_DISP0_DAT22__GPIO5_IO16 | MUX_PAD_CTRL(WEAK_PULLUP) |
181 MUX_MODE_SION,
182 MX6_PAD_DISP0_DAT21__GPIO5_IO15 | MUX_PAD_CTRL(WEAK_PULLUP) |
183 MUX_MODE_SION,
184 MX6_PAD_DISP0_DAT20__GPIO5_IO14 | MUX_PAD_CTRL(WEAK_PULLUP) |
185 MUX_MODE_SION,
186 MX6_PAD_DISP0_DAT19__GPIO5_IO13 | MUX_PAD_CTRL(WEAK_PULLUP) |
187 MUX_MODE_SION,
188 MX6_PAD_DISP0_DAT18__GPIO5_IO12 | MUX_PAD_CTRL(WEAK_PULLUP) |
189 MUX_MODE_SION,
a02d517b 190 /* DATA[16:29] [31] used as GPIO */
e7cf5349
MZ		 191 MX6_PAD_EIM_LBA__GPIO2_IO27 | MUX_PAD_CTRL(WEAK_PULLUP) |
192 MUX_MODE_SION,
193 MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(WEAK_PULLUP) |
194 MUX_MODE_SION,
195 MX6_PAD_NANDF_CS3__GPIO6_IO16 | MUX_PAD_CTRL(WEAK_PULLUP) |
196 MUX_MODE_SION,
197 MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(WEAK_PULLUP) |
198 MUX_MODE_SION,
199 MX6_PAD_NANDF_RB0__GPIO6_IO10 | MUX_PAD_CTRL(WEAK_PULLUP) |
200 MUX_MODE_SION,
201 MX6_PAD_NANDF_ALE__GPIO6_IO08 | MUX_PAD_CTRL(WEAK_PULLUP) |
202 MUX_MODE_SION,
203 MX6_PAD_NANDF_WP_B__GPIO6_IO09 | MUX_PAD_CTRL(WEAK_PULLUP) |
204 MUX_MODE_SION,
205 MX6_PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(WEAK_PULLUP) |
206 MUX_MODE_SION,
207 MX6_PAD_NANDF_CLE__GPIO6_IO07 | MUX_PAD_CTRL(WEAK_PULLUP) |
208 MUX_MODE_SION,
209 MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(WEAK_PULLUP) |
210 MUX_MODE_SION,
211 MX6_PAD_CSI0_MCLK__GPIO5_IO19 | MUX_PAD_CTRL(WEAK_PULLUP) |
212 MUX_MODE_SION,
213 MX6_PAD_CSI0_PIXCLK__GPIO5_IO18 | MUX_PAD_CTRL(WEAK_PULLUP) |
214 MUX_MODE_SION,
215 MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(WEAK_PULLUP) |
216 MUX_MODE_SION,
217 MX6_PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(WEAK_PULLUP) |
218 MUX_MODE_SION,
219 MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(WEAK_PULLUP) |
220 MUX_MODE_SION,
a02d517b 221 /* DQM[0:3] used as GPIO */
e7cf5349
MZ		 222 MX6_PAD_EIM_EB0__GPIO2_IO28 | MUX_PAD_CTRL(WEAK_PULLUP) |
223 MUX_MODE_SION,
224 MX6_PAD_EIM_EB1__GPIO2_IO29 | MUX_PAD_CTRL(WEAK_PULLUP) |
225 MUX_MODE_SION,
226 MX6_PAD_SD2_DAT2__GPIO1_IO13 | MUX_PAD_CTRL(WEAK_PULLUP) |
227 MUX_MODE_SION,
228 MX6_PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(WEAK_PULLUP) |
229 MUX_MODE_SION,
a02d517b 230 /* RDY used as GPIO */
e7cf5349
MZ		 231 MX6_PAD_EIM_WAIT__GPIO5_IO00 | MUX_PAD_CTRL(WEAK_PULLUP) |
232 MUX_MODE_SION,
a02d517b 233 /* ADDRESS[16] DATA[30] used as GPIO */
e7cf5349
MZ		 234 MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(WEAK_PULLDOWN) |
235 MUX_MODE_SION,
236 MX6_PAD_KEY_COL4__GPIO4_IO14 | MUX_PAD_CTRL(WEAK_PULLUP) |
237 MUX_MODE_SION,
a02d517b 238 /* CSI pins used as GPIO */
e7cf5349
MZ		 239 MX6_PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(WEAK_PULLUP) |
240 MUX_MODE_SION,
241 MX6_PAD_SD2_CMD__GPIO1_IO11 | MUX_PAD_CTRL(WEAK_PULLUP) |
242 MUX_MODE_SION,
243 MX6_PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(WEAK_PULLUP) |
244 MUX_MODE_SION,
245 MX6_PAD_EIM_D18__GPIO3_IO18 | MUX_PAD_CTRL(WEAK_PULLUP) |
246 MUX_MODE_SION,
247 MX6_PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(WEAK_PULLUP) |
248 MUX_MODE_SION,
249 MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(WEAK_PULLDOWN) |
250 MUX_MODE_SION,
251 MX6_PAD_EIM_A23__GPIO6_IO06 | MUX_PAD_CTRL(WEAK_PULLUP) |
252 MUX_MODE_SION,
253 MX6_PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(WEAK_PULLUP) |
254 MUX_MODE_SION,
255 MX6_PAD_EIM_A17__GPIO2_IO21 | MUX_PAD_CTRL(WEAK_PULLUP) |
256 MUX_MODE_SION,
257 MX6_PAD_EIM_A18__GPIO2_IO20 | MUX_PAD_CTRL(WEAK_PULLUP) |
258 MUX_MODE_SION,
259 MX6_PAD_EIM_EB3__GPIO2_IO31 | MUX_PAD_CTRL(WEAK_PULLUP) |
260 MUX_MODE_SION,
261 MX6_PAD_EIM_D17__GPIO3_IO17 | MUX_PAD_CTRL(WEAK_PULLUP) |
262 MUX_MODE_SION,
263 MX6_PAD_SD2_DAT0__GPIO1_IO15 | MUX_PAD_CTRL(WEAK_PULLUP) |
264 MUX_MODE_SION,
a02d517b 265 /* GPIO */
e7cf5349
MZ		 266 MX6_PAD_EIM_D26__GPIO3_IO26 | MUX_PAD_CTRL(WEAK_PULLUP) |
267 MUX_MODE_SION,
268 MX6_PAD_EIM_D27__GPIO3_IO27 | MUX_PAD_CTRL(WEAK_PULLUP) |
269 MUX_MODE_SION,
270 MX6_PAD_NANDF_D6__GPIO2_IO06 | MUX_PAD_CTRL(WEAK_PULLUP) |
271 MUX_MODE_SION,
272 MX6_PAD_NANDF_D3__GPIO2_IO03 | MUX_PAD_CTRL(WEAK_PULLUP) |
273 MUX_MODE_SION,
274 MX6_PAD_ENET_REF_CLK__GPIO1_IO23 | MUX_PAD_CTRL(WEAK_PULLUP) |
275 MUX_MODE_SION,
276 MX6_PAD_DI0_PIN4__GPIO4_IO20 | MUX_PAD_CTRL(WEAK_PULLUP) |
277 MUX_MODE_SION,
278 MX6_PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(WEAK_PULLUP) |
279 MUX_MODE_SION,
280 MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(WEAK_PULLUP) |
281 MUX_MODE_SION,
282 MX6_PAD_SD4_DAT0__GPIO2_IO08 | MUX_PAD_CTRL(WEAK_PULLUP) |
283 MUX_MODE_SION,
284 MX6_PAD_GPIO_7__GPIO1_IO07 | MUX_PAD_CTRL(WEAK_PULLUP) |
285 MUX_MODE_SION,
286 MX6_PAD_GPIO_8__GPIO1_IO08 | MUX_PAD_CTRL(WEAK_PULLUP) |
287 MUX_MODE_SION,
a02d517b
MK		 288 /* USBH_OC */
289 MX6_PAD_EIM_D30__GPIO3_IO30 | MUX_PAD_CTRL(WEAK_PULLUP),
290 /* USBC_ID */
291 MX6_PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(WEAK_PULLUP),
292 /* USBC_DET */
293 MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(WEAK_PULLUP),
294};
295
296static void setup_iomux_gpio(void)
297{
298 imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads));
299}
300
301iomux_v3_cfg_t const usb_pads[] = {
e7cf5349
MZ		 302 /* USBH_PEN */
303 MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL) | MUX_MODE_SION,
a02d517b
MK		 304# define GPIO_USBH_EN IMX_GPIO_NR(3, 31)
305};
306
307/*
308 * UARTs are used in DTE mode, switch the mode on all UARTs before
309 * any pinmuxing connects a (DCE) output to a transceiver output.
310 */
311#define UFCR 0x90 /* FIFO Control Register */
312#define UFCR_DCEDTE (1<<6) /* DCE=0 */
313
314static void setup_dtemode_uart(void)
315{
316 setbits_le32((u32 *)(UART1_BASE + UFCR), UFCR_DCEDTE);
317 setbits_le32((u32 *)(UART2_BASE + UFCR), UFCR_DCEDTE);
318 setbits_le32((u32 *)(UART3_BASE + UFCR), UFCR_DCEDTE);
319}
320
321static void setup_iomux_uart(void)
322{
323 setup_dtemode_uart();
324 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
325}
326
327#ifdef CONFIG_USB_EHCI_MX6
328int board_ehci_hcd_init(int port)
329{
330 imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
331 return 0;
332}
333
334int board_ehci_power(int port, int on)
335{
336 switch (port) {
337 case 0:
338 /* control OTG power */
339 /* No special PE for USBC, always on when ID pin signals
340 host mode */
341 break;
342 case 1:
343 /* Control MXM USBH */
344 /* Set MXM USBH power enable, '0' means on */
e7cf5349 345 gpio_request(GPIO_USBH_EN, "USBH_EN");
a02d517b
MK		 346 gpio_direction_output(GPIO_USBH_EN, !on);
347 mdelay(100);
348 break;
349 default:
350 break;
351 }
352 return 0;
353}
e7cf5349 354#endif /* CONFIG_USB_EHCI_MX6 */
a02d517b
MK		 355
356#ifdef CONFIG_FSL_ESDHC
357/* use the following sequence: eMMC, MMC */
358struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = {
359 {USDHC3_BASE_ADDR},
360 {USDHC1_BASE_ADDR},
361};
362
363int board_mmc_getcd(struct mmc *mmc)
364{
365 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
366 int ret = true; /* default: assume inserted */
367
368 switch (cfg->esdhc_base) {
369 case USDHC1_BASE_ADDR:
e7cf5349 370 gpio_request(GPIO_MMC_CD, "MMC_CD");
a02d517b
MK		 371 gpio_direction_input(GPIO_MMC_CD);
372 ret = !gpio_get_value(GPIO_MMC_CD);
373 break;
374 }
375
376 return ret;
377}
378
379int board_mmc_init(bd_t *bis)
380{
381#ifndef CONFIG_SPL_BUILD
382 s32 status = 0;
383 u32 index = 0;
384
385 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
386 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
387
388 usdhc_cfg[0].max_bus_width = 8;
389 usdhc_cfg[1].max_bus_width = 4;
390
391 for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
392 switch (index) {
393 case 0:
394 imx_iomux_v3_setup_multiple_pads(
395 usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
396 break;
397 case 1:
398 imx_iomux_v3_setup_multiple_pads(
399 usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
400 break;
401 default:
402 printf("Warning: you configured more USDHC controllers (%d) then supported by the board (%d)\n",
403 index + 1, CONFIG_SYS_FSL_USDHC_NUM);
404 return status;
405 }
406
407 status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
408 }
409
410 return status;
e7cf5349 411#else /* !CONFIG_SPL_BUILD */
a02d517b
MK		 412 struct src *psrc = (struct src *)SRC_BASE_ADDR;
413 unsigned reg = readl(&psrc->sbmr1) >> 11;
414 /*
415 * Upon reading BOOT_CFG register the following map is done:
416 * Bit 11 and 12 of BOOT_CFG register can determine the current
417 * mmc port
418 * 0x1 SD1
419 * 0x2 SD2
420 * 0x3 SD4
421 */
422
423 switch (reg & 0x3) {
424 case 0x0:
425 imx_iomux_v3_setup_multiple_pads(
426 usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
427 usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR;
428 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
429 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
430 break;
431 case 0x2:
432 imx_iomux_v3_setup_multiple_pads(
433 usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
434 usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
435 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
436 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
437 break;
438 default:
439 puts("MMC boot device not available");
440 }
441
442 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
e7cf5349 443#endif /* !CONFIG_SPL_BUILD */
a02d517b 444}
e7cf5349 445#endif /* CONFIG_FSL_ESDHC */
a02d517b
MK		 446
447int board_phy_config(struct phy_device *phydev)
448{
449 if (phydev->drv->config)
450 phydev->drv->config(phydev);
451
452 return 0;
453}
454
455int board_eth_init(bd_t *bis)
456{
457 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
458 uint32_t base = IMX_FEC_BASE;
459 struct mii_dev *bus = NULL;
460 struct phy_device *phydev = NULL;
461 int ret;
462
463 /* provide the PHY clock from the i.MX 6 */
464 ret = enable_fec_anatop_clock(0, ENET_50MHZ);
465 if (ret)
466 return ret;
e7cf5349 467
a02d517b
MK		 468 /* set gpr1[ENET_CLK_SEL] */
469 setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
470
471 setup_iomux_enet();
472
473#ifdef CONFIG_FEC_MXC
474 bus = fec_get_miibus(base, -1);
475 if (!bus)
476 return 0;
e7cf5349 477
a02d517b
MK		 478 /* scan PHY 1..7 */
479 phydev = phy_find_by_mask(bus, 0xff, PHY_INTERFACE_MODE_RMII);
480 if (!phydev) {
481 free(bus);
482 puts("no PHY found\n");
483 return 0;
484 }
e7cf5349 485
a02d517b
MK		 486 phy_reset(phydev);
487 printf("using PHY at %d\n", phydev->addr);
488 ret = fec_probe(bis, -1, base, bus, phydev);
489 if (ret) {
490 printf("FEC MXC: %s:failed\n", __func__);
491 free(phydev);
492 free(bus);
493 }
e7cf5349
MZ		 494#endif /* CONFIG_FEC_MXC */
495
a02d517b
MK		 496 return 0;
497}
498
499static iomux_v3_cfg_t const pwr_intb_pads[] = {
500 /*
501 * the bootrom sets the iomux to vselect, potentially connecting
502 * two outputs. Set this back to GPIO
503 */
504 MX6_PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL)
505};
506
507#if defined(CONFIG_VIDEO_IPUV3)
508
509static iomux_v3_cfg_t const backlight_pads[] = {
510 /* Backlight On */
e7cf5349 511 MX6_PAD_EIM_D26__GPIO3_IO26 | MUX_PAD_CTRL(NO_PAD_CTRL) | MUX_MODE_SION,
a02d517b
MK		 512#define RGB_BACKLIGHT_GP IMX_GPIO_NR(3, 26)
513 /* Backlight PWM, used as GPIO in U-Boot */
514 MX6_PAD_EIM_A22__GPIO2_IO16 | MUX_PAD_CTRL(NO_PULLUP),
e7cf5349
MZ		 515 MX6_PAD_SD4_DAT1__GPIO2_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL) |
516 MUX_MODE_SION,
a02d517b
MK		 517#define RGB_BACKLIGHTPWM_GP IMX_GPIO_NR(2, 9)
518};
519
520static iomux_v3_cfg_t const rgb_pads[] = {
521 MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(OUTPUT_RGB),
522 MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 | MUX_PAD_CTRL(OUTPUT_RGB),
523 MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02 | MUX_PAD_CTRL(OUTPUT_RGB),
524 MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03 | MUX_PAD_CTRL(OUTPUT_RGB),
525 MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 | MUX_PAD_CTRL(OUTPUT_RGB),
526 MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 | MUX_PAD_CTRL(OUTPUT_RGB),
527 MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 | MUX_PAD_CTRL(OUTPUT_RGB),
528 MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 | MUX_PAD_CTRL(OUTPUT_RGB),
529 MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 | MUX_PAD_CTRL(OUTPUT_RGB),
530 MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 | MUX_PAD_CTRL(OUTPUT_RGB),
531 MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 | MUX_PAD_CTRL(OUTPUT_RGB),
532 MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 | MUX_PAD_CTRL(OUTPUT_RGB),
533 MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 | MUX_PAD_CTRL(OUTPUT_RGB),
534 MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 | MUX_PAD_CTRL(OUTPUT_RGB),
535 MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 | MUX_PAD_CTRL(OUTPUT_RGB),
536 MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 | MUX_PAD_CTRL(OUTPUT_RGB),
537 MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 | MUX_PAD_CTRL(OUTPUT_RGB),
538 MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 | MUX_PAD_CTRL(OUTPUT_RGB),
539 MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 | MUX_PAD_CTRL(OUTPUT_RGB),
540 MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 | MUX_PAD_CTRL(OUTPUT_RGB),
541 MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 | MUX_PAD_CTRL(OUTPUT_RGB),
542 MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 | MUX_PAD_CTRL(OUTPUT_RGB),
543};
544
545static void do_enable_hdmi(struct display_info_t const *dev)
546{
547 imx_enable_hdmi_phy();
548}
549
550static void enable_rgb(struct display_info_t const *dev)
551{
552 imx_iomux_v3_setup_multiple_pads(
553 rgb_pads,
554 ARRAY_SIZE(rgb_pads));
555 gpio_direction_output(RGB_BACKLIGHT_GP, 1);
556 gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
557}
558
559static int detect_default(struct display_info_t const *dev)
560{
561 (void) dev;
562 return 1;
563}
564
565struct display_info_t const displays[] = {{
566 .bus = -1,
567 .addr = 0,
568 .pixfmt = IPU_PIX_FMT_RGB24,
569 .detect = detect_hdmi,
570 .enable = do_enable_hdmi,
571 .mode = {
572 .name = "HDMI",
573 .refresh = 60,
574 .xres = 1024,
575 .yres = 768,
576 .pixclock = 15385,
577 .left_margin = 220,
578 .right_margin = 40,
579 .upper_margin = 21,
580 .lower_margin = 7,
581 .hsync_len = 60,
582 .vsync_len = 10,
583 .sync = FB_SYNC_EXT,
584 .vmode = FB_VMODE_NONINTERLACED
585} }, {
586 .bus = -1,
587 .addr = 0,
588 .pixfmt = IPU_PIX_FMT_RGB666,
589 .detect = detect_default,
590 .enable = enable_rgb,
591 .mode = {
592 .name = "vga-rgb",
593 .refresh = 60,
594 .xres = 640,
595 .yres = 480,
596 .pixclock = 33000,
597 .left_margin = 48,
598 .right_margin = 16,
599 .upper_margin = 31,
600 .lower_margin = 11,
601 .hsync_len = 96,
602 .vsync_len = 2,
603 .sync = 0,
604 .vmode = FB_VMODE_NONINTERLACED
605} }, {
606 .bus = -1,
607 .addr = 0,
608 .pixfmt = IPU_PIX_FMT_RGB666,
609 .enable = enable_rgb,
610 .mode = {
611 .name = "wvga-rgb",
612 .refresh = 60,
613 .xres = 800,
614 .yres = 480,
615 .pixclock = 25000,
616 .left_margin = 40,
617 .right_margin = 88,
618 .upper_margin = 33,
619 .lower_margin = 10,
620 .hsync_len = 128,
621 .vsync_len = 2,
622 .sync = 0,
623 .vmode = FB_VMODE_NONINTERLACED
624} } };
625size_t display_count = ARRAY_SIZE(displays);
626
627static void setup_display(void)
628{
629 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
630 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
631 int reg;
632
633 enable_ipu_clock();
634 imx_setup_hdmi();
635 /* Turn on LDB0,IPU,IPU DI0 clocks */
636 reg = __raw_readl(&mxc_ccm->CCGR3);
637 reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
638 writel(reg, &mxc_ccm->CCGR3);
639
640 /* set LDB0, LDB1 clk select to 011/011 */
641 reg = readl(&mxc_ccm->cs2cdr);
642 reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
643 |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
644 reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
645 |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
646 writel(reg, &mxc_ccm->cs2cdr);
647
648 reg = readl(&mxc_ccm->cscmr2);
649 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
650 writel(reg, &mxc_ccm->cscmr2);
651
652 reg = readl(&mxc_ccm->chsccdr);
653 reg |= (CHSCCDR_CLK_SEL_LDB_DI0
654 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
655 writel(reg, &mxc_ccm->chsccdr);
656
657 reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
658 |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
659 |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
660 |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
661 |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
662 |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
663 |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
664 |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
665 |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
666 writel(reg, &iomux->gpr[2]);
667
668 reg = readl(&iomux->gpr[3]);
669 reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK
670 |IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
671 | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
672 <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
673 writel(reg, &iomux->gpr[3]);
674
675 /* backlight unconditionally on for now */
676 imx_iomux_v3_setup_multiple_pads(backlight_pads,
677 ARRAY_SIZE(backlight_pads));
678 /* use 0 for EDT 7", use 1 for LG fullHD panel */
e7cf5349
MZ		 679 gpio_request(RGB_BACKLIGHTPWM_GP, "PWM<A>");
680 gpio_request(RGB_BACKLIGHT_GP, "BL_ON");
a02d517b
MK		 681 gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
682 gpio_direction_output(RGB_BACKLIGHT_GP, 1);
683}
a3c90217
GS		 684
685/*
686 * Backlight off before OS handover
687 */
688void board_preboot_os(void)
689{
690 gpio_direction_output(RGB_BACKLIGHTPWM_GP, 1);
691 gpio_direction_output(RGB_BACKLIGHT_GP, 0);
692}
a02d517b
MK		 693#endif /* defined(CONFIG_VIDEO_IPUV3) */
694
695int board_early_init_f(void)
696{
697 imx_iomux_v3_setup_multiple_pads(pwr_intb_pads,
698 ARRAY_SIZE(pwr_intb_pads));
699 setup_iomux_uart();
700
a02d517b
MK		 701 return 0;
702}
703
704/*
705 * Do not overwrite the console
706 * Use always serial for U-Boot console
707 */
708int overwrite_console(void)
709{
710 return 1;
711}
712
713int board_init(void)
714{
715 /* address of boot parameters */
716 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
717
718 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
719 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info_loc);
720
464c988a
FE		 721#if defined(CONFIG_VIDEO_IPUV3)
722 setup_display();
723#endif
724
a02d517b
MK		 725#ifdef CONFIG_TDX_CMD_IMX_MFGR
726 (void) pmic_init();
727#endif
728
10e40d54 729#ifdef CONFIG_SATA
a02d517b
MK		 730 setup_sata();
731#endif
732
733 setup_iomux_gpio();
734
735 return 0;
736}
737
738#ifdef CONFIG_BOARD_LATE_INIT
739int board_late_init(void)
740{
741#if defined(CONFIG_REVISION_TAG) && \
742 defined(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)
743 char env_str[256];
744 u32 rev;
745
746 rev = get_board_rev();
747 snprintf(env_str, ARRAY_SIZE(env_str), "%.4x", rev);
382bee57 748 env_set("board_rev", env_str);
a02d517b
MK		 749#endif
750
751 return 0;
752}
753#endif /* CONFIG_BOARD_LATE_INIT */
754
755#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_SYSTEM_SETUP)
756int ft_system_setup(void *blob, bd_t *bd)
757{
758 return 0;
759}
760#endif
761
762int checkboard(void)
763{
764 char it[] = " IT";
765 int minc, maxc;
766
767 switch (get_cpu_temp_grade(&minc, &maxc)) {
768 case TEMP_AUTOMOTIVE:
769 case TEMP_INDUSTRIAL:
770 break;
771 case TEMP_EXTCOMMERCIAL:
772 default:
773 it[0] = 0;
774 };
775 printf("Model: Toradex Colibri iMX6 %s %sMB%s\n",
776 is_cpu_type(MXC_CPU_MX6DL) ? "DualLite" : "Solo",
777 (gd->ram_size == 0x20000000) ? "512" : "256", it);
778 return 0;
779}
780
781#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
782int ft_board_setup(void *blob, bd_t *bd)
783{
784 return ft_common_board_setup(blob, bd);
785}
786#endif
787
788#ifdef CONFIG_CMD_BMODE
789static const struct boot_mode board_boot_modes[] = {
790 {"mmc", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
791 {NULL, 0},
792};
793#endif
794
795int misc_init_r(void)
796{
797#ifdef CONFIG_CMD_BMODE
798 add_board_boot_modes(board_boot_modes);
799#endif
800 return 0;
801}
802
803#ifdef CONFIG_LDO_BYPASS_CHECK
804/* TODO, use external pmic, for now always ldo_enable */
805void ldo_mode_set(int ldo_bypass)
806{
807 return;
808}
809#endif
810
811#ifdef CONFIG_SPL_BUILD
812#include <spl.h>
b08c8c48 813#include <linux/libfdt.h>
a02d517b
MK		 814#include "asm/arch/mx6dl-ddr.h"
815#include "asm/arch/iomux.h"
816#include "asm/arch/crm_regs.h"
817
818static int mx6s_dcd_table[] = {
819/* ddr-setup.cfg */
820
821MX6_IOM_DRAM_SDQS0, 0x00000030,
822MX6_IOM_DRAM_SDQS1, 0x00000030,
823MX6_IOM_DRAM_SDQS2, 0x00000030,
824MX6_IOM_DRAM_SDQS3, 0x00000030,
825MX6_IOM_DRAM_SDQS4, 0x00000030,
826MX6_IOM_DRAM_SDQS5, 0x00000030,
827MX6_IOM_DRAM_SDQS6, 0x00000030,
828MX6_IOM_DRAM_SDQS7, 0x00000030,
829
830MX6_IOM_GRP_B0DS, 0x00000030,
831MX6_IOM_GRP_B1DS, 0x00000030,
832MX6_IOM_GRP_B2DS, 0x00000030,
833MX6_IOM_GRP_B3DS, 0x00000030,
834MX6_IOM_GRP_B4DS, 0x00000030,
835MX6_IOM_GRP_B5DS, 0x00000030,
836MX6_IOM_GRP_B6DS, 0x00000030,
837MX6_IOM_GRP_B7DS, 0x00000030,
838MX6_IOM_GRP_ADDDS, 0x00000030,
839/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
840MX6_IOM_GRP_CTLDS, 0x00000030,
841
842MX6_IOM_DRAM_DQM0, 0x00020030,
843MX6_IOM_DRAM_DQM1, 0x00020030,
844MX6_IOM_DRAM_DQM2, 0x00020030,
845MX6_IOM_DRAM_DQM3, 0x00020030,
846MX6_IOM_DRAM_DQM4, 0x00020030,
847MX6_IOM_DRAM_DQM5, 0x00020030,
848MX6_IOM_DRAM_DQM6, 0x00020030,
849MX6_IOM_DRAM_DQM7, 0x00020030,
850
851MX6_IOM_DRAM_CAS, 0x00020030,
852MX6_IOM_DRAM_RAS, 0x00020030,
853MX6_IOM_DRAM_SDCLK_0, 0x00020030,
854MX6_IOM_DRAM_SDCLK_1, 0x00020030,
855
856MX6_IOM_DRAM_RESET, 0x00020030,
857MX6_IOM_DRAM_SDCKE0, 0x00003000,
858MX6_IOM_DRAM_SDCKE1, 0x00003000,
859
860MX6_IOM_DRAM_SDODT0, 0x00003030,
861MX6_IOM_DRAM_SDODT1, 0x00003030,
862
863/* (differential input) */
864MX6_IOM_DDRMODE_CTL, 0x00020000,
865/* (differential input) */
866MX6_IOM_GRP_DDRMODE, 0x00020000,
867/* disable ddr pullups */
868MX6_IOM_GRP_DDRPKE, 0x00000000,
869MX6_IOM_DRAM_SDBA2, 0x00000000,
870/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
871MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
872
873/* Read data DQ Byte0-3 delay */
874MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
875MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
876MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
877MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
878MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333,
879MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333,
880MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333,
881MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333,
882
883/*
884 * MDMISC mirroring interleaved (row/bank/col)
885 */
886/* TODO: check what the RALAT field does */
887MX6_MMDC_P0_MDMISC, 0x00081740,
888
889/*
890 * MDSCR con_req
891 */
892MX6_MMDC_P0_MDSCR, 0x00008000,
893
894
895/* 800mhz_2x64mx16.cfg */
896
897MX6_MMDC_P0_MDPDC, 0x0002002D,
898MX6_MMDC_P0_MDCFG0, 0x2C305503,
899MX6_MMDC_P0_MDCFG1, 0xB66D8D63,
900MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
901MX6_MMDC_P0_MDRWD, 0x000026D2,
902MX6_MMDC_P0_MDOR, 0x00301023,
903MX6_MMDC_P0_MDOTC, 0x00333030,
904MX6_MMDC_P0_MDPDC, 0x0002556D,
905/* CS0 End: 7MSB of ((0x10000000, + 512M) -1) >> 25 */
906MX6_MMDC_P0_MDASP, 0x00000017,
907/* DDR3 DATA BUS SIZE: 64BIT */
908/* MX6_MMDC_P0_MDCTL, 0x821A0000, */
909/* DDR3 DATA BUS SIZE: 32BIT */
910MX6_MMDC_P0_MDCTL, 0x82190000,
911
912/* Write commands to DDR */
913/* Load Mode Registers */
914/* TODO Use Auto Self-Refresh mode (Extended Temperature)*/
915/* MX6_MMDC_P0_MDSCR, 0x04408032, */
916MX6_MMDC_P0_MDSCR, 0x04008032,
917MX6_MMDC_P0_MDSCR, 0x00008033,
918MX6_MMDC_P0_MDSCR, 0x00048031,
919MX6_MMDC_P0_MDSCR, 0x13208030,
920/* ZQ calibration */
921MX6_MMDC_P0_MDSCR, 0x04008040,
922
923MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
924MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003,
925MX6_MMDC_P0_MDREF, 0x00005800,
926
927MX6_MMDC_P0_MPODTCTRL, 0x00000000,
928MX6_MMDC_P1_MPODTCTRL, 0x00000000,
929
930MX6_MMDC_P0_MPDGCTRL0, 0x42360232,
931MX6_MMDC_P0_MPDGCTRL1, 0x021F022A,
932MX6_MMDC_P1_MPDGCTRL0, 0x421E0224,
933MX6_MMDC_P1_MPDGCTRL1, 0x02110218,
934
935MX6_MMDC_P0_MPRDDLCTL, 0x41434344,
936MX6_MMDC_P1_MPRDDLCTL, 0x4345423E,
937MX6_MMDC_P0_MPWRDLCTL, 0x39383339,
938MX6_MMDC_P1_MPWRDLCTL, 0x3E363930,
939
940MX6_MMDC_P0_MPWLDECTRL0, 0x00340039,
941MX6_MMDC_P0_MPWLDECTRL1, 0x002C002D,
942MX6_MMDC_P1_MPWLDECTRL0, 0x00120019,
943MX6_MMDC_P1_MPWLDECTRL1, 0x0012002D,
944
945MX6_MMDC_P0_MPMUR0, 0x00000800,
946MX6_MMDC_P1_MPMUR0, 0x00000800,
947MX6_MMDC_P0_MDSCR, 0x00000000,
948MX6_MMDC_P0_MAPSR, 0x00011006,
949};
950
951static int mx6dl_dcd_table[] = {
952/* ddr-setup.cfg */
953
954MX6_IOM_DRAM_SDQS0, 0x00000030,
955MX6_IOM_DRAM_SDQS1, 0x00000030,
956MX6_IOM_DRAM_SDQS2, 0x00000030,
957MX6_IOM_DRAM_SDQS3, 0x00000030,
958MX6_IOM_DRAM_SDQS4, 0x00000030,
959MX6_IOM_DRAM_SDQS5, 0x00000030,
960MX6_IOM_DRAM_SDQS6, 0x00000030,
961MX6_IOM_DRAM_SDQS7, 0x00000030,
962
963MX6_IOM_GRP_B0DS, 0x00000030,
964MX6_IOM_GRP_B1DS, 0x00000030,
965MX6_IOM_GRP_B2DS, 0x00000030,
966MX6_IOM_GRP_B3DS, 0x00000030,
967MX6_IOM_GRP_B4DS, 0x00000030,
968MX6_IOM_GRP_B5DS, 0x00000030,
969MX6_IOM_GRP_B6DS, 0x00000030,
970MX6_IOM_GRP_B7DS, 0x00000030,
971MX6_IOM_GRP_ADDDS, 0x00000030,
972/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
973MX6_IOM_GRP_CTLDS, 0x00000030,
974
975MX6_IOM_DRAM_DQM0, 0x00020030,
976MX6_IOM_DRAM_DQM1, 0x00020030,
977MX6_IOM_DRAM_DQM2, 0x00020030,
978MX6_IOM_DRAM_DQM3, 0x00020030,
979MX6_IOM_DRAM_DQM4, 0x00020030,
980MX6_IOM_DRAM_DQM5, 0x00020030,
981MX6_IOM_DRAM_DQM6, 0x00020030,
982MX6_IOM_DRAM_DQM7, 0x00020030,
983
984MX6_IOM_DRAM_CAS, 0x00020030,
985MX6_IOM_DRAM_RAS, 0x00020030,
986MX6_IOM_DRAM_SDCLK_0, 0x00020030,
987MX6_IOM_DRAM_SDCLK_1, 0x00020030,
988
989MX6_IOM_DRAM_RESET, 0x00020030,
990MX6_IOM_DRAM_SDCKE0, 0x00003000,
991MX6_IOM_DRAM_SDCKE1, 0x00003000,
992
993MX6_IOM_DRAM_SDODT0, 0x00003030,
994MX6_IOM_DRAM_SDODT1, 0x00003030,
995
996/* (differential input) */
997MX6_IOM_DDRMODE_CTL, 0x00020000,
998/* (differential input) */
999MX6_IOM_GRP_DDRMODE, 0x00020000,
1000/* disable ddr pullups */
1001MX6_IOM_GRP_DDRPKE, 0x00000000,
1002MX6_IOM_DRAM_SDBA2, 0x00000000,
1003/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
1004MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
1005
1006/* Read data DQ Byte0-3 delay */
1007MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
1008MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
1009MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
1010MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
1011MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333,
1012MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333,
1013MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333,
1014MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333,
1015
1016/*
1017 * MDMISC mirroring interleaved (row/bank/col)
1018 */
1019/* TODO: check what the RALAT field does */
1020MX6_MMDC_P0_MDMISC, 0x00081740,
1021
1022/*
1023 * MDSCR con_req
1024 */
1025MX6_MMDC_P0_MDSCR, 0x00008000,
1026
1027
1028/* 800mhz_2x64mx16.cfg */
1029
1030MX6_MMDC_P0_MDPDC, 0x0002002D,
1031MX6_MMDC_P0_MDCFG0, 0x2C305503,
1032MX6_MMDC_P0_MDCFG1, 0xB66D8D63,
1033MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
1034MX6_MMDC_P0_MDRWD, 0x000026D2,
1035MX6_MMDC_P0_MDOR, 0x00301023,
1036MX6_MMDC_P0_MDOTC, 0x00333030,
1037MX6_MMDC_P0_MDPDC, 0x0002556D,
1038/* CS0 End: 7MSB of ((0x10000000, + 512M) -1) >> 25 */
1039MX6_MMDC_P0_MDASP, 0x00000017,
1040/* DDR3 DATA BUS SIZE: 64BIT */
1041MX6_MMDC_P0_MDCTL, 0x821A0000,
1042/* DDR3 DATA BUS SIZE: 32BIT */
1043/* MX6_MMDC_P0_MDCTL, 0x82190000, */
1044
1045/* Write commands to DDR */
1046/* Load Mode Registers */
1047/* TODO Use Auto Self-Refresh mode (Extended Temperature)*/
1048/* MX6_MMDC_P0_MDSCR, 0x04408032, */
1049MX6_MMDC_P0_MDSCR, 0x04008032,
1050MX6_MMDC_P0_MDSCR, 0x00008033,
1051MX6_MMDC_P0_MDSCR, 0x00048031,
1052MX6_MMDC_P0_MDSCR, 0x13208030,
1053/* ZQ calibration */
1054MX6_MMDC_P0_MDSCR, 0x04008040,
1055
1056MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
1057MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003,
1058MX6_MMDC_P0_MDREF, 0x00005800,
1059
1060MX6_MMDC_P0_MPODTCTRL, 0x00000000,
1061MX6_MMDC_P1_MPODTCTRL, 0x00000000,
1062
1063MX6_MMDC_P0_MPDGCTRL0, 0x42360232,
1064MX6_MMDC_P0_MPDGCTRL1, 0x021F022A,
1065MX6_MMDC_P1_MPDGCTRL0, 0x421E0224,
1066MX6_MMDC_P1_MPDGCTRL1, 0x02110218,
1067
1068MX6_MMDC_P0_MPRDDLCTL, 0x41434344,
1069MX6_MMDC_P1_MPRDDLCTL, 0x4345423E,
1070MX6_MMDC_P0_MPWRDLCTL, 0x39383339,
1071MX6_MMDC_P1_MPWRDLCTL, 0x3E363930,
1072
1073MX6_MMDC_P0_MPWLDECTRL0, 0x00340039,
1074MX6_MMDC_P0_MPWLDECTRL1, 0x002C002D,
1075MX6_MMDC_P1_MPWLDECTRL0, 0x00120019,
1076MX6_MMDC_P1_MPWLDECTRL1, 0x0012002D,
1077
1078MX6_MMDC_P0_MPMUR0, 0x00000800,
1079MX6_MMDC_P1_MPMUR0, 0x00000800,
1080MX6_MMDC_P0_MDSCR, 0x00000000,
1081MX6_MMDC_P0_MAPSR, 0x00011006,
1082};
1083
1084static void ccgr_init(void)
1085{
1086 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
1087
1088 writel(0x00C03F3F, &ccm->CCGR0);
1089 writel(0x0030FC03, &ccm->CCGR1);
1090 writel(0x0FFFFFF3, &ccm->CCGR2);
1091 writel(0x3FF0300F, &ccm->CCGR3);
1092 writel(0x00FFF300, &ccm->CCGR4);
1093 writel(0x0F0000F3, &ccm->CCGR5);
1094 writel(0x000003FF, &ccm->CCGR6);
1095
1096/*
1097 * Setup CCM_CCOSR register as follows:
1098 *
1099 * cko1_en = 1 --> CKO1 enabled
1100 * cko1_div = 111 --> divide by 8
1101 * cko1_sel = 1011 --> ahb_clk_root
1102 *
1103 * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
1104 */
1105 writel(0x000000FB, &ccm->ccosr);
1106}
1107
a02d517b
MK		 1108static void ddr_init(int *table, int size)
1109{
1110 int i;
1111
1112 for (i = 0; i < size / 2 ; i++)
1113 writel(table[2 * i + 1], table[2 * i]);
1114}
1115
1116static void spl_dram_init(void)
1117{
1118 int minc, maxc;
1119
1120 switch (get_cpu_temp_grade(&minc, &maxc)) {
1121 case TEMP_COMMERCIAL:
1122 case TEMP_EXTCOMMERCIAL:
1123 if (is_cpu_type(MXC_CPU_MX6DL)) {
1124 puts("Commercial temperature grade DDR3 timings, 64bit bus width.\n");
1125 ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table));
1126 } else {
1127 puts("Commercial temperature grade DDR3 timings, 32bit bus width.\n");
1128 ddr_init(mx6s_dcd_table, ARRAY_SIZE(mx6s_dcd_table));
1129 }
1130 break;
1131 case TEMP_INDUSTRIAL:
1132 case TEMP_AUTOMOTIVE:
1133 default:
1134 if (is_cpu_type(MXC_CPU_MX6DL)) {
1135 ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table));
1136 } else {
1137 puts("Industrial temperature grade DDR3 timings, 32bit bus width.\n");
1138 ddr_init(mx6s_dcd_table, ARRAY_SIZE(mx6s_dcd_table));
1139 }
1140 break;
1141 };
1142 udelay(100);
1143}
1144
1145void board_init_f(ulong dummy)
1146{
1147 /* setup AIPS and disable watchdog */
1148 arch_cpu_init();
1149
1150 ccgr_init();
1151 gpr_init();
1152
1153 /* iomux and setup of i2c */
1154 board_early_init_f();
1155
1156 /* setup GP timer */
1157 timer_init();
1158
1159 /* UART clocks enabled and gd valid - init serial console */
1160 preloader_console_init();
1161
1162 /* Make sure we use dte mode */
1163 setup_dtemode_uart();
1164
1165 /* DDR initialization */
1166 spl_dram_init();
1167
1168 /* Clear the BSS. */
1169 memset(__bss_start, 0, __bss_end - __bss_start);
1170
1171 /* load/boot image from boot device */
1172 board_init_r(NULL, 0);
1173}
1174
1175void reset_cpu(ulong addr)
1176{
1177}
1178
e7cf5349 1179#endif /* CONFIG_SPL_BUILD */
a02d517b
MK		 1180
1181static struct mxc_serial_platdata mxc_serial_plat = {
1182 .reg = (struct mxc_uart *)UART1_BASE,
1183 .use_dte = true,
1184};
1185
1186U_BOOT_DEVICE(mxc_serial) = {
1187 .name = "serial_mxc",
1188 .platdata = &mxc_serial_plat,
1189};
Empty description
This page took 0.402205 seconds and 4 git commands to generate.