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[J-u-boot.git] / board / toradex / colibri_imx6 / colibri_imx6.c
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83d290c5 1// SPDX-License-Identifier: GPL-2.0+
a02d517b
MK		 2/*
3 * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
4 * Copyright (C) 2013, Boundary Devices <[email protected]>
e7cf5349 5 * Copyright (C) 2014-2019, Toradex AG
a02d517b 6 * copied from nitrogen6x
a02d517b
MK		 7 */
8
9#include <common.h>
9a3b4ceb 10#include <cpu_func.h>
9d922450 11#include <dm.h>
9eef56db 12#include <env.h>
5255932f 13#include <init.h>
90526e9f 14#include <net.h>
c05ed00a 15#include <linux/delay.h>
e7cf5349 16
a02d517b
MK		 17#include <asm/arch/clock.h>
18#include <asm/arch/crm_regs.h>
19#include <asm/arch/imx-regs.h>
a02d517b 20#include <asm/arch/mx6-ddr.h>
e7cf5349 21#include <asm/arch/mx6-pins.h>
a02d517b
MK		 22#include <asm/arch/mxc_hdmi.h>
23#include <asm/arch/sys_proto.h>
24#include <asm/bootm.h>
25#include <asm/gpio.h>
e7cf5349 26#include <asm/mach-imx/boot_mode.h>
552a848e 27#include <asm/mach-imx/iomux-v3.h>
552a848e 28#include <asm/mach-imx/sata.h>
552a848e 29#include <asm/mach-imx/video.h>
bee73083 30#include <cpu.h>
a02d517b 31#include <dm/platform_data/serial_mxc.h>
e37ac717 32#include <fsl_esdhc_imx.h>
a02d517b 33#include <imx_thermal.h>
a02d517b 34#include <miiphy.h>
a02d517b 35#include <netdev.h>
82029bf5 36#include <cpu.h>
a02d517b
MK		 37
38#include "../common/tdx-cfg-block.h"
39#ifdef CONFIG_TDX_CMD_IMX_MFGR
40#include "pf0100.h"
41#endif
42
43DECLARE_GLOBAL_DATA_PTR;
44
45#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
46 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
47 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
48
49#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
eaa50e08
MK		 50 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm | \
51 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
52
53#define USDHC_EMMC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
a02d517b
MK		 54 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
55 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
56
a02d517b
MK		 57#define WEAK_PULLUP (PAD_CTL_PUS_100K_UP | \
58 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
59 PAD_CTL_SRE_SLOW)
60
61#define NO_PULLUP ( \
62 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
63 PAD_CTL_SRE_SLOW)
64
65#define WEAK_PULLDOWN (PAD_CTL_PUS_100K_DOWN | \
66 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
67 PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
68
a02d517b
MK		 69#define OUTPUT_RGB (PAD_CTL_SPEED_MED|PAD_CTL_DSE_60ohm|PAD_CTL_SRE_FAST)
70
71int dram_init(void)
72{
73 /* use the DDR controllers configured size */
74 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
75 (ulong)imx_ddr_size());
76
77 return 0;
78}
79
80/* Colibri UARTA */
81iomux_v3_cfg_t const uart1_pads[] = {
82 MX6_PAD_CSI0_DAT10__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
83 MX6_PAD_CSI0_DAT11__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
84};
85
bfeaea7d 86#if defined(CONFIG_FSL_ESDHC_IMX) && defined(CONFIG_SPL_BUILD)
6eea69bd 87/* Colibri MMC */
a02d517b
MK		 88iomux_v3_cfg_t const usdhc1_pads[] = {
89 MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
90 MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
91 MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
92 MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
93 MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
94 MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
95 MX6_PAD_NANDF_D5__GPIO2_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
96# define GPIO_MMC_CD IMX_GPIO_NR(2, 5)
97};
98
99/* eMMC */
100iomux_v3_cfg_t const usdhc3_pads[] = {
eaa50e08
MK		 101 MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
102 MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
103 MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
104 MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
105 MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
106 MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
107 MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
108 MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
109 MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
110 MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
a02d517b
MK		 111 MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL),
112};
e37ac717 113#endif /* CONFIG_FSL_ESDHC_IMX & CONFIG_SPL_BUILD */
a02d517b 114
a02d517b
MK		 115/* mux auxiliary pins to GPIO, so they can be used from the U-Boot cmdline */
116iomux_v3_cfg_t const gpio_pads[] = {
117 /* ADDRESS[17:18] [25] used as GPIO */
e7cf5349
MZ		 118 MX6_PAD_KEY_ROW2__GPIO4_IO11 | MUX_PAD_CTRL(WEAK_PULLUP) |
119 MUX_MODE_SION,
120 MX6_PAD_KEY_COL2__GPIO4_IO10 | MUX_PAD_CTRL(WEAK_PULLUP) |
121 MUX_MODE_SION,
122 MX6_PAD_NANDF_D1__GPIO2_IO01 | MUX_PAD_CTRL(WEAK_PULLUP) |
123 MUX_MODE_SION,
a02d517b 124 /* ADDRESS[19:24] used as GPIO */
e7cf5349
MZ		 125 MX6_PAD_DISP0_DAT23__GPIO5_IO17 | MUX_PAD_CTRL(WEAK_PULLUP) |
126 MUX_MODE_SION,
127 MX6_PAD_DISP0_DAT22__GPIO5_IO16 | MUX_PAD_CTRL(WEAK_PULLUP) |
128 MUX_MODE_SION,
129 MX6_PAD_DISP0_DAT21__GPIO5_IO15 | MUX_PAD_CTRL(WEAK_PULLUP) |
130 MUX_MODE_SION,
131 MX6_PAD_DISP0_DAT20__GPIO5_IO14 | MUX_PAD_CTRL(WEAK_PULLUP) |
132 MUX_MODE_SION,
133 MX6_PAD_DISP0_DAT19__GPIO5_IO13 | MUX_PAD_CTRL(WEAK_PULLUP) |
134 MUX_MODE_SION,
135 MX6_PAD_DISP0_DAT18__GPIO5_IO12 | MUX_PAD_CTRL(WEAK_PULLUP) |
136 MUX_MODE_SION,
a02d517b 137 /* DATA[16:29] [31] used as GPIO */
e7cf5349
MZ		 138 MX6_PAD_EIM_LBA__GPIO2_IO27 | MUX_PAD_CTRL(WEAK_PULLUP) |
139 MUX_MODE_SION,
140 MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(WEAK_PULLUP) |
141 MUX_MODE_SION,
142 MX6_PAD_NANDF_CS3__GPIO6_IO16 | MUX_PAD_CTRL(WEAK_PULLUP) |
143 MUX_MODE_SION,
144 MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(WEAK_PULLUP) |
145 MUX_MODE_SION,
146 MX6_PAD_NANDF_RB0__GPIO6_IO10 | MUX_PAD_CTRL(WEAK_PULLUP) |
147 MUX_MODE_SION,
148 MX6_PAD_NANDF_ALE__GPIO6_IO08 | MUX_PAD_CTRL(WEAK_PULLUP) |
149 MUX_MODE_SION,
150 MX6_PAD_NANDF_WP_B__GPIO6_IO09 | MUX_PAD_CTRL(WEAK_PULLUP) |
151 MUX_MODE_SION,
152 MX6_PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(WEAK_PULLUP) |
153 MUX_MODE_SION,
154 MX6_PAD_NANDF_CLE__GPIO6_IO07 | MUX_PAD_CTRL(WEAK_PULLUP) |
155 MUX_MODE_SION,
156 MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(WEAK_PULLUP) |
157 MUX_MODE_SION,
158 MX6_PAD_CSI0_MCLK__GPIO5_IO19 | MUX_PAD_CTRL(WEAK_PULLUP) |
159 MUX_MODE_SION,
160 MX6_PAD_CSI0_PIXCLK__GPIO5_IO18 | MUX_PAD_CTRL(WEAK_PULLUP) |
161 MUX_MODE_SION,
162 MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(WEAK_PULLUP) |
163 MUX_MODE_SION,
164 MX6_PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(WEAK_PULLUP) |
165 MUX_MODE_SION,
166 MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(WEAK_PULLUP) |
167 MUX_MODE_SION,
a02d517b 168 /* DQM[0:3] used as GPIO */
e7cf5349
MZ		 169 MX6_PAD_EIM_EB0__GPIO2_IO28 | MUX_PAD_CTRL(WEAK_PULLUP) |
170 MUX_MODE_SION,
171 MX6_PAD_EIM_EB1__GPIO2_IO29 | MUX_PAD_CTRL(WEAK_PULLUP) |
172 MUX_MODE_SION,
173 MX6_PAD_SD2_DAT2__GPIO1_IO13 | MUX_PAD_CTRL(WEAK_PULLUP) |
174 MUX_MODE_SION,
175 MX6_PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(WEAK_PULLUP) |
176 MUX_MODE_SION,
a02d517b 177 /* RDY used as GPIO */
e7cf5349
MZ		 178 MX6_PAD_EIM_WAIT__GPIO5_IO00 | MUX_PAD_CTRL(WEAK_PULLUP) |
179 MUX_MODE_SION,
a02d517b 180 /* ADDRESS[16] DATA[30] used as GPIO */
e7cf5349
MZ		 181 MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(WEAK_PULLDOWN) |
182 MUX_MODE_SION,
183 MX6_PAD_KEY_COL4__GPIO4_IO14 | MUX_PAD_CTRL(WEAK_PULLUP) |
184 MUX_MODE_SION,
a02d517b 185 /* CSI pins used as GPIO */
e7cf5349
MZ		 186 MX6_PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(WEAK_PULLUP) |
187 MUX_MODE_SION,
188 MX6_PAD_SD2_CMD__GPIO1_IO11 | MUX_PAD_CTRL(WEAK_PULLUP) |
189 MUX_MODE_SION,
190 MX6_PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(WEAK_PULLUP) |
191 MUX_MODE_SION,
192 MX6_PAD_EIM_D18__GPIO3_IO18 | MUX_PAD_CTRL(WEAK_PULLUP) |
193 MUX_MODE_SION,
194 MX6_PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(WEAK_PULLUP) |
195 MUX_MODE_SION,
196 MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(WEAK_PULLDOWN) |
197 MUX_MODE_SION,
198 MX6_PAD_EIM_A23__GPIO6_IO06 | MUX_PAD_CTRL(WEAK_PULLUP) |
199 MUX_MODE_SION,
200 MX6_PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(WEAK_PULLUP) |
201 MUX_MODE_SION,
202 MX6_PAD_EIM_A17__GPIO2_IO21 | MUX_PAD_CTRL(WEAK_PULLUP) |
203 MUX_MODE_SION,
204 MX6_PAD_EIM_A18__GPIO2_IO20 | MUX_PAD_CTRL(WEAK_PULLUP) |
205 MUX_MODE_SION,
206 MX6_PAD_EIM_EB3__GPIO2_IO31 | MUX_PAD_CTRL(WEAK_PULLUP) |
207 MUX_MODE_SION,
208 MX6_PAD_EIM_D17__GPIO3_IO17 | MUX_PAD_CTRL(WEAK_PULLUP) |
209 MUX_MODE_SION,
210 MX6_PAD_SD2_DAT0__GPIO1_IO15 | MUX_PAD_CTRL(WEAK_PULLUP) |
211 MUX_MODE_SION,
a02d517b 212 /* GPIO */
e7cf5349
MZ		 213 MX6_PAD_EIM_D26__GPIO3_IO26 | MUX_PAD_CTRL(WEAK_PULLUP) |
214 MUX_MODE_SION,
215 MX6_PAD_EIM_D27__GPIO3_IO27 | MUX_PAD_CTRL(WEAK_PULLUP) |
216 MUX_MODE_SION,
217 MX6_PAD_NANDF_D6__GPIO2_IO06 | MUX_PAD_CTRL(WEAK_PULLUP) |
218 MUX_MODE_SION,
219 MX6_PAD_NANDF_D3__GPIO2_IO03 | MUX_PAD_CTRL(WEAK_PULLUP) |
220 MUX_MODE_SION,
221 MX6_PAD_ENET_REF_CLK__GPIO1_IO23 | MUX_PAD_CTRL(WEAK_PULLUP) |
222 MUX_MODE_SION,
223 MX6_PAD_DI0_PIN4__GPIO4_IO20 | MUX_PAD_CTRL(WEAK_PULLUP) |
224 MUX_MODE_SION,
225 MX6_PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(WEAK_PULLUP) |
226 MUX_MODE_SION,
227 MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(WEAK_PULLUP) |
228 MUX_MODE_SION,
229 MX6_PAD_SD4_DAT0__GPIO2_IO08 | MUX_PAD_CTRL(WEAK_PULLUP) |
230 MUX_MODE_SION,
231 MX6_PAD_GPIO_7__GPIO1_IO07 | MUX_PAD_CTRL(WEAK_PULLUP) |
232 MUX_MODE_SION,
233 MX6_PAD_GPIO_8__GPIO1_IO08 | MUX_PAD_CTRL(WEAK_PULLUP) |
234 MUX_MODE_SION,
a02d517b
MK		 235 /* USBH_OC */
236 MX6_PAD_EIM_D30__GPIO3_IO30 | MUX_PAD_CTRL(WEAK_PULLUP),
237 /* USBC_ID */
238 MX6_PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(WEAK_PULLUP),
239 /* USBC_DET */
240 MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(WEAK_PULLUP),
241};
242
243static void setup_iomux_gpio(void)
244{
245 imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads));
246}
247
248iomux_v3_cfg_t const usb_pads[] = {
e7cf5349
MZ		 249 /* USBH_PEN */
250 MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL) | MUX_MODE_SION,
a02d517b
MK		 251# define GPIO_USBH_EN IMX_GPIO_NR(3, 31)
252};
253
254/*
255 * UARTs are used in DTE mode, switch the mode on all UARTs before
256 * any pinmuxing connects a (DCE) output to a transceiver output.
257 */
08621424
MK		 258#define UCR3 0x88 /* FIFO Control Register */
259#define UCR3_RI BIT(8) /* RIDELT DTE mode */
260#define UCR3_DCD BIT(9) /* DCDDELT DTE mode */
a02d517b 261#define UFCR 0x90 /* FIFO Control Register */
08621424 262#define UFCR_DCEDTE BIT(6) /* DCE=0 */
a02d517b
MK		 263
264static void setup_dtemode_uart(void)
265{
266 setbits_le32((u32 *)(UART1_BASE + UFCR), UFCR_DCEDTE);
267 setbits_le32((u32 *)(UART2_BASE + UFCR), UFCR_DCEDTE);
268 setbits_le32((u32 *)(UART3_BASE + UFCR), UFCR_DCEDTE);
08621424
MK		 269
270 clrbits_le32((u32 *)(UART1_BASE + UCR3), UCR3_DCD | UCR3_RI);
271 clrbits_le32((u32 *)(UART2_BASE + UCR3), UCR3_DCD | UCR3_RI);
272 clrbits_le32((u32 *)(UART3_BASE + UCR3), UCR3_DCD | UCR3_RI);
a02d517b
MK		 273}
274
275static void setup_iomux_uart(void)
276{
277 setup_dtemode_uart();
278 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
279}
280
281#ifdef CONFIG_USB_EHCI_MX6
282int board_ehci_hcd_init(int port)
283{
284 imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
285 return 0;
286}
7b726c09 287#endif
a02d517b 288
bfeaea7d 289#if defined(CONFIG_FSL_ESDHC_IMX) && defined(CONFIG_SPL_BUILD)
a02d517b
MK		 290/* use the following sequence: eMMC, MMC */
291struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = {
292 {USDHC3_BASE_ADDR},
293 {USDHC1_BASE_ADDR},
294};
295
296int board_mmc_getcd(struct mmc *mmc)
297{
298 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
299 int ret = true; /* default: assume inserted */
300
301 switch (cfg->esdhc_base) {
302 case USDHC1_BASE_ADDR:
e7cf5349 303 gpio_request(GPIO_MMC_CD, "MMC_CD");
a02d517b
MK		 304 gpio_direction_input(GPIO_MMC_CD);
305 ret = !gpio_get_value(GPIO_MMC_CD);
306 break;
307 }
308
309 return ret;
310}
311
312int board_mmc_init(bd_t *bis)
313{
a02d517b
MK		 314 struct src *psrc = (struct src *)SRC_BASE_ADDR;
315 unsigned reg = readl(&psrc->sbmr1) >> 11;
316 /*
317 * Upon reading BOOT_CFG register the following map is done:
318 * Bit 11 and 12 of BOOT_CFG register can determine the current
319 * mmc port
320 * 0x1 SD1
321 * 0x2 SD2
322 * 0x3 SD4
323 */
324
325 switch (reg & 0x3) {
326 case 0x0:
327 imx_iomux_v3_setup_multiple_pads(
328 usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
329 usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR;
330 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
331 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
332 break;
333 case 0x2:
334 imx_iomux_v3_setup_multiple_pads(
335 usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
336 usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
337 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
338 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
339 break;
340 default:
341 puts("MMC boot device not available");
342 }
343
344 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
a02d517b 345}
e37ac717 346#endif /* CONFIG_FSL_ESDHC_IMX & CONFIG_SPL_BUILD */
a02d517b
MK		 347
348int board_phy_config(struct phy_device *phydev)
349{
350 if (phydev->drv->config)
351 phydev->drv->config(phydev);
352
353 return 0;
354}
355
431cd76d 356int setup_fec(void)
a02d517b 357{
a02d517b 358 int ret;
1efb80c4 359 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
a02d517b
MK		 360
361 /* provide the PHY clock from the i.MX 6 */
362 ret = enable_fec_anatop_clock(0, ENET_50MHZ);
363 if (ret)
364 return ret;
e7cf5349 365
1efb80c4
IO		 366 setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
367
a02d517b
MK		 368 return 0;
369}
370
371static iomux_v3_cfg_t const pwr_intb_pads[] = {
372 /*
373 * the bootrom sets the iomux to vselect, potentially connecting
374 * two outputs. Set this back to GPIO
375 */
376 MX6_PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL)
377};
378
379#if defined(CONFIG_VIDEO_IPUV3)
380
381static iomux_v3_cfg_t const backlight_pads[] = {
382 /* Backlight On */
e7cf5349 383 MX6_PAD_EIM_D26__GPIO3_IO26 | MUX_PAD_CTRL(NO_PAD_CTRL) | MUX_MODE_SION,
a02d517b
MK		 384#define RGB_BACKLIGHT_GP IMX_GPIO_NR(3, 26)
385 /* Backlight PWM, used as GPIO in U-Boot */
386 MX6_PAD_EIM_A22__GPIO2_IO16 | MUX_PAD_CTRL(NO_PULLUP),
e7cf5349
MZ		 387 MX6_PAD_SD4_DAT1__GPIO2_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL) |
388 MUX_MODE_SION,
a02d517b
MK		 389#define RGB_BACKLIGHTPWM_GP IMX_GPIO_NR(2, 9)
390};
391
392static iomux_v3_cfg_t const rgb_pads[] = {
393 MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(OUTPUT_RGB),
394 MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 | MUX_PAD_CTRL(OUTPUT_RGB),
395 MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02 | MUX_PAD_CTRL(OUTPUT_RGB),
396 MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03 | MUX_PAD_CTRL(OUTPUT_RGB),
397 MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 | MUX_PAD_CTRL(OUTPUT_RGB),
398 MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 | MUX_PAD_CTRL(OUTPUT_RGB),
399 MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 | MUX_PAD_CTRL(OUTPUT_RGB),
400 MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 | MUX_PAD_CTRL(OUTPUT_RGB),
401 MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 | MUX_PAD_CTRL(OUTPUT_RGB),
402 MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 | MUX_PAD_CTRL(OUTPUT_RGB),
403 MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 | MUX_PAD_CTRL(OUTPUT_RGB),
404 MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 | MUX_PAD_CTRL(OUTPUT_RGB),
405 MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 | MUX_PAD_CTRL(OUTPUT_RGB),
406 MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 | MUX_PAD_CTRL(OUTPUT_RGB),
407 MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 | MUX_PAD_CTRL(OUTPUT_RGB),
408 MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 | MUX_PAD_CTRL(OUTPUT_RGB),
409 MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 | MUX_PAD_CTRL(OUTPUT_RGB),
410 MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 | MUX_PAD_CTRL(OUTPUT_RGB),
411 MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 | MUX_PAD_CTRL(OUTPUT_RGB),
412 MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 | MUX_PAD_CTRL(OUTPUT_RGB),
413 MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 | MUX_PAD_CTRL(OUTPUT_RGB),
414 MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 | MUX_PAD_CTRL(OUTPUT_RGB),
415};
416
417static void do_enable_hdmi(struct display_info_t const *dev)
418{
419 imx_enable_hdmi_phy();
420}
421
422static void enable_rgb(struct display_info_t const *dev)
423{
424 imx_iomux_v3_setup_multiple_pads(
425 rgb_pads,
426 ARRAY_SIZE(rgb_pads));
427 gpio_direction_output(RGB_BACKLIGHT_GP, 1);
428 gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
429}
430
431static int detect_default(struct display_info_t const *dev)
432{
433 (void) dev;
434 return 1;
435}
436
437struct display_info_t const displays[] = {{
438 .bus = -1,
439 .addr = 0,
440 .pixfmt = IPU_PIX_FMT_RGB24,
441 .detect = detect_hdmi,
442 .enable = do_enable_hdmi,
443 .mode = {
444 .name = "HDMI",
445 .refresh = 60,
446 .xres = 1024,
447 .yres = 768,
448 .pixclock = 15385,
449 .left_margin = 220,
450 .right_margin = 40,
451 .upper_margin = 21,
452 .lower_margin = 7,
453 .hsync_len = 60,
454 .vsync_len = 10,
455 .sync = FB_SYNC_EXT,
456 .vmode = FB_VMODE_NONINTERLACED
457} }, {
458 .bus = -1,
459 .addr = 0,
460 .pixfmt = IPU_PIX_FMT_RGB666,
461 .detect = detect_default,
462 .enable = enable_rgb,
463 .mode = {
464 .name = "vga-rgb",
465 .refresh = 60,
466 .xres = 640,
467 .yres = 480,
468 .pixclock = 33000,
469 .left_margin = 48,
470 .right_margin = 16,
471 .upper_margin = 31,
472 .lower_margin = 11,
473 .hsync_len = 96,
474 .vsync_len = 2,
475 .sync = 0,
476 .vmode = FB_VMODE_NONINTERLACED
477} }, {
478 .bus = -1,
479 .addr = 0,
480 .pixfmt = IPU_PIX_FMT_RGB666,
481 .enable = enable_rgb,
482 .mode = {
483 .name = "wvga-rgb",
484 .refresh = 60,
485 .xres = 800,
486 .yres = 480,
487 .pixclock = 25000,
488 .left_margin = 40,
489 .right_margin = 88,
490 .upper_margin = 33,
491 .lower_margin = 10,
492 .hsync_len = 128,
493 .vsync_len = 2,
494 .sync = 0,
495 .vmode = FB_VMODE_NONINTERLACED
496} } };
497size_t display_count = ARRAY_SIZE(displays);
498
499static void setup_display(void)
500{
501 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
502 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
503 int reg;
504
505 enable_ipu_clock();
506 imx_setup_hdmi();
507 /* Turn on LDB0,IPU,IPU DI0 clocks */
508 reg = __raw_readl(&mxc_ccm->CCGR3);
509 reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
510 writel(reg, &mxc_ccm->CCGR3);
511
512 /* set LDB0, LDB1 clk select to 011/011 */
513 reg = readl(&mxc_ccm->cs2cdr);
514 reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
515 |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
516 reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
517 |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
518 writel(reg, &mxc_ccm->cs2cdr);
519
520 reg = readl(&mxc_ccm->cscmr2);
521 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
522 writel(reg, &mxc_ccm->cscmr2);
523
524 reg = readl(&mxc_ccm->chsccdr);
525 reg |= (CHSCCDR_CLK_SEL_LDB_DI0
526 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
527 writel(reg, &mxc_ccm->chsccdr);
528
529 reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
530 |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
531 |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
532 |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
533 |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
534 |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
535 |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
536 |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
537 |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
538 writel(reg, &iomux->gpr[2]);
539
540 reg = readl(&iomux->gpr[3]);
541 reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK
542 |IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
543 | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
544 <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
545 writel(reg, &iomux->gpr[3]);
546
547 /* backlight unconditionally on for now */
548 imx_iomux_v3_setup_multiple_pads(backlight_pads,
549 ARRAY_SIZE(backlight_pads));
550 /* use 0 for EDT 7", use 1 for LG fullHD panel */
e7cf5349
MZ		 551 gpio_request(RGB_BACKLIGHTPWM_GP, "PWM<A>");
552 gpio_request(RGB_BACKLIGHT_GP, "BL_ON");
a02d517b
MK		 553 gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
554 gpio_direction_output(RGB_BACKLIGHT_GP, 1);
555}
a3c90217
GS		 556
557/*
558 * Backlight off before OS handover
559 */
560void board_preboot_os(void)
561{
562 gpio_direction_output(RGB_BACKLIGHTPWM_GP, 1);
563 gpio_direction_output(RGB_BACKLIGHT_GP, 0);
564}
a02d517b
MK		 565#endif /* defined(CONFIG_VIDEO_IPUV3) */
566
567int board_early_init_f(void)
568{
569 imx_iomux_v3_setup_multiple_pads(pwr_intb_pads,
570 ARRAY_SIZE(pwr_intb_pads));
571 setup_iomux_uart();
572
a02d517b
MK		 573 return 0;
574}
575
576/*
577 * Do not overwrite the console
578 * Use always serial for U-Boot console
579 */
580int overwrite_console(void)
581{
582 return 1;
583}
584
585int board_init(void)
586{
587 /* address of boot parameters */
588 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
431cd76d
IO		 589#if defined(CONFIG_FEC_MXC)
590 setup_fec();
591#endif
464c988a
FE		 592#if defined(CONFIG_VIDEO_IPUV3)
593 setup_display();
594#endif
595
a02d517b
MK		 596#ifdef CONFIG_TDX_CMD_IMX_MFGR
597 (void) pmic_init();
598#endif
599
10e40d54 600#ifdef CONFIG_SATA
a02d517b
MK		 601 setup_sata();
602#endif
603
604 setup_iomux_gpio();
605
606 return 0;
607}
608
609#ifdef CONFIG_BOARD_LATE_INIT
610int board_late_init(void)
611{
612#if defined(CONFIG_REVISION_TAG) && \
613 defined(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)
614 char env_str[256];
615 u32 rev;
616
617 rev = get_board_rev();
618 snprintf(env_str, ARRAY_SIZE(env_str), "%.4x", rev);
382bee57 619 env_set("board_rev", env_str);
a02d517b
MK		 620#endif
621
52084bfc
SA		 622#ifdef CONFIG_CMD_USB_SDP
623 if (is_boot_from_usb()) {
624 printf("Serial Downloader recovery mode, using sdp command\n");
625 env_set("bootdelay", "0");
626 env_set("bootcmd", "sdp 0");
627 }
628#endif /* CONFIG_CMD_USB_SDP */
629
a02d517b
MK		 630 return 0;
631}
632#endif /* CONFIG_BOARD_LATE_INIT */
633
a02d517b
MK		 634int checkboard(void)
635{
636 char it[] = " IT";
637 int minc, maxc;
638
639 switch (get_cpu_temp_grade(&minc, &maxc)) {
640 case TEMP_AUTOMOTIVE:
641 case TEMP_INDUSTRIAL:
642 break;
643 case TEMP_EXTCOMMERCIAL:
644 default:
645 it[0] = 0;
646 };
647 printf("Model: Toradex Colibri iMX6 %s %sMB%s\n",
648 is_cpu_type(MXC_CPU_MX6DL) ? "DualLite" : "Solo",
649 (gd->ram_size == 0x20000000) ? "512" : "256", it);
650 return 0;
651}
652
653#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
654int ft_board_setup(void *blob, bd_t *bd)
655{
bee73083
BD		 656 u32 cma_size;
657
658 ft_common_board_setup(blob, bd);
659
52084bfc 660 cma_size = env_get_ulong("cma-size", 10, 320 * 1024 * 1024);
bee73083
BD		 661 cma_size = min((u32)(gd->ram_size >> 1), cma_size);
662
663 fdt_setprop_u32(blob,
664 fdt_path_offset(blob, "/reserved-memory/linux,cma"),
665 "size",
666 cma_size);
667 return 0;
a02d517b
MK		 668}
669#endif
670
671#ifdef CONFIG_CMD_BMODE
672static const struct boot_mode board_boot_modes[] = {
673 {"mmc", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
674 {NULL, 0},
675};
676#endif
677
678int misc_init_r(void)
679{
680#ifdef CONFIG_CMD_BMODE
681 add_board_boot_modes(board_boot_modes);
682#endif
683 return 0;
684}
685
686#ifdef CONFIG_LDO_BYPASS_CHECK
687/* TODO, use external pmic, for now always ldo_enable */
688void ldo_mode_set(int ldo_bypass)
689{
690 return;
691}
692#endif
693
694#ifdef CONFIG_SPL_BUILD
695#include <spl.h>
b08c8c48 696#include <linux/libfdt.h>
a02d517b
MK		 697#include "asm/arch/mx6dl-ddr.h"
698#include "asm/arch/iomux.h"
699#include "asm/arch/crm_regs.h"
700
701static int mx6s_dcd_table[] = {
702/* ddr-setup.cfg */
703
704MX6_IOM_DRAM_SDQS0, 0x00000030,
705MX6_IOM_DRAM_SDQS1, 0x00000030,
706MX6_IOM_DRAM_SDQS2, 0x00000030,
707MX6_IOM_DRAM_SDQS3, 0x00000030,
708MX6_IOM_DRAM_SDQS4, 0x00000030,
709MX6_IOM_DRAM_SDQS5, 0x00000030,
710MX6_IOM_DRAM_SDQS6, 0x00000030,
711MX6_IOM_DRAM_SDQS7, 0x00000030,
712
713MX6_IOM_GRP_B0DS, 0x00000030,
714MX6_IOM_GRP_B1DS, 0x00000030,
715MX6_IOM_GRP_B2DS, 0x00000030,
716MX6_IOM_GRP_B3DS, 0x00000030,
717MX6_IOM_GRP_B4DS, 0x00000030,
718MX6_IOM_GRP_B5DS, 0x00000030,
719MX6_IOM_GRP_B6DS, 0x00000030,
720MX6_IOM_GRP_B7DS, 0x00000030,
721MX6_IOM_GRP_ADDDS, 0x00000030,
722/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
723MX6_IOM_GRP_CTLDS, 0x00000030,
724
725MX6_IOM_DRAM_DQM0, 0x00020030,
726MX6_IOM_DRAM_DQM1, 0x00020030,
727MX6_IOM_DRAM_DQM2, 0x00020030,
728MX6_IOM_DRAM_DQM3, 0x00020030,
729MX6_IOM_DRAM_DQM4, 0x00020030,
730MX6_IOM_DRAM_DQM5, 0x00020030,
731MX6_IOM_DRAM_DQM6, 0x00020030,
732MX6_IOM_DRAM_DQM7, 0x00020030,
733
734MX6_IOM_DRAM_CAS, 0x00020030,
735MX6_IOM_DRAM_RAS, 0x00020030,
736MX6_IOM_DRAM_SDCLK_0, 0x00020030,
737MX6_IOM_DRAM_SDCLK_1, 0x00020030,
738
739MX6_IOM_DRAM_RESET, 0x00020030,
740MX6_IOM_DRAM_SDCKE0, 0x00003000,
741MX6_IOM_DRAM_SDCKE1, 0x00003000,
742
743MX6_IOM_DRAM_SDODT0, 0x00003030,
744MX6_IOM_DRAM_SDODT1, 0x00003030,
745
746/* (differential input) */
747MX6_IOM_DDRMODE_CTL, 0x00020000,
748/* (differential input) */
749MX6_IOM_GRP_DDRMODE, 0x00020000,
750/* disable ddr pullups */
751MX6_IOM_GRP_DDRPKE, 0x00000000,
752MX6_IOM_DRAM_SDBA2, 0x00000000,
753/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
754MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
755
756/* Read data DQ Byte0-3 delay */
757MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
758MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
759MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
760MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
761MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333,
762MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333,
763MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333,
764MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333,
765
766/*
767 * MDMISC mirroring interleaved (row/bank/col)
768 */
769/* TODO: check what the RALAT field does */
770MX6_MMDC_P0_MDMISC, 0x00081740,
771
772/*
773 * MDSCR con_req
774 */
775MX6_MMDC_P0_MDSCR, 0x00008000,
776
777
778/* 800mhz_2x64mx16.cfg */
779
780MX6_MMDC_P0_MDPDC, 0x0002002D,
781MX6_MMDC_P0_MDCFG0, 0x2C305503,
782MX6_MMDC_P0_MDCFG1, 0xB66D8D63,
783MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
784MX6_MMDC_P0_MDRWD, 0x000026D2,
785MX6_MMDC_P0_MDOR, 0x00301023,
786MX6_MMDC_P0_MDOTC, 0x00333030,
787MX6_MMDC_P0_MDPDC, 0x0002556D,
788/* CS0 End: 7MSB of ((0x10000000, + 512M) -1) >> 25 */
789MX6_MMDC_P0_MDASP, 0x00000017,
790/* DDR3 DATA BUS SIZE: 64BIT */
791/* MX6_MMDC_P0_MDCTL, 0x821A0000, */
792/* DDR3 DATA BUS SIZE: 32BIT */
793MX6_MMDC_P0_MDCTL, 0x82190000,
794
795/* Write commands to DDR */
796/* Load Mode Registers */
797/* TODO Use Auto Self-Refresh mode (Extended Temperature)*/
798/* MX6_MMDC_P0_MDSCR, 0x04408032, */
799MX6_MMDC_P0_MDSCR, 0x04008032,
800MX6_MMDC_P0_MDSCR, 0x00008033,
801MX6_MMDC_P0_MDSCR, 0x00048031,
802MX6_MMDC_P0_MDSCR, 0x13208030,
803/* ZQ calibration */
804MX6_MMDC_P0_MDSCR, 0x04008040,
805
806MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
807MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003,
808MX6_MMDC_P0_MDREF, 0x00005800,
809
810MX6_MMDC_P0_MPODTCTRL, 0x00000000,
811MX6_MMDC_P1_MPODTCTRL, 0x00000000,
812
813MX6_MMDC_P0_MPDGCTRL0, 0x42360232,
814MX6_MMDC_P0_MPDGCTRL1, 0x021F022A,
815MX6_MMDC_P1_MPDGCTRL0, 0x421E0224,
816MX6_MMDC_P1_MPDGCTRL1, 0x02110218,
817
818MX6_MMDC_P0_MPRDDLCTL, 0x41434344,
819MX6_MMDC_P1_MPRDDLCTL, 0x4345423E,
820MX6_MMDC_P0_MPWRDLCTL, 0x39383339,
821MX6_MMDC_P1_MPWRDLCTL, 0x3E363930,
822
823MX6_MMDC_P0_MPWLDECTRL0, 0x00340039,
824MX6_MMDC_P0_MPWLDECTRL1, 0x002C002D,
825MX6_MMDC_P1_MPWLDECTRL0, 0x00120019,
826MX6_MMDC_P1_MPWLDECTRL1, 0x0012002D,
827
828MX6_MMDC_P0_MPMUR0, 0x00000800,
829MX6_MMDC_P1_MPMUR0, 0x00000800,
830MX6_MMDC_P0_MDSCR, 0x00000000,
831MX6_MMDC_P0_MAPSR, 0x00011006,
832};
833
834static int mx6dl_dcd_table[] = {
835/* ddr-setup.cfg */
836
837MX6_IOM_DRAM_SDQS0, 0x00000030,
838MX6_IOM_DRAM_SDQS1, 0x00000030,
839MX6_IOM_DRAM_SDQS2, 0x00000030,
840MX6_IOM_DRAM_SDQS3, 0x00000030,
841MX6_IOM_DRAM_SDQS4, 0x00000030,
842MX6_IOM_DRAM_SDQS5, 0x00000030,
843MX6_IOM_DRAM_SDQS6, 0x00000030,
844MX6_IOM_DRAM_SDQS7, 0x00000030,
845
846MX6_IOM_GRP_B0DS, 0x00000030,
847MX6_IOM_GRP_B1DS, 0x00000030,
848MX6_IOM_GRP_B2DS, 0x00000030,
849MX6_IOM_GRP_B3DS, 0x00000030,
850MX6_IOM_GRP_B4DS, 0x00000030,
851MX6_IOM_GRP_B5DS, 0x00000030,
852MX6_IOM_GRP_B6DS, 0x00000030,
853MX6_IOM_GRP_B7DS, 0x00000030,
854MX6_IOM_GRP_ADDDS, 0x00000030,
855/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
856MX6_IOM_GRP_CTLDS, 0x00000030,
857
858MX6_IOM_DRAM_DQM0, 0x00020030,
859MX6_IOM_DRAM_DQM1, 0x00020030,
860MX6_IOM_DRAM_DQM2, 0x00020030,
861MX6_IOM_DRAM_DQM3, 0x00020030,
862MX6_IOM_DRAM_DQM4, 0x00020030,
863MX6_IOM_DRAM_DQM5, 0x00020030,
864MX6_IOM_DRAM_DQM6, 0x00020030,
865MX6_IOM_DRAM_DQM7, 0x00020030,
866
867MX6_IOM_DRAM_CAS, 0x00020030,
868MX6_IOM_DRAM_RAS, 0x00020030,
869MX6_IOM_DRAM_SDCLK_0, 0x00020030,
870MX6_IOM_DRAM_SDCLK_1, 0x00020030,
871
872MX6_IOM_DRAM_RESET, 0x00020030,
873MX6_IOM_DRAM_SDCKE0, 0x00003000,
874MX6_IOM_DRAM_SDCKE1, 0x00003000,
875
876MX6_IOM_DRAM_SDODT0, 0x00003030,
877MX6_IOM_DRAM_SDODT1, 0x00003030,
878
879/* (differential input) */
880MX6_IOM_DDRMODE_CTL, 0x00020000,
881/* (differential input) */
882MX6_IOM_GRP_DDRMODE, 0x00020000,
883/* disable ddr pullups */
884MX6_IOM_GRP_DDRPKE, 0x00000000,
885MX6_IOM_DRAM_SDBA2, 0x00000000,
886/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
887MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
888
889/* Read data DQ Byte0-3 delay */
890MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
891MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
892MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
893MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
894MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333,
895MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333,
896MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333,
897MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333,
898
899/*
900 * MDMISC mirroring interleaved (row/bank/col)
901 */
902/* TODO: check what the RALAT field does */
903MX6_MMDC_P0_MDMISC, 0x00081740,
904
905/*
906 * MDSCR con_req
907 */
908MX6_MMDC_P0_MDSCR, 0x00008000,
909
910
911/* 800mhz_2x64mx16.cfg */
912
913MX6_MMDC_P0_MDPDC, 0x0002002D,
914MX6_MMDC_P0_MDCFG0, 0x2C305503,
915MX6_MMDC_P0_MDCFG1, 0xB66D8D63,
916MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
917MX6_MMDC_P0_MDRWD, 0x000026D2,
918MX6_MMDC_P0_MDOR, 0x00301023,
919MX6_MMDC_P0_MDOTC, 0x00333030,
920MX6_MMDC_P0_MDPDC, 0x0002556D,
921/* CS0 End: 7MSB of ((0x10000000, + 512M) -1) >> 25 */
922MX6_MMDC_P0_MDASP, 0x00000017,
923/* DDR3 DATA BUS SIZE: 64BIT */
924MX6_MMDC_P0_MDCTL, 0x821A0000,
925/* DDR3 DATA BUS SIZE: 32BIT */
926/* MX6_MMDC_P0_MDCTL, 0x82190000, */
927
928/* Write commands to DDR */
929/* Load Mode Registers */
930/* TODO Use Auto Self-Refresh mode (Extended Temperature)*/
931/* MX6_MMDC_P0_MDSCR, 0x04408032, */
932MX6_MMDC_P0_MDSCR, 0x04008032,
933MX6_MMDC_P0_MDSCR, 0x00008033,
934MX6_MMDC_P0_MDSCR, 0x00048031,
935MX6_MMDC_P0_MDSCR, 0x13208030,
936/* ZQ calibration */
937MX6_MMDC_P0_MDSCR, 0x04008040,
938
939MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
940MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003,
941MX6_MMDC_P0_MDREF, 0x00005800,
942
943MX6_MMDC_P0_MPODTCTRL, 0x00000000,
944MX6_MMDC_P1_MPODTCTRL, 0x00000000,
945
946MX6_MMDC_P0_MPDGCTRL0, 0x42360232,
947MX6_MMDC_P0_MPDGCTRL1, 0x021F022A,
948MX6_MMDC_P1_MPDGCTRL0, 0x421E0224,
949MX6_MMDC_P1_MPDGCTRL1, 0x02110218,
950
951MX6_MMDC_P0_MPRDDLCTL, 0x41434344,
952MX6_MMDC_P1_MPRDDLCTL, 0x4345423E,
953MX6_MMDC_P0_MPWRDLCTL, 0x39383339,
954MX6_MMDC_P1_MPWRDLCTL, 0x3E363930,
955
956MX6_MMDC_P0_MPWLDECTRL0, 0x00340039,
957MX6_MMDC_P0_MPWLDECTRL1, 0x002C002D,
958MX6_MMDC_P1_MPWLDECTRL0, 0x00120019,
959MX6_MMDC_P1_MPWLDECTRL1, 0x0012002D,
960
961MX6_MMDC_P0_MPMUR0, 0x00000800,
962MX6_MMDC_P1_MPMUR0, 0x00000800,
963MX6_MMDC_P0_MDSCR, 0x00000000,
964MX6_MMDC_P0_MAPSR, 0x00011006,
965};
966
967static void ccgr_init(void)
968{
969 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
970
971 writel(0x00C03F3F, &ccm->CCGR0);
972 writel(0x0030FC03, &ccm->CCGR1);
973 writel(0x0FFFFFF3, &ccm->CCGR2);
974 writel(0x3FF0300F, &ccm->CCGR3);
975 writel(0x00FFF300, &ccm->CCGR4);
976 writel(0x0F0000F3, &ccm->CCGR5);
977 writel(0x000003FF, &ccm->CCGR6);
978
979/*
980 * Setup CCM_CCOSR register as follows:
981 *
982 * cko1_en = 1 --> CKO1 enabled
983 * cko1_div = 111 --> divide by 8
984 * cko1_sel = 1011 --> ahb_clk_root
985 *
986 * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
987 */
988 writel(0x000000FB, &ccm->ccosr);
989}
990
a02d517b
MK		 991static void ddr_init(int *table, int size)
992{
993 int i;
994
995 for (i = 0; i < size / 2 ; i++)
996 writel(table[2 * i + 1], table[2 * i]);
997}
998
999static void spl_dram_init(void)
1000{
1001 int minc, maxc;
1002
1003 switch (get_cpu_temp_grade(&minc, &maxc)) {
1004 case TEMP_COMMERCIAL:
1005 case TEMP_EXTCOMMERCIAL:
1006 if (is_cpu_type(MXC_CPU_MX6DL)) {
1007 puts("Commercial temperature grade DDR3 timings, 64bit bus width.\n");
1008 ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table));
1009 } else {
1010 puts("Commercial temperature grade DDR3 timings, 32bit bus width.\n");
1011 ddr_init(mx6s_dcd_table, ARRAY_SIZE(mx6s_dcd_table));
1012 }
1013 break;
1014 case TEMP_INDUSTRIAL:
1015 case TEMP_AUTOMOTIVE:
1016 default:
1017 if (is_cpu_type(MXC_CPU_MX6DL)) {
2910c0a1 1018 puts("Industrial temperature grade DDR3 timings, 64bit bus width.\n");
a02d517b
MK		 1019 ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table));
1020 } else {
1021 puts("Industrial temperature grade DDR3 timings, 32bit bus width.\n");
1022 ddr_init(mx6s_dcd_table, ARRAY_SIZE(mx6s_dcd_table));
1023 }
1024 break;
1025 };
1026 udelay(100);
1027}
1028
82029bf5
GS		 1029static iomux_v3_cfg_t const gpio_reset_pad[] = {
1030 MX6_PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL) |
1031 MUX_MODE_SION
1032#define GPIO_NRESET IMX_GPIO_NR(6, 27)
1033};
1034
1035#define IMX_RESET_CAUSE_POR 0x00011
1036static void nreset_out(void)
1037{
1038 int reset_cause = get_imx_reset_cause();
1039
1040 if (reset_cause != IMX_RESET_CAUSE_POR) {
1041 imx_iomux_v3_setup_multiple_pads(gpio_reset_pad,
1042 ARRAY_SIZE(gpio_reset_pad));
1043 gpio_direction_output(GPIO_NRESET, 1);
1044 udelay(100);
1045 gpio_direction_output(GPIO_NRESET, 0);
1046 }
1047}
1048
a02d517b
MK		 1049void board_init_f(ulong dummy)
1050{
1051 /* setup AIPS and disable watchdog */
1052 arch_cpu_init();
1053
1054 ccgr_init();
1055 gpr_init();
1056
6eea69bd 1057 /* iomux */
a02d517b
MK		 1058 board_early_init_f();
1059
1060 /* setup GP timer */
1061 timer_init();
1062
1063 /* UART clocks enabled and gd valid - init serial console */
1064 preloader_console_init();
1065
1066 /* Make sure we use dte mode */
1067 setup_dtemode_uart();
1068
1069 /* DDR initialization */
1070 spl_dram_init();
1071
1072 /* Clear the BSS. */
1073 memset(__bss_start, 0, __bss_end - __bss_start);
1074
82029bf5
GS		 1075 /* Assert nReset_Out */
1076 nreset_out();
1077
a02d517b
MK		 1078 /* load/boot image from boot device */
1079 board_init_r(NULL, 0);
1080}
1081
1082void reset_cpu(ulong addr)
1083{
1084}
1085
e7cf5349 1086#endif /* CONFIG_SPL_BUILD */
a02d517b
MK		 1087
1088static struct mxc_serial_platdata mxc_serial_plat = {
1089 .reg = (struct mxc_uart *)UART1_BASE,
1090 .use_dte = true,
1091};
1092
1093U_BOOT_DEVICE(mxc_serial) = {
1094 .name = "serial_mxc",
1095 .platdata = &mxc_serial_plat,
1096};
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