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dm: usb: Add a legacy block interface for USB storage
[u-boot.git] / drivers / mmc / mmc.c
CommitLineData
272cc70b
AF		 1/*
2 * Copyright 2008, Freescale Semiconductor, Inc
3 * Andy Fleming
4 *
5 * Based vaguely on the Linux code
6 *
1a459660 7 * SPDX-License-Identifier: GPL-2.0+
272cc70b
AF		 8 */
9
10#include <config.h>
11#include <common.h>
12#include <command.h>
8e3332e2
SS		 13#include <dm.h>
14#include <dm/device-internal.h>
d4622df3 15#include <errno.h>
272cc70b
AF		 16#include <mmc.h>
17#include <part.h>
18#include <malloc.h>
cf92e05c 19#include <memalign.h>
272cc70b 20#include <linux/list.h>
9b1f942c 21#include <div64.h>
da61fa5f 22#include "mmc_private.h"
272cc70b
AF		 23
24static struct list_head mmc_devices;
25static int cur_dev_num = -1;
26
750121c3 27__weak int board_mmc_getwp(struct mmc *mmc)
d23d8d7e
NK		 28{
29 return -1;
30}
31
32int mmc_getwp(struct mmc *mmc)
33{
34 int wp;
35
36 wp = board_mmc_getwp(mmc);
37
d4e1da4e 38 if (wp < 0) {
93bfd616
PA		 39 if (mmc->cfg->ops->getwp)
40 wp = mmc->cfg->ops->getwp(mmc);
d4e1da4e
PK		 41 else
42 wp = 0;
43 }
d23d8d7e
NK		 44
45 return wp;
46}
47
cee9ab7c
JH		 48__weak int board_mmc_getcd(struct mmc *mmc)
49{
11fdade2
SB		 50 return -1;
51}
52
da61fa5f 53int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
272cc70b 54{
5db2fe3a 55 int ret;
8635ff9e 56
8635ff9e 57#ifdef CONFIG_MMC_TRACE
5db2fe3a
RR		 58 int i;
59 u8 *ptr;
60
61 printf("CMD_SEND:%d\n", cmd->cmdidx);
62 printf("\t\tARG\t\t\t 0x%08X\n", cmd->cmdarg);
93bfd616 63 ret = mmc->cfg->ops->send_cmd(mmc, cmd, data);
7863ce58
BM		 64 if (ret) {
65 printf("\t\tRET\t\t\t %d\n", ret);
66 } else {
67 switch (cmd->resp_type) {
68 case MMC_RSP_NONE:
69 printf("\t\tMMC_RSP_NONE\n");
70 break;
71 case MMC_RSP_R1:
72 printf("\t\tMMC_RSP_R1,5,6,7 \t 0x%08X \n",
73 cmd->response[0]);
74 break;
75 case MMC_RSP_R1b:
76 printf("\t\tMMC_RSP_R1b\t\t 0x%08X \n",
77 cmd->response[0]);
78 break;
79 case MMC_RSP_R2:
80 printf("\t\tMMC_RSP_R2\t\t 0x%08X \n",
81 cmd->response[0]);
82 printf("\t\t \t\t 0x%08X \n",
83 cmd->response[1]);
84 printf("\t\t \t\t 0x%08X \n",
85 cmd->response[2]);
86 printf("\t\t \t\t 0x%08X \n",
87 cmd->response[3]);
5db2fe3a 88 printf("\n");
7863ce58
BM		 89 printf("\t\t\t\t\tDUMPING DATA\n");
90 for (i = 0; i < 4; i++) {
91 int j;
92 printf("\t\t\t\t\t%03d - ", i*4);
93 ptr = (u8 *)&cmd->response[i];
94 ptr += 3;
95 for (j = 0; j < 4; j++)
96 printf("%02X ", *ptr--);
97 printf("\n");
98 }
99 break;
100 case MMC_RSP_R3:
101 printf("\t\tMMC_RSP_R3,4\t\t 0x%08X \n",
102 cmd->response[0]);
103 break;
104 default:
105 printf("\t\tERROR MMC rsp not supported\n");
106 break;
53e8e40b 107 }
5db2fe3a 108 }
5db2fe3a 109#else
93bfd616 110 ret = mmc->cfg->ops->send_cmd(mmc, cmd, data);
5db2fe3a 111#endif
8635ff9e 112 return ret;
272cc70b
AF		 113}
114
da61fa5f 115int mmc_send_status(struct mmc *mmc, int timeout)
5d4fc8d9
RR		 116{
117 struct mmc_cmd cmd;
d617c426 118 int err, retries = 5;
5d4fc8d9
RR		 119#ifdef CONFIG_MMC_TRACE
120 int status;
121#endif
122
123 cmd.cmdidx = MMC_CMD_SEND_STATUS;
124 cmd.resp_type = MMC_RSP_R1;
aaf3d41a
MV		 125 if (!mmc_host_is_spi(mmc))
126 cmd.cmdarg = mmc->rca << 16;
5d4fc8d9 127
1677eef4 128 while (1) {
5d4fc8d9 129 err = mmc_send_cmd(mmc, &cmd, NULL);
d617c426
JK		 130 if (!err) {
131 if ((cmd.response[0] & MMC_STATUS_RDY_FOR_DATA) &&
132 (cmd.response[0] & MMC_STATUS_CURR_STATE) !=
133 MMC_STATE_PRG)
134 break;
135 else if (cmd.response[0] & MMC_STATUS_MASK) {
56196826 136#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
d617c426
JK		 137 printf("Status Error: 0x%08X\n",
138 cmd.response[0]);
56196826 139#endif
d617c426
JK		 140 return COMM_ERR;
141 }
142 } else if (--retries < 0)
5d4fc8d9 143 return err;
5d4fc8d9 144
1677eef4
AG		 145 if (timeout-- <= 0)
146 break;
5d4fc8d9 147
1677eef4
AG		 148 udelay(1000);
149 }
5d4fc8d9 150
5db2fe3a
RR		 151#ifdef CONFIG_MMC_TRACE
152 status = (cmd.response[0] & MMC_STATUS_CURR_STATE) >> 9;
153 printf("CURR STATE:%d\n", status);
154#endif
5b0c942f 155 if (timeout <= 0) {
56196826 156#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
5d4fc8d9 157 printf("Timeout waiting card ready\n");
56196826 158#endif
5d4fc8d9
RR		 159 return TIMEOUT;
160 }
6b2221b0
AG		 161 if (cmd.response[0] & MMC_STATUS_SWITCH_ERROR)
162 return SWITCH_ERR;
5d4fc8d9
RR		 163
164 return 0;
165}
166
da61fa5f 167int mmc_set_blocklen(struct mmc *mmc, int len)
272cc70b
AF		 168{
169 struct mmc_cmd cmd;
170
786e8f81 171 if (mmc->ddr_mode)
d22e3d46
JC		 172 return 0;
173
272cc70b
AF		 174 cmd.cmdidx = MMC_CMD_SET_BLOCKLEN;
175 cmd.resp_type = MMC_RSP_R1;
176 cmd.cmdarg = len;
272cc70b
AF		 177
178 return mmc_send_cmd(mmc, &cmd, NULL);
179}
180
181struct mmc *find_mmc_device(int dev_num)
182{
183 struct mmc *m;
184 struct list_head *entry;
185
186 list_for_each(entry, &mmc_devices) {
187 m = list_entry(entry, struct mmc, link);
188
bcce53d0 189 if (m->block_dev.devnum == dev_num)
272cc70b
AF		 190 return m;
191 }
192
56196826 193#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
272cc70b 194 printf("MMC Device %d not found\n", dev_num);
56196826 195#endif
272cc70b
AF		 196
197 return NULL;
198}
199
ff8fef56 200static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start,
fdbb873e 201 lbaint_t blkcnt)
272cc70b
AF		 202{
203 struct mmc_cmd cmd;
204 struct mmc_data data;
205
4a1a06bc
AS		 206 if (blkcnt > 1)
207 cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK;
208 else
209 cmd.cmdidx = MMC_CMD_READ_SINGLE_BLOCK;
272cc70b
AF		 210
211 if (mmc->high_capacity)
4a1a06bc 212 cmd.cmdarg = start;
272cc70b 213 else
4a1a06bc 214 cmd.cmdarg = start * mmc->read_bl_len;
272cc70b
AF		 215
216 cmd.resp_type = MMC_RSP_R1;
272cc70b
AF		 217
218 data.dest = dst;
4a1a06bc 219 data.blocks = blkcnt;
272cc70b
AF		 220 data.blocksize = mmc->read_bl_len;
221 data.flags = MMC_DATA_READ;
222
4a1a06bc
AS		 223 if (mmc_send_cmd(mmc, &cmd, &data))
224 return 0;
272cc70b 225
4a1a06bc
AS		 226 if (blkcnt > 1) {
227 cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
228 cmd.cmdarg = 0;
229 cmd.resp_type = MMC_RSP_R1b;
4a1a06bc 230 if (mmc_send_cmd(mmc, &cmd, NULL)) {
56196826 231#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
4a1a06bc 232 printf("mmc fail to send stop cmd\n");
56196826 233#endif
4a1a06bc
AS		 234 return 0;
235 }
272cc70b
AF		 236 }
237
4a1a06bc 238 return blkcnt;
272cc70b
AF		 239}
240
4101f687 241static ulong mmc_bread(struct blk_desc *block_dev, lbaint_t start,
7c4213f6 242 lbaint_t blkcnt, void *dst)
272cc70b 243{
bcce53d0 244 int dev_num = block_dev->devnum;
873cc1d7 245 int err;
4a1a06bc
AS		 246 lbaint_t cur, blocks_todo = blkcnt;
247
248 if (blkcnt == 0)
249 return 0;
272cc70b 250
4a1a06bc 251 struct mmc *mmc = find_mmc_device(dev_num);
272cc70b
AF		 252 if (!mmc)
253 return 0;
254
873cc1d7
SW		 255 err = mmc_select_hwpart(dev_num, block_dev->hwpart);
256 if (err < 0)
257 return 0;
258
d2bf29e3 259 if ((start + blkcnt) > mmc->block_dev.lba) {
56196826 260#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
ff8fef56 261 printf("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n",
d2bf29e3 262 start + blkcnt, mmc->block_dev.lba);
56196826 263#endif
d2bf29e3
LW		 264 return 0;
265 }
272cc70b 266
11692991
SG		 267 if (mmc_set_blocklen(mmc, mmc->read_bl_len)) {
268 debug("%s: Failed to set blocklen\n", __func__);
272cc70b 269 return 0;
11692991 270 }
272cc70b 271
4a1a06bc 272 do {
93bfd616
PA		 273 cur = (blocks_todo > mmc->cfg->b_max) ?
274 mmc->cfg->b_max : blocks_todo;
11692991
SG		 275 if (mmc_read_blocks(mmc, dst, start, cur) != cur) {
276 debug("%s: Failed to read blocks\n", __func__);
4a1a06bc 277 return 0;
11692991 278 }
4a1a06bc
AS		 279 blocks_todo -= cur;
280 start += cur;
281 dst += cur * mmc->read_bl_len;
282 } while (blocks_todo > 0);
272cc70b
AF		 283
284 return blkcnt;
285}
286
fdbb873e 287static int mmc_go_idle(struct mmc *mmc)
272cc70b
AF		 288{
289 struct mmc_cmd cmd;
290 int err;
291
292 udelay(1000);
293
294 cmd.cmdidx = MMC_CMD_GO_IDLE_STATE;
295 cmd.cmdarg = 0;
296 cmd.resp_type = MMC_RSP_NONE;
272cc70b
AF		 297
298 err = mmc_send_cmd(mmc, &cmd, NULL);
299
300 if (err)
301 return err;
302
303 udelay(2000);
304
305 return 0;
306}
307
fdbb873e 308static int sd_send_op_cond(struct mmc *mmc)
272cc70b
AF		 309{
310 int timeout = 1000;
311 int err;
312 struct mmc_cmd cmd;
313
1677eef4 314 while (1) {
272cc70b
AF		 315 cmd.cmdidx = MMC_CMD_APP_CMD;
316 cmd.resp_type = MMC_RSP_R1;
317 cmd.cmdarg = 0;
272cc70b
AF		 318
319 err = mmc_send_cmd(mmc, &cmd, NULL);
320
321 if (err)
322 return err;
323
324 cmd.cmdidx = SD_CMD_APP_SEND_OP_COND;
325 cmd.resp_type = MMC_RSP_R3;
250de12b
SB		 326
327 /*
328 * Most cards do not answer if some reserved bits
329 * in the ocr are set. However, Some controller
330 * can set bit 7 (reserved for low voltages), but
331 * how to manage low voltages SD card is not yet
332 * specified.
333 */
d52ebf10 334 cmd.cmdarg = mmc_host_is_spi(mmc) ? 0 :
93bfd616 335 (mmc->cfg->voltages & 0xff8000);
272cc70b
AF		 336
337 if (mmc->version == SD_VERSION_2)
338 cmd.cmdarg |= OCR_HCS;
339
340 err = mmc_send_cmd(mmc, &cmd, NULL);
341
342 if (err)
343 return err;
344
1677eef4
AG		 345 if (cmd.response[0] & OCR_BUSY)
346 break;
347
348 if (timeout-- <= 0)
349 return UNUSABLE_ERR;
272cc70b 350
1677eef4
AG		 351 udelay(1000);
352 }
272cc70b
AF		 353
354 if (mmc->version != SD_VERSION_2)
355 mmc->version = SD_VERSION_1_0;
356
d52ebf10
TC		 357 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
358 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
359 cmd.resp_type = MMC_RSP_R3;
360 cmd.cmdarg = 0;
d52ebf10
TC		 361
362 err = mmc_send_cmd(mmc, &cmd, NULL);
363
364 if (err)
365 return err;
366 }
367
998be3dd 368 mmc->ocr = cmd.response[0];
272cc70b
AF		 369
370 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
371 mmc->rca = 0;
372
373 return 0;
374}
375
5289b535 376static int mmc_send_op_cond_iter(struct mmc *mmc, int use_arg)
272cc70b 377{
5289b535 378 struct mmc_cmd cmd;
272cc70b
AF		 379 int err;
380
5289b535
AG		 381 cmd.cmdidx = MMC_CMD_SEND_OP_COND;
382 cmd.resp_type = MMC_RSP_R3;
383 cmd.cmdarg = 0;
5a20397b
RH		 384 if (use_arg && !mmc_host_is_spi(mmc))
385 cmd.cmdarg = OCR_HCS |
93bfd616 386 (mmc->cfg->voltages &
a626c8d4
AG		 387 (mmc->ocr & OCR_VOLTAGE_MASK)) |
388 (mmc->ocr & OCR_ACCESS_MODE);
e9550449 389
5289b535 390 err = mmc_send_cmd(mmc, &cmd, NULL);
e9550449
CLC		 391 if (err)
392 return err;
5289b535 393 mmc->ocr = cmd.response[0];
e9550449
CLC		 394 return 0;
395}
396
750121c3 397static int mmc_send_op_cond(struct mmc *mmc)
e9550449 398{
e9550449
CLC		 399 int err, i;
400
272cc70b
AF		 401 /* Some cards seem to need this */
402 mmc_go_idle(mmc);
403
31cacbab 404 /* Asking to the card its capabilities */
e9550449 405 for (i = 0; i < 2; i++) {
5289b535 406 err = mmc_send_op_cond_iter(mmc, i != 0);
e9550449
CLC		 407 if (err)
408 return err;
cd6881b5 409
e9550449 410 /* exit if not busy (flag seems to be inverted) */
a626c8d4 411 if (mmc->ocr & OCR_BUSY)
bd47c135 412 break;
e9550449 413 }
bd47c135
AG		 414 mmc->op_cond_pending = 1;
415 return 0;
e9550449 416}
cd6881b5 417
750121c3 418static int mmc_complete_op_cond(struct mmc *mmc)
e9550449
CLC		 419{
420 struct mmc_cmd cmd;
421 int timeout = 1000;
422 uint start;
423 int err;
cd6881b5 424
e9550449 425 mmc->op_cond_pending = 0;
cc17c01f
AG		 426 if (!(mmc->ocr & OCR_BUSY)) {
427 start = get_timer(0);
1677eef4 428 while (1) {
cc17c01f
AG		 429 err = mmc_send_op_cond_iter(mmc, 1);
430 if (err)
431 return err;
1677eef4
AG		 432 if (mmc->ocr & OCR_BUSY)
433 break;
cc17c01f
AG		 434 if (get_timer(start) > timeout)
435 return UNUSABLE_ERR;
436 udelay(100);
1677eef4 437 }
cc17c01f 438 }
272cc70b 439
d52ebf10
TC		 440 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
441 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
442 cmd.resp_type = MMC_RSP_R3;
443 cmd.cmdarg = 0;
d52ebf10
TC		 444
445 err = mmc_send_cmd(mmc, &cmd, NULL);
446
447 if (err)
448 return err;
a626c8d4
AG		 449
450 mmc->ocr = cmd.response[0];
d52ebf10
TC		 451 }
452
272cc70b 453 mmc->version = MMC_VERSION_UNKNOWN;
272cc70b
AF		 454
455 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
def816a2 456 mmc->rca = 1;
272cc70b
AF		 457
458 return 0;
459}
460
461
fdbb873e 462static int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd)
272cc70b
AF		 463{
464 struct mmc_cmd cmd;
465 struct mmc_data data;
466 int err;
467
468 /* Get the Card Status Register */
469 cmd.cmdidx = MMC_CMD_SEND_EXT_CSD;
470 cmd.resp_type = MMC_RSP_R1;
471 cmd.cmdarg = 0;
272cc70b 472
cdfd1ac6 473 data.dest = (char *)ext_csd;
272cc70b 474 data.blocks = 1;
8bfa195e 475 data.blocksize = MMC_MAX_BLOCK_LEN;
272cc70b
AF		 476 data.flags = MMC_DATA_READ;
477
478 err = mmc_send_cmd(mmc, &cmd, &data);
479
480 return err;
481}
482
483
fdbb873e 484static int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value)
272cc70b
AF		 485{
486 struct mmc_cmd cmd;
5d4fc8d9
RR		 487 int timeout = 1000;
488 int ret;
272cc70b
AF		 489
490 cmd.cmdidx = MMC_CMD_SWITCH;
491 cmd.resp_type = MMC_RSP_R1b;
492 cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) |
5d4fc8d9
RR		 493 (index << 16) |
494 (value << 8);
272cc70b 495
5d4fc8d9
RR		 496 ret = mmc_send_cmd(mmc, &cmd, NULL);
497
498 /* Waiting for the ready status */
93ad0d18
JK		 499 if (!ret)
500 ret = mmc_send_status(mmc, timeout);
5d4fc8d9
RR		 501
502 return ret;
503
272cc70b
AF		 504}
505
fdbb873e 506static int mmc_change_freq(struct mmc *mmc)
272cc70b 507{
8bfa195e 508 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
272cc70b
AF		 509 char cardtype;
510 int err;
511
fc5b32fb 512 mmc->card_caps = 0;
272cc70b 513
d52ebf10
TC		 514 if (mmc_host_is_spi(mmc))
515 return 0;
516
272cc70b
AF		 517 /* Only version 4 supports high-speed */
518 if (mmc->version < MMC_VERSION_4)
519 return 0;
520
fc5b32fb
AG		 521 mmc->card_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT;
522
272cc70b
AF		 523 err = mmc_send_ext_csd(mmc, ext_csd);
524
525 if (err)
526 return err;
527
0560db18 528 cardtype = ext_csd[EXT_CSD_CARD_TYPE] & 0xf;
272cc70b
AF		 529
530 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING, 1);
531
532 if (err)
6b2221b0 533 return err == SWITCH_ERR ? 0 : err;
272cc70b
AF		 534
535 /* Now check to see that it worked */
536 err = mmc_send_ext_csd(mmc, ext_csd);
537
538 if (err)
539 return err;
540
541 /* No high-speed support */
0560db18 542 if (!ext_csd[EXT_CSD_HS_TIMING])
272cc70b
AF		 543 return 0;
544
545 /* High Speed is set, there are two types: 52MHz and 26MHz */
d22e3d46 546 if (cardtype & EXT_CSD_CARD_TYPE_52) {
201d5ac4 547 if (cardtype & EXT_CSD_CARD_TYPE_DDR_1_8V)
d22e3d46 548 mmc->card_caps |= MMC_MODE_DDR_52MHz;
272cc70b 549 mmc->card_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
d22e3d46 550 } else {
272cc70b 551 mmc->card_caps |= MMC_MODE_HS;
d22e3d46 552 }
272cc70b
AF		 553
554 return 0;
555}
556
f866a46d
SW		 557static int mmc_set_capacity(struct mmc *mmc, int part_num)
558{
559 switch (part_num) {
560 case 0:
561 mmc->capacity = mmc->capacity_user;
562 break;
563 case 1:
564 case 2:
565 mmc->capacity = mmc->capacity_boot;
566 break;
567 case 3:
568 mmc->capacity = mmc->capacity_rpmb;
569 break;
570 case 4:
571 case 5:
572 case 6:
573 case 7:
574 mmc->capacity = mmc->capacity_gp[part_num - 4];
575 break;
576 default:
577 return -1;
578 }
579
580 mmc->block_dev.lba = lldiv(mmc->capacity, mmc->read_bl_len);
581
582 return 0;
583}
584
d2356284
SW		 585int mmc_select_hwpart(int dev_num, int hwpart)
586{
587 struct mmc *mmc = find_mmc_device(dev_num);
588 int ret;
589
590 if (!mmc)
d4622df3 591 return -ENODEV;
d2356284 592
873cc1d7 593 if (mmc->block_dev.hwpart == hwpart)
d2356284
SW		 594 return 0;
595
596 if (mmc->part_config == MMCPART_NOAVAILABLE) {
597 printf("Card doesn't support part_switch\n");
d4622df3 598 return -EMEDIUMTYPE;
d2356284
SW		 599 }
600
601 ret = mmc_switch_part(dev_num, hwpart);
602 if (ret)
d4622df3 603 return ret;
d2356284 604
d2356284
SW		 605 return 0;
606}
607
608
bc897b1d
LW		 609int mmc_switch_part(int dev_num, unsigned int part_num)
610{
611 struct mmc *mmc = find_mmc_device(dev_num);
f866a46d 612 int ret;
bc897b1d
LW		 613
614 if (!mmc)
615 return -1;
616
f866a46d
SW		 617 ret = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF,
618 (mmc->part_config & ~PART_ACCESS_MASK)
619 | (part_num & PART_ACCESS_MASK));
f866a46d 620
6dc93e70
PB		 621 /*
622 * Set the capacity if the switch succeeded or was intended
623 * to return to representing the raw device.
624 */
873cc1d7 625 if ((ret == 0) || ((ret == -ENODEV) && (part_num == 0))) {
6dc93e70 626 ret = mmc_set_capacity(mmc, part_num);
873cc1d7
SW		 627 mmc->block_dev.hwpart = part_num;
628 }
6dc93e70
PB		 629
630 return ret;
bc897b1d
LW		 631}
632
ac9da0e0
DSC		 633int mmc_hwpart_config(struct mmc *mmc,
634 const struct mmc_hwpart_conf *conf,
635 enum mmc_hwpart_conf_mode mode)
636{
637 u8 part_attrs = 0;
638 u32 enh_size_mult;
639 u32 enh_start_addr;
640 u32 gp_size_mult[4];
641 u32 max_enh_size_mult;
642 u32 tot_enh_size_mult = 0;
8dda5b0e 643 u8 wr_rel_set;
ac9da0e0
DSC		 644 int i, pidx, err;
645 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
646
647 if (mode < MMC_HWPART_CONF_CHECK || mode > MMC_HWPART_CONF_COMPLETE)
648 return -EINVAL;
649
650 if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4_41)) {
651 printf("eMMC >= 4.4 required for enhanced user data area\n");
652 return -EMEDIUMTYPE;
653 }
654
655 if (!(mmc->part_support & PART_SUPPORT)) {
656 printf("Card does not support partitioning\n");
657 return -EMEDIUMTYPE;
658 }
659
660 if (!mmc->hc_wp_grp_size) {
661 printf("Card does not define HC WP group size\n");
662 return -EMEDIUMTYPE;
663 }
664
665 /* check partition alignment and total enhanced size */
666 if (conf->user.enh_size) {
667 if (conf->user.enh_size % mmc->hc_wp_grp_size ||
668 conf->user.enh_start % mmc->hc_wp_grp_size) {
669 printf("User data enhanced area not HC WP group "
670 "size aligned\n");
671 return -EINVAL;
672 }
673 part_attrs |= EXT_CSD_ENH_USR;
674 enh_size_mult = conf->user.enh_size / mmc->hc_wp_grp_size;
675 if (mmc->high_capacity) {
676 enh_start_addr = conf->user.enh_start;
677 } else {
678 enh_start_addr = (conf->user.enh_start << 9);
679 }
680 } else {
681 enh_size_mult = 0;
682 enh_start_addr = 0;
683 }
684 tot_enh_size_mult += enh_size_mult;
685
686 for (pidx = 0; pidx < 4; pidx++) {
687 if (conf->gp_part[pidx].size % mmc->hc_wp_grp_size) {
688 printf("GP%i partition not HC WP group size "
689 "aligned\n", pidx+1);
690 return -EINVAL;
691 }
692 gp_size_mult[pidx] = conf->gp_part[pidx].size / mmc->hc_wp_grp_size;
693 if (conf->gp_part[pidx].size && conf->gp_part[pidx].enhanced) {
694 part_attrs |= EXT_CSD_ENH_GP(pidx);
695 tot_enh_size_mult += gp_size_mult[pidx];
696 }
697 }
698
699 if (part_attrs && ! (mmc->part_support & ENHNCD_SUPPORT)) {
700 printf("Card does not support enhanced attribute\n");
701 return -EMEDIUMTYPE;
702 }
703
704 err = mmc_send_ext_csd(mmc, ext_csd);
705 if (err)
706 return err;
707
708 max_enh_size_mult =
709 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+2] << 16) +
710 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+1] << 8) +
711 ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT];
712 if (tot_enh_size_mult > max_enh_size_mult) {
713 printf("Total enhanced size exceeds maximum (%u > %u)\n",
714 tot_enh_size_mult, max_enh_size_mult);
715 return -EMEDIUMTYPE;
716 }
717
8dda5b0e
DSC		 718 /* The default value of EXT_CSD_WR_REL_SET is device
719 * dependent, the values can only be changed if the
720 * EXT_CSD_HS_CTRL_REL bit is set. The values can be
721 * changed only once and before partitioning is completed. */
722 wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
723 if (conf->user.wr_rel_change) {
724 if (conf->user.wr_rel_set)
725 wr_rel_set |= EXT_CSD_WR_DATA_REL_USR;
726 else
727 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_USR;
728 }
729 for (pidx = 0; pidx < 4; pidx++) {
730 if (conf->gp_part[pidx].wr_rel_change) {
731 if (conf->gp_part[pidx].wr_rel_set)
732 wr_rel_set |= EXT_CSD_WR_DATA_REL_GP(pidx);
733 else
734 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_GP(pidx);
735 }
736 }
737
738 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET] &&
739 !(ext_csd[EXT_CSD_WR_REL_PARAM] & EXT_CSD_HS_CTRL_REL)) {
740 puts("Card does not support host controlled partition write "
741 "reliability settings\n");
742 return -EMEDIUMTYPE;
743 }
744
ac9da0e0
DSC		 745 if (ext_csd[EXT_CSD_PARTITION_SETTING] &
746 EXT_CSD_PARTITION_SETTING_COMPLETED) {
747 printf("Card already partitioned\n");
748 return -EPERM;
749 }
750
751 if (mode == MMC_HWPART_CONF_CHECK)
752 return 0;
753
754 /* Partitioning requires high-capacity size definitions */
755 if (!(ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01)) {
756 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
757 EXT_CSD_ERASE_GROUP_DEF, 1);
758
759 if (err)
760 return err;
761
762 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
763
764 /* update erase group size to be high-capacity */
765 mmc->erase_grp_size =
766 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
767
768 }
769
770 /* all OK, write the configuration */
771 for (i = 0; i < 4; i++) {
772 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
773 EXT_CSD_ENH_START_ADDR+i,
774 (enh_start_addr >> (i*8)) & 0xFF);
775 if (err)
776 return err;
777 }
778 for (i = 0; i < 3; i++) {
779 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
780 EXT_CSD_ENH_SIZE_MULT+i,
781 (enh_size_mult >> (i*8)) & 0xFF);
782 if (err)
783 return err;
784 }
785 for (pidx = 0; pidx < 4; pidx++) {
786 for (i = 0; i < 3; i++) {
787 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
788 EXT_CSD_GP_SIZE_MULT+pidx*3+i,
789 (gp_size_mult[pidx] >> (i*8)) & 0xFF);
790 if (err)
791 return err;
792 }
793 }
794 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
795 EXT_CSD_PARTITIONS_ATTRIBUTE, part_attrs);
796 if (err)
797 return err;
798
799 if (mode == MMC_HWPART_CONF_SET)
800 return 0;
801
8dda5b0e
DSC		 802 /* The WR_REL_SET is a write-once register but shall be
803 * written before setting PART_SETTING_COMPLETED. As it is
804 * write-once we can only write it when completing the
805 * partitioning. */
806 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET]) {
807 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
808 EXT_CSD_WR_REL_SET, wr_rel_set);
809 if (err)
810 return err;
811 }
812
ac9da0e0
DSC		 813 /* Setting PART_SETTING_COMPLETED confirms the partition
814 * configuration but it only becomes effective after power
815 * cycle, so we do not adjust the partition related settings
816 * in the mmc struct. */
817
818 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
819 EXT_CSD_PARTITION_SETTING,
820 EXT_CSD_PARTITION_SETTING_COMPLETED);
821 if (err)
822 return err;
823
824 return 0;
825}
826
48972d90
TR		 827int mmc_getcd(struct mmc *mmc)
828{
829 int cd;
830
831 cd = board_mmc_getcd(mmc);
832
d4e1da4e 833 if (cd < 0) {
93bfd616
PA		 834 if (mmc->cfg->ops->getcd)
835 cd = mmc->cfg->ops->getcd(mmc);
d4e1da4e
PK		 836 else
837 cd = 1;
838 }
48972d90
TR		 839
840 return cd;
841}
842
fdbb873e 843static int sd_switch(struct mmc *mmc, int mode, int group, u8 value, u8 *resp)
272cc70b
AF		 844{
845 struct mmc_cmd cmd;
846 struct mmc_data data;
847
848 /* Switch the frequency */
849 cmd.cmdidx = SD_CMD_SWITCH_FUNC;
850 cmd.resp_type = MMC_RSP_R1;
851 cmd.cmdarg = (mode << 31) | 0xffffff;
852 cmd.cmdarg &= ~(0xf << (group * 4));
853 cmd.cmdarg |= value << (group * 4);
272cc70b
AF		 854
855 data.dest = (char *)resp;
856 data.blocksize = 64;
857 data.blocks = 1;
858 data.flags = MMC_DATA_READ;
859
860 return mmc_send_cmd(mmc, &cmd, &data);
861}
862
863
fdbb873e 864static int sd_change_freq(struct mmc *mmc)
272cc70b
AF		 865{
866 int err;
867 struct mmc_cmd cmd;
f781dd38
A		 868 ALLOC_CACHE_ALIGN_BUFFER(uint, scr, 2);
869 ALLOC_CACHE_ALIGN_BUFFER(uint, switch_status, 16);
272cc70b
AF		 870 struct mmc_data data;
871 int timeout;
872
873 mmc->card_caps = 0;
874
d52ebf10
TC		 875 if (mmc_host_is_spi(mmc))
876 return 0;
877
272cc70b
AF		 878 /* Read the SCR to find out if this card supports higher speeds */
879 cmd.cmdidx = MMC_CMD_APP_CMD;
880 cmd.resp_type = MMC_RSP_R1;
881 cmd.cmdarg = mmc->rca << 16;
272cc70b
AF		 882
883 err = mmc_send_cmd(mmc, &cmd, NULL);
884
885 if (err)
886 return err;
887
888 cmd.cmdidx = SD_CMD_APP_SEND_SCR;
889 cmd.resp_type = MMC_RSP_R1;
890 cmd.cmdarg = 0;
272cc70b
AF		 891
892 timeout = 3;
893
894retry_scr:
f781dd38 895 data.dest = (char *)scr;
272cc70b
AF		 896 data.blocksize = 8;
897 data.blocks = 1;
898 data.flags = MMC_DATA_READ;
899
900 err = mmc_send_cmd(mmc, &cmd, &data);
901
902 if (err) {
903 if (timeout--)
904 goto retry_scr;
905
906 return err;
907 }
908
4e3d89ba
YK		 909 mmc->scr[0] = __be32_to_cpu(scr[0]);
910 mmc->scr[1] = __be32_to_cpu(scr[1]);
272cc70b
AF		 911
912 switch ((mmc->scr[0] >> 24) & 0xf) {
53e8e40b
BM		 913 case 0:
914 mmc->version = SD_VERSION_1_0;
915 break;
916 case 1:
917 mmc->version = SD_VERSION_1_10;
918 break;
919 case 2:
920 mmc->version = SD_VERSION_2;
921 if ((mmc->scr[0] >> 15) & 0x1)
922 mmc->version = SD_VERSION_3;
923 break;
924 default:
925 mmc->version = SD_VERSION_1_0;
926 break;
272cc70b
AF		 927 }
928
b44c7083
AS		 929 if (mmc->scr[0] & SD_DATA_4BIT)
930 mmc->card_caps |= MMC_MODE_4BIT;
931
272cc70b
AF		 932 /* Version 1.0 doesn't support switching */
933 if (mmc->version == SD_VERSION_1_0)
934 return 0;
935
936 timeout = 4;
937 while (timeout--) {
938 err = sd_switch(mmc, SD_SWITCH_CHECK, 0, 1,
f781dd38 939 (u8 *)switch_status);
272cc70b
AF		 940
941 if (err)
942 return err;
943
944 /* The high-speed function is busy. Try again */
4e3d89ba 945 if (!(__be32_to_cpu(switch_status[7]) & SD_HIGHSPEED_BUSY))
272cc70b
AF		 946 break;
947 }
948
272cc70b 949 /* If high-speed isn't supported, we return */
4e3d89ba 950 if (!(__be32_to_cpu(switch_status[3]) & SD_HIGHSPEED_SUPPORTED))
272cc70b
AF		 951 return 0;
952
2c3fbf4c
ML		 953 /*
954 * If the host doesn't support SD_HIGHSPEED, do not switch card to
955 * HIGHSPEED mode even if the card support SD_HIGHSPPED.
956 * This can avoid furthur problem when the card runs in different
957 * mode between the host.
958 */
93bfd616
PA		 959 if (!((mmc->cfg->host_caps & MMC_MODE_HS_52MHz) &&
960 (mmc->cfg->host_caps & MMC_MODE_HS)))
2c3fbf4c
ML		 961 return 0;
962
f781dd38 963 err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, 1, (u8 *)switch_status);
272cc70b
AF		 964
965 if (err)
966 return err;
967
4e3d89ba 968 if ((__be32_to_cpu(switch_status[4]) & 0x0f000000) == 0x01000000)
272cc70b
AF		 969 mmc->card_caps |= MMC_MODE_HS;
970
971 return 0;
972}
973
974/* frequency bases */
975/* divided by 10 to be nice to platforms without floating point */
5f837c2c 976static const int fbase[] = {
272cc70b
AF		 977 10000,
978 100000,
979 1000000,
980 10000000,
981};
982
983/* Multiplier values for TRAN_SPEED. Multiplied by 10 to be nice
984 * to platforms without floating point.
985 */
5f837c2c 986static const int multipliers[] = {
272cc70b
AF		 987 0, /* reserved */
988 10,
989 12,
990 13,
991 15,
992 20,
993 25,
994 30,
995 35,
996 40,
997 45,
998 50,
999 55,
1000 60,
1001 70,
1002 80,
1003};
1004
fdbb873e 1005static void mmc_set_ios(struct mmc *mmc)
272cc70b 1006{
93bfd616
PA		 1007 if (mmc->cfg->ops->set_ios)
1008 mmc->cfg->ops->set_ios(mmc);
272cc70b
AF		 1009}
1010
1011void mmc_set_clock(struct mmc *mmc, uint clock)
1012{
93bfd616
PA		 1013 if (clock > mmc->cfg->f_max)
1014 clock = mmc->cfg->f_max;
272cc70b 1015
93bfd616
PA		 1016 if (clock < mmc->cfg->f_min)
1017 clock = mmc->cfg->f_min;
272cc70b
AF		 1018
1019 mmc->clock = clock;
1020
1021 mmc_set_ios(mmc);
1022}
1023
fdbb873e 1024static void mmc_set_bus_width(struct mmc *mmc, uint width)
272cc70b
AF		 1025{
1026 mmc->bus_width = width;
1027
1028 mmc_set_ios(mmc);
1029}
1030
fdbb873e 1031static int mmc_startup(struct mmc *mmc)
272cc70b 1032{
f866a46d 1033 int err, i;
272cc70b 1034 uint mult, freq;
639b7827 1035 u64 cmult, csize, capacity;
272cc70b 1036 struct mmc_cmd cmd;
8bfa195e
SG		 1037 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
1038 ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
5d4fc8d9 1039 int timeout = 1000;
0c453bb7 1040 bool has_parts = false;
8a0cf490 1041 bool part_completed;
272cc70b 1042
d52ebf10
TC		 1043#ifdef CONFIG_MMC_SPI_CRC_ON
1044 if (mmc_host_is_spi(mmc)) { /* enable CRC check for spi */
1045 cmd.cmdidx = MMC_CMD_SPI_CRC_ON_OFF;
1046 cmd.resp_type = MMC_RSP_R1;
1047 cmd.cmdarg = 1;
d52ebf10
TC		 1048 err = mmc_send_cmd(mmc, &cmd, NULL);
1049
1050 if (err)
1051 return err;
1052 }
1053#endif
1054
272cc70b 1055 /* Put the Card in Identify Mode */
d52ebf10
TC		 1056 cmd.cmdidx = mmc_host_is_spi(mmc) ? MMC_CMD_SEND_CID :
1057 MMC_CMD_ALL_SEND_CID; /* cmd not supported in spi */
272cc70b
AF		 1058 cmd.resp_type = MMC_RSP_R2;
1059 cmd.cmdarg = 0;
272cc70b
AF		 1060
1061 err = mmc_send_cmd(mmc, &cmd, NULL);
1062
1063 if (err)
1064 return err;
1065
1066 memcpy(mmc->cid, cmd.response, 16);
1067
1068 /*
1069 * For MMC cards, set the Relative Address.
1070 * For SD cards, get the Relatvie Address.
1071 * This also puts the cards into Standby State
1072 */
d52ebf10
TC		 1073 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
1074 cmd.cmdidx = SD_CMD_SEND_RELATIVE_ADDR;
1075 cmd.cmdarg = mmc->rca << 16;
1076 cmd.resp_type = MMC_RSP_R6;
272cc70b 1077
d52ebf10 1078 err = mmc_send_cmd(mmc, &cmd, NULL);
272cc70b 1079
d52ebf10
TC		 1080 if (err)
1081 return err;
272cc70b 1082
d52ebf10
TC		 1083 if (IS_SD(mmc))
1084 mmc->rca = (cmd.response[0] >> 16) & 0xffff;
1085 }
272cc70b
AF		 1086
1087 /* Get the Card-Specific Data */
1088 cmd.cmdidx = MMC_CMD_SEND_CSD;
1089 cmd.resp_type = MMC_RSP_R2;
1090 cmd.cmdarg = mmc->rca << 16;
272cc70b
AF		 1091
1092 err = mmc_send_cmd(mmc, &cmd, NULL);
1093
5d4fc8d9
RR		 1094 /* Waiting for the ready status */
1095 mmc_send_status(mmc, timeout);
1096
272cc70b
AF		 1097 if (err)
1098 return err;
1099
998be3dd
RV		 1100 mmc->csd[0] = cmd.response[0];
1101 mmc->csd[1] = cmd.response[1];
1102 mmc->csd[2] = cmd.response[2];
1103 mmc->csd[3] = cmd.response[3];
272cc70b
AF		 1104
1105 if (mmc->version == MMC_VERSION_UNKNOWN) {
0b453ffe 1106 int version = (cmd.response[0] >> 26) & 0xf;
272cc70b
AF		 1107
1108 switch (version) {
53e8e40b
BM		 1109 case 0:
1110 mmc->version = MMC_VERSION_1_2;
1111 break;
1112 case 1:
1113 mmc->version = MMC_VERSION_1_4;
1114 break;
1115 case 2:
1116 mmc->version = MMC_VERSION_2_2;
1117 break;
1118 case 3:
1119 mmc->version = MMC_VERSION_3;
1120 break;
1121 case 4:
1122 mmc->version = MMC_VERSION_4;
1123 break;
1124 default:
1125 mmc->version = MMC_VERSION_1_2;
1126 break;
272cc70b
AF		 1127 }
1128 }
1129
1130 /* divide frequency by 10, since the mults are 10x bigger */
0b453ffe
RV		 1131 freq = fbase[(cmd.response[0] & 0x7)];
1132 mult = multipliers[((cmd.response[0] >> 3) & 0xf)];
272cc70b
AF		 1133
1134 mmc->tran_speed = freq * mult;
1135
ab71188c 1136 mmc->dsr_imp = ((cmd.response[1] >> 12) & 0x1);
998be3dd 1137 mmc->read_bl_len = 1 << ((cmd.response[1] >> 16) & 0xf);
272cc70b
AF		 1138
1139 if (IS_SD(mmc))
1140 mmc->write_bl_len = mmc->read_bl_len;
1141 else
998be3dd 1142 mmc->write_bl_len = 1 << ((cmd.response[3] >> 22) & 0xf);
272cc70b
AF		 1143
1144 if (mmc->high_capacity) {
1145 csize = (mmc->csd[1] & 0x3f) << 16
1146 | (mmc->csd[2] & 0xffff0000) >> 16;
1147 cmult = 8;
1148 } else {
1149 csize = (mmc->csd[1] & 0x3ff) << 2
1150 | (mmc->csd[2] & 0xc0000000) >> 30;
1151 cmult = (mmc->csd[2] & 0x00038000) >> 15;
1152 }
1153
f866a46d
SW		 1154 mmc->capacity_user = (csize + 1) << (cmult + 2);
1155 mmc->capacity_user *= mmc->read_bl_len;
1156 mmc->capacity_boot = 0;
1157 mmc->capacity_rpmb = 0;
1158 for (i = 0; i < 4; i++)
1159 mmc->capacity_gp[i] = 0;
272cc70b 1160
8bfa195e
SG		 1161 if (mmc->read_bl_len > MMC_MAX_BLOCK_LEN)
1162 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
272cc70b 1163
8bfa195e
SG		 1164 if (mmc->write_bl_len > MMC_MAX_BLOCK_LEN)
1165 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
272cc70b 1166
ab71188c
MN		 1167 if ((mmc->dsr_imp) && (0xffffffff != mmc->dsr)) {
1168 cmd.cmdidx = MMC_CMD_SET_DSR;
1169 cmd.cmdarg = (mmc->dsr & 0xffff) << 16;
1170 cmd.resp_type = MMC_RSP_NONE;
1171 if (mmc_send_cmd(mmc, &cmd, NULL))
1172 printf("MMC: SET_DSR failed\n");
1173 }
1174
272cc70b 1175 /* Select the card, and put it into Transfer Mode */
d52ebf10
TC		 1176 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
1177 cmd.cmdidx = MMC_CMD_SELECT_CARD;
fe8f7066 1178 cmd.resp_type = MMC_RSP_R1;
d52ebf10 1179 cmd.cmdarg = mmc->rca << 16;
d52ebf10 1180 err = mmc_send_cmd(mmc, &cmd, NULL);
272cc70b 1181
d52ebf10
TC		 1182 if (err)
1183 return err;
1184 }
272cc70b 1185
e6f99a56
LW		 1186 /*
1187 * For SD, its erase group is always one sector
1188 */
1189 mmc->erase_grp_size = 1;
bc897b1d 1190 mmc->part_config = MMCPART_NOAVAILABLE;
d23e2c09
SG		 1191 if (!IS_SD(mmc) && (mmc->version >= MMC_VERSION_4)) {
1192 /* check ext_csd version and capacity */
1193 err = mmc_send_ext_csd(mmc, ext_csd);
9cf199eb
DSC		 1194 if (err)
1195 return err;
1196 if (ext_csd[EXT_CSD_REV] >= 2) {
639b7827
YS		 1197 /*
1198 * According to the JEDEC Standard, the value of
1199 * ext_csd's capacity is valid if the value is more
1200 * than 2GB
1201 */
0560db18
LW		 1202 capacity = ext_csd[EXT_CSD_SEC_CNT] << 0
1203 | ext_csd[EXT_CSD_SEC_CNT + 1] << 8
1204 | ext_csd[EXT_CSD_SEC_CNT + 2] << 16
1205 | ext_csd[EXT_CSD_SEC_CNT + 3] << 24;
8bfa195e 1206 capacity *= MMC_MAX_BLOCK_LEN;
b1f1e821 1207 if ((capacity >> 20) > 2 * 1024)
f866a46d 1208 mmc->capacity_user = capacity;
d23e2c09 1209 }
bc897b1d 1210
64f4a619
JC		 1211 switch (ext_csd[EXT_CSD_REV]) {
1212 case 1:
1213 mmc->version = MMC_VERSION_4_1;
1214 break;
1215 case 2:
1216 mmc->version = MMC_VERSION_4_2;
1217 break;
1218 case 3:
1219 mmc->version = MMC_VERSION_4_3;
1220 break;
1221 case 5:
1222 mmc->version = MMC_VERSION_4_41;
1223 break;
1224 case 6:
1225 mmc->version = MMC_VERSION_4_5;
1226 break;
edab723b
MN		 1227 case 7:
1228 mmc->version = MMC_VERSION_5_0;
1229 break;
64f4a619
JC		 1230 }
1231
8a0cf490
DSC		 1232 /* The partition data may be non-zero but it is only
1233 * effective if PARTITION_SETTING_COMPLETED is set in
1234 * EXT_CSD, so ignore any data if this bit is not set,
1235 * except for enabling the high-capacity group size
1236 * definition (see below). */
1237 part_completed = !!(ext_csd[EXT_CSD_PARTITION_SETTING] &
1238 EXT_CSD_PARTITION_SETTING_COMPLETED);
1239
0c453bb7
DSC		 1240 /* store the partition info of emmc */
1241 mmc->part_support = ext_csd[EXT_CSD_PARTITIONING_SUPPORT];
1242 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) ||
1243 ext_csd[EXT_CSD_BOOT_MULT])
1244 mmc->part_config = ext_csd[EXT_CSD_PART_CONF];
8a0cf490
DSC		 1245 if (part_completed &&
1246 (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & ENHNCD_SUPPORT))
0c453bb7
DSC		 1247 mmc->part_attr = ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE];
1248
1249 mmc->capacity_boot = ext_csd[EXT_CSD_BOOT_MULT] << 17;
1250
1251 mmc->capacity_rpmb = ext_csd[EXT_CSD_RPMB_MULT] << 17;
1252
1253 for (i = 0; i < 4; i++) {
1254 int idx = EXT_CSD_GP_SIZE_MULT + i * 3;
8a0cf490 1255 uint mult = (ext_csd[idx + 2] << 16) +
0c453bb7 1256 (ext_csd[idx + 1] << 8) + ext_csd[idx];
8a0cf490
DSC		 1257 if (mult)
1258 has_parts = true;
1259 if (!part_completed)
1260 continue;
1261 mmc->capacity_gp[i] = mult;
0c453bb7
DSC		 1262 mmc->capacity_gp[i] *=
1263 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
1264 mmc->capacity_gp[i] *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
f8e89d67 1265 mmc->capacity_gp[i] <<= 19;
0c453bb7
DSC		 1266 }
1267
8a0cf490
DSC		 1268 if (part_completed) {
1269 mmc->enh_user_size =
1270 (ext_csd[EXT_CSD_ENH_SIZE_MULT+2] << 16) +
1271 (ext_csd[EXT_CSD_ENH_SIZE_MULT+1] << 8) +
1272 ext_csd[EXT_CSD_ENH_SIZE_MULT];
1273 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
1274 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
1275 mmc->enh_user_size <<= 19;
1276 mmc->enh_user_start =
1277 (ext_csd[EXT_CSD_ENH_START_ADDR+3] << 24) +
1278 (ext_csd[EXT_CSD_ENH_START_ADDR+2] << 16) +
1279 (ext_csd[EXT_CSD_ENH_START_ADDR+1] << 8) +
1280 ext_csd[EXT_CSD_ENH_START_ADDR];
1281 if (mmc->high_capacity)
1282 mmc->enh_user_start <<= 9;
1283 }
a7f852b6 1284
e6f99a56 1285 /*
1937e5aa
OM		 1286 * Host needs to enable ERASE_GRP_DEF bit if device is
1287 * partitioned. This bit will be lost every time after a reset
1288 * or power off. This will affect erase size.
e6f99a56 1289 */
8a0cf490 1290 if (part_completed)
0c453bb7 1291 has_parts = true;
1937e5aa 1292 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) &&
0c453bb7
DSC		 1293 (ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE] & PART_ENH_ATTRIB))
1294 has_parts = true;
1295 if (has_parts) {
1937e5aa
OM		 1296 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1297 EXT_CSD_ERASE_GROUP_DEF, 1);
1298
1299 if (err)
1300 return err;
021a8055
HP		 1301 else
1302 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
037dc0ab 1303 }
1937e5aa 1304
037dc0ab 1305 if (ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01) {
1937e5aa 1306 /* Read out group size from ext_csd */
0560db18 1307 mmc->erase_grp_size =
a4ff9f83 1308 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
d7b29129
MN		 1309 /*
1310 * if high capacity and partition setting completed
1311 * SEC_COUNT is valid even if it is smaller than 2 GiB
1312 * JEDEC Standard JESD84-B45, 6.2.4
1313 */
8a0cf490 1314 if (mmc->high_capacity && part_completed) {
d7b29129
MN		 1315 capacity = (ext_csd[EXT_CSD_SEC_CNT]) |
1316 (ext_csd[EXT_CSD_SEC_CNT + 1] << 8) |
1317 (ext_csd[EXT_CSD_SEC_CNT + 2] << 16) |
1318 (ext_csd[EXT_CSD_SEC_CNT + 3] << 24);
1319 capacity *= MMC_MAX_BLOCK_LEN;
1320 mmc->capacity_user = capacity;
1321 }
8bfa195e 1322 } else {
1937e5aa 1323 /* Calculate the group size from the csd value. */
e6f99a56
LW		 1324 int erase_gsz, erase_gmul;
1325 erase_gsz = (mmc->csd[2] & 0x00007c00) >> 10;
1326 erase_gmul = (mmc->csd[2] & 0x000003e0) >> 5;
1327 mmc->erase_grp_size = (erase_gsz + 1)
1328 * (erase_gmul + 1);
1329 }
037dc0ab
DSC		 1330
1331 mmc->hc_wp_grp_size = 1024
1332 * ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
1333 * ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
9e41a00b
DSC		 1334
1335 mmc->wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
d23e2c09
SG		 1336 }
1337
873cc1d7 1338 err = mmc_set_capacity(mmc, mmc->block_dev.hwpart);
f866a46d
SW		 1339 if (err)
1340 return err;
1341
272cc70b
AF		 1342 if (IS_SD(mmc))
1343 err = sd_change_freq(mmc);
1344 else
1345 err = mmc_change_freq(mmc);
1346
1347 if (err)
1348 return err;
1349
1350 /* Restrict card's capabilities by what the host can do */
93bfd616 1351 mmc->card_caps &= mmc->cfg->host_caps;
272cc70b
AF		 1352
1353 if (IS_SD(mmc)) {
1354 if (mmc->card_caps & MMC_MODE_4BIT) {
1355 cmd.cmdidx = MMC_CMD_APP_CMD;
1356 cmd.resp_type = MMC_RSP_R1;
1357 cmd.cmdarg = mmc->rca << 16;
272cc70b
AF		 1358
1359 err = mmc_send_cmd(mmc, &cmd, NULL);
1360 if (err)
1361 return err;
1362
1363 cmd.cmdidx = SD_CMD_APP_SET_BUS_WIDTH;
1364 cmd.resp_type = MMC_RSP_R1;
1365 cmd.cmdarg = 2;
272cc70b
AF		 1366 err = mmc_send_cmd(mmc, &cmd, NULL);
1367 if (err)
1368 return err;
1369
1370 mmc_set_bus_width(mmc, 4);
1371 }
1372
1373 if (mmc->card_caps & MMC_MODE_HS)
ad5fd922 1374 mmc->tran_speed = 50000000;
272cc70b 1375 else
ad5fd922 1376 mmc->tran_speed = 25000000;
fc5b32fb
AG		 1377 } else if (mmc->version >= MMC_VERSION_4) {
1378 /* Only version 4 of MMC supports wider bus widths */
7798f6db
AF		 1379 int idx;
1380
1381 /* An array of possible bus widths in order of preference */
1382 static unsigned ext_csd_bits[] = {
d22e3d46
JC		 1383 EXT_CSD_DDR_BUS_WIDTH_8,
1384 EXT_CSD_DDR_BUS_WIDTH_4,
7798f6db
AF		 1385 EXT_CSD_BUS_WIDTH_8,
1386 EXT_CSD_BUS_WIDTH_4,
1387 EXT_CSD_BUS_WIDTH_1,
1388 };
1389
1390 /* An array to map CSD bus widths to host cap bits */
1391 static unsigned ext_to_hostcaps[] = {
786e8f81
AG		 1392 [EXT_CSD_DDR_BUS_WIDTH_4] =
1393 MMC_MODE_DDR_52MHz | MMC_MODE_4BIT,
1394 [EXT_CSD_DDR_BUS_WIDTH_8] =
1395 MMC_MODE_DDR_52MHz | MMC_MODE_8BIT,
7798f6db
AF		 1396 [EXT_CSD_BUS_WIDTH_4] = MMC_MODE_4BIT,
1397 [EXT_CSD_BUS_WIDTH_8] = MMC_MODE_8BIT,
1398 };
1399
1400 /* An array to map chosen bus width to an integer */
1401 static unsigned widths[] = {
d22e3d46 1402 8, 4, 8, 4, 1,
7798f6db
AF		 1403 };
1404
1405 for (idx=0; idx < ARRAY_SIZE(ext_csd_bits); idx++) {
1406 unsigned int extw = ext_csd_bits[idx];
786e8f81 1407 unsigned int caps = ext_to_hostcaps[extw];
7798f6db 1408
bf477073
AG		 1409 /*
1410 * If the bus width is still not changed,
1411 * don't try to set the default again.
1412 * Otherwise, recover from switch attempts
1413 * by switching to 1-bit bus width.
1414 */
1415 if (extw == EXT_CSD_BUS_WIDTH_1 &&
1416 mmc->bus_width == 1) {
1417 err = 0;
1418 break;
1419 }
1420
7798f6db 1421 /*
786e8f81
AG		 1422 * Check to make sure the card and controller support
1423 * these capabilities
7798f6db 1424 */
786e8f81 1425 if ((mmc->card_caps & caps) != caps)
7798f6db
AF		 1426 continue;
1427
272cc70b 1428 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
7798f6db 1429 EXT_CSD_BUS_WIDTH, extw);
272cc70b
AF		 1430
1431 if (err)
4137894e 1432 continue;
272cc70b 1433
786e8f81 1434 mmc->ddr_mode = (caps & MMC_MODE_DDR_52MHz) ? 1 : 0;
7798f6db 1435 mmc_set_bus_width(mmc, widths[idx]);
4137894e
LW		 1436
1437 err = mmc_send_ext_csd(mmc, test_csd);
786e8f81
AG		 1438
1439 if (err)
1440 continue;
1441
786a27b7 1442 /* Only compare read only fields */
786e8f81
AG		 1443 if (ext_csd[EXT_CSD_PARTITIONING_SUPPORT]
1444 == test_csd[EXT_CSD_PARTITIONING_SUPPORT] &&
1445 ext_csd[EXT_CSD_HC_WP_GRP_SIZE]
1446 == test_csd[EXT_CSD_HC_WP_GRP_SIZE] &&
1447 ext_csd[EXT_CSD_REV]
1448 == test_csd[EXT_CSD_REV] &&
1449 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
1450 == test_csd[EXT_CSD_HC_ERASE_GRP_SIZE] &&
1451 memcmp(&ext_csd[EXT_CSD_SEC_CNT],
1452 &test_csd[EXT_CSD_SEC_CNT], 4) == 0)
4137894e 1453 break;
786e8f81
AG		 1454 else
1455 err = SWITCH_ERR;
272cc70b
AF		 1456 }
1457
786e8f81
AG		 1458 if (err)
1459 return err;
1460
272cc70b
AF		 1461 if (mmc->card_caps & MMC_MODE_HS) {
1462 if (mmc->card_caps & MMC_MODE_HS_52MHz)
ad5fd922 1463 mmc->tran_speed = 52000000;
272cc70b 1464 else
ad5fd922
JC		 1465 mmc->tran_speed = 26000000;
1466 }
272cc70b
AF		 1467 }
1468
ad5fd922
JC		 1469 mmc_set_clock(mmc, mmc->tran_speed);
1470
5af8f45c
AG		 1471 /* Fix the block length for DDR mode */
1472 if (mmc->ddr_mode) {
1473 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
1474 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
1475 }
1476
272cc70b
AF		 1477 /* fill in device description */
1478 mmc->block_dev.lun = 0;
873cc1d7 1479 mmc->block_dev.hwpart = 0;
272cc70b
AF		 1480 mmc->block_dev.type = 0;
1481 mmc->block_dev.blksz = mmc->read_bl_len;
0472fbfd 1482 mmc->block_dev.log2blksz = LOG2(mmc->block_dev.blksz);
9b1f942c 1483 mmc->block_dev.lba = lldiv(mmc->capacity, mmc->read_bl_len);
fc011f64
SS		 1484#if !defined(CONFIG_SPL_BUILD) || \
1485 (defined(CONFIG_SPL_LIBCOMMON_SUPPORT) && \
1486 !defined(CONFIG_USE_TINY_PRINTF))
babce5f6
TH		 1487 sprintf(mmc->block_dev.vendor, "Man %06x Snr %04x%04x",
1488 mmc->cid[0] >> 24, (mmc->cid[2] & 0xffff),
1489 (mmc->cid[3] >> 16) & 0xffff);
1490 sprintf(mmc->block_dev.product, "%c%c%c%c%c%c", mmc->cid[0] & 0xff,
1491 (mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff,
1492 (mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff,
1493 (mmc->cid[2] >> 24) & 0xff);
1494 sprintf(mmc->block_dev.revision, "%d.%d", (mmc->cid[2] >> 20) & 0xf,
1495 (mmc->cid[2] >> 16) & 0xf);
56196826
PB		 1496#else
1497 mmc->block_dev.vendor[0] = 0;
1498 mmc->block_dev.product[0] = 0;
1499 mmc->block_dev.revision[0] = 0;
1500#endif
122efd43 1501#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBDISK_SUPPORT)
3e8bd469 1502 part_init(&mmc->block_dev);
122efd43 1503#endif
272cc70b
AF		 1504
1505 return 0;
1506}
1507
fdbb873e 1508static int mmc_send_if_cond(struct mmc *mmc)
272cc70b
AF		 1509{
1510 struct mmc_cmd cmd;
1511 int err;
1512
1513 cmd.cmdidx = SD_CMD_SEND_IF_COND;
1514 /* We set the bit if the host supports voltages between 2.7 and 3.6 V */
93bfd616 1515 cmd.cmdarg = ((mmc->cfg->voltages & 0xff8000) != 0) << 8 | 0xaa;
272cc70b 1516 cmd.resp_type = MMC_RSP_R7;
272cc70b
AF		 1517
1518 err = mmc_send_cmd(mmc, &cmd, NULL);
1519
1520 if (err)
1521 return err;
1522
998be3dd 1523 if ((cmd.response[0] & 0xff) != 0xaa)
272cc70b
AF		 1524 return UNUSABLE_ERR;
1525 else
1526 mmc->version = SD_VERSION_2;
1527
1528 return 0;
1529}
1530
93bfd616
PA		 1531/* not used any more */
1532int __deprecated mmc_register(struct mmc *mmc)
1533{
1534#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
1535 printf("%s is deprecated! use mmc_create() instead.\n", __func__);
1536#endif
1537 return -1;
1538}
1539
1540struct mmc *mmc_create(const struct mmc_config *cfg, void *priv)
272cc70b 1541{
93bfd616
PA		 1542 struct mmc *mmc;
1543
1544 /* quick validation */
1545 if (cfg == NULL || cfg->ops == NULL || cfg->ops->send_cmd == NULL ||
1546 cfg->f_min == 0 || cfg->f_max == 0 || cfg->b_max == 0)
1547 return NULL;
1548
1549 mmc = calloc(1, sizeof(*mmc));
1550 if (mmc == NULL)
1551 return NULL;
1552
1553 mmc->cfg = cfg;
1554 mmc->priv = priv;
1555
1556 /* the following chunk was mmc_register() */
1557
ab71188c
MN		 1558 /* Setup dsr related values */
1559 mmc->dsr_imp = 0;
1560 mmc->dsr = 0xffffffff;
272cc70b
AF		 1561 /* Setup the universal parts of the block interface just once */
1562 mmc->block_dev.if_type = IF_TYPE_MMC;
bcce53d0 1563 mmc->block_dev.devnum = cur_dev_num++;
272cc70b
AF		 1564 mmc->block_dev.removable = 1;
1565 mmc->block_dev.block_read = mmc_bread;
1566 mmc->block_dev.block_write = mmc_bwrite;
e6f99a56 1567 mmc->block_dev.block_erase = mmc_berase;
272cc70b 1568
93bfd616
PA		 1569 /* setup initial part type */
1570 mmc->block_dev.part_type = mmc->cfg->part_type;
272cc70b 1571
93bfd616 1572 INIT_LIST_HEAD(&mmc->link);
272cc70b 1573
93bfd616
PA		 1574 list_add_tail(&mmc->link, &mmc_devices);
1575
1576 return mmc;
1577}
1578
1579void mmc_destroy(struct mmc *mmc)
1580{
1581 /* only freeing memory for now */
1582 free(mmc);
272cc70b
AF		 1583}
1584
df3fc526 1585#ifdef CONFIG_PARTITIONS
4101f687 1586struct blk_desc *mmc_get_dev(int dev)
272cc70b
AF		 1587{
1588 struct mmc *mmc = find_mmc_device(dev);
6bb4b4bc 1589 if (!mmc || mmc_init(mmc))
40242bc3 1590 return NULL;
272cc70b 1591
40242bc3 1592 return &mmc->block_dev;
272cc70b 1593}
df3fc526 1594#endif
272cc70b 1595
95de9ab2
PK		 1596/* board-specific MMC power initializations. */
1597__weak void board_mmc_power_init(void)
1598{
1599}
1600
e9550449 1601int mmc_start_init(struct mmc *mmc)
272cc70b 1602{
afd5932b 1603 int err;
272cc70b 1604
ab769f22 1605 /* we pretend there's no card when init is NULL */
93bfd616 1606 if (mmc_getcd(mmc) == 0 || mmc->cfg->ops->init == NULL) {
48972d90 1607 mmc->has_init = 0;
56196826 1608#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
48972d90 1609 printf("MMC: no card present\n");
56196826 1610#endif
48972d90
TR		 1611 return NO_CARD_ERR;
1612 }
1613
bc897b1d
LW		 1614 if (mmc->has_init)
1615 return 0;
1616
5a8dbdc6
YL		 1617#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
1618 mmc_adapter_card_type_ident();
1619#endif
95de9ab2
PK		 1620 board_mmc_power_init();
1621
ab769f22 1622 /* made sure it's not NULL earlier */
93bfd616 1623 err = mmc->cfg->ops->init(mmc);
272cc70b
AF		 1624
1625 if (err)
1626 return err;
1627
786e8f81 1628 mmc->ddr_mode = 0;
b86b85e2
IY		 1629 mmc_set_bus_width(mmc, 1);
1630 mmc_set_clock(mmc, 1);
1631
272cc70b
AF		 1632 /* Reset the Card */
1633 err = mmc_go_idle(mmc);
1634
1635 if (err)
1636 return err;
1637
bc897b1d 1638 /* The internal partition reset to user partition(0) at every CMD0*/
873cc1d7 1639 mmc->block_dev.hwpart = 0;
bc897b1d 1640
272cc70b 1641 /* Test for SD version 2 */
afd5932b 1642 err = mmc_send_if_cond(mmc);
272cc70b 1643
272cc70b
AF		 1644 /* Now try to get the SD card's operating condition */
1645 err = sd_send_op_cond(mmc);
1646
1647 /* If the command timed out, we check for an MMC card */
1648 if (err == TIMEOUT) {
1649 err = mmc_send_op_cond(mmc);
1650
bd47c135 1651 if (err) {
56196826 1652#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
272cc70b 1653 printf("Card did not respond to voltage select!\n");
56196826 1654#endif
272cc70b
AF		 1655 return UNUSABLE_ERR;
1656 }
1657 }
1658
bd47c135 1659 if (!err)
e9550449
CLC		 1660 mmc->init_in_progress = 1;
1661
1662 return err;
1663}
1664
1665static int mmc_complete_init(struct mmc *mmc)
1666{
1667 int err = 0;
1668
bd47c135 1669 mmc->init_in_progress = 0;
e9550449
CLC		 1670 if (mmc->op_cond_pending)
1671 err = mmc_complete_op_cond(mmc);
1672
1673 if (!err)
1674 err = mmc_startup(mmc);
bc897b1d
LW		 1675 if (err)
1676 mmc->has_init = 0;
1677 else
1678 mmc->has_init = 1;
e9550449
CLC		 1679 return err;
1680}
1681
1682int mmc_init(struct mmc *mmc)
1683{
bd47c135 1684 int err = 0;
d803fea5 1685 unsigned start;
e9550449
CLC		 1686
1687 if (mmc->has_init)
1688 return 0;
d803fea5
MZ		 1689
1690 start = get_timer(0);
1691
e9550449
CLC		 1692 if (!mmc->init_in_progress)
1693 err = mmc_start_init(mmc);
1694
bd47c135 1695 if (!err)
e9550449
CLC		 1696 err = mmc_complete_init(mmc);
1697 debug("%s: %d, time %lu\n", __func__, err, get_timer(start));
bc897b1d 1698 return err;
272cc70b
AF		 1699}
1700
ab71188c
MN		 1701int mmc_set_dsr(struct mmc *mmc, u16 val)
1702{
1703 mmc->dsr = val;
1704 return 0;
1705}
1706
cee9ab7c
JH		 1707/* CPU-specific MMC initializations */
1708__weak int cpu_mmc_init(bd_t *bis)
272cc70b
AF		 1709{
1710 return -1;
1711}
1712
cee9ab7c
JH		 1713/* board-specific MMC initializations. */
1714__weak int board_mmc_init(bd_t *bis)
1715{
1716 return -1;
1717}
272cc70b 1718
56196826
PB		 1719#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
1720
272cc70b
AF		 1721void print_mmc_devices(char separator)
1722{
1723 struct mmc *m;
1724 struct list_head *entry;
34dd9284 1725 char *mmc_type;
272cc70b
AF		 1726
1727 list_for_each(entry, &mmc_devices) {
1728 m = list_entry(entry, struct mmc, link);
1729
34dd9284
PM		 1730 if (m->has_init)
1731 mmc_type = IS_SD(m) ? "SD" : "eMMC";
1732 else
1733 mmc_type = NULL;
1734
bcce53d0 1735 printf("%s: %d", m->cfg->name, m->block_dev.devnum);
34dd9284
PM		 1736 if (mmc_type)
1737 printf(" (%s)", mmc_type);
272cc70b 1738
e75eaf10
LP		 1739 if (entry->next != &mmc_devices) {
1740 printf("%c", separator);
1741 if (separator != '\n')
1742 puts (" ");
1743 }
272cc70b
AF		 1744 }
1745
1746 printf("\n");
1747}
1748
56196826
PB		 1749#else
1750void print_mmc_devices(char separator) { }
1751#endif
1752
ea6ebe21
LW		 1753int get_mmc_num(void)
1754{
1755 return cur_dev_num;
1756}
1757
e9550449
CLC		 1758void mmc_set_preinit(struct mmc *mmc, int preinit)
1759{
1760 mmc->preinit = preinit;
1761}
1762
1763static void do_preinit(void)
1764{
1765 struct mmc *m;
1766 struct list_head *entry;
1767
1768 list_for_each(entry, &mmc_devices) {
1769 m = list_entry(entry, struct mmc, link);
1770
5a8dbdc6
YL		 1771#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
1772 mmc_set_preinit(m, 1);
1773#endif
e9550449
CLC		 1774 if (m->preinit)
1775 mmc_start_init(m);
1776 }
1777}
1778
8e3332e2
SS		 1779#if defined(CONFIG_DM_MMC) && defined(CONFIG_SPL_BUILD)
1780static int mmc_probe(bd_t *bis)
1781{
1782 return 0;
1783}
1784#elif defined(CONFIG_DM_MMC)
1785static int mmc_probe(bd_t *bis)
1786{
4a1db6d8 1787 int ret, i;
8e3332e2 1788 struct uclass *uc;
4a1db6d8 1789 struct udevice *dev;
8e3332e2
SS		 1790
1791 ret = uclass_get(UCLASS_MMC, &uc);
1792 if (ret)
1793 return ret;
1794
4a1db6d8
SG		 1795 /*
1796 * Try to add them in sequence order. Really with driver model we
1797 * should allow holes, but the current MMC list does not allow that.
1798 * So if we request 0, 1, 3 we will get 0, 1, 2.
1799 */
1800 for (i = 0; ; i++) {
1801 ret = uclass_get_device_by_seq(UCLASS_MMC, i, &dev);
1802 if (ret == -ENODEV)
1803 break;
1804 }
1805 uclass_foreach_dev(dev, uc) {
1806 ret = device_probe(dev);
8e3332e2 1807 if (ret)
4a1db6d8 1808 printf("%s - probe failed: %d\n", dev->name, ret);
8e3332e2
SS		 1809 }
1810
1811 return 0;
1812}
1813#else
1814static int mmc_probe(bd_t *bis)
1815{
1816 if (board_mmc_init(bis) < 0)
1817 cpu_mmc_init(bis);
1818
1819 return 0;
1820}
1821#endif
e9550449 1822
272cc70b
AF		 1823int mmc_initialize(bd_t *bis)
1824{
1b26bab1 1825 static int initialized = 0;
8e3332e2 1826 int ret;
1b26bab1
DK		 1827 if (initialized) /* Avoid initializing mmc multiple times */
1828 return 0;
1829 initialized = 1;
1830
272cc70b
AF		 1831 INIT_LIST_HEAD (&mmc_devices);
1832 cur_dev_num = 0;
1833
8e3332e2
SS		 1834 ret = mmc_probe(bis);
1835 if (ret)
1836 return ret;
272cc70b 1837
bb0dc108 1838#ifndef CONFIG_SPL_BUILD
272cc70b 1839 print_mmc_devices(',');
bb0dc108 1840#endif
272cc70b 1841
e9550449 1842 do_preinit();
272cc70b
AF		 1843 return 0;
1844}
3690d6d6
A		 1845
1846#ifdef CONFIG_SUPPORT_EMMC_BOOT
1847/*
1848 * This function changes the size of boot partition and the size of rpmb
1849 * partition present on EMMC devices.
1850 *
1851 * Input Parameters:
1852 * struct *mmc: pointer for the mmc device strcuture
1853 * bootsize: size of boot partition
1854 * rpmbsize: size of rpmb partition
1855 *
1856 * Returns 0 on success.
1857 */
1858
1859int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize,
1860 unsigned long rpmbsize)
1861{
1862 int err;
1863 struct mmc_cmd cmd;
1864
1865 /* Only use this command for raw EMMC moviNAND. Enter backdoor mode */
1866 cmd.cmdidx = MMC_CMD_RES_MAN;
1867 cmd.resp_type = MMC_RSP_R1b;
1868 cmd.cmdarg = MMC_CMD62_ARG1;
1869
1870 err = mmc_send_cmd(mmc, &cmd, NULL);
1871 if (err) {
1872 debug("mmc_boot_partition_size_change: Error1 = %d\n", err);
1873 return err;
1874 }
1875
1876 /* Boot partition changing mode */
1877 cmd.cmdidx = MMC_CMD_RES_MAN;
1878 cmd.resp_type = MMC_RSP_R1b;
1879 cmd.cmdarg = MMC_CMD62_ARG2;
1880
1881 err = mmc_send_cmd(mmc, &cmd, NULL);
1882 if (err) {
1883 debug("mmc_boot_partition_size_change: Error2 = %d\n", err);
1884 return err;
1885 }
1886 /* boot partition size is multiple of 128KB */
1887 bootsize = (bootsize * 1024) / 128;
1888
1889 /* Arg: boot partition size */
1890 cmd.cmdidx = MMC_CMD_RES_MAN;
1891 cmd.resp_type = MMC_RSP_R1b;
1892 cmd.cmdarg = bootsize;
1893
1894 err = mmc_send_cmd(mmc, &cmd, NULL);
1895 if (err) {
1896 debug("mmc_boot_partition_size_change: Error3 = %d\n", err);
1897 return err;
1898 }
1899 /* RPMB partition size is multiple of 128KB */
1900 rpmbsize = (rpmbsize * 1024) / 128;
1901 /* Arg: RPMB partition size */
1902 cmd.cmdidx = MMC_CMD_RES_MAN;
1903 cmd.resp_type = MMC_RSP_R1b;
1904 cmd.cmdarg = rpmbsize;
1905
1906 err = mmc_send_cmd(mmc, &cmd, NULL);
1907 if (err) {
1908 debug("mmc_boot_partition_size_change: Error4 = %d\n", err);
1909 return err;
1910 }
1911 return 0;
1912}
1913
5a99b9de
TR		 1914/*
1915 * Modify EXT_CSD[177] which is BOOT_BUS_WIDTH
1916 * based on the passed in values for BOOT_BUS_WIDTH, RESET_BOOT_BUS_WIDTH
1917 * and BOOT_MODE.
1918 *
1919 * Returns 0 on success.
1920 */
1921int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode)
1922{
1923 int err;
1924
1925 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BOOT_BUS_WIDTH,
1926 EXT_CSD_BOOT_BUS_WIDTH_MODE(mode) |
1927 EXT_CSD_BOOT_BUS_WIDTH_RESET(reset) |
1928 EXT_CSD_BOOT_BUS_WIDTH_WIDTH(width));
1929
1930 if (err)
1931 return err;
1932 return 0;
1933}
1934
792970b0
TR		 1935/*
1936 * Modify EXT_CSD[179] which is PARTITION_CONFIG (formerly BOOT_CONFIG)
1937 * based on the passed in values for BOOT_ACK, BOOT_PARTITION_ENABLE and
1938 * PARTITION_ACCESS.
1939 *
1940 * Returns 0 on success.
1941 */
1942int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access)
1943{
1944 int err;
1945
1946 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF,
1947 EXT_CSD_BOOT_ACK(ack) |
1948 EXT_CSD_BOOT_PART_NUM(part_num) |
1949 EXT_CSD_PARTITION_ACCESS(access));
1950
1951 if (err)
1952 return err;
1953 return 0;
1954}
33ace362
TR		 1955
1956/*
1957 * Modify EXT_CSD[162] which is RST_n_FUNCTION based on the given value
1958 * for enable. Note that this is a write-once field for non-zero values.
1959 *
1960 * Returns 0 on success.
1961 */
1962int mmc_set_rst_n_function(struct mmc *mmc, u8 enable)
1963{
1964 return mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_RST_N_FUNCTION,
1965 enable);
1966}
3690d6d6 1967#endif
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