]> Git Repo - u-boot.git/blame - drivers/mmc/mmc.c
mmc: Convert mmc struct's name array to a pointer
[u-boot.git] / drivers / mmc / mmc.c
CommitLineData
272cc70b
AF
1/*
2 * Copyright 2008, Freescale Semiconductor, Inc
3 * Andy Fleming
4 *
5 * Based vaguely on the Linux code
6 *
1a459660 7 * SPDX-License-Identifier: GPL-2.0+
272cc70b
AF
8 */
9
10#include <config.h>
11#include <common.h>
12#include <command.h>
13#include <mmc.h>
14#include <part.h>
15#include <malloc.h>
16#include <linux/list.h>
9b1f942c 17#include <div64.h>
da61fa5f 18#include "mmc_private.h"
272cc70b 19
ce0fbcd2
MW
20/* Set block count limit because of 16 bit register limit on some hardware*/
21#ifndef CONFIG_SYS_MMC_MAX_BLK_COUNT
22#define CONFIG_SYS_MMC_MAX_BLK_COUNT 65535
23#endif
24
272cc70b
AF
25static struct list_head mmc_devices;
26static int cur_dev_num = -1;
27
d23d8d7e
NK
28int __weak board_mmc_getwp(struct mmc *mmc)
29{
30 return -1;
31}
32
33int mmc_getwp(struct mmc *mmc)
34{
35 int wp;
36
37 wp = board_mmc_getwp(mmc);
38
d4e1da4e 39 if (wp < 0) {
ab769f22
PA
40 if (mmc->ops->getwp)
41 wp = mmc->ops->getwp(mmc);
d4e1da4e
PK
42 else
43 wp = 0;
44 }
d23d8d7e
NK
45
46 return wp;
47}
48
314284b1 49int __board_mmc_getcd(struct mmc *mmc) {
11fdade2
SB
50 return -1;
51}
52
314284b1 53int board_mmc_getcd(struct mmc *mmc)__attribute__((weak,
11fdade2
SB
54 alias("__board_mmc_getcd")));
55
da61fa5f 56int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
272cc70b 57{
5db2fe3a 58 int ret;
8635ff9e 59
8635ff9e 60#ifdef CONFIG_MMC_TRACE
5db2fe3a
RR
61 int i;
62 u8 *ptr;
63
64 printf("CMD_SEND:%d\n", cmd->cmdidx);
65 printf("\t\tARG\t\t\t 0x%08X\n", cmd->cmdarg);
ab769f22 66 ret = mmc->ops->send_cmd(mmc, cmd, data);
5db2fe3a
RR
67 switch (cmd->resp_type) {
68 case MMC_RSP_NONE:
69 printf("\t\tMMC_RSP_NONE\n");
70 break;
71 case MMC_RSP_R1:
72 printf("\t\tMMC_RSP_R1,5,6,7 \t 0x%08X \n",
73 cmd->response[0]);
74 break;
75 case MMC_RSP_R1b:
76 printf("\t\tMMC_RSP_R1b\t\t 0x%08X \n",
77 cmd->response[0]);
78 break;
79 case MMC_RSP_R2:
80 printf("\t\tMMC_RSP_R2\t\t 0x%08X \n",
81 cmd->response[0]);
82 printf("\t\t \t\t 0x%08X \n",
83 cmd->response[1]);
84 printf("\t\t \t\t 0x%08X \n",
85 cmd->response[2]);
86 printf("\t\t \t\t 0x%08X \n",
87 cmd->response[3]);
88 printf("\n");
89 printf("\t\t\t\t\tDUMPING DATA\n");
90 for (i = 0; i < 4; i++) {
91 int j;
92 printf("\t\t\t\t\t%03d - ", i*4);
146bec79 93 ptr = (u8 *)&cmd->response[i];
5db2fe3a
RR
94 ptr += 3;
95 for (j = 0; j < 4; j++)
96 printf("%02X ", *ptr--);
97 printf("\n");
98 }
99 break;
100 case MMC_RSP_R3:
101 printf("\t\tMMC_RSP_R3,4\t\t 0x%08X \n",
102 cmd->response[0]);
103 break;
104 default:
105 printf("\t\tERROR MMC rsp not supported\n");
106 break;
107 }
5db2fe3a 108#else
ab769f22 109 ret = mmc->ops->send_cmd(mmc, cmd, data);
5db2fe3a 110#endif
8635ff9e 111 return ret;
272cc70b
AF
112}
113
da61fa5f 114int mmc_send_status(struct mmc *mmc, int timeout)
5d4fc8d9
RR
115{
116 struct mmc_cmd cmd;
d617c426 117 int err, retries = 5;
5d4fc8d9
RR
118#ifdef CONFIG_MMC_TRACE
119 int status;
120#endif
121
122 cmd.cmdidx = MMC_CMD_SEND_STATUS;
123 cmd.resp_type = MMC_RSP_R1;
aaf3d41a
MV
124 if (!mmc_host_is_spi(mmc))
125 cmd.cmdarg = mmc->rca << 16;
5d4fc8d9
RR
126
127 do {
128 err = mmc_send_cmd(mmc, &cmd, NULL);
d617c426
JK
129 if (!err) {
130 if ((cmd.response[0] & MMC_STATUS_RDY_FOR_DATA) &&
131 (cmd.response[0] & MMC_STATUS_CURR_STATE) !=
132 MMC_STATE_PRG)
133 break;
134 else if (cmd.response[0] & MMC_STATUS_MASK) {
56196826 135#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
d617c426
JK
136 printf("Status Error: 0x%08X\n",
137 cmd.response[0]);
56196826 138#endif
d617c426
JK
139 return COMM_ERR;
140 }
141 } else if (--retries < 0)
5d4fc8d9 142 return err;
5d4fc8d9
RR
143
144 udelay(1000);
145
5d4fc8d9
RR
146 } while (timeout--);
147
5db2fe3a
RR
148#ifdef CONFIG_MMC_TRACE
149 status = (cmd.response[0] & MMC_STATUS_CURR_STATE) >> 9;
150 printf("CURR STATE:%d\n", status);
151#endif
5b0c942f 152 if (timeout <= 0) {
56196826 153#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
5d4fc8d9 154 printf("Timeout waiting card ready\n");
56196826 155#endif
5d4fc8d9
RR
156 return TIMEOUT;
157 }
158
159 return 0;
160}
161
da61fa5f 162int mmc_set_blocklen(struct mmc *mmc, int len)
272cc70b
AF
163{
164 struct mmc_cmd cmd;
165
166 cmd.cmdidx = MMC_CMD_SET_BLOCKLEN;
167 cmd.resp_type = MMC_RSP_R1;
168 cmd.cmdarg = len;
272cc70b
AF
169
170 return mmc_send_cmd(mmc, &cmd, NULL);
171}
172
173struct mmc *find_mmc_device(int dev_num)
174{
175 struct mmc *m;
176 struct list_head *entry;
177
178 list_for_each(entry, &mmc_devices) {
179 m = list_entry(entry, struct mmc, link);
180
181 if (m->block_dev.dev == dev_num)
182 return m;
183 }
184
56196826 185#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
272cc70b 186 printf("MMC Device %d not found\n", dev_num);
56196826 187#endif
272cc70b
AF
188
189 return NULL;
190}
191
ff8fef56 192static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start,
fdbb873e 193 lbaint_t blkcnt)
272cc70b
AF
194{
195 struct mmc_cmd cmd;
196 struct mmc_data data;
197
4a1a06bc
AS
198 if (blkcnt > 1)
199 cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK;
200 else
201 cmd.cmdidx = MMC_CMD_READ_SINGLE_BLOCK;
272cc70b
AF
202
203 if (mmc->high_capacity)
4a1a06bc 204 cmd.cmdarg = start;
272cc70b 205 else
4a1a06bc 206 cmd.cmdarg = start * mmc->read_bl_len;
272cc70b
AF
207
208 cmd.resp_type = MMC_RSP_R1;
272cc70b
AF
209
210 data.dest = dst;
4a1a06bc 211 data.blocks = blkcnt;
272cc70b
AF
212 data.blocksize = mmc->read_bl_len;
213 data.flags = MMC_DATA_READ;
214
4a1a06bc
AS
215 if (mmc_send_cmd(mmc, &cmd, &data))
216 return 0;
272cc70b 217
4a1a06bc
AS
218 if (blkcnt > 1) {
219 cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
220 cmd.cmdarg = 0;
221 cmd.resp_type = MMC_RSP_R1b;
4a1a06bc 222 if (mmc_send_cmd(mmc, &cmd, NULL)) {
56196826 223#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
4a1a06bc 224 printf("mmc fail to send stop cmd\n");
56196826 225#endif
4a1a06bc
AS
226 return 0;
227 }
272cc70b
AF
228 }
229
4a1a06bc 230 return blkcnt;
272cc70b
AF
231}
232
ff8fef56 233static ulong mmc_bread(int dev_num, lbaint_t start, lbaint_t blkcnt, void *dst)
272cc70b 234{
4a1a06bc
AS
235 lbaint_t cur, blocks_todo = blkcnt;
236
237 if (blkcnt == 0)
238 return 0;
272cc70b 239
4a1a06bc 240 struct mmc *mmc = find_mmc_device(dev_num);
272cc70b
AF
241 if (!mmc)
242 return 0;
243
d2bf29e3 244 if ((start + blkcnt) > mmc->block_dev.lba) {
56196826 245#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
ff8fef56 246 printf("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n",
d2bf29e3 247 start + blkcnt, mmc->block_dev.lba);
56196826 248#endif
d2bf29e3
LW
249 return 0;
250 }
272cc70b 251
4a1a06bc 252 if (mmc_set_blocklen(mmc, mmc->read_bl_len))
272cc70b 253 return 0;
272cc70b 254
4a1a06bc 255 do {
8feafcc4 256 cur = (blocks_todo > mmc->b_max) ? mmc->b_max : blocks_todo;
4a1a06bc
AS
257 if(mmc_read_blocks(mmc, dst, start, cur) != cur)
258 return 0;
259 blocks_todo -= cur;
260 start += cur;
261 dst += cur * mmc->read_bl_len;
262 } while (blocks_todo > 0);
272cc70b
AF
263
264 return blkcnt;
265}
266
fdbb873e 267static int mmc_go_idle(struct mmc *mmc)
272cc70b
AF
268{
269 struct mmc_cmd cmd;
270 int err;
271
272 udelay(1000);
273
274 cmd.cmdidx = MMC_CMD_GO_IDLE_STATE;
275 cmd.cmdarg = 0;
276 cmd.resp_type = MMC_RSP_NONE;
272cc70b
AF
277
278 err = mmc_send_cmd(mmc, &cmd, NULL);
279
280 if (err)
281 return err;
282
283 udelay(2000);
284
285 return 0;
286}
287
fdbb873e 288static int sd_send_op_cond(struct mmc *mmc)
272cc70b
AF
289{
290 int timeout = 1000;
291 int err;
292 struct mmc_cmd cmd;
293
294 do {
295 cmd.cmdidx = MMC_CMD_APP_CMD;
296 cmd.resp_type = MMC_RSP_R1;
297 cmd.cmdarg = 0;
272cc70b
AF
298
299 err = mmc_send_cmd(mmc, &cmd, NULL);
300
301 if (err)
302 return err;
303
304 cmd.cmdidx = SD_CMD_APP_SEND_OP_COND;
305 cmd.resp_type = MMC_RSP_R3;
250de12b
SB
306
307 /*
308 * Most cards do not answer if some reserved bits
309 * in the ocr are set. However, Some controller
310 * can set bit 7 (reserved for low voltages), but
311 * how to manage low voltages SD card is not yet
312 * specified.
313 */
d52ebf10
TC
314 cmd.cmdarg = mmc_host_is_spi(mmc) ? 0 :
315 (mmc->voltages & 0xff8000);
272cc70b
AF
316
317 if (mmc->version == SD_VERSION_2)
318 cmd.cmdarg |= OCR_HCS;
319
320 err = mmc_send_cmd(mmc, &cmd, NULL);
321
322 if (err)
323 return err;
324
325 udelay(1000);
326 } while ((!(cmd.response[0] & OCR_BUSY)) && timeout--);
327
328 if (timeout <= 0)
329 return UNUSABLE_ERR;
330
331 if (mmc->version != SD_VERSION_2)
332 mmc->version = SD_VERSION_1_0;
333
d52ebf10
TC
334 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
335 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
336 cmd.resp_type = MMC_RSP_R3;
337 cmd.cmdarg = 0;
d52ebf10
TC
338
339 err = mmc_send_cmd(mmc, &cmd, NULL);
340
341 if (err)
342 return err;
343 }
344
998be3dd 345 mmc->ocr = cmd.response[0];
272cc70b
AF
346
347 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
348 mmc->rca = 0;
349
350 return 0;
351}
352
e9550449
CLC
353/* We pass in the cmd since otherwise the init seems to fail */
354static int mmc_send_op_cond_iter(struct mmc *mmc, struct mmc_cmd *cmd,
355 int use_arg)
272cc70b 356{
272cc70b
AF
357 int err;
358
e9550449
CLC
359 cmd->cmdidx = MMC_CMD_SEND_OP_COND;
360 cmd->resp_type = MMC_RSP_R3;
361 cmd->cmdarg = 0;
362 if (use_arg && !mmc_host_is_spi(mmc)) {
363 cmd->cmdarg =
364 (mmc->voltages &
365 (mmc->op_cond_response & OCR_VOLTAGE_MASK)) |
366 (mmc->op_cond_response & OCR_ACCESS_MODE);
367
368 if (mmc->host_caps & MMC_MODE_HC)
369 cmd->cmdarg |= OCR_HCS;
370 }
371 err = mmc_send_cmd(mmc, cmd, NULL);
372 if (err)
373 return err;
374 mmc->op_cond_response = cmd->response[0];
375 return 0;
376}
377
378int mmc_send_op_cond(struct mmc *mmc)
379{
380 struct mmc_cmd cmd;
381 int err, i;
382
272cc70b
AF
383 /* Some cards seem to need this */
384 mmc_go_idle(mmc);
385
31cacbab 386 /* Asking to the card its capabilities */
e9550449
CLC
387 mmc->op_cond_pending = 1;
388 for (i = 0; i < 2; i++) {
389 err = mmc_send_op_cond_iter(mmc, &cmd, i != 0);
390 if (err)
391 return err;
cd6881b5 392
e9550449
CLC
393 /* exit if not busy (flag seems to be inverted) */
394 if (mmc->op_cond_response & OCR_BUSY)
395 return 0;
396 }
397 return IN_PROGRESS;
398}
cd6881b5 399
e9550449
CLC
400int mmc_complete_op_cond(struct mmc *mmc)
401{
402 struct mmc_cmd cmd;
403 int timeout = 1000;
404 uint start;
405 int err;
cd6881b5 406
e9550449
CLC
407 mmc->op_cond_pending = 0;
408 start = get_timer(0);
272cc70b 409 do {
e9550449 410 err = mmc_send_op_cond_iter(mmc, &cmd, 1);
272cc70b
AF
411 if (err)
412 return err;
e9550449
CLC
413 if (get_timer(start) > timeout)
414 return UNUSABLE_ERR;
415 udelay(100);
416 } while (!(mmc->op_cond_response & OCR_BUSY));
272cc70b 417
d52ebf10
TC
418 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
419 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
420 cmd.resp_type = MMC_RSP_R3;
421 cmd.cmdarg = 0;
d52ebf10
TC
422
423 err = mmc_send_cmd(mmc, &cmd, NULL);
424
425 if (err)
426 return err;
427 }
428
272cc70b 429 mmc->version = MMC_VERSION_UNKNOWN;
998be3dd 430 mmc->ocr = cmd.response[0];
272cc70b
AF
431
432 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
def816a2 433 mmc->rca = 1;
272cc70b
AF
434
435 return 0;
436}
437
438
fdbb873e 439static int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd)
272cc70b
AF
440{
441 struct mmc_cmd cmd;
442 struct mmc_data data;
443 int err;
444
445 /* Get the Card Status Register */
446 cmd.cmdidx = MMC_CMD_SEND_EXT_CSD;
447 cmd.resp_type = MMC_RSP_R1;
448 cmd.cmdarg = 0;
272cc70b 449
cdfd1ac6 450 data.dest = (char *)ext_csd;
272cc70b 451 data.blocks = 1;
8bfa195e 452 data.blocksize = MMC_MAX_BLOCK_LEN;
272cc70b
AF
453 data.flags = MMC_DATA_READ;
454
455 err = mmc_send_cmd(mmc, &cmd, &data);
456
457 return err;
458}
459
460
fdbb873e 461static int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value)
272cc70b
AF
462{
463 struct mmc_cmd cmd;
5d4fc8d9
RR
464 int timeout = 1000;
465 int ret;
272cc70b
AF
466
467 cmd.cmdidx = MMC_CMD_SWITCH;
468 cmd.resp_type = MMC_RSP_R1b;
469 cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) |
5d4fc8d9
RR
470 (index << 16) |
471 (value << 8);
272cc70b 472
5d4fc8d9
RR
473 ret = mmc_send_cmd(mmc, &cmd, NULL);
474
475 /* Waiting for the ready status */
93ad0d18
JK
476 if (!ret)
477 ret = mmc_send_status(mmc, timeout);
5d4fc8d9
RR
478
479 return ret;
480
272cc70b
AF
481}
482
fdbb873e 483static int mmc_change_freq(struct mmc *mmc)
272cc70b 484{
8bfa195e 485 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
272cc70b
AF
486 char cardtype;
487 int err;
488
489 mmc->card_caps = 0;
490
d52ebf10
TC
491 if (mmc_host_is_spi(mmc))
492 return 0;
493
272cc70b
AF
494 /* Only version 4 supports high-speed */
495 if (mmc->version < MMC_VERSION_4)
496 return 0;
497
272cc70b
AF
498 err = mmc_send_ext_csd(mmc, ext_csd);
499
500 if (err)
501 return err;
502
0560db18 503 cardtype = ext_csd[EXT_CSD_CARD_TYPE] & 0xf;
272cc70b
AF
504
505 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING, 1);
506
507 if (err)
508 return err;
509
510 /* Now check to see that it worked */
511 err = mmc_send_ext_csd(mmc, ext_csd);
512
513 if (err)
514 return err;
515
516 /* No high-speed support */
0560db18 517 if (!ext_csd[EXT_CSD_HS_TIMING])
272cc70b
AF
518 return 0;
519
520 /* High Speed is set, there are two types: 52MHz and 26MHz */
521 if (cardtype & MMC_HS_52MHZ)
522 mmc->card_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
523 else
524 mmc->card_caps |= MMC_MODE_HS;
525
526 return 0;
527}
528
f866a46d
SW
529static int mmc_set_capacity(struct mmc *mmc, int part_num)
530{
531 switch (part_num) {
532 case 0:
533 mmc->capacity = mmc->capacity_user;
534 break;
535 case 1:
536 case 2:
537 mmc->capacity = mmc->capacity_boot;
538 break;
539 case 3:
540 mmc->capacity = mmc->capacity_rpmb;
541 break;
542 case 4:
543 case 5:
544 case 6:
545 case 7:
546 mmc->capacity = mmc->capacity_gp[part_num - 4];
547 break;
548 default:
549 return -1;
550 }
551
552 mmc->block_dev.lba = lldiv(mmc->capacity, mmc->read_bl_len);
553
554 return 0;
555}
556
bc897b1d
LW
557int mmc_switch_part(int dev_num, unsigned int part_num)
558{
559 struct mmc *mmc = find_mmc_device(dev_num);
f866a46d 560 int ret;
bc897b1d
LW
561
562 if (!mmc)
563 return -1;
564
f866a46d
SW
565 ret = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF,
566 (mmc->part_config & ~PART_ACCESS_MASK)
567 | (part_num & PART_ACCESS_MASK));
568 if (ret)
569 return ret;
570
571 return mmc_set_capacity(mmc, part_num);
bc897b1d
LW
572}
573
48972d90
TR
574int mmc_getcd(struct mmc *mmc)
575{
576 int cd;
577
578 cd = board_mmc_getcd(mmc);
579
d4e1da4e 580 if (cd < 0) {
ab769f22
PA
581 if (mmc->ops->getcd)
582 cd = mmc->ops->getcd(mmc);
d4e1da4e
PK
583 else
584 cd = 1;
585 }
48972d90
TR
586
587 return cd;
588}
589
fdbb873e 590static int sd_switch(struct mmc *mmc, int mode, int group, u8 value, u8 *resp)
272cc70b
AF
591{
592 struct mmc_cmd cmd;
593 struct mmc_data data;
594
595 /* Switch the frequency */
596 cmd.cmdidx = SD_CMD_SWITCH_FUNC;
597 cmd.resp_type = MMC_RSP_R1;
598 cmd.cmdarg = (mode << 31) | 0xffffff;
599 cmd.cmdarg &= ~(0xf << (group * 4));
600 cmd.cmdarg |= value << (group * 4);
272cc70b
AF
601
602 data.dest = (char *)resp;
603 data.blocksize = 64;
604 data.blocks = 1;
605 data.flags = MMC_DATA_READ;
606
607 return mmc_send_cmd(mmc, &cmd, &data);
608}
609
610
fdbb873e 611static int sd_change_freq(struct mmc *mmc)
272cc70b
AF
612{
613 int err;
614 struct mmc_cmd cmd;
f781dd38
A
615 ALLOC_CACHE_ALIGN_BUFFER(uint, scr, 2);
616 ALLOC_CACHE_ALIGN_BUFFER(uint, switch_status, 16);
272cc70b
AF
617 struct mmc_data data;
618 int timeout;
619
620 mmc->card_caps = 0;
621
d52ebf10
TC
622 if (mmc_host_is_spi(mmc))
623 return 0;
624
272cc70b
AF
625 /* Read the SCR to find out if this card supports higher speeds */
626 cmd.cmdidx = MMC_CMD_APP_CMD;
627 cmd.resp_type = MMC_RSP_R1;
628 cmd.cmdarg = mmc->rca << 16;
272cc70b
AF
629
630 err = mmc_send_cmd(mmc, &cmd, NULL);
631
632 if (err)
633 return err;
634
635 cmd.cmdidx = SD_CMD_APP_SEND_SCR;
636 cmd.resp_type = MMC_RSP_R1;
637 cmd.cmdarg = 0;
272cc70b
AF
638
639 timeout = 3;
640
641retry_scr:
f781dd38 642 data.dest = (char *)scr;
272cc70b
AF
643 data.blocksize = 8;
644 data.blocks = 1;
645 data.flags = MMC_DATA_READ;
646
647 err = mmc_send_cmd(mmc, &cmd, &data);
648
649 if (err) {
650 if (timeout--)
651 goto retry_scr;
652
653 return err;
654 }
655
4e3d89ba
YK
656 mmc->scr[0] = __be32_to_cpu(scr[0]);
657 mmc->scr[1] = __be32_to_cpu(scr[1]);
272cc70b
AF
658
659 switch ((mmc->scr[0] >> 24) & 0xf) {
660 case 0:
661 mmc->version = SD_VERSION_1_0;
662 break;
663 case 1:
664 mmc->version = SD_VERSION_1_10;
665 break;
666 case 2:
667 mmc->version = SD_VERSION_2;
1741c64d
JC
668 if ((mmc->scr[0] >> 15) & 0x1)
669 mmc->version = SD_VERSION_3;
272cc70b
AF
670 break;
671 default:
672 mmc->version = SD_VERSION_1_0;
673 break;
674 }
675
b44c7083
AS
676 if (mmc->scr[0] & SD_DATA_4BIT)
677 mmc->card_caps |= MMC_MODE_4BIT;
678
272cc70b
AF
679 /* Version 1.0 doesn't support switching */
680 if (mmc->version == SD_VERSION_1_0)
681 return 0;
682
683 timeout = 4;
684 while (timeout--) {
685 err = sd_switch(mmc, SD_SWITCH_CHECK, 0, 1,
f781dd38 686 (u8 *)switch_status);
272cc70b
AF
687
688 if (err)
689 return err;
690
691 /* The high-speed function is busy. Try again */
4e3d89ba 692 if (!(__be32_to_cpu(switch_status[7]) & SD_HIGHSPEED_BUSY))
272cc70b
AF
693 break;
694 }
695
272cc70b 696 /* If high-speed isn't supported, we return */
4e3d89ba 697 if (!(__be32_to_cpu(switch_status[3]) & SD_HIGHSPEED_SUPPORTED))
272cc70b
AF
698 return 0;
699
2c3fbf4c
ML
700 /*
701 * If the host doesn't support SD_HIGHSPEED, do not switch card to
702 * HIGHSPEED mode even if the card support SD_HIGHSPPED.
703 * This can avoid furthur problem when the card runs in different
704 * mode between the host.
705 */
706 if (!((mmc->host_caps & MMC_MODE_HS_52MHz) &&
707 (mmc->host_caps & MMC_MODE_HS)))
708 return 0;
709
f781dd38 710 err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, 1, (u8 *)switch_status);
272cc70b
AF
711
712 if (err)
713 return err;
714
4e3d89ba 715 if ((__be32_to_cpu(switch_status[4]) & 0x0f000000) == 0x01000000)
272cc70b
AF
716 mmc->card_caps |= MMC_MODE_HS;
717
718 return 0;
719}
720
721/* frequency bases */
722/* divided by 10 to be nice to platforms without floating point */
5f837c2c 723static const int fbase[] = {
272cc70b
AF
724 10000,
725 100000,
726 1000000,
727 10000000,
728};
729
730/* Multiplier values for TRAN_SPEED. Multiplied by 10 to be nice
731 * to platforms without floating point.
732 */
5f837c2c 733static const int multipliers[] = {
272cc70b
AF
734 0, /* reserved */
735 10,
736 12,
737 13,
738 15,
739 20,
740 25,
741 30,
742 35,
743 40,
744 45,
745 50,
746 55,
747 60,
748 70,
749 80,
750};
751
fdbb873e 752static void mmc_set_ios(struct mmc *mmc)
272cc70b 753{
ab769f22
PA
754 if (mmc->ops->set_ios)
755 mmc->ops->set_ios(mmc);
272cc70b
AF
756}
757
758void mmc_set_clock(struct mmc *mmc, uint clock)
759{
760 if (clock > mmc->f_max)
761 clock = mmc->f_max;
762
763 if (clock < mmc->f_min)
764 clock = mmc->f_min;
765
766 mmc->clock = clock;
767
768 mmc_set_ios(mmc);
769}
770
fdbb873e 771static void mmc_set_bus_width(struct mmc *mmc, uint width)
272cc70b
AF
772{
773 mmc->bus_width = width;
774
775 mmc_set_ios(mmc);
776}
777
fdbb873e 778static int mmc_startup(struct mmc *mmc)
272cc70b 779{
f866a46d 780 int err, i;
272cc70b 781 uint mult, freq;
639b7827 782 u64 cmult, csize, capacity;
272cc70b 783 struct mmc_cmd cmd;
8bfa195e
SG
784 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
785 ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
5d4fc8d9 786 int timeout = 1000;
272cc70b 787
d52ebf10
TC
788#ifdef CONFIG_MMC_SPI_CRC_ON
789 if (mmc_host_is_spi(mmc)) { /* enable CRC check for spi */
790 cmd.cmdidx = MMC_CMD_SPI_CRC_ON_OFF;
791 cmd.resp_type = MMC_RSP_R1;
792 cmd.cmdarg = 1;
d52ebf10
TC
793 err = mmc_send_cmd(mmc, &cmd, NULL);
794
795 if (err)
796 return err;
797 }
798#endif
799
272cc70b 800 /* Put the Card in Identify Mode */
d52ebf10
TC
801 cmd.cmdidx = mmc_host_is_spi(mmc) ? MMC_CMD_SEND_CID :
802 MMC_CMD_ALL_SEND_CID; /* cmd not supported in spi */
272cc70b
AF
803 cmd.resp_type = MMC_RSP_R2;
804 cmd.cmdarg = 0;
272cc70b
AF
805
806 err = mmc_send_cmd(mmc, &cmd, NULL);
807
808 if (err)
809 return err;
810
811 memcpy(mmc->cid, cmd.response, 16);
812
813 /*
814 * For MMC cards, set the Relative Address.
815 * For SD cards, get the Relatvie Address.
816 * This also puts the cards into Standby State
817 */
d52ebf10
TC
818 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
819 cmd.cmdidx = SD_CMD_SEND_RELATIVE_ADDR;
820 cmd.cmdarg = mmc->rca << 16;
821 cmd.resp_type = MMC_RSP_R6;
272cc70b 822
d52ebf10 823 err = mmc_send_cmd(mmc, &cmd, NULL);
272cc70b 824
d52ebf10
TC
825 if (err)
826 return err;
272cc70b 827
d52ebf10
TC
828 if (IS_SD(mmc))
829 mmc->rca = (cmd.response[0] >> 16) & 0xffff;
830 }
272cc70b
AF
831
832 /* Get the Card-Specific Data */
833 cmd.cmdidx = MMC_CMD_SEND_CSD;
834 cmd.resp_type = MMC_RSP_R2;
835 cmd.cmdarg = mmc->rca << 16;
272cc70b
AF
836
837 err = mmc_send_cmd(mmc, &cmd, NULL);
838
5d4fc8d9
RR
839 /* Waiting for the ready status */
840 mmc_send_status(mmc, timeout);
841
272cc70b
AF
842 if (err)
843 return err;
844
998be3dd
RV
845 mmc->csd[0] = cmd.response[0];
846 mmc->csd[1] = cmd.response[1];
847 mmc->csd[2] = cmd.response[2];
848 mmc->csd[3] = cmd.response[3];
272cc70b
AF
849
850 if (mmc->version == MMC_VERSION_UNKNOWN) {
0b453ffe 851 int version = (cmd.response[0] >> 26) & 0xf;
272cc70b
AF
852
853 switch (version) {
854 case 0:
855 mmc->version = MMC_VERSION_1_2;
856 break;
857 case 1:
858 mmc->version = MMC_VERSION_1_4;
859 break;
860 case 2:
861 mmc->version = MMC_VERSION_2_2;
862 break;
863 case 3:
864 mmc->version = MMC_VERSION_3;
865 break;
866 case 4:
867 mmc->version = MMC_VERSION_4;
868 break;
869 default:
870 mmc->version = MMC_VERSION_1_2;
871 break;
872 }
873 }
874
875 /* divide frequency by 10, since the mults are 10x bigger */
0b453ffe
RV
876 freq = fbase[(cmd.response[0] & 0x7)];
877 mult = multipliers[((cmd.response[0] >> 3) & 0xf)];
272cc70b
AF
878
879 mmc->tran_speed = freq * mult;
880
ab71188c 881 mmc->dsr_imp = ((cmd.response[1] >> 12) & 0x1);
998be3dd 882 mmc->read_bl_len = 1 << ((cmd.response[1] >> 16) & 0xf);
272cc70b
AF
883
884 if (IS_SD(mmc))
885 mmc->write_bl_len = mmc->read_bl_len;
886 else
998be3dd 887 mmc->write_bl_len = 1 << ((cmd.response[3] >> 22) & 0xf);
272cc70b
AF
888
889 if (mmc->high_capacity) {
890 csize = (mmc->csd[1] & 0x3f) << 16
891 | (mmc->csd[2] & 0xffff0000) >> 16;
892 cmult = 8;
893 } else {
894 csize = (mmc->csd[1] & 0x3ff) << 2
895 | (mmc->csd[2] & 0xc0000000) >> 30;
896 cmult = (mmc->csd[2] & 0x00038000) >> 15;
897 }
898
f866a46d
SW
899 mmc->capacity_user = (csize + 1) << (cmult + 2);
900 mmc->capacity_user *= mmc->read_bl_len;
901 mmc->capacity_boot = 0;
902 mmc->capacity_rpmb = 0;
903 for (i = 0; i < 4; i++)
904 mmc->capacity_gp[i] = 0;
272cc70b 905
8bfa195e
SG
906 if (mmc->read_bl_len > MMC_MAX_BLOCK_LEN)
907 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
272cc70b 908
8bfa195e
SG
909 if (mmc->write_bl_len > MMC_MAX_BLOCK_LEN)
910 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
272cc70b 911
ab71188c
MN
912 if ((mmc->dsr_imp) && (0xffffffff != mmc->dsr)) {
913 cmd.cmdidx = MMC_CMD_SET_DSR;
914 cmd.cmdarg = (mmc->dsr & 0xffff) << 16;
915 cmd.resp_type = MMC_RSP_NONE;
916 if (mmc_send_cmd(mmc, &cmd, NULL))
917 printf("MMC: SET_DSR failed\n");
918 }
919
272cc70b 920 /* Select the card, and put it into Transfer Mode */
d52ebf10
TC
921 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
922 cmd.cmdidx = MMC_CMD_SELECT_CARD;
fe8f7066 923 cmd.resp_type = MMC_RSP_R1;
d52ebf10 924 cmd.cmdarg = mmc->rca << 16;
d52ebf10 925 err = mmc_send_cmd(mmc, &cmd, NULL);
272cc70b 926
d52ebf10
TC
927 if (err)
928 return err;
929 }
272cc70b 930
e6f99a56
LW
931 /*
932 * For SD, its erase group is always one sector
933 */
934 mmc->erase_grp_size = 1;
bc897b1d 935 mmc->part_config = MMCPART_NOAVAILABLE;
d23e2c09
SG
936 if (!IS_SD(mmc) && (mmc->version >= MMC_VERSION_4)) {
937 /* check ext_csd version and capacity */
938 err = mmc_send_ext_csd(mmc, ext_csd);
fdbb873e 939 if (!err && (ext_csd[EXT_CSD_REV] >= 2)) {
639b7827
YS
940 /*
941 * According to the JEDEC Standard, the value of
942 * ext_csd's capacity is valid if the value is more
943 * than 2GB
944 */
0560db18
LW
945 capacity = ext_csd[EXT_CSD_SEC_CNT] << 0
946 | ext_csd[EXT_CSD_SEC_CNT + 1] << 8
947 | ext_csd[EXT_CSD_SEC_CNT + 2] << 16
948 | ext_csd[EXT_CSD_SEC_CNT + 3] << 24;
8bfa195e 949 capacity *= MMC_MAX_BLOCK_LEN;
b1f1e821 950 if ((capacity >> 20) > 2 * 1024)
f866a46d 951 mmc->capacity_user = capacity;
d23e2c09 952 }
bc897b1d 953
64f4a619
JC
954 switch (ext_csd[EXT_CSD_REV]) {
955 case 1:
956 mmc->version = MMC_VERSION_4_1;
957 break;
958 case 2:
959 mmc->version = MMC_VERSION_4_2;
960 break;
961 case 3:
962 mmc->version = MMC_VERSION_4_3;
963 break;
964 case 5:
965 mmc->version = MMC_VERSION_4_41;
966 break;
967 case 6:
968 mmc->version = MMC_VERSION_4_5;
969 break;
970 }
971
e6f99a56 972 /*
1937e5aa
OM
973 * Host needs to enable ERASE_GRP_DEF bit if device is
974 * partitioned. This bit will be lost every time after a reset
975 * or power off. This will affect erase size.
e6f99a56 976 */
1937e5aa
OM
977 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) &&
978 (ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE] & PART_ENH_ATTRIB)) {
979 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
980 EXT_CSD_ERASE_GROUP_DEF, 1);
981
982 if (err)
983 return err;
984
985 /* Read out group size from ext_csd */
0560db18 986 mmc->erase_grp_size =
8bfa195e
SG
987 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] *
988 MMC_MAX_BLOCK_LEN * 1024;
989 } else {
1937e5aa 990 /* Calculate the group size from the csd value. */
e6f99a56
LW
991 int erase_gsz, erase_gmul;
992 erase_gsz = (mmc->csd[2] & 0x00007c00) >> 10;
993 erase_gmul = (mmc->csd[2] & 0x000003e0) >> 5;
994 mmc->erase_grp_size = (erase_gsz + 1)
995 * (erase_gmul + 1);
996 }
997
bc897b1d 998 /* store the partition info of emmc */
8948ea83
SW
999 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) ||
1000 ext_csd[EXT_CSD_BOOT_MULT])
0560db18 1001 mmc->part_config = ext_csd[EXT_CSD_PART_CONF];
f866a46d
SW
1002
1003 mmc->capacity_boot = ext_csd[EXT_CSD_BOOT_MULT] << 17;
1004
1005 mmc->capacity_rpmb = ext_csd[EXT_CSD_RPMB_MULT] << 17;
1006
1007 for (i = 0; i < 4; i++) {
1008 int idx = EXT_CSD_GP_SIZE_MULT + i * 3;
1009 mmc->capacity_gp[i] = (ext_csd[idx + 2] << 16) +
1010 (ext_csd[idx + 1] << 8) + ext_csd[idx];
1011 mmc->capacity_gp[i] *=
1012 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
1013 mmc->capacity_gp[i] *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
1014 }
d23e2c09
SG
1015 }
1016
f866a46d
SW
1017 err = mmc_set_capacity(mmc, mmc->part_num);
1018 if (err)
1019 return err;
1020
272cc70b
AF
1021 if (IS_SD(mmc))
1022 err = sd_change_freq(mmc);
1023 else
1024 err = mmc_change_freq(mmc);
1025
1026 if (err)
1027 return err;
1028
1029 /* Restrict card's capabilities by what the host can do */
1030 mmc->card_caps &= mmc->host_caps;
1031
1032 if (IS_SD(mmc)) {
1033 if (mmc->card_caps & MMC_MODE_4BIT) {
1034 cmd.cmdidx = MMC_CMD_APP_CMD;
1035 cmd.resp_type = MMC_RSP_R1;
1036 cmd.cmdarg = mmc->rca << 16;
272cc70b
AF
1037
1038 err = mmc_send_cmd(mmc, &cmd, NULL);
1039 if (err)
1040 return err;
1041
1042 cmd.cmdidx = SD_CMD_APP_SET_BUS_WIDTH;
1043 cmd.resp_type = MMC_RSP_R1;
1044 cmd.cmdarg = 2;
272cc70b
AF
1045 err = mmc_send_cmd(mmc, &cmd, NULL);
1046 if (err)
1047 return err;
1048
1049 mmc_set_bus_width(mmc, 4);
1050 }
1051
1052 if (mmc->card_caps & MMC_MODE_HS)
ad5fd922 1053 mmc->tran_speed = 50000000;
272cc70b 1054 else
ad5fd922 1055 mmc->tran_speed = 25000000;
272cc70b 1056 } else {
7798f6db
AF
1057 int idx;
1058
1059 /* An array of possible bus widths in order of preference */
1060 static unsigned ext_csd_bits[] = {
1061 EXT_CSD_BUS_WIDTH_8,
1062 EXT_CSD_BUS_WIDTH_4,
1063 EXT_CSD_BUS_WIDTH_1,
1064 };
1065
1066 /* An array to map CSD bus widths to host cap bits */
1067 static unsigned ext_to_hostcaps[] = {
1068 [EXT_CSD_BUS_WIDTH_4] = MMC_MODE_4BIT,
1069 [EXT_CSD_BUS_WIDTH_8] = MMC_MODE_8BIT,
1070 };
1071
1072 /* An array to map chosen bus width to an integer */
1073 static unsigned widths[] = {
1074 8, 4, 1,
1075 };
1076
1077 for (idx=0; idx < ARRAY_SIZE(ext_csd_bits); idx++) {
1078 unsigned int extw = ext_csd_bits[idx];
1079
1080 /*
1081 * Check to make sure the controller supports
1082 * this bus width, if it's more than 1
1083 */
1084 if (extw != EXT_CSD_BUS_WIDTH_1 &&
1085 !(mmc->host_caps & ext_to_hostcaps[extw]))
1086 continue;
1087
272cc70b 1088 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
7798f6db 1089 EXT_CSD_BUS_WIDTH, extw);
272cc70b
AF
1090
1091 if (err)
4137894e 1092 continue;
272cc70b 1093
7798f6db 1094 mmc_set_bus_width(mmc, widths[idx]);
4137894e
LW
1095
1096 err = mmc_send_ext_csd(mmc, test_csd);
1097 if (!err && ext_csd[EXT_CSD_PARTITIONING_SUPPORT] \
1098 == test_csd[EXT_CSD_PARTITIONING_SUPPORT]
1099 && ext_csd[EXT_CSD_ERASE_GROUP_DEF] \
1100 == test_csd[EXT_CSD_ERASE_GROUP_DEF] \
1101 && ext_csd[EXT_CSD_REV] \
1102 == test_csd[EXT_CSD_REV]
1103 && ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] \
1104 == test_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
1105 && memcmp(&ext_csd[EXT_CSD_SEC_CNT], \
1106 &test_csd[EXT_CSD_SEC_CNT], 4) == 0) {
1107
7798f6db 1108 mmc->card_caps |= ext_to_hostcaps[extw];
4137894e
LW
1109 break;
1110 }
272cc70b
AF
1111 }
1112
1113 if (mmc->card_caps & MMC_MODE_HS) {
1114 if (mmc->card_caps & MMC_MODE_HS_52MHz)
ad5fd922 1115 mmc->tran_speed = 52000000;
272cc70b 1116 else
ad5fd922
JC
1117 mmc->tran_speed = 26000000;
1118 }
272cc70b
AF
1119 }
1120
ad5fd922
JC
1121 mmc_set_clock(mmc, mmc->tran_speed);
1122
272cc70b
AF
1123 /* fill in device description */
1124 mmc->block_dev.lun = 0;
1125 mmc->block_dev.type = 0;
1126 mmc->block_dev.blksz = mmc->read_bl_len;
0472fbfd 1127 mmc->block_dev.log2blksz = LOG2(mmc->block_dev.blksz);
9b1f942c 1128 mmc->block_dev.lba = lldiv(mmc->capacity, mmc->read_bl_len);
56196826 1129#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
babce5f6
TH
1130 sprintf(mmc->block_dev.vendor, "Man %06x Snr %04x%04x",
1131 mmc->cid[0] >> 24, (mmc->cid[2] & 0xffff),
1132 (mmc->cid[3] >> 16) & 0xffff);
1133 sprintf(mmc->block_dev.product, "%c%c%c%c%c%c", mmc->cid[0] & 0xff,
1134 (mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff,
1135 (mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff,
1136 (mmc->cid[2] >> 24) & 0xff);
1137 sprintf(mmc->block_dev.revision, "%d.%d", (mmc->cid[2] >> 20) & 0xf,
1138 (mmc->cid[2] >> 16) & 0xf);
56196826
PB
1139#else
1140 mmc->block_dev.vendor[0] = 0;
1141 mmc->block_dev.product[0] = 0;
1142 mmc->block_dev.revision[0] = 0;
1143#endif
122efd43 1144#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBDISK_SUPPORT)
272cc70b 1145 init_part(&mmc->block_dev);
122efd43 1146#endif
272cc70b
AF
1147
1148 return 0;
1149}
1150
fdbb873e 1151static int mmc_send_if_cond(struct mmc *mmc)
272cc70b
AF
1152{
1153 struct mmc_cmd cmd;
1154 int err;
1155
1156 cmd.cmdidx = SD_CMD_SEND_IF_COND;
1157 /* We set the bit if the host supports voltages between 2.7 and 3.6 V */
1158 cmd.cmdarg = ((mmc->voltages & 0xff8000) != 0) << 8 | 0xaa;
1159 cmd.resp_type = MMC_RSP_R7;
272cc70b
AF
1160
1161 err = mmc_send_cmd(mmc, &cmd, NULL);
1162
1163 if (err)
1164 return err;
1165
998be3dd 1166 if ((cmd.response[0] & 0xff) != 0xaa)
272cc70b
AF
1167 return UNUSABLE_ERR;
1168 else
1169 mmc->version = SD_VERSION_2;
1170
1171 return 0;
1172}
1173
1174int mmc_register(struct mmc *mmc)
1175{
ab71188c
MN
1176 /* Setup dsr related values */
1177 mmc->dsr_imp = 0;
1178 mmc->dsr = 0xffffffff;
272cc70b
AF
1179 /* Setup the universal parts of the block interface just once */
1180 mmc->block_dev.if_type = IF_TYPE_MMC;
1181 mmc->block_dev.dev = cur_dev_num++;
1182 mmc->block_dev.removable = 1;
1183 mmc->block_dev.block_read = mmc_bread;
1184 mmc->block_dev.block_write = mmc_bwrite;
e6f99a56 1185 mmc->block_dev.block_erase = mmc_berase;
8feafcc4
JR
1186 if (!mmc->b_max)
1187 mmc->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
272cc70b
AF
1188
1189 INIT_LIST_HEAD (&mmc->link);
1190
1191 list_add_tail (&mmc->link, &mmc_devices);
1192
1193 return 0;
1194}
1195
df3fc526 1196#ifdef CONFIG_PARTITIONS
272cc70b
AF
1197block_dev_desc_t *mmc_get_dev(int dev)
1198{
1199 struct mmc *mmc = find_mmc_device(dev);
6bb4b4bc 1200 if (!mmc || mmc_init(mmc))
40242bc3 1201 return NULL;
272cc70b 1202
40242bc3 1203 return &mmc->block_dev;
272cc70b 1204}
df3fc526 1205#endif
272cc70b 1206
e9550449 1207int mmc_start_init(struct mmc *mmc)
272cc70b 1208{
afd5932b 1209 int err;
272cc70b 1210
ab769f22
PA
1211 /* we pretend there's no card when init is NULL */
1212 if (mmc_getcd(mmc) == 0 || mmc->ops->init == NULL) {
48972d90 1213 mmc->has_init = 0;
56196826 1214#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
48972d90 1215 printf("MMC: no card present\n");
56196826 1216#endif
48972d90
TR
1217 return NO_CARD_ERR;
1218 }
1219
bc897b1d
LW
1220 if (mmc->has_init)
1221 return 0;
1222
ab769f22
PA
1223 /* made sure it's not NULL earlier */
1224 err = mmc->ops->init(mmc);
272cc70b
AF
1225
1226 if (err)
1227 return err;
1228
b86b85e2
IY
1229 mmc_set_bus_width(mmc, 1);
1230 mmc_set_clock(mmc, 1);
1231
272cc70b
AF
1232 /* Reset the Card */
1233 err = mmc_go_idle(mmc);
1234
1235 if (err)
1236 return err;
1237
bc897b1d
LW
1238 /* The internal partition reset to user partition(0) at every CMD0*/
1239 mmc->part_num = 0;
1240
272cc70b 1241 /* Test for SD version 2 */
afd5932b 1242 err = mmc_send_if_cond(mmc);
272cc70b 1243
272cc70b
AF
1244 /* Now try to get the SD card's operating condition */
1245 err = sd_send_op_cond(mmc);
1246
1247 /* If the command timed out, we check for an MMC card */
1248 if (err == TIMEOUT) {
1249 err = mmc_send_op_cond(mmc);
1250
e9550449 1251 if (err && err != IN_PROGRESS) {
56196826 1252#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
272cc70b 1253 printf("Card did not respond to voltage select!\n");
56196826 1254#endif
272cc70b
AF
1255 return UNUSABLE_ERR;
1256 }
1257 }
1258
e9550449
CLC
1259 if (err == IN_PROGRESS)
1260 mmc->init_in_progress = 1;
1261
1262 return err;
1263}
1264
1265static int mmc_complete_init(struct mmc *mmc)
1266{
1267 int err = 0;
1268
1269 if (mmc->op_cond_pending)
1270 err = mmc_complete_op_cond(mmc);
1271
1272 if (!err)
1273 err = mmc_startup(mmc);
bc897b1d
LW
1274 if (err)
1275 mmc->has_init = 0;
1276 else
1277 mmc->has_init = 1;
e9550449
CLC
1278 mmc->init_in_progress = 0;
1279 return err;
1280}
1281
1282int mmc_init(struct mmc *mmc)
1283{
1284 int err = IN_PROGRESS;
1285 unsigned start = get_timer(0);
1286
1287 if (mmc->has_init)
1288 return 0;
1289 if (!mmc->init_in_progress)
1290 err = mmc_start_init(mmc);
1291
1292 if (!err || err == IN_PROGRESS)
1293 err = mmc_complete_init(mmc);
1294 debug("%s: %d, time %lu\n", __func__, err, get_timer(start));
bc897b1d 1295 return err;
272cc70b
AF
1296}
1297
ab71188c
MN
1298int mmc_set_dsr(struct mmc *mmc, u16 val)
1299{
1300 mmc->dsr = val;
1301 return 0;
1302}
1303
272cc70b
AF
1304/*
1305 * CPU and board-specific MMC initializations. Aliased function
1306 * signals caller to move on
1307 */
1308static int __def_mmc_init(bd_t *bis)
1309{
1310 return -1;
1311}
1312
f9a109b3
PT
1313int cpu_mmc_init(bd_t *bis) __attribute__((weak, alias("__def_mmc_init")));
1314int board_mmc_init(bd_t *bis) __attribute__((weak, alias("__def_mmc_init")));
272cc70b 1315
56196826
PB
1316#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
1317
272cc70b
AF
1318void print_mmc_devices(char separator)
1319{
1320 struct mmc *m;
1321 struct list_head *entry;
1322
1323 list_for_each(entry, &mmc_devices) {
1324 m = list_entry(entry, struct mmc, link);
1325
1326 printf("%s: %d", m->name, m->block_dev.dev);
1327
1328 if (entry->next != &mmc_devices)
1329 printf("%c ", separator);
1330 }
1331
1332 printf("\n");
1333}
1334
56196826
PB
1335#else
1336void print_mmc_devices(char separator) { }
1337#endif
1338
ea6ebe21
LW
1339int get_mmc_num(void)
1340{
1341 return cur_dev_num;
1342}
1343
e9550449
CLC
1344void mmc_set_preinit(struct mmc *mmc, int preinit)
1345{
1346 mmc->preinit = preinit;
1347}
1348
1349static void do_preinit(void)
1350{
1351 struct mmc *m;
1352 struct list_head *entry;
1353
1354 list_for_each(entry, &mmc_devices) {
1355 m = list_entry(entry, struct mmc, link);
1356
1357 if (m->preinit)
1358 mmc_start_init(m);
1359 }
1360}
1361
1362
272cc70b
AF
1363int mmc_initialize(bd_t *bis)
1364{
1365 INIT_LIST_HEAD (&mmc_devices);
1366 cur_dev_num = 0;
1367
1368 if (board_mmc_init(bis) < 0)
1369 cpu_mmc_init(bis);
1370
bb0dc108 1371#ifndef CONFIG_SPL_BUILD
272cc70b 1372 print_mmc_devices(',');
bb0dc108 1373#endif
272cc70b 1374
e9550449 1375 do_preinit();
272cc70b
AF
1376 return 0;
1377}
3690d6d6
A
1378
1379#ifdef CONFIG_SUPPORT_EMMC_BOOT
1380/*
1381 * This function changes the size of boot partition and the size of rpmb
1382 * partition present on EMMC devices.
1383 *
1384 * Input Parameters:
1385 * struct *mmc: pointer for the mmc device strcuture
1386 * bootsize: size of boot partition
1387 * rpmbsize: size of rpmb partition
1388 *
1389 * Returns 0 on success.
1390 */
1391
1392int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize,
1393 unsigned long rpmbsize)
1394{
1395 int err;
1396 struct mmc_cmd cmd;
1397
1398 /* Only use this command for raw EMMC moviNAND. Enter backdoor mode */
1399 cmd.cmdidx = MMC_CMD_RES_MAN;
1400 cmd.resp_type = MMC_RSP_R1b;
1401 cmd.cmdarg = MMC_CMD62_ARG1;
1402
1403 err = mmc_send_cmd(mmc, &cmd, NULL);
1404 if (err) {
1405 debug("mmc_boot_partition_size_change: Error1 = %d\n", err);
1406 return err;
1407 }
1408
1409 /* Boot partition changing mode */
1410 cmd.cmdidx = MMC_CMD_RES_MAN;
1411 cmd.resp_type = MMC_RSP_R1b;
1412 cmd.cmdarg = MMC_CMD62_ARG2;
1413
1414 err = mmc_send_cmd(mmc, &cmd, NULL);
1415 if (err) {
1416 debug("mmc_boot_partition_size_change: Error2 = %d\n", err);
1417 return err;
1418 }
1419 /* boot partition size is multiple of 128KB */
1420 bootsize = (bootsize * 1024) / 128;
1421
1422 /* Arg: boot partition size */
1423 cmd.cmdidx = MMC_CMD_RES_MAN;
1424 cmd.resp_type = MMC_RSP_R1b;
1425 cmd.cmdarg = bootsize;
1426
1427 err = mmc_send_cmd(mmc, &cmd, NULL);
1428 if (err) {
1429 debug("mmc_boot_partition_size_change: Error3 = %d\n", err);
1430 return err;
1431 }
1432 /* RPMB partition size is multiple of 128KB */
1433 rpmbsize = (rpmbsize * 1024) / 128;
1434 /* Arg: RPMB partition size */
1435 cmd.cmdidx = MMC_CMD_RES_MAN;
1436 cmd.resp_type = MMC_RSP_R1b;
1437 cmd.cmdarg = rpmbsize;
1438
1439 err = mmc_send_cmd(mmc, &cmd, NULL);
1440 if (err) {
1441 debug("mmc_boot_partition_size_change: Error4 = %d\n", err);
1442 return err;
1443 }
1444 return 0;
1445}
1446
5a99b9de
TR
1447/*
1448 * Modify EXT_CSD[177] which is BOOT_BUS_WIDTH
1449 * based on the passed in values for BOOT_BUS_WIDTH, RESET_BOOT_BUS_WIDTH
1450 * and BOOT_MODE.
1451 *
1452 * Returns 0 on success.
1453 */
1454int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode)
1455{
1456 int err;
1457
1458 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BOOT_BUS_WIDTH,
1459 EXT_CSD_BOOT_BUS_WIDTH_MODE(mode) |
1460 EXT_CSD_BOOT_BUS_WIDTH_RESET(reset) |
1461 EXT_CSD_BOOT_BUS_WIDTH_WIDTH(width));
1462
1463 if (err)
1464 return err;
1465 return 0;
1466}
1467
792970b0
TR
1468/*
1469 * Modify EXT_CSD[179] which is PARTITION_CONFIG (formerly BOOT_CONFIG)
1470 * based on the passed in values for BOOT_ACK, BOOT_PARTITION_ENABLE and
1471 * PARTITION_ACCESS.
1472 *
1473 * Returns 0 on success.
1474 */
1475int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access)
1476{
1477 int err;
1478
1479 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF,
1480 EXT_CSD_BOOT_ACK(ack) |
1481 EXT_CSD_BOOT_PART_NUM(part_num) |
1482 EXT_CSD_PARTITION_ACCESS(access));
1483
1484 if (err)
1485 return err;
1486 return 0;
1487}
3690d6d6 1488#endif
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