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mmc: Restructure polling loops to avoid extra delays
[u-boot.git] / drivers / mmc / mmc.c
CommitLineData
272cc70b
AF		 1/*
2 * Copyright 2008, Freescale Semiconductor, Inc
3 * Andy Fleming
4 *
5 * Based vaguely on the Linux code
6 *
1a459660 7 * SPDX-License-Identifier: GPL-2.0+
272cc70b
AF		 8 */
9
10#include <config.h>
11#include <common.h>
12#include <command.h>
d4622df3 13#include <errno.h>
272cc70b
AF		 14#include <mmc.h>
15#include <part.h>
16#include <malloc.h>
17#include <linux/list.h>
9b1f942c 18#include <div64.h>
da61fa5f 19#include "mmc_private.h"
272cc70b
AF		 20
21static struct list_head mmc_devices;
22static int cur_dev_num = -1;
23
750121c3 24__weak int board_mmc_getwp(struct mmc *mmc)
d23d8d7e
NK		 25{
26 return -1;
27}
28
29int mmc_getwp(struct mmc *mmc)
30{
31 int wp;
32
33 wp = board_mmc_getwp(mmc);
34
d4e1da4e 35 if (wp < 0) {
93bfd616
PA		 36 if (mmc->cfg->ops->getwp)
37 wp = mmc->cfg->ops->getwp(mmc);
d4e1da4e
PK		 38 else
39 wp = 0;
40 }
d23d8d7e
NK		 41
42 return wp;
43}
44
cee9ab7c
JH		 45__weak int board_mmc_getcd(struct mmc *mmc)
46{
11fdade2
SB		 47 return -1;
48}
49
da61fa5f 50int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
272cc70b 51{
5db2fe3a 52 int ret;
8635ff9e 53
8635ff9e 54#ifdef CONFIG_MMC_TRACE
5db2fe3a
RR		 55 int i;
56 u8 *ptr;
57
58 printf("CMD_SEND:%d\n", cmd->cmdidx);
59 printf("\t\tARG\t\t\t 0x%08X\n", cmd->cmdarg);
93bfd616 60 ret = mmc->cfg->ops->send_cmd(mmc, cmd, data);
5db2fe3a
RR		 61 switch (cmd->resp_type) {
62 case MMC_RSP_NONE:
63 printf("\t\tMMC_RSP_NONE\n");
64 break;
65 case MMC_RSP_R1:
66 printf("\t\tMMC_RSP_R1,5,6,7 \t 0x%08X \n",
67 cmd->response[0]);
68 break;
69 case MMC_RSP_R1b:
70 printf("\t\tMMC_RSP_R1b\t\t 0x%08X \n",
71 cmd->response[0]);
72 break;
73 case MMC_RSP_R2:
74 printf("\t\tMMC_RSP_R2\t\t 0x%08X \n",
75 cmd->response[0]);
76 printf("\t\t \t\t 0x%08X \n",
77 cmd->response[1]);
78 printf("\t\t \t\t 0x%08X \n",
79 cmd->response[2]);
80 printf("\t\t \t\t 0x%08X \n",
81 cmd->response[3]);
82 printf("\n");
83 printf("\t\t\t\t\tDUMPING DATA\n");
84 for (i = 0; i < 4; i++) {
85 int j;
86 printf("\t\t\t\t\t%03d - ", i*4);
146bec79 87 ptr = (u8 *)&cmd->response[i];
5db2fe3a
RR		 88 ptr += 3;
89 for (j = 0; j < 4; j++)
90 printf("%02X ", *ptr--);
91 printf("\n");
92 }
93 break;
94 case MMC_RSP_R3:
95 printf("\t\tMMC_RSP_R3,4\t\t 0x%08X \n",
96 cmd->response[0]);
97 break;
98 default:
99 printf("\t\tERROR MMC rsp not supported\n");
100 break;
101 }
5db2fe3a 102#else
93bfd616 103 ret = mmc->cfg->ops->send_cmd(mmc, cmd, data);
5db2fe3a 104#endif
8635ff9e 105 return ret;
272cc70b
AF		 106}
107
da61fa5f 108int mmc_send_status(struct mmc *mmc, int timeout)
5d4fc8d9
RR		 109{
110 struct mmc_cmd cmd;
d617c426 111 int err, retries = 5;
5d4fc8d9
RR		 112#ifdef CONFIG_MMC_TRACE
113 int status;
114#endif
115
116 cmd.cmdidx = MMC_CMD_SEND_STATUS;
117 cmd.resp_type = MMC_RSP_R1;
aaf3d41a
MV		 118 if (!mmc_host_is_spi(mmc))
119 cmd.cmdarg = mmc->rca << 16;
5d4fc8d9 120
1677eef4 121 while (1) {
5d4fc8d9 122 err = mmc_send_cmd(mmc, &cmd, NULL);
d617c426
JK		 123 if (!err) {
124 if ((cmd.response[0] & MMC_STATUS_RDY_FOR_DATA) &&
125 (cmd.response[0] & MMC_STATUS_CURR_STATE) !=
126 MMC_STATE_PRG)
127 break;
128 else if (cmd.response[0] & MMC_STATUS_MASK) {
56196826 129#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
d617c426
JK		 130 printf("Status Error: 0x%08X\n",
131 cmd.response[0]);
56196826 132#endif
d617c426
JK		 133 return COMM_ERR;
134 }
135 } else if (--retries < 0)
5d4fc8d9 136 return err;
5d4fc8d9 137
1677eef4
AG		 138 if (timeout-- <= 0)
139 break;
5d4fc8d9 140
1677eef4
AG		 141 udelay(1000);
142 }
5d4fc8d9 143
5db2fe3a
RR		 144#ifdef CONFIG_MMC_TRACE
145 status = (cmd.response[0] & MMC_STATUS_CURR_STATE) >> 9;
146 printf("CURR STATE:%d\n", status);
147#endif
5b0c942f 148 if (timeout <= 0) {
56196826 149#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
5d4fc8d9 150 printf("Timeout waiting card ready\n");
56196826 151#endif
5d4fc8d9
RR		 152 return TIMEOUT;
153 }
6b2221b0
AG		 154 if (cmd.response[0] & MMC_STATUS_SWITCH_ERROR)
155 return SWITCH_ERR;
5d4fc8d9
RR		 156
157 return 0;
158}
159
da61fa5f 160int mmc_set_blocklen(struct mmc *mmc, int len)
272cc70b
AF		 161{
162 struct mmc_cmd cmd;
163
786e8f81 164 if (mmc->ddr_mode)
d22e3d46
JC		 165 return 0;
166
272cc70b
AF		 167 cmd.cmdidx = MMC_CMD_SET_BLOCKLEN;
168 cmd.resp_type = MMC_RSP_R1;
169 cmd.cmdarg = len;
272cc70b
AF		 170
171 return mmc_send_cmd(mmc, &cmd, NULL);
172}
173
174struct mmc *find_mmc_device(int dev_num)
175{
176 struct mmc *m;
177 struct list_head *entry;
178
179 list_for_each(entry, &mmc_devices) {
180 m = list_entry(entry, struct mmc, link);
181
182 if (m->block_dev.dev == dev_num)
183 return m;
184 }
185
56196826 186#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
272cc70b 187 printf("MMC Device %d not found\n", dev_num);
56196826 188#endif
272cc70b
AF		 189
190 return NULL;
191}
192
ff8fef56 193static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start,
fdbb873e 194 lbaint_t blkcnt)
272cc70b
AF		 195{
196 struct mmc_cmd cmd;
197 struct mmc_data data;
198
4a1a06bc
AS		 199 if (blkcnt > 1)
200 cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK;
201 else
202 cmd.cmdidx = MMC_CMD_READ_SINGLE_BLOCK;
272cc70b
AF		 203
204 if (mmc->high_capacity)
4a1a06bc 205 cmd.cmdarg = start;
272cc70b 206 else
4a1a06bc 207 cmd.cmdarg = start * mmc->read_bl_len;
272cc70b
AF		 208
209 cmd.resp_type = MMC_RSP_R1;
272cc70b
AF		 210
211 data.dest = dst;
4a1a06bc 212 data.blocks = blkcnt;
272cc70b
AF		 213 data.blocksize = mmc->read_bl_len;
214 data.flags = MMC_DATA_READ;
215
4a1a06bc
AS		 216 if (mmc_send_cmd(mmc, &cmd, &data))
217 return 0;
272cc70b 218
4a1a06bc
AS		 219 if (blkcnt > 1) {
220 cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
221 cmd.cmdarg = 0;
222 cmd.resp_type = MMC_RSP_R1b;
4a1a06bc 223 if (mmc_send_cmd(mmc, &cmd, NULL)) {
56196826 224#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
4a1a06bc 225 printf("mmc fail to send stop cmd\n");
56196826 226#endif
4a1a06bc
AS		 227 return 0;
228 }
272cc70b
AF		 229 }
230
4a1a06bc 231 return blkcnt;
272cc70b
AF		 232}
233
ff8fef56 234static ulong mmc_bread(int dev_num, lbaint_t start, lbaint_t blkcnt, void *dst)
272cc70b 235{
4a1a06bc
AS		 236 lbaint_t cur, blocks_todo = blkcnt;
237
238 if (blkcnt == 0)
239 return 0;
272cc70b 240
4a1a06bc 241 struct mmc *mmc = find_mmc_device(dev_num);
272cc70b
AF		 242 if (!mmc)
243 return 0;
244
d2bf29e3 245 if ((start + blkcnt) > mmc->block_dev.lba) {
56196826 246#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
ff8fef56 247 printf("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n",
d2bf29e3 248 start + blkcnt, mmc->block_dev.lba);
56196826 249#endif
d2bf29e3
LW		 250 return 0;
251 }
272cc70b 252
4a1a06bc 253 if (mmc_set_blocklen(mmc, mmc->read_bl_len))
272cc70b 254 return 0;
272cc70b 255
4a1a06bc 256 do {
93bfd616
PA		 257 cur = (blocks_todo > mmc->cfg->b_max) ?
258 mmc->cfg->b_max : blocks_todo;
4a1a06bc
AS		 259 if(mmc_read_blocks(mmc, dst, start, cur) != cur)
260 return 0;
261 blocks_todo -= cur;
262 start += cur;
263 dst += cur * mmc->read_bl_len;
264 } while (blocks_todo > 0);
272cc70b
AF		 265
266 return blkcnt;
267}
268
fdbb873e 269static int mmc_go_idle(struct mmc *mmc)
272cc70b
AF		 270{
271 struct mmc_cmd cmd;
272 int err;
273
274 udelay(1000);
275
276 cmd.cmdidx = MMC_CMD_GO_IDLE_STATE;
277 cmd.cmdarg = 0;
278 cmd.resp_type = MMC_RSP_NONE;
272cc70b
AF		 279
280 err = mmc_send_cmd(mmc, &cmd, NULL);
281
282 if (err)
283 return err;
284
285 udelay(2000);
286
287 return 0;
288}
289
fdbb873e 290static int sd_send_op_cond(struct mmc *mmc)
272cc70b
AF		 291{
292 int timeout = 1000;
293 int err;
294 struct mmc_cmd cmd;
295
1677eef4 296 while (1) {
272cc70b
AF		 297 cmd.cmdidx = MMC_CMD_APP_CMD;
298 cmd.resp_type = MMC_RSP_R1;
299 cmd.cmdarg = 0;
272cc70b
AF		 300
301 err = mmc_send_cmd(mmc, &cmd, NULL);
302
303 if (err)
304 return err;
305
306 cmd.cmdidx = SD_CMD_APP_SEND_OP_COND;
307 cmd.resp_type = MMC_RSP_R3;
250de12b
SB		 308
309 /*
310 * Most cards do not answer if some reserved bits
311 * in the ocr are set. However, Some controller
312 * can set bit 7 (reserved for low voltages), but
313 * how to manage low voltages SD card is not yet
314 * specified.
315 */
d52ebf10 316 cmd.cmdarg = mmc_host_is_spi(mmc) ? 0 :
93bfd616 317 (mmc->cfg->voltages & 0xff8000);
272cc70b
AF		 318
319 if (mmc->version == SD_VERSION_2)
320 cmd.cmdarg |= OCR_HCS;
321
322 err = mmc_send_cmd(mmc, &cmd, NULL);
323
324 if (err)
325 return err;
326
1677eef4
AG		 327 if (cmd.response[0] & OCR_BUSY)
328 break;
329
330 if (timeout-- <= 0)
331 return UNUSABLE_ERR;
272cc70b 332
1677eef4
AG		 333 udelay(1000);
334 }
272cc70b
AF		 335
336 if (mmc->version != SD_VERSION_2)
337 mmc->version = SD_VERSION_1_0;
338
d52ebf10
TC		 339 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
340 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
341 cmd.resp_type = MMC_RSP_R3;
342 cmd.cmdarg = 0;
d52ebf10
TC		 343
344 err = mmc_send_cmd(mmc, &cmd, NULL);
345
346 if (err)
347 return err;
348 }
349
998be3dd 350 mmc->ocr = cmd.response[0];
272cc70b
AF		 351
352 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
353 mmc->rca = 0;
354
355 return 0;
356}
357
5289b535 358static int mmc_send_op_cond_iter(struct mmc *mmc, int use_arg)
272cc70b 359{
5289b535 360 struct mmc_cmd cmd;
272cc70b
AF		 361 int err;
362
5289b535
AG		 363 cmd.cmdidx = MMC_CMD_SEND_OP_COND;
364 cmd.resp_type = MMC_RSP_R3;
365 cmd.cmdarg = 0;
e9550449 366 if (use_arg && !mmc_host_is_spi(mmc)) {
5289b535 367 cmd.cmdarg =
93bfd616 368 (mmc->cfg->voltages &
a626c8d4
AG		 369 (mmc->ocr & OCR_VOLTAGE_MASK)) |
370 (mmc->ocr & OCR_ACCESS_MODE);
e9550449 371
93bfd616 372 if (mmc->cfg->host_caps & MMC_MODE_HC)
5289b535 373 cmd.cmdarg |= OCR_HCS;
e9550449 374 }
5289b535 375 err = mmc_send_cmd(mmc, &cmd, NULL);
e9550449
CLC		 376 if (err)
377 return err;
5289b535 378 mmc->ocr = cmd.response[0];
e9550449
CLC		 379 return 0;
380}
381
750121c3 382static int mmc_send_op_cond(struct mmc *mmc)
e9550449 383{
e9550449
CLC		 384 int err, i;
385
272cc70b
AF		 386 /* Some cards seem to need this */
387 mmc_go_idle(mmc);
388
31cacbab 389 /* Asking to the card its capabilities */
e9550449
CLC		 390 mmc->op_cond_pending = 1;
391 for (i = 0; i < 2; i++) {
5289b535 392 err = mmc_send_op_cond_iter(mmc, i != 0);
e9550449
CLC		 393 if (err)
394 return err;
cd6881b5 395
e9550449 396 /* exit if not busy (flag seems to be inverted) */
a626c8d4 397 if (mmc->ocr & OCR_BUSY)
e9550449
CLC		 398 return 0;
399 }
400 return IN_PROGRESS;
401}
cd6881b5 402
750121c3 403static int mmc_complete_op_cond(struct mmc *mmc)
e9550449
CLC		 404{
405 struct mmc_cmd cmd;
406 int timeout = 1000;
407 uint start;
408 int err;
cd6881b5 409
e9550449 410 mmc->op_cond_pending = 0;
cc17c01f
AG		 411 if (!(mmc->ocr & OCR_BUSY)) {
412 start = get_timer(0);
1677eef4 413 while (1) {
cc17c01f
AG		 414 err = mmc_send_op_cond_iter(mmc, 1);
415 if (err)
416 return err;
1677eef4
AG		 417 if (mmc->ocr & OCR_BUSY)
418 break;
cc17c01f
AG		 419 if (get_timer(start) > timeout)
420 return UNUSABLE_ERR;
421 udelay(100);
1677eef4 422 }
cc17c01f 423 }
272cc70b 424
d52ebf10
TC		 425 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
426 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
427 cmd.resp_type = MMC_RSP_R3;
428 cmd.cmdarg = 0;
d52ebf10
TC		 429
430 err = mmc_send_cmd(mmc, &cmd, NULL);
431
432 if (err)
433 return err;
a626c8d4
AG		 434
435 mmc->ocr = cmd.response[0];
d52ebf10
TC		 436 }
437
272cc70b 438 mmc->version = MMC_VERSION_UNKNOWN;
272cc70b
AF		 439
440 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
def816a2 441 mmc->rca = 1;
272cc70b
AF		 442
443 return 0;
444}
445
446
fdbb873e 447static int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd)
272cc70b
AF		 448{
449 struct mmc_cmd cmd;
450 struct mmc_data data;
451 int err;
452
453 /* Get the Card Status Register */
454 cmd.cmdidx = MMC_CMD_SEND_EXT_CSD;
455 cmd.resp_type = MMC_RSP_R1;
456 cmd.cmdarg = 0;
272cc70b 457
cdfd1ac6 458 data.dest = (char *)ext_csd;
272cc70b 459 data.blocks = 1;
8bfa195e 460 data.blocksize = MMC_MAX_BLOCK_LEN;
272cc70b
AF		 461 data.flags = MMC_DATA_READ;
462
463 err = mmc_send_cmd(mmc, &cmd, &data);
464
465 return err;
466}
467
468
fdbb873e 469static int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value)
272cc70b
AF		 470{
471 struct mmc_cmd cmd;
5d4fc8d9
RR		 472 int timeout = 1000;
473 int ret;
272cc70b
AF		 474
475 cmd.cmdidx = MMC_CMD_SWITCH;
476 cmd.resp_type = MMC_RSP_R1b;
477 cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) |
5d4fc8d9
RR		 478 (index << 16) |
479 (value << 8);
272cc70b 480
5d4fc8d9
RR		 481 ret = mmc_send_cmd(mmc, &cmd, NULL);
482
483 /* Waiting for the ready status */
93ad0d18
JK		 484 if (!ret)
485 ret = mmc_send_status(mmc, timeout);
5d4fc8d9
RR		 486
487 return ret;
488
272cc70b
AF		 489}
490
fdbb873e 491static int mmc_change_freq(struct mmc *mmc)
272cc70b 492{
8bfa195e 493 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
272cc70b
AF		 494 char cardtype;
495 int err;
496
fc5b32fb 497 mmc->card_caps = 0;
272cc70b 498
d52ebf10
TC		 499 if (mmc_host_is_spi(mmc))
500 return 0;
501
272cc70b
AF		 502 /* Only version 4 supports high-speed */
503 if (mmc->version < MMC_VERSION_4)
504 return 0;
505
fc5b32fb
AG		 506 mmc->card_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT;
507
272cc70b
AF		 508 err = mmc_send_ext_csd(mmc, ext_csd);
509
510 if (err)
511 return err;
512
0560db18 513 cardtype = ext_csd[EXT_CSD_CARD_TYPE] & 0xf;
272cc70b
AF		 514
515 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING, 1);
516
517 if (err)
6b2221b0 518 return err == SWITCH_ERR ? 0 : err;
272cc70b
AF		 519
520 /* Now check to see that it worked */
521 err = mmc_send_ext_csd(mmc, ext_csd);
522
523 if (err)
524 return err;
525
526 /* No high-speed support */
0560db18 527 if (!ext_csd[EXT_CSD_HS_TIMING])
272cc70b
AF		 528 return 0;
529
530 /* High Speed is set, there are two types: 52MHz and 26MHz */
d22e3d46 531 if (cardtype & EXT_CSD_CARD_TYPE_52) {
201d5ac4 532 if (cardtype & EXT_CSD_CARD_TYPE_DDR_1_8V)
d22e3d46 533 mmc->card_caps |= MMC_MODE_DDR_52MHz;
272cc70b 534 mmc->card_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
d22e3d46 535 } else {
272cc70b 536 mmc->card_caps |= MMC_MODE_HS;
d22e3d46 537 }
272cc70b
AF		 538
539 return 0;
540}
541
f866a46d
SW		 542static int mmc_set_capacity(struct mmc *mmc, int part_num)
543{
544 switch (part_num) {
545 case 0:
546 mmc->capacity = mmc->capacity_user;
547 break;
548 case 1:
549 case 2:
550 mmc->capacity = mmc->capacity_boot;
551 break;
552 case 3:
553 mmc->capacity = mmc->capacity_rpmb;
554 break;
555 case 4:
556 case 5:
557 case 6:
558 case 7:
559 mmc->capacity = mmc->capacity_gp[part_num - 4];
560 break;
561 default:
562 return -1;
563 }
564
565 mmc->block_dev.lba = lldiv(mmc->capacity, mmc->read_bl_len);
566
567 return 0;
568}
569
d2356284
SW		 570int mmc_select_hwpart(int dev_num, int hwpart)
571{
572 struct mmc *mmc = find_mmc_device(dev_num);
573 int ret;
574
575 if (!mmc)
d4622df3 576 return -ENODEV;
d2356284
SW		 577
578 if (mmc->part_num == hwpart)
579 return 0;
580
581 if (mmc->part_config == MMCPART_NOAVAILABLE) {
582 printf("Card doesn't support part_switch\n");
d4622df3 583 return -EMEDIUMTYPE;
d2356284
SW		 584 }
585
586 ret = mmc_switch_part(dev_num, hwpart);
587 if (ret)
d4622df3 588 return ret;
d2356284
SW		 589
590 mmc->part_num = hwpart;
591
592 return 0;
593}
594
595
bc897b1d
LW		 596int mmc_switch_part(int dev_num, unsigned int part_num)
597{
598 struct mmc *mmc = find_mmc_device(dev_num);
f866a46d 599 int ret;
bc897b1d
LW		 600
601 if (!mmc)
602 return -1;
603
f866a46d
SW		 604 ret = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF,
605 (mmc->part_config & ~PART_ACCESS_MASK)
606 | (part_num & PART_ACCESS_MASK));
f866a46d 607
6dc93e70
PB		 608 /*
609 * Set the capacity if the switch succeeded or was intended
610 * to return to representing the raw device.
611 */
612 if ((ret == 0) || ((ret == -ENODEV) && (part_num == 0)))
613 ret = mmc_set_capacity(mmc, part_num);
614
615 return ret;
bc897b1d
LW		 616}
617
ac9da0e0
DSC		 618int mmc_hwpart_config(struct mmc *mmc,
619 const struct mmc_hwpart_conf *conf,
620 enum mmc_hwpart_conf_mode mode)
621{
622 u8 part_attrs = 0;
623 u32 enh_size_mult;
624 u32 enh_start_addr;
625 u32 gp_size_mult[4];
626 u32 max_enh_size_mult;
627 u32 tot_enh_size_mult = 0;
8dda5b0e 628 u8 wr_rel_set;
ac9da0e0
DSC		 629 int i, pidx, err;
630 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
631
632 if (mode < MMC_HWPART_CONF_CHECK || mode > MMC_HWPART_CONF_COMPLETE)
633 return -EINVAL;
634
635 if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4_41)) {
636 printf("eMMC >= 4.4 required for enhanced user data area\n");
637 return -EMEDIUMTYPE;
638 }
639
640 if (!(mmc->part_support & PART_SUPPORT)) {
641 printf("Card does not support partitioning\n");
642 return -EMEDIUMTYPE;
643 }
644
645 if (!mmc->hc_wp_grp_size) {
646 printf("Card does not define HC WP group size\n");
647 return -EMEDIUMTYPE;
648 }
649
650 /* check partition alignment and total enhanced size */
651 if (conf->user.enh_size) {
652 if (conf->user.enh_size % mmc->hc_wp_grp_size ||
653 conf->user.enh_start % mmc->hc_wp_grp_size) {
654 printf("User data enhanced area not HC WP group "
655 "size aligned\n");
656 return -EINVAL;
657 }
658 part_attrs |= EXT_CSD_ENH_USR;
659 enh_size_mult = conf->user.enh_size / mmc->hc_wp_grp_size;
660 if (mmc->high_capacity) {
661 enh_start_addr = conf->user.enh_start;
662 } else {
663 enh_start_addr = (conf->user.enh_start << 9);
664 }
665 } else {
666 enh_size_mult = 0;
667 enh_start_addr = 0;
668 }
669 tot_enh_size_mult += enh_size_mult;
670
671 for (pidx = 0; pidx < 4; pidx++) {
672 if (conf->gp_part[pidx].size % mmc->hc_wp_grp_size) {
673 printf("GP%i partition not HC WP group size "
674 "aligned\n", pidx+1);
675 return -EINVAL;
676 }
677 gp_size_mult[pidx] = conf->gp_part[pidx].size / mmc->hc_wp_grp_size;
678 if (conf->gp_part[pidx].size && conf->gp_part[pidx].enhanced) {
679 part_attrs |= EXT_CSD_ENH_GP(pidx);
680 tot_enh_size_mult += gp_size_mult[pidx];
681 }
682 }
683
684 if (part_attrs && ! (mmc->part_support & ENHNCD_SUPPORT)) {
685 printf("Card does not support enhanced attribute\n");
686 return -EMEDIUMTYPE;
687 }
688
689 err = mmc_send_ext_csd(mmc, ext_csd);
690 if (err)
691 return err;
692
693 max_enh_size_mult =
694 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+2] << 16) +
695 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+1] << 8) +
696 ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT];
697 if (tot_enh_size_mult > max_enh_size_mult) {
698 printf("Total enhanced size exceeds maximum (%u > %u)\n",
699 tot_enh_size_mult, max_enh_size_mult);
700 return -EMEDIUMTYPE;
701 }
702
8dda5b0e
DSC		 703 /* The default value of EXT_CSD_WR_REL_SET is device
704 * dependent, the values can only be changed if the
705 * EXT_CSD_HS_CTRL_REL bit is set. The values can be
706 * changed only once and before partitioning is completed. */
707 wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
708 if (conf->user.wr_rel_change) {
709 if (conf->user.wr_rel_set)
710 wr_rel_set |= EXT_CSD_WR_DATA_REL_USR;
711 else
712 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_USR;
713 }
714 for (pidx = 0; pidx < 4; pidx++) {
715 if (conf->gp_part[pidx].wr_rel_change) {
716 if (conf->gp_part[pidx].wr_rel_set)
717 wr_rel_set |= EXT_CSD_WR_DATA_REL_GP(pidx);
718 else
719 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_GP(pidx);
720 }
721 }
722
723 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET] &&
724 !(ext_csd[EXT_CSD_WR_REL_PARAM] & EXT_CSD_HS_CTRL_REL)) {
725 puts("Card does not support host controlled partition write "
726 "reliability settings\n");
727 return -EMEDIUMTYPE;
728 }
729
ac9da0e0
DSC		 730 if (ext_csd[EXT_CSD_PARTITION_SETTING] &
731 EXT_CSD_PARTITION_SETTING_COMPLETED) {
732 printf("Card already partitioned\n");
733 return -EPERM;
734 }
735
736 if (mode == MMC_HWPART_CONF_CHECK)
737 return 0;
738
739 /* Partitioning requires high-capacity size definitions */
740 if (!(ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01)) {
741 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
742 EXT_CSD_ERASE_GROUP_DEF, 1);
743
744 if (err)
745 return err;
746
747 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
748
749 /* update erase group size to be high-capacity */
750 mmc->erase_grp_size =
751 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
752
753 }
754
755 /* all OK, write the configuration */
756 for (i = 0; i < 4; i++) {
757 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
758 EXT_CSD_ENH_START_ADDR+i,
759 (enh_start_addr >> (i*8)) & 0xFF);
760 if (err)
761 return err;
762 }
763 for (i = 0; i < 3; i++) {
764 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
765 EXT_CSD_ENH_SIZE_MULT+i,
766 (enh_size_mult >> (i*8)) & 0xFF);
767 if (err)
768 return err;
769 }
770 for (pidx = 0; pidx < 4; pidx++) {
771 for (i = 0; i < 3; i++) {
772 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
773 EXT_CSD_GP_SIZE_MULT+pidx*3+i,
774 (gp_size_mult[pidx] >> (i*8)) & 0xFF);
775 if (err)
776 return err;
777 }
778 }
779 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
780 EXT_CSD_PARTITIONS_ATTRIBUTE, part_attrs);
781 if (err)
782 return err;
783
784 if (mode == MMC_HWPART_CONF_SET)
785 return 0;
786
8dda5b0e
DSC		 787 /* The WR_REL_SET is a write-once register but shall be
788 * written before setting PART_SETTING_COMPLETED. As it is
789 * write-once we can only write it when completing the
790 * partitioning. */
791 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET]) {
792 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
793 EXT_CSD_WR_REL_SET, wr_rel_set);
794 if (err)
795 return err;
796 }
797
ac9da0e0
DSC		 798 /* Setting PART_SETTING_COMPLETED confirms the partition
799 * configuration but it only becomes effective after power
800 * cycle, so we do not adjust the partition related settings
801 * in the mmc struct. */
802
803 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
804 EXT_CSD_PARTITION_SETTING,
805 EXT_CSD_PARTITION_SETTING_COMPLETED);
806 if (err)
807 return err;
808
809 return 0;
810}
811
48972d90
TR		 812int mmc_getcd(struct mmc *mmc)
813{
814 int cd;
815
816 cd = board_mmc_getcd(mmc);
817
d4e1da4e 818 if (cd < 0) {
93bfd616
PA		 819 if (mmc->cfg->ops->getcd)
820 cd = mmc->cfg->ops->getcd(mmc);
d4e1da4e
PK		 821 else
822 cd = 1;
823 }
48972d90
TR		 824
825 return cd;
826}
827
fdbb873e 828static int sd_switch(struct mmc *mmc, int mode, int group, u8 value, u8 *resp)
272cc70b
AF		 829{
830 struct mmc_cmd cmd;
831 struct mmc_data data;
832
833 /* Switch the frequency */
834 cmd.cmdidx = SD_CMD_SWITCH_FUNC;
835 cmd.resp_type = MMC_RSP_R1;
836 cmd.cmdarg = (mode << 31) | 0xffffff;
837 cmd.cmdarg &= ~(0xf << (group * 4));
838 cmd.cmdarg |= value << (group * 4);
272cc70b
AF		 839
840 data.dest = (char *)resp;
841 data.blocksize = 64;
842 data.blocks = 1;
843 data.flags = MMC_DATA_READ;
844
845 return mmc_send_cmd(mmc, &cmd, &data);
846}
847
848
fdbb873e 849static int sd_change_freq(struct mmc *mmc)
272cc70b
AF		 850{
851 int err;
852 struct mmc_cmd cmd;
f781dd38
A		 853 ALLOC_CACHE_ALIGN_BUFFER(uint, scr, 2);
854 ALLOC_CACHE_ALIGN_BUFFER(uint, switch_status, 16);
272cc70b
AF		 855 struct mmc_data data;
856 int timeout;
857
858 mmc->card_caps = 0;
859
d52ebf10
TC		 860 if (mmc_host_is_spi(mmc))
861 return 0;
862
272cc70b
AF		 863 /* Read the SCR to find out if this card supports higher speeds */
864 cmd.cmdidx = MMC_CMD_APP_CMD;
865 cmd.resp_type = MMC_RSP_R1;
866 cmd.cmdarg = mmc->rca << 16;
272cc70b
AF		 867
868 err = mmc_send_cmd(mmc, &cmd, NULL);
869
870 if (err)
871 return err;
872
873 cmd.cmdidx = SD_CMD_APP_SEND_SCR;
874 cmd.resp_type = MMC_RSP_R1;
875 cmd.cmdarg = 0;
272cc70b
AF		 876
877 timeout = 3;
878
879retry_scr:
f781dd38 880 data.dest = (char *)scr;
272cc70b
AF		 881 data.blocksize = 8;
882 data.blocks = 1;
883 data.flags = MMC_DATA_READ;
884
885 err = mmc_send_cmd(mmc, &cmd, &data);
886
887 if (err) {
888 if (timeout--)
889 goto retry_scr;
890
891 return err;
892 }
893
4e3d89ba
YK		 894 mmc->scr[0] = __be32_to_cpu(scr[0]);
895 mmc->scr[1] = __be32_to_cpu(scr[1]);
272cc70b
AF		 896
897 switch ((mmc->scr[0] >> 24) & 0xf) {
898 case 0:
899 mmc->version = SD_VERSION_1_0;
900 break;
901 case 1:
902 mmc->version = SD_VERSION_1_10;
903 break;
904 case 2:
905 mmc->version = SD_VERSION_2;
1741c64d
JC		 906 if ((mmc->scr[0] >> 15) & 0x1)
907 mmc->version = SD_VERSION_3;
272cc70b
AF		 908 break;
909 default:
910 mmc->version = SD_VERSION_1_0;
911 break;
912 }
913
b44c7083
AS		 914 if (mmc->scr[0] & SD_DATA_4BIT)
915 mmc->card_caps |= MMC_MODE_4BIT;
916
272cc70b
AF		 917 /* Version 1.0 doesn't support switching */
918 if (mmc->version == SD_VERSION_1_0)
919 return 0;
920
921 timeout = 4;
922 while (timeout--) {
923 err = sd_switch(mmc, SD_SWITCH_CHECK, 0, 1,
f781dd38 924 (u8 *)switch_status);
272cc70b
AF		 925
926 if (err)
927 return err;
928
929 /* The high-speed function is busy. Try again */
4e3d89ba 930 if (!(__be32_to_cpu(switch_status[7]) & SD_HIGHSPEED_BUSY))
272cc70b
AF		 931 break;
932 }
933
272cc70b 934 /* If high-speed isn't supported, we return */
4e3d89ba 935 if (!(__be32_to_cpu(switch_status[3]) & SD_HIGHSPEED_SUPPORTED))
272cc70b
AF		 936 return 0;
937
2c3fbf4c
ML		 938 /*
939 * If the host doesn't support SD_HIGHSPEED, do not switch card to
940 * HIGHSPEED mode even if the card support SD_HIGHSPPED.
941 * This can avoid furthur problem when the card runs in different
942 * mode between the host.
943 */
93bfd616
PA		 944 if (!((mmc->cfg->host_caps & MMC_MODE_HS_52MHz) &&
945 (mmc->cfg->host_caps & MMC_MODE_HS)))
2c3fbf4c
ML		 946 return 0;
947
f781dd38 948 err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, 1, (u8 *)switch_status);
272cc70b
AF		 949
950 if (err)
951 return err;
952
4e3d89ba 953 if ((__be32_to_cpu(switch_status[4]) & 0x0f000000) == 0x01000000)
272cc70b
AF		 954 mmc->card_caps |= MMC_MODE_HS;
955
956 return 0;
957}
958
959/* frequency bases */
960/* divided by 10 to be nice to platforms without floating point */
5f837c2c 961static const int fbase[] = {
272cc70b
AF		 962 10000,
963 100000,
964 1000000,
965 10000000,
966};
967
968/* Multiplier values for TRAN_SPEED. Multiplied by 10 to be nice
969 * to platforms without floating point.
970 */
5f837c2c 971static const int multipliers[] = {
272cc70b
AF		 972 0, /* reserved */
973 10,
974 12,
975 13,
976 15,
977 20,
978 25,
979 30,
980 35,
981 40,
982 45,
983 50,
984 55,
985 60,
986 70,
987 80,
988};
989
fdbb873e 990static void mmc_set_ios(struct mmc *mmc)
272cc70b 991{
93bfd616
PA		 992 if (mmc->cfg->ops->set_ios)
993 mmc->cfg->ops->set_ios(mmc);
272cc70b
AF		 994}
995
996void mmc_set_clock(struct mmc *mmc, uint clock)
997{
93bfd616
PA		 998 if (clock > mmc->cfg->f_max)
999 clock = mmc->cfg->f_max;
272cc70b 1000
93bfd616
PA		 1001 if (clock < mmc->cfg->f_min)
1002 clock = mmc->cfg->f_min;
272cc70b
AF		 1003
1004 mmc->clock = clock;
1005
1006 mmc_set_ios(mmc);
1007}
1008
fdbb873e 1009static void mmc_set_bus_width(struct mmc *mmc, uint width)
272cc70b
AF		 1010{
1011 mmc->bus_width = width;
1012
1013 mmc_set_ios(mmc);
1014}
1015
fdbb873e 1016static int mmc_startup(struct mmc *mmc)
272cc70b 1017{
f866a46d 1018 int err, i;
272cc70b 1019 uint mult, freq;
639b7827 1020 u64 cmult, csize, capacity;
272cc70b 1021 struct mmc_cmd cmd;
8bfa195e
SG		 1022 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
1023 ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
5d4fc8d9 1024 int timeout = 1000;
0c453bb7 1025 bool has_parts = false;
8a0cf490 1026 bool part_completed;
272cc70b 1027
d52ebf10
TC		 1028#ifdef CONFIG_MMC_SPI_CRC_ON
1029 if (mmc_host_is_spi(mmc)) { /* enable CRC check for spi */
1030 cmd.cmdidx = MMC_CMD_SPI_CRC_ON_OFF;
1031 cmd.resp_type = MMC_RSP_R1;
1032 cmd.cmdarg = 1;
d52ebf10
TC		 1033 err = mmc_send_cmd(mmc, &cmd, NULL);
1034
1035 if (err)
1036 return err;
1037 }
1038#endif
1039
272cc70b 1040 /* Put the Card in Identify Mode */
d52ebf10
TC		 1041 cmd.cmdidx = mmc_host_is_spi(mmc) ? MMC_CMD_SEND_CID :
1042 MMC_CMD_ALL_SEND_CID; /* cmd not supported in spi */
272cc70b
AF		 1043 cmd.resp_type = MMC_RSP_R2;
1044 cmd.cmdarg = 0;
272cc70b
AF		 1045
1046 err = mmc_send_cmd(mmc, &cmd, NULL);
1047
1048 if (err)
1049 return err;
1050
1051 memcpy(mmc->cid, cmd.response, 16);
1052
1053 /*
1054 * For MMC cards, set the Relative Address.
1055 * For SD cards, get the Relatvie Address.
1056 * This also puts the cards into Standby State
1057 */
d52ebf10
TC		 1058 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
1059 cmd.cmdidx = SD_CMD_SEND_RELATIVE_ADDR;
1060 cmd.cmdarg = mmc->rca << 16;
1061 cmd.resp_type = MMC_RSP_R6;
272cc70b 1062
d52ebf10 1063 err = mmc_send_cmd(mmc, &cmd, NULL);
272cc70b 1064
d52ebf10
TC		 1065 if (err)
1066 return err;
272cc70b 1067
d52ebf10
TC		 1068 if (IS_SD(mmc))
1069 mmc->rca = (cmd.response[0] >> 16) & 0xffff;
1070 }
272cc70b
AF		 1071
1072 /* Get the Card-Specific Data */
1073 cmd.cmdidx = MMC_CMD_SEND_CSD;
1074 cmd.resp_type = MMC_RSP_R2;
1075 cmd.cmdarg = mmc->rca << 16;
272cc70b
AF		 1076
1077 err = mmc_send_cmd(mmc, &cmd, NULL);
1078
5d4fc8d9
RR		 1079 /* Waiting for the ready status */
1080 mmc_send_status(mmc, timeout);
1081
272cc70b
AF		 1082 if (err)
1083 return err;
1084
998be3dd
RV		 1085 mmc->csd[0] = cmd.response[0];
1086 mmc->csd[1] = cmd.response[1];
1087 mmc->csd[2] = cmd.response[2];
1088 mmc->csd[3] = cmd.response[3];
272cc70b
AF		 1089
1090 if (mmc->version == MMC_VERSION_UNKNOWN) {
0b453ffe 1091 int version = (cmd.response[0] >> 26) & 0xf;
272cc70b
AF		 1092
1093 switch (version) {
1094 case 0:
1095 mmc->version = MMC_VERSION_1_2;
1096 break;
1097 case 1:
1098 mmc->version = MMC_VERSION_1_4;
1099 break;
1100 case 2:
1101 mmc->version = MMC_VERSION_2_2;
1102 break;
1103 case 3:
1104 mmc->version = MMC_VERSION_3;
1105 break;
1106 case 4:
1107 mmc->version = MMC_VERSION_4;
1108 break;
1109 default:
1110 mmc->version = MMC_VERSION_1_2;
1111 break;
1112 }
1113 }
1114
1115 /* divide frequency by 10, since the mults are 10x bigger */
0b453ffe
RV		 1116 freq = fbase[(cmd.response[0] & 0x7)];
1117 mult = multipliers[((cmd.response[0] >> 3) & 0xf)];
272cc70b
AF		 1118
1119 mmc->tran_speed = freq * mult;
1120
ab71188c 1121 mmc->dsr_imp = ((cmd.response[1] >> 12) & 0x1);
998be3dd 1122 mmc->read_bl_len = 1 << ((cmd.response[1] >> 16) & 0xf);
272cc70b
AF		 1123
1124 if (IS_SD(mmc))
1125 mmc->write_bl_len = mmc->read_bl_len;
1126 else
998be3dd 1127 mmc->write_bl_len = 1 << ((cmd.response[3] >> 22) & 0xf);
272cc70b
AF		 1128
1129 if (mmc->high_capacity) {
1130 csize = (mmc->csd[1] & 0x3f) << 16
1131 | (mmc->csd[2] & 0xffff0000) >> 16;
1132 cmult = 8;
1133 } else {
1134 csize = (mmc->csd[1] & 0x3ff) << 2
1135 | (mmc->csd[2] & 0xc0000000) >> 30;
1136 cmult = (mmc->csd[2] & 0x00038000) >> 15;
1137 }
1138
f866a46d
SW		 1139 mmc->capacity_user = (csize + 1) << (cmult + 2);
1140 mmc->capacity_user *= mmc->read_bl_len;
1141 mmc->capacity_boot = 0;
1142 mmc->capacity_rpmb = 0;
1143 for (i = 0; i < 4; i++)
1144 mmc->capacity_gp[i] = 0;
272cc70b 1145
8bfa195e
SG		 1146 if (mmc->read_bl_len > MMC_MAX_BLOCK_LEN)
1147 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
272cc70b 1148
8bfa195e
SG		 1149 if (mmc->write_bl_len > MMC_MAX_BLOCK_LEN)
1150 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
272cc70b 1151
ab71188c
MN		 1152 if ((mmc->dsr_imp) && (0xffffffff != mmc->dsr)) {
1153 cmd.cmdidx = MMC_CMD_SET_DSR;
1154 cmd.cmdarg = (mmc->dsr & 0xffff) << 16;
1155 cmd.resp_type = MMC_RSP_NONE;
1156 if (mmc_send_cmd(mmc, &cmd, NULL))
1157 printf("MMC: SET_DSR failed\n");
1158 }
1159
272cc70b 1160 /* Select the card, and put it into Transfer Mode */
d52ebf10
TC		 1161 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
1162 cmd.cmdidx = MMC_CMD_SELECT_CARD;
fe8f7066 1163 cmd.resp_type = MMC_RSP_R1;
d52ebf10 1164 cmd.cmdarg = mmc->rca << 16;
d52ebf10 1165 err = mmc_send_cmd(mmc, &cmd, NULL);
272cc70b 1166
d52ebf10
TC		 1167 if (err)
1168 return err;
1169 }
272cc70b 1170
e6f99a56
LW		 1171 /*
1172 * For SD, its erase group is always one sector
1173 */
1174 mmc->erase_grp_size = 1;
bc897b1d 1175 mmc->part_config = MMCPART_NOAVAILABLE;
d23e2c09
SG		 1176 if (!IS_SD(mmc) && (mmc->version >= MMC_VERSION_4)) {
1177 /* check ext_csd version and capacity */
1178 err = mmc_send_ext_csd(mmc, ext_csd);
9cf199eb
DSC		 1179 if (err)
1180 return err;
1181 if (ext_csd[EXT_CSD_REV] >= 2) {
639b7827
YS		 1182 /*
1183 * According to the JEDEC Standard, the value of
1184 * ext_csd's capacity is valid if the value is more
1185 * than 2GB
1186 */
0560db18
LW		 1187 capacity = ext_csd[EXT_CSD_SEC_CNT] << 0
1188 | ext_csd[EXT_CSD_SEC_CNT + 1] << 8
1189 | ext_csd[EXT_CSD_SEC_CNT + 2] << 16
1190 | ext_csd[EXT_CSD_SEC_CNT + 3] << 24;
8bfa195e 1191 capacity *= MMC_MAX_BLOCK_LEN;
b1f1e821 1192 if ((capacity >> 20) > 2 * 1024)
f866a46d 1193 mmc->capacity_user = capacity;
d23e2c09 1194 }
bc897b1d 1195
64f4a619
JC		 1196 switch (ext_csd[EXT_CSD_REV]) {
1197 case 1:
1198 mmc->version = MMC_VERSION_4_1;
1199 break;
1200 case 2:
1201 mmc->version = MMC_VERSION_4_2;
1202 break;
1203 case 3:
1204 mmc->version = MMC_VERSION_4_3;
1205 break;
1206 case 5:
1207 mmc->version = MMC_VERSION_4_41;
1208 break;
1209 case 6:
1210 mmc->version = MMC_VERSION_4_5;
1211 break;
edab723b
MN		 1212 case 7:
1213 mmc->version = MMC_VERSION_5_0;
1214 break;
64f4a619
JC		 1215 }
1216
8a0cf490
DSC		 1217 /* The partition data may be non-zero but it is only
1218 * effective if PARTITION_SETTING_COMPLETED is set in
1219 * EXT_CSD, so ignore any data if this bit is not set,
1220 * except for enabling the high-capacity group size
1221 * definition (see below). */
1222 part_completed = !!(ext_csd[EXT_CSD_PARTITION_SETTING] &
1223 EXT_CSD_PARTITION_SETTING_COMPLETED);
1224
0c453bb7
DSC		 1225 /* store the partition info of emmc */
1226 mmc->part_support = ext_csd[EXT_CSD_PARTITIONING_SUPPORT];
1227 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) ||
1228 ext_csd[EXT_CSD_BOOT_MULT])
1229 mmc->part_config = ext_csd[EXT_CSD_PART_CONF];
8a0cf490
DSC		 1230 if (part_completed &&
1231 (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & ENHNCD_SUPPORT))
0c453bb7
DSC		 1232 mmc->part_attr = ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE];
1233
1234 mmc->capacity_boot = ext_csd[EXT_CSD_BOOT_MULT] << 17;
1235
1236 mmc->capacity_rpmb = ext_csd[EXT_CSD_RPMB_MULT] << 17;
1237
1238 for (i = 0; i < 4; i++) {
1239 int idx = EXT_CSD_GP_SIZE_MULT + i * 3;
8a0cf490 1240 uint mult = (ext_csd[idx + 2] << 16) +
0c453bb7 1241 (ext_csd[idx + 1] << 8) + ext_csd[idx];
8a0cf490
DSC		 1242 if (mult)
1243 has_parts = true;
1244 if (!part_completed)
1245 continue;
1246 mmc->capacity_gp[i] = mult;
0c453bb7
DSC		 1247 mmc->capacity_gp[i] *=
1248 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
1249 mmc->capacity_gp[i] *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
f8e89d67 1250 mmc->capacity_gp[i] <<= 19;
0c453bb7
DSC		 1251 }
1252
8a0cf490
DSC		 1253 if (part_completed) {
1254 mmc->enh_user_size =
1255 (ext_csd[EXT_CSD_ENH_SIZE_MULT+2] << 16) +
1256 (ext_csd[EXT_CSD_ENH_SIZE_MULT+1] << 8) +
1257 ext_csd[EXT_CSD_ENH_SIZE_MULT];
1258 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
1259 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
1260 mmc->enh_user_size <<= 19;
1261 mmc->enh_user_start =
1262 (ext_csd[EXT_CSD_ENH_START_ADDR+3] << 24) +
1263 (ext_csd[EXT_CSD_ENH_START_ADDR+2] << 16) +
1264 (ext_csd[EXT_CSD_ENH_START_ADDR+1] << 8) +
1265 ext_csd[EXT_CSD_ENH_START_ADDR];
1266 if (mmc->high_capacity)
1267 mmc->enh_user_start <<= 9;
1268 }
a7f852b6 1269
e6f99a56 1270 /*
1937e5aa
OM		 1271 * Host needs to enable ERASE_GRP_DEF bit if device is
1272 * partitioned. This bit will be lost every time after a reset
1273 * or power off. This will affect erase size.
e6f99a56 1274 */
8a0cf490 1275 if (part_completed)
0c453bb7 1276 has_parts = true;
1937e5aa 1277 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) &&
0c453bb7
DSC		 1278 (ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE] & PART_ENH_ATTRIB))
1279 has_parts = true;
1280 if (has_parts) {
1937e5aa
OM		 1281 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1282 EXT_CSD_ERASE_GROUP_DEF, 1);
1283
1284 if (err)
1285 return err;
021a8055
HP		 1286 else
1287 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
037dc0ab 1288 }
1937e5aa 1289
037dc0ab 1290 if (ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01) {
1937e5aa 1291 /* Read out group size from ext_csd */
0560db18 1292 mmc->erase_grp_size =
a4ff9f83 1293 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
d7b29129
MN		 1294 /*
1295 * if high capacity and partition setting completed
1296 * SEC_COUNT is valid even if it is smaller than 2 GiB
1297 * JEDEC Standard JESD84-B45, 6.2.4
1298 */
8a0cf490 1299 if (mmc->high_capacity && part_completed) {
d7b29129
MN		 1300 capacity = (ext_csd[EXT_CSD_SEC_CNT]) |
1301 (ext_csd[EXT_CSD_SEC_CNT + 1] << 8) |
1302 (ext_csd[EXT_CSD_SEC_CNT + 2] << 16) |
1303 (ext_csd[EXT_CSD_SEC_CNT + 3] << 24);
1304 capacity *= MMC_MAX_BLOCK_LEN;
1305 mmc->capacity_user = capacity;
1306 }
8bfa195e 1307 } else {
1937e5aa 1308 /* Calculate the group size from the csd value. */
e6f99a56
LW		 1309 int erase_gsz, erase_gmul;
1310 erase_gsz = (mmc->csd[2] & 0x00007c00) >> 10;
1311 erase_gmul = (mmc->csd[2] & 0x000003e0) >> 5;
1312 mmc->erase_grp_size = (erase_gsz + 1)
1313 * (erase_gmul + 1);
1314 }
037dc0ab
DSC		 1315
1316 mmc->hc_wp_grp_size = 1024
1317 * ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
1318 * ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
9e41a00b
DSC		 1319
1320 mmc->wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
d23e2c09
SG		 1321 }
1322
f866a46d
SW		 1323 err = mmc_set_capacity(mmc, mmc->part_num);
1324 if (err)
1325 return err;
1326
272cc70b
AF		 1327 if (IS_SD(mmc))
1328 err = sd_change_freq(mmc);
1329 else
1330 err = mmc_change_freq(mmc);
1331
1332 if (err)
1333 return err;
1334
1335 /* Restrict card's capabilities by what the host can do */
93bfd616 1336 mmc->card_caps &= mmc->cfg->host_caps;
272cc70b
AF		 1337
1338 if (IS_SD(mmc)) {
1339 if (mmc->card_caps & MMC_MODE_4BIT) {
1340 cmd.cmdidx = MMC_CMD_APP_CMD;
1341 cmd.resp_type = MMC_RSP_R1;
1342 cmd.cmdarg = mmc->rca << 16;
272cc70b
AF		 1343
1344 err = mmc_send_cmd(mmc, &cmd, NULL);
1345 if (err)
1346 return err;
1347
1348 cmd.cmdidx = SD_CMD_APP_SET_BUS_WIDTH;
1349 cmd.resp_type = MMC_RSP_R1;
1350 cmd.cmdarg = 2;
272cc70b
AF		 1351 err = mmc_send_cmd(mmc, &cmd, NULL);
1352 if (err)
1353 return err;
1354
1355 mmc_set_bus_width(mmc, 4);
1356 }
1357
1358 if (mmc->card_caps & MMC_MODE_HS)
ad5fd922 1359 mmc->tran_speed = 50000000;
272cc70b 1360 else
ad5fd922 1361 mmc->tran_speed = 25000000;
fc5b32fb
AG		 1362 } else if (mmc->version >= MMC_VERSION_4) {
1363 /* Only version 4 of MMC supports wider bus widths */
7798f6db
AF		 1364 int idx;
1365
1366 /* An array of possible bus widths in order of preference */
1367 static unsigned ext_csd_bits[] = {
d22e3d46
JC		 1368 EXT_CSD_DDR_BUS_WIDTH_8,
1369 EXT_CSD_DDR_BUS_WIDTH_4,
7798f6db
AF		 1370 EXT_CSD_BUS_WIDTH_8,
1371 EXT_CSD_BUS_WIDTH_4,
1372 EXT_CSD_BUS_WIDTH_1,
1373 };
1374
1375 /* An array to map CSD bus widths to host cap bits */
1376 static unsigned ext_to_hostcaps[] = {
786e8f81
AG		 1377 [EXT_CSD_DDR_BUS_WIDTH_4] =
1378 MMC_MODE_DDR_52MHz | MMC_MODE_4BIT,
1379 [EXT_CSD_DDR_BUS_WIDTH_8] =
1380 MMC_MODE_DDR_52MHz | MMC_MODE_8BIT,
7798f6db
AF		 1381 [EXT_CSD_BUS_WIDTH_4] = MMC_MODE_4BIT,
1382 [EXT_CSD_BUS_WIDTH_8] = MMC_MODE_8BIT,
1383 };
1384
1385 /* An array to map chosen bus width to an integer */
1386 static unsigned widths[] = {
d22e3d46 1387 8, 4, 8, 4, 1,
7798f6db
AF		 1388 };
1389
1390 for (idx=0; idx < ARRAY_SIZE(ext_csd_bits); idx++) {
1391 unsigned int extw = ext_csd_bits[idx];
786e8f81 1392 unsigned int caps = ext_to_hostcaps[extw];
7798f6db 1393
bf477073
AG		 1394 /*
1395 * If the bus width is still not changed,
1396 * don't try to set the default again.
1397 * Otherwise, recover from switch attempts
1398 * by switching to 1-bit bus width.
1399 */
1400 if (extw == EXT_CSD_BUS_WIDTH_1 &&
1401 mmc->bus_width == 1) {
1402 err = 0;
1403 break;
1404 }
1405
7798f6db 1406 /*
786e8f81
AG		 1407 * Check to make sure the card and controller support
1408 * these capabilities
7798f6db 1409 */
786e8f81 1410 if ((mmc->card_caps & caps) != caps)
7798f6db
AF		 1411 continue;
1412
272cc70b 1413 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
7798f6db 1414 EXT_CSD_BUS_WIDTH, extw);
272cc70b
AF		 1415
1416 if (err)
4137894e 1417 continue;
272cc70b 1418
786e8f81 1419 mmc->ddr_mode = (caps & MMC_MODE_DDR_52MHz) ? 1 : 0;
7798f6db 1420 mmc_set_bus_width(mmc, widths[idx]);
4137894e
LW		 1421
1422 err = mmc_send_ext_csd(mmc, test_csd);
786e8f81
AG		 1423
1424 if (err)
1425 continue;
1426
786a27b7 1427 /* Only compare read only fields */
786e8f81
AG		 1428 if (ext_csd[EXT_CSD_PARTITIONING_SUPPORT]
1429 == test_csd[EXT_CSD_PARTITIONING_SUPPORT] &&
1430 ext_csd[EXT_CSD_HC_WP_GRP_SIZE]
1431 == test_csd[EXT_CSD_HC_WP_GRP_SIZE] &&
1432 ext_csd[EXT_CSD_REV]
1433 == test_csd[EXT_CSD_REV] &&
1434 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
1435 == test_csd[EXT_CSD_HC_ERASE_GRP_SIZE] &&
1436 memcmp(&ext_csd[EXT_CSD_SEC_CNT],
1437 &test_csd[EXT_CSD_SEC_CNT], 4) == 0)
4137894e 1438 break;
786e8f81
AG		 1439 else
1440 err = SWITCH_ERR;
272cc70b
AF		 1441 }
1442
786e8f81
AG		 1443 if (err)
1444 return err;
1445
272cc70b
AF		 1446 if (mmc->card_caps & MMC_MODE_HS) {
1447 if (mmc->card_caps & MMC_MODE_HS_52MHz)
ad5fd922 1448 mmc->tran_speed = 52000000;
272cc70b 1449 else
ad5fd922
JC		 1450 mmc->tran_speed = 26000000;
1451 }
272cc70b
AF		 1452 }
1453
ad5fd922
JC		 1454 mmc_set_clock(mmc, mmc->tran_speed);
1455
5af8f45c
AG		 1456 /* Fix the block length for DDR mode */
1457 if (mmc->ddr_mode) {
1458 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
1459 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
1460 }
1461
272cc70b
AF		 1462 /* fill in device description */
1463 mmc->block_dev.lun = 0;
1464 mmc->block_dev.type = 0;
1465 mmc->block_dev.blksz = mmc->read_bl_len;
0472fbfd 1466 mmc->block_dev.log2blksz = LOG2(mmc->block_dev.blksz);
9b1f942c 1467 mmc->block_dev.lba = lldiv(mmc->capacity, mmc->read_bl_len);
56196826 1468#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
babce5f6
TH		 1469 sprintf(mmc->block_dev.vendor, "Man %06x Snr %04x%04x",
1470 mmc->cid[0] >> 24, (mmc->cid[2] & 0xffff),
1471 (mmc->cid[3] >> 16) & 0xffff);
1472 sprintf(mmc->block_dev.product, "%c%c%c%c%c%c", mmc->cid[0] & 0xff,
1473 (mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff,
1474 (mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff,
1475 (mmc->cid[2] >> 24) & 0xff);
1476 sprintf(mmc->block_dev.revision, "%d.%d", (mmc->cid[2] >> 20) & 0xf,
1477 (mmc->cid[2] >> 16) & 0xf);
56196826
PB		 1478#else
1479 mmc->block_dev.vendor[0] = 0;
1480 mmc->block_dev.product[0] = 0;
1481 mmc->block_dev.revision[0] = 0;
1482#endif
122efd43 1483#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBDISK_SUPPORT)
272cc70b 1484 init_part(&mmc->block_dev);
122efd43 1485#endif
272cc70b
AF		 1486
1487 return 0;
1488}
1489
fdbb873e 1490static int mmc_send_if_cond(struct mmc *mmc)
272cc70b
AF		 1491{
1492 struct mmc_cmd cmd;
1493 int err;
1494
1495 cmd.cmdidx = SD_CMD_SEND_IF_COND;
1496 /* We set the bit if the host supports voltages between 2.7 and 3.6 V */
93bfd616 1497 cmd.cmdarg = ((mmc->cfg->voltages & 0xff8000) != 0) << 8 | 0xaa;
272cc70b 1498 cmd.resp_type = MMC_RSP_R7;
272cc70b
AF		 1499
1500 err = mmc_send_cmd(mmc, &cmd, NULL);
1501
1502 if (err)
1503 return err;
1504
998be3dd 1505 if ((cmd.response[0] & 0xff) != 0xaa)
272cc70b
AF		 1506 return UNUSABLE_ERR;
1507 else
1508 mmc->version = SD_VERSION_2;
1509
1510 return 0;
1511}
1512
93bfd616
PA		 1513/* not used any more */
1514int __deprecated mmc_register(struct mmc *mmc)
1515{
1516#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
1517 printf("%s is deprecated! use mmc_create() instead.\n", __func__);
1518#endif
1519 return -1;
1520}
1521
1522struct mmc *mmc_create(const struct mmc_config *cfg, void *priv)
272cc70b 1523{
93bfd616
PA		 1524 struct mmc *mmc;
1525
1526 /* quick validation */
1527 if (cfg == NULL || cfg->ops == NULL || cfg->ops->send_cmd == NULL ||
1528 cfg->f_min == 0 || cfg->f_max == 0 || cfg->b_max == 0)
1529 return NULL;
1530
1531 mmc = calloc(1, sizeof(*mmc));
1532 if (mmc == NULL)
1533 return NULL;
1534
1535 mmc->cfg = cfg;
1536 mmc->priv = priv;
1537
1538 /* the following chunk was mmc_register() */
1539
ab71188c
MN		 1540 /* Setup dsr related values */
1541 mmc->dsr_imp = 0;
1542 mmc->dsr = 0xffffffff;
272cc70b
AF		 1543 /* Setup the universal parts of the block interface just once */
1544 mmc->block_dev.if_type = IF_TYPE_MMC;
1545 mmc->block_dev.dev = cur_dev_num++;
1546 mmc->block_dev.removable = 1;
1547 mmc->block_dev.block_read = mmc_bread;
1548 mmc->block_dev.block_write = mmc_bwrite;
e6f99a56 1549 mmc->block_dev.block_erase = mmc_berase;
272cc70b 1550
93bfd616
PA		 1551 /* setup initial part type */
1552 mmc->block_dev.part_type = mmc->cfg->part_type;
272cc70b 1553
93bfd616 1554 INIT_LIST_HEAD(&mmc->link);
272cc70b 1555
93bfd616
PA		 1556 list_add_tail(&mmc->link, &mmc_devices);
1557
1558 return mmc;
1559}
1560
1561void mmc_destroy(struct mmc *mmc)
1562{
1563 /* only freeing memory for now */
1564 free(mmc);
272cc70b
AF		 1565}
1566
df3fc526 1567#ifdef CONFIG_PARTITIONS
272cc70b
AF		 1568block_dev_desc_t *mmc_get_dev(int dev)
1569{
1570 struct mmc *mmc = find_mmc_device(dev);
6bb4b4bc 1571 if (!mmc || mmc_init(mmc))
40242bc3 1572 return NULL;
272cc70b 1573
40242bc3 1574 return &mmc->block_dev;
272cc70b 1575}
df3fc526 1576#endif
272cc70b 1577
95de9ab2
PK		 1578/* board-specific MMC power initializations. */
1579__weak void board_mmc_power_init(void)
1580{
1581}
1582
e9550449 1583int mmc_start_init(struct mmc *mmc)
272cc70b 1584{
afd5932b 1585 int err;
272cc70b 1586
ab769f22 1587 /* we pretend there's no card when init is NULL */
93bfd616 1588 if (mmc_getcd(mmc) == 0 || mmc->cfg->ops->init == NULL) {
48972d90 1589 mmc->has_init = 0;
56196826 1590#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
48972d90 1591 printf("MMC: no card present\n");
56196826 1592#endif
48972d90
TR		 1593 return NO_CARD_ERR;
1594 }
1595
bc897b1d
LW		 1596 if (mmc->has_init)
1597 return 0;
1598
95de9ab2
PK		 1599 board_mmc_power_init();
1600
ab769f22 1601 /* made sure it's not NULL earlier */
93bfd616 1602 err = mmc->cfg->ops->init(mmc);
272cc70b
AF		 1603
1604 if (err)
1605 return err;
1606
786e8f81 1607 mmc->ddr_mode = 0;
b86b85e2
IY		 1608 mmc_set_bus_width(mmc, 1);
1609 mmc_set_clock(mmc, 1);
1610
272cc70b
AF		 1611 /* Reset the Card */
1612 err = mmc_go_idle(mmc);
1613
1614 if (err)
1615 return err;
1616
bc897b1d
LW		 1617 /* The internal partition reset to user partition(0) at every CMD0*/
1618 mmc->part_num = 0;
1619
272cc70b 1620 /* Test for SD version 2 */
afd5932b 1621 err = mmc_send_if_cond(mmc);
272cc70b 1622
272cc70b
AF		 1623 /* Now try to get the SD card's operating condition */
1624 err = sd_send_op_cond(mmc);
1625
1626 /* If the command timed out, we check for an MMC card */
1627 if (err == TIMEOUT) {
1628 err = mmc_send_op_cond(mmc);
1629
e9550449 1630 if (err && err != IN_PROGRESS) {
56196826 1631#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
272cc70b 1632 printf("Card did not respond to voltage select!\n");
56196826 1633#endif
272cc70b
AF		 1634 return UNUSABLE_ERR;
1635 }
1636 }
1637
e9550449
CLC		 1638 if (err == IN_PROGRESS)
1639 mmc->init_in_progress = 1;
1640
1641 return err;
1642}
1643
1644static int mmc_complete_init(struct mmc *mmc)
1645{
1646 int err = 0;
1647
1648 if (mmc->op_cond_pending)
1649 err = mmc_complete_op_cond(mmc);
1650
1651 if (!err)
1652 err = mmc_startup(mmc);
bc897b1d
LW		 1653 if (err)
1654 mmc->has_init = 0;
1655 else
1656 mmc->has_init = 1;
e9550449
CLC		 1657 mmc->init_in_progress = 0;
1658 return err;
1659}
1660
1661int mmc_init(struct mmc *mmc)
1662{
1663 int err = IN_PROGRESS;
d803fea5 1664 unsigned start;
e9550449
CLC		 1665
1666 if (mmc->has_init)
1667 return 0;
d803fea5
MZ		 1668
1669 start = get_timer(0);
1670
e9550449
CLC		 1671 if (!mmc->init_in_progress)
1672 err = mmc_start_init(mmc);
1673
1674 if (!err || err == IN_PROGRESS)
1675 err = mmc_complete_init(mmc);
1676 debug("%s: %d, time %lu\n", __func__, err, get_timer(start));
bc897b1d 1677 return err;
272cc70b
AF		 1678}
1679
ab71188c
MN		 1680int mmc_set_dsr(struct mmc *mmc, u16 val)
1681{
1682 mmc->dsr = val;
1683 return 0;
1684}
1685
cee9ab7c
JH		 1686/* CPU-specific MMC initializations */
1687__weak int cpu_mmc_init(bd_t *bis)
272cc70b
AF		 1688{
1689 return -1;
1690}
1691
cee9ab7c
JH		 1692/* board-specific MMC initializations. */
1693__weak int board_mmc_init(bd_t *bis)
1694{
1695 return -1;
1696}
272cc70b 1697
56196826
PB		 1698#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
1699
272cc70b
AF		 1700void print_mmc_devices(char separator)
1701{
1702 struct mmc *m;
1703 struct list_head *entry;
34dd9284 1704 char *mmc_type;
272cc70b
AF		 1705
1706 list_for_each(entry, &mmc_devices) {
1707 m = list_entry(entry, struct mmc, link);
1708
34dd9284
PM		 1709 if (m->has_init)
1710 mmc_type = IS_SD(m) ? "SD" : "eMMC";
1711 else
1712 mmc_type = NULL;
1713
93bfd616 1714 printf("%s: %d", m->cfg->name, m->block_dev.dev);
34dd9284
PM		 1715 if (mmc_type)
1716 printf(" (%s)", mmc_type);
272cc70b 1717
e75eaf10
LP		 1718 if (entry->next != &mmc_devices) {
1719 printf("%c", separator);
1720 if (separator != '\n')
1721 puts (" ");
1722 }
272cc70b
AF		 1723 }
1724
1725 printf("\n");
1726}
1727
56196826
PB		 1728#else
1729void print_mmc_devices(char separator) { }
1730#endif
1731
ea6ebe21
LW		 1732int get_mmc_num(void)
1733{
1734 return cur_dev_num;
1735}
1736
e9550449
CLC		 1737void mmc_set_preinit(struct mmc *mmc, int preinit)
1738{
1739 mmc->preinit = preinit;
1740}
1741
1742static void do_preinit(void)
1743{
1744 struct mmc *m;
1745 struct list_head *entry;
1746
1747 list_for_each(entry, &mmc_devices) {
1748 m = list_entry(entry, struct mmc, link);
1749
1750 if (m->preinit)
1751 mmc_start_init(m);
1752 }
1753}
1754
1755
272cc70b
AF		 1756int mmc_initialize(bd_t *bis)
1757{
1758 INIT_LIST_HEAD (&mmc_devices);
1759 cur_dev_num = 0;
1760
1761 if (board_mmc_init(bis) < 0)
1762 cpu_mmc_init(bis);
1763
bb0dc108 1764#ifndef CONFIG_SPL_BUILD
272cc70b 1765 print_mmc_devices(',');
bb0dc108 1766#endif
272cc70b 1767
e9550449 1768 do_preinit();
272cc70b
AF		 1769 return 0;
1770}
3690d6d6
A		 1771
1772#ifdef CONFIG_SUPPORT_EMMC_BOOT
1773/*
1774 * This function changes the size of boot partition and the size of rpmb
1775 * partition present on EMMC devices.
1776 *
1777 * Input Parameters:
1778 * struct *mmc: pointer for the mmc device strcuture
1779 * bootsize: size of boot partition
1780 * rpmbsize: size of rpmb partition
1781 *
1782 * Returns 0 on success.
1783 */
1784
1785int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize,
1786 unsigned long rpmbsize)
1787{
1788 int err;
1789 struct mmc_cmd cmd;
1790
1791 /* Only use this command for raw EMMC moviNAND. Enter backdoor mode */
1792 cmd.cmdidx = MMC_CMD_RES_MAN;
1793 cmd.resp_type = MMC_RSP_R1b;
1794 cmd.cmdarg = MMC_CMD62_ARG1;
1795
1796 err = mmc_send_cmd(mmc, &cmd, NULL);
1797 if (err) {
1798 debug("mmc_boot_partition_size_change: Error1 = %d\n", err);
1799 return err;
1800 }
1801
1802 /* Boot partition changing mode */
1803 cmd.cmdidx = MMC_CMD_RES_MAN;
1804 cmd.resp_type = MMC_RSP_R1b;
1805 cmd.cmdarg = MMC_CMD62_ARG2;
1806
1807 err = mmc_send_cmd(mmc, &cmd, NULL);
1808 if (err) {
1809 debug("mmc_boot_partition_size_change: Error2 = %d\n", err);
1810 return err;
1811 }
1812 /* boot partition size is multiple of 128KB */
1813 bootsize = (bootsize * 1024) / 128;
1814
1815 /* Arg: boot partition size */
1816 cmd.cmdidx = MMC_CMD_RES_MAN;
1817 cmd.resp_type = MMC_RSP_R1b;
1818 cmd.cmdarg = bootsize;
1819
1820 err = mmc_send_cmd(mmc, &cmd, NULL);
1821 if (err) {
1822 debug("mmc_boot_partition_size_change: Error3 = %d\n", err);
1823 return err;
1824 }
1825 /* RPMB partition size is multiple of 128KB */
1826 rpmbsize = (rpmbsize * 1024) / 128;
1827 /* Arg: RPMB partition size */
1828 cmd.cmdidx = MMC_CMD_RES_MAN;
1829 cmd.resp_type = MMC_RSP_R1b;
1830 cmd.cmdarg = rpmbsize;
1831
1832 err = mmc_send_cmd(mmc, &cmd, NULL);
1833 if (err) {
1834 debug("mmc_boot_partition_size_change: Error4 = %d\n", err);
1835 return err;
1836 }
1837 return 0;
1838}
1839
5a99b9de
TR		 1840/*
1841 * Modify EXT_CSD[177] which is BOOT_BUS_WIDTH
1842 * based on the passed in values for BOOT_BUS_WIDTH, RESET_BOOT_BUS_WIDTH
1843 * and BOOT_MODE.
1844 *
1845 * Returns 0 on success.
1846 */
1847int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode)
1848{
1849 int err;
1850
1851 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BOOT_BUS_WIDTH,
1852 EXT_CSD_BOOT_BUS_WIDTH_MODE(mode) |
1853 EXT_CSD_BOOT_BUS_WIDTH_RESET(reset) |
1854 EXT_CSD_BOOT_BUS_WIDTH_WIDTH(width));
1855
1856 if (err)
1857 return err;
1858 return 0;
1859}
1860
792970b0
TR		 1861/*
1862 * Modify EXT_CSD[179] which is PARTITION_CONFIG (formerly BOOT_CONFIG)
1863 * based on the passed in values for BOOT_ACK, BOOT_PARTITION_ENABLE and
1864 * PARTITION_ACCESS.
1865 *
1866 * Returns 0 on success.
1867 */
1868int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access)
1869{
1870 int err;
1871
1872 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF,
1873 EXT_CSD_BOOT_ACK(ack) |
1874 EXT_CSD_BOOT_PART_NUM(part_num) |
1875 EXT_CSD_PARTITION_ACCESS(access));
1876
1877 if (err)
1878 return err;
1879 return 0;
1880}
33ace362
TR		 1881
1882/*
1883 * Modify EXT_CSD[162] which is RST_n_FUNCTION based on the given value
1884 * for enable. Note that this is a write-once field for non-zero values.
1885 *
1886 * Returns 0 on success.
1887 */
1888int mmc_set_rst_n_function(struct mmc *mmc, u8 enable)
1889{
1890 return mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_RST_N_FUNCTION,
1891 enable);
1892}
3690d6d6 1893#endif
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