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Restore patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"
[u-boot.git] / drivers / mmc / mmc.c
CommitLineData
83d290c5 1// SPDX-License-Identifier: GPL-2.0+
272cc70b
AF		 2/*
3 * Copyright 2008, Freescale Semiconductor, Inc
39913ace 4 * Copyright 2020 NXP
272cc70b
AF		 5 * Andy Fleming
6 *
7 * Based vaguely on the Linux code
272cc70b
AF		 8 */
9
10#include <config.h>
e6f6f9e6 11#include <blk.h>
272cc70b 12#include <command.h>
8e3332e2 13#include <dm.h>
f7ae49fc 14#include <log.h>
8e3332e2 15#include <dm/device-internal.h>
d4622df3 16#include <errno.h>
272cc70b
AF		 17#include <mmc.h>
18#include <part.h>
03de305e 19#include <time.h>
cd93d625 20#include <linux/bitops.h>
c05ed00a 21#include <linux/delay.h>
1e94b46f 22#include <linux/printk.h>
2051aefe 23#include <power/regulator.h>
272cc70b 24#include <malloc.h>
cf92e05c 25#include <memalign.h>
272cc70b 26#include <linux/list.h>
03de305e 27#include <linux/printk.h>
9b1f942c 28#include <div64.h>
da61fa5f 29#include "mmc_private.h"
272cc70b 30
39320c53
JJH		 31#define DEFAULT_CMD6_TIMEOUT_MS 500
32
aff5d3c8 33static int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage);
b5b838f1 34
e7881d85 35#if !CONFIG_IS_ENABLED(DM_MMC)
c10b85d6 36
6cf8a903 37static int mmc_wait_dat0(struct mmc *mmc, int state, int timeout_us)
c10b85d6 38{
d6ad5a0a
LP		 39 if (mmc->cfg->ops->wait_dat0)
40 return mmc->cfg->ops->wait_dat0(mmc, state, timeout_us);
41
c10b85d6
JJH		 42 return -ENOSYS;
43}
44
750121c3 45__weak int board_mmc_getwp(struct mmc *mmc)
d23d8d7e
NK		 46{
47 return -1;
48}
49
50int mmc_getwp(struct mmc *mmc)
51{
52 int wp;
53
54 wp = board_mmc_getwp(mmc);
55
d4e1da4e 56 if (wp < 0) {
93bfd616
PA		 57 if (mmc->cfg->ops->getwp)
58 wp = mmc->cfg->ops->getwp(mmc);
d4e1da4e
PK		 59 else
60 wp = 0;
61 }
d23d8d7e
NK		 62
63 return wp;
64}
65
cee9ab7c
JH		 66__weak int board_mmc_getcd(struct mmc *mmc)
67{
11fdade2
SB		 68 return -1;
69}
8ca51e51 70#endif
11fdade2 71
c0c76eba
SG		 72#ifdef CONFIG_MMC_TRACE
73void mmmc_trace_before_send(struct mmc *mmc, struct mmc_cmd *cmd)
272cc70b 74{
c0c76eba 75 printf("CMD_SEND:%d\n", cmd->cmdidx);
7d5ccb1a 76 printf("\t\tARG\t\t\t 0x%08x\n", cmd->cmdarg);
c0c76eba 77}
8635ff9e 78
c0c76eba
SG		 79void mmmc_trace_after_send(struct mmc *mmc, struct mmc_cmd *cmd, int ret)
80{
5db2fe3a
RR		 81 int i;
82 u8 *ptr;
83
7863ce58
BM		 84 if (ret) {
85 printf("\t\tRET\t\t\t %d\n", ret);
86 } else {
87 switch (cmd->resp_type) {
88 case MMC_RSP_NONE:
89 printf("\t\tMMC_RSP_NONE\n");
90 break;
91 case MMC_RSP_R1:
7d5ccb1a 92 printf("\t\tMMC_RSP_R1,5,6,7 \t 0x%08x \n",
7863ce58
BM		 93 cmd->response[0]);
94 break;
95 case MMC_RSP_R1b:
7d5ccb1a 96 printf("\t\tMMC_RSP_R1b\t\t 0x%08x \n",
7863ce58
BM		 97 cmd->response[0]);
98 break;
99 case MMC_RSP_R2:
7d5ccb1a 100 printf("\t\tMMC_RSP_R2\t\t 0x%08x \n",
7863ce58 101 cmd->response[0]);
7d5ccb1a 102 printf("\t\t \t\t 0x%08x \n",
7863ce58 103 cmd->response[1]);
7d5ccb1a 104 printf("\t\t \t\t 0x%08x \n",
7863ce58 105 cmd->response[2]);
7d5ccb1a 106 printf("\t\t \t\t 0x%08x \n",
7863ce58 107 cmd->response[3]);
5db2fe3a 108 printf("\n");
7863ce58
BM		 109 printf("\t\t\t\t\tDUMPING DATA\n");
110 for (i = 0; i < 4; i++) {
111 int j;
112 printf("\t\t\t\t\t%03d - ", i*4);
113 ptr = (u8 *)&cmd->response[i];
114 ptr += 3;
115 for (j = 0; j < 4; j++)
7d5ccb1a 116 printf("%02x ", *ptr--);
7863ce58
BM		 117 printf("\n");
118 }
119 break;
120 case MMC_RSP_R3:
7d5ccb1a 121 printf("\t\tMMC_RSP_R3,4\t\t 0x%08x \n",
7863ce58
BM		 122 cmd->response[0]);
123 break;
124 default:
125 printf("\t\tERROR MMC rsp not supported\n");
126 break;
53e8e40b 127 }
5db2fe3a 128 }
c0c76eba
SG		 129}
130
131void mmc_trace_state(struct mmc *mmc, struct mmc_cmd *cmd)
132{
133 int status;
134
135 status = (cmd->response[0] & MMC_STATUS_CURR_STATE) >> 9;
136 printf("CURR STATE:%d\n", status);
137}
5db2fe3a 138#endif
c0c76eba 139
48467e47 140#if CONFIG_IS_ENABLED(MMC_VERBOSE) || defined(DEBUG) || CONFIG_VAL(LOGLEVEL) >= LOGL_DEBUG
35f9e196
JJH		 141const char *mmc_mode_name(enum bus_mode mode)
142{
143 static const char *const names[] = {
144 [MMC_LEGACY] = "MMC legacy",
35f9e196
JJH		 145 [MMC_HS] = "MMC High Speed (26MHz)",
146 [SD_HS] = "SD High Speed (50MHz)",
147 [UHS_SDR12] = "UHS SDR12 (25MHz)",
148 [UHS_SDR25] = "UHS SDR25 (50MHz)",
149 [UHS_SDR50] = "UHS SDR50 (100MHz)",
150 [UHS_SDR104] = "UHS SDR104 (208MHz)",
151 [UHS_DDR50] = "UHS DDR50 (50MHz)",
152 [MMC_HS_52] = "MMC High Speed (52MHz)",
153 [MMC_DDR_52] = "MMC DDR52 (52MHz)",
154 [MMC_HS_200] = "HS200 (200MHz)",
3dd2626f 155 [MMC_HS_400] = "HS400 (200MHz)",
44acd492 156 [MMC_HS_400_ES] = "HS400ES (200MHz)",
35f9e196
JJH		 157 };
158
159 if (mode >= MMC_MODES_END)
160 return "Unknown mode";
161 else
162 return names[mode];
163}
164#endif
165
05038576
JJH		 166static uint mmc_mode2freq(struct mmc *mmc, enum bus_mode mode)
167{
168 static const int freqs[] = {
1b313aa3 169 [MMC_LEGACY] = 25000000,
05038576
JJH		 170 [MMC_HS] = 26000000,
171 [SD_HS] = 50000000,
1b313aa3
JC		 172 [MMC_HS_52] = 52000000,
173 [MMC_DDR_52] = 52000000,
05038576
JJH		 174 [UHS_SDR12] = 25000000,
175 [UHS_SDR25] = 50000000,
176 [UHS_SDR50] = 100000000,
05038576 177 [UHS_DDR50] = 50000000,
f99c2efe 178 [UHS_SDR104] = 208000000,
05038576 179 [MMC_HS_200] = 200000000,
3dd2626f 180 [MMC_HS_400] = 200000000,
44acd492 181 [MMC_HS_400_ES] = 200000000,
05038576
JJH		 182 };
183
184 if (mode == MMC_LEGACY)
185 return mmc->legacy_speed;
186 else if (mode >= MMC_MODES_END)
187 return 0;
188 else
189 return freqs[mode];
190}
191
35f9e196
JJH		 192static int mmc_select_mode(struct mmc *mmc, enum bus_mode mode)
193{
194 mmc->selected_mode = mode;
05038576 195 mmc->tran_speed = mmc_mode2freq(mmc, mode);
3862b854 196 mmc->ddr_mode = mmc_is_mode_ddr(mode);
d4d64889
MY		 197 pr_debug("selecting mode %s (freq : %d MHz)\n", mmc_mode_name(mode),
198 mmc->tran_speed / 1000000);
35f9e196
JJH		 199 return 0;
200}
201
e7881d85 202#if !CONFIG_IS_ENABLED(DM_MMC)
c0c76eba
SG		 203int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
204{
205 int ret;
206
207 mmmc_trace_before_send(mmc, cmd);
208 ret = mmc->cfg->ops->send_cmd(mmc, cmd, data);
209 mmmc_trace_after_send(mmc, cmd, ret);
210
8635ff9e 211 return ret;
272cc70b 212}
8ca51e51 213#endif
272cc70b 214
da129170
SA		 215/**
216 * mmc_send_cmd_retry() - send a command to the mmc device, retrying on error
217 *
218 * @dev: device to receive the command
219 * @cmd: command to send
220 * @data: additional data to send/receive
221 * @retries: how many times to retry; mmc_send_cmd is always called at least
222 * once
185f812c 223 * Return: 0 if ok, -ve on error
da129170
SA		 224 */
225static int mmc_send_cmd_retry(struct mmc *mmc, struct mmc_cmd *cmd,
226 struct mmc_data *data, uint retries)
227{
228 int ret;
229
230 do {
231 ret = mmc_send_cmd(mmc, cmd, data);
232 } while (ret && retries--);
233
234 return ret;
235}
236
237/**
238 * mmc_send_cmd_quirks() - send a command to the mmc device, retrying if a
239 * specific quirk is enabled
240 *
241 * @dev: device to receive the command
242 * @cmd: command to send
243 * @data: additional data to send/receive
244 * @quirk: retry only if this quirk is enabled
245 * @retries: how many times to retry; mmc_send_cmd is always called at least
246 * once
185f812c 247 * Return: 0 if ok, -ve on error
da129170
SA		 248 */
249static int mmc_send_cmd_quirks(struct mmc *mmc, struct mmc_cmd *cmd,
250 struct mmc_data *data, u32 quirk, uint retries)
251{
497b7c6b 252 if (IS_ENABLED(CONFIG_MMC_QUIRKS) && mmc->quirks & quirk)
da129170
SA		 253 return mmc_send_cmd_retry(mmc, cmd, data, retries);
254 else
255 return mmc_send_cmd(mmc, cmd, data);
256}
257
863d1004 258int mmc_send_status(struct mmc *mmc, unsigned int *status)
5d4fc8d9
RR		 259{
260 struct mmc_cmd cmd;
da129170 261 int ret;
5d4fc8d9
RR		 262
263 cmd.cmdidx = MMC_CMD_SEND_STATUS;
264 cmd.resp_type = MMC_RSP_R1;
aaf3d41a
MV		 265 if (!mmc_host_is_spi(mmc))
266 cmd.cmdarg = mmc->rca << 16;
5d4fc8d9 267
da129170 268 ret = mmc_send_cmd_retry(mmc, &cmd, NULL, 4);
863d1004 269 mmc_trace_state(mmc, &cmd);
da129170
SA		 270 if (!ret)
271 *status = cmd.response[0];
272
273 return ret;
863d1004
JJH		 274}
275
6cf8a903 276int mmc_poll_for_busy(struct mmc *mmc, int timeout_ms)
863d1004
JJH		 277{
278 unsigned int status;
279 int err;
d0c221fe 280
6cf8a903 281 err = mmc_wait_dat0(mmc, 1, timeout_ms * 1000);
cd0b80ec
JJH		 282 if (err != -ENOSYS)
283 return err;
284
863d1004
JJH		 285 while (1) {
286 err = mmc_send_status(mmc, &status);
287 if (err)
288 return err;
289
290 if ((status & MMC_STATUS_RDY_FOR_DATA) &&
291 (status & MMC_STATUS_CURR_STATE) !=
292 MMC_STATE_PRG)
293 break;
294
295 if (status & MMC_STATUS_MASK) {
56196826 296#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
863d1004 297 pr_err("Status Error: 0x%08x\n", status);
56196826 298#endif
863d1004
JJH		 299 return -ECOMM;
300 }
5d4fc8d9 301
6cf8a903 302 if (timeout_ms-- <= 0)
1677eef4 303 break;
5d4fc8d9 304
1677eef4
AG		 305 udelay(1000);
306 }
5d4fc8d9 307
6cf8a903 308 if (timeout_ms <= 0) {
56196826 309#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
d8e3d420 310 pr_err("Timeout waiting card ready\n");
56196826 311#endif
915ffa52 312 return -ETIMEDOUT;
5d4fc8d9
RR		 313 }
314
315 return 0;
316}
317
da61fa5f 318int mmc_set_blocklen(struct mmc *mmc, int len)
272cc70b
AF		 319{
320 struct mmc_cmd cmd;
321
786e8f81 322 if (mmc->ddr_mode)
d22e3d46
JC		 323 return 0;
324
272cc70b
AF		 325 cmd.cmdidx = MMC_CMD_SET_BLOCKLEN;
326 cmd.resp_type = MMC_RSP_R1;
327 cmd.cmdarg = len;
272cc70b 328
da129170
SA		 329 return mmc_send_cmd_quirks(mmc, &cmd, NULL,
330 MMC_QUIRK_RETRY_SET_BLOCKLEN, 4);
272cc70b
AF		 331}
332
03de305e 333#if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING)
9815e3ba
JJH		 334static const u8 tuning_blk_pattern_4bit[] = {
335 0xff, 0x0f, 0xff, 0x00, 0xff, 0xcc, 0xc3, 0xcc,
336 0xc3, 0x3c, 0xcc, 0xff, 0xfe, 0xff, 0xfe, 0xef,
337 0xff, 0xdf, 0xff, 0xdd, 0xff, 0xfb, 0xff, 0xfb,
338 0xbf, 0xff, 0x7f, 0xff, 0x77, 0xf7, 0xbd, 0xef,
339 0xff, 0xf0, 0xff, 0xf0, 0x0f, 0xfc, 0xcc, 0x3c,
340 0xcc, 0x33, 0xcc, 0xcf, 0xff, 0xef, 0xff, 0xee,
341 0xff, 0xfd, 0xff, 0xfd, 0xdf, 0xff, 0xbf, 0xff,
342 0xbb, 0xff, 0xf7, 0xff, 0xf7, 0x7f, 0x7b, 0xde,
343};
344
345static const u8 tuning_blk_pattern_8bit[] = {
346 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00, 0x00,
347 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc, 0xcc,
348 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff, 0xff,
349 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee, 0xff,
350 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd, 0xdd,
351 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff, 0xbb,
352 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff, 0xff,
353 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee, 0xff,
354 0xff, 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00,
355 0x00, 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc,
356 0xcc, 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff,
357 0xff, 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee,
358 0xff, 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd,
359 0xdd, 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff,
360 0xbb, 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff,
361 0xff, 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee,
362};
363
a3b27866 364int mmc_send_tuning(struct mmc *mmc, u32 opcode)
9815e3ba
JJH		 365{
366 struct mmc_cmd cmd;
367 struct mmc_data data;
368 const u8 *tuning_block_pattern;
369 int size, err;
370
371 if (mmc->bus_width == 8) {
372 tuning_block_pattern = tuning_blk_pattern_8bit;
373 size = sizeof(tuning_blk_pattern_8bit);
374 } else if (mmc->bus_width == 4) {
375 tuning_block_pattern = tuning_blk_pattern_4bit;
376 size = sizeof(tuning_blk_pattern_4bit);
377 } else {
378 return -EINVAL;
379 }
380
381 ALLOC_CACHE_ALIGN_BUFFER(u8, data_buf, size);
382
383 cmd.cmdidx = opcode;
384 cmd.cmdarg = 0;
385 cmd.resp_type = MMC_RSP_R1;
386
387 data.dest = (void *)data_buf;
388 data.blocks = 1;
389 data.blocksize = size;
390 data.flags = MMC_DATA_READ;
391
392 err = mmc_send_cmd(mmc, &cmd, &data);
393 if (err)
394 return err;
395
396 if (memcmp(data_buf, tuning_block_pattern, size))
397 return -EIO;
398
399 return 0;
400}
f99c2efe 401#endif
9815e3ba 402
0ac2cca3
HP		 403int mmc_send_stop_transmission(struct mmc *mmc, bool write)
404{
405 struct mmc_cmd cmd;
406
407 cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
408 cmd.cmdarg = 0;
409 /*
410 * JEDEC Standard No. 84-B51 Page 126
411 * CMD12 STOP_TRANSMISSION R1/R1b[3]
412 * NOTE 3 R1 for read cases and R1b for write cases.
413 *
414 * Physical Layer Simplified Specification Version 9.00
415 * 7.3.1.3 Detailed Command Description
416 * CMD12 R1b
417 */
418 cmd.resp_type = (IS_SD(mmc) || write) ? MMC_RSP_R1b : MMC_RSP_R1;
419
420 return mmc_send_cmd(mmc, &cmd, NULL);
421}
422
ff8fef56 423static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start,
fdbb873e 424 lbaint_t blkcnt)
272cc70b
AF		 425{
426 struct mmc_cmd cmd;
427 struct mmc_data data;
428
4a1a06bc
AS		 429 if (blkcnt > 1)
430 cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK;
431 else
432 cmd.cmdidx = MMC_CMD_READ_SINGLE_BLOCK;
272cc70b
AF		 433
434 if (mmc->high_capacity)
4a1a06bc 435 cmd.cmdarg = start;
272cc70b 436 else
4a1a06bc 437 cmd.cmdarg = start * mmc->read_bl_len;
272cc70b
AF		 438
439 cmd.resp_type = MMC_RSP_R1;
272cc70b
AF		 440
441 data.dest = dst;
4a1a06bc 442 data.blocks = blkcnt;
272cc70b
AF		 443 data.blocksize = mmc->read_bl_len;
444 data.flags = MMC_DATA_READ;
445
4a1a06bc
AS		 446 if (mmc_send_cmd(mmc, &cmd, &data))
447 return 0;
272cc70b 448
4a1a06bc 449 if (blkcnt > 1) {
0ac2cca3 450 if (mmc_send_stop_transmission(mmc, false)) {
56196826 451#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
d8e3d420 452 pr_err("mmc fail to send stop cmd\n");
56196826 453#endif
4a1a06bc
AS		 454 return 0;
455 }
272cc70b
AF		 456 }
457
4a1a06bc 458 return blkcnt;
272cc70b
AF		 459}
460
145429aa
MV		 461#if !CONFIG_IS_ENABLED(DM_MMC)
462static int mmc_get_b_max(struct mmc *mmc, void *dst, lbaint_t blkcnt)
463{
464 if (mmc->cfg->ops->get_b_max)
465 return mmc->cfg->ops->get_b_max(mmc, dst, blkcnt);
466 else
467 return mmc->cfg->b_max;
468}
469#endif
470
c4d660d4 471#if CONFIG_IS_ENABLED(BLK)
7dba0b93 472ulong mmc_bread(struct udevice *dev, lbaint_t start, lbaint_t blkcnt, void *dst)
33fb211d 473#else
7dba0b93
SG		 474ulong mmc_bread(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt,
475 void *dst)
33fb211d 476#endif
272cc70b 477{
c4d660d4 478#if CONFIG_IS_ENABLED(BLK)
caa4daa2 479 struct blk_desc *block_dev = dev_get_uclass_plat(dev);
33fb211d 480#endif
bcce53d0 481 int dev_num = block_dev->devnum;
873cc1d7 482 int err;
4a1a06bc 483 lbaint_t cur, blocks_todo = blkcnt;
145429aa 484 uint b_max;
4a1a06bc
AS		 485
486 if (blkcnt == 0)
487 return 0;
272cc70b 488
4a1a06bc 489 struct mmc *mmc = find_mmc_device(dev_num);
272cc70b
AF		 490 if (!mmc)
491 return 0;
492
b5b838f1
MV		 493 if (CONFIG_IS_ENABLED(MMC_TINY))
494 err = mmc_switch_part(mmc, block_dev->hwpart);
495 else
496 err = blk_dselect_hwpart(block_dev, block_dev->hwpart);
497
873cc1d7
SW		 498 if (err < 0)
499 return 0;
500
c40fdca6 501 if ((start + blkcnt) > block_dev->lba) {
56196826 502#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
d8e3d420
JJH		 503 pr_err("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n",
504 start + blkcnt, block_dev->lba);
56196826 505#endif
d2bf29e3
LW		 506 return 0;
507 }
272cc70b 508
11692991 509 if (mmc_set_blocklen(mmc, mmc->read_bl_len)) {
d4d64889 510 pr_debug("%s: Failed to set blocklen\n", __func__);
272cc70b 511 return 0;
11692991 512 }
272cc70b 513
145429aa
MV		 514 b_max = mmc_get_b_max(mmc, dst, blkcnt);
515
4a1a06bc 516 do {
145429aa 517 cur = (blocks_todo > b_max) ? b_max : blocks_todo;
11692991 518 if (mmc_read_blocks(mmc, dst, start, cur) != cur) {
d4d64889 519 pr_debug("%s: Failed to read blocks\n", __func__);
4a1a06bc 520 return 0;
11692991 521 }
4a1a06bc
AS		 522 blocks_todo -= cur;
523 start += cur;
524 dst += cur * mmc->read_bl_len;
525 } while (blocks_todo > 0);
272cc70b
AF		 526
527 return blkcnt;
528}
529
fdbb873e 530static int mmc_go_idle(struct mmc *mmc)
272cc70b
AF		 531{
532 struct mmc_cmd cmd;
533 int err;
534
535 udelay(1000);
536
537 cmd.cmdidx = MMC_CMD_GO_IDLE_STATE;
538 cmd.cmdarg = 0;
539 cmd.resp_type = MMC_RSP_NONE;
272cc70b
AF		 540
541 err = mmc_send_cmd(mmc, &cmd, NULL);
542
543 if (err)
544 return err;
545
546 udelay(2000);
547
548 return 0;
549}
550
f99c2efe 551#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
c10b85d6
JJH		 552static int mmc_switch_voltage(struct mmc *mmc, int signal_voltage)
553{
554 struct mmc_cmd cmd;
555 int err = 0;
556
557 /*
558 * Send CMD11 only if the request is to switch the card to
559 * 1.8V signalling.
560 */
561 if (signal_voltage == MMC_SIGNAL_VOLTAGE_330)
562 return mmc_set_signal_voltage(mmc, signal_voltage);
563
564 cmd.cmdidx = SD_CMD_SWITCH_UHS18V;
565 cmd.cmdarg = 0;
566 cmd.resp_type = MMC_RSP_R1;
567
568 err = mmc_send_cmd(mmc, &cmd, NULL);
569 if (err)
570 return err;
571
572 if (!mmc_host_is_spi(mmc) && (cmd.response[0] & MMC_STATUS_ERROR))
573 return -EIO;
574
575 /*
576 * The card should drive cmd and dat[0:3] low immediately
577 * after the response of cmd11, but wait 100 us to be sure
578 */
579 err = mmc_wait_dat0(mmc, 0, 100);
580 if (err == -ENOSYS)
581 udelay(100);
582 else if (err)
583 return -ETIMEDOUT;
584
585 /*
586 * During a signal voltage level switch, the clock must be gated
587 * for 5 ms according to the SD spec
588 */
65117182 589 mmc_set_clock(mmc, mmc->clock, MMC_CLK_DISABLE);
c10b85d6
JJH		 590
591 err = mmc_set_signal_voltage(mmc, signal_voltage);
592 if (err)
593 return err;
594
595 /* Keep clock gated for at least 10 ms, though spec only says 5 ms */
596 mdelay(10);
65117182 597 mmc_set_clock(mmc, mmc->clock, MMC_CLK_ENABLE);
c10b85d6
JJH		 598
599 /*
600 * Failure to switch is indicated by the card holding
601 * dat[0:3] low. Wait for at least 1 ms according to spec
602 */
603 err = mmc_wait_dat0(mmc, 1, 1000);
604 if (err == -ENOSYS)
605 udelay(1000);
606 else if (err)
607 return -ETIMEDOUT;
608
609 return 0;
610}
f99c2efe 611#endif
c10b85d6
JJH		 612
613static int sd_send_op_cond(struct mmc *mmc, bool uhs_en)
272cc70b
AF		 614{
615 int timeout = 1000;
616 int err;
617 struct mmc_cmd cmd;
618
1677eef4 619 while (1) {
272cc70b
AF		 620 cmd.cmdidx = MMC_CMD_APP_CMD;
621 cmd.resp_type = MMC_RSP_R1;
622 cmd.cmdarg = 0;
272cc70b
AF		 623
624 err = mmc_send_cmd(mmc, &cmd, NULL);
625
626 if (err)
627 return err;
628
629 cmd.cmdidx = SD_CMD_APP_SEND_OP_COND;
630 cmd.resp_type = MMC_RSP_R3;
250de12b
SB		 631
632 /*
633 * Most cards do not answer if some reserved bits
634 * in the ocr are set. However, Some controller
635 * can set bit 7 (reserved for low voltages), but
636 * how to manage low voltages SD card is not yet
637 * specified.
638 */
d52ebf10 639 cmd.cmdarg = mmc_host_is_spi(mmc) ? 0 :
93bfd616 640 (mmc->cfg->voltages & 0xff8000);
272cc70b
AF		 641
642 if (mmc->version == SD_VERSION_2)
643 cmd.cmdarg |= OCR_HCS;
644
c10b85d6
JJH		 645 if (uhs_en)
646 cmd.cmdarg |= OCR_S18R;
647
272cc70b
AF		 648 err = mmc_send_cmd(mmc, &cmd, NULL);
649
650 if (err)
651 return err;
652
1677eef4
AG		 653 if (cmd.response[0] & OCR_BUSY)
654 break;
655
656 if (timeout-- <= 0)
915ffa52 657 return -EOPNOTSUPP;
272cc70b 658
1677eef4
AG		 659 udelay(1000);
660 }
272cc70b
AF		 661
662 if (mmc->version != SD_VERSION_2)
663 mmc->version = SD_VERSION_1_0;
664
d52ebf10
TC		 665 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
666 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
667 cmd.resp_type = MMC_RSP_R3;
668 cmd.cmdarg = 0;
d52ebf10
TC		 669
670 err = mmc_send_cmd(mmc, &cmd, NULL);
671
672 if (err)
673 return err;
674 }
675
998be3dd 676 mmc->ocr = cmd.response[0];
272cc70b 677
f99c2efe 678#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
c10b85d6
JJH		 679 if (uhs_en && !(mmc_host_is_spi(mmc)) && (cmd.response[0] & 0x41000000)
680 == 0x41000000) {
681 err = mmc_switch_voltage(mmc, MMC_SIGNAL_VOLTAGE_180);
682 if (err)
683 return err;
684 }
f99c2efe 685#endif
c10b85d6 686
272cc70b
AF		 687 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
688 mmc->rca = 0;
689
690 return 0;
691}
692
5289b535 693static int mmc_send_op_cond_iter(struct mmc *mmc, int use_arg)
272cc70b 694{
5289b535 695 struct mmc_cmd cmd;
272cc70b
AF		 696 int err;
697
5289b535
AG		 698 cmd.cmdidx = MMC_CMD_SEND_OP_COND;
699 cmd.resp_type = MMC_RSP_R3;
700 cmd.cmdarg = 0;
5a20397b
RH		 701 if (use_arg && !mmc_host_is_spi(mmc))
702 cmd.cmdarg = OCR_HCS |
93bfd616 703 (mmc->cfg->voltages &
a626c8d4
AG		 704 (mmc->ocr & OCR_VOLTAGE_MASK)) |
705 (mmc->ocr & OCR_ACCESS_MODE);
e9550449 706
5289b535 707 err = mmc_send_cmd(mmc, &cmd, NULL);
e9550449
CLC		 708 if (err)
709 return err;
5289b535 710 mmc->ocr = cmd.response[0];
e9550449
CLC		 711 return 0;
712}
713
750121c3 714static int mmc_send_op_cond(struct mmc *mmc)
e9550449 715{
e9550449 716 int err, i;
fe95905f
HC		 717 int timeout = 1000;
718 uint start;
e9550449 719
272cc70b
AF		 720 /* Some cards seem to need this */
721 mmc_go_idle(mmc);
722
fe95905f 723 start = get_timer(0);
0cf207ec 724 /* Asking to the card its capabilities */
fe95905f 725 for (i = 0; ; i++) {
5289b535 726 err = mmc_send_op_cond_iter(mmc, i != 0);
e9550449
CLC		 727 if (err)
728 return err;
cd6881b5 729
e9550449 730 /* exit if not busy (flag seems to be inverted) */
a626c8d4 731 if (mmc->ocr & OCR_BUSY)
bd47c135 732 break;
fe95905f
HC		 733
734 if (get_timer(start) > timeout)
735 return -ETIMEDOUT;
736 udelay(100);
e9550449 737 }
bd47c135
AG		 738 mmc->op_cond_pending = 1;
739 return 0;
e9550449 740}
cd6881b5 741
750121c3 742static int mmc_complete_op_cond(struct mmc *mmc)
e9550449
CLC		 743{
744 struct mmc_cmd cmd;
745 int timeout = 1000;
36332b6e 746 ulong start;
e9550449 747 int err;
cd6881b5 748
e9550449 749 mmc->op_cond_pending = 0;
cc17c01f 750 if (!(mmc->ocr & OCR_BUSY)) {
d188b113
YL		 751 /* Some cards seem to need this */
752 mmc_go_idle(mmc);
753
cc17c01f 754 start = get_timer(0);
1677eef4 755 while (1) {
cc17c01f
AG		 756 err = mmc_send_op_cond_iter(mmc, 1);
757 if (err)
758 return err;
1677eef4
AG		 759 if (mmc->ocr & OCR_BUSY)
760 break;
cc17c01f 761 if (get_timer(start) > timeout)
915ffa52 762 return -EOPNOTSUPP;
cc17c01f 763 udelay(100);
1677eef4 764 }
cc17c01f 765 }
272cc70b 766
d52ebf10
TC		 767 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
768 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
769 cmd.resp_type = MMC_RSP_R3;
770 cmd.cmdarg = 0;
d52ebf10
TC		 771
772 err = mmc_send_cmd(mmc, &cmd, NULL);
773
774 if (err)
775 return err;
a626c8d4
AG		 776
777 mmc->ocr = cmd.response[0];
d52ebf10
TC		 778 }
779
272cc70b 780 mmc->version = MMC_VERSION_UNKNOWN;
272cc70b
AF		 781
782 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
def816a2 783 mmc->rca = 1;
272cc70b
AF		 784
785 return 0;
786}
787
788
1601ea21 789int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd)
272cc70b
AF		 790{
791 struct mmc_cmd cmd;
792 struct mmc_data data;
793 int err;
794
795 /* Get the Card Status Register */
796 cmd.cmdidx = MMC_CMD_SEND_EXT_CSD;
797 cmd.resp_type = MMC_RSP_R1;
798 cmd.cmdarg = 0;
272cc70b 799
cdfd1ac6 800 data.dest = (char *)ext_csd;
272cc70b 801 data.blocks = 1;
8bfa195e 802 data.blocksize = MMC_MAX_BLOCK_LEN;
272cc70b
AF		 803 data.flags = MMC_DATA_READ;
804
805 err = mmc_send_cmd(mmc, &cmd, &data);
806
807 return err;
808}
809
6892550c
MV		 810static int __mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value,
811 bool send_status)
272cc70b 812{
bb98b8c5 813 unsigned int status, start;
272cc70b 814 struct mmc_cmd cmd;
6cf8a903 815 int timeout_ms = DEFAULT_CMD6_TIMEOUT_MS;
513e00b6
JJH		 816 bool is_part_switch = (set == EXT_CSD_CMD_SET_NORMAL) &&
817 (index == EXT_CSD_PART_CONF);
5d4fc8d9 818 int ret;
272cc70b 819
39320c53 820 if (mmc->gen_cmd6_time)
6cf8a903 821 timeout_ms = mmc->gen_cmd6_time * 10;
39320c53 822
513e00b6 823 if (is_part_switch && mmc->part_switch_time)
6cf8a903 824 timeout_ms = mmc->part_switch_time * 10;
513e00b6 825
272cc70b
AF		 826 cmd.cmdidx = MMC_CMD_SWITCH;
827 cmd.resp_type = MMC_RSP_R1b;
828 cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) |
5d4fc8d9
RR		 829 (index << 16) |
830 (value << 8);
272cc70b 831
da129170 832 ret = mmc_send_cmd_retry(mmc, &cmd, NULL, 3);
bb98b8c5
JJH		 833 if (ret)
834 return ret;
6892550c 835
bb98b8c5 836 start = get_timer(0);
a9003dc6 837
bb98b8c5 838 /* poll dat0 for rdy/buys status */
6cf8a903 839 ret = mmc_wait_dat0(mmc, 1, timeout_ms * 1000);
bb98b8c5
JJH		 840 if (ret && ret != -ENOSYS)
841 return ret;
5d4fc8d9 842
bb98b8c5 843 /*
44645f87 844 * In cases when neiter allowed to poll by using CMD13 nor we are
bb98b8c5
JJH		 845 * capable of polling by using mmc_wait_dat0, then rely on waiting the
846 * stated timeout to be sufficient.
847 */
44645f87 848 if (ret == -ENOSYS && !send_status) {
6cf8a903 849 mdelay(timeout_ms);
ef5ab0d1
HC		 850 return 0;
851 }
bb98b8c5 852
2349ecff
MV		 853 if (!send_status)
854 return 0;
855
bb98b8c5
JJH		 856 /* Finally wait until the card is ready or indicates a failure
857 * to switch. It doesn't hurt to use CMD13 here even if send_status
6cf8a903 858 * is false, because by now (after 'timeout_ms' ms) the bus should be
bb98b8c5
JJH		 859 * reliable.
860 */
861 do {
862 ret = mmc_send_status(mmc, &status);
863
864 if (!ret && (status & MMC_STATUS_SWITCH_ERROR)) {
865 pr_debug("switch failed %d/%d/0x%x !\n", set, index,
866 value);
867 return -EIO;
868 }
8e2b0af7
SB		 869 if (!ret && (status & MMC_STATUS_RDY_FOR_DATA) &&
870 (status & MMC_STATUS_CURR_STATE) == MMC_STATE_TRANS)
bb98b8c5
JJH		 871 return 0;
872 udelay(100);
6cf8a903 873 } while (get_timer(start) < timeout_ms);
5d4fc8d9 874
bb98b8c5 875 return -ETIMEDOUT;
272cc70b
AF		 876}
877
6892550c
MV		 878int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value)
879{
880 return __mmc_switch(mmc, set, index, value, true);
881}
882
0469d846
HS		 883int mmc_boot_wp(struct mmc *mmc)
884{
885 return mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BOOT_WP, 1);
886}
887
19a29ff3
YCLP		 888int mmc_boot_wp_single_partition(struct mmc *mmc, int partition)
889{
890 u8 value;
891 int ret;
892
893 value = EXT_CSD_BOOT_WP_B_PWR_WP_EN;
894
895 if (partition == 0) {
896 value |= EXT_CSD_BOOT_WP_B_SEC_WP_SEL;
897 ret = mmc_switch(mmc,
898 EXT_CSD_CMD_SET_NORMAL,
899 EXT_CSD_BOOT_WP,
900 value);
901 } else if (partition == 1) {
902 value |= EXT_CSD_BOOT_WP_B_SEC_WP_SEL;
903 value |= EXT_CSD_BOOT_WP_B_PWR_WP_SEC_SEL;
904 ret = mmc_switch(mmc,
905 EXT_CSD_CMD_SET_NORMAL,
906 EXT_CSD_BOOT_WP,
907 value);
908 } else {
909 ret = mmc_boot_wp(mmc);
910 }
911
912 return ret;
913}
914
62d77cea 915#if !CONFIG_IS_ENABLED(MMC_TINY)
b9a2a0e2
MV		 916static int mmc_set_card_speed(struct mmc *mmc, enum bus_mode mode,
917 bool hsdowngrade)
272cc70b 918{
272cc70b 919 int err;
3862b854
JJH		 920 int speed_bits;
921
922 ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
923
924 switch (mode) {
925 case MMC_HS:
926 case MMC_HS_52:
927 case MMC_DDR_52:
928 speed_bits = EXT_CSD_TIMING_HS;
634d4849 929 break;
baef2070 930#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
634d4849
KVA		 931 case MMC_HS_200:
932 speed_bits = EXT_CSD_TIMING_HS200;
933 break;
3dd2626f
PF		 934#endif
935#if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
936 case MMC_HS_400:
937 speed_bits = EXT_CSD_TIMING_HS400;
938 break;
44acd492
PF		 939#endif
940#if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
941 case MMC_HS_400_ES:
942 speed_bits = EXT_CSD_TIMING_HS400;
943 break;
baef2070 944#endif
3862b854
JJH		 945 case MMC_LEGACY:
946 speed_bits = EXT_CSD_TIMING_LEGACY;
947 break;
948 default:
949 return -EINVAL;
950 }
6892550c
MV		 951
952 err = __mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING,
953 speed_bits, !hsdowngrade);
3862b854
JJH		 954 if (err)
955 return err;
956
b9a2a0e2
MV		 957#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
958 CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
959 /*
960 * In case the eMMC is in HS200/HS400 mode and we are downgrading
961 * to HS mode, the card clock are still running much faster than
962 * the supported HS mode clock, so we can not reliably read out
963 * Extended CSD. Reconfigure the controller to run at HS mode.
964 */
965 if (hsdowngrade) {
966 mmc_select_mode(mmc, MMC_HS);
967 mmc_set_clock(mmc, mmc_mode2freq(mmc, MMC_HS), false);
968 }
969#endif
970
3862b854
JJH		 971 if ((mode == MMC_HS) || (mode == MMC_HS_52)) {
972 /* Now check to see that it worked */
973 err = mmc_send_ext_csd(mmc, test_csd);
974 if (err)
975 return err;
976
977 /* No high-speed support */
978 if (!test_csd[EXT_CSD_HS_TIMING])
979 return -ENOTSUPP;
980 }
981
982 return 0;
983}
984
985static int mmc_get_capabilities(struct mmc *mmc)
986{
987 u8 *ext_csd = mmc->ext_csd;
988 char cardtype;
272cc70b 989
00e446fa 990 mmc->card_caps = MMC_MODE_1BIT | MMC_CAP(MMC_LEGACY);
272cc70b 991
d52ebf10
TC		 992 if (mmc_host_is_spi(mmc))
993 return 0;
994
272cc70b
AF		 995 /* Only version 4 supports high-speed */
996 if (mmc->version < MMC_VERSION_4)
997 return 0;
998
3862b854 999 if (!ext_csd) {
d8e3d420 1000 pr_err("No ext_csd found!\n"); /* this should enver happen */
3862b854
JJH		 1001 return -ENOTSUPP;
1002 }
272cc70b 1003
3862b854 1004 mmc->card_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT;
272cc70b 1005
3dd2626f 1006 cardtype = ext_csd[EXT_CSD_CARD_TYPE];
bc1e3272 1007 mmc->cardtype = cardtype;
272cc70b 1008
baef2070 1009#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
634d4849
KVA		 1010 if (cardtype & (EXT_CSD_CARD_TYPE_HS200_1_2V |
1011 EXT_CSD_CARD_TYPE_HS200_1_8V)) {
1012 mmc->card_caps |= MMC_MODE_HS200;
1013 }
3dd2626f 1014#endif
44acd492
PF		 1015#if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT) || \
1016 CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
3dd2626f
PF		 1017 if (cardtype & (EXT_CSD_CARD_TYPE_HS400_1_2V |
1018 EXT_CSD_CARD_TYPE_HS400_1_8V)) {
1019 mmc->card_caps |= MMC_MODE_HS400;
1020 }
baef2070 1021#endif
d22e3d46 1022 if (cardtype & EXT_CSD_CARD_TYPE_52) {
3862b854 1023 if (cardtype & EXT_CSD_CARD_TYPE_DDR_52)
d22e3d46 1024 mmc->card_caps |= MMC_MODE_DDR_52MHz;
3862b854 1025 mmc->card_caps |= MMC_MODE_HS_52MHz;
d22e3d46 1026 }
3862b854
JJH		 1027 if (cardtype & EXT_CSD_CARD_TYPE_26)
1028 mmc->card_caps |= MMC_MODE_HS;
272cc70b 1029
44acd492
PF		 1030#if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
1031 if (ext_csd[EXT_CSD_STROBE_SUPPORT] &&
1032 (mmc->card_caps & MMC_MODE_HS400)) {
1033 mmc->card_caps |= MMC_MODE_HS400_ES;
1034 }
1035#endif
1036
272cc70b
AF		 1037 return 0;
1038}
62d77cea 1039#endif
272cc70b 1040
f866a46d
SW		 1041static int mmc_set_capacity(struct mmc *mmc, int part_num)
1042{
1043 switch (part_num) {
1044 case 0:
1045 mmc->capacity = mmc->capacity_user;
1046 break;
1047 case 1:
1048 case 2:
1049 mmc->capacity = mmc->capacity_boot;
1050 break;
1051 case 3:
1052 mmc->capacity = mmc->capacity_rpmb;
1053 break;
1054 case 4:
1055 case 5:
1056 case 6:
1057 case 7:
1058 mmc->capacity = mmc->capacity_gp[part_num - 4];
1059 break;
1060 default:
1061 return -1;
1062 }
1063
c40fdca6 1064 mmc_get_blk_desc(mmc)->lba = lldiv(mmc->capacity, mmc->read_bl_len);
f866a46d
SW		 1065
1066 return 0;
1067}
1068
7dba0b93 1069int mmc_switch_part(struct mmc *mmc, unsigned int part_num)
bc897b1d 1070{
f866a46d 1071 int ret;
0538477c 1072 int retry = 3;
bc897b1d 1073
0538477c
JJH		 1074 do {
1075 ret = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1076 EXT_CSD_PART_CONF,
1077 (mmc->part_config & ~PART_ACCESS_MASK)
1078 | (part_num & PART_ACCESS_MASK));
1079 } while (ret && retry--);
f866a46d 1080
6dc93e70
PB		 1081 /*
1082 * Set the capacity if the switch succeeded or was intended
1083 * to return to representing the raw device.
1084 */
873cc1d7 1085 if ((ret == 0) || ((ret == -ENODEV) && (part_num == 0))) {
6dc93e70 1086 ret = mmc_set_capacity(mmc, part_num);
fdbb139f 1087 mmc_get_blk_desc(mmc)->hwpart = part_num;
873cc1d7 1088 }
6dc93e70
PB		 1089
1090 return ret;
bc897b1d
LW		 1091}
1092
cf17789e 1093#if CONFIG_IS_ENABLED(MMC_HW_PARTITIONING)
ac9da0e0
DSC		 1094int mmc_hwpart_config(struct mmc *mmc,
1095 const struct mmc_hwpart_conf *conf,
1096 enum mmc_hwpart_conf_mode mode)
1097{
1098 u8 part_attrs = 0;
1099 u32 enh_size_mult;
1100 u32 enh_start_addr;
1101 u32 gp_size_mult[4];
1102 u32 max_enh_size_mult;
1103 u32 tot_enh_size_mult = 0;
8dda5b0e 1104 u8 wr_rel_set;
ac9da0e0
DSC		 1105 int i, pidx, err;
1106 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
1107
1108 if (mode < MMC_HWPART_CONF_CHECK || mode > MMC_HWPART_CONF_COMPLETE)
1109 return -EINVAL;
1110
1111 if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4_41)) {
d8e3d420 1112 pr_err("eMMC >= 4.4 required for enhanced user data area\n");
ac9da0e0
DSC		 1113 return -EMEDIUMTYPE;
1114 }
1115
1116 if (!(mmc->part_support & PART_SUPPORT)) {
d8e3d420 1117 pr_err("Card does not support partitioning\n");
ac9da0e0
DSC		 1118 return -EMEDIUMTYPE;
1119 }
1120
1121 if (!mmc->hc_wp_grp_size) {
d8e3d420 1122 pr_err("Card does not define HC WP group size\n");
ac9da0e0
DSC		 1123 return -EMEDIUMTYPE;
1124 }
1125
1126 /* check partition alignment and total enhanced size */
1127 if (conf->user.enh_size) {
1128 if (conf->user.enh_size % mmc->hc_wp_grp_size ||
1129 conf->user.enh_start % mmc->hc_wp_grp_size) {
d8e3d420 1130 pr_err("User data enhanced area not HC WP group "
ac9da0e0
DSC		 1131 "size aligned\n");
1132 return -EINVAL;
1133 }
1134 part_attrs |= EXT_CSD_ENH_USR;
1135 enh_size_mult = conf->user.enh_size / mmc->hc_wp_grp_size;
1136 if (mmc->high_capacity) {
1137 enh_start_addr = conf->user.enh_start;
1138 } else {
1139 enh_start_addr = (conf->user.enh_start << 9);
1140 }
1141 } else {
1142 enh_size_mult = 0;
1143 enh_start_addr = 0;
1144 }
1145 tot_enh_size_mult += enh_size_mult;
1146
1147 for (pidx = 0; pidx < 4; pidx++) {
1148 if (conf->gp_part[pidx].size % mmc->hc_wp_grp_size) {
d8e3d420 1149 pr_err("GP%i partition not HC WP group size "
ac9da0e0
DSC		 1150 "aligned\n", pidx+1);
1151 return -EINVAL;
1152 }
1153 gp_size_mult[pidx] = conf->gp_part[pidx].size / mmc->hc_wp_grp_size;
1154 if (conf->gp_part[pidx].size && conf->gp_part[pidx].enhanced) {
1155 part_attrs |= EXT_CSD_ENH_GP(pidx);
1156 tot_enh_size_mult += gp_size_mult[pidx];
1157 }
1158 }
1159
1160 if (part_attrs && ! (mmc->part_support & ENHNCD_SUPPORT)) {
d8e3d420 1161 pr_err("Card does not support enhanced attribute\n");
ac9da0e0
DSC		 1162 return -EMEDIUMTYPE;
1163 }
1164
1165 err = mmc_send_ext_csd(mmc, ext_csd);
1166 if (err)
1167 return err;
1168
1169 max_enh_size_mult =
1170 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+2] << 16) +
1171 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+1] << 8) +
1172 ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT];
1173 if (tot_enh_size_mult > max_enh_size_mult) {
d8e3d420 1174 pr_err("Total enhanced size exceeds maximum (%u > %u)\n",
ac9da0e0
DSC		 1175 tot_enh_size_mult, max_enh_size_mult);
1176 return -EMEDIUMTYPE;
1177 }
1178
8dda5b0e
DSC		 1179 /* The default value of EXT_CSD_WR_REL_SET is device
1180 * dependent, the values can only be changed if the
1181 * EXT_CSD_HS_CTRL_REL bit is set. The values can be
1182 * changed only once and before partitioning is completed. */
1183 wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
1184 if (conf->user.wr_rel_change) {
1185 if (conf->user.wr_rel_set)
1186 wr_rel_set |= EXT_CSD_WR_DATA_REL_USR;
1187 else
1188 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_USR;
1189 }
1190 for (pidx = 0; pidx < 4; pidx++) {
1191 if (conf->gp_part[pidx].wr_rel_change) {
1192 if (conf->gp_part[pidx].wr_rel_set)
1193 wr_rel_set |= EXT_CSD_WR_DATA_REL_GP(pidx);
1194 else
1195 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_GP(pidx);
1196 }
1197 }
1198
1199 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET] &&
1200 !(ext_csd[EXT_CSD_WR_REL_PARAM] & EXT_CSD_HS_CTRL_REL)) {
1201 puts("Card does not support host controlled partition write "
1202 "reliability settings\n");
1203 return -EMEDIUMTYPE;
1204 }
1205
ac9da0e0
DSC		 1206 if (ext_csd[EXT_CSD_PARTITION_SETTING] &
1207 EXT_CSD_PARTITION_SETTING_COMPLETED) {
d8e3d420 1208 pr_err("Card already partitioned\n");
ac9da0e0
DSC		 1209 return -EPERM;
1210 }
1211
1212 if (mode == MMC_HWPART_CONF_CHECK)
1213 return 0;
1214
1215 /* Partitioning requires high-capacity size definitions */
1216 if (!(ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01)) {
1217 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1218 EXT_CSD_ERASE_GROUP_DEF, 1);
1219
1220 if (err)
1221 return err;
1222
1223 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
1224
4af66596 1225#if CONFIG_IS_ENABLED(MMC_WRITE)
ac9da0e0
DSC		 1226 /* update erase group size to be high-capacity */
1227 mmc->erase_grp_size =
1228 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
4af66596 1229#endif
ac9da0e0
DSC		 1230
1231 }
1232
1233 /* all OK, write the configuration */
1234 for (i = 0; i < 4; i++) {
1235 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1236 EXT_CSD_ENH_START_ADDR+i,
1237 (enh_start_addr >> (i*8)) & 0xFF);
1238 if (err)
1239 return err;
1240 }
1241 for (i = 0; i < 3; i++) {
1242 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1243 EXT_CSD_ENH_SIZE_MULT+i,
1244 (enh_size_mult >> (i*8)) & 0xFF);
1245 if (err)
1246 return err;
1247 }
1248 for (pidx = 0; pidx < 4; pidx++) {
1249 for (i = 0; i < 3; i++) {
1250 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1251 EXT_CSD_GP_SIZE_MULT+pidx*3+i,
1252 (gp_size_mult[pidx] >> (i*8)) & 0xFF);
1253 if (err)
1254 return err;
1255 }
1256 }
1257 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1258 EXT_CSD_PARTITIONS_ATTRIBUTE, part_attrs);
1259 if (err)
1260 return err;
1261
1262 if (mode == MMC_HWPART_CONF_SET)
1263 return 0;
1264
8dda5b0e
DSC		 1265 /* The WR_REL_SET is a write-once register but shall be
1266 * written before setting PART_SETTING_COMPLETED. As it is
1267 * write-once we can only write it when completing the
1268 * partitioning. */
1269 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET]) {
1270 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1271 EXT_CSD_WR_REL_SET, wr_rel_set);
1272 if (err)
1273 return err;
1274 }
1275
ac9da0e0
DSC		 1276 /* Setting PART_SETTING_COMPLETED confirms the partition
1277 * configuration but it only becomes effective after power
1278 * cycle, so we do not adjust the partition related settings
1279 * in the mmc struct. */
1280
1281 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1282 EXT_CSD_PARTITION_SETTING,
1283 EXT_CSD_PARTITION_SETTING_COMPLETED);
1284 if (err)
1285 return err;
1286
1287 return 0;
1288}
cf17789e 1289#endif
ac9da0e0 1290
e7881d85 1291#if !CONFIG_IS_ENABLED(DM_MMC)
48972d90
TR		 1292int mmc_getcd(struct mmc *mmc)
1293{
1294 int cd;
1295
1296 cd = board_mmc_getcd(mmc);
1297
d4e1da4e 1298 if (cd < 0) {
93bfd616
PA		 1299 if (mmc->cfg->ops->getcd)
1300 cd = mmc->cfg->ops->getcd(mmc);
d4e1da4e
PK		 1301 else
1302 cd = 1;
1303 }
48972d90
TR		 1304
1305 return cd;
1306}
8ca51e51 1307#endif
48972d90 1308
62d77cea 1309#if !CONFIG_IS_ENABLED(MMC_TINY)
fdbb873e 1310static int sd_switch(struct mmc *mmc, int mode, int group, u8 value, u8 *resp)
272cc70b
AF		 1311{
1312 struct mmc_cmd cmd;
1313 struct mmc_data data;
1314
1315 /* Switch the frequency */
1316 cmd.cmdidx = SD_CMD_SWITCH_FUNC;
1317 cmd.resp_type = MMC_RSP_R1;
1318 cmd.cmdarg = (mode << 31) | 0xffffff;
1319 cmd.cmdarg &= ~(0xf << (group * 4));
1320 cmd.cmdarg |= value << (group * 4);
272cc70b
AF		 1321
1322 data.dest = (char *)resp;
1323 data.blocksize = 64;
1324 data.blocks = 1;
1325 data.flags = MMC_DATA_READ;
1326
1327 return mmc_send_cmd(mmc, &cmd, &data);
1328}
1329
d0c221fe 1330static int sd_get_capabilities(struct mmc *mmc)
272cc70b
AF		 1331{
1332 int err;
1333 struct mmc_cmd cmd;
18e7c8f6
SM		 1334 ALLOC_CACHE_ALIGN_BUFFER(__be32, scr, 2);
1335 ALLOC_CACHE_ALIGN_BUFFER(__be32, switch_status, 16);
272cc70b
AF		 1336 struct mmc_data data;
1337 int timeout;
f99c2efe 1338#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
c10b85d6 1339 u32 sd3_bus_mode;
f99c2efe 1340#endif
272cc70b 1341
e8d5dde4 1342 mmc->card_caps = MMC_MODE_1BIT | MMC_CAP(MMC_LEGACY);
272cc70b 1343
d52ebf10
TC		 1344 if (mmc_host_is_spi(mmc))
1345 return 0;
1346
272cc70b
AF		 1347 /* Read the SCR to find out if this card supports higher speeds */
1348 cmd.cmdidx = MMC_CMD_APP_CMD;
1349 cmd.resp_type = MMC_RSP_R1;
1350 cmd.cmdarg = mmc->rca << 16;
272cc70b
AF		 1351
1352 err = mmc_send_cmd(mmc, &cmd, NULL);
1353
1354 if (err)
1355 return err;
1356
1357 cmd.cmdidx = SD_CMD_APP_SEND_SCR;
1358 cmd.resp_type = MMC_RSP_R1;
1359 cmd.cmdarg = 0;
272cc70b 1360
f781dd38 1361 data.dest = (char *)scr;
272cc70b
AF		 1362 data.blocksize = 8;
1363 data.blocks = 1;
1364 data.flags = MMC_DATA_READ;
1365
da129170 1366 err = mmc_send_cmd_retry(mmc, &cmd, &data, 3);
272cc70b 1367
da129170 1368 if (err)
272cc70b 1369 return err;
272cc70b 1370
4e3d89ba
YK		 1371 mmc->scr[0] = __be32_to_cpu(scr[0]);
1372 mmc->scr[1] = __be32_to_cpu(scr[1]);
272cc70b
AF		 1373
1374 switch ((mmc->scr[0] >> 24) & 0xf) {
53e8e40b
BM		 1375 case 0:
1376 mmc->version = SD_VERSION_1_0;
1377 break;
1378 case 1:
1379 mmc->version = SD_VERSION_1_10;
1380 break;
1381 case 2:
1382 mmc->version = SD_VERSION_2;
1383 if ((mmc->scr[0] >> 15) & 0x1)
1384 mmc->version = SD_VERSION_3;
1385 break;
1386 default:
1387 mmc->version = SD_VERSION_1_0;
1388 break;
272cc70b
AF		 1389 }
1390
b44c7083
AS		 1391 if (mmc->scr[0] & SD_DATA_4BIT)
1392 mmc->card_caps |= MMC_MODE_4BIT;
1393
272cc70b
AF		 1394 /* Version 1.0 doesn't support switching */
1395 if (mmc->version == SD_VERSION_1_0)
1396 return 0;
1397
1398 timeout = 4;
1399 while (timeout--) {
1400 err = sd_switch(mmc, SD_SWITCH_CHECK, 0, 1,
f781dd38 1401 (u8 *)switch_status);
272cc70b
AF		 1402
1403 if (err)
1404 return err;
1405
1406 /* The high-speed function is busy. Try again */
4e3d89ba 1407 if (!(__be32_to_cpu(switch_status[7]) & SD_HIGHSPEED_BUSY))
272cc70b
AF		 1408 break;
1409 }
1410
272cc70b 1411 /* If high-speed isn't supported, we return */
d0c221fe
JJH		 1412 if (__be32_to_cpu(switch_status[3]) & SD_HIGHSPEED_SUPPORTED)
1413 mmc->card_caps |= MMC_CAP(SD_HS);
272cc70b 1414
f99c2efe 1415#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
c10b85d6
JJH		 1416 /* Version before 3.0 don't support UHS modes */
1417 if (mmc->version < SD_VERSION_3)
1418 return 0;
1419
1420 sd3_bus_mode = __be32_to_cpu(switch_status[3]) >> 16 & 0x1f;
1421 if (sd3_bus_mode & SD_MODE_UHS_SDR104)
1422 mmc->card_caps |= MMC_CAP(UHS_SDR104);
1423 if (sd3_bus_mode & SD_MODE_UHS_SDR50)
1424 mmc->card_caps |= MMC_CAP(UHS_SDR50);
1425 if (sd3_bus_mode & SD_MODE_UHS_SDR25)
1426 mmc->card_caps |= MMC_CAP(UHS_SDR25);
1427 if (sd3_bus_mode & SD_MODE_UHS_SDR12)
1428 mmc->card_caps |= MMC_CAP(UHS_SDR12);
1429 if (sd3_bus_mode & SD_MODE_UHS_DDR50)
1430 mmc->card_caps |= MMC_CAP(UHS_DDR50);
f99c2efe 1431#endif
c10b85d6 1432
d0c221fe
JJH		 1433 return 0;
1434}
1435
1436static int sd_set_card_speed(struct mmc *mmc, enum bus_mode mode)
1437{
1438 int err;
1439
1440 ALLOC_CACHE_ALIGN_BUFFER(uint, switch_status, 16);
c10b85d6 1441 int speed;
2c3fbf4c 1442
cf345760
MV		 1443 /* SD version 1.00 and 1.01 does not support CMD 6 */
1444 if (mmc->version == SD_VERSION_1_0)
1445 return 0;
1446
c10b85d6 1447 switch (mode) {
e8d5dde4 1448 case MMC_LEGACY:
c10b85d6
JJH		 1449 speed = UHS_SDR12_BUS_SPEED;
1450 break;
1451 case SD_HS:
baef2070
JJH		 1452 speed = HIGH_SPEED_BUS_SPEED;
1453 break;
1454#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
1455 case UHS_SDR12:
1456 speed = UHS_SDR12_BUS_SPEED;
1457 break;
c10b85d6
JJH		 1458 case UHS_SDR25:
1459 speed = UHS_SDR25_BUS_SPEED;
1460 break;
1461 case UHS_SDR50:
1462 speed = UHS_SDR50_BUS_SPEED;
1463 break;
1464 case UHS_DDR50:
1465 speed = UHS_DDR50_BUS_SPEED;
1466 break;
1467 case UHS_SDR104:
1468 speed = UHS_SDR104_BUS_SPEED;
1469 break;
baef2070 1470#endif
c10b85d6
JJH		 1471 default:
1472 return -EINVAL;
1473 }
1474
1475 err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, speed, (u8 *)switch_status);
d0c221fe
JJH		 1476 if (err)
1477 return err;
1478
a0276f3e 1479 if (((__be32_to_cpu(switch_status[4]) >> 24) & 0xF) != speed)
d0c221fe 1480 return -ENOTSUPP;
272cc70b 1481
d0c221fe
JJH		 1482 return 0;
1483}
1484
ec360e64 1485static int sd_select_bus_width(struct mmc *mmc, int w)
d0c221fe
JJH		 1486{
1487 int err;
1488 struct mmc_cmd cmd;
1489
1490 if ((w != 4) && (w != 1))
1491 return -EINVAL;
1492
1493 cmd.cmdidx = MMC_CMD_APP_CMD;
1494 cmd.resp_type = MMC_RSP_R1;
1495 cmd.cmdarg = mmc->rca << 16;
1496
1497 err = mmc_send_cmd(mmc, &cmd, NULL);
272cc70b
AF		 1498 if (err)
1499 return err;
1500
d0c221fe
JJH		 1501 cmd.cmdidx = SD_CMD_APP_SET_BUS_WIDTH;
1502 cmd.resp_type = MMC_RSP_R1;
1503 if (w == 4)
1504 cmd.cmdarg = 2;
1505 else if (w == 1)
1506 cmd.cmdarg = 0;
1507 err = mmc_send_cmd(mmc, &cmd, NULL);
1508 if (err)
1509 return err;
272cc70b
AF		 1510
1511 return 0;
1512}
62d77cea 1513#endif
272cc70b 1514
5b2e72f3 1515#if CONFIG_IS_ENABLED(MMC_WRITE)
3697e599
PF		 1516static int sd_read_ssr(struct mmc *mmc)
1517{
5b2e72f3
JJH		 1518 static const unsigned int sd_au_size[] = {
1519 0, SZ_16K / 512, SZ_32K / 512,
1520 SZ_64K / 512, SZ_128K / 512, SZ_256K / 512,
1521 SZ_512K / 512, SZ_1M / 512, SZ_2M / 512,
1522 SZ_4M / 512, SZ_8M / 512, (SZ_8M + SZ_4M) / 512,
1523 SZ_16M / 512, (SZ_16M + SZ_8M) / 512, SZ_32M / 512,
1524 SZ_64M / 512,
1525 };
3697e599
PF		 1526 int err, i;
1527 struct mmc_cmd cmd;
1528 ALLOC_CACHE_ALIGN_BUFFER(uint, ssr, 16);
1529 struct mmc_data data;
3697e599
PF		 1530 unsigned int au, eo, et, es;
1531
1532 cmd.cmdidx = MMC_CMD_APP_CMD;
1533 cmd.resp_type = MMC_RSP_R1;
1534 cmd.cmdarg = mmc->rca << 16;
1535
da129170 1536 err = mmc_send_cmd_quirks(mmc, &cmd, NULL, MMC_QUIRK_RETRY_APP_CMD, 4);
3697e599
PF		 1537 if (err)
1538 return err;
1539
1540 cmd.cmdidx = SD_CMD_APP_SD_STATUS;
1541 cmd.resp_type = MMC_RSP_R1;
1542 cmd.cmdarg = 0;
1543
3697e599
PF		 1544 data.dest = (char *)ssr;
1545 data.blocksize = 64;
1546 data.blocks = 1;
1547 data.flags = MMC_DATA_READ;
1548
da129170
SA		 1549 err = mmc_send_cmd_retry(mmc, &cmd, &data, 3);
1550 if (err)
3697e599 1551 return err;
3697e599
PF		 1552
1553 for (i = 0; i < 16; i++)
1554 ssr[i] = be32_to_cpu(ssr[i]);
1555
1556 au = (ssr[2] >> 12) & 0xF;
1557 if ((au <= 9) || (mmc->version == SD_VERSION_3)) {
1558 mmc->ssr.au = sd_au_size[au];
1559 es = (ssr[3] >> 24) & 0xFF;
1560 es |= (ssr[2] & 0xFF) << 8;
1561 et = (ssr[3] >> 18) & 0x3F;
1562 if (es && et) {
1563 eo = (ssr[3] >> 16) & 0x3;
1564 mmc->ssr.erase_timeout = (et * 1000) / es;
1565 mmc->ssr.erase_offset = eo * 1000;
1566 }
1567 } else {
d4d64889 1568 pr_debug("Invalid Allocation Unit Size.\n");
3697e599
PF		 1569 }
1570
1571 return 0;
1572}
5b2e72f3 1573#endif
f9a86fb1
HS		 1574/*
1575 * TRAN_SPEED bits 0:2 encode the frequency unit:
1576 * 0 = 100KHz, 1 = 1MHz, 2 = 10MHz, 3 = 100MHz, values 4 - 7 are reserved.
1577 * The values in fbase[] are divided by 10 to avoid floats in multiplier[].
1578 */
5f837c2c 1579static const int fbase[] = {
272cc70b
AF		 1580 10000,
1581 100000,
1582 1000000,
1583 10000000,
f9a86fb1
HS		 1584 0, /* reserved */
1585 0, /* reserved */
1586 0, /* reserved */
1587 0, /* reserved */
272cc70b
AF		 1588};
1589
1590/* Multiplier values for TRAN_SPEED. Multiplied by 10 to be nice
1591 * to platforms without floating point.
1592 */
61fe076f 1593static const u8 multipliers[] = {
272cc70b
AF		 1594 0, /* reserved */
1595 10,
1596 12,
1597 13,
1598 15,
1599 20,
1600 25,
1601 30,
1602 35,
1603 40,
1604 45,
1605 50,
1606 55,
1607 60,
1608 70,
1609 80,
1610};
1611
d0c221fe
JJH		 1612static inline int bus_width(uint cap)
1613{
1614 if (cap == MMC_MODE_8BIT)
1615 return 8;
1616 if (cap == MMC_MODE_4BIT)
1617 return 4;
1618 if (cap == MMC_MODE_1BIT)
1619 return 1;
d8e3d420 1620 pr_warn("invalid bus witdh capability 0x%x\n", cap);
d0c221fe
JJH		 1621 return 0;
1622}
1623
e7881d85 1624#if !CONFIG_IS_ENABLED(DM_MMC)
03de305e 1625#if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING)
ec841209
KVA		 1626static int mmc_execute_tuning(struct mmc *mmc, uint opcode)
1627{
1628 return -ENOTSUPP;
1629}
f99c2efe 1630#endif
ec841209 1631
2a4d212f 1632static int mmc_set_ios(struct mmc *mmc)
272cc70b 1633{
2a4d212f
KVA		 1634 int ret = 0;
1635
93bfd616 1636 if (mmc->cfg->ops->set_ios)
2a4d212f
KVA		 1637 ret = mmc->cfg->ops->set_ios(mmc);
1638
1639 return ret;
272cc70b 1640}
3602a56a
YG		 1641
1642static int mmc_host_power_cycle(struct mmc *mmc)
1643{
1644 int ret = 0;
1645
1646 if (mmc->cfg->ops->host_power_cycle)
1647 ret = mmc->cfg->ops->host_power_cycle(mmc);
1648
1649 return ret;
1650}
8ca51e51 1651#endif
272cc70b 1652
35f67820 1653int mmc_set_clock(struct mmc *mmc, uint clock, bool disable)
272cc70b 1654{
c0fafe64 1655 if (!disable) {
9546eb92
JC		 1656 if (clock > mmc->cfg->f_max)
1657 clock = mmc->cfg->f_max;
272cc70b 1658
9546eb92
JC		 1659 if (clock < mmc->cfg->f_min)
1660 clock = mmc->cfg->f_min;
1661 }
272cc70b
AF		 1662
1663 mmc->clock = clock;
35f67820 1664 mmc->clk_disable = disable;
272cc70b 1665
d2faadb5
JC		 1666 debug("clock is %s (%dHz)\n", disable ? "disabled" : "enabled", clock);
1667
2a4d212f 1668 return mmc_set_ios(mmc);
272cc70b
AF		 1669}
1670
2a4d212f 1671static int mmc_set_bus_width(struct mmc *mmc, uint width)
272cc70b
AF		 1672{
1673 mmc->bus_width = width;
1674
2a4d212f 1675 return mmc_set_ios(mmc);
272cc70b
AF		 1676}
1677
4c9d2aaa
JJH		 1678#if CONFIG_IS_ENABLED(MMC_VERBOSE) || defined(DEBUG)
1679/*
1680 * helper function to display the capabilities in a human
1681 * friendly manner. The capabilities include bus width and
1682 * supported modes.
1683 */
1684void mmc_dump_capabilities(const char *text, uint caps)
1685{
1686 enum bus_mode mode;
1687
d4d64889 1688 pr_debug("%s: widths [", text);
4c9d2aaa 1689 if (caps & MMC_MODE_8BIT)
d4d64889 1690 pr_debug("8, ");
4c9d2aaa 1691 if (caps & MMC_MODE_4BIT)
d4d64889 1692 pr_debug("4, ");
d0c221fe 1693 if (caps & MMC_MODE_1BIT)
d4d64889
MY		 1694 pr_debug("1, ");
1695 pr_debug("\b\b] modes [");
4c9d2aaa
JJH		 1696 for (mode = MMC_LEGACY; mode < MMC_MODES_END; mode++)
1697 if (MMC_CAP(mode) & caps)
d4d64889
MY		 1698 pr_debug("%s, ", mmc_mode_name(mode));
1699 pr_debug("\b\b]\n");
4c9d2aaa
JJH		 1700}
1701#endif
1702
d0c221fe
JJH		 1703struct mode_width_tuning {
1704 enum bus_mode mode;
1705 uint widths;
03de305e 1706#if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING)
634d4849 1707 uint tuning;
f99c2efe 1708#endif
d0c221fe
JJH		 1709};
1710
f99c2efe 1711#if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE)
bc1e3272
JJH		 1712int mmc_voltage_to_mv(enum mmc_voltage voltage)
1713{
1714 switch (voltage) {
1715 case MMC_SIGNAL_VOLTAGE_000: return 0;
1716 case MMC_SIGNAL_VOLTAGE_330: return 3300;
1717 case MMC_SIGNAL_VOLTAGE_180: return 1800;
1718 case MMC_SIGNAL_VOLTAGE_120: return 1200;
1719 }
1720 return -EINVAL;
1721}
1722
aff5d3c8
KVA		 1723static int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage)
1724{
bc1e3272
JJH		 1725 int err;
1726
1727 if (mmc->signal_voltage == signal_voltage)
1728 return 0;
1729
aff5d3c8 1730 mmc->signal_voltage = signal_voltage;
bc1e3272
JJH		 1731 err = mmc_set_ios(mmc);
1732 if (err)
d4d64889 1733 pr_debug("unable to set voltage (err %d)\n", err);
bc1e3272
JJH		 1734
1735 return err;
aff5d3c8 1736}
f99c2efe
JJH		 1737#else
1738static inline int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage)
1739{
1740 return 0;
1741}
1742#endif
aff5d3c8 1743
62d77cea 1744#if !CONFIG_IS_ENABLED(MMC_TINY)
d0c221fe 1745static const struct mode_width_tuning sd_modes_by_pref[] = {
f99c2efe 1746#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
03de305e 1747#if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING)
c10b85d6
JJH		 1748 {
1749 .mode = UHS_SDR104,
1750 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1751 .tuning = MMC_CMD_SEND_TUNING_BLOCK
1752 },
f99c2efe 1753#endif
c10b85d6
JJH		 1754 {
1755 .mode = UHS_SDR50,
1756 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1757 },
1758 {
1759 .mode = UHS_DDR50,
1760 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1761 },
1762 {
1763 .mode = UHS_SDR25,
1764 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1765 },
f99c2efe 1766#endif
d0c221fe
JJH		 1767 {
1768 .mode = SD_HS,
1769 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1770 },
f99c2efe 1771#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
c10b85d6
JJH		 1772 {
1773 .mode = UHS_SDR12,
1774 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1775 },
f99c2efe 1776#endif
d0c221fe 1777 {
e8d5dde4 1778 .mode = MMC_LEGACY,
d0c221fe
JJH		 1779 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1780 }
1781};
1782
1783#define for_each_sd_mode_by_pref(caps, mwt) \
1784 for (mwt = sd_modes_by_pref;\
1785 mwt < sd_modes_by_pref + ARRAY_SIZE(sd_modes_by_pref);\
1786 mwt++) \
1787 if (caps & MMC_CAP(mwt->mode))
1788
01298da3 1789static int sd_select_mode_and_width(struct mmc *mmc, uint card_caps)
8ac8a263
JJH		 1790{
1791 int err;
d0c221fe
JJH		 1792 uint widths[] = {MMC_MODE_4BIT, MMC_MODE_1BIT};
1793 const struct mode_width_tuning *mwt;
f99c2efe 1794#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
c10b85d6 1795 bool uhs_en = (mmc->ocr & OCR_S18R) ? true : false;
f99c2efe
JJH		 1796#else
1797 bool uhs_en = false;
1798#endif
c10b85d6
JJH		 1799 uint caps;
1800
52d241df
JJH		 1801#ifdef DEBUG
1802 mmc_dump_capabilities("sd card", card_caps);
1da8eb59 1803 mmc_dump_capabilities("host", mmc->host_caps);
52d241df 1804#endif
8ac8a263 1805
f49ff799
AP		 1806 if (mmc_host_is_spi(mmc)) {
1807 mmc_set_bus_width(mmc, 1);
e8d5dde4 1808 mmc_select_mode(mmc, MMC_LEGACY);
f49ff799 1809 mmc_set_clock(mmc, mmc->tran_speed, MMC_CLK_ENABLE);
810bc138
PP		 1810#if CONFIG_IS_ENABLED(MMC_WRITE)
1811 err = sd_read_ssr(mmc);
1812 if (err)
1813 pr_warn("unable to read ssr\n");
1814#endif
f49ff799
AP		 1815 return 0;
1816 }
1817
8ac8a263 1818 /* Restrict card's capabilities by what the host can do */
1da8eb59 1819 caps = card_caps & mmc->host_caps;
d0c221fe 1820
c10b85d6
JJH		 1821 if (!uhs_en)
1822 caps &= ~UHS_CAPS;
1823
1824 for_each_sd_mode_by_pref(caps, mwt) {
d0c221fe
JJH		 1825 uint *w;
1826
1827 for (w = widths; w < widths + ARRAY_SIZE(widths); w++) {
c10b85d6 1828 if (*w & caps & mwt->widths) {
d4d64889
MY		 1829 pr_debug("trying mode %s width %d (at %d MHz)\n",
1830 mmc_mode_name(mwt->mode),
1831 bus_width(*w),
1832 mmc_mode2freq(mmc, mwt->mode) / 1000000);
d0c221fe
JJH		 1833
1834 /* configure the bus width (card + host) */
1835 err = sd_select_bus_width(mmc, bus_width(*w));
1836 if (err)
1837 goto error;
1838 mmc_set_bus_width(mmc, bus_width(*w));
1839
1840 /* configure the bus mode (card) */
1841 err = sd_set_card_speed(mmc, mwt->mode);
1842 if (err)
1843 goto error;
1844
1845 /* configure the bus mode (host) */
1846 mmc_select_mode(mmc, mwt->mode);
65117182
JC		 1847 mmc_set_clock(mmc, mmc->tran_speed,
1848 MMC_CLK_ENABLE);
d0c221fe 1849
03de305e 1850#if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING)
c10b85d6
JJH		 1851 /* execute tuning if needed */
1852 if (mwt->tuning && !mmc_host_is_spi(mmc)) {
1853 err = mmc_execute_tuning(mmc,
1854 mwt->tuning);
1855 if (err) {
d4d64889 1856 pr_debug("tuning failed\n");
c10b85d6
JJH		 1857 goto error;
1858 }
1859 }
f99c2efe 1860#endif
c10b85d6 1861
5b2e72f3 1862#if CONFIG_IS_ENABLED(MMC_WRITE)
d0c221fe 1863 err = sd_read_ssr(mmc);
0a4c2b09 1864 if (err)
5b2e72f3
JJH		 1865 pr_warn("unable to read ssr\n");
1866#endif
d0c221fe
JJH		 1867 if (!err)
1868 return 0;
1869
d0c221fe
JJH		 1870error:
1871 /* revert to a safer bus speed */
e8d5dde4 1872 mmc_select_mode(mmc, MMC_LEGACY);
65117182
JC		 1873 mmc_set_clock(mmc, mmc->tran_speed,
1874 MMC_CLK_ENABLE);
d0c221fe
JJH		 1875 }
1876 }
8ac8a263
JJH		 1877 }
1878
d4d64889 1879 pr_err("unable to select a mode\n");
d0c221fe 1880 return -ENOTSUPP;
8ac8a263
JJH		 1881}
1882
7382e691
JJH		 1883/*
1884 * read the compare the part of ext csd that is constant.
1885 * This can be used to check that the transfer is working
1886 * as expected.
1887 */
1888static int mmc_read_and_compare_ext_csd(struct mmc *mmc)
8ac8a263 1889{
7382e691 1890 int err;
dfda9d88 1891 const u8 *ext_csd = mmc->ext_csd;
7382e691
JJH		 1892 ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
1893
1de06b9f
JJH		 1894 if (mmc->version < MMC_VERSION_4)
1895 return 0;
1896
7382e691
JJH		 1897 err = mmc_send_ext_csd(mmc, test_csd);
1898 if (err)
1899 return err;
1900
1901 /* Only compare read only fields */
1902 if (ext_csd[EXT_CSD_PARTITIONING_SUPPORT]
1903 == test_csd[EXT_CSD_PARTITIONING_SUPPORT] &&
1904 ext_csd[EXT_CSD_HC_WP_GRP_SIZE]
1905 == test_csd[EXT_CSD_HC_WP_GRP_SIZE] &&
1906 ext_csd[EXT_CSD_REV]
1907 == test_csd[EXT_CSD_REV] &&
1908 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
1909 == test_csd[EXT_CSD_HC_ERASE_GRP_SIZE] &&
1910 memcmp(&ext_csd[EXT_CSD_SEC_CNT],
1911 &test_csd[EXT_CSD_SEC_CNT], 4) == 0)
1912 return 0;
1913
1914 return -EBADMSG;
1915}
1916
f99c2efe 1917#if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE)
bc1e3272
JJH		 1918static int mmc_set_lowest_voltage(struct mmc *mmc, enum bus_mode mode,
1919 uint32_t allowed_mask)
1920{
1921 u32 card_mask = 0;
1922
1923 switch (mode) {
44acd492 1924 case MMC_HS_400_ES:
3dd2626f 1925 case MMC_HS_400:
bc1e3272 1926 case MMC_HS_200:
3dd2626f
PF		 1927 if (mmc->cardtype & (EXT_CSD_CARD_TYPE_HS200_1_8V |
1928 EXT_CSD_CARD_TYPE_HS400_1_8V))
bc1e3272 1929 card_mask |= MMC_SIGNAL_VOLTAGE_180;
3dd2626f
PF		 1930 if (mmc->cardtype & (EXT_CSD_CARD_TYPE_HS200_1_2V |
1931 EXT_CSD_CARD_TYPE_HS400_1_2V))
bc1e3272
JJH		 1932 card_mask |= MMC_SIGNAL_VOLTAGE_120;
1933 break;
1934 case MMC_DDR_52:
1935 if (mmc->cardtype & EXT_CSD_CARD_TYPE_DDR_1_8V)
1936 card_mask |= MMC_SIGNAL_VOLTAGE_330 |
1937 MMC_SIGNAL_VOLTAGE_180;
1938 if (mmc->cardtype & EXT_CSD_CARD_TYPE_DDR_1_2V)
1939 card_mask |= MMC_SIGNAL_VOLTAGE_120;
1940 break;
1941 default:
1942 card_mask |= MMC_SIGNAL_VOLTAGE_330;
1943 break;
1944 }
1945
1946 while (card_mask & allowed_mask) {
1947 enum mmc_voltage best_match;
1948
1949 best_match = 1 << (ffs(card_mask & allowed_mask) - 1);
1950 if (!mmc_set_signal_voltage(mmc, best_match))
1951 return 0;
1952
1953 allowed_mask &= ~best_match;
1954 }
1955
1956 return -ENOTSUPP;
1957}
f99c2efe
JJH		 1958#else
1959static inline int mmc_set_lowest_voltage(struct mmc *mmc, enum bus_mode mode,
1960 uint32_t allowed_mask)
1961{
1962 return 0;
1963}
1964#endif
bc1e3272 1965
3862b854 1966static const struct mode_width_tuning mmc_modes_by_pref[] = {
44acd492
PF		 1967#if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
1968 {
1969 .mode = MMC_HS_400_ES,
1970 .widths = MMC_MODE_8BIT,
1971 },
1972#endif
3dd2626f
PF		 1973#if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
1974 {
1975 .mode = MMC_HS_400,
1976 .widths = MMC_MODE_8BIT,
1977 .tuning = MMC_CMD_SEND_TUNING_BLOCK_HS200
1978 },
1979#endif
f99c2efe 1980#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
3862b854
JJH		 1981 {
1982 .mode = MMC_HS_200,
1983 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT,
634d4849 1984 .tuning = MMC_CMD_SEND_TUNING_BLOCK_HS200
3862b854 1985 },
f99c2efe 1986#endif
3862b854
JJH		 1987 {
1988 .mode = MMC_DDR_52,
1989 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT,
1990 },
1991 {
1992 .mode = MMC_HS_52,
1993 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,
1994 },
1995 {
1996 .mode = MMC_HS,
1997 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,
1998 },
1999 {
2000 .mode = MMC_LEGACY,
2001 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,
2002 }
2003};
2004
2005#define for_each_mmc_mode_by_pref(caps, mwt) \
2006 for (mwt = mmc_modes_by_pref;\
2007 mwt < mmc_modes_by_pref + ARRAY_SIZE(mmc_modes_by_pref);\
2008 mwt++) \
2009 if (caps & MMC_CAP(mwt->mode))
2010
2011static const struct ext_csd_bus_width {
2012 uint cap;
2013 bool is_ddr;
2014 uint ext_csd_bits;
2015} ext_csd_bus_width[] = {
2016 {MMC_MODE_8BIT, true, EXT_CSD_DDR_BUS_WIDTH_8},
2017 {MMC_MODE_4BIT, true, EXT_CSD_DDR_BUS_WIDTH_4},
2018 {MMC_MODE_8BIT, false, EXT_CSD_BUS_WIDTH_8},
2019 {MMC_MODE_4BIT, false, EXT_CSD_BUS_WIDTH_4},
2020 {MMC_MODE_1BIT, false, EXT_CSD_BUS_WIDTH_1},
2021};
2022
3dd2626f
PF		 2023#if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
2024static int mmc_select_hs400(struct mmc *mmc)
2025{
2026 int err;
2027
2028 /* Set timing to HS200 for tuning */
b9a2a0e2 2029 err = mmc_set_card_speed(mmc, MMC_HS_200, false);
3dd2626f
PF		 2030 if (err)
2031 return err;
2032
2033 /* configure the bus mode (host) */
2034 mmc_select_mode(mmc, MMC_HS_200);
2035 mmc_set_clock(mmc, mmc->tran_speed, false);
2036
2037 /* execute tuning if needed */
d1343522 2038 mmc->hs400_tuning = true;
3dd2626f 2039 err = mmc_execute_tuning(mmc, MMC_CMD_SEND_TUNING_BLOCK_HS200);
d1343522 2040 mmc->hs400_tuning = false;
3dd2626f
PF		 2041 if (err) {
2042 debug("tuning failed\n");
2043 return err;
2044 }
2045
2046 /* Set back to HS */
5cf12031 2047 mmc_set_card_speed(mmc, MMC_HS, true);
3dd2626f 2048
d271e105
YL		 2049 err = mmc_hs400_prepare_ddr(mmc);
2050 if (err)
2051 return err;
2052
3dd2626f
PF		 2053 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BUS_WIDTH,
2054 EXT_CSD_BUS_WIDTH_8 | EXT_CSD_DDR_FLAG);
2055 if (err)
2056 return err;
2057
b9a2a0e2 2058 err = mmc_set_card_speed(mmc, MMC_HS_400, false);
3dd2626f
PF		 2059 if (err)
2060 return err;
2061
2062 mmc_select_mode(mmc, MMC_HS_400);
2063 err = mmc_set_clock(mmc, mmc->tran_speed, false);
2064 if (err)
2065 return err;
2066
2067 return 0;
2068}
2069#else
2070static int mmc_select_hs400(struct mmc *mmc)
2071{
2072 return -ENOTSUPP;
2073}
2074#endif
2075
44acd492
PF		 2076#if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
2077#if !CONFIG_IS_ENABLED(DM_MMC)
2078static int mmc_set_enhanced_strobe(struct mmc *mmc)
2079{
2080 return -ENOTSUPP;
2081}
2082#endif
2083static int mmc_select_hs400es(struct mmc *mmc)
2084{
2085 int err;
2086
2087 err = mmc_set_card_speed(mmc, MMC_HS, true);
2088 if (err)
2089 return err;
2090
2091 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BUS_WIDTH,
2092 EXT_CSD_BUS_WIDTH_8 | EXT_CSD_DDR_FLAG |
2093 EXT_CSD_BUS_WIDTH_STROBE);
2094 if (err) {
2095 printf("switch to bus width for hs400 failed\n");
2096 return err;
2097 }
2098 /* TODO: driver strength */
2099 err = mmc_set_card_speed(mmc, MMC_HS_400_ES, false);
2100 if (err)
2101 return err;
2102
2103 mmc_select_mode(mmc, MMC_HS_400_ES);
2104 err = mmc_set_clock(mmc, mmc->tran_speed, false);
2105 if (err)
2106 return err;
2107
2108 return mmc_set_enhanced_strobe(mmc);
2109}
2110#else
2111static int mmc_select_hs400es(struct mmc *mmc)
2112{
2113 return -ENOTSUPP;
2114}
2115#endif
2116
3862b854
JJH		 2117#define for_each_supported_width(caps, ddr, ecbv) \
2118 for (ecbv = ext_csd_bus_width;\
2119 ecbv < ext_csd_bus_width + ARRAY_SIZE(ext_csd_bus_width);\
2120 ecbv++) \
2121 if ((ddr == ecbv->is_ddr) && (caps & ecbv->cap))
2122
01298da3 2123static int mmc_select_mode_and_width(struct mmc *mmc, uint card_caps)
7382e691 2124{
52ff04a2 2125 int err = 0;
3862b854
JJH		 2126 const struct mode_width_tuning *mwt;
2127 const struct ext_csd_bus_width *ecbw;
8ac8a263 2128
52d241df
JJH		 2129#ifdef DEBUG
2130 mmc_dump_capabilities("mmc", card_caps);
1da8eb59 2131 mmc_dump_capabilities("host", mmc->host_caps);
52d241df
JJH		 2132#endif
2133
f49ff799
AP		 2134 if (mmc_host_is_spi(mmc)) {
2135 mmc_set_bus_width(mmc, 1);
2136 mmc_select_mode(mmc, MMC_LEGACY);
2137 mmc_set_clock(mmc, mmc->tran_speed, MMC_CLK_ENABLE);
2138 return 0;
2139 }
2140
8ac8a263 2141 /* Restrict card's capabilities by what the host can do */
1da8eb59 2142 card_caps &= mmc->host_caps;
8ac8a263
JJH		 2143
2144 /* Only version 4 of MMC supports wider bus widths */
2145 if (mmc->version < MMC_VERSION_4)
2146 return 0;
2147
dfda9d88 2148 if (!mmc->ext_csd) {
d4d64889 2149 pr_debug("No ext_csd found!\n"); /* this should enver happen */
dfda9d88
JJH		 2150 return -ENOTSUPP;
2151 }
2152
b9a2a0e2 2153#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
fb8c2e8f
YL		 2154 CONFIG_IS_ENABLED(MMC_HS400_SUPPORT) || \
2155 CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
b9a2a0e2
MV		 2156 /*
2157 * In case the eMMC is in HS200/HS400 mode, downgrade to HS mode
2158 * before doing anything else, since a transition from either of
2159 * the HS200/HS400 mode directly to legacy mode is not supported.
2160 */
2161 if (mmc->selected_mode == MMC_HS_200 ||
fb8c2e8f
YL		 2162 mmc->selected_mode == MMC_HS_400 ||
2163 mmc->selected_mode == MMC_HS_400_ES)
b9a2a0e2
MV		 2164 mmc_set_card_speed(mmc, MMC_HS, true);
2165 else
2166#endif
2167 mmc_set_clock(mmc, mmc->legacy_speed, MMC_CLK_ENABLE);
01298da3
JJH		 2168
2169 for_each_mmc_mode_by_pref(card_caps, mwt) {
2170 for_each_supported_width(card_caps & mwt->widths,
3862b854 2171 mmc_is_mode_ddr(mwt->mode), ecbw) {
bc1e3272 2172 enum mmc_voltage old_voltage;
d4d64889
MY		 2173 pr_debug("trying mode %s width %d (at %d MHz)\n",
2174 mmc_mode_name(mwt->mode),
2175 bus_width(ecbw->cap),
2176 mmc_mode2freq(mmc, mwt->mode) / 1000000);
bc1e3272
JJH		 2177 old_voltage = mmc->signal_voltage;
2178 err = mmc_set_lowest_voltage(mmc, mwt->mode,
2179 MMC_ALL_SIGNAL_VOLTAGE);
2180 if (err)
2181 continue;
2182
3862b854
JJH		 2183 /* configure the bus width (card + host) */
2184 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
2185 EXT_CSD_BUS_WIDTH,
2186 ecbw->ext_csd_bits & ~EXT_CSD_DDR_FLAG);
2187 if (err)
2188 goto error;
2189 mmc_set_bus_width(mmc, bus_width(ecbw->cap));
8ac8a263 2190
3dd2626f
PF		 2191 if (mwt->mode == MMC_HS_400) {
2192 err = mmc_select_hs400(mmc);
2193 if (err) {
2194 printf("Select HS400 failed %d\n", err);
2195 goto error;
2196 }
44acd492
PF		 2197 } else if (mwt->mode == MMC_HS_400_ES) {
2198 err = mmc_select_hs400es(mmc);
2199 if (err) {
2200 printf("Select HS400ES failed %d\n",
2201 err);
2202 goto error;
2203 }
3dd2626f
PF		 2204 } else {
2205 /* configure the bus speed (card) */
b9a2a0e2 2206 err = mmc_set_card_speed(mmc, mwt->mode, false);
3862b854
JJH		 2207 if (err)
2208 goto error;
8ac8a263 2209
3dd2626f
PF		 2210 /*
2211 * configure the bus width AND the ddr mode
2212 * (card). The host side will be taken care
2213 * of in the next step
2214 */
2215 if (ecbw->ext_csd_bits & EXT_CSD_DDR_FLAG) {
2216 err = mmc_switch(mmc,
2217 EXT_CSD_CMD_SET_NORMAL,
2218 EXT_CSD_BUS_WIDTH,
2219 ecbw->ext_csd_bits);
2220 if (err)
2221 goto error;
2222 }
2223
2224 /* configure the bus mode (host) */
2225 mmc_select_mode(mmc, mwt->mode);
2226 mmc_set_clock(mmc, mmc->tran_speed,
2227 MMC_CLK_ENABLE);
03de305e 2228#if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING)
8ac8a263 2229
3dd2626f
PF		 2230 /* execute tuning if needed */
2231 if (mwt->tuning) {
2232 err = mmc_execute_tuning(mmc,
2233 mwt->tuning);
2234 if (err) {
58896458 2235 pr_debug("tuning failed : %d\n", err);
3dd2626f
PF		 2236 goto error;
2237 }
634d4849 2238 }
f99c2efe 2239#endif
3dd2626f 2240 }
634d4849 2241
3862b854
JJH		 2242 /* do a transfer to check the configuration */
2243 err = mmc_read_and_compare_ext_csd(mmc);
2244 if (!err)
2245 return 0;
2246error:
bc1e3272 2247 mmc_set_signal_voltage(mmc, old_voltage);
64dbd86b 2248 /* if an error occurred, revert to a safer bus mode */
3862b854
JJH		 2249 mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
2250 EXT_CSD_BUS_WIDTH, EXT_CSD_BUS_WIDTH_1);
2251 mmc_select_mode(mmc, MMC_LEGACY);
50dee4f3 2252 mmc_set_clock(mmc, mmc->legacy_speed, MMC_CLK_ENABLE);
3862b854
JJH		 2253 mmc_set_bus_width(mmc, 1);
2254 }
8ac8a263
JJH		 2255 }
2256
58896458 2257 pr_err("unable to select a mode : %d\n", err);
8ac8a263 2258
3862b854 2259 return -ENOTSUPP;
8ac8a263 2260}
27ba82cb
MV		 2261#else
2262static int sd_select_mode_and_width(struct mmc *mmc, uint card_caps)
2263{
2264 return 0;
2265};
2266
2267static int mmc_select_mode_and_width(struct mmc *mmc, uint card_caps)
2268{
2269 return 0;
2270};
62d77cea
MV		 2271#endif
2272
2273#if CONFIG_IS_ENABLED(MMC_TINY)
2274DEFINE_CACHE_ALIGN_BUFFER(u8, ext_csd_bkup, MMC_MAX_BLOCK_LEN);
2275#endif
8ac8a263 2276
dfda9d88 2277static int mmc_startup_v4(struct mmc *mmc)
c744b6f6
JJH		 2278{
2279 int err, i;
2280 u64 capacity;
2281 bool has_parts = false;
2282 bool part_completed;
58a6fb7b
JJH		 2283 static const u32 mmc_versions[] = {
2284 MMC_VERSION_4,
2285 MMC_VERSION_4_1,
2286 MMC_VERSION_4_2,
2287 MMC_VERSION_4_3,
ace1bed3 2288 MMC_VERSION_4_4,
58a6fb7b
JJH		 2289 MMC_VERSION_4_41,
2290 MMC_VERSION_4_5,
2291 MMC_VERSION_5_0,
2292 MMC_VERSION_5_1
2293 };
2294
62d77cea
MV		 2295#if CONFIG_IS_ENABLED(MMC_TINY)
2296 u8 *ext_csd = ext_csd_bkup;
2297
2298 if (IS_SD(mmc) || mmc->version < MMC_VERSION_4)
2299 return 0;
2300
2301 if (!mmc->ext_csd)
229d689e 2302 memset(ext_csd_bkup, 0, MMC_MAX_BLOCK_LEN);
62d77cea
MV		 2303
2304 err = mmc_send_ext_csd(mmc, ext_csd);
2305 if (err)
2306 goto error;
2307
2308 /* store the ext csd for future reference */
2309 if (!mmc->ext_csd)
2310 mmc->ext_csd = ext_csd;
2311#else
f7d5dffc 2312 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
c744b6f6
JJH		 2313
2314 if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4))
2315 return 0;
2316
2317 /* check ext_csd version and capacity */
2318 err = mmc_send_ext_csd(mmc, ext_csd);
2319 if (err)
f7d5dffc
JJH		 2320 goto error;
2321
2322 /* store the ext csd for future reference */
2323 if (!mmc->ext_csd)
2324 mmc->ext_csd = malloc(MMC_MAX_BLOCK_LEN);
2325 if (!mmc->ext_csd)
2326 return -ENOMEM;
2327 memcpy(mmc->ext_csd, ext_csd, MMC_MAX_BLOCK_LEN);
62d77cea 2328#endif
76584e33 2329 if (ext_csd[EXT_CSD_REV] >= ARRAY_SIZE(mmc_versions))
58a6fb7b
JJH		 2330 return -EINVAL;
2331
2332 mmc->version = mmc_versions[ext_csd[EXT_CSD_REV]];
2333
2334 if (mmc->version >= MMC_VERSION_4_2) {
c744b6f6
JJH		 2335 /*
2336 * According to the JEDEC Standard, the value of
2337 * ext_csd's capacity is valid if the value is more
2338 * than 2GB
2339 */
2340 capacity = ext_csd[EXT_CSD_SEC_CNT] << 0
2341 | ext_csd[EXT_CSD_SEC_CNT + 1] << 8
2342 | ext_csd[EXT_CSD_SEC_CNT + 2] << 16
2343 | ext_csd[EXT_CSD_SEC_CNT + 3] << 24;
2344 capacity *= MMC_MAX_BLOCK_LEN;
2345 if ((capacity >> 20) > 2 * 1024)
2346 mmc->capacity_user = capacity;
2347 }
2348
39320c53
JJH		 2349 if (mmc->version >= MMC_VERSION_4_5)
2350 mmc->gen_cmd6_time = ext_csd[EXT_CSD_GENERIC_CMD6_TIME];
2351
c744b6f6
JJH		 2352 /* The partition data may be non-zero but it is only
2353 * effective if PARTITION_SETTING_COMPLETED is set in
2354 * EXT_CSD, so ignore any data if this bit is not set,
2355 * except for enabling the high-capacity group size
2356 * definition (see below).
2357 */
2358 part_completed = !!(ext_csd[EXT_CSD_PARTITION_SETTING] &
2359 EXT_CSD_PARTITION_SETTING_COMPLETED);
2360
513e00b6
JJH		 2361 mmc->part_switch_time = ext_csd[EXT_CSD_PART_SWITCH_TIME];
2362 /* Some eMMC set the value too low so set a minimum */
2363 if (mmc->part_switch_time < MMC_MIN_PART_SWITCH_TIME && mmc->part_switch_time)
2364 mmc->part_switch_time = MMC_MIN_PART_SWITCH_TIME;
2365
c744b6f6
JJH		 2366 /* store the partition info of emmc */
2367 mmc->part_support = ext_csd[EXT_CSD_PARTITIONING_SUPPORT];
2368 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) ||
2369 ext_csd[EXT_CSD_BOOT_MULT])
2370 mmc->part_config = ext_csd[EXT_CSD_PART_CONF];
2371 if (part_completed &&
2372 (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & ENHNCD_SUPPORT))
2373 mmc->part_attr = ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE];
2374
2375 mmc->capacity_boot = ext_csd[EXT_CSD_BOOT_MULT] << 17;
2376
2377 mmc->capacity_rpmb = ext_csd[EXT_CSD_RPMB_MULT] << 17;
2378
2379 for (i = 0; i < 4; i++) {
2380 int idx = EXT_CSD_GP_SIZE_MULT + i * 3;
2381 uint mult = (ext_csd[idx + 2] << 16) +
2382 (ext_csd[idx + 1] << 8) + ext_csd[idx];
2383 if (mult)
2384 has_parts = true;
2385 if (!part_completed)
2386 continue;
2387 mmc->capacity_gp[i] = mult;
2388 mmc->capacity_gp[i] *=
2389 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
2390 mmc->capacity_gp[i] *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
2391 mmc->capacity_gp[i] <<= 19;
2392 }
2393
173c06df 2394#ifndef CONFIG_SPL_BUILD
c744b6f6
JJH		 2395 if (part_completed) {
2396 mmc->enh_user_size =
2397 (ext_csd[EXT_CSD_ENH_SIZE_MULT + 2] << 16) +
2398 (ext_csd[EXT_CSD_ENH_SIZE_MULT + 1] << 8) +
2399 ext_csd[EXT_CSD_ENH_SIZE_MULT];
2400 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
2401 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
2402 mmc->enh_user_size <<= 19;
2403 mmc->enh_user_start =
2404 (ext_csd[EXT_CSD_ENH_START_ADDR + 3] << 24) +
2405 (ext_csd[EXT_CSD_ENH_START_ADDR + 2] << 16) +
2406 (ext_csd[EXT_CSD_ENH_START_ADDR + 1] << 8) +
2407 ext_csd[EXT_CSD_ENH_START_ADDR];
2408 if (mmc->high_capacity)
2409 mmc->enh_user_start <<= 9;
2410 }
173c06df 2411#endif
c744b6f6
JJH		 2412
2413 /*
2414 * Host needs to enable ERASE_GRP_DEF bit if device is
2415 * partitioned. This bit will be lost every time after a reset
2416 * or power off. This will affect erase size.
2417 */
2418 if (part_completed)
2419 has_parts = true;
2420 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) &&
2421 (ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE] & PART_ENH_ATTRIB))
2422 has_parts = true;
2423 if (has_parts) {
2424 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
2425 EXT_CSD_ERASE_GROUP_DEF, 1);
2426
2427 if (err)
f7d5dffc 2428 goto error;
c744b6f6
JJH		 2429
2430 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
2431 }
2432
2433 if (ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01) {
e6fa5a54 2434#if CONFIG_IS_ENABLED(MMC_WRITE)
c744b6f6
JJH		 2435 /* Read out group size from ext_csd */
2436 mmc->erase_grp_size =
2437 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
e6fa5a54 2438#endif
c744b6f6
JJH		 2439 /*
2440 * if high capacity and partition setting completed
2441 * SEC_COUNT is valid even if it is smaller than 2 GiB
2442 * JEDEC Standard JESD84-B45, 6.2.4
2443 */
2444 if (mmc->high_capacity && part_completed) {
2445 capacity = (ext_csd[EXT_CSD_SEC_CNT]) |
2446 (ext_csd[EXT_CSD_SEC_CNT + 1] << 8) |
2447 (ext_csd[EXT_CSD_SEC_CNT + 2] << 16) |
2448 (ext_csd[EXT_CSD_SEC_CNT + 3] << 24);
2449 capacity *= MMC_MAX_BLOCK_LEN;
2450 mmc->capacity_user = capacity;
2451 }
e6fa5a54
JJH		 2452 }
2453#if CONFIG_IS_ENABLED(MMC_WRITE)
2454 else {
c744b6f6
JJH		 2455 /* Calculate the group size from the csd value. */
2456 int erase_gsz, erase_gmul;
2457
2458 erase_gsz = (mmc->csd[2] & 0x00007c00) >> 10;
2459 erase_gmul = (mmc->csd[2] & 0x000003e0) >> 5;
2460 mmc->erase_grp_size = (erase_gsz + 1)
2461 * (erase_gmul + 1);
2462 }
e6fa5a54 2463#endif
b7a6e2c9 2464#if CONFIG_IS_ENABLED(MMC_HW_PARTITIONING)
c744b6f6
JJH		 2465 mmc->hc_wp_grp_size = 1024
2466 * ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
2467 * ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
b7a6e2c9 2468#endif
c744b6f6
JJH		 2469
2470 mmc->wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
2471
eeb739a6
LP		 2472 mmc->can_trim =
2473 !!(ext_csd[EXT_CSD_SEC_FEATURE] & EXT_CSD_SEC_FEATURE_TRIM_EN);
2474
c744b6f6 2475 return 0;
f7d5dffc
JJH		 2476error:
2477 if (mmc->ext_csd) {
62d77cea 2478#if !CONFIG_IS_ENABLED(MMC_TINY)
f7d5dffc 2479 free(mmc->ext_csd);
62d77cea 2480#endif
f7d5dffc
JJH		 2481 mmc->ext_csd = NULL;
2482 }
2483 return err;
c744b6f6
JJH		 2484}
2485
fdbb873e 2486static int mmc_startup(struct mmc *mmc)
272cc70b 2487{
f866a46d 2488 int err, i;
272cc70b 2489 uint mult, freq;
c744b6f6 2490 u64 cmult, csize;
272cc70b 2491 struct mmc_cmd cmd;
c40fdca6 2492 struct blk_desc *bdesc;
272cc70b 2493
d52ebf10
TC		 2494#ifdef CONFIG_MMC_SPI_CRC_ON
2495 if (mmc_host_is_spi(mmc)) { /* enable CRC check for spi */
2496 cmd.cmdidx = MMC_CMD_SPI_CRC_ON_OFF;
2497 cmd.resp_type = MMC_RSP_R1;
2498 cmd.cmdarg = 1;
d52ebf10 2499 err = mmc_send_cmd(mmc, &cmd, NULL);
d52ebf10
TC		 2500 if (err)
2501 return err;
2502 }
2503#endif
2504
272cc70b 2505 /* Put the Card in Identify Mode */
d52ebf10
TC		 2506 cmd.cmdidx = mmc_host_is_spi(mmc) ? MMC_CMD_SEND_CID :
2507 MMC_CMD_ALL_SEND_CID; /* cmd not supported in spi */
272cc70b
AF		 2508 cmd.resp_type = MMC_RSP_R2;
2509 cmd.cmdarg = 0;
272cc70b 2510
da129170 2511 err = mmc_send_cmd_quirks(mmc, &cmd, NULL, MMC_QUIRK_RETRY_SEND_CID, 4);
272cc70b
AF		 2512 if (err)
2513 return err;
2514
2515 memcpy(mmc->cid, cmd.response, 16);
2516
2517 /*
2518 * For MMC cards, set the Relative Address.
2519 * For SD cards, get the Relatvie Address.
2520 * This also puts the cards into Standby State
2521 */
d52ebf10
TC		 2522 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
2523 cmd.cmdidx = SD_CMD_SEND_RELATIVE_ADDR;
2524 cmd.cmdarg = mmc->rca << 16;
2525 cmd.resp_type = MMC_RSP_R6;
272cc70b 2526
d52ebf10 2527 err = mmc_send_cmd(mmc, &cmd, NULL);
272cc70b 2528
d52ebf10
TC		 2529 if (err)
2530 return err;
272cc70b 2531
d52ebf10
TC		 2532 if (IS_SD(mmc))
2533 mmc->rca = (cmd.response[0] >> 16) & 0xffff;
2534 }
272cc70b
AF		 2535
2536 /* Get the Card-Specific Data */
2537 cmd.cmdidx = MMC_CMD_SEND_CSD;
2538 cmd.resp_type = MMC_RSP_R2;
2539 cmd.cmdarg = mmc->rca << 16;
272cc70b
AF		 2540
2541 err = mmc_send_cmd(mmc, &cmd, NULL);
2542
2543 if (err)
2544 return err;
2545
998be3dd
RV		 2546 mmc->csd[0] = cmd.response[0];
2547 mmc->csd[1] = cmd.response[1];
2548 mmc->csd[2] = cmd.response[2];
2549 mmc->csd[3] = cmd.response[3];
272cc70b
AF		 2550
2551 if (mmc->version == MMC_VERSION_UNKNOWN) {
0b453ffe 2552 int version = (cmd.response[0] >> 26) & 0xf;
272cc70b
AF		 2553
2554 switch (version) {
53e8e40b
BM		 2555 case 0:
2556 mmc->version = MMC_VERSION_1_2;
2557 break;
2558 case 1:
2559 mmc->version = MMC_VERSION_1_4;
2560 break;
2561 case 2:
2562 mmc->version = MMC_VERSION_2_2;
2563 break;
2564 case 3:
2565 mmc->version = MMC_VERSION_3;
2566 break;
2567 case 4:
2568 mmc->version = MMC_VERSION_4;
2569 break;
2570 default:
2571 mmc->version = MMC_VERSION_1_2;
2572 break;
272cc70b
AF		 2573 }
2574 }
2575
2576 /* divide frequency by 10, since the mults are 10x bigger */
0b453ffe
RV		 2577 freq = fbase[(cmd.response[0] & 0x7)];
2578 mult = multipliers[((cmd.response[0] >> 3) & 0xf)];
272cc70b 2579
35f9e196 2580 mmc->legacy_speed = freq * mult;
f9a86fb1
HS		 2581 if (!mmc->legacy_speed)
2582 log_debug("TRAN_SPEED: reserved value");
35f9e196 2583 mmc_select_mode(mmc, MMC_LEGACY);
272cc70b 2584
ab71188c 2585 mmc->dsr_imp = ((cmd.response[1] >> 12) & 0x1);
998be3dd 2586 mmc->read_bl_len = 1 << ((cmd.response[1] >> 16) & 0xf);
e6fa5a54 2587#if CONFIG_IS_ENABLED(MMC_WRITE)
272cc70b
AF		 2588
2589 if (IS_SD(mmc))
2590 mmc->write_bl_len = mmc->read_bl_len;
2591 else
998be3dd 2592 mmc->write_bl_len = 1 << ((cmd.response[3] >> 22) & 0xf);
e6fa5a54 2593#endif
272cc70b
AF		 2594
2595 if (mmc->high_capacity) {
2596 csize = (mmc->csd[1] & 0x3f) << 16
2597 | (mmc->csd[2] & 0xffff0000) >> 16;
2598 cmult = 8;
2599 } else {
2600 csize = (mmc->csd[1] & 0x3ff) << 2
2601 | (mmc->csd[2] & 0xc0000000) >> 30;
2602 cmult = (mmc->csd[2] & 0x00038000) >> 15;
2603 }
2604
f866a46d
SW		 2605 mmc->capacity_user = (csize + 1) << (cmult + 2);
2606 mmc->capacity_user *= mmc->read_bl_len;
2607 mmc->capacity_boot = 0;
2608 mmc->capacity_rpmb = 0;
2609 for (i = 0; i < 4; i++)
2610 mmc->capacity_gp[i] = 0;
272cc70b 2611
8bfa195e
SG		 2612 if (mmc->read_bl_len > MMC_MAX_BLOCK_LEN)
2613 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
272cc70b 2614
e6fa5a54 2615#if CONFIG_IS_ENABLED(MMC_WRITE)
8bfa195e
SG		 2616 if (mmc->write_bl_len > MMC_MAX_BLOCK_LEN)
2617 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
e6fa5a54 2618#endif
272cc70b 2619
ab71188c
MN		 2620 if ((mmc->dsr_imp) && (0xffffffff != mmc->dsr)) {
2621 cmd.cmdidx = MMC_CMD_SET_DSR;
2622 cmd.cmdarg = (mmc->dsr & 0xffff) << 16;
2623 cmd.resp_type = MMC_RSP_NONE;
2624 if (mmc_send_cmd(mmc, &cmd, NULL))
d8e3d420 2625 pr_warn("MMC: SET_DSR failed\n");
ab71188c
MN		 2626 }
2627
272cc70b 2628 /* Select the card, and put it into Transfer Mode */
d52ebf10
TC		 2629 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
2630 cmd.cmdidx = MMC_CMD_SELECT_CARD;
fe8f7066 2631 cmd.resp_type = MMC_RSP_R1;
d52ebf10 2632 cmd.cmdarg = mmc->rca << 16;
d52ebf10 2633 err = mmc_send_cmd(mmc, &cmd, NULL);
272cc70b 2634
d52ebf10
TC		 2635 if (err)
2636 return err;
2637 }
272cc70b 2638
e6f99a56
LW		 2639 /*
2640 * For SD, its erase group is always one sector
2641 */
e6fa5a54 2642#if CONFIG_IS_ENABLED(MMC_WRITE)
e6f99a56 2643 mmc->erase_grp_size = 1;
e6fa5a54 2644#endif
bc897b1d 2645 mmc->part_config = MMCPART_NOAVAILABLE;
1937e5aa 2646
dfda9d88 2647 err = mmc_startup_v4(mmc);
c744b6f6
JJH		 2648 if (err)
2649 return err;
d23e2c09 2650
c40fdca6 2651 err = mmc_set_capacity(mmc, mmc_get_blk_desc(mmc)->hwpart);
f866a46d
SW		 2652 if (err)
2653 return err;
2654
62d77cea
MV		 2655#if CONFIG_IS_ENABLED(MMC_TINY)
2656 mmc_set_clock(mmc, mmc->legacy_speed, false);
e8d5dde4 2657 mmc_select_mode(mmc, MMC_LEGACY);
62d77cea
MV		 2658 mmc_set_bus_width(mmc, 1);
2659#else
01298da3
JJH		 2660 if (IS_SD(mmc)) {
2661 err = sd_get_capabilities(mmc);
2662 if (err)
2663 return err;
2664 err = sd_select_mode_and_width(mmc, mmc->card_caps);
2665 } else {
2666 err = mmc_get_capabilities(mmc);
2667 if (err)
2668 return err;
8adf50ef 2669 err = mmc_select_mode_and_width(mmc, mmc->card_caps);
01298da3 2670 }
62d77cea 2671#endif
272cc70b
AF		 2672 if (err)
2673 return err;
2674
01298da3 2675 mmc->best_mode = mmc->selected_mode;
ad5fd922 2676
5af8f45c
AG		 2677 /* Fix the block length for DDR mode */
2678 if (mmc->ddr_mode) {
2679 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
e6fa5a54 2680#if CONFIG_IS_ENABLED(MMC_WRITE)
5af8f45c 2681 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
e6fa5a54 2682#endif
5af8f45c
AG		 2683 }
2684
272cc70b 2685 /* fill in device description */
c40fdca6
SG		 2686 bdesc = mmc_get_blk_desc(mmc);
2687 bdesc->lun = 0;
2688 bdesc->hwpart = 0;
2689 bdesc->type = 0;
2690 bdesc->blksz = mmc->read_bl_len;
2691 bdesc->log2blksz = LOG2(bdesc->blksz);
2692 bdesc->lba = lldiv(mmc->capacity, mmc->read_bl_len);
fc011f64
SS		 2693#if !defined(CONFIG_SPL_BUILD) || \
2694 (defined(CONFIG_SPL_LIBCOMMON_SUPPORT) && \
27084c03 2695 !CONFIG_IS_ENABLED(USE_TINY_PRINTF))
c40fdca6 2696 sprintf(bdesc->vendor, "Man %06x Snr %04x%04x",
babce5f6
TH		 2697 mmc->cid[0] >> 24, (mmc->cid[2] & 0xffff),
2698 (mmc->cid[3] >> 16) & 0xffff);
c40fdca6 2699 sprintf(bdesc->product, "%c%c%c%c%c%c", mmc->cid[0] & 0xff,
babce5f6
TH		 2700 (mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff,
2701 (mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff,
2702 (mmc->cid[2] >> 24) & 0xff);
c40fdca6 2703 sprintf(bdesc->revision, "%d.%d", (mmc->cid[2] >> 20) & 0xf,
babce5f6 2704 (mmc->cid[2] >> 16) & 0xf);
56196826 2705#else
c40fdca6
SG		 2706 bdesc->vendor[0] = 0;
2707 bdesc->product[0] = 0;
2708 bdesc->revision[0] = 0;
56196826 2709#endif
272cc70b 2710
eef05fd3
AP		 2711#if !defined(CONFIG_DM_MMC) && (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBDISK_SUPPORT))
2712 part_init(bdesc);
2713#endif
2714
272cc70b
AF		 2715 return 0;
2716}
2717
fdbb873e 2718static int mmc_send_if_cond(struct mmc *mmc)
272cc70b
AF		 2719{
2720 struct mmc_cmd cmd;
2721 int err;
2722
2723 cmd.cmdidx = SD_CMD_SEND_IF_COND;
2724 /* We set the bit if the host supports voltages between 2.7 and 3.6 V */
93bfd616 2725 cmd.cmdarg = ((mmc->cfg->voltages & 0xff8000) != 0) << 8 | 0xaa;
272cc70b 2726 cmd.resp_type = MMC_RSP_R7;
272cc70b
AF		 2727
2728 err = mmc_send_cmd(mmc, &cmd, NULL);
2729
2730 if (err)
2731 return err;
2732
998be3dd 2733 if ((cmd.response[0] & 0xff) != 0xaa)
915ffa52 2734 return -EOPNOTSUPP;
272cc70b
AF		 2735 else
2736 mmc->version = SD_VERSION_2;
2737
2738 return 0;
2739}
2740
c4d660d4 2741#if !CONFIG_IS_ENABLED(DM_MMC)
95de9ab2
PK		 2742/* board-specific MMC power initializations. */
2743__weak void board_mmc_power_init(void)
2744{
2745}
05cbeb7c 2746#endif
95de9ab2 2747
2051aefe
PF		 2748static int mmc_power_init(struct mmc *mmc)
2749{
c4d660d4 2750#if CONFIG_IS_ENABLED(DM_MMC)
06ec045f 2751#if CONFIG_IS_ENABLED(DM_REGULATOR)
2051aefe
PF		 2752 int ret;
2753
2754 ret = device_get_supply_regulator(mmc->dev, "vmmc-supply",
06ec045f
JJH		 2755 &mmc->vmmc_supply);
2756 if (ret)
d4d64889 2757 pr_debug("%s: No vmmc supply\n", mmc->dev->name);
2051aefe 2758
06ec045f
JJH		 2759 ret = device_get_supply_regulator(mmc->dev, "vqmmc-supply",
2760 &mmc->vqmmc_supply);
2761 if (ret)
d4d64889 2762 pr_debug("%s: No vqmmc supply\n", mmc->dev->name);
fb7c3beb
KVA		 2763#endif
2764#else /* !CONFIG_DM_MMC */
2765 /*
2766 * Driver model should use a regulator, as above, rather than calling
2767 * out to board code.
2768 */
2769 board_mmc_power_init();
2770#endif
2771 return 0;
2772}
2773
2774/*
2775 * put the host in the initial state:
2776 * - turn on Vdd (card power supply)
2777 * - configure the bus width and clock to minimal values
2778 */
2779static void mmc_set_initial_state(struct mmc *mmc)
2780{
2781 int err;
2782
2783 /* First try to set 3.3V. If it fails set to 1.8V */
2784 err = mmc_set_signal_voltage(mmc, MMC_SIGNAL_VOLTAGE_330);
2785 if (err != 0)
2786 err = mmc_set_signal_voltage(mmc, MMC_SIGNAL_VOLTAGE_180);
2787 if (err != 0)
d8e3d420 2788 pr_warn("mmc: failed to set signal voltage\n");
fb7c3beb
KVA		 2789
2790 mmc_select_mode(mmc, MMC_LEGACY);
2791 mmc_set_bus_width(mmc, 1);
65117182 2792 mmc_set_clock(mmc, 0, MMC_CLK_ENABLE);
fb7c3beb 2793}
06ec045f 2794
fb7c3beb
KVA		 2795static int mmc_power_on(struct mmc *mmc)
2796{
2797#if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(DM_REGULATOR)
06ec045f 2798 if (mmc->vmmc_supply) {
9a2e9cc6
JK		 2799 int ret = regulator_set_enable_if_allowed(mmc->vmmc_supply,
2800 true);
fb7c3beb 2801
9a2e9cc6 2802 if (ret && ret != -ENOSYS) {
58896458 2803 printf("Error enabling VMMC supply : %d\n", ret);
06ec045f
JJH		 2804 return ret;
2805 }
2051aefe 2806 }
05cbeb7c 2807#endif
fb7c3beb
KVA		 2808 return 0;
2809}
2810
2811static int mmc_power_off(struct mmc *mmc)
2812{
65117182 2813 mmc_set_clock(mmc, 0, MMC_CLK_DISABLE);
fb7c3beb
KVA		 2814#if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(DM_REGULATOR)
2815 if (mmc->vmmc_supply) {
9a2e9cc6
JK		 2816 int ret = regulator_set_enable_if_allowed(mmc->vmmc_supply,
2817 false);
fb7c3beb 2818
9a2e9cc6 2819 if (ret && ret != -ENOSYS) {
58896458 2820 pr_debug("Error disabling VMMC supply : %d\n", ret);
fb7c3beb
KVA		 2821 return ret;
2822 }
2823 }
2051aefe
PF		 2824#endif
2825 return 0;
2826}
2827
fb7c3beb
KVA		 2828static int mmc_power_cycle(struct mmc *mmc)
2829{
2830 int ret;
2831
2832 ret = mmc_power_off(mmc);
2833 if (ret)
2834 return ret;
3602a56a
YG		 2835
2836 ret = mmc_host_power_cycle(mmc);
2837 if (ret)
2838 return ret;
2839
fb7c3beb
KVA		 2840 /*
2841 * SD spec recommends at least 1ms of delay. Let's wait for 2ms
2842 * to be on the safer side.
2843 */
2844 udelay(2000);
2845 return mmc_power_on(mmc);
2846}
2847
a4c577f9 2848int mmc_get_op_cond(struct mmc *mmc, bool quiet)
272cc70b 2849{
c10b85d6 2850 bool uhs_en = supports_uhs(mmc->cfg->host_caps);
afd5932b 2851 int err;
272cc70b 2852
bc897b1d
LW		 2853 if (mmc->has_init)
2854 return 0;
2855
2051aefe
PF		 2856 err = mmc_power_init(mmc);
2857 if (err)
2858 return err;
95de9ab2 2859
83dc4227
KVA		 2860#ifdef CONFIG_MMC_QUIRKS
2861 mmc->quirks = MMC_QUIRK_RETRY_SET_BLOCKLEN |
d4a5fa31
JJ		 2862 MMC_QUIRK_RETRY_SEND_CID |
2863 MMC_QUIRK_RETRY_APP_CMD;
83dc4227
KVA		 2864#endif
2865
04a2ea24
JJH		 2866 err = mmc_power_cycle(mmc);
2867 if (err) {
2868 /*
2869 * if power cycling is not supported, we should not try
2870 * to use the UHS modes, because we wouldn't be able to
2871 * recover from an error during the UHS initialization.
2872 */
d4d64889 2873 pr_debug("Unable to do a full power cycle. Disabling the UHS modes for safety\n");
04a2ea24
JJH		 2874 uhs_en = false;
2875 mmc->host_caps &= ~UHS_CAPS;
2876 err = mmc_power_on(mmc);
2877 }
fb7c3beb
KVA		 2878 if (err)
2879 return err;
2880
e7881d85 2881#if CONFIG_IS_ENABLED(DM_MMC)
390f9bdd
YL		 2882 /*
2883 * Re-initialization is needed to clear old configuration for
2884 * mmc rescan.
2885 */
2886 err = mmc_reinit(mmc);
8ca51e51 2887#else
ab769f22 2888 /* made sure it's not NULL earlier */
93bfd616 2889 err = mmc->cfg->ops->init(mmc);
390f9bdd 2890#endif
272cc70b
AF		 2891 if (err)
2892 return err;
786e8f81 2893 mmc->ddr_mode = 0;
aff5d3c8 2894
c10b85d6 2895retry:
fb7c3beb 2896 mmc_set_initial_state(mmc);
318a7a57 2897
272cc70b
AF		 2898 /* Reset the Card */
2899 err = mmc_go_idle(mmc);
2900
2901 if (err)
2902 return err;
2903
f5624b10 2904 /* The internal partition reset to user partition(0) at every CMD0 */
c40fdca6 2905 mmc_get_blk_desc(mmc)->hwpart = 0;
bc897b1d 2906
272cc70b 2907 /* Test for SD version 2 */
afd5932b 2908 err = mmc_send_if_cond(mmc);
272cc70b 2909
272cc70b 2910 /* Now try to get the SD card's operating condition */
c10b85d6
JJH		 2911 err = sd_send_op_cond(mmc, uhs_en);
2912 if (err && uhs_en) {
2913 uhs_en = false;
2914 mmc_power_cycle(mmc);
2915 goto retry;
2916 }
272cc70b
AF		 2917
2918 /* If the command timed out, we check for an MMC card */
915ffa52 2919 if (err == -ETIMEDOUT) {
272cc70b
AF		 2920 err = mmc_send_op_cond(mmc);
2921
bd47c135 2922 if (err) {
56196826 2923#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
a4c577f9
T		 2924 if (!quiet)
2925 pr_err("Card did not respond to voltage select! : %d\n", err);
56196826 2926#endif
915ffa52 2927 return -EOPNOTSUPP;
272cc70b
AF		 2928 }
2929 }
2930
6c09eba5
JN		 2931 return err;
2932}
2933
2934int mmc_start_init(struct mmc *mmc)
2935{
2936 bool no_card;
2937 int err = 0;
2938
2939 /*
2940 * all hosts are capable of 1 bit bus-width and able to use the legacy
2941 * timings.
2942 */
e8d5dde4 2943 mmc->host_caps = mmc->cfg->host_caps | MMC_CAP(MMC_LEGACY) |
19f7a34a
AG		 2944 MMC_MODE_1BIT;
2945
2946 if (IS_ENABLED(CONFIG_MMC_SPEED_MODE_SET)) {
2947 if (mmc->user_speed_mode != MMC_MODES_END) {
2948 int i;
2949 /* set host caps */
2950 if (mmc->host_caps & MMC_CAP(mmc->user_speed_mode)) {
2951 /* Remove all existing speed capabilities */
2952 for (i = MMC_LEGACY; i < MMC_MODES_END; i++)
2953 mmc->host_caps &= ~MMC_CAP(i);
2954 mmc->host_caps |= (MMC_CAP(mmc->user_speed_mode)
2955 | MMC_CAP(MMC_LEGACY) |
2956 MMC_MODE_1BIT);
2957 } else {
2958 pr_err("bus_mode requested is not supported\n");
2959 return -EINVAL;
2960 }
2961 }
2962 }
32860bdb
FA		 2963#if CONFIG_IS_ENABLED(DM_MMC)
2964 mmc_deferred_probe(mmc);
2965#endif
6c09eba5 2966#if !defined(CONFIG_MMC_BROKEN_CD)
6c09eba5
JN		 2967 no_card = mmc_getcd(mmc) == 0;
2968#else
2969 no_card = 0;
2970#endif
2971#if !CONFIG_IS_ENABLED(DM_MMC)
fea3939d 2972 /* we pretend there's no card when init is NULL */
6c09eba5
JN		 2973 no_card = no_card || (mmc->cfg->ops->init == NULL);
2974#endif
2975 if (no_card) {
2976 mmc->has_init = 0;
2977#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
2978 pr_err("MMC: no card present\n");
2979#endif
2980 return -ENOMEDIUM;
2981 }
2982
a4c577f9 2983 err = mmc_get_op_cond(mmc, false);
6c09eba5 2984
bd47c135 2985 if (!err)
e9550449
CLC		 2986 mmc->init_in_progress = 1;
2987
2988 return err;
2989}
2990
2991static int mmc_complete_init(struct mmc *mmc)
2992{
2993 int err = 0;
2994
bd47c135 2995 mmc->init_in_progress = 0;
e9550449
CLC		 2996 if (mmc->op_cond_pending)
2997 err = mmc_complete_op_cond(mmc);
2998
2999 if (!err)
3000 err = mmc_startup(mmc);
bc897b1d
LW		 3001 if (err)
3002 mmc->has_init = 0;
3003 else
3004 mmc->has_init = 1;
e9550449
CLC		 3005 return err;
3006}
3007
3008int mmc_init(struct mmc *mmc)
3009{
bd47c135 3010 int err = 0;
36332b6e 3011 __maybe_unused ulong start;
c4d660d4 3012#if CONFIG_IS_ENABLED(DM_MMC)
33fb211d 3013 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(mmc->dev);
e9550449 3014
33fb211d
SG		 3015 upriv->mmc = mmc;
3016#endif
e9550449
CLC		 3017 if (mmc->has_init)
3018 return 0;
d803fea5
MZ		 3019
3020 start = get_timer(0);
3021
e9550449
CLC		 3022 if (!mmc->init_in_progress)
3023 err = mmc_start_init(mmc);
3024
bd47c135 3025 if (!err)
e9550449 3026 err = mmc_complete_init(mmc);
919b4858 3027 if (err)
d4d64889 3028 pr_info("%s: %d, time %lu\n", __func__, err, get_timer(start));
919b4858 3029
bc897b1d 3030 return err;
272cc70b
AF		 3031}
3032
fceea992
MV		 3033int mmc_deinit(struct mmc *mmc)
3034{
3035 u32 caps_filtered;
3036
27ba82cb
MV		 3037 if (!CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) &&
3038 !CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) &&
3039 !CONFIG_IS_ENABLED(MMC_HS400_SUPPORT))
3040 return 0;
3041
fceea992
MV		 3042 if (!mmc->has_init)
3043 return 0;
3044
3045 if (IS_SD(mmc)) {
3046 caps_filtered = mmc->card_caps &
3047 ~(MMC_CAP(UHS_SDR12) | MMC_CAP(UHS_SDR25) |
3048 MMC_CAP(UHS_SDR50) | MMC_CAP(UHS_DDR50) |
3049 MMC_CAP(UHS_SDR104));
3050
3051 return sd_select_mode_and_width(mmc, caps_filtered);
3052 } else {
3053 caps_filtered = mmc->card_caps &
fb8c2e8f 3054 ~(MMC_CAP(MMC_HS_200) | MMC_CAP(MMC_HS_400) | MMC_CAP(MMC_HS_400_ES));
fceea992
MV		 3055
3056 return mmc_select_mode_and_width(mmc, caps_filtered);
3057 }
3058}
fceea992 3059
ab71188c
MN		 3060int mmc_set_dsr(struct mmc *mmc, u16 val)
3061{
3062 mmc->dsr = val;
3063 return 0;
3064}
3065
cee9ab7c 3066/* CPU-specific MMC initializations */
b75d8dc5 3067__weak int cpu_mmc_init(struct bd_info *bis)
272cc70b
AF		 3068{
3069 return -1;
3070}
3071
cee9ab7c 3072/* board-specific MMC initializations. */
b75d8dc5 3073__weak int board_mmc_init(struct bd_info *bis)
cee9ab7c
JH		 3074{
3075 return -1;
3076}
272cc70b 3077
e9550449
CLC		 3078void mmc_set_preinit(struct mmc *mmc, int preinit)
3079{
3080 mmc->preinit = preinit;
3081}
3082
8a856db2 3083#if CONFIG_IS_ENABLED(DM_MMC)
b75d8dc5 3084static int mmc_probe(struct bd_info *bis)
8e3332e2 3085{
4a1db6d8 3086 int ret, i;
8e3332e2 3087 struct uclass *uc;
4a1db6d8 3088 struct udevice *dev;
8e3332e2
SS		 3089
3090 ret = uclass_get(UCLASS_MMC, &uc);
3091 if (ret)
3092 return ret;
3093
4a1db6d8
SG		 3094 /*
3095 * Try to add them in sequence order. Really with driver model we
3096 * should allow holes, but the current MMC list does not allow that.
3097 * So if we request 0, 1, 3 we will get 0, 1, 2.
3098 */
3099 for (i = 0; ; i++) {
3100 ret = uclass_get_device_by_seq(UCLASS_MMC, i, &dev);
3101 if (ret == -ENODEV)
3102 break;
3103 }
3104 uclass_foreach_dev(dev, uc) {
3105 ret = device_probe(dev);
8e3332e2 3106 if (ret)
d8e3d420 3107 pr_err("%s - probe failed: %d\n", dev->name, ret);
8e3332e2
SS		 3108 }
3109
3110 return 0;
3111}
3112#else
b75d8dc5 3113static int mmc_probe(struct bd_info *bis)
8e3332e2
SS		 3114{
3115 if (board_mmc_init(bis) < 0)
3116 cpu_mmc_init(bis);
3117
3118 return 0;
3119}
3120#endif
e9550449 3121
b75d8dc5 3122int mmc_initialize(struct bd_info *bis)
272cc70b 3123{
1b26bab1 3124 static int initialized = 0;
8e3332e2 3125 int ret;
1b26bab1
DK		 3126 if (initialized) /* Avoid initializing mmc multiple times */
3127 return 0;
3128 initialized = 1;
3129
c4d660d4 3130#if !CONFIG_IS_ENABLED(BLK)
b5b838f1 3131#if !CONFIG_IS_ENABLED(MMC_TINY)
c40fdca6 3132 mmc_list_init();
b5b838f1 3133#endif
c40fdca6 3134#endif
8e3332e2
SS		 3135 ret = mmc_probe(bis);
3136 if (ret)
3137 return ret;
272cc70b 3138
bb0dc108 3139#ifndef CONFIG_SPL_BUILD
272cc70b 3140 print_mmc_devices(',');
bb0dc108 3141#endif
272cc70b 3142
c40fdca6 3143 mmc_do_preinit();
272cc70b
AF		 3144 return 0;
3145}
cd3d4880 3146
80f02019
LV		 3147#if CONFIG_IS_ENABLED(DM_MMC)
3148int mmc_init_device(int num)
3149{
3150 struct udevice *dev;
3151 struct mmc *m;
3152 int ret;
3153
2153a08a
AG		 3154 if (uclass_get_device_by_seq(UCLASS_MMC, num, &dev)) {
3155 ret = uclass_get_device(UCLASS_MMC, num, &dev);
3156 if (ret)
3157 return ret;
3158 }
80f02019
LV		 3159
3160 m = mmc_get_mmc_dev(dev);
3161 if (!m)
3162 return 0;
337af54a
VYA		 3163
3164 /* Initialising user set speed mode */
3165 m->user_speed_mode = MMC_MODES_END;
3166
80f02019
LV		 3167 if (m->preinit)
3168 mmc_start_init(m);
3169
3170 return 0;
3171}
3172#endif
3173
cd3d4880 3174#ifdef CONFIG_CMD_BKOPS_ENABLE
cf1f7355 3175int mmc_set_bkops_enable(struct mmc *mmc, bool autobkops, bool enable)
cd3d4880
TM		 3176{
3177 int err;
cf1f7355 3178 u32 bit = autobkops ? BIT(1) : BIT(0);
cd3d4880
TM		 3179 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
3180
3181 err = mmc_send_ext_csd(mmc, ext_csd);
3182 if (err) {
3183 puts("Could not get ext_csd register values\n");
3184 return err;
3185 }
3186
3187 if (!(ext_csd[EXT_CSD_BKOPS_SUPPORT] & 0x1)) {
3188 puts("Background operations not supported on device\n");
3189 return -EMEDIUMTYPE;
3190 }
3191
cf1f7355 3192 if (enable && (ext_csd[EXT_CSD_BKOPS_EN] & bit)) {
cd3d4880
TM		 3193 puts("Background operations already enabled\n");
3194 return 0;
3195 }
3196
cf1f7355
MV		 3197 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BKOPS_EN,
3198 enable ? bit : 0);
cd3d4880 3199 if (err) {
cf1f7355
MV		 3200 printf("Failed to %sable manual background operations\n",
3201 enable ? "en" : "dis");
cd3d4880
TM		 3202 return err;
3203 }
3204
cf1f7355
MV		 3205 printf("%sabled %s background operations\n",
3206 enable ? "En" : "Dis", autobkops ? "auto" : "manual");
cd3d4880
TM		 3207
3208 return 0;
3209}
3210#endif
4dee3f78
DW		 3211
3212__weak int mmc_get_env_dev(void)
3213{
3214#ifdef CONFIG_SYS_MMC_ENV_DEV
3215 return CONFIG_SYS_MMC_ENV_DEV;
3216#else
3217 return 0;
3218#endif
3219}
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