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mmc: fsl_esdhc_imx: disable the CMD CRC check for standard tuning
[u-boot.git] / drivers / mmc / mmc.c
CommitLineData
83d290c5 1// SPDX-License-Identifier: GPL-2.0+
272cc70b
AF		 2/*
3 * Copyright 2008, Freescale Semiconductor, Inc
4 * Andy Fleming
5 *
6 * Based vaguely on the Linux code
272cc70b
AF		 7 */
8
9#include <config.h>
10#include <common.h>
e6f6f9e6 11#include <blk.h>
272cc70b 12#include <command.h>
8e3332e2 13#include <dm.h>
f7ae49fc 14#include <log.h>
8e3332e2 15#include <dm/device-internal.h>
d4622df3 16#include <errno.h>
272cc70b
AF		 17#include <mmc.h>
18#include <part.h>
cd93d625 19#include <linux/bitops.h>
c05ed00a 20#include <linux/delay.h>
2051aefe 21#include <power/regulator.h>
272cc70b 22#include <malloc.h>
cf92e05c 23#include <memalign.h>
272cc70b 24#include <linux/list.h>
9b1f942c 25#include <div64.h>
da61fa5f 26#include "mmc_private.h"
272cc70b 27
39320c53
JJH		 28#define DEFAULT_CMD6_TIMEOUT_MS 500
29
aff5d3c8 30static int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage);
b5b838f1 31
e7881d85 32#if !CONFIG_IS_ENABLED(DM_MMC)
c10b85d6 33
6cf8a903 34static int mmc_wait_dat0(struct mmc *mmc, int state, int timeout_us)
c10b85d6
JJH		 35{
36 return -ENOSYS;
37}
38
750121c3 39__weak int board_mmc_getwp(struct mmc *mmc)
d23d8d7e
NK		 40{
41 return -1;
42}
43
44int mmc_getwp(struct mmc *mmc)
45{
46 int wp;
47
48 wp = board_mmc_getwp(mmc);
49
d4e1da4e 50 if (wp < 0) {
93bfd616
PA		 51 if (mmc->cfg->ops->getwp)
52 wp = mmc->cfg->ops->getwp(mmc);
d4e1da4e
PK		 53 else
54 wp = 0;
55 }
d23d8d7e
NK		 56
57 return wp;
58}
59
cee9ab7c
JH		 60__weak int board_mmc_getcd(struct mmc *mmc)
61{
11fdade2
SB		 62 return -1;
63}
8ca51e51 64#endif
11fdade2 65
c0c76eba
SG		 66#ifdef CONFIG_MMC_TRACE
67void mmmc_trace_before_send(struct mmc *mmc, struct mmc_cmd *cmd)
272cc70b 68{
c0c76eba 69 printf("CMD_SEND:%d\n", cmd->cmdidx);
7d5ccb1a 70 printf("\t\tARG\t\t\t 0x%08x\n", cmd->cmdarg);
c0c76eba 71}
8635ff9e 72
c0c76eba
SG		 73void mmmc_trace_after_send(struct mmc *mmc, struct mmc_cmd *cmd, int ret)
74{
5db2fe3a
RR		 75 int i;
76 u8 *ptr;
77
7863ce58
BM		 78 if (ret) {
79 printf("\t\tRET\t\t\t %d\n", ret);
80 } else {
81 switch (cmd->resp_type) {
82 case MMC_RSP_NONE:
83 printf("\t\tMMC_RSP_NONE\n");
84 break;
85 case MMC_RSP_R1:
7d5ccb1a 86 printf("\t\tMMC_RSP_R1,5,6,7 \t 0x%08x \n",
7863ce58
BM		 87 cmd->response[0]);
88 break;
89 case MMC_RSP_R1b:
7d5ccb1a 90 printf("\t\tMMC_RSP_R1b\t\t 0x%08x \n",
7863ce58
BM		 91 cmd->response[0]);
92 break;
93 case MMC_RSP_R2:
7d5ccb1a 94 printf("\t\tMMC_RSP_R2\t\t 0x%08x \n",
7863ce58 95 cmd->response[0]);
7d5ccb1a 96 printf("\t\t \t\t 0x%08x \n",
7863ce58 97 cmd->response[1]);
7d5ccb1a 98 printf("\t\t \t\t 0x%08x \n",
7863ce58 99 cmd->response[2]);
7d5ccb1a 100 printf("\t\t \t\t 0x%08x \n",
7863ce58 101 cmd->response[3]);
5db2fe3a 102 printf("\n");
7863ce58
BM		 103 printf("\t\t\t\t\tDUMPING DATA\n");
104 for (i = 0; i < 4; i++) {
105 int j;
106 printf("\t\t\t\t\t%03d - ", i*4);
107 ptr = (u8 *)&cmd->response[i];
108 ptr += 3;
109 for (j = 0; j < 4; j++)
7d5ccb1a 110 printf("%02x ", *ptr--);
7863ce58
BM		 111 printf("\n");
112 }
113 break;
114 case MMC_RSP_R3:
7d5ccb1a 115 printf("\t\tMMC_RSP_R3,4\t\t 0x%08x \n",
7863ce58
BM		 116 cmd->response[0]);
117 break;
118 default:
119 printf("\t\tERROR MMC rsp not supported\n");
120 break;
53e8e40b 121 }
5db2fe3a 122 }
c0c76eba
SG		 123}
124
125void mmc_trace_state(struct mmc *mmc, struct mmc_cmd *cmd)
126{
127 int status;
128
129 status = (cmd->response[0] & MMC_STATUS_CURR_STATE) >> 9;
130 printf("CURR STATE:%d\n", status);
131}
5db2fe3a 132#endif
c0c76eba 133
35f9e196
JJH		 134#if CONFIG_IS_ENABLED(MMC_VERBOSE) || defined(DEBUG)
135const char *mmc_mode_name(enum bus_mode mode)
136{
137 static const char *const names[] = {
138 [MMC_LEGACY] = "MMC legacy",
35f9e196
JJH		 139 [MMC_HS] = "MMC High Speed (26MHz)",
140 [SD_HS] = "SD High Speed (50MHz)",
141 [UHS_SDR12] = "UHS SDR12 (25MHz)",
142 [UHS_SDR25] = "UHS SDR25 (50MHz)",
143 [UHS_SDR50] = "UHS SDR50 (100MHz)",
144 [UHS_SDR104] = "UHS SDR104 (208MHz)",
145 [UHS_DDR50] = "UHS DDR50 (50MHz)",
146 [MMC_HS_52] = "MMC High Speed (52MHz)",
147 [MMC_DDR_52] = "MMC DDR52 (52MHz)",
148 [MMC_HS_200] = "HS200 (200MHz)",
3dd2626f 149 [MMC_HS_400] = "HS400 (200MHz)",
44acd492 150 [MMC_HS_400_ES] = "HS400ES (200MHz)",
35f9e196
JJH		 151 };
152
153 if (mode >= MMC_MODES_END)
154 return "Unknown mode";
155 else
156 return names[mode];
157}
158#endif
159
05038576
JJH		 160static uint mmc_mode2freq(struct mmc *mmc, enum bus_mode mode)
161{
162 static const int freqs[] = {
1b313aa3 163 [MMC_LEGACY] = 25000000,
05038576
JJH		 164 [MMC_HS] = 26000000,
165 [SD_HS] = 50000000,
1b313aa3
JC		 166 [MMC_HS_52] = 52000000,
167 [MMC_DDR_52] = 52000000,
05038576
JJH		 168 [UHS_SDR12] = 25000000,
169 [UHS_SDR25] = 50000000,
170 [UHS_SDR50] = 100000000,
05038576 171 [UHS_DDR50] = 50000000,
f99c2efe 172 [UHS_SDR104] = 208000000,
05038576 173 [MMC_HS_200] = 200000000,
3dd2626f 174 [MMC_HS_400] = 200000000,
44acd492 175 [MMC_HS_400_ES] = 200000000,
05038576
JJH		 176 };
177
178 if (mode == MMC_LEGACY)
179 return mmc->legacy_speed;
180 else if (mode >= MMC_MODES_END)
181 return 0;
182 else
183 return freqs[mode];
184}
185
35f9e196
JJH		 186static int mmc_select_mode(struct mmc *mmc, enum bus_mode mode)
187{
188 mmc->selected_mode = mode;
05038576 189 mmc->tran_speed = mmc_mode2freq(mmc, mode);
3862b854 190 mmc->ddr_mode = mmc_is_mode_ddr(mode);
d4d64889
MY		 191 pr_debug("selecting mode %s (freq : %d MHz)\n", mmc_mode_name(mode),
192 mmc->tran_speed / 1000000);
35f9e196
JJH		 193 return 0;
194}
195
e7881d85 196#if !CONFIG_IS_ENABLED(DM_MMC)
c0c76eba
SG		 197int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
198{
199 int ret;
200
201 mmmc_trace_before_send(mmc, cmd);
202 ret = mmc->cfg->ops->send_cmd(mmc, cmd, data);
203 mmmc_trace_after_send(mmc, cmd, ret);
204
8635ff9e 205 return ret;
272cc70b 206}
8ca51e51 207#endif
272cc70b 208
863d1004 209int mmc_send_status(struct mmc *mmc, unsigned int *status)
5d4fc8d9
RR		 210{
211 struct mmc_cmd cmd;
d617c426 212 int err, retries = 5;
5d4fc8d9
RR		 213
214 cmd.cmdidx = MMC_CMD_SEND_STATUS;
215 cmd.resp_type = MMC_RSP_R1;
aaf3d41a
MV		 216 if (!mmc_host_is_spi(mmc))
217 cmd.cmdarg = mmc->rca << 16;
5d4fc8d9 218
863d1004 219 while (retries--) {
5d4fc8d9 220 err = mmc_send_cmd(mmc, &cmd, NULL);
d617c426 221 if (!err) {
863d1004
JJH		 222 mmc_trace_state(mmc, &cmd);
223 *status = cmd.response[0];
224 return 0;
225 }
226 }
227 mmc_trace_state(mmc, &cmd);
228 return -ECOMM;
229}
230
6cf8a903 231int mmc_poll_for_busy(struct mmc *mmc, int timeout_ms)
863d1004
JJH		 232{
233 unsigned int status;
234 int err;
d0c221fe 235
6cf8a903 236 err = mmc_wait_dat0(mmc, 1, timeout_ms * 1000);
cd0b80ec
JJH		 237 if (err != -ENOSYS)
238 return err;
239
863d1004
JJH		 240 while (1) {
241 err = mmc_send_status(mmc, &status);
242 if (err)
243 return err;
244
245 if ((status & MMC_STATUS_RDY_FOR_DATA) &&
246 (status & MMC_STATUS_CURR_STATE) !=
247 MMC_STATE_PRG)
248 break;
249
250 if (status & MMC_STATUS_MASK) {
56196826 251#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
863d1004 252 pr_err("Status Error: 0x%08x\n", status);
56196826 253#endif
863d1004
JJH		 254 return -ECOMM;
255 }
5d4fc8d9 256
6cf8a903 257 if (timeout_ms-- <= 0)
1677eef4 258 break;
5d4fc8d9 259
1677eef4
AG		 260 udelay(1000);
261 }
5d4fc8d9 262
6cf8a903 263 if (timeout_ms <= 0) {
56196826 264#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
d8e3d420 265 pr_err("Timeout waiting card ready\n");
56196826 266#endif
915ffa52 267 return -ETIMEDOUT;
5d4fc8d9
RR		 268 }
269
270 return 0;
271}
272
da61fa5f 273int mmc_set_blocklen(struct mmc *mmc, int len)
272cc70b
AF		 274{
275 struct mmc_cmd cmd;
83dc4227 276 int err;
272cc70b 277
786e8f81 278 if (mmc->ddr_mode)
d22e3d46
JC		 279 return 0;
280
272cc70b
AF		 281 cmd.cmdidx = MMC_CMD_SET_BLOCKLEN;
282 cmd.resp_type = MMC_RSP_R1;
283 cmd.cmdarg = len;
272cc70b 284
83dc4227
KVA		 285 err = mmc_send_cmd(mmc, &cmd, NULL);
286
287#ifdef CONFIG_MMC_QUIRKS
288 if (err && (mmc->quirks & MMC_QUIRK_RETRY_SET_BLOCKLEN)) {
289 int retries = 4;
290 /*
291 * It has been seen that SET_BLOCKLEN may fail on the first
292 * attempt, let's try a few more time
293 */
294 do {
295 err = mmc_send_cmd(mmc, &cmd, NULL);
296 if (!err)
297 break;
298 } while (retries--);
299 }
300#endif
301
302 return err;
272cc70b
AF		 303}
304
f99c2efe 305#ifdef MMC_SUPPORTS_TUNING
9815e3ba
JJH		 306static const u8 tuning_blk_pattern_4bit[] = {
307 0xff, 0x0f, 0xff, 0x00, 0xff, 0xcc, 0xc3, 0xcc,
308 0xc3, 0x3c, 0xcc, 0xff, 0xfe, 0xff, 0xfe, 0xef,
309 0xff, 0xdf, 0xff, 0xdd, 0xff, 0xfb, 0xff, 0xfb,
310 0xbf, 0xff, 0x7f, 0xff, 0x77, 0xf7, 0xbd, 0xef,
311 0xff, 0xf0, 0xff, 0xf0, 0x0f, 0xfc, 0xcc, 0x3c,
312 0xcc, 0x33, 0xcc, 0xcf, 0xff, 0xef, 0xff, 0xee,
313 0xff, 0xfd, 0xff, 0xfd, 0xdf, 0xff, 0xbf, 0xff,
314 0xbb, 0xff, 0xf7, 0xff, 0xf7, 0x7f, 0x7b, 0xde,
315};
316
317static const u8 tuning_blk_pattern_8bit[] = {
318 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00, 0x00,
319 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc, 0xcc,
320 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff, 0xff,
321 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee, 0xff,
322 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd, 0xdd,
323 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff, 0xbb,
324 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff, 0xff,
325 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee, 0xff,
326 0xff, 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00,
327 0x00, 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc,
328 0xcc, 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff,
329 0xff, 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee,
330 0xff, 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd,
331 0xdd, 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff,
332 0xbb, 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff,
333 0xff, 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee,
334};
335
336int mmc_send_tuning(struct mmc *mmc, u32 opcode, int *cmd_error)
337{
338 struct mmc_cmd cmd;
339 struct mmc_data data;
340 const u8 *tuning_block_pattern;
341 int size, err;
342
343 if (mmc->bus_width == 8) {
344 tuning_block_pattern = tuning_blk_pattern_8bit;
345 size = sizeof(tuning_blk_pattern_8bit);
346 } else if (mmc->bus_width == 4) {
347 tuning_block_pattern = tuning_blk_pattern_4bit;
348 size = sizeof(tuning_blk_pattern_4bit);
349 } else {
350 return -EINVAL;
351 }
352
353 ALLOC_CACHE_ALIGN_BUFFER(u8, data_buf, size);
354
355 cmd.cmdidx = opcode;
356 cmd.cmdarg = 0;
357 cmd.resp_type = MMC_RSP_R1;
358
359 data.dest = (void *)data_buf;
360 data.blocks = 1;
361 data.blocksize = size;
362 data.flags = MMC_DATA_READ;
363
364 err = mmc_send_cmd(mmc, &cmd, &data);
365 if (err)
366 return err;
367
368 if (memcmp(data_buf, tuning_block_pattern, size))
369 return -EIO;
370
371 return 0;
372}
f99c2efe 373#endif
9815e3ba 374
ff8fef56 375static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start,
fdbb873e 376 lbaint_t blkcnt)
272cc70b
AF		 377{
378 struct mmc_cmd cmd;
379 struct mmc_data data;
380
4a1a06bc
AS		 381 if (blkcnt > 1)
382 cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK;
383 else
384 cmd.cmdidx = MMC_CMD_READ_SINGLE_BLOCK;
272cc70b
AF		 385
386 if (mmc->high_capacity)
4a1a06bc 387 cmd.cmdarg = start;
272cc70b 388 else
4a1a06bc 389 cmd.cmdarg = start * mmc->read_bl_len;
272cc70b
AF		 390
391 cmd.resp_type = MMC_RSP_R1;
272cc70b
AF		 392
393 data.dest = dst;
4a1a06bc 394 data.blocks = blkcnt;
272cc70b
AF		 395 data.blocksize = mmc->read_bl_len;
396 data.flags = MMC_DATA_READ;
397
4a1a06bc
AS		 398 if (mmc_send_cmd(mmc, &cmd, &data))
399 return 0;
272cc70b 400
4a1a06bc
AS		 401 if (blkcnt > 1) {
402 cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
403 cmd.cmdarg = 0;
404 cmd.resp_type = MMC_RSP_R1b;
4a1a06bc 405 if (mmc_send_cmd(mmc, &cmd, NULL)) {
56196826 406#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
d8e3d420 407 pr_err("mmc fail to send stop cmd\n");
56196826 408#endif
4a1a06bc
AS		 409 return 0;
410 }
272cc70b
AF		 411 }
412
4a1a06bc 413 return blkcnt;
272cc70b
AF		 414}
415
145429aa
MV		 416#if !CONFIG_IS_ENABLED(DM_MMC)
417static int mmc_get_b_max(struct mmc *mmc, void *dst, lbaint_t blkcnt)
418{
419 if (mmc->cfg->ops->get_b_max)
420 return mmc->cfg->ops->get_b_max(mmc, dst, blkcnt);
421 else
422 return mmc->cfg->b_max;
423}
424#endif
425
c4d660d4 426#if CONFIG_IS_ENABLED(BLK)
7dba0b93 427ulong mmc_bread(struct udevice *dev, lbaint_t start, lbaint_t blkcnt, void *dst)
33fb211d 428#else
7dba0b93
SG		 429ulong mmc_bread(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt,
430 void *dst)
33fb211d 431#endif
272cc70b 432{
c4d660d4 433#if CONFIG_IS_ENABLED(BLK)
33fb211d
SG		 434 struct blk_desc *block_dev = dev_get_uclass_platdata(dev);
435#endif
bcce53d0 436 int dev_num = block_dev->devnum;
873cc1d7 437 int err;
4a1a06bc 438 lbaint_t cur, blocks_todo = blkcnt;
145429aa 439 uint b_max;
4a1a06bc
AS		 440
441 if (blkcnt == 0)
442 return 0;
272cc70b 443
4a1a06bc 444 struct mmc *mmc = find_mmc_device(dev_num);
272cc70b
AF		 445 if (!mmc)
446 return 0;
447
b5b838f1
MV		 448 if (CONFIG_IS_ENABLED(MMC_TINY))
449 err = mmc_switch_part(mmc, block_dev->hwpart);
450 else
451 err = blk_dselect_hwpart(block_dev, block_dev->hwpart);
452
873cc1d7
SW		 453 if (err < 0)
454 return 0;
455
c40fdca6 456 if ((start + blkcnt) > block_dev->lba) {
56196826 457#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
d8e3d420
JJH		 458 pr_err("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n",
459 start + blkcnt, block_dev->lba);
56196826 460#endif
d2bf29e3
LW		 461 return 0;
462 }
272cc70b 463
11692991 464 if (mmc_set_blocklen(mmc, mmc->read_bl_len)) {
d4d64889 465 pr_debug("%s: Failed to set blocklen\n", __func__);
272cc70b 466 return 0;
11692991 467 }
272cc70b 468
145429aa
MV		 469 b_max = mmc_get_b_max(mmc, dst, blkcnt);
470
4a1a06bc 471 do {
145429aa 472 cur = (blocks_todo > b_max) ? b_max : blocks_todo;
11692991 473 if (mmc_read_blocks(mmc, dst, start, cur) != cur) {
d4d64889 474 pr_debug("%s: Failed to read blocks\n", __func__);
4a1a06bc 475 return 0;
11692991 476 }
4a1a06bc
AS		 477 blocks_todo -= cur;
478 start += cur;
479 dst += cur * mmc->read_bl_len;
480 } while (blocks_todo > 0);
272cc70b
AF		 481
482 return blkcnt;
483}
484
fdbb873e 485static int mmc_go_idle(struct mmc *mmc)
272cc70b
AF		 486{
487 struct mmc_cmd cmd;
488 int err;
489
490 udelay(1000);
491
492 cmd.cmdidx = MMC_CMD_GO_IDLE_STATE;
493 cmd.cmdarg = 0;
494 cmd.resp_type = MMC_RSP_NONE;
272cc70b
AF		 495
496 err = mmc_send_cmd(mmc, &cmd, NULL);
497
498 if (err)
499 return err;
500
501 udelay(2000);
502
503 return 0;
504}
505
f99c2efe 506#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
c10b85d6
JJH		 507static int mmc_switch_voltage(struct mmc *mmc, int signal_voltage)
508{
509 struct mmc_cmd cmd;
510 int err = 0;
511
512 /*
513 * Send CMD11 only if the request is to switch the card to
514 * 1.8V signalling.
515 */
516 if (signal_voltage == MMC_SIGNAL_VOLTAGE_330)
517 return mmc_set_signal_voltage(mmc, signal_voltage);
518
519 cmd.cmdidx = SD_CMD_SWITCH_UHS18V;
520 cmd.cmdarg = 0;
521 cmd.resp_type = MMC_RSP_R1;
522
523 err = mmc_send_cmd(mmc, &cmd, NULL);
524 if (err)
525 return err;
526
527 if (!mmc_host_is_spi(mmc) && (cmd.response[0] & MMC_STATUS_ERROR))
528 return -EIO;
529
530 /*
531 * The card should drive cmd and dat[0:3] low immediately
532 * after the response of cmd11, but wait 100 us to be sure
533 */
534 err = mmc_wait_dat0(mmc, 0, 100);
535 if (err == -ENOSYS)
536 udelay(100);
537 else if (err)
538 return -ETIMEDOUT;
539
540 /*
541 * During a signal voltage level switch, the clock must be gated
542 * for 5 ms according to the SD spec
543 */
65117182 544 mmc_set_clock(mmc, mmc->clock, MMC_CLK_DISABLE);
c10b85d6
JJH		 545
546 err = mmc_set_signal_voltage(mmc, signal_voltage);
547 if (err)
548 return err;
549
550 /* Keep clock gated for at least 10 ms, though spec only says 5 ms */
551 mdelay(10);
65117182 552 mmc_set_clock(mmc, mmc->clock, MMC_CLK_ENABLE);
c10b85d6
JJH		 553
554 /*
555 * Failure to switch is indicated by the card holding
556 * dat[0:3] low. Wait for at least 1 ms according to spec
557 */
558 err = mmc_wait_dat0(mmc, 1, 1000);
559 if (err == -ENOSYS)
560 udelay(1000);
561 else if (err)
562 return -ETIMEDOUT;
563
564 return 0;
565}
f99c2efe 566#endif
c10b85d6
JJH		 567
568static int sd_send_op_cond(struct mmc *mmc, bool uhs_en)
272cc70b
AF		 569{
570 int timeout = 1000;
571 int err;
572 struct mmc_cmd cmd;
573
1677eef4 574 while (1) {
272cc70b
AF		 575 cmd.cmdidx = MMC_CMD_APP_CMD;
576 cmd.resp_type = MMC_RSP_R1;
577 cmd.cmdarg = 0;
272cc70b
AF		 578
579 err = mmc_send_cmd(mmc, &cmd, NULL);
580
581 if (err)
582 return err;
583
584 cmd.cmdidx = SD_CMD_APP_SEND_OP_COND;
585 cmd.resp_type = MMC_RSP_R3;
250de12b
SB		 586
587 /*
588 * Most cards do not answer if some reserved bits
589 * in the ocr are set. However, Some controller
590 * can set bit 7 (reserved for low voltages), but
591 * how to manage low voltages SD card is not yet
592 * specified.
593 */
d52ebf10 594 cmd.cmdarg = mmc_host_is_spi(mmc) ? 0 :
93bfd616 595 (mmc->cfg->voltages & 0xff8000);
272cc70b
AF		 596
597 if (mmc->version == SD_VERSION_2)
598 cmd.cmdarg |= OCR_HCS;
599
c10b85d6
JJH		 600 if (uhs_en)
601 cmd.cmdarg |= OCR_S18R;
602
272cc70b
AF		 603 err = mmc_send_cmd(mmc, &cmd, NULL);
604
605 if (err)
606 return err;
607
1677eef4
AG		 608 if (cmd.response[0] & OCR_BUSY)
609 break;
610
611 if (timeout-- <= 0)
915ffa52 612 return -EOPNOTSUPP;
272cc70b 613
1677eef4
AG		 614 udelay(1000);
615 }
272cc70b
AF		 616
617 if (mmc->version != SD_VERSION_2)
618 mmc->version = SD_VERSION_1_0;
619
d52ebf10
TC		 620 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
621 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
622 cmd.resp_type = MMC_RSP_R3;
623 cmd.cmdarg = 0;
d52ebf10
TC		 624
625 err = mmc_send_cmd(mmc, &cmd, NULL);
626
627 if (err)
628 return err;
629 }
630
998be3dd 631 mmc->ocr = cmd.response[0];
272cc70b 632
f99c2efe 633#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
c10b85d6
JJH		 634 if (uhs_en && !(mmc_host_is_spi(mmc)) && (cmd.response[0] & 0x41000000)
635 == 0x41000000) {
636 err = mmc_switch_voltage(mmc, MMC_SIGNAL_VOLTAGE_180);
637 if (err)
638 return err;
639 }
f99c2efe 640#endif
c10b85d6 641
272cc70b
AF		 642 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
643 mmc->rca = 0;
644
645 return 0;
646}
647
5289b535 648static int mmc_send_op_cond_iter(struct mmc *mmc, int use_arg)
272cc70b 649{
5289b535 650 struct mmc_cmd cmd;
272cc70b
AF		 651 int err;
652
5289b535
AG		 653 cmd.cmdidx = MMC_CMD_SEND_OP_COND;
654 cmd.resp_type = MMC_RSP_R3;
655 cmd.cmdarg = 0;
5a20397b
RH		 656 if (use_arg && !mmc_host_is_spi(mmc))
657 cmd.cmdarg = OCR_HCS |
93bfd616 658 (mmc->cfg->voltages &
a626c8d4
AG		 659 (mmc->ocr & OCR_VOLTAGE_MASK)) |
660 (mmc->ocr & OCR_ACCESS_MODE);
e9550449 661
5289b535 662 err = mmc_send_cmd(mmc, &cmd, NULL);
e9550449
CLC		 663 if (err)
664 return err;
5289b535 665 mmc->ocr = cmd.response[0];
e9550449
CLC		 666 return 0;
667}
668
750121c3 669static int mmc_send_op_cond(struct mmc *mmc)
e9550449 670{
e9550449
CLC		 671 int err, i;
672
272cc70b
AF		 673 /* Some cards seem to need this */
674 mmc_go_idle(mmc);
675
31cacbab 676 /* Asking to the card its capabilities */
e9550449 677 for (i = 0; i < 2; i++) {
5289b535 678 err = mmc_send_op_cond_iter(mmc, i != 0);
e9550449
CLC		 679 if (err)
680 return err;
cd6881b5 681
e9550449 682 /* exit if not busy (flag seems to be inverted) */
a626c8d4 683 if (mmc->ocr & OCR_BUSY)
bd47c135 684 break;
e9550449 685 }
bd47c135
AG		 686 mmc->op_cond_pending = 1;
687 return 0;
e9550449 688}
cd6881b5 689
750121c3 690static int mmc_complete_op_cond(struct mmc *mmc)
e9550449
CLC		 691{
692 struct mmc_cmd cmd;
693 int timeout = 1000;
36332b6e 694 ulong start;
e9550449 695 int err;
cd6881b5 696
e9550449 697 mmc->op_cond_pending = 0;
cc17c01f 698 if (!(mmc->ocr & OCR_BUSY)) {
d188b113
YL		 699 /* Some cards seem to need this */
700 mmc_go_idle(mmc);
701
cc17c01f 702 start = get_timer(0);
1677eef4 703 while (1) {
cc17c01f
AG		 704 err = mmc_send_op_cond_iter(mmc, 1);
705 if (err)
706 return err;
1677eef4
AG		 707 if (mmc->ocr & OCR_BUSY)
708 break;
cc17c01f 709 if (get_timer(start) > timeout)
915ffa52 710 return -EOPNOTSUPP;
cc17c01f 711 udelay(100);
1677eef4 712 }
cc17c01f 713 }
272cc70b 714
d52ebf10
TC		 715 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
716 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
717 cmd.resp_type = MMC_RSP_R3;
718 cmd.cmdarg = 0;
d52ebf10
TC		 719
720 err = mmc_send_cmd(mmc, &cmd, NULL);
721
722 if (err)
723 return err;
a626c8d4
AG		 724
725 mmc->ocr = cmd.response[0];
d52ebf10
TC		 726 }
727
272cc70b 728 mmc->version = MMC_VERSION_UNKNOWN;
272cc70b
AF		 729
730 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
def816a2 731 mmc->rca = 1;
272cc70b
AF		 732
733 return 0;
734}
735
736
1601ea21 737int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd)
272cc70b
AF		 738{
739 struct mmc_cmd cmd;
740 struct mmc_data data;
741 int err;
742
743 /* Get the Card Status Register */
744 cmd.cmdidx = MMC_CMD_SEND_EXT_CSD;
745 cmd.resp_type = MMC_RSP_R1;
746 cmd.cmdarg = 0;
272cc70b 747
cdfd1ac6 748 data.dest = (char *)ext_csd;
272cc70b 749 data.blocks = 1;
8bfa195e 750 data.blocksize = MMC_MAX_BLOCK_LEN;
272cc70b
AF		 751 data.flags = MMC_DATA_READ;
752
753 err = mmc_send_cmd(mmc, &cmd, &data);
754
755 return err;
756}
757
6892550c
MV		 758static int __mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value,
759 bool send_status)
272cc70b 760{
bb98b8c5 761 unsigned int status, start;
272cc70b 762 struct mmc_cmd cmd;
6cf8a903 763 int timeout_ms = DEFAULT_CMD6_TIMEOUT_MS;
513e00b6
JJH		 764 bool is_part_switch = (set == EXT_CSD_CMD_SET_NORMAL) &&
765 (index == EXT_CSD_PART_CONF);
a9003dc6 766 int retries = 3;
5d4fc8d9 767 int ret;
272cc70b 768
39320c53 769 if (mmc->gen_cmd6_time)
6cf8a903 770 timeout_ms = mmc->gen_cmd6_time * 10;
39320c53 771
513e00b6 772 if (is_part_switch && mmc->part_switch_time)
6cf8a903 773 timeout_ms = mmc->part_switch_time * 10;
513e00b6 774
272cc70b
AF		 775 cmd.cmdidx = MMC_CMD_SWITCH;
776 cmd.resp_type = MMC_RSP_R1b;
777 cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) |
5d4fc8d9
RR		 778 (index << 16) |
779 (value << 8);
272cc70b 780
bb98b8c5 781 do {
a9003dc6 782 ret = mmc_send_cmd(mmc, &cmd, NULL);
bb98b8c5 783 } while (ret && retries-- > 0);
5d4fc8d9 784
bb98b8c5
JJH		 785 if (ret)
786 return ret;
6892550c 787
bb98b8c5 788 start = get_timer(0);
a9003dc6 789
bb98b8c5 790 /* poll dat0 for rdy/buys status */
6cf8a903 791 ret = mmc_wait_dat0(mmc, 1, timeout_ms * 1000);
bb98b8c5
JJH		 792 if (ret && ret != -ENOSYS)
793 return ret;
5d4fc8d9 794
bb98b8c5
JJH		 795 /*
796 * In cases when not allowed to poll by using CMD13 or because we aren't
797 * capable of polling by using mmc_wait_dat0, then rely on waiting the
798 * stated timeout to be sufficient.
799 */
800 if (ret == -ENOSYS && !send_status)
6cf8a903 801 mdelay(timeout_ms);
bb98b8c5
JJH		 802
803 /* Finally wait until the card is ready or indicates a failure
804 * to switch. It doesn't hurt to use CMD13 here even if send_status
6cf8a903 805 * is false, because by now (after 'timeout_ms' ms) the bus should be
bb98b8c5
JJH		 806 * reliable.
807 */
808 do {
809 ret = mmc_send_status(mmc, &status);
810
811 if (!ret && (status & MMC_STATUS_SWITCH_ERROR)) {
812 pr_debug("switch failed %d/%d/0x%x !\n", set, index,
813 value);
814 return -EIO;
815 }
816 if (!ret && (status & MMC_STATUS_RDY_FOR_DATA))
817 return 0;
818 udelay(100);
6cf8a903 819 } while (get_timer(start) < timeout_ms);
5d4fc8d9 820
bb98b8c5 821 return -ETIMEDOUT;
272cc70b
AF		 822}
823
6892550c
MV		 824int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value)
825{
826 return __mmc_switch(mmc, set, index, value, true);
827}
828
0469d846
HS		 829int mmc_boot_wp(struct mmc *mmc)
830{
831 return mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BOOT_WP, 1);
832}
833
62d77cea 834#if !CONFIG_IS_ENABLED(MMC_TINY)
b9a2a0e2
MV		 835static int mmc_set_card_speed(struct mmc *mmc, enum bus_mode mode,
836 bool hsdowngrade)
272cc70b 837{
272cc70b 838 int err;
3862b854
JJH		 839 int speed_bits;
840
841 ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
842
843 switch (mode) {
844 case MMC_HS:
845 case MMC_HS_52:
846 case MMC_DDR_52:
847 speed_bits = EXT_CSD_TIMING_HS;
634d4849 848 break;
baef2070 849#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
634d4849
KVA		 850 case MMC_HS_200:
851 speed_bits = EXT_CSD_TIMING_HS200;
852 break;
3dd2626f
PF		 853#endif
854#if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
855 case MMC_HS_400:
856 speed_bits = EXT_CSD_TIMING_HS400;
857 break;
44acd492
PF		 858#endif
859#if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
860 case MMC_HS_400_ES:
861 speed_bits = EXT_CSD_TIMING_HS400;
862 break;
baef2070 863#endif
3862b854
JJH		 864 case MMC_LEGACY:
865 speed_bits = EXT_CSD_TIMING_LEGACY;
866 break;
867 default:
868 return -EINVAL;
869 }
6892550c
MV		 870
871 err = __mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING,
872 speed_bits, !hsdowngrade);
3862b854
JJH		 873 if (err)
874 return err;
875
b9a2a0e2
MV		 876#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
877 CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
878 /*
879 * In case the eMMC is in HS200/HS400 mode and we are downgrading
880 * to HS mode, the card clock are still running much faster than
881 * the supported HS mode clock, so we can not reliably read out
882 * Extended CSD. Reconfigure the controller to run at HS mode.
883 */
884 if (hsdowngrade) {
885 mmc_select_mode(mmc, MMC_HS);
886 mmc_set_clock(mmc, mmc_mode2freq(mmc, MMC_HS), false);
887 }
888#endif
889
3862b854
JJH		 890 if ((mode == MMC_HS) || (mode == MMC_HS_52)) {
891 /* Now check to see that it worked */
892 err = mmc_send_ext_csd(mmc, test_csd);
893 if (err)
894 return err;
895
896 /* No high-speed support */
897 if (!test_csd[EXT_CSD_HS_TIMING])
898 return -ENOTSUPP;
899 }
900
901 return 0;
902}
903
904static int mmc_get_capabilities(struct mmc *mmc)
905{
906 u8 *ext_csd = mmc->ext_csd;
907 char cardtype;
272cc70b 908
00e446fa 909 mmc->card_caps = MMC_MODE_1BIT | MMC_CAP(MMC_LEGACY);
272cc70b 910
d52ebf10
TC		 911 if (mmc_host_is_spi(mmc))
912 return 0;
913
272cc70b
AF		 914 /* Only version 4 supports high-speed */
915 if (mmc->version < MMC_VERSION_4)
916 return 0;
917
3862b854 918 if (!ext_csd) {
d8e3d420 919 pr_err("No ext_csd found!\n"); /* this should enver happen */
3862b854
JJH		 920 return -ENOTSUPP;
921 }
272cc70b 922
3862b854 923 mmc->card_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT;
272cc70b 924
3dd2626f 925 cardtype = ext_csd[EXT_CSD_CARD_TYPE];
bc1e3272 926 mmc->cardtype = cardtype;
272cc70b 927
baef2070 928#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
634d4849
KVA		 929 if (cardtype & (EXT_CSD_CARD_TYPE_HS200_1_2V |
930 EXT_CSD_CARD_TYPE_HS200_1_8V)) {
931 mmc->card_caps |= MMC_MODE_HS200;
932 }
3dd2626f 933#endif
44acd492
PF		 934#if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT) || \
935 CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
3dd2626f
PF		 936 if (cardtype & (EXT_CSD_CARD_TYPE_HS400_1_2V |
937 EXT_CSD_CARD_TYPE_HS400_1_8V)) {
938 mmc->card_caps |= MMC_MODE_HS400;
939 }
baef2070 940#endif
d22e3d46 941 if (cardtype & EXT_CSD_CARD_TYPE_52) {
3862b854 942 if (cardtype & EXT_CSD_CARD_TYPE_DDR_52)
d22e3d46 943 mmc->card_caps |= MMC_MODE_DDR_52MHz;
3862b854 944 mmc->card_caps |= MMC_MODE_HS_52MHz;
d22e3d46 945 }
3862b854
JJH		 946 if (cardtype & EXT_CSD_CARD_TYPE_26)
947 mmc->card_caps |= MMC_MODE_HS;
272cc70b 948
44acd492
PF		 949#if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
950 if (ext_csd[EXT_CSD_STROBE_SUPPORT] &&
951 (mmc->card_caps & MMC_MODE_HS400)) {
952 mmc->card_caps |= MMC_MODE_HS400_ES;
953 }
954#endif
955
272cc70b
AF		 956 return 0;
957}
62d77cea 958#endif
272cc70b 959
f866a46d
SW		 960static int mmc_set_capacity(struct mmc *mmc, int part_num)
961{
962 switch (part_num) {
963 case 0:
964 mmc->capacity = mmc->capacity_user;
965 break;
966 case 1:
967 case 2:
968 mmc->capacity = mmc->capacity_boot;
969 break;
970 case 3:
971 mmc->capacity = mmc->capacity_rpmb;
972 break;
973 case 4:
974 case 5:
975 case 6:
976 case 7:
977 mmc->capacity = mmc->capacity_gp[part_num - 4];
978 break;
979 default:
980 return -1;
981 }
982
c40fdca6 983 mmc_get_blk_desc(mmc)->lba = lldiv(mmc->capacity, mmc->read_bl_len);
f866a46d
SW		 984
985 return 0;
986}
987
7dba0b93 988int mmc_switch_part(struct mmc *mmc, unsigned int part_num)
bc897b1d 989{
f866a46d 990 int ret;
0538477c 991 int retry = 3;
bc897b1d 992
0538477c
JJH		 993 do {
994 ret = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
995 EXT_CSD_PART_CONF,
996 (mmc->part_config & ~PART_ACCESS_MASK)
997 | (part_num & PART_ACCESS_MASK));
998 } while (ret && retry--);
f866a46d 999
6dc93e70
PB		 1000 /*
1001 * Set the capacity if the switch succeeded or was intended
1002 * to return to representing the raw device.
1003 */
873cc1d7 1004 if ((ret == 0) || ((ret == -ENODEV) && (part_num == 0))) {
6dc93e70 1005 ret = mmc_set_capacity(mmc, part_num);
fdbb139f 1006 mmc_get_blk_desc(mmc)->hwpart = part_num;
873cc1d7 1007 }
6dc93e70
PB		 1008
1009 return ret;
bc897b1d
LW		 1010}
1011
cf17789e 1012#if CONFIG_IS_ENABLED(MMC_HW_PARTITIONING)
ac9da0e0
DSC		 1013int mmc_hwpart_config(struct mmc *mmc,
1014 const struct mmc_hwpart_conf *conf,
1015 enum mmc_hwpart_conf_mode mode)
1016{
1017 u8 part_attrs = 0;
1018 u32 enh_size_mult;
1019 u32 enh_start_addr;
1020 u32 gp_size_mult[4];
1021 u32 max_enh_size_mult;
1022 u32 tot_enh_size_mult = 0;
8dda5b0e 1023 u8 wr_rel_set;
ac9da0e0
DSC		 1024 int i, pidx, err;
1025 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
1026
1027 if (mode < MMC_HWPART_CONF_CHECK || mode > MMC_HWPART_CONF_COMPLETE)
1028 return -EINVAL;
1029
1030 if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4_41)) {
d8e3d420 1031 pr_err("eMMC >= 4.4 required for enhanced user data area\n");
ac9da0e0
DSC		 1032 return -EMEDIUMTYPE;
1033 }
1034
1035 if (!(mmc->part_support & PART_SUPPORT)) {
d8e3d420 1036 pr_err("Card does not support partitioning\n");
ac9da0e0
DSC		 1037 return -EMEDIUMTYPE;
1038 }
1039
1040 if (!mmc->hc_wp_grp_size) {
d8e3d420 1041 pr_err("Card does not define HC WP group size\n");
ac9da0e0
DSC		 1042 return -EMEDIUMTYPE;
1043 }
1044
1045 /* check partition alignment and total enhanced size */
1046 if (conf->user.enh_size) {
1047 if (conf->user.enh_size % mmc->hc_wp_grp_size ||
1048 conf->user.enh_start % mmc->hc_wp_grp_size) {
d8e3d420 1049 pr_err("User data enhanced area not HC WP group "
ac9da0e0
DSC		 1050 "size aligned\n");
1051 return -EINVAL;
1052 }
1053 part_attrs |= EXT_CSD_ENH_USR;
1054 enh_size_mult = conf->user.enh_size / mmc->hc_wp_grp_size;
1055 if (mmc->high_capacity) {
1056 enh_start_addr = conf->user.enh_start;
1057 } else {
1058 enh_start_addr = (conf->user.enh_start << 9);
1059 }
1060 } else {
1061 enh_size_mult = 0;
1062 enh_start_addr = 0;
1063 }
1064 tot_enh_size_mult += enh_size_mult;
1065
1066 for (pidx = 0; pidx < 4; pidx++) {
1067 if (conf->gp_part[pidx].size % mmc->hc_wp_grp_size) {
d8e3d420 1068 pr_err("GP%i partition not HC WP group size "
ac9da0e0
DSC		 1069 "aligned\n", pidx+1);
1070 return -EINVAL;
1071 }
1072 gp_size_mult[pidx] = conf->gp_part[pidx].size / mmc->hc_wp_grp_size;
1073 if (conf->gp_part[pidx].size && conf->gp_part[pidx].enhanced) {
1074 part_attrs |= EXT_CSD_ENH_GP(pidx);
1075 tot_enh_size_mult += gp_size_mult[pidx];
1076 }
1077 }
1078
1079 if (part_attrs && ! (mmc->part_support & ENHNCD_SUPPORT)) {
d8e3d420 1080 pr_err("Card does not support enhanced attribute\n");
ac9da0e0
DSC		 1081 return -EMEDIUMTYPE;
1082 }
1083
1084 err = mmc_send_ext_csd(mmc, ext_csd);
1085 if (err)
1086 return err;
1087
1088 max_enh_size_mult =
1089 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+2] << 16) +
1090 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+1] << 8) +
1091 ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT];
1092 if (tot_enh_size_mult > max_enh_size_mult) {
d8e3d420 1093 pr_err("Total enhanced size exceeds maximum (%u > %u)\n",
ac9da0e0
DSC		 1094 tot_enh_size_mult, max_enh_size_mult);
1095 return -EMEDIUMTYPE;
1096 }
1097
8dda5b0e
DSC		 1098 /* The default value of EXT_CSD_WR_REL_SET is device
1099 * dependent, the values can only be changed if the
1100 * EXT_CSD_HS_CTRL_REL bit is set. The values can be
1101 * changed only once and before partitioning is completed. */
1102 wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
1103 if (conf->user.wr_rel_change) {
1104 if (conf->user.wr_rel_set)
1105 wr_rel_set |= EXT_CSD_WR_DATA_REL_USR;
1106 else
1107 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_USR;
1108 }
1109 for (pidx = 0; pidx < 4; pidx++) {
1110 if (conf->gp_part[pidx].wr_rel_change) {
1111 if (conf->gp_part[pidx].wr_rel_set)
1112 wr_rel_set |= EXT_CSD_WR_DATA_REL_GP(pidx);
1113 else
1114 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_GP(pidx);
1115 }
1116 }
1117
1118 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET] &&
1119 !(ext_csd[EXT_CSD_WR_REL_PARAM] & EXT_CSD_HS_CTRL_REL)) {
1120 puts("Card does not support host controlled partition write "
1121 "reliability settings\n");
1122 return -EMEDIUMTYPE;
1123 }
1124
ac9da0e0
DSC		 1125 if (ext_csd[EXT_CSD_PARTITION_SETTING] &
1126 EXT_CSD_PARTITION_SETTING_COMPLETED) {
d8e3d420 1127 pr_err("Card already partitioned\n");
ac9da0e0
DSC		 1128 return -EPERM;
1129 }
1130
1131 if (mode == MMC_HWPART_CONF_CHECK)
1132 return 0;
1133
1134 /* Partitioning requires high-capacity size definitions */
1135 if (!(ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01)) {
1136 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1137 EXT_CSD_ERASE_GROUP_DEF, 1);
1138
1139 if (err)
1140 return err;
1141
1142 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
1143
4af66596 1144#if CONFIG_IS_ENABLED(MMC_WRITE)
ac9da0e0
DSC		 1145 /* update erase group size to be high-capacity */
1146 mmc->erase_grp_size =
1147 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
4af66596 1148#endif
ac9da0e0
DSC		 1149
1150 }
1151
1152 /* all OK, write the configuration */
1153 for (i = 0; i < 4; i++) {
1154 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1155 EXT_CSD_ENH_START_ADDR+i,
1156 (enh_start_addr >> (i*8)) & 0xFF);
1157 if (err)
1158 return err;
1159 }
1160 for (i = 0; i < 3; i++) {
1161 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1162 EXT_CSD_ENH_SIZE_MULT+i,
1163 (enh_size_mult >> (i*8)) & 0xFF);
1164 if (err)
1165 return err;
1166 }
1167 for (pidx = 0; pidx < 4; pidx++) {
1168 for (i = 0; i < 3; i++) {
1169 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1170 EXT_CSD_GP_SIZE_MULT+pidx*3+i,
1171 (gp_size_mult[pidx] >> (i*8)) & 0xFF);
1172 if (err)
1173 return err;
1174 }
1175 }
1176 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1177 EXT_CSD_PARTITIONS_ATTRIBUTE, part_attrs);
1178 if (err)
1179 return err;
1180
1181 if (mode == MMC_HWPART_CONF_SET)
1182 return 0;
1183
8dda5b0e
DSC		 1184 /* The WR_REL_SET is a write-once register but shall be
1185 * written before setting PART_SETTING_COMPLETED. As it is
1186 * write-once we can only write it when completing the
1187 * partitioning. */
1188 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET]) {
1189 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1190 EXT_CSD_WR_REL_SET, wr_rel_set);
1191 if (err)
1192 return err;
1193 }
1194
ac9da0e0
DSC		 1195 /* Setting PART_SETTING_COMPLETED confirms the partition
1196 * configuration but it only becomes effective after power
1197 * cycle, so we do not adjust the partition related settings
1198 * in the mmc struct. */
1199
1200 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1201 EXT_CSD_PARTITION_SETTING,
1202 EXT_CSD_PARTITION_SETTING_COMPLETED);
1203 if (err)
1204 return err;
1205
1206 return 0;
1207}
cf17789e 1208#endif
ac9da0e0 1209
e7881d85 1210#if !CONFIG_IS_ENABLED(DM_MMC)
48972d90
TR		 1211int mmc_getcd(struct mmc *mmc)
1212{
1213 int cd;
1214
1215 cd = board_mmc_getcd(mmc);
1216
d4e1da4e 1217 if (cd < 0) {
93bfd616
PA		 1218 if (mmc->cfg->ops->getcd)
1219 cd = mmc->cfg->ops->getcd(mmc);
d4e1da4e
PK		 1220 else
1221 cd = 1;
1222 }
48972d90
TR		 1223
1224 return cd;
1225}
8ca51e51 1226#endif
48972d90 1227
62d77cea 1228#if !CONFIG_IS_ENABLED(MMC_TINY)
fdbb873e 1229static int sd_switch(struct mmc *mmc, int mode, int group, u8 value, u8 *resp)
272cc70b
AF		 1230{
1231 struct mmc_cmd cmd;
1232 struct mmc_data data;
1233
1234 /* Switch the frequency */
1235 cmd.cmdidx = SD_CMD_SWITCH_FUNC;
1236 cmd.resp_type = MMC_RSP_R1;
1237 cmd.cmdarg = (mode << 31) | 0xffffff;
1238 cmd.cmdarg &= ~(0xf << (group * 4));
1239 cmd.cmdarg |= value << (group * 4);
272cc70b
AF		 1240
1241 data.dest = (char *)resp;
1242 data.blocksize = 64;
1243 data.blocks = 1;
1244 data.flags = MMC_DATA_READ;
1245
1246 return mmc_send_cmd(mmc, &cmd, &data);
1247}
1248
d0c221fe 1249static int sd_get_capabilities(struct mmc *mmc)
272cc70b
AF		 1250{
1251 int err;
1252 struct mmc_cmd cmd;
18e7c8f6
SM		 1253 ALLOC_CACHE_ALIGN_BUFFER(__be32, scr, 2);
1254 ALLOC_CACHE_ALIGN_BUFFER(__be32, switch_status, 16);
272cc70b
AF		 1255 struct mmc_data data;
1256 int timeout;
f99c2efe 1257#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
c10b85d6 1258 u32 sd3_bus_mode;
f99c2efe 1259#endif
272cc70b 1260
e8d5dde4 1261 mmc->card_caps = MMC_MODE_1BIT | MMC_CAP(MMC_LEGACY);
272cc70b 1262
d52ebf10
TC		 1263 if (mmc_host_is_spi(mmc))
1264 return 0;
1265
272cc70b
AF		 1266 /* Read the SCR to find out if this card supports higher speeds */
1267 cmd.cmdidx = MMC_CMD_APP_CMD;
1268 cmd.resp_type = MMC_RSP_R1;
1269 cmd.cmdarg = mmc->rca << 16;
272cc70b
AF		 1270
1271 err = mmc_send_cmd(mmc, &cmd, NULL);
1272
1273 if (err)
1274 return err;
1275
1276 cmd.cmdidx = SD_CMD_APP_SEND_SCR;
1277 cmd.resp_type = MMC_RSP_R1;
1278 cmd.cmdarg = 0;
272cc70b
AF		 1279
1280 timeout = 3;
1281
1282retry_scr:
f781dd38 1283 data.dest = (char *)scr;
272cc70b
AF		 1284 data.blocksize = 8;
1285 data.blocks = 1;
1286 data.flags = MMC_DATA_READ;
1287
1288 err = mmc_send_cmd(mmc, &cmd, &data);
1289
1290 if (err) {
1291 if (timeout--)
1292 goto retry_scr;
1293
1294 return err;
1295 }
1296
4e3d89ba
YK		 1297 mmc->scr[0] = __be32_to_cpu(scr[0]);
1298 mmc->scr[1] = __be32_to_cpu(scr[1]);
272cc70b
AF		 1299
1300 switch ((mmc->scr[0] >> 24) & 0xf) {
53e8e40b
BM		 1301 case 0:
1302 mmc->version = SD_VERSION_1_0;
1303 break;
1304 case 1:
1305 mmc->version = SD_VERSION_1_10;
1306 break;
1307 case 2:
1308 mmc->version = SD_VERSION_2;
1309 if ((mmc->scr[0] >> 15) & 0x1)
1310 mmc->version = SD_VERSION_3;
1311 break;
1312 default:
1313 mmc->version = SD_VERSION_1_0;
1314 break;
272cc70b
AF		 1315 }
1316
b44c7083
AS		 1317 if (mmc->scr[0] & SD_DATA_4BIT)
1318 mmc->card_caps |= MMC_MODE_4BIT;
1319
272cc70b
AF		 1320 /* Version 1.0 doesn't support switching */
1321 if (mmc->version == SD_VERSION_1_0)
1322 return 0;
1323
1324 timeout = 4;
1325 while (timeout--) {
1326 err = sd_switch(mmc, SD_SWITCH_CHECK, 0, 1,
f781dd38 1327 (u8 *)switch_status);
272cc70b
AF		 1328
1329 if (err)
1330 return err;
1331
1332 /* The high-speed function is busy. Try again */
4e3d89ba 1333 if (!(__be32_to_cpu(switch_status[7]) & SD_HIGHSPEED_BUSY))
272cc70b
AF		 1334 break;
1335 }
1336
272cc70b 1337 /* If high-speed isn't supported, we return */
d0c221fe
JJH		 1338 if (__be32_to_cpu(switch_status[3]) & SD_HIGHSPEED_SUPPORTED)
1339 mmc->card_caps |= MMC_CAP(SD_HS);
272cc70b 1340
f99c2efe 1341#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
c10b85d6
JJH		 1342 /* Version before 3.0 don't support UHS modes */
1343 if (mmc->version < SD_VERSION_3)
1344 return 0;
1345
1346 sd3_bus_mode = __be32_to_cpu(switch_status[3]) >> 16 & 0x1f;
1347 if (sd3_bus_mode & SD_MODE_UHS_SDR104)
1348 mmc->card_caps |= MMC_CAP(UHS_SDR104);
1349 if (sd3_bus_mode & SD_MODE_UHS_SDR50)
1350 mmc->card_caps |= MMC_CAP(UHS_SDR50);
1351 if (sd3_bus_mode & SD_MODE_UHS_SDR25)
1352 mmc->card_caps |= MMC_CAP(UHS_SDR25);
1353 if (sd3_bus_mode & SD_MODE_UHS_SDR12)
1354 mmc->card_caps |= MMC_CAP(UHS_SDR12);
1355 if (sd3_bus_mode & SD_MODE_UHS_DDR50)
1356 mmc->card_caps |= MMC_CAP(UHS_DDR50);
f99c2efe 1357#endif
c10b85d6 1358
d0c221fe
JJH		 1359 return 0;
1360}
1361
1362static int sd_set_card_speed(struct mmc *mmc, enum bus_mode mode)
1363{
1364 int err;
1365
1366 ALLOC_CACHE_ALIGN_BUFFER(uint, switch_status, 16);
c10b85d6 1367 int speed;
2c3fbf4c 1368
cf345760
MV		 1369 /* SD version 1.00 and 1.01 does not support CMD 6 */
1370 if (mmc->version == SD_VERSION_1_0)
1371 return 0;
1372
c10b85d6 1373 switch (mode) {
e8d5dde4 1374 case MMC_LEGACY:
c10b85d6
JJH		 1375 speed = UHS_SDR12_BUS_SPEED;
1376 break;
1377 case SD_HS:
baef2070
JJH		 1378 speed = HIGH_SPEED_BUS_SPEED;
1379 break;
1380#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
1381 case UHS_SDR12:
1382 speed = UHS_SDR12_BUS_SPEED;
1383 break;
c10b85d6
JJH		 1384 case UHS_SDR25:
1385 speed = UHS_SDR25_BUS_SPEED;
1386 break;
1387 case UHS_SDR50:
1388 speed = UHS_SDR50_BUS_SPEED;
1389 break;
1390 case UHS_DDR50:
1391 speed = UHS_DDR50_BUS_SPEED;
1392 break;
1393 case UHS_SDR104:
1394 speed = UHS_SDR104_BUS_SPEED;
1395 break;
baef2070 1396#endif
c10b85d6
JJH		 1397 default:
1398 return -EINVAL;
1399 }
1400
1401 err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, speed, (u8 *)switch_status);
d0c221fe
JJH		 1402 if (err)
1403 return err;
1404
a0276f3e 1405 if (((__be32_to_cpu(switch_status[4]) >> 24) & 0xF) != speed)
d0c221fe 1406 return -ENOTSUPP;
272cc70b 1407
d0c221fe
JJH		 1408 return 0;
1409}
1410
ec360e64 1411static int sd_select_bus_width(struct mmc *mmc, int w)
d0c221fe
JJH		 1412{
1413 int err;
1414 struct mmc_cmd cmd;
1415
1416 if ((w != 4) && (w != 1))
1417 return -EINVAL;
1418
1419 cmd.cmdidx = MMC_CMD_APP_CMD;
1420 cmd.resp_type = MMC_RSP_R1;
1421 cmd.cmdarg = mmc->rca << 16;
1422
1423 err = mmc_send_cmd(mmc, &cmd, NULL);
272cc70b
AF		 1424 if (err)
1425 return err;
1426
d0c221fe
JJH		 1427 cmd.cmdidx = SD_CMD_APP_SET_BUS_WIDTH;
1428 cmd.resp_type = MMC_RSP_R1;
1429 if (w == 4)
1430 cmd.cmdarg = 2;
1431 else if (w == 1)
1432 cmd.cmdarg = 0;
1433 err = mmc_send_cmd(mmc, &cmd, NULL);
1434 if (err)
1435 return err;
272cc70b
AF		 1436
1437 return 0;
1438}
62d77cea 1439#endif
272cc70b 1440
5b2e72f3 1441#if CONFIG_IS_ENABLED(MMC_WRITE)
3697e599
PF		 1442static int sd_read_ssr(struct mmc *mmc)
1443{
5b2e72f3
JJH		 1444 static const unsigned int sd_au_size[] = {
1445 0, SZ_16K / 512, SZ_32K / 512,
1446 SZ_64K / 512, SZ_128K / 512, SZ_256K / 512,
1447 SZ_512K / 512, SZ_1M / 512, SZ_2M / 512,
1448 SZ_4M / 512, SZ_8M / 512, (SZ_8M + SZ_4M) / 512,
1449 SZ_16M / 512, (SZ_16M + SZ_8M) / 512, SZ_32M / 512,
1450 SZ_64M / 512,
1451 };
3697e599
PF		 1452 int err, i;
1453 struct mmc_cmd cmd;
1454 ALLOC_CACHE_ALIGN_BUFFER(uint, ssr, 16);
1455 struct mmc_data data;
1456 int timeout = 3;
1457 unsigned int au, eo, et, es;
1458
1459 cmd.cmdidx = MMC_CMD_APP_CMD;
1460 cmd.resp_type = MMC_RSP_R1;
1461 cmd.cmdarg = mmc->rca << 16;
1462
1463 err = mmc_send_cmd(mmc, &cmd, NULL);
d4a5fa31
JJ		 1464#ifdef CONFIG_MMC_QUIRKS
1465 if (err && (mmc->quirks & MMC_QUIRK_RETRY_APP_CMD)) {
1466 int retries = 4;
1467 /*
1468 * It has been seen that APP_CMD may fail on the first
1469 * attempt, let's try a few more times
1470 */
1471 do {
1472 err = mmc_send_cmd(mmc, &cmd, NULL);
1473 if (!err)
1474 break;
1475 } while (retries--);
1476 }
1477#endif
3697e599
PF		 1478 if (err)
1479 return err;
1480
1481 cmd.cmdidx = SD_CMD_APP_SD_STATUS;
1482 cmd.resp_type = MMC_RSP_R1;
1483 cmd.cmdarg = 0;
1484
1485retry_ssr:
1486 data.dest = (char *)ssr;
1487 data.blocksize = 64;
1488 data.blocks = 1;
1489 data.flags = MMC_DATA_READ;
1490
1491 err = mmc_send_cmd(mmc, &cmd, &data);
1492 if (err) {
1493 if (timeout--)
1494 goto retry_ssr;
1495
1496 return err;
1497 }
1498
1499 for (i = 0; i < 16; i++)
1500 ssr[i] = be32_to_cpu(ssr[i]);
1501
1502 au = (ssr[2] >> 12) & 0xF;
1503 if ((au <= 9) || (mmc->version == SD_VERSION_3)) {
1504 mmc->ssr.au = sd_au_size[au];
1505 es = (ssr[3] >> 24) & 0xFF;
1506 es |= (ssr[2] & 0xFF) << 8;
1507 et = (ssr[3] >> 18) & 0x3F;
1508 if (es && et) {
1509 eo = (ssr[3] >> 16) & 0x3;
1510 mmc->ssr.erase_timeout = (et * 1000) / es;
1511 mmc->ssr.erase_offset = eo * 1000;
1512 }
1513 } else {
d4d64889 1514 pr_debug("Invalid Allocation Unit Size.\n");
3697e599
PF		 1515 }
1516
1517 return 0;
1518}
5b2e72f3 1519#endif
272cc70b
AF		 1520/* frequency bases */
1521/* divided by 10 to be nice to platforms without floating point */
5f837c2c 1522static const int fbase[] = {
272cc70b
AF		 1523 10000,
1524 100000,
1525 1000000,
1526 10000000,
1527};
1528
1529/* Multiplier values for TRAN_SPEED. Multiplied by 10 to be nice
1530 * to platforms without floating point.
1531 */
61fe076f 1532static const u8 multipliers[] = {
272cc70b
AF		 1533 0, /* reserved */
1534 10,
1535 12,
1536 13,
1537 15,
1538 20,
1539 25,
1540 30,
1541 35,
1542 40,
1543 45,
1544 50,
1545 55,
1546 60,
1547 70,
1548 80,
1549};
1550
d0c221fe
JJH		 1551static inline int bus_width(uint cap)
1552{
1553 if (cap == MMC_MODE_8BIT)
1554 return 8;
1555 if (cap == MMC_MODE_4BIT)
1556 return 4;
1557 if (cap == MMC_MODE_1BIT)
1558 return 1;
d8e3d420 1559 pr_warn("invalid bus witdh capability 0x%x\n", cap);
d0c221fe
JJH		 1560 return 0;
1561}
1562
e7881d85 1563#if !CONFIG_IS_ENABLED(DM_MMC)
f99c2efe 1564#ifdef MMC_SUPPORTS_TUNING
ec841209
KVA		 1565static int mmc_execute_tuning(struct mmc *mmc, uint opcode)
1566{
1567 return -ENOTSUPP;
1568}
f99c2efe 1569#endif
ec841209 1570
2a4d212f 1571static int mmc_set_ios(struct mmc *mmc)
272cc70b 1572{
2a4d212f
KVA		 1573 int ret = 0;
1574
93bfd616 1575 if (mmc->cfg->ops->set_ios)
2a4d212f
KVA		 1576 ret = mmc->cfg->ops->set_ios(mmc);
1577
1578 return ret;
272cc70b 1579}
3602a56a
YG		 1580
1581static int mmc_host_power_cycle(struct mmc *mmc)
1582{
1583 int ret = 0;
1584
1585 if (mmc->cfg->ops->host_power_cycle)
1586 ret = mmc->cfg->ops->host_power_cycle(mmc);
1587
1588 return ret;
1589}
8ca51e51 1590#endif
272cc70b 1591
35f67820 1592int mmc_set_clock(struct mmc *mmc, uint clock, bool disable)
272cc70b 1593{
c0fafe64 1594 if (!disable) {
9546eb92
JC		 1595 if (clock > mmc->cfg->f_max)
1596 clock = mmc->cfg->f_max;
272cc70b 1597
9546eb92
JC		 1598 if (clock < mmc->cfg->f_min)
1599 clock = mmc->cfg->f_min;
1600 }
272cc70b
AF		 1601
1602 mmc->clock = clock;
35f67820 1603 mmc->clk_disable = disable;
272cc70b 1604
d2faadb5
JC		 1605 debug("clock is %s (%dHz)\n", disable ? "disabled" : "enabled", clock);
1606
2a4d212f 1607 return mmc_set_ios(mmc);
272cc70b
AF		 1608}
1609
2a4d212f 1610static int mmc_set_bus_width(struct mmc *mmc, uint width)
272cc70b
AF		 1611{
1612 mmc->bus_width = width;
1613
2a4d212f 1614 return mmc_set_ios(mmc);
272cc70b
AF		 1615}
1616
4c9d2aaa
JJH		 1617#if CONFIG_IS_ENABLED(MMC_VERBOSE) || defined(DEBUG)
1618/*
1619 * helper function to display the capabilities in a human
1620 * friendly manner. The capabilities include bus width and
1621 * supported modes.
1622 */
1623void mmc_dump_capabilities(const char *text, uint caps)
1624{
1625 enum bus_mode mode;
1626
d4d64889 1627 pr_debug("%s: widths [", text);
4c9d2aaa 1628 if (caps & MMC_MODE_8BIT)
d4d64889 1629 pr_debug("8, ");
4c9d2aaa 1630 if (caps & MMC_MODE_4BIT)
d4d64889 1631 pr_debug("4, ");
d0c221fe 1632 if (caps & MMC_MODE_1BIT)
d4d64889
MY		 1633 pr_debug("1, ");
1634 pr_debug("\b\b] modes [");
4c9d2aaa
JJH		 1635 for (mode = MMC_LEGACY; mode < MMC_MODES_END; mode++)
1636 if (MMC_CAP(mode) & caps)
d4d64889
MY		 1637 pr_debug("%s, ", mmc_mode_name(mode));
1638 pr_debug("\b\b]\n");
4c9d2aaa
JJH		 1639}
1640#endif
1641
d0c221fe
JJH		 1642struct mode_width_tuning {
1643 enum bus_mode mode;
1644 uint widths;
f99c2efe 1645#ifdef MMC_SUPPORTS_TUNING
634d4849 1646 uint tuning;
f99c2efe 1647#endif
d0c221fe
JJH		 1648};
1649
f99c2efe 1650#if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE)
bc1e3272
JJH		 1651int mmc_voltage_to_mv(enum mmc_voltage voltage)
1652{
1653 switch (voltage) {
1654 case MMC_SIGNAL_VOLTAGE_000: return 0;
1655 case MMC_SIGNAL_VOLTAGE_330: return 3300;
1656 case MMC_SIGNAL_VOLTAGE_180: return 1800;
1657 case MMC_SIGNAL_VOLTAGE_120: return 1200;
1658 }
1659 return -EINVAL;
1660}
1661
aff5d3c8
KVA		 1662static int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage)
1663{
bc1e3272
JJH		 1664 int err;
1665
1666 if (mmc->signal_voltage == signal_voltage)
1667 return 0;
1668
aff5d3c8 1669 mmc->signal_voltage = signal_voltage;
bc1e3272
JJH		 1670 err = mmc_set_ios(mmc);
1671 if (err)
d4d64889 1672 pr_debug("unable to set voltage (err %d)\n", err);
bc1e3272
JJH		 1673
1674 return err;
aff5d3c8 1675}
f99c2efe
JJH		 1676#else
1677static inline int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage)
1678{
1679 return 0;
1680}
1681#endif
aff5d3c8 1682
62d77cea 1683#if !CONFIG_IS_ENABLED(MMC_TINY)
d0c221fe 1684static const struct mode_width_tuning sd_modes_by_pref[] = {
f99c2efe
JJH		 1685#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
1686#ifdef MMC_SUPPORTS_TUNING
c10b85d6
JJH		 1687 {
1688 .mode = UHS_SDR104,
1689 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1690 .tuning = MMC_CMD_SEND_TUNING_BLOCK
1691 },
f99c2efe 1692#endif
c10b85d6
JJH		 1693 {
1694 .mode = UHS_SDR50,
1695 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1696 },
1697 {
1698 .mode = UHS_DDR50,
1699 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1700 },
1701 {
1702 .mode = UHS_SDR25,
1703 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1704 },
f99c2efe 1705#endif
d0c221fe
JJH		 1706 {
1707 .mode = SD_HS,
1708 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1709 },
f99c2efe 1710#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
c10b85d6
JJH		 1711 {
1712 .mode = UHS_SDR12,
1713 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1714 },
f99c2efe 1715#endif
d0c221fe 1716 {
e8d5dde4 1717 .mode = MMC_LEGACY,
d0c221fe
JJH		 1718 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1719 }
1720};
1721
1722#define for_each_sd_mode_by_pref(caps, mwt) \
1723 for (mwt = sd_modes_by_pref;\
1724 mwt < sd_modes_by_pref + ARRAY_SIZE(sd_modes_by_pref);\
1725 mwt++) \
1726 if (caps & MMC_CAP(mwt->mode))
1727
01298da3 1728static int sd_select_mode_and_width(struct mmc *mmc, uint card_caps)
8ac8a263
JJH		 1729{
1730 int err;
d0c221fe
JJH		 1731 uint widths[] = {MMC_MODE_4BIT, MMC_MODE_1BIT};
1732 const struct mode_width_tuning *mwt;
f99c2efe 1733#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
c10b85d6 1734 bool uhs_en = (mmc->ocr & OCR_S18R) ? true : false;
f99c2efe
JJH		 1735#else
1736 bool uhs_en = false;
1737#endif
c10b85d6
JJH		 1738 uint caps;
1739
52d241df
JJH		 1740#ifdef DEBUG
1741 mmc_dump_capabilities("sd card", card_caps);
1da8eb59 1742 mmc_dump_capabilities("host", mmc->host_caps);
52d241df 1743#endif
8ac8a263 1744
f49ff799
AP		 1745 if (mmc_host_is_spi(mmc)) {
1746 mmc_set_bus_width(mmc, 1);
e8d5dde4 1747 mmc_select_mode(mmc, MMC_LEGACY);
f49ff799
AP		 1748 mmc_set_clock(mmc, mmc->tran_speed, MMC_CLK_ENABLE);
1749 return 0;
1750 }
1751
8ac8a263 1752 /* Restrict card's capabilities by what the host can do */
1da8eb59 1753 caps = card_caps & mmc->host_caps;
d0c221fe 1754
c10b85d6
JJH		 1755 if (!uhs_en)
1756 caps &= ~UHS_CAPS;
1757
1758 for_each_sd_mode_by_pref(caps, mwt) {
d0c221fe
JJH		 1759 uint *w;
1760
1761 for (w = widths; w < widths + ARRAY_SIZE(widths); w++) {
c10b85d6 1762 if (*w & caps & mwt->widths) {
d4d64889
MY		 1763 pr_debug("trying mode %s width %d (at %d MHz)\n",
1764 mmc_mode_name(mwt->mode),
1765 bus_width(*w),
1766 mmc_mode2freq(mmc, mwt->mode) / 1000000);
d0c221fe
JJH		 1767
1768 /* configure the bus width (card + host) */
1769 err = sd_select_bus_width(mmc, bus_width(*w));
1770 if (err)
1771 goto error;
1772 mmc_set_bus_width(mmc, bus_width(*w));
1773
1774 /* configure the bus mode (card) */
1775 err = sd_set_card_speed(mmc, mwt->mode);
1776 if (err)
1777 goto error;
1778
1779 /* configure the bus mode (host) */
1780 mmc_select_mode(mmc, mwt->mode);
65117182
JC		 1781 mmc_set_clock(mmc, mmc->tran_speed,
1782 MMC_CLK_ENABLE);
d0c221fe 1783
f99c2efe 1784#ifdef MMC_SUPPORTS_TUNING
c10b85d6
JJH		 1785 /* execute tuning if needed */
1786 if (mwt->tuning && !mmc_host_is_spi(mmc)) {
1787 err = mmc_execute_tuning(mmc,
1788 mwt->tuning);
1789 if (err) {
d4d64889 1790 pr_debug("tuning failed\n");
c10b85d6
JJH		 1791 goto error;
1792 }
1793 }
f99c2efe 1794#endif
c10b85d6 1795
5b2e72f3 1796#if CONFIG_IS_ENABLED(MMC_WRITE)
d0c221fe 1797 err = sd_read_ssr(mmc);
0a4c2b09 1798 if (err)
5b2e72f3
JJH		 1799 pr_warn("unable to read ssr\n");
1800#endif
d0c221fe
JJH		 1801 if (!err)
1802 return 0;
1803
d0c221fe
JJH		 1804error:
1805 /* revert to a safer bus speed */
e8d5dde4 1806 mmc_select_mode(mmc, MMC_LEGACY);
65117182
JC		 1807 mmc_set_clock(mmc, mmc->tran_speed,
1808 MMC_CLK_ENABLE);
d0c221fe
JJH		 1809 }
1810 }
8ac8a263
JJH		 1811 }
1812
d4d64889 1813 pr_err("unable to select a mode\n");
d0c221fe 1814 return -ENOTSUPP;
8ac8a263
JJH		 1815}
1816
7382e691
JJH		 1817/*
1818 * read the compare the part of ext csd that is constant.
1819 * This can be used to check that the transfer is working
1820 * as expected.
1821 */
1822static int mmc_read_and_compare_ext_csd(struct mmc *mmc)
8ac8a263 1823{
7382e691 1824 int err;
dfda9d88 1825 const u8 *ext_csd = mmc->ext_csd;
7382e691
JJH		 1826 ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
1827
1de06b9f
JJH		 1828 if (mmc->version < MMC_VERSION_4)
1829 return 0;
1830
7382e691
JJH		 1831 err = mmc_send_ext_csd(mmc, test_csd);
1832 if (err)
1833 return err;
1834
1835 /* Only compare read only fields */
1836 if (ext_csd[EXT_CSD_PARTITIONING_SUPPORT]
1837 == test_csd[EXT_CSD_PARTITIONING_SUPPORT] &&
1838 ext_csd[EXT_CSD_HC_WP_GRP_SIZE]
1839 == test_csd[EXT_CSD_HC_WP_GRP_SIZE] &&
1840 ext_csd[EXT_CSD_REV]
1841 == test_csd[EXT_CSD_REV] &&
1842 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
1843 == test_csd[EXT_CSD_HC_ERASE_GRP_SIZE] &&
1844 memcmp(&ext_csd[EXT_CSD_SEC_CNT],
1845 &test_csd[EXT_CSD_SEC_CNT], 4) == 0)
1846 return 0;
1847
1848 return -EBADMSG;
1849}
1850
f99c2efe 1851#if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE)
bc1e3272
JJH		 1852static int mmc_set_lowest_voltage(struct mmc *mmc, enum bus_mode mode,
1853 uint32_t allowed_mask)
1854{
1855 u32 card_mask = 0;
1856
1857 switch (mode) {
44acd492 1858 case MMC_HS_400_ES:
3dd2626f 1859 case MMC_HS_400:
bc1e3272 1860 case MMC_HS_200:
3dd2626f
PF		 1861 if (mmc->cardtype & (EXT_CSD_CARD_TYPE_HS200_1_8V |
1862 EXT_CSD_CARD_TYPE_HS400_1_8V))
bc1e3272 1863 card_mask |= MMC_SIGNAL_VOLTAGE_180;
3dd2626f
PF		 1864 if (mmc->cardtype & (EXT_CSD_CARD_TYPE_HS200_1_2V |
1865 EXT_CSD_CARD_TYPE_HS400_1_2V))
bc1e3272
JJH		 1866 card_mask |= MMC_SIGNAL_VOLTAGE_120;
1867 break;
1868 case MMC_DDR_52:
1869 if (mmc->cardtype & EXT_CSD_CARD_TYPE_DDR_1_8V)
1870 card_mask |= MMC_SIGNAL_VOLTAGE_330 |
1871 MMC_SIGNAL_VOLTAGE_180;
1872 if (mmc->cardtype & EXT_CSD_CARD_TYPE_DDR_1_2V)
1873 card_mask |= MMC_SIGNAL_VOLTAGE_120;
1874 break;
1875 default:
1876 card_mask |= MMC_SIGNAL_VOLTAGE_330;
1877 break;
1878 }
1879
1880 while (card_mask & allowed_mask) {
1881 enum mmc_voltage best_match;
1882
1883 best_match = 1 << (ffs(card_mask & allowed_mask) - 1);
1884 if (!mmc_set_signal_voltage(mmc, best_match))
1885 return 0;
1886
1887 allowed_mask &= ~best_match;
1888 }
1889
1890 return -ENOTSUPP;
1891}
f99c2efe
JJH		 1892#else
1893static inline int mmc_set_lowest_voltage(struct mmc *mmc, enum bus_mode mode,
1894 uint32_t allowed_mask)
1895{
1896 return 0;
1897}
1898#endif
bc1e3272 1899
3862b854 1900static const struct mode_width_tuning mmc_modes_by_pref[] = {
44acd492
PF		 1901#if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
1902 {
1903 .mode = MMC_HS_400_ES,
1904 .widths = MMC_MODE_8BIT,
1905 },
1906#endif
3dd2626f
PF		 1907#if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
1908 {
1909 .mode = MMC_HS_400,
1910 .widths = MMC_MODE_8BIT,
1911 .tuning = MMC_CMD_SEND_TUNING_BLOCK_HS200
1912 },
1913#endif
f99c2efe 1914#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
3862b854
JJH		 1915 {
1916 .mode = MMC_HS_200,
1917 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT,
634d4849 1918 .tuning = MMC_CMD_SEND_TUNING_BLOCK_HS200
3862b854 1919 },
f99c2efe 1920#endif
3862b854
JJH		 1921 {
1922 .mode = MMC_DDR_52,
1923 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT,
1924 },
1925 {
1926 .mode = MMC_HS_52,
1927 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,
1928 },
1929 {
1930 .mode = MMC_HS,
1931 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,
1932 },
1933 {
1934 .mode = MMC_LEGACY,
1935 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,
1936 }
1937};
1938
1939#define for_each_mmc_mode_by_pref(caps, mwt) \
1940 for (mwt = mmc_modes_by_pref;\
1941 mwt < mmc_modes_by_pref + ARRAY_SIZE(mmc_modes_by_pref);\
1942 mwt++) \
1943 if (caps & MMC_CAP(mwt->mode))
1944
1945static const struct ext_csd_bus_width {
1946 uint cap;
1947 bool is_ddr;
1948 uint ext_csd_bits;
1949} ext_csd_bus_width[] = {
1950 {MMC_MODE_8BIT, true, EXT_CSD_DDR_BUS_WIDTH_8},
1951 {MMC_MODE_4BIT, true, EXT_CSD_DDR_BUS_WIDTH_4},
1952 {MMC_MODE_8BIT, false, EXT_CSD_BUS_WIDTH_8},
1953 {MMC_MODE_4BIT, false, EXT_CSD_BUS_WIDTH_4},
1954 {MMC_MODE_1BIT, false, EXT_CSD_BUS_WIDTH_1},
1955};
1956
3dd2626f
PF		 1957#if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
1958static int mmc_select_hs400(struct mmc *mmc)
1959{
1960 int err;
1961
1962 /* Set timing to HS200 for tuning */
b9a2a0e2 1963 err = mmc_set_card_speed(mmc, MMC_HS_200, false);
3dd2626f
PF		 1964 if (err)
1965 return err;
1966
1967 /* configure the bus mode (host) */
1968 mmc_select_mode(mmc, MMC_HS_200);
1969 mmc_set_clock(mmc, mmc->tran_speed, false);
1970
1971 /* execute tuning if needed */
1972 err = mmc_execute_tuning(mmc, MMC_CMD_SEND_TUNING_BLOCK_HS200);
1973 if (err) {
1974 debug("tuning failed\n");
1975 return err;
1976 }
1977
1978 /* Set back to HS */
5cf12031 1979 mmc_set_card_speed(mmc, MMC_HS, true);
3dd2626f
PF		 1980
1981 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BUS_WIDTH,
1982 EXT_CSD_BUS_WIDTH_8 | EXT_CSD_DDR_FLAG);
1983 if (err)
1984 return err;
1985
b9a2a0e2 1986 err = mmc_set_card_speed(mmc, MMC_HS_400, false);
3dd2626f
PF		 1987 if (err)
1988 return err;
1989
1990 mmc_select_mode(mmc, MMC_HS_400);
1991 err = mmc_set_clock(mmc, mmc->tran_speed, false);
1992 if (err)
1993 return err;
1994
1995 return 0;
1996}
1997#else
1998static int mmc_select_hs400(struct mmc *mmc)
1999{
2000 return -ENOTSUPP;
2001}
2002#endif
2003
44acd492
PF		 2004#if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
2005#if !CONFIG_IS_ENABLED(DM_MMC)
2006static int mmc_set_enhanced_strobe(struct mmc *mmc)
2007{
2008 return -ENOTSUPP;
2009}
2010#endif
2011static int mmc_select_hs400es(struct mmc *mmc)
2012{
2013 int err;
2014
2015 err = mmc_set_card_speed(mmc, MMC_HS, true);
2016 if (err)
2017 return err;
2018
2019 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BUS_WIDTH,
2020 EXT_CSD_BUS_WIDTH_8 | EXT_CSD_DDR_FLAG |
2021 EXT_CSD_BUS_WIDTH_STROBE);
2022 if (err) {
2023 printf("switch to bus width for hs400 failed\n");
2024 return err;
2025 }
2026 /* TODO: driver strength */
2027 err = mmc_set_card_speed(mmc, MMC_HS_400_ES, false);
2028 if (err)
2029 return err;
2030
2031 mmc_select_mode(mmc, MMC_HS_400_ES);
2032 err = mmc_set_clock(mmc, mmc->tran_speed, false);
2033 if (err)
2034 return err;
2035
2036 return mmc_set_enhanced_strobe(mmc);
2037}
2038#else
2039static int mmc_select_hs400es(struct mmc *mmc)
2040{
2041 return -ENOTSUPP;
2042}
2043#endif
2044
3862b854
JJH		 2045#define for_each_supported_width(caps, ddr, ecbv) \
2046 for (ecbv = ext_csd_bus_width;\
2047 ecbv < ext_csd_bus_width + ARRAY_SIZE(ext_csd_bus_width);\
2048 ecbv++) \
2049 if ((ddr == ecbv->is_ddr) && (caps & ecbv->cap))
2050
01298da3 2051static int mmc_select_mode_and_width(struct mmc *mmc, uint card_caps)
7382e691 2052{
8ac8a263 2053 int err;
3862b854
JJH		 2054 const struct mode_width_tuning *mwt;
2055 const struct ext_csd_bus_width *ecbw;
8ac8a263 2056
52d241df
JJH		 2057#ifdef DEBUG
2058 mmc_dump_capabilities("mmc", card_caps);
1da8eb59 2059 mmc_dump_capabilities("host", mmc->host_caps);
52d241df
JJH		 2060#endif
2061
f49ff799
AP		 2062 if (mmc_host_is_spi(mmc)) {
2063 mmc_set_bus_width(mmc, 1);
2064 mmc_select_mode(mmc, MMC_LEGACY);
2065 mmc_set_clock(mmc, mmc->tran_speed, MMC_CLK_ENABLE);
2066 return 0;
2067 }
2068
8ac8a263 2069 /* Restrict card's capabilities by what the host can do */
1da8eb59 2070 card_caps &= mmc->host_caps;
8ac8a263
JJH		 2071
2072 /* Only version 4 of MMC supports wider bus widths */
2073 if (mmc->version < MMC_VERSION_4)
2074 return 0;
2075
dfda9d88 2076 if (!mmc->ext_csd) {
d4d64889 2077 pr_debug("No ext_csd found!\n"); /* this should enver happen */
dfda9d88
JJH		 2078 return -ENOTSUPP;
2079 }
2080
b9a2a0e2
MV		 2081#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
2082 CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
2083 /*
2084 * In case the eMMC is in HS200/HS400 mode, downgrade to HS mode
2085 * before doing anything else, since a transition from either of
2086 * the HS200/HS400 mode directly to legacy mode is not supported.
2087 */
2088 if (mmc->selected_mode == MMC_HS_200 ||
2089 mmc->selected_mode == MMC_HS_400)
2090 mmc_set_card_speed(mmc, MMC_HS, true);
2091 else
2092#endif
2093 mmc_set_clock(mmc, mmc->legacy_speed, MMC_CLK_ENABLE);
01298da3
JJH		 2094
2095 for_each_mmc_mode_by_pref(card_caps, mwt) {
2096 for_each_supported_width(card_caps & mwt->widths,
3862b854 2097 mmc_is_mode_ddr(mwt->mode), ecbw) {
bc1e3272 2098 enum mmc_voltage old_voltage;
d4d64889
MY		 2099 pr_debug("trying mode %s width %d (at %d MHz)\n",
2100 mmc_mode_name(mwt->mode),
2101 bus_width(ecbw->cap),
2102 mmc_mode2freq(mmc, mwt->mode) / 1000000);
bc1e3272
JJH		 2103 old_voltage = mmc->signal_voltage;
2104 err = mmc_set_lowest_voltage(mmc, mwt->mode,
2105 MMC_ALL_SIGNAL_VOLTAGE);
2106 if (err)
2107 continue;
2108
3862b854
JJH		 2109 /* configure the bus width (card + host) */
2110 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
2111 EXT_CSD_BUS_WIDTH,
2112 ecbw->ext_csd_bits & ~EXT_CSD_DDR_FLAG);
2113 if (err)
2114 goto error;
2115 mmc_set_bus_width(mmc, bus_width(ecbw->cap));
8ac8a263 2116
3dd2626f
PF		 2117 if (mwt->mode == MMC_HS_400) {
2118 err = mmc_select_hs400(mmc);
2119 if (err) {
2120 printf("Select HS400 failed %d\n", err);
2121 goto error;
2122 }
44acd492
PF		 2123 } else if (mwt->mode == MMC_HS_400_ES) {
2124 err = mmc_select_hs400es(mmc);
2125 if (err) {
2126 printf("Select HS400ES failed %d\n",
2127 err);
2128 goto error;
2129 }
3dd2626f
PF		 2130 } else {
2131 /* configure the bus speed (card) */
b9a2a0e2 2132 err = mmc_set_card_speed(mmc, mwt->mode, false);
3862b854
JJH		 2133 if (err)
2134 goto error;
8ac8a263 2135
3dd2626f
PF		 2136 /*
2137 * configure the bus width AND the ddr mode
2138 * (card). The host side will be taken care
2139 * of in the next step
2140 */
2141 if (ecbw->ext_csd_bits & EXT_CSD_DDR_FLAG) {
2142 err = mmc_switch(mmc,
2143 EXT_CSD_CMD_SET_NORMAL,
2144 EXT_CSD_BUS_WIDTH,
2145 ecbw->ext_csd_bits);
2146 if (err)
2147 goto error;
2148 }
2149
2150 /* configure the bus mode (host) */
2151 mmc_select_mode(mmc, mwt->mode);
2152 mmc_set_clock(mmc, mmc->tran_speed,
2153 MMC_CLK_ENABLE);
f99c2efe 2154#ifdef MMC_SUPPORTS_TUNING
8ac8a263 2155
3dd2626f
PF		 2156 /* execute tuning if needed */
2157 if (mwt->tuning) {
2158 err = mmc_execute_tuning(mmc,
2159 mwt->tuning);
2160 if (err) {
2161 pr_debug("tuning failed\n");
2162 goto error;
2163 }
634d4849 2164 }
f99c2efe 2165#endif
3dd2626f 2166 }
634d4849 2167
3862b854
JJH		 2168 /* do a transfer to check the configuration */
2169 err = mmc_read_and_compare_ext_csd(mmc);
2170 if (!err)
2171 return 0;
2172error:
bc1e3272 2173 mmc_set_signal_voltage(mmc, old_voltage);
3862b854
JJH		 2174 /* if an error occured, revert to a safer bus mode */
2175 mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
2176 EXT_CSD_BUS_WIDTH, EXT_CSD_BUS_WIDTH_1);
2177 mmc_select_mode(mmc, MMC_LEGACY);
2178 mmc_set_bus_width(mmc, 1);
2179 }
8ac8a263
JJH		 2180 }
2181
d8e3d420 2182 pr_err("unable to select a mode\n");
8ac8a263 2183
3862b854 2184 return -ENOTSUPP;
8ac8a263 2185}
62d77cea
MV		 2186#endif
2187
2188#if CONFIG_IS_ENABLED(MMC_TINY)
2189DEFINE_CACHE_ALIGN_BUFFER(u8, ext_csd_bkup, MMC_MAX_BLOCK_LEN);
2190#endif
8ac8a263 2191
dfda9d88 2192static int mmc_startup_v4(struct mmc *mmc)
c744b6f6
JJH		 2193{
2194 int err, i;
2195 u64 capacity;
2196 bool has_parts = false;
2197 bool part_completed;
58a6fb7b
JJH		 2198 static const u32 mmc_versions[] = {
2199 MMC_VERSION_4,
2200 MMC_VERSION_4_1,
2201 MMC_VERSION_4_2,
2202 MMC_VERSION_4_3,
ace1bed3 2203 MMC_VERSION_4_4,
58a6fb7b
JJH		 2204 MMC_VERSION_4_41,
2205 MMC_VERSION_4_5,
2206 MMC_VERSION_5_0,
2207 MMC_VERSION_5_1
2208 };
2209
62d77cea
MV		 2210#if CONFIG_IS_ENABLED(MMC_TINY)
2211 u8 *ext_csd = ext_csd_bkup;
2212
2213 if (IS_SD(mmc) || mmc->version < MMC_VERSION_4)
2214 return 0;
2215
2216 if (!mmc->ext_csd)
2217 memset(ext_csd_bkup, 0, sizeof(ext_csd_bkup));
2218
2219 err = mmc_send_ext_csd(mmc, ext_csd);
2220 if (err)
2221 goto error;
2222
2223 /* store the ext csd for future reference */
2224 if (!mmc->ext_csd)
2225 mmc->ext_csd = ext_csd;
2226#else
f7d5dffc 2227 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
c744b6f6
JJH		 2228
2229 if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4))
2230 return 0;
2231
2232 /* check ext_csd version and capacity */
2233 err = mmc_send_ext_csd(mmc, ext_csd);
2234 if (err)
f7d5dffc
JJH		 2235 goto error;
2236
2237 /* store the ext csd for future reference */
2238 if (!mmc->ext_csd)
2239 mmc->ext_csd = malloc(MMC_MAX_BLOCK_LEN);
2240 if (!mmc->ext_csd)
2241 return -ENOMEM;
2242 memcpy(mmc->ext_csd, ext_csd, MMC_MAX_BLOCK_LEN);
62d77cea 2243#endif
76584e33 2244 if (ext_csd[EXT_CSD_REV] >= ARRAY_SIZE(mmc_versions))
58a6fb7b
JJH		 2245 return -EINVAL;
2246
2247 mmc->version = mmc_versions[ext_csd[EXT_CSD_REV]];
2248
2249 if (mmc->version >= MMC_VERSION_4_2) {
c744b6f6
JJH		 2250 /*
2251 * According to the JEDEC Standard, the value of
2252 * ext_csd's capacity is valid if the value is more
2253 * than 2GB
2254 */
2255 capacity = ext_csd[EXT_CSD_SEC_CNT] << 0
2256 | ext_csd[EXT_CSD_SEC_CNT + 1] << 8
2257 | ext_csd[EXT_CSD_SEC_CNT + 2] << 16
2258 | ext_csd[EXT_CSD_SEC_CNT + 3] << 24;
2259 capacity *= MMC_MAX_BLOCK_LEN;
2260 if ((capacity >> 20) > 2 * 1024)
2261 mmc->capacity_user = capacity;
2262 }
2263
39320c53
JJH		 2264 if (mmc->version >= MMC_VERSION_4_5)
2265 mmc->gen_cmd6_time = ext_csd[EXT_CSD_GENERIC_CMD6_TIME];
2266
c744b6f6
JJH		 2267 /* The partition data may be non-zero but it is only
2268 * effective if PARTITION_SETTING_COMPLETED is set in
2269 * EXT_CSD, so ignore any data if this bit is not set,
2270 * except for enabling the high-capacity group size
2271 * definition (see below).
2272 */
2273 part_completed = !!(ext_csd[EXT_CSD_PARTITION_SETTING] &
2274 EXT_CSD_PARTITION_SETTING_COMPLETED);
2275
513e00b6
JJH		 2276 mmc->part_switch_time = ext_csd[EXT_CSD_PART_SWITCH_TIME];
2277 /* Some eMMC set the value too low so set a minimum */
2278 if (mmc->part_switch_time < MMC_MIN_PART_SWITCH_TIME && mmc->part_switch_time)
2279 mmc->part_switch_time = MMC_MIN_PART_SWITCH_TIME;
2280
c744b6f6
JJH		 2281 /* store the partition info of emmc */
2282 mmc->part_support = ext_csd[EXT_CSD_PARTITIONING_SUPPORT];
2283 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) ||
2284 ext_csd[EXT_CSD_BOOT_MULT])
2285 mmc->part_config = ext_csd[EXT_CSD_PART_CONF];
2286 if (part_completed &&
2287 (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & ENHNCD_SUPPORT))
2288 mmc->part_attr = ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE];
2289
2290 mmc->capacity_boot = ext_csd[EXT_CSD_BOOT_MULT] << 17;
2291
2292 mmc->capacity_rpmb = ext_csd[EXT_CSD_RPMB_MULT] << 17;
2293
2294 for (i = 0; i < 4; i++) {
2295 int idx = EXT_CSD_GP_SIZE_MULT + i * 3;
2296 uint mult = (ext_csd[idx + 2] << 16) +
2297 (ext_csd[idx + 1] << 8) + ext_csd[idx];
2298 if (mult)
2299 has_parts = true;
2300 if (!part_completed)
2301 continue;
2302 mmc->capacity_gp[i] = mult;
2303 mmc->capacity_gp[i] *=
2304 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
2305 mmc->capacity_gp[i] *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
2306 mmc->capacity_gp[i] <<= 19;
2307 }
2308
173c06df 2309#ifndef CONFIG_SPL_BUILD
c744b6f6
JJH		 2310 if (part_completed) {
2311 mmc->enh_user_size =
2312 (ext_csd[EXT_CSD_ENH_SIZE_MULT + 2] << 16) +
2313 (ext_csd[EXT_CSD_ENH_SIZE_MULT + 1] << 8) +
2314 ext_csd[EXT_CSD_ENH_SIZE_MULT];
2315 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
2316 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
2317 mmc->enh_user_size <<= 19;
2318 mmc->enh_user_start =
2319 (ext_csd[EXT_CSD_ENH_START_ADDR + 3] << 24) +
2320 (ext_csd[EXT_CSD_ENH_START_ADDR + 2] << 16) +
2321 (ext_csd[EXT_CSD_ENH_START_ADDR + 1] << 8) +
2322 ext_csd[EXT_CSD_ENH_START_ADDR];
2323 if (mmc->high_capacity)
2324 mmc->enh_user_start <<= 9;
2325 }
173c06df 2326#endif
c744b6f6
JJH		 2327
2328 /*
2329 * Host needs to enable ERASE_GRP_DEF bit if device is
2330 * partitioned. This bit will be lost every time after a reset
2331 * or power off. This will affect erase size.
2332 */
2333 if (part_completed)
2334 has_parts = true;
2335 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) &&
2336 (ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE] & PART_ENH_ATTRIB))
2337 has_parts = true;
2338 if (has_parts) {
2339 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
2340 EXT_CSD_ERASE_GROUP_DEF, 1);
2341
2342 if (err)
f7d5dffc 2343 goto error;
c744b6f6
JJH		 2344
2345 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
2346 }
2347
2348 if (ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01) {
e6fa5a54 2349#if CONFIG_IS_ENABLED(MMC_WRITE)
c744b6f6
JJH		 2350 /* Read out group size from ext_csd */
2351 mmc->erase_grp_size =
2352 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
e6fa5a54 2353#endif
c744b6f6
JJH		 2354 /*
2355 * if high capacity and partition setting completed
2356 * SEC_COUNT is valid even if it is smaller than 2 GiB
2357 * JEDEC Standard JESD84-B45, 6.2.4
2358 */
2359 if (mmc->high_capacity && part_completed) {
2360 capacity = (ext_csd[EXT_CSD_SEC_CNT]) |
2361 (ext_csd[EXT_CSD_SEC_CNT + 1] << 8) |
2362 (ext_csd[EXT_CSD_SEC_CNT + 2] << 16) |
2363 (ext_csd[EXT_CSD_SEC_CNT + 3] << 24);
2364 capacity *= MMC_MAX_BLOCK_LEN;
2365 mmc->capacity_user = capacity;
2366 }
e6fa5a54
JJH		 2367 }
2368#if CONFIG_IS_ENABLED(MMC_WRITE)
2369 else {
c744b6f6
JJH		 2370 /* Calculate the group size from the csd value. */
2371 int erase_gsz, erase_gmul;
2372
2373 erase_gsz = (mmc->csd[2] & 0x00007c00) >> 10;
2374 erase_gmul = (mmc->csd[2] & 0x000003e0) >> 5;
2375 mmc->erase_grp_size = (erase_gsz + 1)
2376 * (erase_gmul + 1);
2377 }
e6fa5a54 2378#endif
b7a6e2c9 2379#if CONFIG_IS_ENABLED(MMC_HW_PARTITIONING)
c744b6f6
JJH		 2380 mmc->hc_wp_grp_size = 1024
2381 * ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
2382 * ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
b7a6e2c9 2383#endif
c744b6f6
JJH		 2384
2385 mmc->wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
2386
2387 return 0;
f7d5dffc
JJH		 2388error:
2389 if (mmc->ext_csd) {
62d77cea 2390#if !CONFIG_IS_ENABLED(MMC_TINY)
f7d5dffc 2391 free(mmc->ext_csd);
62d77cea 2392#endif
f7d5dffc
JJH		 2393 mmc->ext_csd = NULL;
2394 }
2395 return err;
c744b6f6
JJH		 2396}
2397
fdbb873e 2398static int mmc_startup(struct mmc *mmc)
272cc70b 2399{
f866a46d 2400 int err, i;
272cc70b 2401 uint mult, freq;
c744b6f6 2402 u64 cmult, csize;
272cc70b 2403 struct mmc_cmd cmd;
c40fdca6 2404 struct blk_desc *bdesc;
272cc70b 2405
d52ebf10
TC		 2406#ifdef CONFIG_MMC_SPI_CRC_ON
2407 if (mmc_host_is_spi(mmc)) { /* enable CRC check for spi */
2408 cmd.cmdidx = MMC_CMD_SPI_CRC_ON_OFF;
2409 cmd.resp_type = MMC_RSP_R1;
2410 cmd.cmdarg = 1;
d52ebf10 2411 err = mmc_send_cmd(mmc, &cmd, NULL);
d52ebf10
TC		 2412 if (err)
2413 return err;
2414 }
2415#endif
2416
272cc70b 2417 /* Put the Card in Identify Mode */
d52ebf10
TC		 2418 cmd.cmdidx = mmc_host_is_spi(mmc) ? MMC_CMD_SEND_CID :
2419 MMC_CMD_ALL_SEND_CID; /* cmd not supported in spi */
272cc70b
AF		 2420 cmd.resp_type = MMC_RSP_R2;
2421 cmd.cmdarg = 0;
272cc70b
AF		 2422
2423 err = mmc_send_cmd(mmc, &cmd, NULL);
2424
83dc4227
KVA		 2425#ifdef CONFIG_MMC_QUIRKS
2426 if (err && (mmc->quirks & MMC_QUIRK_RETRY_SEND_CID)) {
2427 int retries = 4;
2428 /*
2429 * It has been seen that SEND_CID may fail on the first
2430 * attempt, let's try a few more time
2431 */
2432 do {
2433 err = mmc_send_cmd(mmc, &cmd, NULL);
2434 if (!err)
2435 break;
2436 } while (retries--);
2437 }
2438#endif
2439
272cc70b
AF		 2440 if (err)
2441 return err;
2442
2443 memcpy(mmc->cid, cmd.response, 16);
2444
2445 /*
2446 * For MMC cards, set the Relative Address.
2447 * For SD cards, get the Relatvie Address.
2448 * This also puts the cards into Standby State
2449 */
d52ebf10
TC		 2450 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
2451 cmd.cmdidx = SD_CMD_SEND_RELATIVE_ADDR;
2452 cmd.cmdarg = mmc->rca << 16;
2453 cmd.resp_type = MMC_RSP_R6;
272cc70b 2454
d52ebf10 2455 err = mmc_send_cmd(mmc, &cmd, NULL);
272cc70b 2456
d52ebf10
TC		 2457 if (err)
2458 return err;
272cc70b 2459
d52ebf10
TC		 2460 if (IS_SD(mmc))
2461 mmc->rca = (cmd.response[0] >> 16) & 0xffff;
2462 }
272cc70b
AF		 2463
2464 /* Get the Card-Specific Data */
2465 cmd.cmdidx = MMC_CMD_SEND_CSD;
2466 cmd.resp_type = MMC_RSP_R2;
2467 cmd.cmdarg = mmc->rca << 16;
272cc70b
AF		 2468
2469 err = mmc_send_cmd(mmc, &cmd, NULL);
2470
2471 if (err)
2472 return err;
2473
998be3dd
RV		 2474 mmc->csd[0] = cmd.response[0];
2475 mmc->csd[1] = cmd.response[1];
2476 mmc->csd[2] = cmd.response[2];
2477 mmc->csd[3] = cmd.response[3];
272cc70b
AF		 2478
2479 if (mmc->version == MMC_VERSION_UNKNOWN) {
0b453ffe 2480 int version = (cmd.response[0] >> 26) & 0xf;
272cc70b
AF		 2481
2482 switch (version) {
53e8e40b
BM		 2483 case 0:
2484 mmc->version = MMC_VERSION_1_2;
2485 break;
2486 case 1:
2487 mmc->version = MMC_VERSION_1_4;
2488 break;
2489 case 2:
2490 mmc->version = MMC_VERSION_2_2;
2491 break;
2492 case 3:
2493 mmc->version = MMC_VERSION_3;
2494 break;
2495 case 4:
2496 mmc->version = MMC_VERSION_4;
2497 break;
2498 default:
2499 mmc->version = MMC_VERSION_1_2;
2500 break;
272cc70b
AF		 2501 }
2502 }
2503
2504 /* divide frequency by 10, since the mults are 10x bigger */
0b453ffe
RV		 2505 freq = fbase[(cmd.response[0] & 0x7)];
2506 mult = multipliers[((cmd.response[0] >> 3) & 0xf)];
272cc70b 2507
35f9e196 2508 mmc->legacy_speed = freq * mult;
35f9e196 2509 mmc_select_mode(mmc, MMC_LEGACY);
272cc70b 2510
ab71188c 2511 mmc->dsr_imp = ((cmd.response[1] >> 12) & 0x1);
998be3dd 2512 mmc->read_bl_len = 1 << ((cmd.response[1] >> 16) & 0xf);
e6fa5a54 2513#if CONFIG_IS_ENABLED(MMC_WRITE)
272cc70b
AF		 2514
2515 if (IS_SD(mmc))
2516 mmc->write_bl_len = mmc->read_bl_len;
2517 else
998be3dd 2518 mmc->write_bl_len = 1 << ((cmd.response[3] >> 22) & 0xf);
e6fa5a54 2519#endif
272cc70b
AF		 2520
2521 if (mmc->high_capacity) {
2522 csize = (mmc->csd[1] & 0x3f) << 16
2523 | (mmc->csd[2] & 0xffff0000) >> 16;
2524 cmult = 8;
2525 } else {
2526 csize = (mmc->csd[1] & 0x3ff) << 2
2527 | (mmc->csd[2] & 0xc0000000) >> 30;
2528 cmult = (mmc->csd[2] & 0x00038000) >> 15;
2529 }
2530
f866a46d
SW		 2531 mmc->capacity_user = (csize + 1) << (cmult + 2);
2532 mmc->capacity_user *= mmc->read_bl_len;
2533 mmc->capacity_boot = 0;
2534 mmc->capacity_rpmb = 0;
2535 for (i = 0; i < 4; i++)
2536 mmc->capacity_gp[i] = 0;
272cc70b 2537
8bfa195e
SG		 2538 if (mmc->read_bl_len > MMC_MAX_BLOCK_LEN)
2539 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
272cc70b 2540
e6fa5a54 2541#if CONFIG_IS_ENABLED(MMC_WRITE)
8bfa195e
SG		 2542 if (mmc->write_bl_len > MMC_MAX_BLOCK_LEN)
2543 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
e6fa5a54 2544#endif
272cc70b 2545
ab71188c
MN		 2546 if ((mmc->dsr_imp) && (0xffffffff != mmc->dsr)) {
2547 cmd.cmdidx = MMC_CMD_SET_DSR;
2548 cmd.cmdarg = (mmc->dsr & 0xffff) << 16;
2549 cmd.resp_type = MMC_RSP_NONE;
2550 if (mmc_send_cmd(mmc, &cmd, NULL))
d8e3d420 2551 pr_warn("MMC: SET_DSR failed\n");
ab71188c
MN		 2552 }
2553
272cc70b 2554 /* Select the card, and put it into Transfer Mode */
d52ebf10
TC		 2555 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
2556 cmd.cmdidx = MMC_CMD_SELECT_CARD;
fe8f7066 2557 cmd.resp_type = MMC_RSP_R1;
d52ebf10 2558 cmd.cmdarg = mmc->rca << 16;
d52ebf10 2559 err = mmc_send_cmd(mmc, &cmd, NULL);
272cc70b 2560
d52ebf10
TC		 2561 if (err)
2562 return err;
2563 }
272cc70b 2564
e6f99a56
LW		 2565 /*
2566 * For SD, its erase group is always one sector
2567 */
e6fa5a54 2568#if CONFIG_IS_ENABLED(MMC_WRITE)
e6f99a56 2569 mmc->erase_grp_size = 1;
e6fa5a54 2570#endif
bc897b1d 2571 mmc->part_config = MMCPART_NOAVAILABLE;
1937e5aa 2572
dfda9d88 2573 err = mmc_startup_v4(mmc);
c744b6f6
JJH		 2574 if (err)
2575 return err;
d23e2c09 2576
c40fdca6 2577 err = mmc_set_capacity(mmc, mmc_get_blk_desc(mmc)->hwpart);
f866a46d
SW		 2578 if (err)
2579 return err;
2580
62d77cea
MV		 2581#if CONFIG_IS_ENABLED(MMC_TINY)
2582 mmc_set_clock(mmc, mmc->legacy_speed, false);
e8d5dde4 2583 mmc_select_mode(mmc, MMC_LEGACY);
62d77cea
MV		 2584 mmc_set_bus_width(mmc, 1);
2585#else
01298da3
JJH		 2586 if (IS_SD(mmc)) {
2587 err = sd_get_capabilities(mmc);
2588 if (err)
2589 return err;
2590 err = sd_select_mode_and_width(mmc, mmc->card_caps);
2591 } else {
2592 err = mmc_get_capabilities(mmc);
2593 if (err)
2594 return err;
8adf50ef 2595 err = mmc_select_mode_and_width(mmc, mmc->card_caps);
01298da3 2596 }
62d77cea 2597#endif
272cc70b
AF		 2598 if (err)
2599 return err;
2600
01298da3 2601 mmc->best_mode = mmc->selected_mode;
ad5fd922 2602
5af8f45c
AG		 2603 /* Fix the block length for DDR mode */
2604 if (mmc->ddr_mode) {
2605 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
e6fa5a54 2606#if CONFIG_IS_ENABLED(MMC_WRITE)
5af8f45c 2607 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
e6fa5a54 2608#endif
5af8f45c
AG		 2609 }
2610
272cc70b 2611 /* fill in device description */
c40fdca6
SG		 2612 bdesc = mmc_get_blk_desc(mmc);
2613 bdesc->lun = 0;
2614 bdesc->hwpart = 0;
2615 bdesc->type = 0;
2616 bdesc->blksz = mmc->read_bl_len;
2617 bdesc->log2blksz = LOG2(bdesc->blksz);
2618 bdesc->lba = lldiv(mmc->capacity, mmc->read_bl_len);
fc011f64
SS		 2619#if !defined(CONFIG_SPL_BUILD) || \
2620 (defined(CONFIG_SPL_LIBCOMMON_SUPPORT) && \
27084c03 2621 !CONFIG_IS_ENABLED(USE_TINY_PRINTF))
c40fdca6 2622 sprintf(bdesc->vendor, "Man %06x Snr %04x%04x",
babce5f6
TH		 2623 mmc->cid[0] >> 24, (mmc->cid[2] & 0xffff),
2624 (mmc->cid[3] >> 16) & 0xffff);
c40fdca6 2625 sprintf(bdesc->product, "%c%c%c%c%c%c", mmc->cid[0] & 0xff,
babce5f6
TH		 2626 (mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff,
2627 (mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff,
2628 (mmc->cid[2] >> 24) & 0xff);
c40fdca6 2629 sprintf(bdesc->revision, "%d.%d", (mmc->cid[2] >> 20) & 0xf,
babce5f6 2630 (mmc->cid[2] >> 16) & 0xf);
56196826 2631#else
c40fdca6
SG		 2632 bdesc->vendor[0] = 0;
2633 bdesc->product[0] = 0;
2634 bdesc->revision[0] = 0;
56196826 2635#endif
272cc70b 2636
eef05fd3
AP		 2637#if !defined(CONFIG_DM_MMC) && (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBDISK_SUPPORT))
2638 part_init(bdesc);
2639#endif
2640
272cc70b
AF		 2641 return 0;
2642}
2643
fdbb873e 2644static int mmc_send_if_cond(struct mmc *mmc)
272cc70b
AF		 2645{
2646 struct mmc_cmd cmd;
2647 int err;
2648
2649 cmd.cmdidx = SD_CMD_SEND_IF_COND;
2650 /* We set the bit if the host supports voltages between 2.7 and 3.6 V */
93bfd616 2651 cmd.cmdarg = ((mmc->cfg->voltages & 0xff8000) != 0) << 8 | 0xaa;
272cc70b 2652 cmd.resp_type = MMC_RSP_R7;
272cc70b
AF		 2653
2654 err = mmc_send_cmd(mmc, &cmd, NULL);
2655
2656 if (err)
2657 return err;
2658
998be3dd 2659 if ((cmd.response[0] & 0xff) != 0xaa)
915ffa52 2660 return -EOPNOTSUPP;
272cc70b
AF		 2661 else
2662 mmc->version = SD_VERSION_2;
2663
2664 return 0;
2665}
2666
c4d660d4 2667#if !CONFIG_IS_ENABLED(DM_MMC)
95de9ab2
PK		 2668/* board-specific MMC power initializations. */
2669__weak void board_mmc_power_init(void)
2670{
2671}
05cbeb7c 2672#endif
95de9ab2 2673
2051aefe
PF		 2674static int mmc_power_init(struct mmc *mmc)
2675{
c4d660d4 2676#if CONFIG_IS_ENABLED(DM_MMC)
06ec045f 2677#if CONFIG_IS_ENABLED(DM_REGULATOR)
2051aefe
PF		 2678 int ret;
2679
2680 ret = device_get_supply_regulator(mmc->dev, "vmmc-supply",
06ec045f
JJH		 2681 &mmc->vmmc_supply);
2682 if (ret)
d4d64889 2683 pr_debug("%s: No vmmc supply\n", mmc->dev->name);
2051aefe 2684
06ec045f
JJH		 2685 ret = device_get_supply_regulator(mmc->dev, "vqmmc-supply",
2686 &mmc->vqmmc_supply);
2687 if (ret)
d4d64889 2688 pr_debug("%s: No vqmmc supply\n", mmc->dev->name);
fb7c3beb
KVA		 2689#endif
2690#else /* !CONFIG_DM_MMC */
2691 /*
2692 * Driver model should use a regulator, as above, rather than calling
2693 * out to board code.
2694 */
2695 board_mmc_power_init();
2696#endif
2697 return 0;
2698}
2699
2700/*
2701 * put the host in the initial state:
2702 * - turn on Vdd (card power supply)
2703 * - configure the bus width and clock to minimal values
2704 */
2705static void mmc_set_initial_state(struct mmc *mmc)
2706{
2707 int err;
2708
2709 /* First try to set 3.3V. If it fails set to 1.8V */
2710 err = mmc_set_signal_voltage(mmc, MMC_SIGNAL_VOLTAGE_330);
2711 if (err != 0)
2712 err = mmc_set_signal_voltage(mmc, MMC_SIGNAL_VOLTAGE_180);
2713 if (err != 0)
d8e3d420 2714 pr_warn("mmc: failed to set signal voltage\n");
fb7c3beb
KVA		 2715
2716 mmc_select_mode(mmc, MMC_LEGACY);
2717 mmc_set_bus_width(mmc, 1);
65117182 2718 mmc_set_clock(mmc, 0, MMC_CLK_ENABLE);
fb7c3beb 2719}
06ec045f 2720
fb7c3beb
KVA		 2721static int mmc_power_on(struct mmc *mmc)
2722{
2723#if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(DM_REGULATOR)
06ec045f 2724 if (mmc->vmmc_supply) {
fb7c3beb
KVA		 2725 int ret = regulator_set_enable(mmc->vmmc_supply, true);
2726
06ec045f
JJH		 2727 if (ret) {
2728 puts("Error enabling VMMC supply\n");
2729 return ret;
2730 }
2051aefe 2731 }
05cbeb7c 2732#endif
fb7c3beb
KVA		 2733 return 0;
2734}
2735
2736static int mmc_power_off(struct mmc *mmc)
2737{
65117182 2738 mmc_set_clock(mmc, 0, MMC_CLK_DISABLE);
fb7c3beb
KVA		 2739#if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(DM_REGULATOR)
2740 if (mmc->vmmc_supply) {
2741 int ret = regulator_set_enable(mmc->vmmc_supply, false);
2742
2743 if (ret) {
d4d64889 2744 pr_debug("Error disabling VMMC supply\n");
fb7c3beb
KVA		 2745 return ret;
2746 }
2747 }
2051aefe
PF		 2748#endif
2749 return 0;
2750}
2751
fb7c3beb
KVA		 2752static int mmc_power_cycle(struct mmc *mmc)
2753{
2754 int ret;
2755
2756 ret = mmc_power_off(mmc);
2757 if (ret)
2758 return ret;
3602a56a
YG		 2759
2760 ret = mmc_host_power_cycle(mmc);
2761 if (ret)
2762 return ret;
2763
fb7c3beb
KVA		 2764 /*
2765 * SD spec recommends at least 1ms of delay. Let's wait for 2ms
2766 * to be on the safer side.
2767 */
2768 udelay(2000);
2769 return mmc_power_on(mmc);
2770}
2771
6c09eba5 2772int mmc_get_op_cond(struct mmc *mmc)
272cc70b 2773{
c10b85d6 2774 bool uhs_en = supports_uhs(mmc->cfg->host_caps);
afd5932b 2775 int err;
272cc70b 2776
bc897b1d
LW		 2777 if (mmc->has_init)
2778 return 0;
2779
5a8dbdc6
YL		 2780#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
2781 mmc_adapter_card_type_ident();
2782#endif
2051aefe
PF		 2783 err = mmc_power_init(mmc);
2784 if (err)
2785 return err;
95de9ab2 2786
83dc4227
KVA		 2787#ifdef CONFIG_MMC_QUIRKS
2788 mmc->quirks = MMC_QUIRK_RETRY_SET_BLOCKLEN |
d4a5fa31
JJ		 2789 MMC_QUIRK_RETRY_SEND_CID |
2790 MMC_QUIRK_RETRY_APP_CMD;
83dc4227
KVA		 2791#endif
2792
04a2ea24
JJH		 2793 err = mmc_power_cycle(mmc);
2794 if (err) {
2795 /*
2796 * if power cycling is not supported, we should not try
2797 * to use the UHS modes, because we wouldn't be able to
2798 * recover from an error during the UHS initialization.
2799 */
d4d64889 2800 pr_debug("Unable to do a full power cycle. Disabling the UHS modes for safety\n");
04a2ea24
JJH		 2801 uhs_en = false;
2802 mmc->host_caps &= ~UHS_CAPS;
2803 err = mmc_power_on(mmc);
2804 }
fb7c3beb
KVA		 2805 if (err)
2806 return err;
2807
e7881d85 2808#if CONFIG_IS_ENABLED(DM_MMC)
8ca51e51
SG		 2809 /* The device has already been probed ready for use */
2810#else
ab769f22 2811 /* made sure it's not NULL earlier */
93bfd616 2812 err = mmc->cfg->ops->init(mmc);
272cc70b
AF		 2813 if (err)
2814 return err;
8ca51e51 2815#endif
786e8f81 2816 mmc->ddr_mode = 0;
aff5d3c8 2817
c10b85d6 2818retry:
fb7c3beb 2819 mmc_set_initial_state(mmc);
318a7a57 2820
272cc70b
AF		 2821 /* Reset the Card */
2822 err = mmc_go_idle(mmc);
2823
2824 if (err)
2825 return err;
2826
bc897b1d 2827 /* The internal partition reset to user partition(0) at every CMD0*/
c40fdca6 2828 mmc_get_blk_desc(mmc)->hwpart = 0;
bc897b1d 2829
272cc70b 2830 /* Test for SD version 2 */
afd5932b 2831 err = mmc_send_if_cond(mmc);
272cc70b 2832
272cc70b 2833 /* Now try to get the SD card's operating condition */
c10b85d6
JJH		 2834 err = sd_send_op_cond(mmc, uhs_en);
2835 if (err && uhs_en) {
2836 uhs_en = false;
2837 mmc_power_cycle(mmc);
2838 goto retry;
2839 }
272cc70b
AF		 2840
2841 /* If the command timed out, we check for an MMC card */
915ffa52 2842 if (err == -ETIMEDOUT) {
272cc70b
AF		 2843 err = mmc_send_op_cond(mmc);
2844
bd47c135 2845 if (err) {
56196826 2846#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
d8e3d420 2847 pr_err("Card did not respond to voltage select!\n");
56196826 2848#endif
915ffa52 2849 return -EOPNOTSUPP;
272cc70b
AF		 2850 }
2851 }
2852
6c09eba5
JN		 2853 return err;
2854}
2855
2856int mmc_start_init(struct mmc *mmc)
2857{
2858 bool no_card;
2859 int err = 0;
2860
2861 /*
2862 * all hosts are capable of 1 bit bus-width and able to use the legacy
2863 * timings.
2864 */
e8d5dde4 2865 mmc->host_caps = mmc->cfg->host_caps | MMC_CAP(MMC_LEGACY) |
6c09eba5 2866 MMC_CAP(MMC_LEGACY) | MMC_MODE_1BIT;
32860bdb
FA		 2867#if CONFIG_IS_ENABLED(DM_MMC)
2868 mmc_deferred_probe(mmc);
2869#endif
6c09eba5 2870#if !defined(CONFIG_MMC_BROKEN_CD)
6c09eba5
JN		 2871 no_card = mmc_getcd(mmc) == 0;
2872#else
2873 no_card = 0;
2874#endif
2875#if !CONFIG_IS_ENABLED(DM_MMC)
fea3939d 2876 /* we pretend there's no card when init is NULL */
6c09eba5
JN		 2877 no_card = no_card || (mmc->cfg->ops->init == NULL);
2878#endif
2879 if (no_card) {
2880 mmc->has_init = 0;
2881#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
2882 pr_err("MMC: no card present\n");
2883#endif
2884 return -ENOMEDIUM;
2885 }
2886
2887 err = mmc_get_op_cond(mmc);
2888
bd47c135 2889 if (!err)
e9550449
CLC		 2890 mmc->init_in_progress = 1;
2891
2892 return err;
2893}
2894
2895static int mmc_complete_init(struct mmc *mmc)
2896{
2897 int err = 0;
2898
bd47c135 2899 mmc->init_in_progress = 0;
e9550449
CLC		 2900 if (mmc->op_cond_pending)
2901 err = mmc_complete_op_cond(mmc);
2902
2903 if (!err)
2904 err = mmc_startup(mmc);
bc897b1d
LW		 2905 if (err)
2906 mmc->has_init = 0;
2907 else
2908 mmc->has_init = 1;
e9550449
CLC		 2909 return err;
2910}
2911
2912int mmc_init(struct mmc *mmc)
2913{
bd47c135 2914 int err = 0;
36332b6e 2915 __maybe_unused ulong start;
c4d660d4 2916#if CONFIG_IS_ENABLED(DM_MMC)
33fb211d 2917 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(mmc->dev);
e9550449 2918
33fb211d
SG		 2919 upriv->mmc = mmc;
2920#endif
e9550449
CLC		 2921 if (mmc->has_init)
2922 return 0;
d803fea5
MZ		 2923
2924 start = get_timer(0);
2925
e9550449
CLC		 2926 if (!mmc->init_in_progress)
2927 err = mmc_start_init(mmc);
2928
bd47c135 2929 if (!err)
e9550449 2930 err = mmc_complete_init(mmc);
919b4858 2931 if (err)
d4d64889 2932 pr_info("%s: %d, time %lu\n", __func__, err, get_timer(start));
919b4858 2933
bc897b1d 2934 return err;
272cc70b
AF		 2935}
2936
fceea992
MV		 2937#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
2938 CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
2939 CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
2940int mmc_deinit(struct mmc *mmc)
2941{
2942 u32 caps_filtered;
2943
2944 if (!mmc->has_init)
2945 return 0;
2946
2947 if (IS_SD(mmc)) {
2948 caps_filtered = mmc->card_caps &
2949 ~(MMC_CAP(UHS_SDR12) | MMC_CAP(UHS_SDR25) |
2950 MMC_CAP(UHS_SDR50) | MMC_CAP(UHS_DDR50) |
2951 MMC_CAP(UHS_SDR104));
2952
2953 return sd_select_mode_and_width(mmc, caps_filtered);
2954 } else {
2955 caps_filtered = mmc->card_caps &
2956 ~(MMC_CAP(MMC_HS_200) | MMC_CAP(MMC_HS_400));
2957
2958 return mmc_select_mode_and_width(mmc, caps_filtered);
2959 }
2960}
2961#endif
2962
ab71188c
MN		 2963int mmc_set_dsr(struct mmc *mmc, u16 val)
2964{
2965 mmc->dsr = val;
2966 return 0;
2967}
2968
cee9ab7c
JH		 2969/* CPU-specific MMC initializations */
2970__weak int cpu_mmc_init(bd_t *bis)
272cc70b
AF		 2971{
2972 return -1;
2973}
2974
cee9ab7c
JH		 2975/* board-specific MMC initializations. */
2976__weak int board_mmc_init(bd_t *bis)
2977{
2978 return -1;
2979}
272cc70b 2980
e9550449
CLC		 2981void mmc_set_preinit(struct mmc *mmc, int preinit)
2982{
2983 mmc->preinit = preinit;
2984}
2985
8a856db2 2986#if CONFIG_IS_ENABLED(DM_MMC)
8e3332e2
SS		 2987static int mmc_probe(bd_t *bis)
2988{
4a1db6d8 2989 int ret, i;
8e3332e2 2990 struct uclass *uc;
4a1db6d8 2991 struct udevice *dev;
8e3332e2
SS		 2992
2993 ret = uclass_get(UCLASS_MMC, &uc);
2994 if (ret)
2995 return ret;
2996
4a1db6d8
SG		 2997 /*
2998 * Try to add them in sequence order. Really with driver model we
2999 * should allow holes, but the current MMC list does not allow that.
3000 * So if we request 0, 1, 3 we will get 0, 1, 2.
3001 */
3002 for (i = 0; ; i++) {
3003 ret = uclass_get_device_by_seq(UCLASS_MMC, i, &dev);
3004 if (ret == -ENODEV)
3005 break;
3006 }
3007 uclass_foreach_dev(dev, uc) {
3008 ret = device_probe(dev);
8e3332e2 3009 if (ret)
d8e3d420 3010 pr_err("%s - probe failed: %d\n", dev->name, ret);
8e3332e2
SS		 3011 }
3012
3013 return 0;
3014}
3015#else
3016static int mmc_probe(bd_t *bis)
3017{
3018 if (board_mmc_init(bis) < 0)
3019 cpu_mmc_init(bis);
3020
3021 return 0;
3022}
3023#endif
e9550449 3024
272cc70b
AF		 3025int mmc_initialize(bd_t *bis)
3026{
1b26bab1 3027 static int initialized = 0;
8e3332e2 3028 int ret;
1b26bab1
DK		 3029 if (initialized) /* Avoid initializing mmc multiple times */
3030 return 0;
3031 initialized = 1;
3032
c4d660d4 3033#if !CONFIG_IS_ENABLED(BLK)
b5b838f1 3034#if !CONFIG_IS_ENABLED(MMC_TINY)
c40fdca6 3035 mmc_list_init();
b5b838f1 3036#endif
c40fdca6 3037#endif
8e3332e2
SS		 3038 ret = mmc_probe(bis);
3039 if (ret)
3040 return ret;
272cc70b 3041
bb0dc108 3042#ifndef CONFIG_SPL_BUILD
272cc70b 3043 print_mmc_devices(',');
bb0dc108 3044#endif
272cc70b 3045
c40fdca6 3046 mmc_do_preinit();
272cc70b
AF		 3047 return 0;
3048}
cd3d4880 3049
80f02019
LV		 3050#if CONFIG_IS_ENABLED(DM_MMC)
3051int mmc_init_device(int num)
3052{
3053 struct udevice *dev;
3054 struct mmc *m;
3055 int ret;
3056
3057 ret = uclass_get_device(UCLASS_MMC, num, &dev);
3058 if (ret)
3059 return ret;
3060
3061 m = mmc_get_mmc_dev(dev);
3062 if (!m)
3063 return 0;
3064#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
3065 mmc_set_preinit(m, 1);
3066#endif
3067 if (m->preinit)
3068 mmc_start_init(m);
3069
3070 return 0;
3071}
3072#endif
3073
cd3d4880
TM		 3074#ifdef CONFIG_CMD_BKOPS_ENABLE
3075int mmc_set_bkops_enable(struct mmc *mmc)
3076{
3077 int err;
3078 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
3079
3080 err = mmc_send_ext_csd(mmc, ext_csd);
3081 if (err) {
3082 puts("Could not get ext_csd register values\n");
3083 return err;
3084 }
3085
3086 if (!(ext_csd[EXT_CSD_BKOPS_SUPPORT] & 0x1)) {
3087 puts("Background operations not supported on device\n");
3088 return -EMEDIUMTYPE;
3089 }
3090
3091 if (ext_csd[EXT_CSD_BKOPS_EN] & 0x1) {
3092 puts("Background operations already enabled\n");
3093 return 0;
3094 }
3095
3096 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BKOPS_EN, 1);
3097 if (err) {
3098 puts("Failed to enable manual background operations\n");
3099 return err;
3100 }
3101
3102 puts("Enabled manual background operations\n");
3103
3104 return 0;
3105}
3106#endif
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