projects / qemu.git / blame
| Commit | Line | Data |
|---|---|---|
| 143d6785 SG |
1 | # SPDX-License-Identifier: GPL-2.0-or-later |
| 2 | # | |
| 3 | # LoongArch instruction decode definitions. | |
| 4 | # | |
| 5 | # Copyright (c) 2021 Loongson Technology Corporation Limited | |
| 6 | # | |
| 7 | ||
| 8 | # | |
| 9 | # Fields | |
| 10 | # | |
| bb79174d | 11 | %i14s2 10:s14 !function=shl_2 |
| 143d6785 | 12 | %sa2p1 15:2 !function=plus_1 |
| ee86bd58 SG |
13 | %offs21 0:s5 10:16 !function=shl_2 |
| 14 | %offs16 10:s16 !function=shl_2 | |
| 15 | %offs26 0:s10 10:16 !function=shl_2 | |
| 143d6785 SG |
16 | |
| 17 | # | |
| 18 | # Argument sets | |
| 19 | # | |
| bb79174d | 20 | &i imm |
| 143d6785 | 21 | &r_i rd imm |
| ad08cb3f | 22 | &rr rd rj |
| 8708a04a | 23 | &rr_jk rj rk |
| 143d6785 SG |
24 | &rrr rd rj rk |
| 25 | &rr_i rd rj imm | |
| bb79174d | 26 | &hint_r_i hint rj imm |
| 143d6785 | 27 | &rrr_sa rd rj rk sa |
| ad08cb3f | 28 | &rr_ms_ls rd rj ms ls |
| d578ca6c SG |
29 | &ff fd fj |
| 30 | &fff fd fj fk | |
| 31 | &ffff fd fj fk fa | |
| 9b741076 | 32 | &cff_fcond cd fj fk fcond |
| b7dabd56 SG |
33 | &fffc fd fj fk ca |
| 34 | &fr fd rj | |
| 35 | &rf rd fj | |
| 36 | &fcsrd_r fcsrd rj | |
| 37 | &r_fcsrs rd fcsrs | |
| 38 | &cf cd fj | |
| 39 | &fc fd cj | |
| 40 | &cr cd rj | |
| 41 | &rc rd cj | |
| e616bdfd SG |
42 | &frr fd rj rk |
| 43 | &fr_i fd rj imm | |
| ee86bd58 SG |
44 | &r_offs rj offs |
| 45 | &c_offs cj offs | |
| 46 | &offs offs | |
| 47 | &rr_offs rj rd offs | |
| 5b1dedfe XY |
48 | &r_csr rd csr |
| 49 | &rr_csr rd rj csr | |
| fcbbeb8e XY |
50 | &empty |
| 51 | &i_rr imm rj rk | |
| d2cba6f7 XY |
52 | &cop_r_i cop rj imm |
| 53 | &j_i rj imm | |
| 143d6785 SG |
54 | |
| 55 | # | |
| 56 | # Formats | |
| 57 | # | |
| bb79174d | 58 | @i15 .... ........ ..... imm:15 &i |
| ad08cb3f | 59 | @rr .... ........ ..... ..... rj:5 rd:5 &rr |
| 8708a04a | 60 | @rr_jk .... ........ ..... rk:5 rj:5 ..... &rr_jk |
| 143d6785 SG |
61 | @rrr .... ........ ..... rk:5 rj:5 rd:5 &rrr |
| 62 | @r_i20 .... ... imm:s20 rd:5 &r_i | |
| 63cfcd47 SG |
63 | @rr_ui5 .... ........ ..... imm:5 rj:5 rd:5 &rr_i |
| 64 | @rr_ui6 .... ........ .... imm:6 rj:5 rd:5 &rr_i | |
| d2cba6f7 | 65 | @rr_ui8 .. ........ .... imm:8 rj:5 rd:5 &rr_i |
| 143d6785 SG |
66 | @rr_i12 .... ...... imm:s12 rj:5 rd:5 &rr_i |
| 67 | @rr_ui12 .... ...... imm:12 rj:5 rd:5 &rr_i | |
| bb79174d | 68 | @rr_i14s2 .... .... .............. rj:5 rd:5 &rr_i imm=%i14s2 |
| 143d6785 | 69 | @rr_i16 .... .. imm:s16 rj:5 rd:5 &rr_i |
| bb79174d | 70 | @hint_r_i12 .... ...... imm:s12 rj:5 hint:5 &hint_r_i |
| 143d6785 | 71 | @rrr_sa2p1 .... ........ ... .. rk:5 rj:5 rd:5 &rrr_sa sa=%sa2p1 |
| ad08cb3f SG |
72 | @rrr_sa2 .... ........ ... sa:2 rk:5 rj:5 rd:5 &rrr_sa |
| 73 | @rrr_sa3 .... ........ .. sa:3 rk:5 rj:5 rd:5 &rrr_sa | |
| 74 | @rr_2bw .... ....... ms:5 . ls:5 rj:5 rd:5 &rr_ms_ls | |
| 75 | @rr_2bd .... ...... ms:6 ls:6 rj:5 rd:5 &rr_ms_ls | |
| d578ca6c SG |
76 | @ff .... ........ ..... ..... fj:5 fd:5 &ff |
| 77 | @fff .... ........ ..... fk:5 fj:5 fd:5 &fff | |
| 78 | @ffff .... ........ fa:5 fk:5 fj:5 fd:5 &ffff | |
| 9b741076 | 79 | @cff_fcond .... ........ fcond:5 fk:5 fj:5 .. cd:3 &cff_fcond |
| b7dabd56 SG |
80 | @fffc .... ........ .. ca:3 fk:5 fj:5 fd:5 &fffc |
| 81 | @fr .... ........ ..... ..... rj:5 fd:5 &fr | |
| 82 | @rf .... ........ ..... ..... fj:5 rd:5 &rf | |
| 83 | @fcsrd_r .... ........ ..... ..... rj:5 fcsrd:5 &fcsrd_r | |
| 84 | @r_fcsrs .... ........ ..... ..... fcsrs:5 rd:5 &r_fcsrs | |
| 85 | @cf .... ........ ..... ..... fj:5 .. cd:3 &cf | |
| 86 | @fc .... ........ ..... ..... .. cj:3 fd:5 &fc | |
| 87 | @cr .... ........ ..... ..... rj:5 .. cd:3 &cr | |
| 88 | @rc .... ........ ..... ..... .. cj:3 rd:5 &rc | |
| e616bdfd SG |
89 | @frr .... ........ ..... rk:5 rj:5 fd:5 &frr |
| 90 | @fr_i12 .... ...... imm:s12 rj:5 fd:5 &fr_i | |
| ee86bd58 SG |
91 | @r_offs21 .... .. ................ rj:5 ..... &r_offs offs=%offs21 |
| 92 | @c_offs21 .... .. ................ .. cj:3 ..... &c_offs offs=%offs21 | |
| 93 | @offs26 .... .. .......................... &offs offs=%offs26 | |
| 94 | @rr_offs16 .... .. ................ rj:5 rd:5 &rr_offs offs=%offs16 | |
| 5b1dedfe XY |
95 | @r_csr .... .... csr:14 ..... rd:5 &r_csr |
| 96 | @rr_csr .... .... csr:14 rj:5 rd:5 &rr_csr | |
| fcbbeb8e XY |
97 | @empty .... ........ ..... ..... ..... ..... &empty |
| 98 | @i_rr ...... ...... ..... rk:5 rj:5 imm:5 &i_rr | |
| d2cba6f7 XY |
99 | @cop_r_i .... ...... imm:s12 rj:5 cop:5 &cop_r_i |
| 100 | @j_i .... ........ .. imm:8 rj:5 ..... &j_i | |
| 143d6785 SG |
101 | |
| 102 | # | |
| 103 | # Fixed point arithmetic operation instruction | |
| 104 | # | |
| 105 | add_w 0000 00000001 00000 ..... ..... ..... @rrr | |
| 106 | add_d 0000 00000001 00001 ..... ..... ..... @rrr | |
| 107 | sub_w 0000 00000001 00010 ..... ..... ..... @rrr | |
| 108 | sub_d 0000 00000001 00011 ..... ..... ..... @rrr | |
| 109 | slt 0000 00000001 00100 ..... ..... ..... @rrr | |
| 110 | sltu 0000 00000001 00101 ..... ..... ..... @rrr | |
| 111 | slti 0000 001000 ............ ..... ..... @rr_i12 | |
| 112 | sltui 0000 001001 ............ ..... ..... @rr_i12 | |
| 113 | nor 0000 00000001 01000 ..... ..... ..... @rrr | |
| 114 | and 0000 00000001 01001 ..... ..... ..... @rrr | |
| 115 | or 0000 00000001 01010 ..... ..... ..... @rrr | |
| 116 | xor 0000 00000001 01011 ..... ..... ..... @rrr | |
| 117 | orn 0000 00000001 01100 ..... ..... ..... @rrr | |
| 118 | andn 0000 00000001 01101 ..... ..... ..... @rrr | |
| 119 | mul_w 0000 00000001 11000 ..... ..... ..... @rrr | |
| 120 | mulh_w 0000 00000001 11001 ..... ..... ..... @rrr | |
| 121 | mulh_wu 0000 00000001 11010 ..... ..... ..... @rrr | |
| 122 | mul_d 0000 00000001 11011 ..... ..... ..... @rrr | |
| 123 | mulh_d 0000 00000001 11100 ..... ..... ..... @rrr | |
| 124 | mulh_du 0000 00000001 11101 ..... ..... ..... @rrr | |
| 125 | mulw_d_w 0000 00000001 11110 ..... ..... ..... @rrr | |
| 126 | mulw_d_wu 0000 00000001 11111 ..... ..... ..... @rrr | |
| 127 | div_w 0000 00000010 00000 ..... ..... ..... @rrr | |
| 128 | mod_w 0000 00000010 00001 ..... ..... ..... @rrr | |
| 129 | div_wu 0000 00000010 00010 ..... ..... ..... @rrr | |
| 130 | mod_wu 0000 00000010 00011 ..... ..... ..... @rrr | |
| 131 | div_d 0000 00000010 00100 ..... ..... ..... @rrr | |
| 132 | mod_d 0000 00000010 00101 ..... ..... ..... @rrr | |
| 133 | div_du 0000 00000010 00110 ..... ..... ..... @rrr | |
| 134 | mod_du 0000 00000010 00111 ..... ..... ..... @rrr | |
| 135 | alsl_w 0000 00000000 010 .. ..... ..... ..... @rrr_sa2p1 | |
| 136 | alsl_wu 0000 00000000 011 .. ..... ..... ..... @rrr_sa2p1 | |
| 137 | alsl_d 0000 00000010 110 .. ..... ..... ..... @rrr_sa2p1 | |
| 138 | lu12i_w 0001 010 .................... ..... @r_i20 | |
| 139 | lu32i_d 0001 011 .................... ..... @r_i20 | |
| 140 | lu52i_d 0000 001100 ............ ..... ..... @rr_i12 | |
| 141 | pcaddi 0001 100 .................... ..... @r_i20 | |
| 142 | pcalau12i 0001 101 .................... ..... @r_i20 | |
| 143 | pcaddu12i 0001 110 .................... ..... @r_i20 | |
| 144 | pcaddu18i 0001 111 .................... ..... @r_i20 | |
| 145 | addi_w 0000 001010 ............ ..... ..... @rr_i12 | |
| 146 | addi_d 0000 001011 ............ ..... ..... @rr_i12 | |
| 147 | addu16i_d 0001 00 ................ ..... ..... @rr_i16 | |
| 148 | andi 0000 001101 ............ ..... ..... @rr_ui12 | |
| 149 | ori 0000 001110 ............ ..... ..... @rr_ui12 | |
| 150 | xori 0000 001111 ............ ..... ..... @rr_ui12 | |
| 63cfcd47 SG |
151 | |
| 152 | # | |
| 153 | # Fixed point shift operation instruction | |
| 154 | # | |
| 155 | sll_w 0000 00000001 01110 ..... ..... ..... @rrr | |
| 156 | srl_w 0000 00000001 01111 ..... ..... ..... @rrr | |
| 157 | sra_w 0000 00000001 10000 ..... ..... ..... @rrr | |
| 158 | sll_d 0000 00000001 10001 ..... ..... ..... @rrr | |
| 159 | srl_d 0000 00000001 10010 ..... ..... ..... @rrr | |
| 160 | sra_d 0000 00000001 10011 ..... ..... ..... @rrr | |
| 161 | rotr_w 0000 00000001 10110 ..... ..... ..... @rrr | |
| 162 | rotr_d 0000 00000001 10111 ..... ..... ..... @rrr | |
| 163 | slli_w 0000 00000100 00001 ..... ..... ..... @rr_ui5 | |
| 164 | slli_d 0000 00000100 0001 ...... ..... ..... @rr_ui6 | |
| 165 | srli_w 0000 00000100 01001 ..... ..... ..... @rr_ui5 | |
| 166 | srli_d 0000 00000100 0101 ...... ..... ..... @rr_ui6 | |
| 167 | srai_w 0000 00000100 10001 ..... ..... ..... @rr_ui5 | |
| 168 | srai_d 0000 00000100 1001 ...... ..... ..... @rr_ui6 | |
| 169 | rotri_w 0000 00000100 11001 ..... ..... ..... @rr_ui5 | |
| 170 | rotri_d 0000 00000100 1101 ...... ..... ..... @rr_ui6 | |
| ad08cb3f SG |
171 | |
| 172 | # | |
| 173 | # Fixed point bit operation instruction | |
| 174 | # | |
| 175 | ext_w_h 0000 00000000 00000 10110 ..... ..... @rr | |
| 176 | ext_w_b 0000 00000000 00000 10111 ..... ..... @rr | |
| 177 | clo_w 0000 00000000 00000 00100 ..... ..... @rr | |
| 178 | clz_w 0000 00000000 00000 00101 ..... ..... @rr | |
| 179 | cto_w 0000 00000000 00000 00110 ..... ..... @rr | |
| 180 | ctz_w 0000 00000000 00000 00111 ..... ..... @rr | |
| 181 | clo_d 0000 00000000 00000 01000 ..... ..... @rr | |
| 182 | clz_d 0000 00000000 00000 01001 ..... ..... @rr | |
| 183 | cto_d 0000 00000000 00000 01010 ..... ..... @rr | |
| 184 | ctz_d 0000 00000000 00000 01011 ..... ..... @rr | |
| 185 | revb_2h 0000 00000000 00000 01100 ..... ..... @rr | |
| 186 | revb_4h 0000 00000000 00000 01101 ..... ..... @rr | |
| 187 | revb_2w 0000 00000000 00000 01110 ..... ..... @rr | |
| 188 | revb_d 0000 00000000 00000 01111 ..... ..... @rr | |
| 189 | revh_2w 0000 00000000 00000 10000 ..... ..... @rr | |
| 190 | revh_d 0000 00000000 00000 10001 ..... ..... @rr | |
| 191 | bitrev_4b 0000 00000000 00000 10010 ..... ..... @rr | |
| 192 | bitrev_8b 0000 00000000 00000 10011 ..... ..... @rr | |
| 193 | bitrev_w 0000 00000000 00000 10100 ..... ..... @rr | |
| 194 | bitrev_d 0000 00000000 00000 10101 ..... ..... @rr | |
| 195 | bytepick_w 0000 00000000 100 .. ..... ..... ..... @rrr_sa2 | |
| 196 | bytepick_d 0000 00000000 11 ... ..... ..... ..... @rrr_sa3 | |
| 197 | maskeqz 0000 00000001 00110 ..... ..... ..... @rrr | |
| 198 | masknez 0000 00000001 00111 ..... ..... ..... @rrr | |
| 199 | bstrins_w 0000 0000011 ..... 0 ..... ..... ..... @rr_2bw | |
| 200 | bstrpick_w 0000 0000011 ..... 1 ..... ..... ..... @rr_2bw | |
| 201 | bstrins_d 0000 000010 ...... ...... ..... ..... @rr_2bd | |
| 202 | bstrpick_d 0000 000011 ...... ...... ..... ..... @rr_2bd | |
| bb79174d SG |
203 | |
| 204 | # | |
| 205 | # Fixed point load/store instruction | |
| 206 | # | |
| 207 | ld_b 0010 100000 ............ ..... ..... @rr_i12 | |
| 208 | ld_h 0010 100001 ............ ..... ..... @rr_i12 | |
| 209 | ld_w 0010 100010 ............ ..... ..... @rr_i12 | |
| 210 | ld_d 0010 100011 ............ ..... ..... @rr_i12 | |
| 211 | st_b 0010 100100 ............ ..... ..... @rr_i12 | |
| 212 | st_h 0010 100101 ............ ..... ..... @rr_i12 | |
| 213 | st_w 0010 100110 ............ ..... ..... @rr_i12 | |
| 214 | st_d 0010 100111 ............ ..... ..... @rr_i12 | |
| 215 | ld_bu 0010 101000 ............ ..... ..... @rr_i12 | |
| 216 | ld_hu 0010 101001 ............ ..... ..... @rr_i12 | |
| 217 | ld_wu 0010 101010 ............ ..... ..... @rr_i12 | |
| 218 | ldx_b 0011 10000000 00000 ..... ..... ..... @rrr | |
| 219 | ldx_h 0011 10000000 01000 ..... ..... ..... @rrr | |
| 220 | ldx_w 0011 10000000 10000 ..... ..... ..... @rrr | |
| 221 | ldx_d 0011 10000000 11000 ..... ..... ..... @rrr | |
| 222 | stx_b 0011 10000001 00000 ..... ..... ..... @rrr | |
| 223 | stx_h 0011 10000001 01000 ..... ..... ..... @rrr | |
| 224 | stx_w 0011 10000001 10000 ..... ..... ..... @rrr | |
| 225 | stx_d 0011 10000001 11000 ..... ..... ..... @rrr | |
| 226 | ldx_bu 0011 10000010 00000 ..... ..... ..... @rrr | |
| 227 | ldx_hu 0011 10000010 01000 ..... ..... ..... @rrr | |
| 228 | ldx_wu 0011 10000010 10000 ..... ..... ..... @rrr | |
| 229 | preld 0010 101011 ............ ..... ..... @hint_r_i12 | |
| 230 | dbar 0011 10000111 00100 ............... @i15 | |
| 231 | ibar 0011 10000111 00101 ............... @i15 | |
| 232 | ldptr_w 0010 0100 .............. ..... ..... @rr_i14s2 | |
| 233 | stptr_w 0010 0101 .............. ..... ..... @rr_i14s2 | |
| 234 | ldptr_d 0010 0110 .............. ..... ..... @rr_i14s2 | |
| 235 | stptr_d 0010 0111 .............. ..... ..... @rr_i14s2 | |
| 236 | ldgt_b 0011 10000111 10000 ..... ..... ..... @rrr | |
| 237 | ldgt_h 0011 10000111 10001 ..... ..... ..... @rrr | |
| 238 | ldgt_w 0011 10000111 10010 ..... ..... ..... @rrr | |
| 239 | ldgt_d 0011 10000111 10011 ..... ..... ..... @rrr | |
| 240 | ldle_b 0011 10000111 10100 ..... ..... ..... @rrr | |
| 241 | ldle_h 0011 10000111 10101 ..... ..... ..... @rrr | |
| 242 | ldle_w 0011 10000111 10110 ..... ..... ..... @rrr | |
| 243 | ldle_d 0011 10000111 10111 ..... ..... ..... @rrr | |
| 244 | stgt_b 0011 10000111 11000 ..... ..... ..... @rrr | |
| 245 | stgt_h 0011 10000111 11001 ..... ..... ..... @rrr | |
| 246 | stgt_w 0011 10000111 11010 ..... ..... ..... @rrr | |
| 247 | stgt_d 0011 10000111 11011 ..... ..... ..... @rrr | |
| 248 | stle_b 0011 10000111 11100 ..... ..... ..... @rrr | |
| 249 | stle_h 0011 10000111 11101 ..... ..... ..... @rrr | |
| 250 | stle_w 0011 10000111 11110 ..... ..... ..... @rrr | |
| 251 | stle_d 0011 10000111 11111 ..... ..... ..... @rrr | |
| 94b02d57 SG |
252 | |
| 253 | # | |
| 254 | # Fixed point atomic instruction | |
| 255 | # | |
| 256 | ll_w 0010 0000 .............. ..... ..... @rr_i14s2 | |
| 257 | sc_w 0010 0001 .............. ..... ..... @rr_i14s2 | |
| 258 | ll_d 0010 0010 .............. ..... ..... @rr_i14s2 | |
| 259 | sc_d 0010 0011 .............. ..... ..... @rr_i14s2 | |
| 260 | amswap_w 0011 10000110 00000 ..... ..... ..... @rrr | |
| 261 | amswap_d 0011 10000110 00001 ..... ..... ..... @rrr | |
| 262 | amadd_w 0011 10000110 00010 ..... ..... ..... @rrr | |
| 263 | amadd_d 0011 10000110 00011 ..... ..... ..... @rrr | |
| 264 | amand_w 0011 10000110 00100 ..... ..... ..... @rrr | |
| 265 | amand_d 0011 10000110 00101 ..... ..... ..... @rrr | |
| 266 | amor_w 0011 10000110 00110 ..... ..... ..... @rrr | |
| 267 | amor_d 0011 10000110 00111 ..... ..... ..... @rrr | |
| 268 | amxor_w 0011 10000110 01000 ..... ..... ..... @rrr | |
| 269 | amxor_d 0011 10000110 01001 ..... ..... ..... @rrr | |
| 270 | ammax_w 0011 10000110 01010 ..... ..... ..... @rrr | |
| 271 | ammax_d 0011 10000110 01011 ..... ..... ..... @rrr | |
| 272 | ammin_w 0011 10000110 01100 ..... ..... ..... @rrr | |
| 273 | ammin_d 0011 10000110 01101 ..... ..... ..... @rrr | |
| 274 | ammax_wu 0011 10000110 01110 ..... ..... ..... @rrr | |
| 275 | ammax_du 0011 10000110 01111 ..... ..... ..... @rrr | |
| 276 | ammin_wu 0011 10000110 10000 ..... ..... ..... @rrr | |
| 277 | ammin_du 0011 10000110 10001 ..... ..... ..... @rrr | |
| 278 | amswap_db_w 0011 10000110 10010 ..... ..... ..... @rrr | |
| 279 | amswap_db_d 0011 10000110 10011 ..... ..... ..... @rrr | |
| 280 | amadd_db_w 0011 10000110 10100 ..... ..... ..... @rrr | |
| 281 | amadd_db_d 0011 10000110 10101 ..... ..... ..... @rrr | |
| 282 | amand_db_w 0011 10000110 10110 ..... ..... ..... @rrr | |
| 283 | amand_db_d 0011 10000110 10111 ..... ..... ..... @rrr | |
| 284 | amor_db_w 0011 10000110 11000 ..... ..... ..... @rrr | |
| 285 | amor_db_d 0011 10000110 11001 ..... ..... ..... @rrr | |
| 286 | amxor_db_w 0011 10000110 11010 ..... ..... ..... @rrr | |
| 287 | amxor_db_d 0011 10000110 11011 ..... ..... ..... @rrr | |
| 288 | ammax_db_w 0011 10000110 11100 ..... ..... ..... @rrr | |
| 289 | ammax_db_d 0011 10000110 11101 ..... ..... ..... @rrr | |
| 290 | ammin_db_w 0011 10000110 11110 ..... ..... ..... @rrr | |
| 291 | ammin_db_d 0011 10000110 11111 ..... ..... ..... @rrr | |
| 292 | ammax_db_wu 0011 10000111 00000 ..... ..... ..... @rrr | |
| 293 | ammax_db_du 0011 10000111 00001 ..... ..... ..... @rrr | |
| 294 | ammin_db_wu 0011 10000111 00010 ..... ..... ..... @rrr | |
| 295 | ammin_db_du 0011 10000111 00011 ..... ..... ..... @rrr | |
| 8708a04a SG |
296 | |
| 297 | # | |
| 298 | # Fixed point extra instruction | |
| 299 | # | |
| 300 | crc_w_b_w 0000 00000010 01000 ..... ..... ..... @rrr | |
| 301 | crc_w_h_w 0000 00000010 01001 ..... ..... ..... @rrr | |
| 302 | crc_w_w_w 0000 00000010 01010 ..... ..... ..... @rrr | |
| 303 | crc_w_d_w 0000 00000010 01011 ..... ..... ..... @rrr | |
| 304 | crcc_w_b_w 0000 00000010 01100 ..... ..... ..... @rrr | |
| 305 | crcc_w_h_w 0000 00000010 01101 ..... ..... ..... @rrr | |
| 306 | crcc_w_w_w 0000 00000010 01110 ..... ..... ..... @rrr | |
| 307 | crcc_w_d_w 0000 00000010 01111 ..... ..... ..... @rrr | |
| 308 | break 0000 00000010 10100 ............... @i15 | |
| 309 | syscall 0000 00000010 10110 ............... @i15 | |
| 310 | asrtle_d 0000 00000000 00010 ..... ..... 00000 @rr_jk | |
| 311 | asrtgt_d 0000 00000000 00011 ..... ..... 00000 @rr_jk | |
| f9bf5074 XY |
312 | rdtimel_w 0000 00000000 00000 11000 ..... ..... @rr |
| 313 | rdtimeh_w 0000 00000000 00000 11001 ..... ..... @rr | |
| 314 | rdtime_d 0000 00000000 00000 11010 ..... ..... @rr | |
| 8708a04a | 315 | cpucfg 0000 00000000 00000 11011 ..... ..... @rr |
| d578ca6c SG |
316 | |
| 317 | # | |
| 318 | # Floating point arithmetic operation instruction | |
| 319 | # | |
| 320 | fadd_s 0000 00010000 00001 ..... ..... ..... @fff | |
| 321 | fadd_d 0000 00010000 00010 ..... ..... ..... @fff | |
| 322 | fsub_s 0000 00010000 00101 ..... ..... ..... @fff | |
| 323 | fsub_d 0000 00010000 00110 ..... ..... ..... @fff | |
| 324 | fmul_s 0000 00010000 01001 ..... ..... ..... @fff | |
| 325 | fmul_d 0000 00010000 01010 ..... ..... ..... @fff | |
| 326 | fdiv_s 0000 00010000 01101 ..... ..... ..... @fff | |
| 327 | fdiv_d 0000 00010000 01110 ..... ..... ..... @fff | |
| 328 | fmadd_s 0000 10000001 ..... ..... ..... ..... @ffff | |
| 329 | fmadd_d 0000 10000010 ..... ..... ..... ..... @ffff | |
| 330 | fmsub_s 0000 10000101 ..... ..... ..... ..... @ffff | |
| 331 | fmsub_d 0000 10000110 ..... ..... ..... ..... @ffff | |
| 332 | fnmadd_s 0000 10001001 ..... ..... ..... ..... @ffff | |
| 333 | fnmadd_d 0000 10001010 ..... ..... ..... ..... @ffff | |
| 334 | fnmsub_s 0000 10001101 ..... ..... ..... ..... @ffff | |
| 335 | fnmsub_d 0000 10001110 ..... ..... ..... ..... @ffff | |
| 336 | fmax_s 0000 00010000 10001 ..... ..... ..... @fff | |
| 337 | fmax_d 0000 00010000 10010 ..... ..... ..... @fff | |
| 338 | fmin_s 0000 00010000 10101 ..... ..... ..... @fff | |
| 339 | fmin_d 0000 00010000 10110 ..... ..... ..... @fff | |
| 340 | fmaxa_s 0000 00010000 11001 ..... ..... ..... @fff | |
| 341 | fmaxa_d 0000 00010000 11010 ..... ..... ..... @fff | |
| 342 | fmina_s 0000 00010000 11101 ..... ..... ..... @fff | |
| 343 | fmina_d 0000 00010000 11110 ..... ..... ..... @fff | |
| 344 | fabs_s 0000 00010001 01000 00001 ..... ..... @ff | |
| 345 | fabs_d 0000 00010001 01000 00010 ..... ..... @ff | |
| 346 | fneg_s 0000 00010001 01000 00101 ..... ..... @ff | |
| 347 | fneg_d 0000 00010001 01000 00110 ..... ..... @ff | |
| 348 | fsqrt_s 0000 00010001 01000 10001 ..... ..... @ff | |
| 349 | fsqrt_d 0000 00010001 01000 10010 ..... ..... @ff | |
| 350 | frecip_s 0000 00010001 01000 10101 ..... ..... @ff | |
| 351 | frecip_d 0000 00010001 01000 10110 ..... ..... @ff | |
| 352 | frsqrt_s 0000 00010001 01000 11001 ..... ..... @ff | |
| 353 | frsqrt_d 0000 00010001 01000 11010 ..... ..... @ff | |
| 354 | fscaleb_s 0000 00010001 00001 ..... ..... ..... @fff | |
| 355 | fscaleb_d 0000 00010001 00010 ..... ..... ..... @fff | |
| 356 | flogb_s 0000 00010001 01000 01001 ..... ..... @ff | |
| 357 | flogb_d 0000 00010001 01000 01010 ..... ..... @ff | |
| 358 | fcopysign_s 0000 00010001 00101 ..... ..... ..... @fff | |
| 359 | fcopysign_d 0000 00010001 00110 ..... ..... ..... @fff | |
| 360 | fclass_s 0000 00010001 01000 01101 ..... ..... @ff | |
| 361 | fclass_d 0000 00010001 01000 01110 ..... ..... @ff | |
| 9b741076 SG |
362 | |
| 363 | # | |
| 364 | # Floating point compare instruction | |
| 365 | # | |
| 366 | fcmp_cond_s 0000 11000001 ..... ..... ..... 00 ... @cff_fcond | |
| 367 | fcmp_cond_d 0000 11000010 ..... ..... ..... 00 ... @cff_fcond | |
| 7c1f8870 SG |
368 | |
| 369 | # | |
| 370 | # Floating point conversion instruction | |
| 371 | # | |
| 372 | fcvt_s_d 0000 00010001 10010 00110 ..... ..... @ff | |
| 373 | fcvt_d_s 0000 00010001 10010 01001 ..... ..... @ff | |
| 374 | ftintrm_w_s 0000 00010001 10100 00001 ..... ..... @ff | |
| 375 | ftintrm_w_d 0000 00010001 10100 00010 ..... ..... @ff | |
| 376 | ftintrm_l_s 0000 00010001 10100 01001 ..... ..... @ff | |
| 377 | ftintrm_l_d 0000 00010001 10100 01010 ..... ..... @ff | |
| 378 | ftintrp_w_s 0000 00010001 10100 10001 ..... ..... @ff | |
| 379 | ftintrp_w_d 0000 00010001 10100 10010 ..... ..... @ff | |
| 380 | ftintrp_l_s 0000 00010001 10100 11001 ..... ..... @ff | |
| 381 | ftintrp_l_d 0000 00010001 10100 11010 ..... ..... @ff | |
| 382 | ftintrz_w_s 0000 00010001 10101 00001 ..... ..... @ff | |
| 383 | ftintrz_w_d 0000 00010001 10101 00010 ..... ..... @ff | |
| 384 | ftintrz_l_s 0000 00010001 10101 01001 ..... ..... @ff | |
| 385 | ftintrz_l_d 0000 00010001 10101 01010 ..... ..... @ff | |
| 386 | ftintrne_w_s 0000 00010001 10101 10001 ..... ..... @ff | |
| 387 | ftintrne_w_d 0000 00010001 10101 10010 ..... ..... @ff | |
| 388 | ftintrne_l_s 0000 00010001 10101 11001 ..... ..... @ff | |
| 389 | ftintrne_l_d 0000 00010001 10101 11010 ..... ..... @ff | |
| 390 | ftint_w_s 0000 00010001 10110 00001 ..... ..... @ff | |
| 391 | ftint_w_d 0000 00010001 10110 00010 ..... ..... @ff | |
| 392 | ftint_l_s 0000 00010001 10110 01001 ..... ..... @ff | |
| 393 | ftint_l_d 0000 00010001 10110 01010 ..... ..... @ff | |
| 394 | ffint_s_w 0000 00010001 11010 00100 ..... ..... @ff | |
| 395 | ffint_s_l 0000 00010001 11010 00110 ..... ..... @ff | |
| 396 | ffint_d_w 0000 00010001 11010 01000 ..... ..... @ff | |
| 397 | ffint_d_l 0000 00010001 11010 01010 ..... ..... @ff | |
| 398 | frint_s 0000 00010001 11100 10001 ..... ..... @ff | |
| 399 | frint_d 0000 00010001 11100 10010 ..... ..... @ff | |
| b7dabd56 SG |
400 | |
| 401 | # | |
| 402 | # Floating point move instruction | |
| 403 | # | |
| 404 | fmov_s 0000 00010001 01001 00101 ..... ..... @ff | |
| 405 | fmov_d 0000 00010001 01001 00110 ..... ..... @ff | |
| 406 | fsel 0000 11010000 00 ... ..... ..... ..... @fffc | |
| 407 | movgr2fr_w 0000 00010001 01001 01001 ..... ..... @fr | |
| 408 | movgr2fr_d 0000 00010001 01001 01010 ..... ..... @fr | |
| 409 | movgr2frh_w 0000 00010001 01001 01011 ..... ..... @fr | |
| 410 | movfr2gr_s 0000 00010001 01001 01101 ..... ..... @rf | |
| 411 | movfr2gr_d 0000 00010001 01001 01110 ..... ..... @rf | |
| 412 | movfrh2gr_s 0000 00010001 01001 01111 ..... ..... @rf | |
| 413 | movgr2fcsr 0000 00010001 01001 10000 ..... ..... @fcsrd_r | |
| 414 | movfcsr2gr 0000 00010001 01001 10010 ..... ..... @r_fcsrs | |
| 415 | movfr2cf 0000 00010001 01001 10100 ..... 00 ... @cf | |
| 416 | movcf2fr 0000 00010001 01001 10101 00 ... ..... @fc | |
| 417 | movgr2cf 0000 00010001 01001 10110 ..... 00 ... @cr | |
| 418 | movcf2gr 0000 00010001 01001 10111 00 ... ..... @rc | |
| e616bdfd SG |
419 | |
| 420 | # | |
| 421 | # Floating point load/store instruction | |
| 422 | # | |
| 423 | fld_s 0010 101100 ............ ..... ..... @fr_i12 | |
| 424 | fst_s 0010 101101 ............ ..... ..... @fr_i12 | |
| 425 | fld_d 0010 101110 ............ ..... ..... @fr_i12 | |
| 426 | fst_d 0010 101111 ............ ..... ..... @fr_i12 | |
| 427 | fldx_s 0011 10000011 00000 ..... ..... ..... @frr | |
| 428 | fldx_d 0011 10000011 01000 ..... ..... ..... @frr | |
| 429 | fstx_s 0011 10000011 10000 ..... ..... ..... @frr | |
| 430 | fstx_d 0011 10000011 11000 ..... ..... ..... @frr | |
| 431 | fldgt_s 0011 10000111 01000 ..... ..... ..... @frr | |
| 432 | fldgt_d 0011 10000111 01001 ..... ..... ..... @frr | |
| 433 | fldle_s 0011 10000111 01010 ..... ..... ..... @frr | |
| 434 | fldle_d 0011 10000111 01011 ..... ..... ..... @frr | |
| 435 | fstgt_s 0011 10000111 01100 ..... ..... ..... @frr | |
| 436 | fstgt_d 0011 10000111 01101 ..... ..... ..... @frr | |
| 437 | fstle_s 0011 10000111 01110 ..... ..... ..... @frr | |
| 438 | fstle_d 0011 10000111 01111 ..... ..... ..... @frr | |
| ee86bd58 SG |
439 | |
| 440 | # | |
| 441 | # Branch instructions | |
| 442 | # | |
| 443 | beqz 0100 00 ................ ..... ..... @r_offs21 | |
| 444 | bnez 0100 01 ................ ..... ..... @r_offs21 | |
| 445 | bceqz 0100 10 ................ 00 ... ..... @c_offs21 | |
| 446 | bcnez 0100 10 ................ 01 ... ..... @c_offs21 | |
| 447 | jirl 0100 11 ................ ..... ..... @rr_offs16 | |
| 448 | b 0101 00 .......................... @offs26 | |
| 449 | bl 0101 01 .......................... @offs26 | |
| 450 | beq 0101 10 ................ ..... ..... @rr_offs16 | |
| 451 | bne 0101 11 ................ ..... ..... @rr_offs16 | |
| 452 | blt 0110 00 ................ ..... ..... @rr_offs16 | |
| 453 | bge 0110 01 ................ ..... ..... @rr_offs16 | |
| 454 | bltu 0110 10 ................ ..... ..... @rr_offs16 | |
| 455 | bgeu 0110 11 ................ ..... ..... @rr_offs16 | |
| 5b1dedfe XY |
456 | |
| 457 | # | |
| 458 | # Core instructions | |
| 459 | # | |
| 460 | { | |
| 461 | csrrd 0000 0100 .............. 00000 ..... @r_csr | |
| 462 | csrwr 0000 0100 .............. 00001 ..... @r_csr | |
| 463 | csrxchg 0000 0100 .............. ..... ..... @rr_csr | |
| 464 | } | |
| f84a2aac XY |
465 | |
| 466 | iocsrrd_b 0000 01100100 10000 00000 ..... ..... @rr | |
| 467 | iocsrrd_h 0000 01100100 10000 00001 ..... ..... @rr | |
| 468 | iocsrrd_w 0000 01100100 10000 00010 ..... ..... @rr | |
| 469 | iocsrrd_d 0000 01100100 10000 00011 ..... ..... @rr | |
| 470 | iocsrwr_b 0000 01100100 10000 00100 ..... ..... @rr | |
| 471 | iocsrwr_h 0000 01100100 10000 00101 ..... ..... @rr | |
| 472 | iocsrwr_w 0000 01100100 10000 00110 ..... ..... @rr | |
| 473 | iocsrwr_d 0000 01100100 10000 00111 ..... ..... @rr | |
| fcbbeb8e XY |
474 | tlbsrch 0000 01100100 10000 01010 00000 00000 @empty |
| 475 | tlbrd 0000 01100100 10000 01011 00000 00000 @empty | |
| 476 | tlbwr 0000 01100100 10000 01100 00000 00000 @empty | |
| 477 | tlbfill 0000 01100100 10000 01101 00000 00000 @empty | |
| 478 | tlbclr 0000 01100100 10000 01000 00000 00000 @empty | |
| 479 | tlbflush 0000 01100100 10000 01001 00000 00000 @empty | |
| 480 | invtlb 0000 01100100 10011 ..... ..... ..... @i_rr | |
| d2cba6f7 XY |
481 | cacop 0000 011000 ............ ..... ..... @cop_r_i |
| 482 | lddir 0000 01100100 00 ........ ..... ..... @rr_ui8 | |
| 483 | ldpte 0000 01100100 01 ........ ..... 00000 @j_i | |
| 484 | ertn 0000 01100100 10000 01110 00000 00000 @empty | |
| 485 | idle 0000 01100100 10001 ............... @i15 | |
| 486 | dbcl 0000 00000010 10101 ............... @i15 |