projects / qemu.git / blame
| Commit | Line | Data |
|---|---|---|
| 143d6785 SG |
1 | # SPDX-License-Identifier: GPL-2.0-or-later |
| 2 | # | |
| 3 | # LoongArch instruction decode definitions. | |
| 4 | # | |
| 5 | # Copyright (c) 2021 Loongson Technology Corporation Limited | |
| 6 | # | |
| 7 | ||
| 8 | # | |
| 9 | # Fields | |
| 10 | # | |
| 11 | %sa2p1 15:2 !function=plus_1 | |
| 12 | ||
| 13 | # | |
| 14 | # Argument sets | |
| 15 | # | |
| 16 | &r_i rd imm | |
| 17 | &rrr rd rj rk | |
| 18 | &rr_i rd rj imm | |
| 19 | &rrr_sa rd rj rk sa | |
| 20 | ||
| 21 | # | |
| 22 | # Formats | |
| 23 | # | |
| 24 | @rrr .... ........ ..... rk:5 rj:5 rd:5 &rrr | |
| 25 | @r_i20 .... ... imm:s20 rd:5 &r_i | |
| 63cfcd47 SG |
26 | @rr_ui5 .... ........ ..... imm:5 rj:5 rd:5 &rr_i |
| 27 | @rr_ui6 .... ........ .... imm:6 rj:5 rd:5 &rr_i | |
| 143d6785 SG |
28 | @rr_i12 .... ...... imm:s12 rj:5 rd:5 &rr_i |
| 29 | @rr_ui12 .... ...... imm:12 rj:5 rd:5 &rr_i | |
| 30 | @rr_i16 .... .. imm:s16 rj:5 rd:5 &rr_i | |
| 31 | @rrr_sa2p1 .... ........ ... .. rk:5 rj:5 rd:5 &rrr_sa sa=%sa2p1 | |
| 32 | ||
| 33 | # | |
| 34 | # Fixed point arithmetic operation instruction | |
| 35 | # | |
| 36 | add_w 0000 00000001 00000 ..... ..... ..... @rrr | |
| 37 | add_d 0000 00000001 00001 ..... ..... ..... @rrr | |
| 38 | sub_w 0000 00000001 00010 ..... ..... ..... @rrr | |
| 39 | sub_d 0000 00000001 00011 ..... ..... ..... @rrr | |
| 40 | slt 0000 00000001 00100 ..... ..... ..... @rrr | |
| 41 | sltu 0000 00000001 00101 ..... ..... ..... @rrr | |
| 42 | slti 0000 001000 ............ ..... ..... @rr_i12 | |
| 43 | sltui 0000 001001 ............ ..... ..... @rr_i12 | |
| 44 | nor 0000 00000001 01000 ..... ..... ..... @rrr | |
| 45 | and 0000 00000001 01001 ..... ..... ..... @rrr | |
| 46 | or 0000 00000001 01010 ..... ..... ..... @rrr | |
| 47 | xor 0000 00000001 01011 ..... ..... ..... @rrr | |
| 48 | orn 0000 00000001 01100 ..... ..... ..... @rrr | |
| 49 | andn 0000 00000001 01101 ..... ..... ..... @rrr | |
| 50 | mul_w 0000 00000001 11000 ..... ..... ..... @rrr | |
| 51 | mulh_w 0000 00000001 11001 ..... ..... ..... @rrr | |
| 52 | mulh_wu 0000 00000001 11010 ..... ..... ..... @rrr | |
| 53 | mul_d 0000 00000001 11011 ..... ..... ..... @rrr | |
| 54 | mulh_d 0000 00000001 11100 ..... ..... ..... @rrr | |
| 55 | mulh_du 0000 00000001 11101 ..... ..... ..... @rrr | |
| 56 | mulw_d_w 0000 00000001 11110 ..... ..... ..... @rrr | |
| 57 | mulw_d_wu 0000 00000001 11111 ..... ..... ..... @rrr | |
| 58 | div_w 0000 00000010 00000 ..... ..... ..... @rrr | |
| 59 | mod_w 0000 00000010 00001 ..... ..... ..... @rrr | |
| 60 | div_wu 0000 00000010 00010 ..... ..... ..... @rrr | |
| 61 | mod_wu 0000 00000010 00011 ..... ..... ..... @rrr | |
| 62 | div_d 0000 00000010 00100 ..... ..... ..... @rrr | |
| 63 | mod_d 0000 00000010 00101 ..... ..... ..... @rrr | |
| 64 | div_du 0000 00000010 00110 ..... ..... ..... @rrr | |
| 65 | mod_du 0000 00000010 00111 ..... ..... ..... @rrr | |
| 66 | alsl_w 0000 00000000 010 .. ..... ..... ..... @rrr_sa2p1 | |
| 67 | alsl_wu 0000 00000000 011 .. ..... ..... ..... @rrr_sa2p1 | |
| 68 | alsl_d 0000 00000010 110 .. ..... ..... ..... @rrr_sa2p1 | |
| 69 | lu12i_w 0001 010 .................... ..... @r_i20 | |
| 70 | lu32i_d 0001 011 .................... ..... @r_i20 | |
| 71 | lu52i_d 0000 001100 ............ ..... ..... @rr_i12 | |
| 72 | pcaddi 0001 100 .................... ..... @r_i20 | |
| 73 | pcalau12i 0001 101 .................... ..... @r_i20 | |
| 74 | pcaddu12i 0001 110 .................... ..... @r_i20 | |
| 75 | pcaddu18i 0001 111 .................... ..... @r_i20 | |
| 76 | addi_w 0000 001010 ............ ..... ..... @rr_i12 | |
| 77 | addi_d 0000 001011 ............ ..... ..... @rr_i12 | |
| 78 | addu16i_d 0001 00 ................ ..... ..... @rr_i16 | |
| 79 | andi 0000 001101 ............ ..... ..... @rr_ui12 | |
| 80 | ori 0000 001110 ............ ..... ..... @rr_ui12 | |
| 81 | xori 0000 001111 ............ ..... ..... @rr_ui12 | |
| 63cfcd47 SG |
82 | |
| 83 | # | |
| 84 | # Fixed point shift operation instruction | |
| 85 | # | |
| 86 | sll_w 0000 00000001 01110 ..... ..... ..... @rrr | |
| 87 | srl_w 0000 00000001 01111 ..... ..... ..... @rrr | |
| 88 | sra_w 0000 00000001 10000 ..... ..... ..... @rrr | |
| 89 | sll_d 0000 00000001 10001 ..... ..... ..... @rrr | |
| 90 | srl_d 0000 00000001 10010 ..... ..... ..... @rrr | |
| 91 | sra_d 0000 00000001 10011 ..... ..... ..... @rrr | |
| 92 | rotr_w 0000 00000001 10110 ..... ..... ..... @rrr | |
| 93 | rotr_d 0000 00000001 10111 ..... ..... ..... @rrr | |
| 94 | slli_w 0000 00000100 00001 ..... ..... ..... @rr_ui5 | |
| 95 | slli_d 0000 00000100 0001 ...... ..... ..... @rr_ui6 | |
| 96 | srli_w 0000 00000100 01001 ..... ..... ..... @rr_ui5 | |
| 97 | srli_d 0000 00000100 0101 ...... ..... ..... @rr_ui6 | |
| 98 | srai_w 0000 00000100 10001 ..... ..... ..... @rr_ui5 | |
| 99 | srai_d 0000 00000100 1001 ...... ..... ..... @rr_ui6 | |
| 100 | rotri_w 0000 00000100 11001 ..... ..... ..... @rr_ui5 | |
| 101 | rotri_d 0000 00000100 1101 ...... ..... ..... @rr_ui6 |