projects / qemu.git / blame
| Commit | Line | Data |
|---|---|---|
| 143d6785 SG |
1 | # SPDX-License-Identifier: GPL-2.0-or-later |
| 2 | # | |
| 3 | # LoongArch instruction decode definitions. | |
| 4 | # | |
| 5 | # Copyright (c) 2021 Loongson Technology Corporation Limited | |
| 6 | # | |
| 7 | ||
| 8 | # | |
| 9 | # Fields | |
| 10 | # | |
| bb79174d | 11 | %i14s2 10:s14 !function=shl_2 |
| 143d6785 SG |
12 | %sa2p1 15:2 !function=plus_1 |
| 13 | ||
| 14 | # | |
| 15 | # Argument sets | |
| 16 | # | |
| bb79174d | 17 | &i imm |
| 143d6785 | 18 | &r_i rd imm |
| ad08cb3f | 19 | &rr rd rj |
| 8708a04a | 20 | &rr_jk rj rk |
| 143d6785 SG |
21 | &rrr rd rj rk |
| 22 | &rr_i rd rj imm | |
| bb79174d | 23 | &hint_r_i hint rj imm |
| 143d6785 | 24 | &rrr_sa rd rj rk sa |
| ad08cb3f | 25 | &rr_ms_ls rd rj ms ls |
| d578ca6c SG |
26 | &ff fd fj |
| 27 | &fff fd fj fk | |
| 28 | &ffff fd fj fk fa | |
| 9b741076 | 29 | &cff_fcond cd fj fk fcond |
| 143d6785 SG |
30 | |
| 31 | # | |
| 32 | # Formats | |
| 33 | # | |
| bb79174d | 34 | @i15 .... ........ ..... imm:15 &i |
| ad08cb3f | 35 | @rr .... ........ ..... ..... rj:5 rd:5 &rr |
| 8708a04a | 36 | @rr_jk .... ........ ..... rk:5 rj:5 ..... &rr_jk |
| 143d6785 SG |
37 | @rrr .... ........ ..... rk:5 rj:5 rd:5 &rrr |
| 38 | @r_i20 .... ... imm:s20 rd:5 &r_i | |
| 63cfcd47 SG |
39 | @rr_ui5 .... ........ ..... imm:5 rj:5 rd:5 &rr_i |
| 40 | @rr_ui6 .... ........ .... imm:6 rj:5 rd:5 &rr_i | |
| 143d6785 SG |
41 | @rr_i12 .... ...... imm:s12 rj:5 rd:5 &rr_i |
| 42 | @rr_ui12 .... ...... imm:12 rj:5 rd:5 &rr_i | |
| bb79174d | 43 | @rr_i14s2 .... .... .............. rj:5 rd:5 &rr_i imm=%i14s2 |
| 143d6785 | 44 | @rr_i16 .... .. imm:s16 rj:5 rd:5 &rr_i |
| bb79174d | 45 | @hint_r_i12 .... ...... imm:s12 rj:5 hint:5 &hint_r_i |
| 143d6785 | 46 | @rrr_sa2p1 .... ........ ... .. rk:5 rj:5 rd:5 &rrr_sa sa=%sa2p1 |
| ad08cb3f SG |
47 | @rrr_sa2 .... ........ ... sa:2 rk:5 rj:5 rd:5 &rrr_sa |
| 48 | @rrr_sa3 .... ........ .. sa:3 rk:5 rj:5 rd:5 &rrr_sa | |
| 49 | @rr_2bw .... ....... ms:5 . ls:5 rj:5 rd:5 &rr_ms_ls | |
| 50 | @rr_2bd .... ...... ms:6 ls:6 rj:5 rd:5 &rr_ms_ls | |
| d578ca6c SG |
51 | @ff .... ........ ..... ..... fj:5 fd:5 &ff |
| 52 | @fff .... ........ ..... fk:5 fj:5 fd:5 &fff | |
| 53 | @ffff .... ........ fa:5 fk:5 fj:5 fd:5 &ffff | |
| 9b741076 | 54 | @cff_fcond .... ........ fcond:5 fk:5 fj:5 .. cd:3 &cff_fcond |
| 143d6785 SG |
55 | |
| 56 | # | |
| 57 | # Fixed point arithmetic operation instruction | |
| 58 | # | |
| 59 | add_w 0000 00000001 00000 ..... ..... ..... @rrr | |
| 60 | add_d 0000 00000001 00001 ..... ..... ..... @rrr | |
| 61 | sub_w 0000 00000001 00010 ..... ..... ..... @rrr | |
| 62 | sub_d 0000 00000001 00011 ..... ..... ..... @rrr | |
| 63 | slt 0000 00000001 00100 ..... ..... ..... @rrr | |
| 64 | sltu 0000 00000001 00101 ..... ..... ..... @rrr | |
| 65 | slti 0000 001000 ............ ..... ..... @rr_i12 | |
| 66 | sltui 0000 001001 ............ ..... ..... @rr_i12 | |
| 67 | nor 0000 00000001 01000 ..... ..... ..... @rrr | |
| 68 | and 0000 00000001 01001 ..... ..... ..... @rrr | |
| 69 | or 0000 00000001 01010 ..... ..... ..... @rrr | |
| 70 | xor 0000 00000001 01011 ..... ..... ..... @rrr | |
| 71 | orn 0000 00000001 01100 ..... ..... ..... @rrr | |
| 72 | andn 0000 00000001 01101 ..... ..... ..... @rrr | |
| 73 | mul_w 0000 00000001 11000 ..... ..... ..... @rrr | |
| 74 | mulh_w 0000 00000001 11001 ..... ..... ..... @rrr | |
| 75 | mulh_wu 0000 00000001 11010 ..... ..... ..... @rrr | |
| 76 | mul_d 0000 00000001 11011 ..... ..... ..... @rrr | |
| 77 | mulh_d 0000 00000001 11100 ..... ..... ..... @rrr | |
| 78 | mulh_du 0000 00000001 11101 ..... ..... ..... @rrr | |
| 79 | mulw_d_w 0000 00000001 11110 ..... ..... ..... @rrr | |
| 80 | mulw_d_wu 0000 00000001 11111 ..... ..... ..... @rrr | |
| 81 | div_w 0000 00000010 00000 ..... ..... ..... @rrr | |
| 82 | mod_w 0000 00000010 00001 ..... ..... ..... @rrr | |
| 83 | div_wu 0000 00000010 00010 ..... ..... ..... @rrr | |
| 84 | mod_wu 0000 00000010 00011 ..... ..... ..... @rrr | |
| 85 | div_d 0000 00000010 00100 ..... ..... ..... @rrr | |
| 86 | mod_d 0000 00000010 00101 ..... ..... ..... @rrr | |
| 87 | div_du 0000 00000010 00110 ..... ..... ..... @rrr | |
| 88 | mod_du 0000 00000010 00111 ..... ..... ..... @rrr | |
| 89 | alsl_w 0000 00000000 010 .. ..... ..... ..... @rrr_sa2p1 | |
| 90 | alsl_wu 0000 00000000 011 .. ..... ..... ..... @rrr_sa2p1 | |
| 91 | alsl_d 0000 00000010 110 .. ..... ..... ..... @rrr_sa2p1 | |
| 92 | lu12i_w 0001 010 .................... ..... @r_i20 | |
| 93 | lu32i_d 0001 011 .................... ..... @r_i20 | |
| 94 | lu52i_d 0000 001100 ............ ..... ..... @rr_i12 | |
| 95 | pcaddi 0001 100 .................... ..... @r_i20 | |
| 96 | pcalau12i 0001 101 .................... ..... @r_i20 | |
| 97 | pcaddu12i 0001 110 .................... ..... @r_i20 | |
| 98 | pcaddu18i 0001 111 .................... ..... @r_i20 | |
| 99 | addi_w 0000 001010 ............ ..... ..... @rr_i12 | |
| 100 | addi_d 0000 001011 ............ ..... ..... @rr_i12 | |
| 101 | addu16i_d 0001 00 ................ ..... ..... @rr_i16 | |
| 102 | andi 0000 001101 ............ ..... ..... @rr_ui12 | |
| 103 | ori 0000 001110 ............ ..... ..... @rr_ui12 | |
| 104 | xori 0000 001111 ............ ..... ..... @rr_ui12 | |
| 63cfcd47 SG |
105 | |
| 106 | # | |
| 107 | # Fixed point shift operation instruction | |
| 108 | # | |
| 109 | sll_w 0000 00000001 01110 ..... ..... ..... @rrr | |
| 110 | srl_w 0000 00000001 01111 ..... ..... ..... @rrr | |
| 111 | sra_w 0000 00000001 10000 ..... ..... ..... @rrr | |
| 112 | sll_d 0000 00000001 10001 ..... ..... ..... @rrr | |
| 113 | srl_d 0000 00000001 10010 ..... ..... ..... @rrr | |
| 114 | sra_d 0000 00000001 10011 ..... ..... ..... @rrr | |
| 115 | rotr_w 0000 00000001 10110 ..... ..... ..... @rrr | |
| 116 | rotr_d 0000 00000001 10111 ..... ..... ..... @rrr | |
| 117 | slli_w 0000 00000100 00001 ..... ..... ..... @rr_ui5 | |
| 118 | slli_d 0000 00000100 0001 ...... ..... ..... @rr_ui6 | |
| 119 | srli_w 0000 00000100 01001 ..... ..... ..... @rr_ui5 | |
| 120 | srli_d 0000 00000100 0101 ...... ..... ..... @rr_ui6 | |
| 121 | srai_w 0000 00000100 10001 ..... ..... ..... @rr_ui5 | |
| 122 | srai_d 0000 00000100 1001 ...... ..... ..... @rr_ui6 | |
| 123 | rotri_w 0000 00000100 11001 ..... ..... ..... @rr_ui5 | |
| 124 | rotri_d 0000 00000100 1101 ...... ..... ..... @rr_ui6 | |
| ad08cb3f SG |
125 | |
| 126 | # | |
| 127 | # Fixed point bit operation instruction | |
| 128 | # | |
| 129 | ext_w_h 0000 00000000 00000 10110 ..... ..... @rr | |
| 130 | ext_w_b 0000 00000000 00000 10111 ..... ..... @rr | |
| 131 | clo_w 0000 00000000 00000 00100 ..... ..... @rr | |
| 132 | clz_w 0000 00000000 00000 00101 ..... ..... @rr | |
| 133 | cto_w 0000 00000000 00000 00110 ..... ..... @rr | |
| 134 | ctz_w 0000 00000000 00000 00111 ..... ..... @rr | |
| 135 | clo_d 0000 00000000 00000 01000 ..... ..... @rr | |
| 136 | clz_d 0000 00000000 00000 01001 ..... ..... @rr | |
| 137 | cto_d 0000 00000000 00000 01010 ..... ..... @rr | |
| 138 | ctz_d 0000 00000000 00000 01011 ..... ..... @rr | |
| 139 | revb_2h 0000 00000000 00000 01100 ..... ..... @rr | |
| 140 | revb_4h 0000 00000000 00000 01101 ..... ..... @rr | |
| 141 | revb_2w 0000 00000000 00000 01110 ..... ..... @rr | |
| 142 | revb_d 0000 00000000 00000 01111 ..... ..... @rr | |
| 143 | revh_2w 0000 00000000 00000 10000 ..... ..... @rr | |
| 144 | revh_d 0000 00000000 00000 10001 ..... ..... @rr | |
| 145 | bitrev_4b 0000 00000000 00000 10010 ..... ..... @rr | |
| 146 | bitrev_8b 0000 00000000 00000 10011 ..... ..... @rr | |
| 147 | bitrev_w 0000 00000000 00000 10100 ..... ..... @rr | |
| 148 | bitrev_d 0000 00000000 00000 10101 ..... ..... @rr | |
| 149 | bytepick_w 0000 00000000 100 .. ..... ..... ..... @rrr_sa2 | |
| 150 | bytepick_d 0000 00000000 11 ... ..... ..... ..... @rrr_sa3 | |
| 151 | maskeqz 0000 00000001 00110 ..... ..... ..... @rrr | |
| 152 | masknez 0000 00000001 00111 ..... ..... ..... @rrr | |
| 153 | bstrins_w 0000 0000011 ..... 0 ..... ..... ..... @rr_2bw | |
| 154 | bstrpick_w 0000 0000011 ..... 1 ..... ..... ..... @rr_2bw | |
| 155 | bstrins_d 0000 000010 ...... ...... ..... ..... @rr_2bd | |
| 156 | bstrpick_d 0000 000011 ...... ...... ..... ..... @rr_2bd | |
| bb79174d SG |
157 | |
| 158 | # | |
| 159 | # Fixed point load/store instruction | |
| 160 | # | |
| 161 | ld_b 0010 100000 ............ ..... ..... @rr_i12 | |
| 162 | ld_h 0010 100001 ............ ..... ..... @rr_i12 | |
| 163 | ld_w 0010 100010 ............ ..... ..... @rr_i12 | |
| 164 | ld_d 0010 100011 ............ ..... ..... @rr_i12 | |
| 165 | st_b 0010 100100 ............ ..... ..... @rr_i12 | |
| 166 | st_h 0010 100101 ............ ..... ..... @rr_i12 | |
| 167 | st_w 0010 100110 ............ ..... ..... @rr_i12 | |
| 168 | st_d 0010 100111 ............ ..... ..... @rr_i12 | |
| 169 | ld_bu 0010 101000 ............ ..... ..... @rr_i12 | |
| 170 | ld_hu 0010 101001 ............ ..... ..... @rr_i12 | |
| 171 | ld_wu 0010 101010 ............ ..... ..... @rr_i12 | |
| 172 | ldx_b 0011 10000000 00000 ..... ..... ..... @rrr | |
| 173 | ldx_h 0011 10000000 01000 ..... ..... ..... @rrr | |
| 174 | ldx_w 0011 10000000 10000 ..... ..... ..... @rrr | |
| 175 | ldx_d 0011 10000000 11000 ..... ..... ..... @rrr | |
| 176 | stx_b 0011 10000001 00000 ..... ..... ..... @rrr | |
| 177 | stx_h 0011 10000001 01000 ..... ..... ..... @rrr | |
| 178 | stx_w 0011 10000001 10000 ..... ..... ..... @rrr | |
| 179 | stx_d 0011 10000001 11000 ..... ..... ..... @rrr | |
| 180 | ldx_bu 0011 10000010 00000 ..... ..... ..... @rrr | |
| 181 | ldx_hu 0011 10000010 01000 ..... ..... ..... @rrr | |
| 182 | ldx_wu 0011 10000010 10000 ..... ..... ..... @rrr | |
| 183 | preld 0010 101011 ............ ..... ..... @hint_r_i12 | |
| 184 | dbar 0011 10000111 00100 ............... @i15 | |
| 185 | ibar 0011 10000111 00101 ............... @i15 | |
| 186 | ldptr_w 0010 0100 .............. ..... ..... @rr_i14s2 | |
| 187 | stptr_w 0010 0101 .............. ..... ..... @rr_i14s2 | |
| 188 | ldptr_d 0010 0110 .............. ..... ..... @rr_i14s2 | |
| 189 | stptr_d 0010 0111 .............. ..... ..... @rr_i14s2 | |
| 190 | ldgt_b 0011 10000111 10000 ..... ..... ..... @rrr | |
| 191 | ldgt_h 0011 10000111 10001 ..... ..... ..... @rrr | |
| 192 | ldgt_w 0011 10000111 10010 ..... ..... ..... @rrr | |
| 193 | ldgt_d 0011 10000111 10011 ..... ..... ..... @rrr | |
| 194 | ldle_b 0011 10000111 10100 ..... ..... ..... @rrr | |
| 195 | ldle_h 0011 10000111 10101 ..... ..... ..... @rrr | |
| 196 | ldle_w 0011 10000111 10110 ..... ..... ..... @rrr | |
| 197 | ldle_d 0011 10000111 10111 ..... ..... ..... @rrr | |
| 198 | stgt_b 0011 10000111 11000 ..... ..... ..... @rrr | |
| 199 | stgt_h 0011 10000111 11001 ..... ..... ..... @rrr | |
| 200 | stgt_w 0011 10000111 11010 ..... ..... ..... @rrr | |
| 201 | stgt_d 0011 10000111 11011 ..... ..... ..... @rrr | |
| 202 | stle_b 0011 10000111 11100 ..... ..... ..... @rrr | |
| 203 | stle_h 0011 10000111 11101 ..... ..... ..... @rrr | |
| 204 | stle_w 0011 10000111 11110 ..... ..... ..... @rrr | |
| 205 | stle_d 0011 10000111 11111 ..... ..... ..... @rrr | |
| 94b02d57 SG |
206 | |
| 207 | # | |
| 208 | # Fixed point atomic instruction | |
| 209 | # | |
| 210 | ll_w 0010 0000 .............. ..... ..... @rr_i14s2 | |
| 211 | sc_w 0010 0001 .............. ..... ..... @rr_i14s2 | |
| 212 | ll_d 0010 0010 .............. ..... ..... @rr_i14s2 | |
| 213 | sc_d 0010 0011 .............. ..... ..... @rr_i14s2 | |
| 214 | amswap_w 0011 10000110 00000 ..... ..... ..... @rrr | |
| 215 | amswap_d 0011 10000110 00001 ..... ..... ..... @rrr | |
| 216 | amadd_w 0011 10000110 00010 ..... ..... ..... @rrr | |
| 217 | amadd_d 0011 10000110 00011 ..... ..... ..... @rrr | |
| 218 | amand_w 0011 10000110 00100 ..... ..... ..... @rrr | |
| 219 | amand_d 0011 10000110 00101 ..... ..... ..... @rrr | |
| 220 | amor_w 0011 10000110 00110 ..... ..... ..... @rrr | |
| 221 | amor_d 0011 10000110 00111 ..... ..... ..... @rrr | |
| 222 | amxor_w 0011 10000110 01000 ..... ..... ..... @rrr | |
| 223 | amxor_d 0011 10000110 01001 ..... ..... ..... @rrr | |
| 224 | ammax_w 0011 10000110 01010 ..... ..... ..... @rrr | |
| 225 | ammax_d 0011 10000110 01011 ..... ..... ..... @rrr | |
| 226 | ammin_w 0011 10000110 01100 ..... ..... ..... @rrr | |
| 227 | ammin_d 0011 10000110 01101 ..... ..... ..... @rrr | |
| 228 | ammax_wu 0011 10000110 01110 ..... ..... ..... @rrr | |
| 229 | ammax_du 0011 10000110 01111 ..... ..... ..... @rrr | |
| 230 | ammin_wu 0011 10000110 10000 ..... ..... ..... @rrr | |
| 231 | ammin_du 0011 10000110 10001 ..... ..... ..... @rrr | |
| 232 | amswap_db_w 0011 10000110 10010 ..... ..... ..... @rrr | |
| 233 | amswap_db_d 0011 10000110 10011 ..... ..... ..... @rrr | |
| 234 | amadd_db_w 0011 10000110 10100 ..... ..... ..... @rrr | |
| 235 | amadd_db_d 0011 10000110 10101 ..... ..... ..... @rrr | |
| 236 | amand_db_w 0011 10000110 10110 ..... ..... ..... @rrr | |
| 237 | amand_db_d 0011 10000110 10111 ..... ..... ..... @rrr | |
| 238 | amor_db_w 0011 10000110 11000 ..... ..... ..... @rrr | |
| 239 | amor_db_d 0011 10000110 11001 ..... ..... ..... @rrr | |
| 240 | amxor_db_w 0011 10000110 11010 ..... ..... ..... @rrr | |
| 241 | amxor_db_d 0011 10000110 11011 ..... ..... ..... @rrr | |
| 242 | ammax_db_w 0011 10000110 11100 ..... ..... ..... @rrr | |
| 243 | ammax_db_d 0011 10000110 11101 ..... ..... ..... @rrr | |
| 244 | ammin_db_w 0011 10000110 11110 ..... ..... ..... @rrr | |
| 245 | ammin_db_d 0011 10000110 11111 ..... ..... ..... @rrr | |
| 246 | ammax_db_wu 0011 10000111 00000 ..... ..... ..... @rrr | |
| 247 | ammax_db_du 0011 10000111 00001 ..... ..... ..... @rrr | |
| 248 | ammin_db_wu 0011 10000111 00010 ..... ..... ..... @rrr | |
| 249 | ammin_db_du 0011 10000111 00011 ..... ..... ..... @rrr | |
| 8708a04a SG |
250 | |
| 251 | # | |
| 252 | # Fixed point extra instruction | |
| 253 | # | |
| 254 | crc_w_b_w 0000 00000010 01000 ..... ..... ..... @rrr | |
| 255 | crc_w_h_w 0000 00000010 01001 ..... ..... ..... @rrr | |
| 256 | crc_w_w_w 0000 00000010 01010 ..... ..... ..... @rrr | |
| 257 | crc_w_d_w 0000 00000010 01011 ..... ..... ..... @rrr | |
| 258 | crcc_w_b_w 0000 00000010 01100 ..... ..... ..... @rrr | |
| 259 | crcc_w_h_w 0000 00000010 01101 ..... ..... ..... @rrr | |
| 260 | crcc_w_w_w 0000 00000010 01110 ..... ..... ..... @rrr | |
| 261 | crcc_w_d_w 0000 00000010 01111 ..... ..... ..... @rrr | |
| 262 | break 0000 00000010 10100 ............... @i15 | |
| 263 | syscall 0000 00000010 10110 ............... @i15 | |
| 264 | asrtle_d 0000 00000000 00010 ..... ..... 00000 @rr_jk | |
| 265 | asrtgt_d 0000 00000000 00011 ..... ..... 00000 @rr_jk | |
| 266 | cpucfg 0000 00000000 00000 11011 ..... ..... @rr | |
| d578ca6c SG |
267 | |
| 268 | # | |
| 269 | # Floating point arithmetic operation instruction | |
| 270 | # | |
| 271 | fadd_s 0000 00010000 00001 ..... ..... ..... @fff | |
| 272 | fadd_d 0000 00010000 00010 ..... ..... ..... @fff | |
| 273 | fsub_s 0000 00010000 00101 ..... ..... ..... @fff | |
| 274 | fsub_d 0000 00010000 00110 ..... ..... ..... @fff | |
| 275 | fmul_s 0000 00010000 01001 ..... ..... ..... @fff | |
| 276 | fmul_d 0000 00010000 01010 ..... ..... ..... @fff | |
| 277 | fdiv_s 0000 00010000 01101 ..... ..... ..... @fff | |
| 278 | fdiv_d 0000 00010000 01110 ..... ..... ..... @fff | |
| 279 | fmadd_s 0000 10000001 ..... ..... ..... ..... @ffff | |
| 280 | fmadd_d 0000 10000010 ..... ..... ..... ..... @ffff | |
| 281 | fmsub_s 0000 10000101 ..... ..... ..... ..... @ffff | |
| 282 | fmsub_d 0000 10000110 ..... ..... ..... ..... @ffff | |
| 283 | fnmadd_s 0000 10001001 ..... ..... ..... ..... @ffff | |
| 284 | fnmadd_d 0000 10001010 ..... ..... ..... ..... @ffff | |
| 285 | fnmsub_s 0000 10001101 ..... ..... ..... ..... @ffff | |
| 286 | fnmsub_d 0000 10001110 ..... ..... ..... ..... @ffff | |
| 287 | fmax_s 0000 00010000 10001 ..... ..... ..... @fff | |
| 288 | fmax_d 0000 00010000 10010 ..... ..... ..... @fff | |
| 289 | fmin_s 0000 00010000 10101 ..... ..... ..... @fff | |
| 290 | fmin_d 0000 00010000 10110 ..... ..... ..... @fff | |
| 291 | fmaxa_s 0000 00010000 11001 ..... ..... ..... @fff | |
| 292 | fmaxa_d 0000 00010000 11010 ..... ..... ..... @fff | |
| 293 | fmina_s 0000 00010000 11101 ..... ..... ..... @fff | |
| 294 | fmina_d 0000 00010000 11110 ..... ..... ..... @fff | |
| 295 | fabs_s 0000 00010001 01000 00001 ..... ..... @ff | |
| 296 | fabs_d 0000 00010001 01000 00010 ..... ..... @ff | |
| 297 | fneg_s 0000 00010001 01000 00101 ..... ..... @ff | |
| 298 | fneg_d 0000 00010001 01000 00110 ..... ..... @ff | |
| 299 | fsqrt_s 0000 00010001 01000 10001 ..... ..... @ff | |
| 300 | fsqrt_d 0000 00010001 01000 10010 ..... ..... @ff | |
| 301 | frecip_s 0000 00010001 01000 10101 ..... ..... @ff | |
| 302 | frecip_d 0000 00010001 01000 10110 ..... ..... @ff | |
| 303 | frsqrt_s 0000 00010001 01000 11001 ..... ..... @ff | |
| 304 | frsqrt_d 0000 00010001 01000 11010 ..... ..... @ff | |
| 305 | fscaleb_s 0000 00010001 00001 ..... ..... ..... @fff | |
| 306 | fscaleb_d 0000 00010001 00010 ..... ..... ..... @fff | |
| 307 | flogb_s 0000 00010001 01000 01001 ..... ..... @ff | |
| 308 | flogb_d 0000 00010001 01000 01010 ..... ..... @ff | |
| 309 | fcopysign_s 0000 00010001 00101 ..... ..... ..... @fff | |
| 310 | fcopysign_d 0000 00010001 00110 ..... ..... ..... @fff | |
| 311 | fclass_s 0000 00010001 01000 01101 ..... ..... @ff | |
| 312 | fclass_d 0000 00010001 01000 01110 ..... ..... @ff | |
| 9b741076 SG |
313 | |
| 314 | # | |
| 315 | # Floating point compare instruction | |
| 316 | # | |
| 317 | fcmp_cond_s 0000 11000001 ..... ..... ..... 00 ... @cff_fcond | |
| 318 | fcmp_cond_d 0000 11000010 ..... ..... ..... 00 ... @cff_fcond |