projects / qemu.git / blame
| Commit | Line | Data |
|---|---|---|
| 143d6785 SG |
1 | # SPDX-License-Identifier: GPL-2.0-or-later |
| 2 | # | |
| 3 | # LoongArch instruction decode definitions. | |
| 4 | # | |
| 5 | # Copyright (c) 2021 Loongson Technology Corporation Limited | |
| 6 | # | |
| 7 | ||
| 8 | # | |
| 9 | # Fields | |
| 10 | # | |
| bb79174d | 11 | %i14s2 10:s14 !function=shl_2 |
| 143d6785 SG |
12 | %sa2p1 15:2 !function=plus_1 |
| 13 | ||
| 14 | # | |
| 15 | # Argument sets | |
| 16 | # | |
| bb79174d | 17 | &i imm |
| 143d6785 | 18 | &r_i rd imm |
| ad08cb3f | 19 | &rr rd rj |
| 8708a04a | 20 | &rr_jk rj rk |
| 143d6785 SG |
21 | &rrr rd rj rk |
| 22 | &rr_i rd rj imm | |
| bb79174d | 23 | &hint_r_i hint rj imm |
| 143d6785 | 24 | &rrr_sa rd rj rk sa |
| ad08cb3f | 25 | &rr_ms_ls rd rj ms ls |
| d578ca6c SG |
26 | &ff fd fj |
| 27 | &fff fd fj fk | |
| 28 | &ffff fd fj fk fa | |
| 9b741076 | 29 | &cff_fcond cd fj fk fcond |
| b7dabd56 SG |
30 | &fffc fd fj fk ca |
| 31 | &fr fd rj | |
| 32 | &rf rd fj | |
| 33 | &fcsrd_r fcsrd rj | |
| 34 | &r_fcsrs rd fcsrs | |
| 35 | &cf cd fj | |
| 36 | &fc fd cj | |
| 37 | &cr cd rj | |
| 38 | &rc rd cj | |
| e616bdfd SG |
39 | &frr fd rj rk |
| 40 | &fr_i fd rj imm | |
| 143d6785 SG |
41 | |
| 42 | # | |
| 43 | # Formats | |
| 44 | # | |
| bb79174d | 45 | @i15 .... ........ ..... imm:15 &i |
| ad08cb3f | 46 | @rr .... ........ ..... ..... rj:5 rd:5 &rr |
| 8708a04a | 47 | @rr_jk .... ........ ..... rk:5 rj:5 ..... &rr_jk |
| 143d6785 SG |
48 | @rrr .... ........ ..... rk:5 rj:5 rd:5 &rrr |
| 49 | @r_i20 .... ... imm:s20 rd:5 &r_i | |
| 63cfcd47 SG |
50 | @rr_ui5 .... ........ ..... imm:5 rj:5 rd:5 &rr_i |
| 51 | @rr_ui6 .... ........ .... imm:6 rj:5 rd:5 &rr_i | |
| 143d6785 SG |
52 | @rr_i12 .... ...... imm:s12 rj:5 rd:5 &rr_i |
| 53 | @rr_ui12 .... ...... imm:12 rj:5 rd:5 &rr_i | |
| bb79174d | 54 | @rr_i14s2 .... .... .............. rj:5 rd:5 &rr_i imm=%i14s2 |
| 143d6785 | 55 | @rr_i16 .... .. imm:s16 rj:5 rd:5 &rr_i |
| bb79174d | 56 | @hint_r_i12 .... ...... imm:s12 rj:5 hint:5 &hint_r_i |
| 143d6785 | 57 | @rrr_sa2p1 .... ........ ... .. rk:5 rj:5 rd:5 &rrr_sa sa=%sa2p1 |
| ad08cb3f SG |
58 | @rrr_sa2 .... ........ ... sa:2 rk:5 rj:5 rd:5 &rrr_sa |
| 59 | @rrr_sa3 .... ........ .. sa:3 rk:5 rj:5 rd:5 &rrr_sa | |
| 60 | @rr_2bw .... ....... ms:5 . ls:5 rj:5 rd:5 &rr_ms_ls | |
| 61 | @rr_2bd .... ...... ms:6 ls:6 rj:5 rd:5 &rr_ms_ls | |
| d578ca6c SG |
62 | @ff .... ........ ..... ..... fj:5 fd:5 &ff |
| 63 | @fff .... ........ ..... fk:5 fj:5 fd:5 &fff | |
| 64 | @ffff .... ........ fa:5 fk:5 fj:5 fd:5 &ffff | |
| 9b741076 | 65 | @cff_fcond .... ........ fcond:5 fk:5 fj:5 .. cd:3 &cff_fcond |
| b7dabd56 SG |
66 | @fffc .... ........ .. ca:3 fk:5 fj:5 fd:5 &fffc |
| 67 | @fr .... ........ ..... ..... rj:5 fd:5 &fr | |
| 68 | @rf .... ........ ..... ..... fj:5 rd:5 &rf | |
| 69 | @fcsrd_r .... ........ ..... ..... rj:5 fcsrd:5 &fcsrd_r | |
| 70 | @r_fcsrs .... ........ ..... ..... fcsrs:5 rd:5 &r_fcsrs | |
| 71 | @cf .... ........ ..... ..... fj:5 .. cd:3 &cf | |
| 72 | @fc .... ........ ..... ..... .. cj:3 fd:5 &fc | |
| 73 | @cr .... ........ ..... ..... rj:5 .. cd:3 &cr | |
| 74 | @rc .... ........ ..... ..... .. cj:3 rd:5 &rc | |
| e616bdfd SG |
75 | @frr .... ........ ..... rk:5 rj:5 fd:5 &frr |
| 76 | @fr_i12 .... ...... imm:s12 rj:5 fd:5 &fr_i | |
| 143d6785 SG |
77 | |
| 78 | # | |
| 79 | # Fixed point arithmetic operation instruction | |
| 80 | # | |
| 81 | add_w 0000 00000001 00000 ..... ..... ..... @rrr | |
| 82 | add_d 0000 00000001 00001 ..... ..... ..... @rrr | |
| 83 | sub_w 0000 00000001 00010 ..... ..... ..... @rrr | |
| 84 | sub_d 0000 00000001 00011 ..... ..... ..... @rrr | |
| 85 | slt 0000 00000001 00100 ..... ..... ..... @rrr | |
| 86 | sltu 0000 00000001 00101 ..... ..... ..... @rrr | |
| 87 | slti 0000 001000 ............ ..... ..... @rr_i12 | |
| 88 | sltui 0000 001001 ............ ..... ..... @rr_i12 | |
| 89 | nor 0000 00000001 01000 ..... ..... ..... @rrr | |
| 90 | and 0000 00000001 01001 ..... ..... ..... @rrr | |
| 91 | or 0000 00000001 01010 ..... ..... ..... @rrr | |
| 92 | xor 0000 00000001 01011 ..... ..... ..... @rrr | |
| 93 | orn 0000 00000001 01100 ..... ..... ..... @rrr | |
| 94 | andn 0000 00000001 01101 ..... ..... ..... @rrr | |
| 95 | mul_w 0000 00000001 11000 ..... ..... ..... @rrr | |
| 96 | mulh_w 0000 00000001 11001 ..... ..... ..... @rrr | |
| 97 | mulh_wu 0000 00000001 11010 ..... ..... ..... @rrr | |
| 98 | mul_d 0000 00000001 11011 ..... ..... ..... @rrr | |
| 99 | mulh_d 0000 00000001 11100 ..... ..... ..... @rrr | |
| 100 | mulh_du 0000 00000001 11101 ..... ..... ..... @rrr | |
| 101 | mulw_d_w 0000 00000001 11110 ..... ..... ..... @rrr | |
| 102 | mulw_d_wu 0000 00000001 11111 ..... ..... ..... @rrr | |
| 103 | div_w 0000 00000010 00000 ..... ..... ..... @rrr | |
| 104 | mod_w 0000 00000010 00001 ..... ..... ..... @rrr | |
| 105 | div_wu 0000 00000010 00010 ..... ..... ..... @rrr | |
| 106 | mod_wu 0000 00000010 00011 ..... ..... ..... @rrr | |
| 107 | div_d 0000 00000010 00100 ..... ..... ..... @rrr | |
| 108 | mod_d 0000 00000010 00101 ..... ..... ..... @rrr | |
| 109 | div_du 0000 00000010 00110 ..... ..... ..... @rrr | |
| 110 | mod_du 0000 00000010 00111 ..... ..... ..... @rrr | |
| 111 | alsl_w 0000 00000000 010 .. ..... ..... ..... @rrr_sa2p1 | |
| 112 | alsl_wu 0000 00000000 011 .. ..... ..... ..... @rrr_sa2p1 | |
| 113 | alsl_d 0000 00000010 110 .. ..... ..... ..... @rrr_sa2p1 | |
| 114 | lu12i_w 0001 010 .................... ..... @r_i20 | |
| 115 | lu32i_d 0001 011 .................... ..... @r_i20 | |
| 116 | lu52i_d 0000 001100 ............ ..... ..... @rr_i12 | |
| 117 | pcaddi 0001 100 .................... ..... @r_i20 | |
| 118 | pcalau12i 0001 101 .................... ..... @r_i20 | |
| 119 | pcaddu12i 0001 110 .................... ..... @r_i20 | |
| 120 | pcaddu18i 0001 111 .................... ..... @r_i20 | |
| 121 | addi_w 0000 001010 ............ ..... ..... @rr_i12 | |
| 122 | addi_d 0000 001011 ............ ..... ..... @rr_i12 | |
| 123 | addu16i_d 0001 00 ................ ..... ..... @rr_i16 | |
| 124 | andi 0000 001101 ............ ..... ..... @rr_ui12 | |
| 125 | ori 0000 001110 ............ ..... ..... @rr_ui12 | |
| 126 | xori 0000 001111 ............ ..... ..... @rr_ui12 | |
| 63cfcd47 SG |
127 | |
| 128 | # | |
| 129 | # Fixed point shift operation instruction | |
| 130 | # | |
| 131 | sll_w 0000 00000001 01110 ..... ..... ..... @rrr | |
| 132 | srl_w 0000 00000001 01111 ..... ..... ..... @rrr | |
| 133 | sra_w 0000 00000001 10000 ..... ..... ..... @rrr | |
| 134 | sll_d 0000 00000001 10001 ..... ..... ..... @rrr | |
| 135 | srl_d 0000 00000001 10010 ..... ..... ..... @rrr | |
| 136 | sra_d 0000 00000001 10011 ..... ..... ..... @rrr | |
| 137 | rotr_w 0000 00000001 10110 ..... ..... ..... @rrr | |
| 138 | rotr_d 0000 00000001 10111 ..... ..... ..... @rrr | |
| 139 | slli_w 0000 00000100 00001 ..... ..... ..... @rr_ui5 | |
| 140 | slli_d 0000 00000100 0001 ...... ..... ..... @rr_ui6 | |
| 141 | srli_w 0000 00000100 01001 ..... ..... ..... @rr_ui5 | |
| 142 | srli_d 0000 00000100 0101 ...... ..... ..... @rr_ui6 | |
| 143 | srai_w 0000 00000100 10001 ..... ..... ..... @rr_ui5 | |
| 144 | srai_d 0000 00000100 1001 ...... ..... ..... @rr_ui6 | |
| 145 | rotri_w 0000 00000100 11001 ..... ..... ..... @rr_ui5 | |
| 146 | rotri_d 0000 00000100 1101 ...... ..... ..... @rr_ui6 | |
| ad08cb3f SG |
147 | |
| 148 | # | |
| 149 | # Fixed point bit operation instruction | |
| 150 | # | |
| 151 | ext_w_h 0000 00000000 00000 10110 ..... ..... @rr | |
| 152 | ext_w_b 0000 00000000 00000 10111 ..... ..... @rr | |
| 153 | clo_w 0000 00000000 00000 00100 ..... ..... @rr | |
| 154 | clz_w 0000 00000000 00000 00101 ..... ..... @rr | |
| 155 | cto_w 0000 00000000 00000 00110 ..... ..... @rr | |
| 156 | ctz_w 0000 00000000 00000 00111 ..... ..... @rr | |
| 157 | clo_d 0000 00000000 00000 01000 ..... ..... @rr | |
| 158 | clz_d 0000 00000000 00000 01001 ..... ..... @rr | |
| 159 | cto_d 0000 00000000 00000 01010 ..... ..... @rr | |
| 160 | ctz_d 0000 00000000 00000 01011 ..... ..... @rr | |
| 161 | revb_2h 0000 00000000 00000 01100 ..... ..... @rr | |
| 162 | revb_4h 0000 00000000 00000 01101 ..... ..... @rr | |
| 163 | revb_2w 0000 00000000 00000 01110 ..... ..... @rr | |
| 164 | revb_d 0000 00000000 00000 01111 ..... ..... @rr | |
| 165 | revh_2w 0000 00000000 00000 10000 ..... ..... @rr | |
| 166 | revh_d 0000 00000000 00000 10001 ..... ..... @rr | |
| 167 | bitrev_4b 0000 00000000 00000 10010 ..... ..... @rr | |
| 168 | bitrev_8b 0000 00000000 00000 10011 ..... ..... @rr | |
| 169 | bitrev_w 0000 00000000 00000 10100 ..... ..... @rr | |
| 170 | bitrev_d 0000 00000000 00000 10101 ..... ..... @rr | |
| 171 | bytepick_w 0000 00000000 100 .. ..... ..... ..... @rrr_sa2 | |
| 172 | bytepick_d 0000 00000000 11 ... ..... ..... ..... @rrr_sa3 | |
| 173 | maskeqz 0000 00000001 00110 ..... ..... ..... @rrr | |
| 174 | masknez 0000 00000001 00111 ..... ..... ..... @rrr | |
| 175 | bstrins_w 0000 0000011 ..... 0 ..... ..... ..... @rr_2bw | |
| 176 | bstrpick_w 0000 0000011 ..... 1 ..... ..... ..... @rr_2bw | |
| 177 | bstrins_d 0000 000010 ...... ...... ..... ..... @rr_2bd | |
| 178 | bstrpick_d 0000 000011 ...... ...... ..... ..... @rr_2bd | |
| bb79174d SG |
179 | |
| 180 | # | |
| 181 | # Fixed point load/store instruction | |
| 182 | # | |
| 183 | ld_b 0010 100000 ............ ..... ..... @rr_i12 | |
| 184 | ld_h 0010 100001 ............ ..... ..... @rr_i12 | |
| 185 | ld_w 0010 100010 ............ ..... ..... @rr_i12 | |
| 186 | ld_d 0010 100011 ............ ..... ..... @rr_i12 | |
| 187 | st_b 0010 100100 ............ ..... ..... @rr_i12 | |
| 188 | st_h 0010 100101 ............ ..... ..... @rr_i12 | |
| 189 | st_w 0010 100110 ............ ..... ..... @rr_i12 | |
| 190 | st_d 0010 100111 ............ ..... ..... @rr_i12 | |
| 191 | ld_bu 0010 101000 ............ ..... ..... @rr_i12 | |
| 192 | ld_hu 0010 101001 ............ ..... ..... @rr_i12 | |
| 193 | ld_wu 0010 101010 ............ ..... ..... @rr_i12 | |
| 194 | ldx_b 0011 10000000 00000 ..... ..... ..... @rrr | |
| 195 | ldx_h 0011 10000000 01000 ..... ..... ..... @rrr | |
| 196 | ldx_w 0011 10000000 10000 ..... ..... ..... @rrr | |
| 197 | ldx_d 0011 10000000 11000 ..... ..... ..... @rrr | |
| 198 | stx_b 0011 10000001 00000 ..... ..... ..... @rrr | |
| 199 | stx_h 0011 10000001 01000 ..... ..... ..... @rrr | |
| 200 | stx_w 0011 10000001 10000 ..... ..... ..... @rrr | |
| 201 | stx_d 0011 10000001 11000 ..... ..... ..... @rrr | |
| 202 | ldx_bu 0011 10000010 00000 ..... ..... ..... @rrr | |
| 203 | ldx_hu 0011 10000010 01000 ..... ..... ..... @rrr | |
| 204 | ldx_wu 0011 10000010 10000 ..... ..... ..... @rrr | |
| 205 | preld 0010 101011 ............ ..... ..... @hint_r_i12 | |
| 206 | dbar 0011 10000111 00100 ............... @i15 | |
| 207 | ibar 0011 10000111 00101 ............... @i15 | |
| 208 | ldptr_w 0010 0100 .............. ..... ..... @rr_i14s2 | |
| 209 | stptr_w 0010 0101 .............. ..... ..... @rr_i14s2 | |
| 210 | ldptr_d 0010 0110 .............. ..... ..... @rr_i14s2 | |
| 211 | stptr_d 0010 0111 .............. ..... ..... @rr_i14s2 | |
| 212 | ldgt_b 0011 10000111 10000 ..... ..... ..... @rrr | |
| 213 | ldgt_h 0011 10000111 10001 ..... ..... ..... @rrr | |
| 214 | ldgt_w 0011 10000111 10010 ..... ..... ..... @rrr | |
| 215 | ldgt_d 0011 10000111 10011 ..... ..... ..... @rrr | |
| 216 | ldle_b 0011 10000111 10100 ..... ..... ..... @rrr | |
| 217 | ldle_h 0011 10000111 10101 ..... ..... ..... @rrr | |
| 218 | ldle_w 0011 10000111 10110 ..... ..... ..... @rrr | |
| 219 | ldle_d 0011 10000111 10111 ..... ..... ..... @rrr | |
| 220 | stgt_b 0011 10000111 11000 ..... ..... ..... @rrr | |
| 221 | stgt_h 0011 10000111 11001 ..... ..... ..... @rrr | |
| 222 | stgt_w 0011 10000111 11010 ..... ..... ..... @rrr | |
| 223 | stgt_d 0011 10000111 11011 ..... ..... ..... @rrr | |
| 224 | stle_b 0011 10000111 11100 ..... ..... ..... @rrr | |
| 225 | stle_h 0011 10000111 11101 ..... ..... ..... @rrr | |
| 226 | stle_w 0011 10000111 11110 ..... ..... ..... @rrr | |
| 227 | stle_d 0011 10000111 11111 ..... ..... ..... @rrr | |
| 94b02d57 SG |
228 | |
| 229 | # | |
| 230 | # Fixed point atomic instruction | |
| 231 | # | |
| 232 | ll_w 0010 0000 .............. ..... ..... @rr_i14s2 | |
| 233 | sc_w 0010 0001 .............. ..... ..... @rr_i14s2 | |
| 234 | ll_d 0010 0010 .............. ..... ..... @rr_i14s2 | |
| 235 | sc_d 0010 0011 .............. ..... ..... @rr_i14s2 | |
| 236 | amswap_w 0011 10000110 00000 ..... ..... ..... @rrr | |
| 237 | amswap_d 0011 10000110 00001 ..... ..... ..... @rrr | |
| 238 | amadd_w 0011 10000110 00010 ..... ..... ..... @rrr | |
| 239 | amadd_d 0011 10000110 00011 ..... ..... ..... @rrr | |
| 240 | amand_w 0011 10000110 00100 ..... ..... ..... @rrr | |
| 241 | amand_d 0011 10000110 00101 ..... ..... ..... @rrr | |
| 242 | amor_w 0011 10000110 00110 ..... ..... ..... @rrr | |
| 243 | amor_d 0011 10000110 00111 ..... ..... ..... @rrr | |
| 244 | amxor_w 0011 10000110 01000 ..... ..... ..... @rrr | |
| 245 | amxor_d 0011 10000110 01001 ..... ..... ..... @rrr | |
| 246 | ammax_w 0011 10000110 01010 ..... ..... ..... @rrr | |
| 247 | ammax_d 0011 10000110 01011 ..... ..... ..... @rrr | |
| 248 | ammin_w 0011 10000110 01100 ..... ..... ..... @rrr | |
| 249 | ammin_d 0011 10000110 01101 ..... ..... ..... @rrr | |
| 250 | ammax_wu 0011 10000110 01110 ..... ..... ..... @rrr | |
| 251 | ammax_du 0011 10000110 01111 ..... ..... ..... @rrr | |
| 252 | ammin_wu 0011 10000110 10000 ..... ..... ..... @rrr | |
| 253 | ammin_du 0011 10000110 10001 ..... ..... ..... @rrr | |
| 254 | amswap_db_w 0011 10000110 10010 ..... ..... ..... @rrr | |
| 255 | amswap_db_d 0011 10000110 10011 ..... ..... ..... @rrr | |
| 256 | amadd_db_w 0011 10000110 10100 ..... ..... ..... @rrr | |
| 257 | amadd_db_d 0011 10000110 10101 ..... ..... ..... @rrr | |
| 258 | amand_db_w 0011 10000110 10110 ..... ..... ..... @rrr | |
| 259 | amand_db_d 0011 10000110 10111 ..... ..... ..... @rrr | |
| 260 | amor_db_w 0011 10000110 11000 ..... ..... ..... @rrr | |
| 261 | amor_db_d 0011 10000110 11001 ..... ..... ..... @rrr | |
| 262 | amxor_db_w 0011 10000110 11010 ..... ..... ..... @rrr | |
| 263 | amxor_db_d 0011 10000110 11011 ..... ..... ..... @rrr | |
| 264 | ammax_db_w 0011 10000110 11100 ..... ..... ..... @rrr | |
| 265 | ammax_db_d 0011 10000110 11101 ..... ..... ..... @rrr | |
| 266 | ammin_db_w 0011 10000110 11110 ..... ..... ..... @rrr | |
| 267 | ammin_db_d 0011 10000110 11111 ..... ..... ..... @rrr | |
| 268 | ammax_db_wu 0011 10000111 00000 ..... ..... ..... @rrr | |
| 269 | ammax_db_du 0011 10000111 00001 ..... ..... ..... @rrr | |
| 270 | ammin_db_wu 0011 10000111 00010 ..... ..... ..... @rrr | |
| 271 | ammin_db_du 0011 10000111 00011 ..... ..... ..... @rrr | |
| 8708a04a SG |
272 | |
| 273 | # | |
| 274 | # Fixed point extra instruction | |
| 275 | # | |
| 276 | crc_w_b_w 0000 00000010 01000 ..... ..... ..... @rrr | |
| 277 | crc_w_h_w 0000 00000010 01001 ..... ..... ..... @rrr | |
| 278 | crc_w_w_w 0000 00000010 01010 ..... ..... ..... @rrr | |
| 279 | crc_w_d_w 0000 00000010 01011 ..... ..... ..... @rrr | |
| 280 | crcc_w_b_w 0000 00000010 01100 ..... ..... ..... @rrr | |
| 281 | crcc_w_h_w 0000 00000010 01101 ..... ..... ..... @rrr | |
| 282 | crcc_w_w_w 0000 00000010 01110 ..... ..... ..... @rrr | |
| 283 | crcc_w_d_w 0000 00000010 01111 ..... ..... ..... @rrr | |
| 284 | break 0000 00000010 10100 ............... @i15 | |
| 285 | syscall 0000 00000010 10110 ............... @i15 | |
| 286 | asrtle_d 0000 00000000 00010 ..... ..... 00000 @rr_jk | |
| 287 | asrtgt_d 0000 00000000 00011 ..... ..... 00000 @rr_jk | |
| 288 | cpucfg 0000 00000000 00000 11011 ..... ..... @rr | |
| d578ca6c SG |
289 | |
| 290 | # | |
| 291 | # Floating point arithmetic operation instruction | |
| 292 | # | |
| 293 | fadd_s 0000 00010000 00001 ..... ..... ..... @fff | |
| 294 | fadd_d 0000 00010000 00010 ..... ..... ..... @fff | |
| 295 | fsub_s 0000 00010000 00101 ..... ..... ..... @fff | |
| 296 | fsub_d 0000 00010000 00110 ..... ..... ..... @fff | |
| 297 | fmul_s 0000 00010000 01001 ..... ..... ..... @fff | |
| 298 | fmul_d 0000 00010000 01010 ..... ..... ..... @fff | |
| 299 | fdiv_s 0000 00010000 01101 ..... ..... ..... @fff | |
| 300 | fdiv_d 0000 00010000 01110 ..... ..... ..... @fff | |
| 301 | fmadd_s 0000 10000001 ..... ..... ..... ..... @ffff | |
| 302 | fmadd_d 0000 10000010 ..... ..... ..... ..... @ffff | |
| 303 | fmsub_s 0000 10000101 ..... ..... ..... ..... @ffff | |
| 304 | fmsub_d 0000 10000110 ..... ..... ..... ..... @ffff | |
| 305 | fnmadd_s 0000 10001001 ..... ..... ..... ..... @ffff | |
| 306 | fnmadd_d 0000 10001010 ..... ..... ..... ..... @ffff | |
| 307 | fnmsub_s 0000 10001101 ..... ..... ..... ..... @ffff | |
| 308 | fnmsub_d 0000 10001110 ..... ..... ..... ..... @ffff | |
| 309 | fmax_s 0000 00010000 10001 ..... ..... ..... @fff | |
| 310 | fmax_d 0000 00010000 10010 ..... ..... ..... @fff | |
| 311 | fmin_s 0000 00010000 10101 ..... ..... ..... @fff | |
| 312 | fmin_d 0000 00010000 10110 ..... ..... ..... @fff | |
| 313 | fmaxa_s 0000 00010000 11001 ..... ..... ..... @fff | |
| 314 | fmaxa_d 0000 00010000 11010 ..... ..... ..... @fff | |
| 315 | fmina_s 0000 00010000 11101 ..... ..... ..... @fff | |
| 316 | fmina_d 0000 00010000 11110 ..... ..... ..... @fff | |
| 317 | fabs_s 0000 00010001 01000 00001 ..... ..... @ff | |
| 318 | fabs_d 0000 00010001 01000 00010 ..... ..... @ff | |
| 319 | fneg_s 0000 00010001 01000 00101 ..... ..... @ff | |
| 320 | fneg_d 0000 00010001 01000 00110 ..... ..... @ff | |
| 321 | fsqrt_s 0000 00010001 01000 10001 ..... ..... @ff | |
| 322 | fsqrt_d 0000 00010001 01000 10010 ..... ..... @ff | |
| 323 | frecip_s 0000 00010001 01000 10101 ..... ..... @ff | |
| 324 | frecip_d 0000 00010001 01000 10110 ..... ..... @ff | |
| 325 | frsqrt_s 0000 00010001 01000 11001 ..... ..... @ff | |
| 326 | frsqrt_d 0000 00010001 01000 11010 ..... ..... @ff | |
| 327 | fscaleb_s 0000 00010001 00001 ..... ..... ..... @fff | |
| 328 | fscaleb_d 0000 00010001 00010 ..... ..... ..... @fff | |
| 329 | flogb_s 0000 00010001 01000 01001 ..... ..... @ff | |
| 330 | flogb_d 0000 00010001 01000 01010 ..... ..... @ff | |
| 331 | fcopysign_s 0000 00010001 00101 ..... ..... ..... @fff | |
| 332 | fcopysign_d 0000 00010001 00110 ..... ..... ..... @fff | |
| 333 | fclass_s 0000 00010001 01000 01101 ..... ..... @ff | |
| 334 | fclass_d 0000 00010001 01000 01110 ..... ..... @ff | |
| 9b741076 SG |
335 | |
| 336 | # | |
| 337 | # Floating point compare instruction | |
| 338 | # | |
| 339 | fcmp_cond_s 0000 11000001 ..... ..... ..... 00 ... @cff_fcond | |
| 340 | fcmp_cond_d 0000 11000010 ..... ..... ..... 00 ... @cff_fcond | |
| 7c1f8870 SG |
341 | |
| 342 | # | |
| 343 | # Floating point conversion instruction | |
| 344 | # | |
| 345 | fcvt_s_d 0000 00010001 10010 00110 ..... ..... @ff | |
| 346 | fcvt_d_s 0000 00010001 10010 01001 ..... ..... @ff | |
| 347 | ftintrm_w_s 0000 00010001 10100 00001 ..... ..... @ff | |
| 348 | ftintrm_w_d 0000 00010001 10100 00010 ..... ..... @ff | |
| 349 | ftintrm_l_s 0000 00010001 10100 01001 ..... ..... @ff | |
| 350 | ftintrm_l_d 0000 00010001 10100 01010 ..... ..... @ff | |
| 351 | ftintrp_w_s 0000 00010001 10100 10001 ..... ..... @ff | |
| 352 | ftintrp_w_d 0000 00010001 10100 10010 ..... ..... @ff | |
| 353 | ftintrp_l_s 0000 00010001 10100 11001 ..... ..... @ff | |
| 354 | ftintrp_l_d 0000 00010001 10100 11010 ..... ..... @ff | |
| 355 | ftintrz_w_s 0000 00010001 10101 00001 ..... ..... @ff | |
| 356 | ftintrz_w_d 0000 00010001 10101 00010 ..... ..... @ff | |
| 357 | ftintrz_l_s 0000 00010001 10101 01001 ..... ..... @ff | |
| 358 | ftintrz_l_d 0000 00010001 10101 01010 ..... ..... @ff | |
| 359 | ftintrne_w_s 0000 00010001 10101 10001 ..... ..... @ff | |
| 360 | ftintrne_w_d 0000 00010001 10101 10010 ..... ..... @ff | |
| 361 | ftintrne_l_s 0000 00010001 10101 11001 ..... ..... @ff | |
| 362 | ftintrne_l_d 0000 00010001 10101 11010 ..... ..... @ff | |
| 363 | ftint_w_s 0000 00010001 10110 00001 ..... ..... @ff | |
| 364 | ftint_w_d 0000 00010001 10110 00010 ..... ..... @ff | |
| 365 | ftint_l_s 0000 00010001 10110 01001 ..... ..... @ff | |
| 366 | ftint_l_d 0000 00010001 10110 01010 ..... ..... @ff | |
| 367 | ffint_s_w 0000 00010001 11010 00100 ..... ..... @ff | |
| 368 | ffint_s_l 0000 00010001 11010 00110 ..... ..... @ff | |
| 369 | ffint_d_w 0000 00010001 11010 01000 ..... ..... @ff | |
| 370 | ffint_d_l 0000 00010001 11010 01010 ..... ..... @ff | |
| 371 | frint_s 0000 00010001 11100 10001 ..... ..... @ff | |
| 372 | frint_d 0000 00010001 11100 10010 ..... ..... @ff | |
| b7dabd56 SG |
373 | |
| 374 | # | |
| 375 | # Floating point move instruction | |
| 376 | # | |
| 377 | fmov_s 0000 00010001 01001 00101 ..... ..... @ff | |
| 378 | fmov_d 0000 00010001 01001 00110 ..... ..... @ff | |
| 379 | fsel 0000 11010000 00 ... ..... ..... ..... @fffc | |
| 380 | movgr2fr_w 0000 00010001 01001 01001 ..... ..... @fr | |
| 381 | movgr2fr_d 0000 00010001 01001 01010 ..... ..... @fr | |
| 382 | movgr2frh_w 0000 00010001 01001 01011 ..... ..... @fr | |
| 383 | movfr2gr_s 0000 00010001 01001 01101 ..... ..... @rf | |
| 384 | movfr2gr_d 0000 00010001 01001 01110 ..... ..... @rf | |
| 385 | movfrh2gr_s 0000 00010001 01001 01111 ..... ..... @rf | |
| 386 | movgr2fcsr 0000 00010001 01001 10000 ..... ..... @fcsrd_r | |
| 387 | movfcsr2gr 0000 00010001 01001 10010 ..... ..... @r_fcsrs | |
| 388 | movfr2cf 0000 00010001 01001 10100 ..... 00 ... @cf | |
| 389 | movcf2fr 0000 00010001 01001 10101 00 ... ..... @fc | |
| 390 | movgr2cf 0000 00010001 01001 10110 ..... 00 ... @cr | |
| 391 | movcf2gr 0000 00010001 01001 10111 00 ... ..... @rc | |
| e616bdfd SG |
392 | |
| 393 | # | |
| 394 | # Floating point load/store instruction | |
| 395 | # | |
| 396 | fld_s 0010 101100 ............ ..... ..... @fr_i12 | |
| 397 | fst_s 0010 101101 ............ ..... ..... @fr_i12 | |
| 398 | fld_d 0010 101110 ............ ..... ..... @fr_i12 | |
| 399 | fst_d 0010 101111 ............ ..... ..... @fr_i12 | |
| 400 | fldx_s 0011 10000011 00000 ..... ..... ..... @frr | |
| 401 | fldx_d 0011 10000011 01000 ..... ..... ..... @frr | |
| 402 | fstx_s 0011 10000011 10000 ..... ..... ..... @frr | |
| 403 | fstx_d 0011 10000011 11000 ..... ..... ..... @frr | |
| 404 | fldgt_s 0011 10000111 01000 ..... ..... ..... @frr | |
| 405 | fldgt_d 0011 10000111 01001 ..... ..... ..... @frr | |
| 406 | fldle_s 0011 10000111 01010 ..... ..... ..... @frr | |
| 407 | fldle_d 0011 10000111 01011 ..... ..... ..... @frr | |
| 408 | fstgt_s 0011 10000111 01100 ..... ..... ..... @frr | |
| 409 | fstgt_d 0011 10000111 01101 ..... ..... ..... @frr | |
| 410 | fstle_s 0011 10000111 01110 ..... ..... ..... @frr | |
| 411 | fstle_d 0011 10000111 01111 ..... ..... ..... @frr |