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linux-user, m68k: correctly manage SR in context
[qemu.git] / target / m68k / translate.c
CommitLineData
e6e5906b
PB		 1/*
2 * m68k translation
5fafdf24 3 *
0633879f 4 * Copyright (c) 2005-2007 CodeSourcery
e6e5906b
PB		 5 * Written by Paul Brook
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
8167ee88 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
e6e5906b 19 */
e6e5906b 20
d8416665 21#include "qemu/osdep.h"
e6e5906b 22#include "cpu.h"
76cad711 23#include "disas/disas.h"
63c91552 24#include "exec/exec-all.h"
57fec1fe 25#include "tcg-op.h"
1de7afc9 26#include "qemu/log.h"
f08b6170 27#include "exec/cpu_ldst.h"
77fc6f5e 28#include "exec/translator.h"
e1f3808e 29
2ef6175a
RH		 30#include "exec/helper-proto.h"
31#include "exec/helper-gen.h"
e6e5906b 32
a7e30d84 33#include "trace-tcg.h"
508127e2 34#include "exec/log.h"
a7e30d84 35
0633879f
PB		 36//#define DEBUG_DISPATCH 1
37
e1f3808e 38#define DEFO32(name, offset) static TCGv QREG_##name;
a7812ae4 39#define DEFO64(name, offset) static TCGv_i64 QREG_##name;
e1f3808e
PB		 40#include "qregs.def"
41#undef DEFO32
42#undef DEFO64
e1f3808e 43
259186a7 44static TCGv_i32 cpu_halted;
27103424 45static TCGv_i32 cpu_exception_index;
259186a7 46
f83311e4 47static char cpu_reg_names[2 * 8 * 3 + 5 * 4];
e1f3808e
PB		 48static TCGv cpu_dregs[8];
49static TCGv cpu_aregs[8];
a7812ae4 50static TCGv_i64 cpu_macc[4];
e1f3808e 51
8a1e52b6 52#define REG(insn, pos) (((insn) >> (pos)) & 7)
bcc098b0 53#define DREG(insn, pos) cpu_dregs[REG(insn, pos)]
8a1e52b6 54#define AREG(insn, pos) get_areg(s, REG(insn, pos))
8a1e52b6
RH		 55#define MACREG(acc) cpu_macc[acc]
56#define QREG_SP get_areg(s, 7)
e1f3808e
PB		 57
58static TCGv NULL_QREG;
11f4e8f8 59#define IS_NULL_QREG(t) (t == NULL_QREG)
e1f3808e
PB		 60/* Used to distinguish stores from bad addressing modes. */
61static TCGv store_dummy;
62
022c62cb 63#include "exec/gen-icount.h"
2e70f6ef 64
e1f3808e
PB		 65void m68k_tcg_init(void)
66{
67 char *p;
68 int i;
69
e1ccc054
RH		 70#define DEFO32(name, offset) \
71 QREG_##name = tcg_global_mem_new_i32(cpu_env, \
72 offsetof(CPUM68KState, offset), #name);
73#define DEFO64(name, offset) \
74 QREG_##name = tcg_global_mem_new_i64(cpu_env, \
75 offsetof(CPUM68KState, offset), #name);
e1f3808e
PB		 76#include "qregs.def"
77#undef DEFO32
78#undef DEFO64
e1f3808e 79
e1ccc054 80 cpu_halted = tcg_global_mem_new_i32(cpu_env,
259186a7
AF		 81 -offsetof(M68kCPU, env) +
82 offsetof(CPUState, halted), "HALTED");
e1ccc054 83 cpu_exception_index = tcg_global_mem_new_i32(cpu_env,
27103424
AF		 84 -offsetof(M68kCPU, env) +
85 offsetof(CPUState, exception_index),
86 "EXCEPTION");
259186a7 87
e1f3808e
PB		 88 p = cpu_reg_names;
89 for (i = 0; i < 8; i++) {
90 sprintf(p, "D%d", i);
e1ccc054 91 cpu_dregs[i] = tcg_global_mem_new(cpu_env,
e1f3808e
PB		 92 offsetof(CPUM68KState, dregs[i]), p);
93 p += 3;
94 sprintf(p, "A%d", i);
e1ccc054 95 cpu_aregs[i] = tcg_global_mem_new(cpu_env,
e1f3808e
PB		 96 offsetof(CPUM68KState, aregs[i]), p);
97 p += 3;
e1f3808e
PB		 98 }
99 for (i = 0; i < 4; i++) {
100 sprintf(p, "ACC%d", i);
e1ccc054 101 cpu_macc[i] = tcg_global_mem_new_i64(cpu_env,
e1f3808e
PB		 102 offsetof(CPUM68KState, macc[i]), p);
103 p += 5;
104 }
105
e1ccc054
RH		 106 NULL_QREG = tcg_global_mem_new(cpu_env, -4, "NULL");
107 store_dummy = tcg_global_mem_new(cpu_env, -8, "NULL");
e1f3808e
PB		 108}
109
e6e5906b
PB		 110/* internal defines */
111typedef struct DisasContext {
e6dbd3b3 112 CPUM68KState *env;
510ff0b7 113 target_ulong insn_pc; /* Start of the current instruction. */
e6e5906b
PB		 114 target_ulong pc;
115 int is_jmp;
9fdb533f 116 CCOp cc_op; /* Current CC operation */
620c6cf6 117 int cc_op_synced;
0633879f 118 int user;
e6e5906b
PB		 119 struct TranslationBlock *tb;
120 int singlestep_enabled;
a7812ae4
PB		 121 TCGv_i64 mactmp;
122 int done_mac;
8a1e52b6
RH		 123 int writeback_mask;
124 TCGv writeback[8];
e6e5906b
PB		 125} DisasContext;
126
8a1e52b6
RH		 127static TCGv get_areg(DisasContext *s, unsigned regno)
128{
129 if (s->writeback_mask & (1 << regno)) {
130 return s->writeback[regno];
131 } else {
132 return cpu_aregs[regno];
133 }
134}
135
136static void delay_set_areg(DisasContext *s, unsigned regno,
137 TCGv val, bool give_temp)
138{
139 if (s->writeback_mask & (1 << regno)) {
140 if (give_temp) {
141 tcg_temp_free(s->writeback[regno]);
142 s->writeback[regno] = val;
143 } else {
144 tcg_gen_mov_i32(s->writeback[regno], val);
145 }
146 } else {
147 s->writeback_mask |= 1 << regno;
148 if (give_temp) {
149 s->writeback[regno] = val;
150 } else {
151 TCGv tmp = tcg_temp_new();
152 s->writeback[regno] = tmp;
153 tcg_gen_mov_i32(tmp, val);
154 }
155 }
156}
157
158static void do_writebacks(DisasContext *s)
159{
160 unsigned mask = s->writeback_mask;
161 if (mask) {
162 s->writeback_mask = 0;
163 do {
164 unsigned regno = ctz32(mask);
165 tcg_gen_mov_i32(cpu_aregs[regno], s->writeback[regno]);
166 tcg_temp_free(s->writeback[regno]);
167 mask &= mask - 1;
168 } while (mask);
169 }
170}
171
77fc6f5e
LV		 172/* is_jmp field values */
173#define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */
174#define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamically */
175#define DISAS_TB_JUMP DISAS_TARGET_2 /* only pc was modified statically */
176#define DISAS_JUMP_NEXT DISAS_TARGET_3
e6e5906b 177
0633879f
PB		 178#if defined(CONFIG_USER_ONLY)
179#define IS_USER(s) 1
180#else
181#define IS_USER(s) s->user
182#endif
183
d4d79bb1 184typedef void (*disas_proc)(CPUM68KState *env, DisasContext *s, uint16_t insn);
e6e5906b 185
0633879f 186#ifdef DEBUG_DISPATCH
d4d79bb1
BS		 187#define DISAS_INSN(name) \
188 static void real_disas_##name(CPUM68KState *env, DisasContext *s, \
189 uint16_t insn); \
190 static void disas_##name(CPUM68KState *env, DisasContext *s, \
191 uint16_t insn) \
192 { \
193 qemu_log("Dispatch " #name "\n"); \
a1ff1930 194 real_disas_##name(env, s, insn); \
d4d79bb1
BS		 195 } \
196 static void real_disas_##name(CPUM68KState *env, DisasContext *s, \
197 uint16_t insn)
0633879f 198#else
d4d79bb1
BS		 199#define DISAS_INSN(name) \
200 static void disas_##name(CPUM68KState *env, DisasContext *s, \
201 uint16_t insn)
0633879f 202#endif
e6e5906b 203
9fdb533f 204static const uint8_t cc_op_live[CC_OP_NB] = {
7deddf96 205 [CC_OP_DYNAMIC] = CCF_C | CCF_V | CCF_Z | CCF_N | CCF_X,
620c6cf6 206 [CC_OP_FLAGS] = CCF_C | CCF_V | CCF_Z | CCF_N | CCF_X,
db3d7945
LV		 207 [CC_OP_ADDB ... CC_OP_ADDL] = CCF_X | CCF_N | CCF_V,
208 [CC_OP_SUBB ... CC_OP_SUBL] = CCF_X | CCF_N | CCF_V,
209 [CC_OP_CMPB ... CC_OP_CMPL] = CCF_X | CCF_N | CCF_V,
620c6cf6 210 [CC_OP_LOGIC] = CCF_X | CCF_N
9fdb533f
LV		 211};
212
213static void set_cc_op(DisasContext *s, CCOp op)
214{
620c6cf6 215 CCOp old_op = s->cc_op;
9fdb533f
LV		 216 int dead;
217
620c6cf6 218 if (old_op == op) {
9fdb533f
LV		 219 return;
220 }
620c6cf6
RH		 221 s->cc_op = op;
222 s->cc_op_synced = 0;
9fdb533f 223
620c6cf6
RH		 224 /* Discard CC computation that will no longer be used.
225 Note that X and N are never dead. */
226 dead = cc_op_live[old_op] & ~cc_op_live[op];
227 if (dead & CCF_C) {
228 tcg_gen_discard_i32(QREG_CC_C);
9fdb533f 229 }
620c6cf6
RH		 230 if (dead & CCF_Z) {
231 tcg_gen_discard_i32(QREG_CC_Z);
9fdb533f 232 }
620c6cf6
RH		 233 if (dead & CCF_V) {
234 tcg_gen_discard_i32(QREG_CC_V);
9fdb533f 235 }
9fdb533f
LV		 236}
237
238/* Update the CPU env CC_OP state. */
620c6cf6 239static void update_cc_op(DisasContext *s)
9fdb533f 240{
620c6cf6
RH		 241 if (!s->cc_op_synced) {
242 s->cc_op_synced = 1;
9fdb533f
LV		 243 tcg_gen_movi_i32(QREG_CC_OP, s->cc_op);
244 }
245}
246
f83311e4
LV		 247/* Generate a jump to an immediate address. */
248static void gen_jmp_im(DisasContext *s, uint32_t dest)
249{
250 update_cc_op(s);
251 tcg_gen_movi_i32(QREG_PC, dest);
252 s->is_jmp = DISAS_JUMP;
253}
254
255/* Generate a jump to the address in qreg DEST. */
256static void gen_jmp(DisasContext *s, TCGv dest)
257{
258 update_cc_op(s);
259 tcg_gen_mov_i32(QREG_PC, dest);
260 s->is_jmp = DISAS_JUMP;
261}
262
263static void gen_raise_exception(int nr)
264{
265 TCGv_i32 tmp = tcg_const_i32(nr);
266
267 gen_helper_raise_exception(cpu_env, tmp);
268 tcg_temp_free_i32(tmp);
269}
270
271static void gen_exception(DisasContext *s, uint32_t where, int nr)
272{
f83311e4
LV		 273 gen_jmp_im(s, where);
274 gen_raise_exception(nr);
275}
276
277static inline void gen_addr_fault(DisasContext *s)
278{
279 gen_exception(s, s->insn_pc, EXCP_ADDRESS);
280}
281
e6e5906b
PB		 282/* Generate a load from the specified address. Narrow values are
283 sign extended to full register width. */
e1f3808e 284static inline TCGv gen_load(DisasContext * s, int opsize, TCGv addr, int sign)
e6e5906b 285{
e1f3808e
PB		 286 TCGv tmp;
287 int index = IS_USER(s);
a7812ae4 288 tmp = tcg_temp_new_i32();
e6e5906b
PB		 289 switch(opsize) {
290 case OS_BYTE:
e6e5906b 291 if (sign)
e1f3808e 292 tcg_gen_qemu_ld8s(tmp, addr, index);
e6e5906b 293 else
e1f3808e 294 tcg_gen_qemu_ld8u(tmp, addr, index);
e6e5906b
PB		 295 break;
296 case OS_WORD:
e6e5906b 297 if (sign)
e1f3808e 298 tcg_gen_qemu_ld16s(tmp, addr, index);
e6e5906b 299 else
e1f3808e 300 tcg_gen_qemu_ld16u(tmp, addr, index);
e6e5906b
PB		 301 break;
302 case OS_LONG:
a7812ae4 303 tcg_gen_qemu_ld32u(tmp, addr, index);
e6e5906b
PB		 304 break;
305 default:
7372c2b9 306 g_assert_not_reached();
e6e5906b 307 }
e6e5906b
PB		 308 return tmp;
309}
310
311/* Generate a store. */
e1f3808e 312static inline void gen_store(DisasContext *s, int opsize, TCGv addr, TCGv val)
e6e5906b 313{
e1f3808e 314 int index = IS_USER(s);
e6e5906b
PB		 315 switch(opsize) {
316 case OS_BYTE:
e1f3808e 317 tcg_gen_qemu_st8(val, addr, index);
e6e5906b
PB		 318 break;
319 case OS_WORD:
e1f3808e 320 tcg_gen_qemu_st16(val, addr, index);
e6e5906b
PB		 321 break;
322 case OS_LONG:
a7812ae4 323 tcg_gen_qemu_st32(val, addr, index);
e6e5906b
PB		 324 break;
325 default:
7372c2b9 326 g_assert_not_reached();
e6e5906b 327 }
e6e5906b
PB		 328}
329
e1f3808e
PB		 330typedef enum {
331 EA_STORE,
332 EA_LOADU,
333 EA_LOADS
334} ea_what;
335
e6e5906b
PB		 336/* Generate an unsigned load if VAL is 0 a signed load if val is -1,
337 otherwise generate a store. */
e1f3808e
PB		 338static TCGv gen_ldst(DisasContext *s, int opsize, TCGv addr, TCGv val,
339 ea_what what)
e6e5906b 340{
e1f3808e 341 if (what == EA_STORE) {
0633879f 342 gen_store(s, opsize, addr, val);
e1f3808e 343 return store_dummy;
e6e5906b 344 } else {
e1f3808e 345 return gen_load(s, opsize, addr, what == EA_LOADS);
e6e5906b
PB		 346 }
347}
348
28b68cd7
LV		 349/* Read a 16-bit immediate constant */
350static inline uint16_t read_im16(CPUM68KState *env, DisasContext *s)
351{
352 uint16_t im;
353 im = cpu_lduw_code(env, s->pc);
354 s->pc += 2;
355 return im;
356}
357
358/* Read an 8-bit immediate constant */
359static inline uint8_t read_im8(CPUM68KState *env, DisasContext *s)
360{
361 return read_im16(env, s);
362}
363
e6dbd3b3 364/* Read a 32-bit immediate constant. */
d4d79bb1 365static inline uint32_t read_im32(CPUM68KState *env, DisasContext *s)
e6dbd3b3
PB		 366{
367 uint32_t im;
28b68cd7
LV		 368 im = read_im16(env, s) << 16;
369 im |= 0xffff & read_im16(env, s);
e6dbd3b3
PB		 370 return im;
371}
372
f83311e4
LV		 373/* Read a 64-bit immediate constant. */
374static inline uint64_t read_im64(CPUM68KState *env, DisasContext *s)
375{
376 uint64_t im;
377 im = (uint64_t)read_im32(env, s) << 32;
378 im |= (uint64_t)read_im32(env, s);
379 return im;
380}
381
e6dbd3b3 382/* Calculate and address index. */
8a1e52b6 383static TCGv gen_addr_index(DisasContext *s, uint16_t ext, TCGv tmp)
e6dbd3b3 384{
e1f3808e 385 TCGv add;
e6dbd3b3
PB		 386 int scale;
387
388 add = (ext & 0x8000) ? AREG(ext, 12) : DREG(ext, 12);
389 if ((ext & 0x800) == 0) {
e1f3808e 390 tcg_gen_ext16s_i32(tmp, add);
e6dbd3b3
PB		 391 add = tmp;
392 }
393 scale = (ext >> 9) & 3;
394 if (scale != 0) {
e1f3808e 395 tcg_gen_shli_i32(tmp, add, scale);
e6dbd3b3
PB		 396 add = tmp;
397 }
398 return add;
399}
400
e1f3808e
PB		 401/* Handle a base + index + displacement effective addresss.
402 A NULL_QREG base means pc-relative. */
a4356126 403static TCGv gen_lea_indexed(CPUM68KState *env, DisasContext *s, TCGv base)
e6e5906b 404{
e6e5906b
PB		 405 uint32_t offset;
406 uint16_t ext;
e1f3808e
PB		 407 TCGv add;
408 TCGv tmp;
e6dbd3b3 409 uint32_t bd, od;
e6e5906b
PB		 410
411 offset = s->pc;
28b68cd7 412 ext = read_im16(env, s);
e6dbd3b3
PB		 413
414 if ((ext & 0x800) == 0 && !m68k_feature(s->env, M68K_FEATURE_WORD_INDEX))
e1f3808e 415 return NULL_QREG;
e6dbd3b3 416
d8633620
LV		 417 if (m68k_feature(s->env, M68K_FEATURE_M68000) &&
418 !m68k_feature(s->env, M68K_FEATURE_SCALED_INDEX)) {
419 ext &= ~(3 << 9);
420 }
421
e6dbd3b3
PB		 422 if (ext & 0x100) {
423 /* full extension word format */
424 if (!m68k_feature(s->env, M68K_FEATURE_EXT_FULL))
e1f3808e 425 return NULL_QREG;
e6dbd3b3
PB		 426
427 if ((ext & 0x30) > 0x10) {
428 /* base displacement */
429 if ((ext & 0x30) == 0x20) {
28b68cd7 430 bd = (int16_t)read_im16(env, s);
e6dbd3b3 431 } else {
d4d79bb1 432 bd = read_im32(env, s);
e6dbd3b3
PB		 433 }
434 } else {
435 bd = 0;
436 }
a7812ae4 437 tmp = tcg_temp_new();
e6dbd3b3
PB		 438 if ((ext & 0x44) == 0) {
439 /* pre-index */
8a1e52b6 440 add = gen_addr_index(s, ext, tmp);
e6dbd3b3 441 } else {
e1f3808e 442 add = NULL_QREG;
e6dbd3b3
PB		 443 }
444 if ((ext & 0x80) == 0) {
445 /* base not suppressed */
e1f3808e 446 if (IS_NULL_QREG(base)) {
351326a6 447 base = tcg_const_i32(offset + bd);
e6dbd3b3
PB		 448 bd = 0;
449 }
e1f3808e
PB		 450 if (!IS_NULL_QREG(add)) {
451 tcg_gen_add_i32(tmp, add, base);
e6dbd3b3
PB		 452 add = tmp;
453 } else {
454 add = base;
455 }
456 }
e1f3808e 457 if (!IS_NULL_QREG(add)) {
e6dbd3b3 458 if (bd != 0) {
e1f3808e 459 tcg_gen_addi_i32(tmp, add, bd);
e6dbd3b3
PB		 460 add = tmp;
461 }
462 } else {
351326a6 463 add = tcg_const_i32(bd);
e6dbd3b3
PB		 464 }
465 if ((ext & 3) != 0) {
466 /* memory indirect */
467 base = gen_load(s, OS_LONG, add, 0);
468 if ((ext & 0x44) == 4) {
8a1e52b6 469 add = gen_addr_index(s, ext, tmp);
e1f3808e 470 tcg_gen_add_i32(tmp, add, base);
e6dbd3b3
PB		 471 add = tmp;
472 } else {
473 add = base;
474 }
475 if ((ext & 3) > 1) {
476 /* outer displacement */
477 if ((ext & 3) == 2) {
28b68cd7 478 od = (int16_t)read_im16(env, s);
e6dbd3b3 479 } else {
d4d79bb1 480 od = read_im32(env, s);
e6dbd3b3
PB		 481 }
482 } else {
483 od = 0;
484 }
485 if (od != 0) {
e1f3808e 486 tcg_gen_addi_i32(tmp, add, od);
e6dbd3b3
PB		 487 add = tmp;
488 }
489 }
e6e5906b 490 } else {
e6dbd3b3 491 /* brief extension word format */
a7812ae4 492 tmp = tcg_temp_new();
8a1e52b6 493 add = gen_addr_index(s, ext, tmp);
e1f3808e
PB		 494 if (!IS_NULL_QREG(base)) {
495 tcg_gen_add_i32(tmp, add, base);
e6dbd3b3 496 if ((int8_t)ext)
e1f3808e 497 tcg_gen_addi_i32(tmp, tmp, (int8_t)ext);
e6dbd3b3 498 } else {
e1f3808e 499 tcg_gen_addi_i32(tmp, add, offset + (int8_t)ext);
e6dbd3b3
PB		 500 }
501 add = tmp;
e6e5906b 502 }
e6dbd3b3 503 return add;
e6e5906b
PB		 504}
505
db3d7945
LV		 506/* Sign or zero extend a value. */
507
508static inline void gen_ext(TCGv res, TCGv val, int opsize, int sign)
509{
510 switch (opsize) {
511 case OS_BYTE:
512 if (sign) {
513 tcg_gen_ext8s_i32(res, val);
514 } else {
515 tcg_gen_ext8u_i32(res, val);
516 }
517 break;
518 case OS_WORD:
519 if (sign) {
520 tcg_gen_ext16s_i32(res, val);
521 } else {
522 tcg_gen_ext16u_i32(res, val);
523 }
524 break;
525 case OS_LONG:
526 tcg_gen_mov_i32(res, val);
527 break;
528 default:
529 g_assert_not_reached();
530 }
531}
532
e6e5906b 533/* Evaluate all the CC flags. */
9fdb533f 534
620c6cf6 535static void gen_flush_flags(DisasContext *s)
e6e5906b 536{
36f0399d 537 TCGv t0, t1;
620c6cf6
RH		 538
539 switch (s->cc_op) {
540 case CC_OP_FLAGS:
e6e5906b 541 return;
36f0399d 542
db3d7945
LV		 543 case CC_OP_ADDB:
544 case CC_OP_ADDW:
545 case CC_OP_ADDL:
36f0399d
RH		 546 tcg_gen_mov_i32(QREG_CC_C, QREG_CC_X);
547 tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N);
548 /* Compute signed overflow for addition. */
549 t0 = tcg_temp_new();
550 t1 = tcg_temp_new();
551 tcg_gen_sub_i32(t0, QREG_CC_N, QREG_CC_V);
db3d7945 552 gen_ext(t0, t0, s->cc_op - CC_OP_ADDB, 1);
36f0399d
RH		 553 tcg_gen_xor_i32(t1, QREG_CC_N, QREG_CC_V);
554 tcg_gen_xor_i32(QREG_CC_V, QREG_CC_V, t0);
555 tcg_temp_free(t0);
556 tcg_gen_andc_i32(QREG_CC_V, t1, QREG_CC_V);
557 tcg_temp_free(t1);
558 break;
559
db3d7945
LV		 560 case CC_OP_SUBB:
561 case CC_OP_SUBW:
562 case CC_OP_SUBL:
36f0399d
RH		 563 tcg_gen_mov_i32(QREG_CC_C, QREG_CC_X);
564 tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N);
565 /* Compute signed overflow for subtraction. */
566 t0 = tcg_temp_new();
567 t1 = tcg_temp_new();
568 tcg_gen_add_i32(t0, QREG_CC_N, QREG_CC_V);
db3d7945 569 gen_ext(t0, t0, s->cc_op - CC_OP_SUBB, 1);
043b936e 570 tcg_gen_xor_i32(t1, QREG_CC_N, t0);
36f0399d
RH		 571 tcg_gen_xor_i32(QREG_CC_V, QREG_CC_V, t0);
572 tcg_temp_free(t0);
573 tcg_gen_and_i32(QREG_CC_V, QREG_CC_V, t1);
574 tcg_temp_free(t1);
575 break;
576
db3d7945
LV		 577 case CC_OP_CMPB:
578 case CC_OP_CMPW:
579 case CC_OP_CMPL:
36f0399d
RH		 580 tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_C, QREG_CC_N, QREG_CC_V);
581 tcg_gen_sub_i32(QREG_CC_Z, QREG_CC_N, QREG_CC_V);
db3d7945 582 gen_ext(QREG_CC_Z, QREG_CC_Z, s->cc_op - CC_OP_CMPB, 1);
36f0399d
RH		 583 /* Compute signed overflow for subtraction. */
584 t0 = tcg_temp_new();
585 tcg_gen_xor_i32(t0, QREG_CC_Z, QREG_CC_N);
586 tcg_gen_xor_i32(QREG_CC_V, QREG_CC_V, QREG_CC_N);
587 tcg_gen_and_i32(QREG_CC_V, QREG_CC_V, t0);
588 tcg_temp_free(t0);
589 tcg_gen_mov_i32(QREG_CC_N, QREG_CC_Z);
590 break;
591
592 case CC_OP_LOGIC:
593 tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N);
594 tcg_gen_movi_i32(QREG_CC_C, 0);
595 tcg_gen_movi_i32(QREG_CC_V, 0);
596 break;
597
620c6cf6
RH		 598 case CC_OP_DYNAMIC:
599 gen_helper_flush_flags(cpu_env, QREG_CC_OP);
695576db 600 s->cc_op_synced = 1;
620c6cf6 601 break;
36f0399d 602
620c6cf6 603 default:
36f0399d
RH		 604 t0 = tcg_const_i32(s->cc_op);
605 gen_helper_flush_flags(cpu_env, t0);
606 tcg_temp_free(t0);
695576db 607 s->cc_op_synced = 1;
620c6cf6
RH		 608 break;
609 }
610
611 /* Note that flush_flags also assigned to env->cc_op. */
612 s->cc_op = CC_OP_FLAGS;
620c6cf6
RH		 613}
614
db3d7945 615static inline TCGv gen_extend(TCGv val, int opsize, int sign)
620c6cf6
RH		 616{
617 TCGv tmp;
618
619 if (opsize == OS_LONG) {
620 tmp = val;
621 } else {
622 tmp = tcg_temp_new();
623 gen_ext(tmp, val, opsize, sign);
624 }
625
626 return tmp;
627}
5dbb6784
LV		 628
629static void gen_logic_cc(DisasContext *s, TCGv val, int opsize)
e1f3808e 630{
620c6cf6
RH		 631 gen_ext(QREG_CC_N, val, opsize, 1);
632 set_cc_op(s, CC_OP_LOGIC);
e1f3808e
PB		 633}
634
ff99b952
LV		 635static void gen_update_cc_cmp(DisasContext *s, TCGv dest, TCGv src, int opsize)
636{
637 tcg_gen_mov_i32(QREG_CC_N, dest);
638 tcg_gen_mov_i32(QREG_CC_V, src);
639 set_cc_op(s, CC_OP_CMPB + opsize);
640}
641
db3d7945 642static void gen_update_cc_add(TCGv dest, TCGv src, int opsize)
e1f3808e 643{
db3d7945 644 gen_ext(QREG_CC_N, dest, opsize, 1);
620c6cf6 645 tcg_gen_mov_i32(QREG_CC_V, src);
e1f3808e
PB		 646}
647
e6e5906b
PB		 648static inline int opsize_bytes(int opsize)
649{
650 switch (opsize) {
651 case OS_BYTE: return 1;
652 case OS_WORD: return 2;
653 case OS_LONG: return 4;
654 case OS_SINGLE: return 4;
655 case OS_DOUBLE: return 8;
7ef25cdd
LV		 656 case OS_EXTENDED: return 12;
657 case OS_PACKED: return 12;
658 default:
659 g_assert_not_reached();
660 }
661}
662
663static inline int insn_opsize(int insn)
664{
665 switch ((insn >> 6) & 3) {
666 case 0: return OS_BYTE;
667 case 1: return OS_WORD;
668 case 2: return OS_LONG;
e6e5906b 669 default:
7372c2b9 670 g_assert_not_reached();
e6e5906b
PB		 671 }
672}
673
69e69822
LV		 674static inline int ext_opsize(int ext, int pos)
675{
676 switch ((ext >> pos) & 7) {
677 case 0: return OS_LONG;
678 case 1: return OS_SINGLE;
679 case 2: return OS_EXTENDED;
680 case 3: return OS_PACKED;
681 case 4: return OS_WORD;
682 case 5: return OS_DOUBLE;
683 case 6: return OS_BYTE;
684 default:
685 g_assert_not_reached();
686 }
687}
688
e6e5906b
PB		 689/* Assign value to a register. If the width is less than the register width
690 only the low part of the register is set. */
e1f3808e 691static void gen_partset_reg(int opsize, TCGv reg, TCGv val)
e6e5906b 692{
e1f3808e 693 TCGv tmp;
e6e5906b
PB		 694 switch (opsize) {
695 case OS_BYTE:
e1f3808e 696 tcg_gen_andi_i32(reg, reg, 0xffffff00);
a7812ae4 697 tmp = tcg_temp_new();
e1f3808e
PB		 698 tcg_gen_ext8u_i32(tmp, val);
699 tcg_gen_or_i32(reg, reg, tmp);
2b5e2170 700 tcg_temp_free(tmp);
e6e5906b
PB		 701 break;
702 case OS_WORD:
e1f3808e 703 tcg_gen_andi_i32(reg, reg, 0xffff0000);
a7812ae4 704 tmp = tcg_temp_new();
e1f3808e
PB		 705 tcg_gen_ext16u_i32(tmp, val);
706 tcg_gen_or_i32(reg, reg, tmp);
2b5e2170 707 tcg_temp_free(tmp);
e6e5906b
PB		 708 break;
709 case OS_LONG:
e6e5906b 710 case OS_SINGLE:
a7812ae4 711 tcg_gen_mov_i32(reg, val);
e6e5906b
PB		 712 break;
713 default:
7372c2b9 714 g_assert_not_reached();
e6e5906b
PB		 715 }
716}
717
e6e5906b 718/* Generate code for an "effective address". Does not adjust the base
1addc7c5 719 register for autoincrement addressing modes. */
f84aab26
RH		 720static TCGv gen_lea_mode(CPUM68KState *env, DisasContext *s,
721 int mode, int reg0, int opsize)
e6e5906b 722{
e1f3808e
PB		 723 TCGv reg;
724 TCGv tmp;
e6e5906b
PB		 725 uint16_t ext;
726 uint32_t offset;
727
f84aab26 728 switch (mode) {
e6e5906b
PB		 729 case 0: /* Data register direct. */
730 case 1: /* Address register direct. */
e1f3808e 731 return NULL_QREG;
e6e5906b 732 case 3: /* Indirect postincrement. */
f2224f2c
RH		 733 if (opsize == OS_UNSIZED) {
734 return NULL_QREG;
735 }
736 /* fallthru */
737 case 2: /* Indirect register */
f84aab26 738 return get_areg(s, reg0);
e6e5906b 739 case 4: /* Indirect predecrememnt. */
f2224f2c
RH		 740 if (opsize == OS_UNSIZED) {
741 return NULL_QREG;
742 }
f84aab26 743 reg = get_areg(s, reg0);
a7812ae4 744 tmp = tcg_temp_new();
727d937b
LV		 745 if (reg0 == 7 && opsize == OS_BYTE &&
746 m68k_feature(s->env, M68K_FEATURE_M68000)) {
747 tcg_gen_subi_i32(tmp, reg, 2);
748 } else {
749 tcg_gen_subi_i32(tmp, reg, opsize_bytes(opsize));
750 }
e6e5906b
PB		 751 return tmp;
752 case 5: /* Indirect displacement. */
f84aab26 753 reg = get_areg(s, reg0);
a7812ae4 754 tmp = tcg_temp_new();
28b68cd7 755 ext = read_im16(env, s);
e1f3808e 756 tcg_gen_addi_i32(tmp, reg, (int16_t)ext);
e6e5906b
PB		 757 return tmp;
758 case 6: /* Indirect index + displacement. */
f84aab26 759 reg = get_areg(s, reg0);
a4356126 760 return gen_lea_indexed(env, s, reg);
e6e5906b 761 case 7: /* Other */
f84aab26 762 switch (reg0) {
e6e5906b 763 case 0: /* Absolute short. */
28b68cd7 764 offset = (int16_t)read_im16(env, s);
351326a6 765 return tcg_const_i32(offset);
e6e5906b 766 case 1: /* Absolute long. */
d4d79bb1 767 offset = read_im32(env, s);
351326a6 768 return tcg_const_i32(offset);
e6e5906b 769 case 2: /* pc displacement */
e6e5906b 770 offset = s->pc;
28b68cd7 771 offset += (int16_t)read_im16(env, s);
351326a6 772 return tcg_const_i32(offset);
e6e5906b 773 case 3: /* pc index+displacement. */
a4356126 774 return gen_lea_indexed(env, s, NULL_QREG);
e6e5906b
PB		 775 case 4: /* Immediate. */
776 default:
e1f3808e 777 return NULL_QREG;
e6e5906b
PB		 778 }
779 }
780 /* Should never happen. */
e1f3808e 781 return NULL_QREG;
e6e5906b
PB		 782}
783
f84aab26
RH		 784static TCGv gen_lea(CPUM68KState *env, DisasContext *s, uint16_t insn,
785 int opsize)
e6e5906b 786{
f84aab26
RH		 787 int mode = extract32(insn, 3, 3);
788 int reg0 = REG(insn, 0);
789 return gen_lea_mode(env, s, mode, reg0, opsize);
e6e5906b
PB		 790}
791
f84aab26 792/* Generate code to load/store a value from/into an EA. If WHAT > 0 this is
e6e5906b
PB		 793 a write otherwise it is a read (0 == sign extend, -1 == zero extend).
794 ADDRP is non-null for readwrite operands. */
f84aab26
RH		 795static TCGv gen_ea_mode(CPUM68KState *env, DisasContext *s, int mode, int reg0,
796 int opsize, TCGv val, TCGv *addrp, ea_what what)
e6e5906b 797{
f84aab26
RH		 798 TCGv reg, tmp, result;
799 int32_t offset;
e6e5906b 800
f84aab26 801 switch (mode) {
e6e5906b 802 case 0: /* Data register direct. */
f84aab26 803 reg = cpu_dregs[reg0];
e1f3808e 804 if (what == EA_STORE) {
e6e5906b 805 gen_partset_reg(opsize, reg, val);
e1f3808e 806 return store_dummy;
e6e5906b 807 } else {
e1f3808e 808 return gen_extend(reg, opsize, what == EA_LOADS);
e6e5906b
PB		 809 }
810 case 1: /* Address register direct. */
f84aab26 811 reg = get_areg(s, reg0);
e1f3808e
PB		 812 if (what == EA_STORE) {
813 tcg_gen_mov_i32(reg, val);
814 return store_dummy;
e6e5906b 815 } else {
e1f3808e 816 return gen_extend(reg, opsize, what == EA_LOADS);
e6e5906b
PB		 817 }
818 case 2: /* Indirect register */
f84aab26 819 reg = get_areg(s, reg0);
e1f3808e 820 return gen_ldst(s, opsize, reg, val, what);
e6e5906b 821 case 3: /* Indirect postincrement. */
f84aab26 822 reg = get_areg(s, reg0);
e1f3808e 823 result = gen_ldst(s, opsize, reg, val, what);
8a1e52b6
RH		 824 if (what == EA_STORE || !addrp) {
825 TCGv tmp = tcg_temp_new();
727d937b
LV		 826 if (reg0 == 7 && opsize == OS_BYTE &&
827 m68k_feature(s->env, M68K_FEATURE_M68000)) {
828 tcg_gen_addi_i32(tmp, reg, 2);
829 } else {
830 tcg_gen_addi_i32(tmp, reg, opsize_bytes(opsize));
831 }
f84aab26 832 delay_set_areg(s, reg0, tmp, true);
8a1e52b6 833 }
e6e5906b
PB		 834 return result;
835 case 4: /* Indirect predecrememnt. */
f84aab26
RH		 836 if (addrp && what == EA_STORE) {
837 tmp = *addrp;
838 } else {
839 tmp = gen_lea_mode(env, s, mode, reg0, opsize);
840 if (IS_NULL_QREG(tmp)) {
841 return tmp;
e6e5906b 842 }
f84aab26
RH		 843 if (addrp) {
844 *addrp = tmp;
e6e5906b
PB		 845 }
846 }
f84aab26
RH		 847 result = gen_ldst(s, opsize, tmp, val, what);
848 if (what == EA_STORE || !addrp) {
849 delay_set_areg(s, reg0, tmp, false);
850 }
e6e5906b
PB		 851 return result;
852 case 5: /* Indirect displacement. */
853 case 6: /* Indirect index + displacement. */
f84aab26
RH		 854 do_indirect:
855 if (addrp && what == EA_STORE) {
856 tmp = *addrp;
857 } else {
858 tmp = gen_lea_mode(env, s, mode, reg0, opsize);
859 if (IS_NULL_QREG(tmp)) {
860 return tmp;
861 }
862 if (addrp) {
863 *addrp = tmp;
864 }
865 }
866 return gen_ldst(s, opsize, tmp, val, what);
e6e5906b 867 case 7: /* Other */
f84aab26 868 switch (reg0) {
e6e5906b
PB		 869 case 0: /* Absolute short. */
870 case 1: /* Absolute long. */
871 case 2: /* pc displacement */
872 case 3: /* pc index+displacement. */
f84aab26 873 goto do_indirect;
e6e5906b
PB		 874 case 4: /* Immediate. */
875 /* Sign extend values for consistency. */
876 switch (opsize) {
877 case OS_BYTE:
31871141 878 if (what == EA_LOADS) {
28b68cd7 879 offset = (int8_t)read_im8(env, s);
31871141 880 } else {
28b68cd7 881 offset = read_im8(env, s);
31871141 882 }
e6e5906b
PB		 883 break;
884 case OS_WORD:
31871141 885 if (what == EA_LOADS) {
28b68cd7 886 offset = (int16_t)read_im16(env, s);
31871141 887 } else {
28b68cd7 888 offset = read_im16(env, s);
31871141 889 }
e6e5906b
PB		 890 break;
891 case OS_LONG:
d4d79bb1 892 offset = read_im32(env, s);
e6e5906b
PB		 893 break;
894 default:
7372c2b9 895 g_assert_not_reached();
e6e5906b 896 }
e1f3808e 897 return tcg_const_i32(offset);
e6e5906b 898 default:
e1f3808e 899 return NULL_QREG;
e6e5906b
PB		 900 }
901 }
902 /* Should never happen. */
e1f3808e 903 return NULL_QREG;
e6e5906b
PB		 904}
905
f84aab26
RH		 906static TCGv gen_ea(CPUM68KState *env, DisasContext *s, uint16_t insn,
907 int opsize, TCGv val, TCGv *addrp, ea_what what)
908{
909 int mode = extract32(insn, 3, 3);
910 int reg0 = REG(insn, 0);
911 return gen_ea_mode(env, s, mode, reg0, opsize, val, addrp, what);
912}
913
f83311e4
LV		 914static TCGv_ptr gen_fp_ptr(int freg)
915{
916 TCGv_ptr fp = tcg_temp_new_ptr();
917 tcg_gen_addi_ptr(fp, cpu_env, offsetof(CPUM68KState, fregs[freg]));
918 return fp;
919}
920
921static TCGv_ptr gen_fp_result_ptr(void)
922{
923 TCGv_ptr fp = tcg_temp_new_ptr();
924 tcg_gen_addi_ptr(fp, cpu_env, offsetof(CPUM68KState, fp_result));
925 return fp;
926}
927
928static void gen_fp_move(TCGv_ptr dest, TCGv_ptr src)
929{
930 TCGv t32;
931 TCGv_i64 t64;
932
933 t32 = tcg_temp_new();
934 tcg_gen_ld16u_i32(t32, src, offsetof(FPReg, l.upper));
935 tcg_gen_st16_i32(t32, dest, offsetof(FPReg, l.upper));
936 tcg_temp_free(t32);
937
938 t64 = tcg_temp_new_i64();
939 tcg_gen_ld_i64(t64, src, offsetof(FPReg, l.lower));
940 tcg_gen_st_i64(t64, dest, offsetof(FPReg, l.lower));
941 tcg_temp_free_i64(t64);
942}
943
944static void gen_load_fp(DisasContext *s, int opsize, TCGv addr, TCGv_ptr fp)
945{
946 TCGv tmp;
947 TCGv_i64 t64;
948 int index = IS_USER(s);
949
950 t64 = tcg_temp_new_i64();
951 tmp = tcg_temp_new();
952 switch (opsize) {
953 case OS_BYTE:
954 tcg_gen_qemu_ld8s(tmp, addr, index);
955 gen_helper_exts32(cpu_env, fp, tmp);
956 break;
957 case OS_WORD:
958 tcg_gen_qemu_ld16s(tmp, addr, index);
959 gen_helper_exts32(cpu_env, fp, tmp);
960 break;
961 case OS_LONG:
962 tcg_gen_qemu_ld32u(tmp, addr, index);
963 gen_helper_exts32(cpu_env, fp, tmp);
964 break;
965 case OS_SINGLE:
966 tcg_gen_qemu_ld32u(tmp, addr, index);
967 gen_helper_extf32(cpu_env, fp, tmp);
968 break;
969 case OS_DOUBLE:
970 tcg_gen_qemu_ld64(t64, addr, index);
971 gen_helper_extf64(cpu_env, fp, t64);
972 tcg_temp_free_i64(t64);
973 break;
974 case OS_EXTENDED:
975 if (m68k_feature(s->env, M68K_FEATURE_CF_FPU)) {
976 gen_exception(s, s->insn_pc, EXCP_FP_UNIMP);
977 break;
978 }
979 tcg_gen_qemu_ld32u(tmp, addr, index);
980 tcg_gen_shri_i32(tmp, tmp, 16);
981 tcg_gen_st16_i32(tmp, fp, offsetof(FPReg, l.upper));
982 tcg_gen_addi_i32(tmp, addr, 4);
983 tcg_gen_qemu_ld64(t64, tmp, index);
984 tcg_gen_st_i64(t64, fp, offsetof(FPReg, l.lower));
985 break;
986 case OS_PACKED:
987 /* unimplemented data type on 68040/ColdFire
988 * FIXME if needed for another FPU
989 */
990 gen_exception(s, s->insn_pc, EXCP_FP_UNIMP);
991 break;
992 default:
993 g_assert_not_reached();
994 }
995 tcg_temp_free(tmp);
996 tcg_temp_free_i64(t64);
f83311e4
LV		 997}
998
999static void gen_store_fp(DisasContext *s, int opsize, TCGv addr, TCGv_ptr fp)
1000{
1001 TCGv tmp;
1002 TCGv_i64 t64;
1003 int index = IS_USER(s);
1004
1005 t64 = tcg_temp_new_i64();
1006 tmp = tcg_temp_new();
1007 switch (opsize) {
1008 case OS_BYTE:
1009 gen_helper_reds32(tmp, cpu_env, fp);
1010 tcg_gen_qemu_st8(tmp, addr, index);
1011 break;
1012 case OS_WORD:
1013 gen_helper_reds32(tmp, cpu_env, fp);
1014 tcg_gen_qemu_st16(tmp, addr, index);
1015 break;
1016 case OS_LONG:
1017 gen_helper_reds32(tmp, cpu_env, fp);
1018 tcg_gen_qemu_st32(tmp, addr, index);
1019 break;
1020 case OS_SINGLE:
1021 gen_helper_redf32(tmp, cpu_env, fp);
1022 tcg_gen_qemu_st32(tmp, addr, index);
1023 break;
1024 case OS_DOUBLE:
1025 gen_helper_redf64(t64, cpu_env, fp);
1026 tcg_gen_qemu_st64(t64, addr, index);
1027 break;
1028 case OS_EXTENDED:
1029 if (m68k_feature(s->env, M68K_FEATURE_CF_FPU)) {
1030 gen_exception(s, s->insn_pc, EXCP_FP_UNIMP);
1031 break;
1032 }
1033 tcg_gen_ld16u_i32(tmp, fp, offsetof(FPReg, l.upper));
1034 tcg_gen_shli_i32(tmp, tmp, 16);
1035 tcg_gen_qemu_st32(tmp, addr, index);
1036 tcg_gen_addi_i32(tmp, addr, 4);
1037 tcg_gen_ld_i64(t64, fp, offsetof(FPReg, l.lower));
1038 tcg_gen_qemu_st64(t64, tmp, index);
1039 break;
1040 case OS_PACKED:
1041 /* unimplemented data type on 68040/ColdFire
1042 * FIXME if needed for another FPU
1043 */
1044 gen_exception(s, s->insn_pc, EXCP_FP_UNIMP);
1045 break;
1046 default:
1047 g_assert_not_reached();
1048 }
1049 tcg_temp_free(tmp);
1050 tcg_temp_free_i64(t64);
f83311e4
LV		 1051}
1052
1053static void gen_ldst_fp(DisasContext *s, int opsize, TCGv addr,
1054 TCGv_ptr fp, ea_what what)
1055{
1056 if (what == EA_STORE) {
1057 gen_store_fp(s, opsize, addr, fp);
1058 } else {
1059 gen_load_fp(s, opsize, addr, fp);
1060 }
1061}
1062
1063static int gen_ea_mode_fp(CPUM68KState *env, DisasContext *s, int mode,
1064 int reg0, int opsize, TCGv_ptr fp, ea_what what)
1065{
1066 TCGv reg, addr, tmp;
1067 TCGv_i64 t64;
1068
1069 switch (mode) {
1070 case 0: /* Data register direct. */
1071 reg = cpu_dregs[reg0];
1072 if (what == EA_STORE) {
1073 switch (opsize) {
1074 case OS_BYTE:
1075 case OS_WORD:
1076 case OS_LONG:
1077 gen_helper_reds32(reg, cpu_env, fp);
1078 break;
1079 case OS_SINGLE:
1080 gen_helper_redf32(reg, cpu_env, fp);
1081 break;
1082 default:
1083 g_assert_not_reached();
1084 }
1085 } else {
1086 tmp = tcg_temp_new();
1087 switch (opsize) {
1088 case OS_BYTE:
1089 tcg_gen_ext8s_i32(tmp, reg);
1090 gen_helper_exts32(cpu_env, fp, tmp);
1091 break;
1092 case OS_WORD:
1093 tcg_gen_ext16s_i32(tmp, reg);
1094 gen_helper_exts32(cpu_env, fp, tmp);
1095 break;
1096 case OS_LONG:
1097 gen_helper_exts32(cpu_env, fp, reg);
1098 break;
1099 case OS_SINGLE:
1100 gen_helper_extf32(cpu_env, fp, reg);
1101 break;
1102 default:
1103 g_assert_not_reached();
1104 }
1105 tcg_temp_free(tmp);
1106 }
1107 return 0;
1108 case 1: /* Address register direct. */
1109 return -1;
1110 case 2: /* Indirect register */
1111 addr = get_areg(s, reg0);
1112 gen_ldst_fp(s, opsize, addr, fp, what);
1113 return 0;
1114 case 3: /* Indirect postincrement. */
1115 addr = cpu_aregs[reg0];
1116 gen_ldst_fp(s, opsize, addr, fp, what);
1117 tcg_gen_addi_i32(addr, addr, opsize_bytes(opsize));
1118 return 0;
1119 case 4: /* Indirect predecrememnt. */
1120 addr = gen_lea_mode(env, s, mode, reg0, opsize);
1121 if (IS_NULL_QREG(addr)) {
1122 return -1;
1123 }
1124 gen_ldst_fp(s, opsize, addr, fp, what);
1125 tcg_gen_mov_i32(cpu_aregs[reg0], addr);
1126 return 0;
1127 case 5: /* Indirect displacement. */
1128 case 6: /* Indirect index + displacement. */
1129 do_indirect:
1130 addr = gen_lea_mode(env, s, mode, reg0, opsize);
1131 if (IS_NULL_QREG(addr)) {
1132 return -1;
1133 }
1134 gen_ldst_fp(s, opsize, addr, fp, what);
1135 return 0;
1136 case 7: /* Other */
1137 switch (reg0) {
1138 case 0: /* Absolute short. */
1139 case 1: /* Absolute long. */
1140 case 2: /* pc displacement */
1141 case 3: /* pc index+displacement. */
1142 goto do_indirect;
1143 case 4: /* Immediate. */
1144 if (what == EA_STORE) {
1145 return -1;
1146 }
1147 switch (opsize) {
1148 case OS_BYTE:
1149 tmp = tcg_const_i32((int8_t)read_im8(env, s));
1150 gen_helper_exts32(cpu_env, fp, tmp);
1151 tcg_temp_free(tmp);
1152 break;
1153 case OS_WORD:
1154 tmp = tcg_const_i32((int16_t)read_im16(env, s));
1155 gen_helper_exts32(cpu_env, fp, tmp);
1156 tcg_temp_free(tmp);
1157 break;
1158 case OS_LONG:
1159 tmp = tcg_const_i32(read_im32(env, s));
1160 gen_helper_exts32(cpu_env, fp, tmp);
1161 tcg_temp_free(tmp);
1162 break;
1163 case OS_SINGLE:
1164 tmp = tcg_const_i32(read_im32(env, s));
1165 gen_helper_extf32(cpu_env, fp, tmp);
1166 tcg_temp_free(tmp);
1167 break;
1168 case OS_DOUBLE:
1169 t64 = tcg_const_i64(read_im64(env, s));
1170 gen_helper_extf64(cpu_env, fp, t64);
1171 tcg_temp_free_i64(t64);
1172 break;
1173 case OS_EXTENDED:
1174 if (m68k_feature(s->env, M68K_FEATURE_CF_FPU)) {
1175 gen_exception(s, s->insn_pc, EXCP_FP_UNIMP);
1176 break;
1177 }
1178 tmp = tcg_const_i32(read_im32(env, s) >> 16);
1179 tcg_gen_st16_i32(tmp, fp, offsetof(FPReg, l.upper));
1180 tcg_temp_free(tmp);
1181 t64 = tcg_const_i64(read_im64(env, s));
1182 tcg_gen_st_i64(t64, fp, offsetof(FPReg, l.lower));
1183 tcg_temp_free_i64(t64);
1184 break;
1185 case OS_PACKED:
1186 /* unimplemented data type on 68040/ColdFire
1187 * FIXME if needed for another FPU
1188 */
1189 gen_exception(s, s->insn_pc, EXCP_FP_UNIMP);
1190 break;
1191 default:
1192 g_assert_not_reached();
1193 }
1194 return 0;
1195 default:
1196 return -1;
1197 }
1198 }
1199 return -1;
1200}
1201
1202static int gen_ea_fp(CPUM68KState *env, DisasContext *s, uint16_t insn,
1203 int opsize, TCGv_ptr fp, ea_what what)
1204{
1205 int mode = extract32(insn, 3, 3);
1206 int reg0 = REG(insn, 0);
1207 return gen_ea_mode_fp(env, s, mode, reg0, opsize, fp, what);
1208}
1209
6a432295
RH		 1210typedef struct {
1211 TCGCond tcond;
1212 bool g1;
1213 bool g2;
1214 TCGv v1;
1215 TCGv v2;
1216} DisasCompare;
1217
1218static void gen_cc_cond(DisasCompare *c, DisasContext *s, int cond)
e6e5906b 1219{
620c6cf6
RH		 1220 TCGv tmp, tmp2;
1221 TCGCond tcond;
9d896621 1222 CCOp op = s->cc_op;
e6e5906b 1223
9d896621 1224 /* The CC_OP_CMP form can handle most normal comparisons directly. */
db3d7945 1225 if (op == CC_OP_CMPB || op == CC_OP_CMPW || op == CC_OP_CMPL) {
9d896621
RH		 1226 c->g1 = c->g2 = 1;
1227 c->v1 = QREG_CC_N;
1228 c->v2 = QREG_CC_V;
1229 switch (cond) {
1230 case 2: /* HI */
1231 case 3: /* LS */
1232 tcond = TCG_COND_LEU;
1233 goto done;
1234 case 4: /* CC */
1235 case 5: /* CS */
1236 tcond = TCG_COND_LTU;
1237 goto done;
1238 case 6: /* NE */
1239 case 7: /* EQ */
1240 tcond = TCG_COND_EQ;
1241 goto done;
1242 case 10: /* PL */
1243 case 11: /* MI */
1244 c->g1 = c->g2 = 0;
1245 c->v2 = tcg_const_i32(0);
1246 c->v1 = tmp = tcg_temp_new();
1247 tcg_gen_sub_i32(tmp, QREG_CC_N, QREG_CC_V);
db3d7945 1248 gen_ext(tmp, tmp, op - CC_OP_CMPB, 1);
9d896621
RH		 1249 /* fallthru */
1250 case 12: /* GE */
1251 case 13: /* LT */
1252 tcond = TCG_COND_LT;
1253 goto done;
1254 case 14: /* GT */
1255 case 15: /* LE */
1256 tcond = TCG_COND_LE;
1257 goto done;
1258 }
1259 }
6a432295
RH		 1260
1261 c->g1 = 1;
1262 c->g2 = 0;
1263 c->v2 = tcg_const_i32(0);
1264
e6e5906b
PB		 1265 switch (cond) {
1266 case 0: /* T */
e6e5906b 1267 case 1: /* F */
6a432295
RH		 1268 c->v1 = c->v2;
1269 tcond = TCG_COND_NEVER;
9d896621
RH		 1270 goto done;
1271 case 14: /* GT (!(Z || (N ^ V))) */
1272 case 15: /* LE (Z || (N ^ V)) */
1273 /* Logic operations clear V, which simplifies LE to (Z || N),
1274 and since Z and N are co-located, this becomes a normal
1275 comparison vs N. */
1276 if (op == CC_OP_LOGIC) {
1277 c->v1 = QREG_CC_N;
1278 tcond = TCG_COND_LE;
1279 goto done;
1280 }
6a432295 1281 break;
9d896621
RH		 1282 case 12: /* GE (!(N ^ V)) */
1283 case 13: /* LT (N ^ V) */
1284 /* Logic operations clear V, which simplifies this to N. */
1285 if (op != CC_OP_LOGIC) {
1286 break;
1287 }
1288 /* fallthru */
1289 case 10: /* PL (!N) */
1290 case 11: /* MI (N) */
1291 /* Several cases represent N normally. */
db3d7945
LV		 1292 if (op == CC_OP_ADDB || op == CC_OP_ADDW || op == CC_OP_ADDL ||
1293 op == CC_OP_SUBB || op == CC_OP_SUBW || op == CC_OP_SUBL ||
1294 op == CC_OP_LOGIC) {
9d896621
RH		 1295 c->v1 = QREG_CC_N;
1296 tcond = TCG_COND_LT;
1297 goto done;
1298 }
1299 break;
1300 case 6: /* NE (!Z) */
1301 case 7: /* EQ (Z) */
1302 /* Some cases fold Z into N. */
db3d7945
LV		 1303 if (op == CC_OP_ADDB || op == CC_OP_ADDW || op == CC_OP_ADDL ||
1304 op == CC_OP_SUBB || op == CC_OP_SUBW || op == CC_OP_SUBL ||
1305 op == CC_OP_LOGIC) {
9d896621
RH		 1306 tcond = TCG_COND_EQ;
1307 c->v1 = QREG_CC_N;
1308 goto done;
1309 }
1310 break;
1311 case 4: /* CC (!C) */
1312 case 5: /* CS (C) */
1313 /* Some cases fold C into X. */
db3d7945 1314 if (op == CC_OP_ADDB || op == CC_OP_ADDW || op == CC_OP_ADDL ||
4b5660e4 1315 op == CC_OP_SUBB || op == CC_OP_SUBW || op == CC_OP_SUBL) {
9d896621
RH		 1316 tcond = TCG_COND_NE;
1317 c->v1 = QREG_CC_X;
1318 goto done;
1319 }
1320 /* fallthru */
1321 case 8: /* VC (!V) */
1322 case 9: /* VS (V) */
1323 /* Logic operations clear V and C. */
1324 if (op == CC_OP_LOGIC) {
1325 tcond = TCG_COND_NEVER;
1326 c->v1 = c->v2;
1327 goto done;
1328 }
1329 break;
1330 }
1331
1332 /* Otherwise, flush flag state to CC_OP_FLAGS. */
1333 gen_flush_flags(s);
1334
1335 switch (cond) {
1336 case 0: /* T */
1337 case 1: /* F */
1338 default:
1339 /* Invalid, or handled above. */
1340 abort();
620c6cf6 1341 case 2: /* HI (!C && !Z) -> !(C || Z)*/
e6e5906b 1342 case 3: /* LS (C || Z) */
6a432295
RH		 1343 c->v1 = tmp = tcg_temp_new();
1344 c->g1 = 0;
1345 tcg_gen_setcond_i32(TCG_COND_EQ, tmp, QREG_CC_Z, c->v2);
620c6cf6 1346 tcg_gen_or_i32(tmp, tmp, QREG_CC_C);
6a432295 1347 tcond = TCG_COND_NE;
e6e5906b
PB		 1348 break;
1349 case 4: /* CC (!C) */
e6e5906b 1350 case 5: /* CS (C) */
6a432295
RH		 1351 c->v1 = QREG_CC_C;
1352 tcond = TCG_COND_NE;
e6e5906b
PB		 1353 break;
1354 case 6: /* NE (!Z) */
e6e5906b 1355 case 7: /* EQ (Z) */
6a432295
RH		 1356 c->v1 = QREG_CC_Z;
1357 tcond = TCG_COND_EQ;
e6e5906b
PB		 1358 break;
1359 case 8: /* VC (!V) */
e6e5906b 1360 case 9: /* VS (V) */
6a432295
RH		 1361 c->v1 = QREG_CC_V;
1362 tcond = TCG_COND_LT;
e6e5906b
PB		 1363 break;
1364 case 10: /* PL (!N) */
e6e5906b 1365 case 11: /* MI (N) */
6a432295
RH		 1366 c->v1 = QREG_CC_N;
1367 tcond = TCG_COND_LT;
e6e5906b
PB		 1368 break;
1369 case 12: /* GE (!(N ^ V)) */
e6e5906b 1370 case 13: /* LT (N ^ V) */
6a432295
RH		 1371 c->v1 = tmp = tcg_temp_new();
1372 c->g1 = 0;
620c6cf6 1373 tcg_gen_xor_i32(tmp, QREG_CC_N, QREG_CC_V);
6a432295 1374 tcond = TCG_COND_LT;
e6e5906b
PB		 1375 break;
1376 case 14: /* GT (!(Z || (N ^ V))) */
e6e5906b 1377 case 15: /* LE (Z || (N ^ V)) */
6a432295
RH		 1378 c->v1 = tmp = tcg_temp_new();
1379 c->g1 = 0;
1380 tcg_gen_setcond_i32(TCG_COND_EQ, tmp, QREG_CC_Z, c->v2);
620c6cf6
RH		 1381 tcg_gen_neg_i32(tmp, tmp);
1382 tmp2 = tcg_temp_new();
1383 tcg_gen_xor_i32(tmp2, QREG_CC_N, QREG_CC_V);
1384 tcg_gen_or_i32(tmp, tmp, tmp2);
6a432295
RH		 1385 tcg_temp_free(tmp2);
1386 tcond = TCG_COND_LT;
e6e5906b 1387 break;
e6e5906b 1388 }
9d896621
RH		 1389
1390 done:
6a432295
RH		 1391 if ((cond & 1) == 0) {
1392 tcond = tcg_invert_cond(tcond);
1393 }
1394 c->tcond = tcond;
1395}
1396
1397static void free_cond(DisasCompare *c)
1398{
1399 if (!c->g1) {
1400 tcg_temp_free(c->v1);
1401 }
1402 if (!c->g2) {
1403 tcg_temp_free(c->v2);
1404 }
1405}
1406
1407static void gen_jmpcc(DisasContext *s, int cond, TCGLabel *l1)
1408{
1409 DisasCompare c;
1410
1411 gen_cc_cond(&c, s, cond);
1412 update_cc_op(s);
1413 tcg_gen_brcond_i32(c.tcond, c.v1, c.v2, l1);
1414 free_cond(&c);
e6e5906b
PB		 1415}
1416
0633879f
PB		 1417/* Force a TB lookup after an instruction that changes the CPU state. */
1418static void gen_lookup_tb(DisasContext *s)
1419{
9fdb533f 1420 update_cc_op(s);
e1f3808e 1421 tcg_gen_movi_i32(QREG_PC, s->pc);
0633879f
PB		 1422 s->is_jmp = DISAS_UPDATE;
1423}
1424
d4d79bb1
BS		 1425#define SRC_EA(env, result, opsize, op_sign, addrp) do { \
1426 result = gen_ea(env, s, insn, opsize, NULL_QREG, addrp, \
1427 op_sign ? EA_LOADS : EA_LOADU); \
1428 if (IS_NULL_QREG(result)) { \
1429 gen_addr_fault(s); \
1430 return; \
1431 } \
510ff0b7
PB		 1432 } while (0)
1433
d4d79bb1
BS		 1434#define DEST_EA(env, insn, opsize, val, addrp) do { \
1435 TCGv ea_result = gen_ea(env, s, insn, opsize, val, addrp, EA_STORE); \
1436 if (IS_NULL_QREG(ea_result)) { \
1437 gen_addr_fault(s); \
1438 return; \
1439 } \
510ff0b7
PB		 1440 } while (0)
1441
90aa39a1
SF		 1442static inline bool use_goto_tb(DisasContext *s, uint32_t dest)
1443{
1444#ifndef CONFIG_USER_ONLY
1445 return (s->tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) ||
1446 (s->insn_pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK);
1447#else
1448 return true;
1449#endif
1450}
1451
e6e5906b
PB		 1452/* Generate a jump to an immediate address. */
1453static void gen_jmp_tb(DisasContext *s, int n, uint32_t dest)
1454{
551bd27f 1455 if (unlikely(s->singlestep_enabled)) {
e6e5906b 1456 gen_exception(s, dest, EXCP_DEBUG);
90aa39a1 1457 } else if (use_goto_tb(s, dest)) {
57fec1fe 1458 tcg_gen_goto_tb(n);
e1f3808e 1459 tcg_gen_movi_i32(QREG_PC, dest);
90aa39a1 1460 tcg_gen_exit_tb((uintptr_t)s->tb + n);
e6e5906b 1461 } else {
e1f3808e 1462 gen_jmp_im(s, dest);
57fec1fe 1463 tcg_gen_exit_tb(0);
e6e5906b
PB		 1464 }
1465 s->is_jmp = DISAS_TB_JUMP;
1466}
1467
d5a3cf33
LV		 1468DISAS_INSN(scc)
1469{
1470 DisasCompare c;
1471 int cond;
1472 TCGv tmp;
1473
1474 cond = (insn >> 8) & 0xf;
1475 gen_cc_cond(&c, s, cond);
1476
1477 tmp = tcg_temp_new();
1478 tcg_gen_setcond_i32(c.tcond, tmp, c.v1, c.v2);
1479 free_cond(&c);
1480
1481 tcg_gen_neg_i32(tmp, tmp);
1482 DEST_EA(env, insn, OS_BYTE, tmp, NULL);
1483 tcg_temp_free(tmp);
1484}
1485
beff27ab
LV		 1486DISAS_INSN(dbcc)
1487{
1488 TCGLabel *l1;
1489 TCGv reg;
1490 TCGv tmp;
1491 int16_t offset;
1492 uint32_t base;
1493
1494 reg = DREG(insn, 0);
1495 base = s->pc;
1496 offset = (int16_t)read_im16(env, s);
1497 l1 = gen_new_label();
1498 gen_jmpcc(s, (insn >> 8) & 0xf, l1);
1499
1500 tmp = tcg_temp_new();
1501 tcg_gen_ext16s_i32(tmp, reg);
1502 tcg_gen_addi_i32(tmp, tmp, -1);
1503 gen_partset_reg(OS_WORD, reg, tmp);
1504 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, -1, l1);
1505 gen_jmp_tb(s, 1, base + offset);
1506 gen_set_label(l1);
1507 gen_jmp_tb(s, 0, s->pc);
1508}
1509
e6e5906b
PB		 1510DISAS_INSN(undef_mac)
1511{
1512 gen_exception(s, s->pc - 2, EXCP_LINEA);
1513}
1514
1515DISAS_INSN(undef_fpu)
1516{
1517 gen_exception(s, s->pc - 2, EXCP_LINEF);
1518}
1519
1520DISAS_INSN(undef)
1521{
72d2e4b6
RH		 1522 /* ??? This is both instructions that are as yet unimplemented
1523 for the 680x0 series, as well as those that are implemented
1524 but actually illegal for CPU32 or pre-68020. */
1525 qemu_log_mask(LOG_UNIMP, "Illegal instruction: %04x @ %08x",
1526 insn, s->pc - 2);
e6e5906b 1527 gen_exception(s, s->pc - 2, EXCP_UNSUPPORTED);
e6e5906b
PB		 1528}
1529
1530DISAS_INSN(mulw)
1531{
e1f3808e
PB		 1532 TCGv reg;
1533 TCGv tmp;
1534 TCGv src;
e6e5906b
PB		 1535 int sign;
1536
1537 sign = (insn & 0x100) != 0;
1538 reg = DREG(insn, 9);
a7812ae4 1539 tmp = tcg_temp_new();
e6e5906b 1540 if (sign)
e1f3808e 1541 tcg_gen_ext16s_i32(tmp, reg);
e6e5906b 1542 else
e1f3808e 1543 tcg_gen_ext16u_i32(tmp, reg);
d4d79bb1 1544 SRC_EA(env, src, OS_WORD, sign, NULL);
e1f3808e
PB		 1545 tcg_gen_mul_i32(tmp, tmp, src);
1546 tcg_gen_mov_i32(reg, tmp);
4a18cd44 1547 gen_logic_cc(s, tmp, OS_LONG);
2b5e2170 1548 tcg_temp_free(tmp);
e6e5906b
PB		 1549}
1550
1551DISAS_INSN(divw)
1552{
e6e5906b 1553 int sign;
0ccb9c1d
LV		 1554 TCGv src;
1555 TCGv destr;
1556
1557 /* divX.w <EA>,Dn 32/16 -> 16r:16q */
e6e5906b
PB		 1558
1559 sign = (insn & 0x100) != 0;
0ccb9c1d
LV		 1560
1561 /* dest.l / src.w */
1562
d4d79bb1 1563 SRC_EA(env, src, OS_WORD, sign, NULL);
0ccb9c1d 1564 destr = tcg_const_i32(REG(insn, 9));
e6e5906b 1565 if (sign) {
0ccb9c1d 1566 gen_helper_divsw(cpu_env, destr, src);
e6e5906b 1567 } else {
0ccb9c1d 1568 gen_helper_divuw(cpu_env, destr, src);
e6e5906b 1569 }
0ccb9c1d 1570 tcg_temp_free(destr);
620c6cf6 1571
9fdb533f 1572 set_cc_op(s, CC_OP_FLAGS);
e6e5906b
PB		 1573}
1574
1575DISAS_INSN(divl)
1576{
0ccb9c1d
LV		 1577 TCGv num, reg, den;
1578 int sign;
e6e5906b
PB		 1579 uint16_t ext;
1580
28b68cd7 1581 ext = read_im16(env, s);
0ccb9c1d
LV		 1582
1583 sign = (ext & 0x0800) != 0;
1584
1585 if (ext & 0x400) {
1586 if (!m68k_feature(s->env, M68K_FEATURE_QUAD_MULDIV)) {
1587 gen_exception(s, s->insn_pc, EXCP_ILLEGAL);
1588 return;
1589 }
1590
1591 /* divX.l <EA>, Dr:Dq 64/32 -> 32r:32q */
1592
1593 SRC_EA(env, den, OS_LONG, 0, NULL);
1594 num = tcg_const_i32(REG(ext, 12));
1595 reg = tcg_const_i32(REG(ext, 0));
1596 if (sign) {
1597 gen_helper_divsll(cpu_env, num, reg, den);
1598 } else {
1599 gen_helper_divull(cpu_env, num, reg, den);
1600 }
1601 tcg_temp_free(reg);
1602 tcg_temp_free(num);
1603 set_cc_op(s, CC_OP_FLAGS);
e6e5906b
PB		 1604 return;
1605 }
0ccb9c1d
LV		 1606
1607 /* divX.l <EA>, Dq 32/32 -> 32q */
1608 /* divXl.l <EA>, Dr:Dq 32/32 -> 32r:32q */
1609
d4d79bb1 1610 SRC_EA(env, den, OS_LONG, 0, NULL);
0ccb9c1d
LV		 1611 num = tcg_const_i32(REG(ext, 12));
1612 reg = tcg_const_i32(REG(ext, 0));
1613 if (sign) {
1614 gen_helper_divsl(cpu_env, num, reg, den);
e6e5906b 1615 } else {
0ccb9c1d 1616 gen_helper_divul(cpu_env, num, reg, den);
e6e5906b 1617 }
0ccb9c1d
LV		 1618 tcg_temp_free(reg);
1619 tcg_temp_free(num);
1620
9fdb533f 1621 set_cc_op(s, CC_OP_FLAGS);
e6e5906b
PB		 1622}
1623
fb5543d8
LV		 1624static void bcd_add(TCGv dest, TCGv src)
1625{
1626 TCGv t0, t1;
1627
1628 /* dest10 = dest10 + src10 + X
1629 *
1630 * t1 = src
1631 * t2 = t1 + 0x066
1632 * t3 = t2 + dest + X
1633 * t4 = t2 ^ dest
1634 * t5 = t3 ^ t4
1635 * t6 = ~t5 & 0x110
1636 * t7 = (t6 >> 2) | (t6 >> 3)
1637 * return t3 - t7
1638 */
1639
1640 /* t1 = (src + 0x066) + dest + X
1641 * = result with some possible exceding 0x6
1642 */
1643
1644 t0 = tcg_const_i32(0x066);
1645 tcg_gen_add_i32(t0, t0, src);
1646
1647 t1 = tcg_temp_new();
1648 tcg_gen_add_i32(t1, t0, dest);
1649 tcg_gen_add_i32(t1, t1, QREG_CC_X);
1650
1651 /* we will remove exceding 0x6 where there is no carry */
1652
1653 /* t0 = (src + 0x0066) ^ dest
1654 * = t1 without carries
1655 */
1656
1657 tcg_gen_xor_i32(t0, t0, dest);
1658
1659 /* extract the carries
1660 * t0 = t0 ^ t1
1661 * = only the carries
1662 */
1663
1664 tcg_gen_xor_i32(t0, t0, t1);
1665
1666 /* generate 0x1 where there is no carry
1667 * and for each 0x10, generate a 0x6
1668 */
1669
1670 tcg_gen_shri_i32(t0, t0, 3);
1671 tcg_gen_not_i32(t0, t0);
1672 tcg_gen_andi_i32(t0, t0, 0x22);
1673 tcg_gen_add_i32(dest, t0, t0);
1674 tcg_gen_add_i32(dest, dest, t0);
1675 tcg_temp_free(t0);
1676
1677 /* remove the exceding 0x6
1678 * for digits that have not generated a carry
1679 */
1680
1681 tcg_gen_sub_i32(dest, t1, dest);
1682 tcg_temp_free(t1);
1683}
1684
1685static void bcd_sub(TCGv dest, TCGv src)
1686{
1687 TCGv t0, t1, t2;
1688
1689 /* dest10 = dest10 - src10 - X
1690 * = bcd_add(dest + 1 - X, 0x199 - src)
1691 */
1692
1693 /* t0 = 0x066 + (0x199 - src) */
1694
1695 t0 = tcg_temp_new();
1696 tcg_gen_subfi_i32(t0, 0x1ff, src);
1697
1698 /* t1 = t0 + dest + 1 - X*/
1699
1700 t1 = tcg_temp_new();
1701 tcg_gen_add_i32(t1, t0, dest);
1702 tcg_gen_addi_i32(t1, t1, 1);
1703 tcg_gen_sub_i32(t1, t1, QREG_CC_X);
1704
1705 /* t2 = t0 ^ dest */
1706
1707 t2 = tcg_temp_new();
1708 tcg_gen_xor_i32(t2, t0, dest);
1709
1710 /* t0 = t1 ^ t2 */
1711
1712 tcg_gen_xor_i32(t0, t1, t2);
1713
1714 /* t2 = ~t0 & 0x110
1715 * t0 = (t2 >> 2) | (t2 >> 3)
1716 *
1717 * to fit on 8bit operands, changed in:
1718 *
1719 * t2 = ~(t0 >> 3) & 0x22
1720 * t0 = t2 + t2
1721 * t0 = t0 + t2
1722 */
1723
1724 tcg_gen_shri_i32(t2, t0, 3);
1725 tcg_gen_not_i32(t2, t2);
1726 tcg_gen_andi_i32(t2, t2, 0x22);
1727 tcg_gen_add_i32(t0, t2, t2);
1728 tcg_gen_add_i32(t0, t0, t2);
1729 tcg_temp_free(t2);
1730
1731 /* return t1 - t0 */
1732
1733 tcg_gen_sub_i32(dest, t1, t0);
1734 tcg_temp_free(t0);
1735 tcg_temp_free(t1);
1736}
1737
1738static void bcd_flags(TCGv val)
1739{
1740 tcg_gen_andi_i32(QREG_CC_C, val, 0x0ff);
1741 tcg_gen_or_i32(QREG_CC_Z, QREG_CC_Z, QREG_CC_C);
1742
0d9acef2 1743 tcg_gen_extract_i32(QREG_CC_C, val, 8, 1);
fb5543d8
LV		 1744
1745 tcg_gen_mov_i32(QREG_CC_X, QREG_CC_C);
1746}
1747
1748DISAS_INSN(abcd_reg)
1749{
1750 TCGv src;
1751 TCGv dest;
1752
1753 gen_flush_flags(s); /* !Z is sticky */
1754
1755 src = gen_extend(DREG(insn, 0), OS_BYTE, 0);
1756 dest = gen_extend(DREG(insn, 9), OS_BYTE, 0);
1757 bcd_add(dest, src);
1758 gen_partset_reg(OS_BYTE, DREG(insn, 9), dest);
1759
1760 bcd_flags(dest);
1761}
1762
1763DISAS_INSN(abcd_mem)
1764{
1765 TCGv src, dest, addr;
1766
1767 gen_flush_flags(s); /* !Z is sticky */
1768
1769 /* Indirect pre-decrement load (mode 4) */
1770
1771 src = gen_ea_mode(env, s, 4, REG(insn, 0), OS_BYTE,
1772 NULL_QREG, NULL, EA_LOADU);
1773 dest = gen_ea_mode(env, s, 4, REG(insn, 9), OS_BYTE,
1774 NULL_QREG, &addr, EA_LOADU);
1775
1776 bcd_add(dest, src);
1777
1778 gen_ea_mode(env, s, 4, REG(insn, 9), OS_BYTE, dest, &addr, EA_STORE);
1779
1780 bcd_flags(dest);
1781}
1782
1783DISAS_INSN(sbcd_reg)
1784{
1785 TCGv src, dest;
1786
1787 gen_flush_flags(s); /* !Z is sticky */
1788
1789 src = gen_extend(DREG(insn, 0), OS_BYTE, 0);
1790 dest = gen_extend(DREG(insn, 9), OS_BYTE, 0);
1791
1792 bcd_sub(dest, src);
1793
1794 gen_partset_reg(OS_BYTE, DREG(insn, 9), dest);
1795
1796 bcd_flags(dest);
1797}
1798
1799DISAS_INSN(sbcd_mem)
1800{
1801 TCGv src, dest, addr;
1802
1803 gen_flush_flags(s); /* !Z is sticky */
1804
1805 /* Indirect pre-decrement load (mode 4) */
1806
1807 src = gen_ea_mode(env, s, 4, REG(insn, 0), OS_BYTE,
1808 NULL_QREG, NULL, EA_LOADU);
1809 dest = gen_ea_mode(env, s, 4, REG(insn, 9), OS_BYTE,
1810 NULL_QREG, &addr, EA_LOADU);
1811
1812 bcd_sub(dest, src);
1813
1814 gen_ea_mode(env, s, 4, REG(insn, 9), OS_BYTE, dest, &addr, EA_STORE);
1815
1816 bcd_flags(dest);
1817}
1818
1819DISAS_INSN(nbcd)
1820{
1821 TCGv src, dest;
1822 TCGv addr;
1823
1824 gen_flush_flags(s); /* !Z is sticky */
1825
1826 SRC_EA(env, src, OS_BYTE, 0, &addr);
1827
1828 dest = tcg_const_i32(0);
1829 bcd_sub(dest, src);
1830
1831 DEST_EA(env, insn, OS_BYTE, dest, &addr);
1832
1833 bcd_flags(dest);
1834
1835 tcg_temp_free(dest);
1836}
1837
e6e5906b
PB		 1838DISAS_INSN(addsub)
1839{
e1f3808e
PB		 1840 TCGv reg;
1841 TCGv dest;
1842 TCGv src;
1843 TCGv tmp;
1844 TCGv addr;
e6e5906b 1845 int add;
8a370c6c 1846 int opsize;
e6e5906b
PB		 1847
1848 add = (insn & 0x4000) != 0;
8a370c6c
LV		 1849 opsize = insn_opsize(insn);
1850 reg = gen_extend(DREG(insn, 9), opsize, 1);
a7812ae4 1851 dest = tcg_temp_new();
e6e5906b 1852 if (insn & 0x100) {
8a370c6c 1853 SRC_EA(env, tmp, opsize, 1, &addr);
e6e5906b
PB		 1854 src = reg;
1855 } else {
1856 tmp = reg;
8a370c6c 1857 SRC_EA(env, src, opsize, 1, NULL);
e6e5906b
PB		 1858 }
1859 if (add) {
e1f3808e 1860 tcg_gen_add_i32(dest, tmp, src);
f9083519 1861 tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, dest, src);
8a370c6c 1862 set_cc_op(s, CC_OP_ADDB + opsize);
e6e5906b 1863 } else {
f9083519 1864 tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, tmp, src);
e1f3808e 1865 tcg_gen_sub_i32(dest, tmp, src);
8a370c6c 1866 set_cc_op(s, CC_OP_SUBB + opsize);
e6e5906b 1867 }
8a370c6c 1868 gen_update_cc_add(dest, src, opsize);
e6e5906b 1869 if (insn & 0x100) {
8a370c6c 1870 DEST_EA(env, insn, opsize, dest, &addr);
e6e5906b 1871 } else {
8a370c6c 1872 gen_partset_reg(opsize, DREG(insn, 9), dest);
e6e5906b 1873 }
8a370c6c 1874 tcg_temp_free(dest);
e6e5906b
PB		 1875}
1876
e6e5906b
PB		 1877/* Reverse the order of the bits in REG. */
1878DISAS_INSN(bitrev)
1879{
e1f3808e 1880 TCGv reg;
e6e5906b 1881 reg = DREG(insn, 0);
e1f3808e 1882 gen_helper_bitrev(reg, reg);
e6e5906b
PB		 1883}
1884
1885DISAS_INSN(bitop_reg)
1886{
1887 int opsize;
1888 int op;
e1f3808e
PB		 1889 TCGv src1;
1890 TCGv src2;
1891 TCGv tmp;
1892 TCGv addr;
1893 TCGv dest;
e6e5906b
PB		 1894
1895 if ((insn & 0x38) != 0)
1896 opsize = OS_BYTE;
1897 else
1898 opsize = OS_LONG;
1899 op = (insn >> 6) & 3;
d4d79bb1 1900 SRC_EA(env, src1, opsize, 0, op ? &addr: NULL);
e6e5906b 1901
3c980d2e
LV		 1902 gen_flush_flags(s);
1903 src2 = tcg_temp_new();
e6e5906b 1904 if (opsize == OS_BYTE)
3c980d2e 1905 tcg_gen_andi_i32(src2, DREG(insn, 9), 7);
e6e5906b 1906 else
3c980d2e 1907 tcg_gen_andi_i32(src2, DREG(insn, 9), 31);
620c6cf6 1908
3c980d2e
LV		 1909 tmp = tcg_const_i32(1);
1910 tcg_gen_shl_i32(tmp, tmp, src2);
1911 tcg_temp_free(src2);
620c6cf6 1912
3c980d2e 1913 tcg_gen_and_i32(QREG_CC_Z, src1, tmp);
620c6cf6 1914
3c980d2e 1915 dest = tcg_temp_new();
e6e5906b
PB		 1916 switch (op) {
1917 case 1: /* bchg */
3c980d2e 1918 tcg_gen_xor_i32(dest, src1, tmp);
e6e5906b
PB		 1919 break;
1920 case 2: /* bclr */
3c980d2e 1921 tcg_gen_andc_i32(dest, src1, tmp);
e6e5906b
PB		 1922 break;
1923 case 3: /* bset */
3c980d2e 1924 tcg_gen_or_i32(dest, src1, tmp);
e6e5906b
PB		 1925 break;
1926 default: /* btst */
1927 break;
1928 }
3c980d2e 1929 tcg_temp_free(tmp);
620c6cf6 1930 if (op) {
d4d79bb1 1931 DEST_EA(env, insn, opsize, dest, &addr);
620c6cf6
RH		 1932 }
1933 tcg_temp_free(dest);
e6e5906b
PB		 1934}
1935
1936DISAS_INSN(sats)
1937{
e1f3808e 1938 TCGv reg;
e6e5906b 1939 reg = DREG(insn, 0);
e6e5906b 1940 gen_flush_flags(s);
620c6cf6 1941 gen_helper_sats(reg, reg, QREG_CC_V);
5dbb6784 1942 gen_logic_cc(s, reg, OS_LONG);
e6e5906b
PB		 1943}
1944
e1f3808e 1945static void gen_push(DisasContext *s, TCGv val)
e6e5906b 1946{
e1f3808e 1947 TCGv tmp;
e6e5906b 1948
a7812ae4 1949 tmp = tcg_temp_new();
e1f3808e 1950 tcg_gen_subi_i32(tmp, QREG_SP, 4);
0633879f 1951 gen_store(s, OS_LONG, tmp, val);
e1f3808e 1952 tcg_gen_mov_i32(QREG_SP, tmp);
2b5e2170 1953 tcg_temp_free(tmp);
e6e5906b
PB		 1954}
1955
7b542eb9
LV		 1956static TCGv mreg(int reg)
1957{
1958 if (reg < 8) {
1959 /* Dx */
1960 return cpu_dregs[reg];
1961 }
1962 /* Ax */
1963 return cpu_aregs[reg & 7];
1964}
1965
e6e5906b
PB		 1966DISAS_INSN(movem)
1967{
7b542eb9
LV		 1968 TCGv addr, incr, tmp, r[16];
1969 int is_load = (insn & 0x0400) != 0;
1970 int opsize = (insn & 0x40) != 0 ? OS_LONG : OS_WORD;
1971 uint16_t mask = read_im16(env, s);
1972 int mode = extract32(insn, 3, 3);
1973 int reg0 = REG(insn, 0);
e6e5906b 1974 int i;
e6e5906b 1975
7b542eb9
LV		 1976 tmp = cpu_aregs[reg0];
1977
1978 switch (mode) {
1979 case 0: /* data register direct */
1980 case 1: /* addr register direct */
1981 do_addr_fault:
510ff0b7
PB		 1982 gen_addr_fault(s);
1983 return;
7b542eb9
LV		 1984
1985 case 2: /* indirect */
1986 break;
1987
1988 case 3: /* indirect post-increment */
1989 if (!is_load) {
1990 /* post-increment is not allowed */
1991 goto do_addr_fault;
1992 }
1993 break;
1994
1995 case 4: /* indirect pre-decrement */
1996 if (is_load) {
1997 /* pre-decrement is not allowed */
1998 goto do_addr_fault;
1999 }
2000 /* We want a bare copy of the address reg, without any pre-decrement
2001 adjustment, as gen_lea would provide. */
2002 break;
2003
2004 default:
2005 tmp = gen_lea_mode(env, s, mode, reg0, opsize);
2006 if (IS_NULL_QREG(tmp)) {
2007 goto do_addr_fault;
2008 }
2009 break;
510ff0b7 2010 }
7b542eb9 2011
a7812ae4 2012 addr = tcg_temp_new();
e1f3808e 2013 tcg_gen_mov_i32(addr, tmp);
7b542eb9
LV		 2014 incr = tcg_const_i32(opsize_bytes(opsize));
2015
2016 if (is_load) {
2017 /* memory to register */
2018 for (i = 0; i < 16; i++) {
2019 if (mask & (1 << i)) {
2020 r[i] = gen_load(s, opsize, addr, 1);
2021 tcg_gen_add_i32(addr, addr, incr);
2022 }
2023 }
2024 for (i = 0; i < 16; i++) {
2025 if (mask & (1 << i)) {
2026 tcg_gen_mov_i32(mreg(i), r[i]);
2027 tcg_temp_free(r[i]);
2028 }
2029 }
2030 if (mode == 3) {
2031 /* post-increment: movem (An)+,X */
2032 tcg_gen_mov_i32(cpu_aregs[reg0], addr);
2033 }
2034 } else {
2035 /* register to memory */
2036 if (mode == 4) {
2037 /* pre-decrement: movem X,-(An) */
2038 for (i = 15; i >= 0; i--) {
2039 if ((mask << i) & 0x8000) {
2040 tcg_gen_sub_i32(addr, addr, incr);
2041 if (reg0 + 8 == i &&
2042 m68k_feature(s->env, M68K_FEATURE_EXT_FULL)) {
2043 /* M68020+: if the addressing register is the
2044 * register moved to memory, the value written
2045 * is the initial value decremented by the size of
2046 * the operation, regardless of how many actual
2047 * stores have been performed until this point.
2048 * M68000/M68010: the value is the initial value.
2049 */
2050 tmp = tcg_temp_new();
2051 tcg_gen_sub_i32(tmp, cpu_aregs[reg0], incr);
2052 gen_store(s, opsize, addr, tmp);
2053 tcg_temp_free(tmp);
2054 } else {
2055 gen_store(s, opsize, addr, mreg(i));
2056 }
2057 }
2058 }
2059 tcg_gen_mov_i32(cpu_aregs[reg0], addr);
2060 } else {
2061 for (i = 0; i < 16; i++) {
2062 if (mask & (1 << i)) {
2063 gen_store(s, opsize, addr, mreg(i));
2064 tcg_gen_add_i32(addr, addr, incr);
2065 }
e6e5906b 2066 }
e6e5906b
PB		 2067 }
2068 }
7b542eb9
LV		 2069
2070 tcg_temp_free(incr);
2071 tcg_temp_free(addr);
e6e5906b
PB		 2072}
2073
2074DISAS_INSN(bitop_im)
2075{
2076 int opsize;
2077 int op;
e1f3808e 2078 TCGv src1;
e6e5906b
PB		 2079 uint32_t mask;
2080 int bitnum;
e1f3808e
PB		 2081 TCGv tmp;
2082 TCGv addr;
e6e5906b
PB		 2083
2084 if ((insn & 0x38) != 0)
2085 opsize = OS_BYTE;
2086 else
2087 opsize = OS_LONG;
2088 op = (insn >> 6) & 3;
2089
28b68cd7 2090 bitnum = read_im16(env, s);
fe53c2be
LV		 2091 if (m68k_feature(s->env, M68K_FEATURE_M68000)) {
2092 if (bitnum & 0xfe00) {
2093 disas_undef(env, s, insn);
2094 return;
2095 }
2096 } else {
2097 if (bitnum & 0xff00) {
2098 disas_undef(env, s, insn);
2099 return;
2100 }
e6e5906b
PB		 2101 }
2102
d4d79bb1 2103 SRC_EA(env, src1, opsize, 0, op ? &addr: NULL);
e6e5906b 2104
3c980d2e 2105 gen_flush_flags(s);
e6e5906b
PB		 2106 if (opsize == OS_BYTE)
2107 bitnum &= 7;
2108 else
2109 bitnum &= 31;
2110 mask = 1 << bitnum;
2111
3c980d2e 2112 tcg_gen_andi_i32(QREG_CC_Z, src1, mask);
620c6cf6 2113
e1f3808e 2114 if (op) {
620c6cf6 2115 tmp = tcg_temp_new();
e1f3808e
PB		 2116 switch (op) {
2117 case 1: /* bchg */
2118 tcg_gen_xori_i32(tmp, src1, mask);
2119 break;
2120 case 2: /* bclr */
2121 tcg_gen_andi_i32(tmp, src1, ~mask);
2122 break;
2123 case 3: /* bset */
2124 tcg_gen_ori_i32(tmp, src1, mask);
2125 break;
2126 default: /* btst */
2127 break;
2128 }
d4d79bb1 2129 DEST_EA(env, insn, opsize, tmp, &addr);
620c6cf6 2130 tcg_temp_free(tmp);
e6e5906b 2131 }
e6e5906b 2132}
620c6cf6 2133
e6e5906b
PB		 2134DISAS_INSN(arith_im)
2135{
2136 int op;
92c62548 2137 TCGv im;
e1f3808e
PB		 2138 TCGv src1;
2139 TCGv dest;
2140 TCGv addr;
92c62548 2141 int opsize;
e6e5906b
PB		 2142
2143 op = (insn >> 9) & 7;
92c62548
LV		 2144 opsize = insn_opsize(insn);
2145 switch (opsize) {
2146 case OS_BYTE:
2147 im = tcg_const_i32((int8_t)read_im8(env, s));
2148 break;
2149 case OS_WORD:
2150 im = tcg_const_i32((int16_t)read_im16(env, s));
2151 break;
2152 case OS_LONG:
2153 im = tcg_const_i32(read_im32(env, s));
2154 break;
2155 default:
2156 abort();
2157 }
2158 SRC_EA(env, src1, opsize, 1, (op == 6) ? NULL : &addr);
a7812ae4 2159 dest = tcg_temp_new();
e6e5906b
PB		 2160 switch (op) {
2161 case 0: /* ori */
92c62548
LV		 2162 tcg_gen_or_i32(dest, src1, im);
2163 gen_logic_cc(s, dest, opsize);
e6e5906b
PB		 2164 break;
2165 case 1: /* andi */
92c62548
LV		 2166 tcg_gen_and_i32(dest, src1, im);
2167 gen_logic_cc(s, dest, opsize);
e6e5906b
PB		 2168 break;
2169 case 2: /* subi */
92c62548
LV		 2170 tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, src1, im);
2171 tcg_gen_sub_i32(dest, src1, im);
2172 gen_update_cc_add(dest, im, opsize);
2173 set_cc_op(s, CC_OP_SUBB + opsize);
e6e5906b
PB		 2174 break;
2175 case 3: /* addi */
92c62548
LV		 2176 tcg_gen_add_i32(dest, src1, im);
2177 gen_update_cc_add(dest, im, opsize);
2178 tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, dest, im);
2179 set_cc_op(s, CC_OP_ADDB + opsize);
e6e5906b
PB		 2180 break;
2181 case 5: /* eori */
92c62548
LV		 2182 tcg_gen_xor_i32(dest, src1, im);
2183 gen_logic_cc(s, dest, opsize);
e6e5906b
PB		 2184 break;
2185 case 6: /* cmpi */
92c62548 2186 gen_update_cc_cmp(s, src1, im, opsize);
e6e5906b
PB		 2187 break;
2188 default:
2189 abort();
2190 }
92c62548 2191 tcg_temp_free(im);
e6e5906b 2192 if (op != 6) {
92c62548 2193 DEST_EA(env, insn, opsize, dest, &addr);
e6e5906b 2194 }
92c62548 2195 tcg_temp_free(dest);
e6e5906b
PB		 2196}
2197
14f94406
LV		 2198DISAS_INSN(cas)
2199{
2200 int opsize;
2201 TCGv addr;
2202 uint16_t ext;
2203 TCGv load;
2204 TCGv cmp;
2205 TCGMemOp opc;
2206
2207 switch ((insn >> 9) & 3) {
2208 case 1:
2209 opsize = OS_BYTE;
2210 opc = MO_SB;
2211 break;
2212 case 2:
2213 opsize = OS_WORD;
2214 opc = MO_TESW;
2215 break;
2216 case 3:
2217 opsize = OS_LONG;
2218 opc = MO_TESL;
2219 break;
2220 default:
2221 g_assert_not_reached();
2222 }
14f94406
LV		 2223
2224 ext = read_im16(env, s);
2225
2226 /* cas Dc,Du,<EA> */
2227
2228 addr = gen_lea(env, s, insn, opsize);
2229 if (IS_NULL_QREG(addr)) {
2230 gen_addr_fault(s);
2231 return;
2232 }
2233
2234 cmp = gen_extend(DREG(ext, 0), opsize, 1);
2235
2236 /* if <EA> == Dc then
2237 * <EA> = Du
2238 * Dc = <EA> (because <EA> == Dc)
2239 * else
2240 * Dc = <EA>
2241 */
2242
2243 load = tcg_temp_new();
2244 tcg_gen_atomic_cmpxchg_i32(load, addr, cmp, DREG(ext, 6),
2245 IS_USER(s), opc);
2246 /* update flags before setting cmp to load */
2247 gen_update_cc_cmp(s, load, cmp, opsize);
2248 gen_partset_reg(opsize, DREG(ext, 0), load);
2249
2250 tcg_temp_free(load);
308feb93
LV		 2251
2252 switch (extract32(insn, 3, 3)) {
2253 case 3: /* Indirect postincrement. */
2254 tcg_gen_addi_i32(AREG(insn, 0), addr, opsize_bytes(opsize));
2255 break;
2256 case 4: /* Indirect predecrememnt. */
2257 tcg_gen_mov_i32(AREG(insn, 0), addr);
2258 break;
2259 }
14f94406
LV		 2260}
2261
2262DISAS_INSN(cas2w)
2263{
2264 uint16_t ext1, ext2;
2265 TCGv addr1, addr2;
2266 TCGv regs;
2267
2268 /* cas2 Dc1:Dc2,Du1:Du2,(Rn1):(Rn2) */
2269
2270 ext1 = read_im16(env, s);
2271
2272 if (ext1 & 0x8000) {
2273 /* Address Register */
2274 addr1 = AREG(ext1, 12);
2275 } else {
2276 /* Data Register */
2277 addr1 = DREG(ext1, 12);
2278 }
2279
2280 ext2 = read_im16(env, s);
2281 if (ext2 & 0x8000) {
2282 /* Address Register */
2283 addr2 = AREG(ext2, 12);
2284 } else {
2285 /* Data Register */
2286 addr2 = DREG(ext2, 12);
2287 }
2288
2289 /* if (R1) == Dc1 && (R2) == Dc2 then
2290 * (R1) = Du1
2291 * (R2) = Du2
2292 * else
2293 * Dc1 = (R1)
2294 * Dc2 = (R2)
2295 */
2296
2297 regs = tcg_const_i32(REG(ext2, 6) |
2298 (REG(ext1, 6) << 3) |
2299 (REG(ext2, 0) << 6) |
2300 (REG(ext1, 0) << 9));
f0ddf11b
EC		 2301 if (tb_cflags(s->tb) & CF_PARALLEL) {
2302 gen_helper_exit_atomic(cpu_env);
2303 } else {
2304 gen_helper_cas2w(cpu_env, regs, addr1, addr2);
2305 }
14f94406
LV		 2306 tcg_temp_free(regs);
2307
2308 /* Note that cas2w also assigned to env->cc_op. */
2309 s->cc_op = CC_OP_CMPW;
2310 s->cc_op_synced = 1;
2311}
2312
2313DISAS_INSN(cas2l)
2314{
2315 uint16_t ext1, ext2;
2316 TCGv addr1, addr2, regs;
2317
2318 /* cas2 Dc1:Dc2,Du1:Du2,(Rn1):(Rn2) */
2319
2320 ext1 = read_im16(env, s);
2321
2322 if (ext1 & 0x8000) {
2323 /* Address Register */
2324 addr1 = AREG(ext1, 12);
2325 } else {
2326 /* Data Register */
2327 addr1 = DREG(ext1, 12);
2328 }
2329
2330 ext2 = read_im16(env, s);
2331 if (ext2 & 0x8000) {
2332 /* Address Register */
2333 addr2 = AREG(ext2, 12);
2334 } else {
2335 /* Data Register */
2336 addr2 = DREG(ext2, 12);
2337 }
2338
2339 /* if (R1) == Dc1 && (R2) == Dc2 then
2340 * (R1) = Du1
2341 * (R2) = Du2
2342 * else
2343 * Dc1 = (R1)
2344 * Dc2 = (R2)
2345 */
2346
2347 regs = tcg_const_i32(REG(ext2, 6) |
2348 (REG(ext1, 6) << 3) |
2349 (REG(ext2, 0) << 6) |
2350 (REG(ext1, 0) << 9));
f0ddf11b
EC		 2351 if (tb_cflags(s->tb) & CF_PARALLEL) {
2352 gen_helper_cas2l_parallel(cpu_env, regs, addr1, addr2);
2353 } else {
2354 gen_helper_cas2l(cpu_env, regs, addr1, addr2);
2355 }
14f94406
LV		 2356 tcg_temp_free(regs);
2357
2358 /* Note that cas2l also assigned to env->cc_op. */
2359 s->cc_op = CC_OP_CMPL;
2360 s->cc_op_synced = 1;
2361}
2362
e6e5906b
PB		 2363DISAS_INSN(byterev)
2364{
e1f3808e 2365 TCGv reg;
e6e5906b
PB		 2366
2367 reg = DREG(insn, 0);
66896cb8 2368 tcg_gen_bswap32_i32(reg, reg);
e6e5906b
PB		 2369}
2370
2371DISAS_INSN(move)
2372{
e1f3808e
PB		 2373 TCGv src;
2374 TCGv dest;
e6e5906b
PB		 2375 int op;
2376 int opsize;
2377
2378 switch (insn >> 12) {
2379 case 1: /* move.b */
2380 opsize = OS_BYTE;
2381 break;
2382 case 2: /* move.l */
2383 opsize = OS_LONG;
2384 break;
2385 case 3: /* move.w */
2386 opsize = OS_WORD;
2387 break;
2388 default:
2389 abort();
2390 }
d4d79bb1 2391 SRC_EA(env, src, opsize, 1, NULL);
e6e5906b
PB		 2392 op = (insn >> 6) & 7;
2393 if (op == 1) {
2394 /* movea */
2395 /* The value will already have been sign extended. */
2396 dest = AREG(insn, 9);
e1f3808e 2397 tcg_gen_mov_i32(dest, src);
e6e5906b
PB		 2398 } else {
2399 /* normal move */
2400 uint16_t dest_ea;
2401 dest_ea = ((insn >> 9) & 7) | (op << 3);
d4d79bb1 2402 DEST_EA(env, dest_ea, opsize, src, NULL);
e6e5906b 2403 /* This will be correct because loads sign extend. */
5dbb6784 2404 gen_logic_cc(s, src, opsize);
e6e5906b
PB		 2405 }
2406}
2407
2408DISAS_INSN(negx)
2409{
a665a820
RH		 2410 TCGv z;
2411 TCGv src;
2412 TCGv addr;
2413 int opsize;
e6e5906b 2414
a665a820
RH		 2415 opsize = insn_opsize(insn);
2416 SRC_EA(env, src, opsize, 1, &addr);
2417
2418 gen_flush_flags(s); /* compute old Z */
2419
2420 /* Perform substract with borrow.
2421 * (X, N) = -(src + X);
2422 */
2423
2424 z = tcg_const_i32(0);
2425 tcg_gen_add2_i32(QREG_CC_N, QREG_CC_X, src, z, QREG_CC_X, z);
2426 tcg_gen_sub2_i32(QREG_CC_N, QREG_CC_X, z, z, QREG_CC_N, QREG_CC_X);
2427 tcg_temp_free(z);
2428 gen_ext(QREG_CC_N, QREG_CC_N, opsize, 1);
2429
2430 tcg_gen_andi_i32(QREG_CC_X, QREG_CC_X, 1);
2431
2432 /* Compute signed-overflow for negation. The normal formula for
2433 * subtraction is (res ^ src) & (src ^ dest), but with dest==0
2434 * this simplies to res & src.
2435 */
2436
2437 tcg_gen_and_i32(QREG_CC_V, QREG_CC_N, src);
2438
2439 /* Copy the rest of the results into place. */
2440 tcg_gen_or_i32(QREG_CC_Z, QREG_CC_Z, QREG_CC_N); /* !Z is sticky */
2441 tcg_gen_mov_i32(QREG_CC_C, QREG_CC_X);
2442
2443 set_cc_op(s, CC_OP_FLAGS);
2444
2445 /* result is in QREG_CC_N */
2446
2447 DEST_EA(env, insn, opsize, QREG_CC_N, &addr);
e6e5906b
PB		 2448}
2449
2450DISAS_INSN(lea)
2451{
e1f3808e
PB		 2452 TCGv reg;
2453 TCGv tmp;
e6e5906b
PB		 2454
2455 reg = AREG(insn, 9);
d4d79bb1 2456 tmp = gen_lea(env, s, insn, OS_LONG);
e1f3808e 2457 if (IS_NULL_QREG(tmp)) {
510ff0b7
PB		 2458 gen_addr_fault(s);
2459 return;
2460 }
e1f3808e 2461 tcg_gen_mov_i32(reg, tmp);
e6e5906b
PB		 2462}
2463
2464DISAS_INSN(clr)
2465{
2466 int opsize;
2b5e2170
LV		 2467 TCGv zero;
2468
2469 zero = tcg_const_i32(0);
e6e5906b 2470
7ef25cdd 2471 opsize = insn_opsize(insn);
2b5e2170
LV		 2472 DEST_EA(env, insn, opsize, zero, NULL);
2473 gen_logic_cc(s, zero, opsize);
2474 tcg_temp_free(zero);
e6e5906b
PB		 2475}
2476
e1f3808e 2477static TCGv gen_get_ccr(DisasContext *s)
e6e5906b 2478{
e1f3808e 2479 TCGv dest;
e6e5906b 2480
620c6cf6 2481 update_cc_op(s);
a7812ae4 2482 dest = tcg_temp_new();
620c6cf6 2483 gen_helper_get_ccr(dest, cpu_env);
0633879f
PB		 2484 return dest;
2485}
2486
2487DISAS_INSN(move_from_ccr)
2488{
e1f3808e 2489 TCGv ccr;
0633879f
PB		 2490
2491 ccr = gen_get_ccr(s);
7c0eb318 2492 DEST_EA(env, insn, OS_WORD, ccr, NULL);
e6e5906b
PB		 2493}
2494
2495DISAS_INSN(neg)
2496{
e1f3808e 2497 TCGv src1;
227de713
LV		 2498 TCGv dest;
2499 TCGv addr;
2500 int opsize;
e6e5906b 2501
227de713
LV		 2502 opsize = insn_opsize(insn);
2503 SRC_EA(env, src1, opsize, 1, &addr);
2504 dest = tcg_temp_new();
2505 tcg_gen_neg_i32(dest, src1);
2506 set_cc_op(s, CC_OP_SUBB + opsize);
2507 gen_update_cc_add(dest, src1, opsize);
2508 tcg_gen_setcondi_i32(TCG_COND_NE, QREG_CC_X, dest, 0);
2509 DEST_EA(env, insn, opsize, dest, &addr);
2510 tcg_temp_free(dest);
e6e5906b
PB		 2511}
2512
0633879f
PB		 2513static void gen_set_sr_im(DisasContext *s, uint16_t val, int ccr_only)
2514{
620c6cf6
RH		 2515 if (ccr_only) {
2516 tcg_gen_movi_i32(QREG_CC_C, val & CCF_C ? 1 : 0);
2517 tcg_gen_movi_i32(QREG_CC_V, val & CCF_V ? -1 : 0);
2518 tcg_gen_movi_i32(QREG_CC_Z, val & CCF_Z ? 0 : 1);
2519 tcg_gen_movi_i32(QREG_CC_N, val & CCF_N ? -1 : 0);
2520 tcg_gen_movi_i32(QREG_CC_X, val & CCF_X ? 1 : 0);
2521 } else {
2522 gen_helper_set_sr(cpu_env, tcg_const_i32(val));
0633879f 2523 }
9fdb533f 2524 set_cc_op(s, CC_OP_FLAGS);
0633879f
PB		 2525}
2526
620c6cf6
RH		 2527static void gen_set_sr(CPUM68KState *env, DisasContext *s, uint16_t insn,
2528 int ccr_only)
e6e5906b 2529{
620c6cf6
RH		 2530 if ((insn & 0x38) == 0) {
2531 if (ccr_only) {
2532 gen_helper_set_ccr(cpu_env, DREG(insn, 0));
2533 } else {
2534 gen_helper_set_sr(cpu_env, DREG(insn, 0));
2535 }
2536 set_cc_op(s, CC_OP_FLAGS);
2537 } else if ((insn & 0x3f) == 0x3c) {
2538 uint16_t val;
2539 val = read_im16(env, s);
2540 gen_set_sr_im(s, val, ccr_only);
2541 } else {
2542 disas_undef(env, s, insn);
7c0eb318
LV		 2543 }
2544}
e6e5906b 2545
7c0eb318 2546
0633879f
PB		 2547DISAS_INSN(move_to_ccr)
2548{
620c6cf6 2549 gen_set_sr(env, s, insn, 1);
0633879f
PB		 2550}
2551
e6e5906b
PB		 2552DISAS_INSN(not)
2553{
ea4f2a84
LV		 2554 TCGv src1;
2555 TCGv dest;
2556 TCGv addr;
2557 int opsize;
e6e5906b 2558
ea4f2a84
LV		 2559 opsize = insn_opsize(insn);
2560 SRC_EA(env, src1, opsize, 1, &addr);
2561 dest = tcg_temp_new();
2562 tcg_gen_not_i32(dest, src1);
2563 DEST_EA(env, insn, opsize, dest, &addr);
2564 gen_logic_cc(s, dest, opsize);
e6e5906b
PB		 2565}
2566
2567DISAS_INSN(swap)
2568{
e1f3808e
PB		 2569 TCGv src1;
2570 TCGv src2;
2571 TCGv reg;
e6e5906b 2572
a7812ae4
PB		 2573 src1 = tcg_temp_new();
2574 src2 = tcg_temp_new();
e6e5906b 2575 reg = DREG(insn, 0);
e1f3808e
PB		 2576 tcg_gen_shli_i32(src1, reg, 16);
2577 tcg_gen_shri_i32(src2, reg, 16);
2578 tcg_gen_or_i32(reg, src1, src2);
2b5e2170
LV		 2579 tcg_temp_free(src2);
2580 tcg_temp_free(src1);
5dbb6784 2581 gen_logic_cc(s, reg, OS_LONG);
e6e5906b
PB		 2582}
2583
71600eda
LV		 2584DISAS_INSN(bkpt)
2585{
2586 gen_exception(s, s->pc - 2, EXCP_DEBUG);
2587}
2588
e6e5906b
PB		 2589DISAS_INSN(pea)
2590{
e1f3808e 2591 TCGv tmp;
e6e5906b 2592
d4d79bb1 2593 tmp = gen_lea(env, s, insn, OS_LONG);
e1f3808e 2594 if (IS_NULL_QREG(tmp)) {
510ff0b7
PB		 2595 gen_addr_fault(s);
2596 return;
2597 }
0633879f 2598 gen_push(s, tmp);
e6e5906b
PB		 2599}
2600
2601DISAS_INSN(ext)
2602{
e6e5906b 2603 int op;
e1f3808e
PB		 2604 TCGv reg;
2605 TCGv tmp;
e6e5906b
PB		 2606
2607 reg = DREG(insn, 0);
2608 op = (insn >> 6) & 7;
a7812ae4 2609 tmp = tcg_temp_new();
e6e5906b 2610 if (op == 3)
e1f3808e 2611 tcg_gen_ext16s_i32(tmp, reg);
e6e5906b 2612 else
e1f3808e 2613 tcg_gen_ext8s_i32(tmp, reg);
e6e5906b
PB		 2614 if (op == 2)
2615 gen_partset_reg(OS_WORD, reg, tmp);
2616 else
e1f3808e 2617 tcg_gen_mov_i32(reg, tmp);
5dbb6784 2618 gen_logic_cc(s, tmp, OS_LONG);
2b5e2170 2619 tcg_temp_free(tmp);
e6e5906b
PB		 2620}
2621
2622DISAS_INSN(tst)
2623{
2624 int opsize;
e1f3808e 2625 TCGv tmp;
e6e5906b 2626
7ef25cdd 2627 opsize = insn_opsize(insn);
d4d79bb1 2628 SRC_EA(env, tmp, opsize, 1, NULL);
5dbb6784 2629 gen_logic_cc(s, tmp, opsize);
e6e5906b
PB		 2630}
2631
2632DISAS_INSN(pulse)
2633{
2634 /* Implemented as a NOP. */
2635}
2636
2637DISAS_INSN(illegal)
2638{
2639 gen_exception(s, s->pc - 2, EXCP_ILLEGAL);
2640}
2641
2642/* ??? This should be atomic. */
2643DISAS_INSN(tas)
2644{
e1f3808e
PB		 2645 TCGv dest;
2646 TCGv src1;
2647 TCGv addr;
e6e5906b 2648
a7812ae4 2649 dest = tcg_temp_new();
d4d79bb1 2650 SRC_EA(env, src1, OS_BYTE, 1, &addr);
5dbb6784 2651 gen_logic_cc(s, src1, OS_BYTE);
e1f3808e 2652 tcg_gen_ori_i32(dest, src1, 0x80);
d4d79bb1 2653 DEST_EA(env, insn, OS_BYTE, dest, &addr);
2b5e2170 2654 tcg_temp_free(dest);
e6e5906b
PB		 2655}
2656
2657DISAS_INSN(mull)
2658{
2659 uint16_t ext;
e1f3808e 2660 TCGv src1;
8be95def 2661 int sign;
e6e5906b 2662
28b68cd7 2663 ext = read_im16(env, s);
8be95def
LV		 2664
2665 sign = ext & 0x800;
2666
2667 if (ext & 0x400) {
2668 if (!m68k_feature(s->env, M68K_FEATURE_QUAD_MULDIV)) {
2669 gen_exception(s, s->pc - 4, EXCP_UNSUPPORTED);
2670 return;
2671 }
2672
2673 SRC_EA(env, src1, OS_LONG, 0, NULL);
2674
2675 if (sign) {
2676 tcg_gen_muls2_i32(QREG_CC_Z, QREG_CC_N, src1, DREG(ext, 12));
2677 } else {
2678 tcg_gen_mulu2_i32(QREG_CC_Z, QREG_CC_N, src1, DREG(ext, 12));
2679 }
2680 /* if Dl == Dh, 68040 returns low word */
2681 tcg_gen_mov_i32(DREG(ext, 0), QREG_CC_N);
2682 tcg_gen_mov_i32(DREG(ext, 12), QREG_CC_Z);
2683 tcg_gen_or_i32(QREG_CC_Z, QREG_CC_Z, QREG_CC_N);
2684
2685 tcg_gen_movi_i32(QREG_CC_V, 0);
2686 tcg_gen_movi_i32(QREG_CC_C, 0);
2687
2688 set_cc_op(s, CC_OP_FLAGS);
e6e5906b
PB		 2689 return;
2690 }
d4d79bb1 2691 SRC_EA(env, src1, OS_LONG, 0, NULL);
8be95def
LV		 2692 if (m68k_feature(s->env, M68K_FEATURE_M68000)) {
2693 tcg_gen_movi_i32(QREG_CC_C, 0);
2694 if (sign) {
2695 tcg_gen_muls2_i32(QREG_CC_N, QREG_CC_V, src1, DREG(ext, 12));
2696 /* QREG_CC_V is -(QREG_CC_V != (QREG_CC_N >> 31)) */
2697 tcg_gen_sari_i32(QREG_CC_Z, QREG_CC_N, 31);
2698 tcg_gen_setcond_i32(TCG_COND_NE, QREG_CC_V, QREG_CC_V, QREG_CC_Z);
2699 } else {
2700 tcg_gen_mulu2_i32(QREG_CC_N, QREG_CC_V, src1, DREG(ext, 12));
2701 /* QREG_CC_V is -(QREG_CC_V != 0), use QREG_CC_C as 0 */
2702 tcg_gen_setcond_i32(TCG_COND_NE, QREG_CC_V, QREG_CC_V, QREG_CC_C);
2703 }
2704 tcg_gen_neg_i32(QREG_CC_V, QREG_CC_V);
2705 tcg_gen_mov_i32(DREG(ext, 12), QREG_CC_N);
2706
2707 tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N);
2708
2709 set_cc_op(s, CC_OP_FLAGS);
2710 } else {
2711 /* The upper 32 bits of the product are discarded, so
2712 muls.l and mulu.l are functionally equivalent. */
2713 tcg_gen_mul_i32(DREG(ext, 12), src1, DREG(ext, 12));
2714 gen_logic_cc(s, DREG(ext, 12), OS_LONG);
2715 }
e6e5906b
PB		 2716}
2717
c630e436 2718static void gen_link(DisasContext *s, uint16_t insn, int32_t offset)
e6e5906b 2719{
e1f3808e
PB		 2720 TCGv reg;
2721 TCGv tmp;
e6e5906b 2722
e6e5906b 2723 reg = AREG(insn, 0);
a7812ae4 2724 tmp = tcg_temp_new();
e1f3808e 2725 tcg_gen_subi_i32(tmp, QREG_SP, 4);
0633879f 2726 gen_store(s, OS_LONG, tmp, reg);
c630e436 2727 if ((insn & 7) != 7) {
e1f3808e 2728 tcg_gen_mov_i32(reg, tmp);
c630e436 2729 }
e1f3808e 2730 tcg_gen_addi_i32(QREG_SP, tmp, offset);
c630e436
LV		 2731 tcg_temp_free(tmp);
2732}
2733
2734DISAS_INSN(link)
2735{
2736 int16_t offset;
2737
2738 offset = read_im16(env, s);
2739 gen_link(s, insn, offset);
2740}
2741
2742DISAS_INSN(linkl)
2743{
2744 int32_t offset;
2745
2746 offset = read_im32(env, s);
2747 gen_link(s, insn, offset);
e6e5906b
PB		 2748}
2749
2750DISAS_INSN(unlk)
2751{
e1f3808e
PB		 2752 TCGv src;
2753 TCGv reg;
2754 TCGv tmp;
e6e5906b 2755
a7812ae4 2756 src = tcg_temp_new();
e6e5906b 2757 reg = AREG(insn, 0);
e1f3808e 2758 tcg_gen_mov_i32(src, reg);
0633879f 2759 tmp = gen_load(s, OS_LONG, src, 0);
e1f3808e
PB		 2760 tcg_gen_mov_i32(reg, tmp);
2761 tcg_gen_addi_i32(QREG_SP, src, 4);
2b5e2170 2762 tcg_temp_free(src);
e6e5906b
PB		 2763}
2764
2765DISAS_INSN(nop)
2766{
2767}
2768
18059c9e
LV		 2769DISAS_INSN(rtd)
2770{
2771 TCGv tmp;
2772 int16_t offset = read_im16(env, s);
2773
2774 tmp = gen_load(s, OS_LONG, QREG_SP, 0);
2775 tcg_gen_addi_i32(QREG_SP, QREG_SP, offset + 4);
2776 gen_jmp(s, tmp);
2777}
2778
e6e5906b
PB		 2779DISAS_INSN(rts)
2780{
e1f3808e 2781 TCGv tmp;
e6e5906b 2782
0633879f 2783 tmp = gen_load(s, OS_LONG, QREG_SP, 0);
e1f3808e 2784 tcg_gen_addi_i32(QREG_SP, QREG_SP, 4);
e6e5906b
PB		 2785 gen_jmp(s, tmp);
2786}
2787
2788DISAS_INSN(jump)
2789{
e1f3808e 2790 TCGv tmp;
e6e5906b
PB		 2791
2792 /* Load the target address first to ensure correct exception
2793 behavior. */
d4d79bb1 2794 tmp = gen_lea(env, s, insn, OS_LONG);
e1f3808e 2795 if (IS_NULL_QREG(tmp)) {
510ff0b7
PB		 2796 gen_addr_fault(s);
2797 return;
2798 }
e6e5906b
PB		 2799 if ((insn & 0x40) == 0) {
2800 /* jsr */
351326a6 2801 gen_push(s, tcg_const_i32(s->pc));
e6e5906b
PB		 2802 }
2803 gen_jmp(s, tmp);
2804}
2805
2806DISAS_INSN(addsubq)
2807{
8a370c6c 2808 TCGv src;
e1f3808e 2809 TCGv dest;
8a370c6c
LV		 2810 TCGv val;
2811 int imm;
e1f3808e 2812 TCGv addr;
8a370c6c 2813 int opsize;
e6e5906b 2814
8a370c6c
LV		 2815 if ((insn & 070) == 010) {
2816 /* Operation on address register is always long. */
2817 opsize = OS_LONG;
2818 } else {
2819 opsize = insn_opsize(insn);
2820 }
2821 SRC_EA(env, src, opsize, 1, &addr);
2822 imm = (insn >> 9) & 7;
2823 if (imm == 0) {
2824 imm = 8;
2825 }
2826 val = tcg_const_i32(imm);
a7812ae4 2827 dest = tcg_temp_new();
8a370c6c 2828 tcg_gen_mov_i32(dest, src);
e6e5906b
PB		 2829 if ((insn & 0x38) == 0x08) {
2830 /* Don't update condition codes if the destination is an
2831 address register. */
2832 if (insn & 0x0100) {
8a370c6c 2833 tcg_gen_sub_i32(dest, dest, val);
e6e5906b 2834 } else {
8a370c6c 2835 tcg_gen_add_i32(dest, dest, val);
e6e5906b
PB		 2836 }
2837 } else {
2838 if (insn & 0x0100) {
8a370c6c
LV		 2839 tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, dest, val);
2840 tcg_gen_sub_i32(dest, dest, val);
2841 set_cc_op(s, CC_OP_SUBB + opsize);
e6e5906b 2842 } else {
8a370c6c
LV		 2843 tcg_gen_add_i32(dest, dest, val);
2844 tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, dest, val);
2845 set_cc_op(s, CC_OP_ADDB + opsize);
e6e5906b 2846 }
8a370c6c 2847 gen_update_cc_add(dest, val, opsize);
e6e5906b 2848 }
2b5e2170 2849 tcg_temp_free(val);
8a370c6c 2850 DEST_EA(env, insn, opsize, dest, &addr);
2b5e2170 2851 tcg_temp_free(dest);
e6e5906b
PB		 2852}
2853
2854DISAS_INSN(tpf)
2855{
2856 switch (insn & 7) {
2857 case 2: /* One extension word. */
2858 s->pc += 2;
2859 break;
2860 case 3: /* Two extension words. */
2861 s->pc += 4;
2862 break;
2863 case 4: /* No extension words. */
2864 break;
2865 default:
d4d79bb1 2866 disas_undef(env, s, insn);
e6e5906b
PB		 2867 }
2868}
2869
2870DISAS_INSN(branch)
2871{
2872 int32_t offset;
2873 uint32_t base;
2874 int op;
42a268c2 2875 TCGLabel *l1;
3b46e624 2876
e6e5906b
PB		 2877 base = s->pc;
2878 op = (insn >> 8) & 0xf;
2879 offset = (int8_t)insn;
2880 if (offset == 0) {
28b68cd7 2881 offset = (int16_t)read_im16(env, s);
e6e5906b 2882 } else if (offset == -1) {
d4d79bb1 2883 offset = read_im32(env, s);
e6e5906b
PB		 2884 }
2885 if (op == 1) {
2886 /* bsr */
351326a6 2887 gen_push(s, tcg_const_i32(s->pc));
e6e5906b 2888 }
e6e5906b
PB		 2889 if (op > 1) {
2890 /* Bcc */
2891 l1 = gen_new_label();
2892 gen_jmpcc(s, ((insn >> 8) & 0xf) ^ 1, l1);
2893 gen_jmp_tb(s, 1, base + offset);
2894 gen_set_label(l1);
2895 gen_jmp_tb(s, 0, s->pc);
2896 } else {
2897 /* Unconditional branch. */
7cd7b5ca 2898 update_cc_op(s);
e6e5906b
PB		 2899 gen_jmp_tb(s, 0, base + offset);
2900 }
2901}
2902
2903DISAS_INSN(moveq)
2904{
2b5e2170
LV		 2905 tcg_gen_movi_i32(DREG(insn, 9), (int8_t)insn);
2906 gen_logic_cc(s, DREG(insn, 9), OS_LONG);
e6e5906b
PB		 2907}
2908
2909DISAS_INSN(mvzs)
2910{
2911 int opsize;
e1f3808e
PB		 2912 TCGv src;
2913 TCGv reg;
e6e5906b
PB		 2914
2915 if (insn & 0x40)
2916 opsize = OS_WORD;
2917 else
2918 opsize = OS_BYTE;
d4d79bb1 2919 SRC_EA(env, src, opsize, (insn & 0x80) == 0, NULL);
e6e5906b 2920 reg = DREG(insn, 9);
e1f3808e 2921 tcg_gen_mov_i32(reg, src);
5dbb6784 2922 gen_logic_cc(s, src, opsize);
e6e5906b
PB		 2923}
2924
2925DISAS_INSN(or)
2926{
e1f3808e
PB		 2927 TCGv reg;
2928 TCGv dest;
2929 TCGv src;
2930 TCGv addr;
020a4659 2931 int opsize;
e6e5906b 2932
020a4659
LV		 2933 opsize = insn_opsize(insn);
2934 reg = gen_extend(DREG(insn, 9), opsize, 0);
a7812ae4 2935 dest = tcg_temp_new();
e6e5906b 2936 if (insn & 0x100) {
020a4659 2937 SRC_EA(env, src, opsize, 0, &addr);
e1f3808e 2938 tcg_gen_or_i32(dest, src, reg);
020a4659 2939 DEST_EA(env, insn, opsize, dest, &addr);
e6e5906b 2940 } else {
020a4659 2941 SRC_EA(env, src, opsize, 0, NULL);
e1f3808e 2942 tcg_gen_or_i32(dest, src, reg);
020a4659 2943 gen_partset_reg(opsize, DREG(insn, 9), dest);
e6e5906b 2944 }
020a4659 2945 gen_logic_cc(s, dest, opsize);
2b5e2170 2946 tcg_temp_free(dest);
e6e5906b
PB		 2947}
2948
2949DISAS_INSN(suba)
2950{
e1f3808e
PB		 2951 TCGv src;
2952 TCGv reg;
e6e5906b 2953
415f4b62 2954 SRC_EA(env, src, (insn & 0x100) ? OS_LONG : OS_WORD, 1, NULL);
e6e5906b 2955 reg = AREG(insn, 9);
e1f3808e 2956 tcg_gen_sub_i32(reg, reg, src);
e6e5906b
PB		 2957}
2958
a665a820 2959static inline void gen_subx(DisasContext *s, TCGv src, TCGv dest, int opsize)
e6e5906b 2960{
a665a820
RH		 2961 TCGv tmp;
2962
2963 gen_flush_flags(s); /* compute old Z */
2964
2965 /* Perform substract with borrow.
2966 * (X, N) = dest - (src + X);
2967 */
2968
2969 tmp = tcg_const_i32(0);
2970 tcg_gen_add2_i32(QREG_CC_N, QREG_CC_X, src, tmp, QREG_CC_X, tmp);
2971 tcg_gen_sub2_i32(QREG_CC_N, QREG_CC_X, dest, tmp, QREG_CC_N, QREG_CC_X);
2972 gen_ext(QREG_CC_N, QREG_CC_N, opsize, 1);
2973 tcg_gen_andi_i32(QREG_CC_X, QREG_CC_X, 1);
2974
2975 /* Compute signed-overflow for substract. */
2976
2977 tcg_gen_xor_i32(QREG_CC_V, QREG_CC_N, dest);
2978 tcg_gen_xor_i32(tmp, dest, src);
2979 tcg_gen_and_i32(QREG_CC_V, QREG_CC_V, tmp);
2980 tcg_temp_free(tmp);
2981
2982 /* Copy the rest of the results into place. */
2983 tcg_gen_or_i32(QREG_CC_Z, QREG_CC_Z, QREG_CC_N); /* !Z is sticky */
2984 tcg_gen_mov_i32(QREG_CC_C, QREG_CC_X);
2985
2986 set_cc_op(s, CC_OP_FLAGS);
2987
2988 /* result is in QREG_CC_N */
2989}
2990
2991DISAS_INSN(subx_reg)
2992{
2993 TCGv dest;
e1f3808e 2994 TCGv src;
a665a820 2995 int opsize;
e6e5906b 2996
a665a820
RH		 2997 opsize = insn_opsize(insn);
2998
2999 src = gen_extend(DREG(insn, 0), opsize, 1);
3000 dest = gen_extend(DREG(insn, 9), opsize, 1);
3001
3002 gen_subx(s, src, dest, opsize);
3003
3004 gen_partset_reg(opsize, DREG(insn, 9), QREG_CC_N);
3005}
3006
3007DISAS_INSN(subx_mem)
3008{
3009 TCGv src;
3010 TCGv addr_src;
3011 TCGv dest;
3012 TCGv addr_dest;
3013 int opsize;
3014
3015 opsize = insn_opsize(insn);
3016
3017 addr_src = AREG(insn, 0);
3018 tcg_gen_subi_i32(addr_src, addr_src, opsize);
3019 src = gen_load(s, opsize, addr_src, 1);
3020
3021 addr_dest = AREG(insn, 9);
3022 tcg_gen_subi_i32(addr_dest, addr_dest, opsize);
3023 dest = gen_load(s, opsize, addr_dest, 1);
3024
3025 gen_subx(s, src, dest, opsize);
3026
3027 gen_store(s, opsize, addr_dest, QREG_CC_N);
e6e5906b
PB		 3028}
3029
3030DISAS_INSN(mov3q)
3031{
e1f3808e 3032 TCGv src;
e6e5906b
PB		 3033 int val;
3034
3035 val = (insn >> 9) & 7;
3036 if (val == 0)
3037 val = -1;
351326a6 3038 src = tcg_const_i32(val);
5dbb6784 3039 gen_logic_cc(s, src, OS_LONG);
d4d79bb1 3040 DEST_EA(env, insn, OS_LONG, src, NULL);
2b5e2170 3041 tcg_temp_free(src);
e6e5906b
PB		 3042}
3043
3044DISAS_INSN(cmp)
3045{
e1f3808e
PB		 3046 TCGv src;
3047 TCGv reg;
e6e5906b
PB		 3048 int opsize;
3049
5dbb6784 3050 opsize = insn_opsize(insn);
ff99b952
LV		 3051 SRC_EA(env, src, opsize, 1, NULL);
3052 reg = gen_extend(DREG(insn, 9), opsize, 1);
3053 gen_update_cc_cmp(s, reg, src, opsize);
e6e5906b
PB		 3054}
3055
3056DISAS_INSN(cmpa)
3057{
3058 int opsize;
e1f3808e
PB		 3059 TCGv src;
3060 TCGv reg;
e6e5906b
PB		 3061
3062 if (insn & 0x100) {
3063 opsize = OS_LONG;
3064 } else {
3065 opsize = OS_WORD;
3066 }
d4d79bb1 3067 SRC_EA(env, src, opsize, 1, NULL);
e6e5906b 3068 reg = AREG(insn, 9);
5436c29d 3069 gen_update_cc_cmp(s, reg, src, OS_LONG);
e6e5906b
PB		 3070}
3071
817af1c7
LV		 3072DISAS_INSN(cmpm)
3073{
3074 int opsize = insn_opsize(insn);
3075 TCGv src, dst;
3076
3077 /* Post-increment load (mode 3) from Ay. */
3078 src = gen_ea_mode(env, s, 3, REG(insn, 0), opsize,
3079 NULL_QREG, NULL, EA_LOADS);
3080 /* Post-increment load (mode 3) from Ax. */
3081 dst = gen_ea_mode(env, s, 3, REG(insn, 9), opsize,
3082 NULL_QREG, NULL, EA_LOADS);
3083
3084 gen_update_cc_cmp(s, dst, src, opsize);
3085}
3086
e6e5906b
PB		 3087DISAS_INSN(eor)
3088{
e1f3808e 3089 TCGv src;
e1f3808e
PB		 3090 TCGv dest;
3091 TCGv addr;
eec37aec 3092 int opsize;
e6e5906b 3093
eec37aec
LV		 3094 opsize = insn_opsize(insn);
3095
3096 SRC_EA(env, src, opsize, 0, &addr);
a7812ae4 3097 dest = tcg_temp_new();
eec37aec
LV		 3098 tcg_gen_xor_i32(dest, src, DREG(insn, 9));
3099 gen_logic_cc(s, dest, opsize);
3100 DEST_EA(env, insn, opsize, dest, &addr);
2b5e2170 3101 tcg_temp_free(dest);
e6e5906b
PB		 3102}
3103
29cf437d
LV		 3104static void do_exg(TCGv reg1, TCGv reg2)
3105{
3106 TCGv temp = tcg_temp_new();
3107 tcg_gen_mov_i32(temp, reg1);
3108 tcg_gen_mov_i32(reg1, reg2);
3109 tcg_gen_mov_i32(reg2, temp);
3110 tcg_temp_free(temp);
3111}
3112
c090c97d 3113DISAS_INSN(exg_dd)
29cf437d
LV		 3114{
3115 /* exchange Dx and Dy */
3116 do_exg(DREG(insn, 9), DREG(insn, 0));
3117}
3118
c090c97d 3119DISAS_INSN(exg_aa)
29cf437d
LV		 3120{
3121 /* exchange Ax and Ay */
3122 do_exg(AREG(insn, 9), AREG(insn, 0));
3123}
3124
3125DISAS_INSN(exg_da)
3126{
3127 /* exchange Dx and Ay */
3128 do_exg(DREG(insn, 9), AREG(insn, 0));
3129}
3130
e6e5906b
PB		 3131DISAS_INSN(and)
3132{
e1f3808e
PB		 3133 TCGv src;
3134 TCGv reg;
3135 TCGv dest;
3136 TCGv addr;
52dc23c5 3137 int opsize;
e6e5906b 3138
a7812ae4 3139 dest = tcg_temp_new();
52dc23c5
LV		 3140
3141 opsize = insn_opsize(insn);
3142 reg = DREG(insn, 9);
e6e5906b 3143 if (insn & 0x100) {
52dc23c5 3144 SRC_EA(env, src, opsize, 0, &addr);
e1f3808e 3145 tcg_gen_and_i32(dest, src, reg);
52dc23c5 3146 DEST_EA(env, insn, opsize, dest, &addr);
e6e5906b 3147 } else {
52dc23c5 3148 SRC_EA(env, src, opsize, 0, NULL);
e1f3808e 3149 tcg_gen_and_i32(dest, src, reg);
52dc23c5 3150 gen_partset_reg(opsize, reg, dest);
e6e5906b 3151 }
52dc23c5 3152 gen_logic_cc(s, dest, opsize);
2b5e2170 3153 tcg_temp_free(dest);
e6e5906b
PB		 3154}
3155
3156DISAS_INSN(adda)
3157{
e1f3808e
PB		 3158 TCGv src;
3159 TCGv reg;
e6e5906b 3160
415f4b62 3161 SRC_EA(env, src, (insn & 0x100) ? OS_LONG : OS_WORD, 1, NULL);
e6e5906b 3162 reg = AREG(insn, 9);
e1f3808e 3163 tcg_gen_add_i32(reg, reg, src);
e6e5906b
PB		 3164}
3165
a665a820 3166static inline void gen_addx(DisasContext *s, TCGv src, TCGv dest, int opsize)
e6e5906b 3167{
a665a820
RH		 3168 TCGv tmp;
3169
3170 gen_flush_flags(s); /* compute old Z */
3171
3172 /* Perform addition with carry.
3173 * (X, N) = src + dest + X;
3174 */
3175
3176 tmp = tcg_const_i32(0);
3177 tcg_gen_add2_i32(QREG_CC_N, QREG_CC_X, QREG_CC_X, tmp, dest, tmp);
3178 tcg_gen_add2_i32(QREG_CC_N, QREG_CC_X, QREG_CC_N, QREG_CC_X, src, tmp);
3179 gen_ext(QREG_CC_N, QREG_CC_N, opsize, 1);
3180
3181 /* Compute signed-overflow for addition. */
3182
3183 tcg_gen_xor_i32(QREG_CC_V, QREG_CC_N, src);
3184 tcg_gen_xor_i32(tmp, dest, src);
3185 tcg_gen_andc_i32(QREG_CC_V, QREG_CC_V, tmp);
3186 tcg_temp_free(tmp);
3187
3188 /* Copy the rest of the results into place. */
3189 tcg_gen_or_i32(QREG_CC_Z, QREG_CC_Z, QREG_CC_N); /* !Z is sticky */
3190 tcg_gen_mov_i32(QREG_CC_C, QREG_CC_X);
3191
3192 set_cc_op(s, CC_OP_FLAGS);
3193
3194 /* result is in QREG_CC_N */
3195}
3196
3197DISAS_INSN(addx_reg)
3198{
3199 TCGv dest;
e1f3808e 3200 TCGv src;
a665a820 3201 int opsize;
e6e5906b 3202
a665a820
RH		 3203 opsize = insn_opsize(insn);
3204
3205 dest = gen_extend(DREG(insn, 9), opsize, 1);
3206 src = gen_extend(DREG(insn, 0), opsize, 1);
3207
3208 gen_addx(s, src, dest, opsize);
3209
3210 gen_partset_reg(opsize, DREG(insn, 9), QREG_CC_N);
3211}
3212
3213DISAS_INSN(addx_mem)
3214{
3215 TCGv src;
3216 TCGv addr_src;
3217 TCGv dest;
3218 TCGv addr_dest;
3219 int opsize;
3220
3221 opsize = insn_opsize(insn);
3222
3223 addr_src = AREG(insn, 0);
3224 tcg_gen_subi_i32(addr_src, addr_src, opsize_bytes(opsize));
3225 src = gen_load(s, opsize, addr_src, 1);
3226
3227 addr_dest = AREG(insn, 9);
3228 tcg_gen_subi_i32(addr_dest, addr_dest, opsize_bytes(opsize));
3229 dest = gen_load(s, opsize, addr_dest, 1);
3230
3231 gen_addx(s, src, dest, opsize);
3232
3233 gen_store(s, opsize, addr_dest, QREG_CC_N);
e6e5906b
PB		 3234}
3235
367790cc 3236static inline void shift_im(DisasContext *s, uint16_t insn, int opsize)
e6e5906b 3237{
367790cc
RH		 3238 int count = (insn >> 9) & 7;
3239 int logical = insn & 8;
3240 int left = insn & 0x100;
3241 int bits = opsize_bytes(opsize) * 8;
3242 TCGv reg = gen_extend(DREG(insn, 0), opsize, !logical);
3243
3244 if (count == 0) {
3245 count = 8;
3246 }
3247
3248 tcg_gen_movi_i32(QREG_CC_V, 0);
3249 if (left) {
3250 tcg_gen_shri_i32(QREG_CC_C, reg, bits - count);
3251 tcg_gen_shli_i32(QREG_CC_N, reg, count);
3252
3253 /* Note that ColdFire always clears V (done above),
3254 while M68000 sets if the most significant bit is changed at
3255 any time during the shift operation */
3256 if (!logical && m68k_feature(s->env, M68K_FEATURE_M68000)) {
3257 /* if shift count >= bits, V is (reg != 0) */
3258 if (count >= bits) {
3259 tcg_gen_setcond_i32(TCG_COND_NE, QREG_CC_V, reg, QREG_CC_V);
3260 } else {
3261 TCGv t0 = tcg_temp_new();
3262 tcg_gen_sari_i32(QREG_CC_V, reg, bits - 1);
3263 tcg_gen_sari_i32(t0, reg, bits - count - 1);
3264 tcg_gen_setcond_i32(TCG_COND_NE, QREG_CC_V, QREG_CC_V, t0);
3265 tcg_temp_free(t0);
3266 }
3267 tcg_gen_neg_i32(QREG_CC_V, QREG_CC_V);
3268 }
3269 } else {
3270 tcg_gen_shri_i32(QREG_CC_C, reg, count - 1);
3271 if (logical) {
3272 tcg_gen_shri_i32(QREG_CC_N, reg, count);
3273 } else {
3274 tcg_gen_sari_i32(QREG_CC_N, reg, count);
3275 }
3276 }
3277
3278 gen_ext(QREG_CC_N, QREG_CC_N, opsize, 1);
3279 tcg_gen_andi_i32(QREG_CC_C, QREG_CC_C, 1);
3280 tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N);
3281 tcg_gen_mov_i32(QREG_CC_X, QREG_CC_C);
e6e5906b 3282
367790cc 3283 gen_partset_reg(opsize, DREG(insn, 0), QREG_CC_N);
620c6cf6 3284 set_cc_op(s, CC_OP_FLAGS);
367790cc 3285}
620c6cf6 3286
367790cc
RH		 3287static inline void shift_reg(DisasContext *s, uint16_t insn, int opsize)
3288{
3289 int logical = insn & 8;
3290 int left = insn & 0x100;
3291 int bits = opsize_bytes(opsize) * 8;
3292 TCGv reg = gen_extend(DREG(insn, 0), opsize, !logical);
3293 TCGv s32;
3294 TCGv_i64 t64, s64;
3295
3296 t64 = tcg_temp_new_i64();
3297 s64 = tcg_temp_new_i64();
3298 s32 = tcg_temp_new();
3299
3300 /* Note that m68k truncates the shift count modulo 64, not 32.
3301 In addition, a 64-bit shift makes it easy to find "the last
3302 bit shifted out", for the carry flag. */
3303 tcg_gen_andi_i32(s32, DREG(insn, 9), 63);
3304 tcg_gen_extu_i32_i64(s64, s32);
3305 tcg_gen_extu_i32_i64(t64, reg);
3306
3307 /* Optimistically set V=0. Also used as a zero source below. */
3308 tcg_gen_movi_i32(QREG_CC_V, 0);
3309 if (left) {
3310 tcg_gen_shl_i64(t64, t64, s64);
3311
3312 if (opsize == OS_LONG) {
3313 tcg_gen_extr_i64_i32(QREG_CC_N, QREG_CC_C, t64);
3314 /* Note that C=0 if shift count is 0, and we get that for free. */
3315 } else {
3316 TCGv zero = tcg_const_i32(0);
3317 tcg_gen_extrl_i64_i32(QREG_CC_N, t64);
3318 tcg_gen_shri_i32(QREG_CC_C, QREG_CC_N, bits);
3319 tcg_gen_movcond_i32(TCG_COND_EQ, QREG_CC_C,
3320 s32, zero, zero, QREG_CC_C);
3321 tcg_temp_free(zero);
3322 }
3323 tcg_gen_andi_i32(QREG_CC_C, QREG_CC_C, 1);
3324
3325 /* X = C, but only if the shift count was non-zero. */
3326 tcg_gen_movcond_i32(TCG_COND_NE, QREG_CC_X, s32, QREG_CC_V,
3327 QREG_CC_C, QREG_CC_X);
3328
3329 /* M68000 sets V if the most significant bit is changed at
3330 * any time during the shift operation. Do this via creating
3331 * an extension of the sign bit, comparing, and discarding
3332 * the bits below the sign bit. I.e.
3333 * int64_t s = (intN_t)reg;
3334 * int64_t t = (int64_t)(intN_t)reg << count;
3335 * V = ((s ^ t) & (-1 << (bits - 1))) != 0
3336 */
3337 if (!logical && m68k_feature(s->env, M68K_FEATURE_M68000)) {
3338 TCGv_i64 tt = tcg_const_i64(32);
3339 /* if shift is greater than 32, use 32 */
3340 tcg_gen_movcond_i64(TCG_COND_GT, s64, s64, tt, tt, s64);
3341 tcg_temp_free_i64(tt);
3342 /* Sign extend the input to 64 bits; re-do the shift. */
3343 tcg_gen_ext_i32_i64(t64, reg);
3344 tcg_gen_shl_i64(s64, t64, s64);
3345 /* Clear all bits that are unchanged. */
3346 tcg_gen_xor_i64(t64, t64, s64);
3347 /* Ignore the bits below the sign bit. */
3348 tcg_gen_andi_i64(t64, t64, -1ULL << (bits - 1));
3349 /* If any bits remain set, we have overflow. */
3350 tcg_gen_setcondi_i64(TCG_COND_NE, t64, t64, 0);
3351 tcg_gen_extrl_i64_i32(QREG_CC_V, t64);
3352 tcg_gen_neg_i32(QREG_CC_V, QREG_CC_V);
3353 }
e6e5906b 3354 } else {
367790cc
RH		 3355 tcg_gen_shli_i64(t64, t64, 32);
3356 if (logical) {
3357 tcg_gen_shr_i64(t64, t64, s64);
e6e5906b 3358 } else {
367790cc 3359 tcg_gen_sar_i64(t64, t64, s64);
e6e5906b 3360 }
367790cc
RH		 3361 tcg_gen_extr_i64_i32(QREG_CC_C, QREG_CC_N, t64);
3362
3363 /* Note that C=0 if shift count is 0, and we get that for free. */
3364 tcg_gen_shri_i32(QREG_CC_C, QREG_CC_C, 31);
3365
3366 /* X = C, but only if the shift count was non-zero. */
3367 tcg_gen_movcond_i32(TCG_COND_NE, QREG_CC_X, s32, QREG_CC_V,
3368 QREG_CC_C, QREG_CC_X);
e6e5906b 3369 }
367790cc
RH		 3370 gen_ext(QREG_CC_N, QREG_CC_N, opsize, 1);
3371 tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N);
3372
3373 tcg_temp_free(s32);
3374 tcg_temp_free_i64(s64);
3375 tcg_temp_free_i64(t64);
3376
3377 /* Write back the result. */
3378 gen_partset_reg(opsize, DREG(insn, 0), QREG_CC_N);
3379 set_cc_op(s, CC_OP_FLAGS);
3380}
3381
3382DISAS_INSN(shift8_im)
3383{
3384 shift_im(s, insn, OS_BYTE);
3385}
3386
3387DISAS_INSN(shift16_im)
3388{
3389 shift_im(s, insn, OS_WORD);
3390}
3391
3392DISAS_INSN(shift_im)
3393{
3394 shift_im(s, insn, OS_LONG);
3395}
3396
3397DISAS_INSN(shift8_reg)
3398{
3399 shift_reg(s, insn, OS_BYTE);
3400}
3401
3402DISAS_INSN(shift16_reg)
3403{
3404 shift_reg(s, insn, OS_WORD);
e6e5906b
PB		 3405}
3406
3407DISAS_INSN(shift_reg)
3408{
367790cc
RH		 3409 shift_reg(s, insn, OS_LONG);
3410}
e6e5906b 3411
367790cc
RH		 3412DISAS_INSN(shift_mem)
3413{
3414 int logical = insn & 8;
3415 int left = insn & 0x100;
3416 TCGv src;
3417 TCGv addr;
3418
3419 SRC_EA(env, src, OS_WORD, !logical, &addr);
3420 tcg_gen_movi_i32(QREG_CC_V, 0);
3421 if (left) {
3422 tcg_gen_shri_i32(QREG_CC_C, src, 15);
3423 tcg_gen_shli_i32(QREG_CC_N, src, 1);
3424
3425 /* Note that ColdFire always clears V,
3426 while M68000 sets if the most significant bit is changed at
3427 any time during the shift operation */
3428 if (!logical && m68k_feature(s->env, M68K_FEATURE_M68000)) {
3429 src = gen_extend(src, OS_WORD, 1);
3430 tcg_gen_xor_i32(QREG_CC_V, QREG_CC_N, src);
3431 }
e6e5906b 3432 } else {
367790cc
RH		 3433 tcg_gen_mov_i32(QREG_CC_C, src);
3434 if (logical) {
3435 tcg_gen_shri_i32(QREG_CC_N, src, 1);
e6e5906b 3436 } else {
367790cc 3437 tcg_gen_sari_i32(QREG_CC_N, src, 1);
e6e5906b
PB		 3438 }
3439 }
367790cc
RH		 3440
3441 gen_ext(QREG_CC_N, QREG_CC_N, OS_WORD, 1);
3442 tcg_gen_andi_i32(QREG_CC_C, QREG_CC_C, 1);
3443 tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N);
3444 tcg_gen_mov_i32(QREG_CC_X, QREG_CC_C);
3445
3446 DEST_EA(env, insn, OS_WORD, QREG_CC_N, &addr);
620c6cf6 3447 set_cc_op(s, CC_OP_FLAGS);
e6e5906b
PB		 3448}
3449
0194cf31
LV		 3450static void rotate(TCGv reg, TCGv shift, int left, int size)
3451{
3452 switch (size) {
3453 case 8:
3454 /* Replicate the 8-bit input so that a 32-bit rotate works. */
3455 tcg_gen_ext8u_i32(reg, reg);
3456 tcg_gen_muli_i32(reg, reg, 0x01010101);
3457 goto do_long;
3458 case 16:
3459 /* Replicate the 16-bit input so that a 32-bit rotate works. */
3460 tcg_gen_deposit_i32(reg, reg, reg, 16, 16);
3461 goto do_long;
3462 do_long:
3463 default:
3464 if (left) {
3465 tcg_gen_rotl_i32(reg, reg, shift);
3466 } else {
3467 tcg_gen_rotr_i32(reg, reg, shift);
3468 }
3469 }
3470
3471 /* compute flags */
3472
3473 switch (size) {
3474 case 8:
3475 tcg_gen_ext8s_i32(reg, reg);
3476 break;
3477 case 16:
3478 tcg_gen_ext16s_i32(reg, reg);
3479 break;
3480 default:
3481 break;
3482 }
3483
3484 /* QREG_CC_X is not affected */
3485
3486 tcg_gen_mov_i32(QREG_CC_N, reg);
3487 tcg_gen_mov_i32(QREG_CC_Z, reg);
3488
3489 if (left) {
3490 tcg_gen_andi_i32(QREG_CC_C, reg, 1);
3491 } else {
3492 tcg_gen_shri_i32(QREG_CC_C, reg, 31);
3493 }
3494
3495 tcg_gen_movi_i32(QREG_CC_V, 0); /* always cleared */
3496}
3497
3498static void rotate_x_flags(TCGv reg, TCGv X, int size)
3499{
3500 switch (size) {
3501 case 8:
3502 tcg_gen_ext8s_i32(reg, reg);
3503 break;
3504 case 16:
3505 tcg_gen_ext16s_i32(reg, reg);
3506 break;
3507 default:
3508 break;
3509 }
3510 tcg_gen_mov_i32(QREG_CC_N, reg);
3511 tcg_gen_mov_i32(QREG_CC_Z, reg);
3512 tcg_gen_mov_i32(QREG_CC_X, X);
3513 tcg_gen_mov_i32(QREG_CC_C, X);
3514 tcg_gen_movi_i32(QREG_CC_V, 0);
3515}
3516
3517/* Result of rotate_x() is valid if 0 <= shift <= size */
3518static TCGv rotate_x(TCGv reg, TCGv shift, int left, int size)
3519{
3520 TCGv X, shl, shr, shx, sz, zero;
3521
3522 sz = tcg_const_i32(size);
3523
3524 shr = tcg_temp_new();
3525 shl = tcg_temp_new();
3526 shx = tcg_temp_new();
3527 if (left) {
3528 tcg_gen_mov_i32(shl, shift); /* shl = shift */
3529 tcg_gen_movi_i32(shr, size + 1);
3530 tcg_gen_sub_i32(shr, shr, shift); /* shr = size + 1 - shift */
3531 tcg_gen_subi_i32(shx, shift, 1); /* shx = shift - 1 */
3532 /* shx = shx < 0 ? size : shx; */
3533 zero = tcg_const_i32(0);
3534 tcg_gen_movcond_i32(TCG_COND_LT, shx, shx, zero, sz, shx);
3535 tcg_temp_free(zero);
3536 } else {
3537 tcg_gen_mov_i32(shr, shift); /* shr = shift */
3538 tcg_gen_movi_i32(shl, size + 1);
3539 tcg_gen_sub_i32(shl, shl, shift); /* shl = size + 1 - shift */
3540 tcg_gen_sub_i32(shx, sz, shift); /* shx = size - shift */
3541 }
3542
3543 /* reg = (reg << shl) | (reg >> shr) | (x << shx); */
3544
3545 tcg_gen_shl_i32(shl, reg, shl);
3546 tcg_gen_shr_i32(shr, reg, shr);
3547 tcg_gen_or_i32(reg, shl, shr);
3548 tcg_temp_free(shl);
3549 tcg_temp_free(shr);
3550 tcg_gen_shl_i32(shx, QREG_CC_X, shx);
3551 tcg_gen_or_i32(reg, reg, shx);
3552 tcg_temp_free(shx);
3553
3554 /* X = (reg >> size) & 1 */
3555
3556 X = tcg_temp_new();
3557 tcg_gen_shr_i32(X, reg, sz);
3558 tcg_gen_andi_i32(X, X, 1);
3559 tcg_temp_free(sz);
3560
3561 return X;
3562}
3563
3564/* Result of rotate32_x() is valid if 0 <= shift < 33 */
3565static TCGv rotate32_x(TCGv reg, TCGv shift, int left)
3566{
3567 TCGv_i64 t0, shift64;
3568 TCGv X, lo, hi, zero;
3569
3570 shift64 = tcg_temp_new_i64();
3571 tcg_gen_extu_i32_i64(shift64, shift);
3572
3573 t0 = tcg_temp_new_i64();
3574
3575 X = tcg_temp_new();
3576 lo = tcg_temp_new();
3577 hi = tcg_temp_new();
3578
3579 if (left) {
3580 /* create [reg:X:..] */
3581
3582 tcg_gen_shli_i32(lo, QREG_CC_X, 31);
3583 tcg_gen_concat_i32_i64(t0, lo, reg);
3584
3585 /* rotate */
3586
3587 tcg_gen_rotl_i64(t0, t0, shift64);
3588 tcg_temp_free_i64(shift64);
3589
3590 /* result is [reg:..:reg:X] */
3591
3592 tcg_gen_extr_i64_i32(lo, hi, t0);
3593 tcg_gen_andi_i32(X, lo, 1);
3594
3595 tcg_gen_shri_i32(lo, lo, 1);
3596 } else {
3597 /* create [..:X:reg] */
3598
3599 tcg_gen_concat_i32_i64(t0, reg, QREG_CC_X);
3600
3601 tcg_gen_rotr_i64(t0, t0, shift64);
3602 tcg_temp_free_i64(shift64);
3603
3604 /* result is value: [X:reg:..:reg] */
3605
3606 tcg_gen_extr_i64_i32(lo, hi, t0);
3607
3608 /* extract X */
3609
3610 tcg_gen_shri_i32(X, hi, 31);
3611
3612 /* extract result */
3613
3614 tcg_gen_shli_i32(hi, hi, 1);
3615 }
3616 tcg_temp_free_i64(t0);
3617 tcg_gen_or_i32(lo, lo, hi);
3618 tcg_temp_free(hi);
3619
3620 /* if shift == 0, register and X are not affected */
3621
3622 zero = tcg_const_i32(0);
3623 tcg_gen_movcond_i32(TCG_COND_EQ, X, shift, zero, QREG_CC_X, X);
3624 tcg_gen_movcond_i32(TCG_COND_EQ, reg, shift, zero, reg, lo);
3625 tcg_temp_free(zero);
3626 tcg_temp_free(lo);
3627
3628 return X;
3629}
3630
3631DISAS_INSN(rotate_im)
3632{
3633 TCGv shift;
3634 int tmp;
3635 int left = (insn & 0x100);
3636
3637 tmp = (insn >> 9) & 7;
3638 if (tmp == 0) {
3639 tmp = 8;
3640 }
3641
3642 shift = tcg_const_i32(tmp);
3643 if (insn & 8) {
3644 rotate(DREG(insn, 0), shift, left, 32);
3645 } else {
3646 TCGv X = rotate32_x(DREG(insn, 0), shift, left);
3647 rotate_x_flags(DREG(insn, 0), X, 32);
3648 tcg_temp_free(X);
3649 }
3650 tcg_temp_free(shift);
3651
3652 set_cc_op(s, CC_OP_FLAGS);
3653}
3654
3655DISAS_INSN(rotate8_im)
3656{
3657 int left = (insn & 0x100);
3658 TCGv reg;
3659 TCGv shift;
3660 int tmp;
3661
3662 reg = gen_extend(DREG(insn, 0), OS_BYTE, 0);
3663
3664 tmp = (insn >> 9) & 7;
3665 if (tmp == 0) {
3666 tmp = 8;
3667 }
3668
3669 shift = tcg_const_i32(tmp);
3670 if (insn & 8) {
3671 rotate(reg, shift, left, 8);
3672 } else {
3673 TCGv X = rotate_x(reg, shift, left, 8);
3674 rotate_x_flags(reg, X, 8);
3675 tcg_temp_free(X);
3676 }
3677 tcg_temp_free(shift);
3678 gen_partset_reg(OS_BYTE, DREG(insn, 0), reg);
3679 set_cc_op(s, CC_OP_FLAGS);
3680}
3681
3682DISAS_INSN(rotate16_im)
3683{
3684 int left = (insn & 0x100);
3685 TCGv reg;
3686 TCGv shift;
3687 int tmp;
3688
3689 reg = gen_extend(DREG(insn, 0), OS_WORD, 0);
3690 tmp = (insn >> 9) & 7;
3691 if (tmp == 0) {
3692 tmp = 8;
3693 }
3694
3695 shift = tcg_const_i32(tmp);
3696 if (insn & 8) {
3697 rotate(reg, shift, left, 16);
3698 } else {
3699 TCGv X = rotate_x(reg, shift, left, 16);
3700 rotate_x_flags(reg, X, 16);
3701 tcg_temp_free(X);
3702 }
3703 tcg_temp_free(shift);
3704 gen_partset_reg(OS_WORD, DREG(insn, 0), reg);
3705 set_cc_op(s, CC_OP_FLAGS);
3706}
3707
3708DISAS_INSN(rotate_reg)
3709{
3710 TCGv reg;
3711 TCGv src;
3712 TCGv t0, t1;
3713 int left = (insn & 0x100);
3714
3715 reg = DREG(insn, 0);
3716 src = DREG(insn, 9);
3717 /* shift in [0..63] */
3718 t0 = tcg_temp_new();
3719 tcg_gen_andi_i32(t0, src, 63);
3720 t1 = tcg_temp_new_i32();
3721 if (insn & 8) {
3722 tcg_gen_andi_i32(t1, src, 31);
3723 rotate(reg, t1, left, 32);
3724 /* if shift == 0, clear C */
3725 tcg_gen_movcond_i32(TCG_COND_EQ, QREG_CC_C,
3726 t0, QREG_CC_V /* 0 */,
3727 QREG_CC_V /* 0 */, QREG_CC_C);
3728 } else {
3729 TCGv X;
3730 /* modulo 33 */
3731 tcg_gen_movi_i32(t1, 33);
3732 tcg_gen_remu_i32(t1, t0, t1);
3733 X = rotate32_x(DREG(insn, 0), t1, left);
3734 rotate_x_flags(DREG(insn, 0), X, 32);
3735 tcg_temp_free(X);
3736 }
3737 tcg_temp_free(t1);
3738 tcg_temp_free(t0);
3739 set_cc_op(s, CC_OP_FLAGS);
3740}
3741
3742DISAS_INSN(rotate8_reg)
3743{
3744 TCGv reg;
3745 TCGv src;
3746 TCGv t0, t1;
3747 int left = (insn & 0x100);
3748
3749 reg = gen_extend(DREG(insn, 0), OS_BYTE, 0);
3750 src = DREG(insn, 9);
3751 /* shift in [0..63] */
3752 t0 = tcg_temp_new_i32();
3753 tcg_gen_andi_i32(t0, src, 63);
3754 t1 = tcg_temp_new_i32();
3755 if (insn & 8) {
3756 tcg_gen_andi_i32(t1, src, 7);
3757 rotate(reg, t1, left, 8);
3758 /* if shift == 0, clear C */
3759 tcg_gen_movcond_i32(TCG_COND_EQ, QREG_CC_C,
3760 t0, QREG_CC_V /* 0 */,
3761 QREG_CC_V /* 0 */, QREG_CC_C);
3762 } else {
3763 TCGv X;
3764 /* modulo 9 */
3765 tcg_gen_movi_i32(t1, 9);
3766 tcg_gen_remu_i32(t1, t0, t1);
3767 X = rotate_x(reg, t1, left, 8);
3768 rotate_x_flags(reg, X, 8);
3769 tcg_temp_free(X);
3770 }
3771 tcg_temp_free(t1);
3772 tcg_temp_free(t0);
3773 gen_partset_reg(OS_BYTE, DREG(insn, 0), reg);
3774 set_cc_op(s, CC_OP_FLAGS);
3775}
3776
3777DISAS_INSN(rotate16_reg)
3778{
3779 TCGv reg;
3780 TCGv src;
3781 TCGv t0, t1;
3782 int left = (insn & 0x100);
3783
3784 reg = gen_extend(DREG(insn, 0), OS_WORD, 0);
3785 src = DREG(insn, 9);
3786 /* shift in [0..63] */
3787 t0 = tcg_temp_new_i32();
3788 tcg_gen_andi_i32(t0, src, 63);
3789 t1 = tcg_temp_new_i32();
3790 if (insn & 8) {
3791 tcg_gen_andi_i32(t1, src, 15);
3792 rotate(reg, t1, left, 16);
3793 /* if shift == 0, clear C */
3794 tcg_gen_movcond_i32(TCG_COND_EQ, QREG_CC_C,
3795 t0, QREG_CC_V /* 0 */,
3796 QREG_CC_V /* 0 */, QREG_CC_C);
3797 } else {
3798 TCGv X;
3799 /* modulo 17 */
3800 tcg_gen_movi_i32(t1, 17);
3801 tcg_gen_remu_i32(t1, t0, t1);
3802 X = rotate_x(reg, t1, left, 16);
3803 rotate_x_flags(reg, X, 16);
3804 tcg_temp_free(X);
3805 }
3806 tcg_temp_free(t1);
3807 tcg_temp_free(t0);
3808 gen_partset_reg(OS_WORD, DREG(insn, 0), reg);
3809 set_cc_op(s, CC_OP_FLAGS);
3810}
3811
3812DISAS_INSN(rotate_mem)
3813{
3814 TCGv src;
3815 TCGv addr;
3816 TCGv shift;
3817 int left = (insn & 0x100);
3818
3819 SRC_EA(env, src, OS_WORD, 0, &addr);
3820
3821 shift = tcg_const_i32(1);
3822 if (insn & 0x0200) {
3823 rotate(src, shift, left, 16);
3824 } else {
3825 TCGv X = rotate_x(src, shift, left, 16);
3826 rotate_x_flags(src, X, 16);
3827 tcg_temp_free(X);
3828 }
3829 tcg_temp_free(shift);
3830 DEST_EA(env, insn, OS_WORD, src, &addr);
3831 set_cc_op(s, CC_OP_FLAGS);
3832}
3833
ac815f46
RH		 3834DISAS_INSN(bfext_reg)
3835{
3836 int ext = read_im16(env, s);
3837 int is_sign = insn & 0x200;
3838 TCGv src = DREG(insn, 0);
3839 TCGv dst = DREG(ext, 12);
3840 int len = ((extract32(ext, 0, 5) - 1) & 31) + 1;
3841 int ofs = extract32(ext, 6, 5); /* big bit-endian */
3842 int pos = 32 - ofs - len; /* little bit-endian */
3843 TCGv tmp = tcg_temp_new();
3844 TCGv shift;
3845
3846 /* In general, we're going to rotate the field so that it's at the
3847 top of the word and then right-shift by the compliment of the
3848 width to extend the field. */
3849 if (ext & 0x20) {
3850 /* Variable width. */
3851 if (ext & 0x800) {
3852 /* Variable offset. */
3853 tcg_gen_andi_i32(tmp, DREG(ext, 6), 31);
3854 tcg_gen_rotl_i32(tmp, src, tmp);
3855 } else {
3856 tcg_gen_rotli_i32(tmp, src, ofs);
3857 }
3858
3859 shift = tcg_temp_new();
3860 tcg_gen_neg_i32(shift, DREG(ext, 0));
3861 tcg_gen_andi_i32(shift, shift, 31);
3862 tcg_gen_sar_i32(QREG_CC_N, tmp, shift);
3863 if (is_sign) {
3864 tcg_gen_mov_i32(dst, QREG_CC_N);
3865 } else {
3866 tcg_gen_shr_i32(dst, tmp, shift);
3867 }
3868 tcg_temp_free(shift);
3869 } else {
3870 /* Immediate width. */
3871 if (ext & 0x800) {
3872 /* Variable offset */
3873 tcg_gen_andi_i32(tmp, DREG(ext, 6), 31);
3874 tcg_gen_rotl_i32(tmp, src, tmp);
3875 src = tmp;
3876 pos = 32 - len;
3877 } else {
3878 /* Immediate offset. If the field doesn't wrap around the
3879 end of the word, rely on (s)extract completely. */
3880 if (pos < 0) {
3881 tcg_gen_rotli_i32(tmp, src, ofs);
3882 src = tmp;
3883 pos = 32 - len;
3884 }
3885 }
3886
3887 tcg_gen_sextract_i32(QREG_CC_N, src, pos, len);
3888 if (is_sign) {
3889 tcg_gen_mov_i32(dst, QREG_CC_N);
3890 } else {
3891 tcg_gen_extract_i32(dst, src, pos, len);
3892 }
3893 }
3894
3895 tcg_temp_free(tmp);
3896 set_cc_op(s, CC_OP_LOGIC);
3897}
3898
f2224f2c
RH		 3899DISAS_INSN(bfext_mem)
3900{
3901 int ext = read_im16(env, s);
3902 int is_sign = insn & 0x200;
3903 TCGv dest = DREG(ext, 12);
3904 TCGv addr, len, ofs;
3905
3906 addr = gen_lea(env, s, insn, OS_UNSIZED);
3907 if (IS_NULL_QREG(addr)) {
3908 gen_addr_fault(s);
3909 return;
3910 }
3911
3912 if (ext & 0x20) {
3913 len = DREG(ext, 0);
3914 } else {
3915 len = tcg_const_i32(extract32(ext, 0, 5));
3916 }
3917 if (ext & 0x800) {
3918 ofs = DREG(ext, 6);
3919 } else {
3920 ofs = tcg_const_i32(extract32(ext, 6, 5));
3921 }
3922
3923 if (is_sign) {
3924 gen_helper_bfexts_mem(dest, cpu_env, addr, ofs, len);
3925 tcg_gen_mov_i32(QREG_CC_N, dest);
3926 } else {
3927 TCGv_i64 tmp = tcg_temp_new_i64();
3928 gen_helper_bfextu_mem(tmp, cpu_env, addr, ofs, len);
3929 tcg_gen_extr_i64_i32(dest, QREG_CC_N, tmp);
3930 tcg_temp_free_i64(tmp);
3931 }
3932 set_cc_op(s, CC_OP_LOGIC);
3933
3934 if (!(ext & 0x20)) {
3935 tcg_temp_free(len);
3936 }
3937 if (!(ext & 0x800)) {
3938 tcg_temp_free(ofs);
3939 }
3940}
3941
ac815f46
RH		 3942DISAS_INSN(bfop_reg)
3943{
3944 int ext = read_im16(env, s);
3945 TCGv src = DREG(insn, 0);
3946 int len = ((extract32(ext, 0, 5) - 1) & 31) + 1;
3947 int ofs = extract32(ext, 6, 5); /* big bit-endian */
a45f1763
RH		 3948 TCGv mask, tofs, tlen;
3949
3950 TCGV_UNUSED(tofs);
3951 TCGV_UNUSED(tlen);
3952 if ((insn & 0x0f00) == 0x0d00) { /* bfffo */
3953 tofs = tcg_temp_new();
3954 tlen = tcg_temp_new();
3955 }
ac815f46
RH		 3956
3957 if ((ext & 0x820) == 0) {
3958 /* Immediate width and offset. */
3959 uint32_t maski = 0x7fffffffu >> (len - 1);
3960 if (ofs + len <= 32) {
3961 tcg_gen_shli_i32(QREG_CC_N, src, ofs);
3962 } else {
3963 tcg_gen_rotli_i32(QREG_CC_N, src, ofs);
3964 }
3965 tcg_gen_andi_i32(QREG_CC_N, QREG_CC_N, ~maski);
3966 mask = tcg_const_i32(ror32(maski, ofs));
a45f1763
RH		 3967 if (!TCGV_IS_UNUSED(tofs)) {
3968 tcg_gen_movi_i32(tofs, ofs);
3969 tcg_gen_movi_i32(tlen, len);
3970 }
ac815f46
RH		 3971 } else {
3972 TCGv tmp = tcg_temp_new();
3973 if (ext & 0x20) {
3974 /* Variable width */
3975 tcg_gen_subi_i32(tmp, DREG(ext, 0), 1);
3976 tcg_gen_andi_i32(tmp, tmp, 31);
3977 mask = tcg_const_i32(0x7fffffffu);
3978 tcg_gen_shr_i32(mask, mask, tmp);
a45f1763
RH		 3979 if (!TCGV_IS_UNUSED(tlen)) {
3980 tcg_gen_addi_i32(tlen, tmp, 1);
3981 }
ac815f46
RH		 3982 } else {
3983 /* Immediate width */
3984 mask = tcg_const_i32(0x7fffffffu >> (len - 1));
a45f1763
RH		 3985 if (!TCGV_IS_UNUSED(tlen)) {
3986 tcg_gen_movi_i32(tlen, len);
3987 }
ac815f46
RH		 3988 }
3989 if (ext & 0x800) {
3990 /* Variable offset */
3991 tcg_gen_andi_i32(tmp, DREG(ext, 6), 31);
3992 tcg_gen_rotl_i32(QREG_CC_N, src, tmp);
3993 tcg_gen_andc_i32(QREG_CC_N, QREG_CC_N, mask);
3994 tcg_gen_rotr_i32(mask, mask, tmp);
a45f1763
RH		 3995 if (!TCGV_IS_UNUSED(tofs)) {
3996 tcg_gen_mov_i32(tofs, tmp);
3997 }
ac815f46
RH		 3998 } else {
3999 /* Immediate offset (and variable width) */
4000 tcg_gen_rotli_i32(QREG_CC_N, src, ofs);
4001 tcg_gen_andc_i32(QREG_CC_N, QREG_CC_N, mask);
4002 tcg_gen_rotri_i32(mask, mask, ofs);
a45f1763
RH		 4003 if (!TCGV_IS_UNUSED(tofs)) {
4004 tcg_gen_movi_i32(tofs, ofs);
4005 }
ac815f46
RH		 4006 }
4007 tcg_temp_free(tmp);
4008 }
4009 set_cc_op(s, CC_OP_LOGIC);
4010
4011 switch (insn & 0x0f00) {
4012 case 0x0a00: /* bfchg */
4013 tcg_gen_eqv_i32(src, src, mask);
4014 break;
4015 case 0x0c00: /* bfclr */
4016 tcg_gen_and_i32(src, src, mask);
4017 break;
a45f1763
RH		 4018 case 0x0d00: /* bfffo */
4019 gen_helper_bfffo_reg(DREG(ext, 12), QREG_CC_N, tofs, tlen);
4020 tcg_temp_free(tlen);
4021 tcg_temp_free(tofs);
4022 break;
ac815f46
RH		 4023 case 0x0e00: /* bfset */
4024 tcg_gen_orc_i32(src, src, mask);
4025 break;
4026 case 0x0800: /* bftst */
4027 /* flags already set; no other work to do. */
4028 break;
4029 default:
4030 g_assert_not_reached();
4031 }
4032 tcg_temp_free(mask);
4033}
4034
f2224f2c
RH		 4035DISAS_INSN(bfop_mem)
4036{
4037 int ext = read_im16(env, s);
4038 TCGv addr, len, ofs;
a45f1763 4039 TCGv_i64 t64;
f2224f2c
RH		 4040
4041 addr = gen_lea(env, s, insn, OS_UNSIZED);
4042 if (IS_NULL_QREG(addr)) {
4043 gen_addr_fault(s);
4044 return;
4045 }
4046
4047 if (ext & 0x20) {
4048 len = DREG(ext, 0);
4049 } else {
4050 len = tcg_const_i32(extract32(ext, 0, 5));
4051 }
4052 if (ext & 0x800) {
4053 ofs = DREG(ext, 6);
4054 } else {
4055 ofs = tcg_const_i32(extract32(ext, 6, 5));
4056 }
4057
4058 switch (insn & 0x0f00) {
4059 case 0x0a00: /* bfchg */
4060 gen_helper_bfchg_mem(QREG_CC_N, cpu_env, addr, ofs, len);
4061 break;
4062 case 0x0c00: /* bfclr */
4063 gen_helper_bfclr_mem(QREG_CC_N, cpu_env, addr, ofs, len);
4064 break;
a45f1763
RH		 4065 case 0x0d00: /* bfffo */
4066 t64 = tcg_temp_new_i64();
4067 gen_helper_bfffo_mem(t64, cpu_env, addr, ofs, len);
4068 tcg_gen_extr_i64_i32(DREG(ext, 12), QREG_CC_N, t64);
4069 tcg_temp_free_i64(t64);
4070 break;
f2224f2c
RH		 4071 case 0x0e00: /* bfset */
4072 gen_helper_bfset_mem(QREG_CC_N, cpu_env, addr, ofs, len);
4073 break;
4074 case 0x0800: /* bftst */
4075 gen_helper_bfexts_mem(QREG_CC_N, cpu_env, addr, ofs, len);
4076 break;
4077 default:
4078 g_assert_not_reached();
4079 }
4080 set_cc_op(s, CC_OP_LOGIC);
4081
4082 if (!(ext & 0x20)) {
4083 tcg_temp_free(len);
4084 }
4085 if (!(ext & 0x800)) {
4086 tcg_temp_free(ofs);
4087 }
4088}
4089
ac815f46
RH		 4090DISAS_INSN(bfins_reg)
4091{
4092 int ext = read_im16(env, s);
4093 TCGv dst = DREG(insn, 0);
4094 TCGv src = DREG(ext, 12);
4095 int len = ((extract32(ext, 0, 5) - 1) & 31) + 1;
4096 int ofs = extract32(ext, 6, 5); /* big bit-endian */
4097 int pos = 32 - ofs - len; /* little bit-endian */
4098 TCGv tmp;
4099
4100 tmp = tcg_temp_new();
4101
4102 if (ext & 0x20) {
4103 /* Variable width */
4104 tcg_gen_neg_i32(tmp, DREG(ext, 0));
4105 tcg_gen_andi_i32(tmp, tmp, 31);
4106 tcg_gen_shl_i32(QREG_CC_N, src, tmp);
4107 } else {
4108 /* Immediate width */
4109 tcg_gen_shli_i32(QREG_CC_N, src, 32 - len);
4110 }
4111 set_cc_op(s, CC_OP_LOGIC);
4112
4113 /* Immediate width and offset */
4114 if ((ext & 0x820) == 0) {
4115 /* Check for suitability for deposit. */
4116 if (pos >= 0) {
4117 tcg_gen_deposit_i32(dst, dst, src, pos, len);
4118 } else {
4119 uint32_t maski = -2U << (len - 1);
4120 uint32_t roti = (ofs + len) & 31;
4121 tcg_gen_andi_i32(tmp, src, ~maski);
4122 tcg_gen_rotri_i32(tmp, tmp, roti);
4123 tcg_gen_andi_i32(dst, dst, ror32(maski, roti));
4124 tcg_gen_or_i32(dst, dst, tmp);
4125 }
4126 } else {
4127 TCGv mask = tcg_temp_new();
4128 TCGv rot = tcg_temp_new();
4129
4130 if (ext & 0x20) {
4131 /* Variable width */
4132 tcg_gen_subi_i32(rot, DREG(ext, 0), 1);
4133 tcg_gen_andi_i32(rot, rot, 31);
4134 tcg_gen_movi_i32(mask, -2);
4135 tcg_gen_shl_i32(mask, mask, rot);
4136 tcg_gen_mov_i32(rot, DREG(ext, 0));
4137 tcg_gen_andc_i32(tmp, src, mask);
4138 } else {
4139 /* Immediate width (variable offset) */
4140 uint32_t maski = -2U << (len - 1);
4141 tcg_gen_andi_i32(tmp, src, ~maski);
4142 tcg_gen_movi_i32(mask, maski);
4143 tcg_gen_movi_i32(rot, len & 31);
4144 }
4145 if (ext & 0x800) {
4146 /* Variable offset */
4147 tcg_gen_add_i32(rot, rot, DREG(ext, 6));
4148 } else {
4149 /* Immediate offset (variable width) */
4150 tcg_gen_addi_i32(rot, rot, ofs);
4151 }
4152 tcg_gen_andi_i32(rot, rot, 31);
4153 tcg_gen_rotr_i32(mask, mask, rot);
4154 tcg_gen_rotr_i32(tmp, tmp, rot);
4155 tcg_gen_and_i32(dst, dst, mask);
4156 tcg_gen_or_i32(dst, dst, tmp);
4157
4158 tcg_temp_free(rot);
4159 tcg_temp_free(mask);
4160 }
4161 tcg_temp_free(tmp);
4162}
4163
f2224f2c
RH		 4164DISAS_INSN(bfins_mem)
4165{
4166 int ext = read_im16(env, s);
4167 TCGv src = DREG(ext, 12);
4168 TCGv addr, len, ofs;
4169
4170 addr = gen_lea(env, s, insn, OS_UNSIZED);
4171 if (IS_NULL_QREG(addr)) {
4172 gen_addr_fault(s);
4173 return;
4174 }
4175
4176 if (ext & 0x20) {
4177 len = DREG(ext, 0);
4178 } else {
4179 len = tcg_const_i32(extract32(ext, 0, 5));
4180 }
4181 if (ext & 0x800) {
4182 ofs = DREG(ext, 6);
4183 } else {
4184 ofs = tcg_const_i32(extract32(ext, 6, 5));
4185 }
4186
4187 gen_helper_bfins_mem(QREG_CC_N, cpu_env, addr, src, ofs, len);
4188 set_cc_op(s, CC_OP_LOGIC);
4189
4190 if (!(ext & 0x20)) {
4191 tcg_temp_free(len);
4192 }
4193 if (!(ext & 0x800)) {
4194 tcg_temp_free(ofs);
4195 }
4196}
4197
e6e5906b
PB		 4198DISAS_INSN(ff1)
4199{
e1f3808e 4200 TCGv reg;
821f7e76 4201 reg = DREG(insn, 0);
5dbb6784 4202 gen_logic_cc(s, reg, OS_LONG);
e1f3808e 4203 gen_helper_ff1(reg, reg);
e6e5906b
PB		 4204}
4205
e1f3808e 4206static TCGv gen_get_sr(DisasContext *s)
0633879f 4207{
e1f3808e
PB		 4208 TCGv ccr;
4209 TCGv sr;
0633879f
PB		 4210
4211 ccr = gen_get_ccr(s);
a7812ae4 4212 sr = tcg_temp_new();
e1f3808e
PB		 4213 tcg_gen_andi_i32(sr, QREG_SR, 0xffe0);
4214 tcg_gen_or_i32(sr, sr, ccr);
0633879f
PB		 4215 return sr;
4216}
4217
e6e5906b
PB		 4218DISAS_INSN(strldsr)
4219{
4220 uint16_t ext;
4221 uint32_t addr;
4222
4223 addr = s->pc - 2;
28b68cd7 4224 ext = read_im16(env, s);
0633879f 4225 if (ext != 0x46FC) {
e6e5906b 4226 gen_exception(s, addr, EXCP_UNSUPPORTED);
0633879f
PB		 4227 return;
4228 }
28b68cd7 4229 ext = read_im16(env, s);
0633879f 4230 if (IS_USER(s) || (ext & SR_S) == 0) {
e6e5906b 4231 gen_exception(s, addr, EXCP_PRIVILEGE);
0633879f
PB		 4232 return;
4233 }
4234 gen_push(s, gen_get_sr(s));
4235 gen_set_sr_im(s, ext, 0);
e6e5906b
PB		 4236}
4237
4238DISAS_INSN(move_from_sr)
4239{
e1f3808e 4240 TCGv sr;
0633879f 4241
7c0eb318 4242 if (IS_USER(s) && !m68k_feature(env, M68K_FEATURE_M68000)) {
0633879f
PB		 4243 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
4244 return;
4245 }
4246 sr = gen_get_sr(s);
7c0eb318 4247 DEST_EA(env, insn, OS_WORD, sr, NULL);
e6e5906b
PB		 4248}
4249
4250DISAS_INSN(move_to_sr)
4251{
0633879f
PB		 4252 if (IS_USER(s)) {
4253 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
4254 return;
4255 }
620c6cf6 4256 gen_set_sr(env, s, insn, 0);
0633879f 4257 gen_lookup_tb(s);
e6e5906b
PB		 4258}
4259
4260DISAS_INSN(move_from_usp)
4261{
0633879f
PB		 4262 if (IS_USER(s)) {
4263 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
4264 return;
4265 }
2a8327e8
GU		 4266 tcg_gen_ld_i32(AREG(insn, 0), cpu_env,
4267 offsetof(CPUM68KState, sp[M68K_USP]));
e6e5906b
PB		 4268}
4269
4270DISAS_INSN(move_to_usp)
4271{
0633879f
PB		 4272 if (IS_USER(s)) {
4273 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
4274 return;
4275 }
2a8327e8
GU		 4276 tcg_gen_st_i32(AREG(insn, 0), cpu_env,
4277 offsetof(CPUM68KState, sp[M68K_USP]));
e6e5906b
PB		 4278}
4279
4280DISAS_INSN(halt)
4281{
e1f3808e 4282 gen_exception(s, s->pc, EXCP_HALT_INSN);
e6e5906b
PB		 4283}
4284
4285DISAS_INSN(stop)
4286{
0633879f
PB		 4287 uint16_t ext;
4288
4289 if (IS_USER(s)) {
4290 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
4291 return;
4292 }
4293
28b68cd7 4294 ext = read_im16(env, s);
0633879f
PB		 4295
4296 gen_set_sr_im(s, ext, 0);
259186a7 4297 tcg_gen_movi_i32(cpu_halted, 1);
e1f3808e 4298 gen_exception(s, s->pc, EXCP_HLT);
e6e5906b
PB		 4299}
4300
4301DISAS_INSN(rte)
4302{
0633879f
PB		 4303 if (IS_USER(s)) {
4304 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
4305 return;
4306 }
4307 gen_exception(s, s->pc - 2, EXCP_RTE);
e6e5906b
PB		 4308}
4309
4310DISAS_INSN(movec)
4311{
0633879f 4312 uint16_t ext;
e1f3808e 4313 TCGv reg;
0633879f
PB		 4314
4315 if (IS_USER(s)) {
4316 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
4317 return;
4318 }
4319
28b68cd7 4320 ext = read_im16(env, s);
0633879f
PB		 4321
4322 if (ext & 0x8000) {
4323 reg = AREG(ext, 12);
4324 } else {
4325 reg = DREG(ext, 12);
4326 }
e1f3808e 4327 gen_helper_movec(cpu_env, tcg_const_i32(ext & 0xfff), reg);
0633879f 4328 gen_lookup_tb(s);
e6e5906b
PB		 4329}
4330
4331DISAS_INSN(intouch)
4332{
0633879f
PB		 4333 if (IS_USER(s)) {
4334 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
4335 return;
4336 }
4337 /* ICache fetch. Implement as no-op. */
e6e5906b
PB		 4338}
4339
4340DISAS_INSN(cpushl)
4341{
0633879f
PB		 4342 if (IS_USER(s)) {
4343 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
4344 return;
4345 }
4346 /* Cache push/invalidate. Implement as no-op. */
e6e5906b
PB		 4347}
4348
4349DISAS_INSN(wddata)
4350{
4351 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
4352}
4353
4354DISAS_INSN(wdebug)
4355{
a47dddd7
AF		 4356 M68kCPU *cpu = m68k_env_get_cpu(env);
4357
0633879f
PB		 4358 if (IS_USER(s)) {
4359 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
4360 return;
4361 }
4362 /* TODO: Implement wdebug. */
a47dddd7 4363 cpu_abort(CPU(cpu), "WDEBUG not implemented");
e6e5906b
PB		 4364}
4365
4366DISAS_INSN(trap)
4367{
4368 gen_exception(s, s->pc - 2, EXCP_TRAP0 + (insn & 0xf));
4369}
4370
ba624944
LV		 4371static void gen_load_fcr(DisasContext *s, TCGv res, int reg)
4372{
4373 switch (reg) {
4374 case M68K_FPIAR:
4375 tcg_gen_movi_i32(res, 0);
4376 break;
4377 case M68K_FPSR:
4378 tcg_gen_ld_i32(res, cpu_env, offsetof(CPUM68KState, fpsr));
4379 break;
4380 case M68K_FPCR:
4381 tcg_gen_ld_i32(res, cpu_env, offsetof(CPUM68KState, fpcr));
4382 break;
4383 }
4384}
4385
4386static void gen_store_fcr(DisasContext *s, TCGv val, int reg)
4387{
4388 switch (reg) {
4389 case M68K_FPIAR:
4390 break;
4391 case M68K_FPSR:
4392 tcg_gen_st_i32(val, cpu_env, offsetof(CPUM68KState, fpsr));
4393 break;
4394 case M68K_FPCR:
4395 gen_helper_set_fpcr(cpu_env, val);
4396 break;
4397 }
4398}
4399
4400static void gen_qemu_store_fcr(DisasContext *s, TCGv addr, int reg)
4401{
4402 int index = IS_USER(s);
4403 TCGv tmp;
4404
4405 tmp = tcg_temp_new();
4406 gen_load_fcr(s, tmp, reg);
4407 tcg_gen_qemu_st32(tmp, addr, index);
4408 tcg_temp_free(tmp);
4409}
4410
4411static void gen_qemu_load_fcr(DisasContext *s, TCGv addr, int reg)
4412{
4413 int index = IS_USER(s);
4414 TCGv tmp;
4415
4416 tmp = tcg_temp_new();
4417 tcg_gen_qemu_ld32u(tmp, addr, index);
4418 gen_store_fcr(s, tmp, reg);
4419 tcg_temp_free(tmp);
4420}
4421
4422
860b9ac7
LV		 4423static void gen_op_fmove_fcr(CPUM68KState *env, DisasContext *s,
4424 uint32_t insn, uint32_t ext)
4425{
4426 int mask = (ext >> 10) & 7;
4427 int is_write = (ext >> 13) & 1;
ba624944
LV		 4428 int mode = extract32(insn, 3, 3);
4429 int i;
4430 TCGv addr, tmp;
860b9ac7 4431
ba624944
LV		 4432 switch (mode) {
4433 case 0: /* Dn */
4434 if (mask != M68K_FPIAR && mask != M68K_FPSR && mask != M68K_FPCR) {
4435 gen_exception(s, s->insn_pc, EXCP_ILLEGAL);
4436 return;
4437 }
860b9ac7 4438 if (is_write) {
ba624944
LV		 4439 gen_load_fcr(s, DREG(insn, 0), mask);
4440 } else {
4441 gen_store_fcr(s, DREG(insn, 0), mask);
860b9ac7 4442 }
ba624944
LV		 4443 return;
4444 case 1: /* An, only with FPIAR */
4445 if (mask != M68K_FPIAR) {
4446 gen_exception(s, s->insn_pc, EXCP_ILLEGAL);
4447 return;
4448 }
4449 if (is_write) {
4450 gen_load_fcr(s, AREG(insn, 0), mask);
4451 } else {
4452 gen_store_fcr(s, AREG(insn, 0), mask);
4453 }
4454 return;
4455 default:
860b9ac7
LV		 4456 break;
4457 }
ba624944
LV		 4458
4459 tmp = gen_lea(env, s, insn, OS_LONG);
4460 if (IS_NULL_QREG(tmp)) {
4461 gen_addr_fault(s);
4462 return;
4463 }
4464
4465 addr = tcg_temp_new();
4466 tcg_gen_mov_i32(addr, tmp);
4467
4468 /* mask:
4469 *
4470 * 0b100 Floating-Point Control Register
4471 * 0b010 Floating-Point Status Register
4472 * 0b001 Floating-Point Instruction Address Register
4473 *
4474 */
4475
4476 if (is_write && mode == 4) {
4477 for (i = 2; i >= 0; i--, mask >>= 1) {
4478 if (mask & 1) {
4479 gen_qemu_store_fcr(s, addr, 1 << i);
4480 if (mask != 1) {
4481 tcg_gen_subi_i32(addr, addr, opsize_bytes(OS_LONG));
4482 }
4483 }
4484 }
4485 tcg_gen_mov_i32(AREG(insn, 0), addr);
4486 } else {
4487 for (i = 0; i < 3; i++, mask >>= 1) {
4488 if (mask & 1) {
4489 if (is_write) {
4490 gen_qemu_store_fcr(s, addr, 1 << i);
4491 } else {
4492 gen_qemu_load_fcr(s, addr, 1 << i);
4493 }
4494 if (mask != 1 || mode == 3) {
4495 tcg_gen_addi_i32(addr, addr, opsize_bytes(OS_LONG));
4496 }
4497 }
4498 }
4499 if (mode == 3) {
4500 tcg_gen_mov_i32(AREG(insn, 0), addr);
4501 }
4502 }
4503 tcg_temp_free_i32(addr);
860b9ac7
LV		 4504}
4505
a1e58ddc
LV		 4506static void gen_op_fmovem(CPUM68KState *env, DisasContext *s,
4507 uint32_t insn, uint32_t ext)
4508{
4509 int opsize;
4510 TCGv addr, tmp;
4511 int mode = (ext >> 11) & 0x3;
4512 int is_load = ((ext & 0x2000) == 0);
4513
4514 if (m68k_feature(s->env, M68K_FEATURE_FPU)) {
4515 opsize = OS_EXTENDED;
4516 } else {
4517 opsize = OS_DOUBLE; /* FIXME */
4518 }
4519
4520 addr = gen_lea(env, s, insn, opsize);
4521 if (IS_NULL_QREG(addr)) {
4522 gen_addr_fault(s);
4523 return;
4524 }
4525
4526 tmp = tcg_temp_new();
4527 if (mode & 0x1) {
4528 /* Dynamic register list */
4529 tcg_gen_ext8u_i32(tmp, DREG(ext, 4));
4530 } else {
4531 /* Static register list */
4532 tcg_gen_movi_i32(tmp, ext & 0xff);
4533 }
4534
4535 if (!is_load && (mode & 2) == 0) {
4536 /* predecrement addressing mode
4537 * only available to store register to memory
4538 */
4539 if (opsize == OS_EXTENDED) {
4540 gen_helper_fmovemx_st_predec(tmp, cpu_env, addr, tmp);
4541 } else {
4542 gen_helper_fmovemd_st_predec(tmp, cpu_env, addr, tmp);
4543 }
4544 } else {
4545 /* postincrement addressing mode */
4546 if (opsize == OS_EXTENDED) {
4547 if (is_load) {
4548 gen_helper_fmovemx_ld_postinc(tmp, cpu_env, addr, tmp);
4549 } else {
4550 gen_helper_fmovemx_st_postinc(tmp, cpu_env, addr, tmp);
4551 }
4552 } else {
4553 if (is_load) {
4554 gen_helper_fmovemd_ld_postinc(tmp, cpu_env, addr, tmp);
4555 } else {
4556 gen_helper_fmovemd_st_postinc(tmp, cpu_env, addr, tmp);
4557 }
4558 }
4559 }
4560 if ((insn & 070) == 030 || (insn & 070) == 040) {
4561 tcg_gen_mov_i32(AREG(insn, 0), tmp);
4562 }
4563 tcg_temp_free(tmp);
4564}
4565
e6e5906b
PB		 4566/* ??? FP exceptions are not implemented. Most exceptions are deferred until
4567 immediately before the next FP instruction is executed. */
4568DISAS_INSN(fpu)
4569{
4570 uint16_t ext;
4571 int opmode;
e6e5906b 4572 int opsize;
f83311e4 4573 TCGv_ptr cpu_src, cpu_dest;
e6e5906b 4574
28b68cd7 4575 ext = read_im16(env, s);
e6e5906b
PB		 4576 opmode = ext & 0x7f;
4577 switch ((ext >> 13) & 7) {
9d403660 4578 case 0:
e6e5906b
PB		 4579 break;
4580 case 1:
4581 goto undef;
9d403660
LV		 4582 case 2:
4583 if (insn == 0xf200 && (ext & 0xfc00) == 0x5c00) {
4584 /* fmovecr */
4585 TCGv rom_offset = tcg_const_i32(opmode);
4586 cpu_dest = gen_fp_ptr(REG(ext, 7));
4587 gen_helper_fconst(cpu_env, cpu_dest, rom_offset);
4588 tcg_temp_free_ptr(cpu_dest);
4589 tcg_temp_free(rom_offset);
4590 return;
4591 }
4592 break;
e6e5906b 4593 case 3: /* fmove out */
f83311e4 4594 cpu_src = gen_fp_ptr(REG(ext, 7));
69e69822 4595 opsize = ext_opsize(ext, 10);
f83311e4
LV		 4596 if (gen_ea_fp(env, s, insn, opsize, cpu_src, EA_STORE) == -1) {
4597 gen_addr_fault(s);
e6e5906b 4598 }
ba624944 4599 gen_helper_ftst(cpu_env, cpu_src);
f83311e4 4600 tcg_temp_free_ptr(cpu_src);
e6e5906b
PB		 4601 return;
4602 case 4: /* fmove to control register. */
e6e5906b 4603 case 5: /* fmove from control register. */
860b9ac7
LV		 4604 gen_op_fmove_fcr(env, s, insn, ext);
4605 return;
5fafdf24 4606 case 6: /* fmovem */
e6e5906b 4607 case 7:
a1e58ddc
LV		 4608 if ((ext & 0x1000) == 0 && !m68k_feature(s->env, M68K_FEATURE_FPU)) {
4609 goto undef;
e6e5906b 4610 }
a1e58ddc 4611 gen_op_fmovem(env, s, insn, ext);
e6e5906b
PB		 4612 return;
4613 }
4614 if (ext & (1 << 14)) {
e6e5906b 4615 /* Source effective address. */
69e69822 4616 opsize = ext_opsize(ext, 10);
f83311e4
LV		 4617 cpu_src = gen_fp_result_ptr();
4618 if (gen_ea_fp(env, s, insn, opsize, cpu_src, EA_LOADS) == -1) {
4619 gen_addr_fault(s);
4620 return;
e6e5906b
PB		 4621 }
4622 } else {
4623 /* Source register. */
f83311e4
LV		 4624 opsize = OS_EXTENDED;
4625 cpu_src = gen_fp_ptr(REG(ext, 10));
e6e5906b 4626 }
f83311e4 4627 cpu_dest = gen_fp_ptr(REG(ext, 7));
e6e5906b 4628 switch (opmode) {
77bdb229 4629 case 0: /* fmove */
f83311e4 4630 gen_fp_move(cpu_dest, cpu_src);
e6e5906b 4631 break;
77bdb229
LV		 4632 case 0x40: /* fsmove */
4633 gen_helper_fsround(cpu_env, cpu_dest, cpu_src);
4634 break;
4635 case 0x44: /* fdmove */
4636 gen_helper_fdround(cpu_env, cpu_dest, cpu_src);
4637 break;
e6e5906b 4638 case 1: /* fint */
f83311e4 4639 gen_helper_firound(cpu_env, cpu_dest, cpu_src);
e6e5906b
PB		 4640 break;
4641 case 3: /* fintrz */
f83311e4 4642 gen_helper_fitrunc(cpu_env, cpu_dest, cpu_src);
e6e5906b 4643 break;
a51b6bc3 4644 case 4: /* fsqrt */
f83311e4 4645 gen_helper_fsqrt(cpu_env, cpu_dest, cpu_src);
e6e5906b 4646 break;
a51b6bc3
LV		 4647 case 0x41: /* fssqrt */
4648 gen_helper_fssqrt(cpu_env, cpu_dest, cpu_src);
4649 break;
4650 case 0x45: /* fdsqrt */
4651 gen_helper_fdsqrt(cpu_env, cpu_dest, cpu_src);
4652 break;
77bdb229 4653 case 0x18: /* fabs */
f83311e4 4654 gen_helper_fabs(cpu_env, cpu_dest, cpu_src);
e6e5906b 4655 break;
77bdb229
LV		 4656 case 0x58: /* fsabs */
4657 gen_helper_fsabs(cpu_env, cpu_dest, cpu_src);
4658 break;
4659 case 0x5c: /* fdabs */
4660 gen_helper_fdabs(cpu_env, cpu_dest, cpu_src);
4661 break;
4662 case 0x1a: /* fneg */
4663 gen_helper_fneg(cpu_env, cpu_dest, cpu_src);
4664 break;
4665 case 0x5a: /* fsneg */
4666 gen_helper_fsneg(cpu_env, cpu_dest, cpu_src);
4667 break;
4668 case 0x5e: /* fdneg */
4669 gen_helper_fdneg(cpu_env, cpu_dest, cpu_src);
e6e5906b 4670 break;
a51b6bc3 4671 case 0x20: /* fdiv */
f83311e4 4672 gen_helper_fdiv(cpu_env, cpu_dest, cpu_src, cpu_dest);
e6e5906b 4673 break;
a51b6bc3
LV		 4674 case 0x60: /* fsdiv */
4675 gen_helper_fsdiv(cpu_env, cpu_dest, cpu_src, cpu_dest);
4676 break;
4677 case 0x64: /* fddiv */
4678 gen_helper_fddiv(cpu_env, cpu_dest, cpu_src, cpu_dest);
4679 break;
4680 case 0x22: /* fadd */
f83311e4 4681 gen_helper_fadd(cpu_env, cpu_dest, cpu_src, cpu_dest);
e6e5906b 4682 break;
a51b6bc3
LV		 4683 case 0x62: /* fsadd */
4684 gen_helper_fsadd(cpu_env, cpu_dest, cpu_src, cpu_dest);
4685 break;
4686 case 0x66: /* fdadd */
4687 gen_helper_fdadd(cpu_env, cpu_dest, cpu_src, cpu_dest);
4688 break;
4689 case 0x23: /* fmul */
f83311e4 4690 gen_helper_fmul(cpu_env, cpu_dest, cpu_src, cpu_dest);
e6e5906b 4691 break;
a51b6bc3
LV		 4692 case 0x63: /* fsmul */
4693 gen_helper_fsmul(cpu_env, cpu_dest, cpu_src, cpu_dest);
4694 break;
4695 case 0x67: /* fdmul */
4696 gen_helper_fdmul(cpu_env, cpu_dest, cpu_src, cpu_dest);
4697 break;
2f77995c
LV		 4698 case 0x24: /* fsgldiv */
4699 gen_helper_fsgldiv(cpu_env, cpu_dest, cpu_src, cpu_dest);
4700 break;
4701 case 0x27: /* fsglmul */
4702 gen_helper_fsglmul(cpu_env, cpu_dest, cpu_src, cpu_dest);
4703 break;
a51b6bc3 4704 case 0x28: /* fsub */
f83311e4 4705 gen_helper_fsub(cpu_env, cpu_dest, cpu_src, cpu_dest);
e6e5906b 4706 break;
a51b6bc3
LV		 4707 case 0x68: /* fssub */
4708 gen_helper_fssub(cpu_env, cpu_dest, cpu_src, cpu_dest);
4709 break;
4710 case 0x6c: /* fdsub */
4711 gen_helper_fdsub(cpu_env, cpu_dest, cpu_src, cpu_dest);
4712 break;
e6e5906b 4713 case 0x38: /* fcmp */
ba624944
LV		 4714 gen_helper_fcmp(cpu_env, cpu_src, cpu_dest);
4715 return;
e6e5906b 4716 case 0x3a: /* ftst */
ba624944
LV		 4717 gen_helper_ftst(cpu_env, cpu_src);
4718 return;
e6e5906b
PB		 4719 default:
4720 goto undef;
4721 }
f83311e4 4722 tcg_temp_free_ptr(cpu_src);
ba624944 4723 gen_helper_ftst(cpu_env, cpu_dest);
f83311e4 4724 tcg_temp_free_ptr(cpu_dest);
e6e5906b
PB		 4725 return;
4726undef:
a7812ae4 4727 /* FIXME: Is this right for offset addressing modes? */
e6e5906b 4728 s->pc -= 2;
d4d79bb1 4729 disas_undef_fpu(env, s, insn);
e6e5906b
PB		 4730}
4731
dd337bf8 4732static void gen_fcc_cond(DisasCompare *c, DisasContext *s, int cond)
e6e5906b 4733{
dd337bf8 4734 TCGv fpsr;
e6e5906b 4735
dd337bf8
LV		 4736 c->g1 = 1;
4737 c->v2 = tcg_const_i32(0);
4738 c->g2 = 0;
4739 /* TODO: Raise BSUN exception. */
ba624944
LV		 4740 fpsr = tcg_temp_new();
4741 gen_load_fcr(s, fpsr, M68K_FPSR);
dd337bf8 4742 switch (cond) {
ba624944
LV		 4743 case 0: /* False */
4744 case 16: /* Signaling False */
dd337bf8
LV		 4745 c->v1 = c->v2;
4746 c->tcond = TCG_COND_NEVER;
e6e5906b 4747 break;
ba624944
LV		 4748 case 1: /* EQual Z */
4749 case 17: /* Signaling EQual Z */
dd337bf8
LV		 4750 c->v1 = tcg_temp_new();
4751 c->g1 = 0;
4752 tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_Z);
4753 c->tcond = TCG_COND_NE;
e6e5906b 4754 break;
ba624944
LV		 4755 case 2: /* Ordered Greater Than !(A || Z || N) */
4756 case 18: /* Greater Than !(A || Z || N) */
dd337bf8
LV		 4757 c->v1 = tcg_temp_new();
4758 c->g1 = 0;
4759 tcg_gen_andi_i32(c->v1, fpsr,
ba624944 4760 FPSR_CC_A | FPSR_CC_Z | FPSR_CC_N);
dd337bf8 4761 c->tcond = TCG_COND_EQ;
e6e5906b 4762 break;
ba624944
LV		 4763 case 3: /* Ordered Greater than or Equal Z || !(A || N) */
4764 case 19: /* Greater than or Equal Z || !(A || N) */
dd337bf8
LV		 4765 c->v1 = tcg_temp_new();
4766 c->g1 = 0;
4767 tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A);
4768 tcg_gen_shli_i32(c->v1, c->v1, ctz32(FPSR_CC_N) - ctz32(FPSR_CC_A));
4769 tcg_gen_andi_i32(fpsr, fpsr, FPSR_CC_Z | FPSR_CC_N);
4770 tcg_gen_or_i32(c->v1, c->v1, fpsr);
4771 tcg_gen_xori_i32(c->v1, c->v1, FPSR_CC_N);
4772 c->tcond = TCG_COND_NE;
e6e5906b 4773 break;
ba624944
LV		 4774 case 4: /* Ordered Less Than !(!N || A || Z); */
4775 case 20: /* Less Than !(!N || A || Z); */
dd337bf8
LV		 4776 c->v1 = tcg_temp_new();
4777 c->g1 = 0;
4778 tcg_gen_xori_i32(c->v1, fpsr, FPSR_CC_N);
4779 tcg_gen_andi_i32(c->v1, c->v1, FPSR_CC_N | FPSR_CC_A | FPSR_CC_Z);
4780 c->tcond = TCG_COND_EQ;
e6e5906b 4781 break;
ba624944
LV		 4782 case 5: /* Ordered Less than or Equal Z || (N && !A) */
4783 case 21: /* Less than or Equal Z || (N && !A) */
dd337bf8
LV		 4784 c->v1 = tcg_temp_new();
4785 c->g1 = 0;
4786 tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A);
4787 tcg_gen_shli_i32(c->v1, c->v1, ctz32(FPSR_CC_N) - ctz32(FPSR_CC_A));
4788 tcg_gen_andc_i32(c->v1, fpsr, c->v1);
4789 tcg_gen_andi_i32(c->v1, c->v1, FPSR_CC_Z | FPSR_CC_N);
4790 c->tcond = TCG_COND_NE;
e6e5906b 4791 break;
ba624944
LV		 4792 case 6: /* Ordered Greater or Less than !(A || Z) */
4793 case 22: /* Greater or Less than !(A || Z) */
dd337bf8
LV		 4794 c->v1 = tcg_temp_new();
4795 c->g1 = 0;
4796 tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A | FPSR_CC_Z);
4797 c->tcond = TCG_COND_EQ;
e6e5906b 4798 break;
ba624944
LV		 4799 case 7: /* Ordered !A */
4800 case 23: /* Greater, Less or Equal !A */
dd337bf8
LV		 4801 c->v1 = tcg_temp_new();
4802 c->g1 = 0;
4803 tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A);
4804 c->tcond = TCG_COND_EQ;
e6e5906b 4805 break;
ba624944
LV		 4806 case 8: /* Unordered A */
4807 case 24: /* Not Greater, Less or Equal A */
dd337bf8
LV		 4808 c->v1 = tcg_temp_new();
4809 c->g1 = 0;
4810 tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A);
4811 c->tcond = TCG_COND_NE;
e6e5906b 4812 break;
ba624944
LV		 4813 case 9: /* Unordered or Equal A || Z */
4814 case 25: /* Not Greater or Less then A || Z */
dd337bf8
LV		 4815 c->v1 = tcg_temp_new();
4816 c->g1 = 0;
4817 tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A | FPSR_CC_Z);
4818 c->tcond = TCG_COND_NE;
e6e5906b 4819 break;
ba624944
LV		 4820 case 10: /* Unordered or Greater Than A || !(N || Z)) */
4821 case 26: /* Not Less or Equal A || !(N || Z)) */
dd337bf8
LV		 4822 c->v1 = tcg_temp_new();
4823 c->g1 = 0;
4824 tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_Z);
4825 tcg_gen_shli_i32(c->v1, c->v1, ctz32(FPSR_CC_N) - ctz32(FPSR_CC_Z));
4826 tcg_gen_andi_i32(fpsr, fpsr, FPSR_CC_A | FPSR_CC_N);
4827 tcg_gen_or_i32(c->v1, c->v1, fpsr);
4828 tcg_gen_xori_i32(c->v1, c->v1, FPSR_CC_N);
4829 c->tcond = TCG_COND_NE;
e6e5906b 4830 break;
ba624944
LV		 4831 case 11: /* Unordered or Greater or Equal A || Z || !N */
4832 case 27: /* Not Less Than A || Z || !N */
dd337bf8
LV		 4833 c->v1 = tcg_temp_new();
4834 c->g1 = 0;
4835 tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A | FPSR_CC_Z | FPSR_CC_N);
4836 tcg_gen_xori_i32(c->v1, c->v1, FPSR_CC_N);
4837 c->tcond = TCG_COND_NE;
e6e5906b 4838 break;
ba624944
LV		 4839 case 12: /* Unordered or Less Than A || (N && !Z) */
4840 case 28: /* Not Greater than or Equal A || (N && !Z) */
dd337bf8
LV		 4841 c->v1 = tcg_temp_new();
4842 c->g1 = 0;
4843 tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_Z);
4844 tcg_gen_shli_i32(c->v1, c->v1, ctz32(FPSR_CC_N) - ctz32(FPSR_CC_Z));
4845 tcg_gen_andc_i32(c->v1, fpsr, c->v1);
4846 tcg_gen_andi_i32(c->v1, c->v1, FPSR_CC_A | FPSR_CC_N);
4847 c->tcond = TCG_COND_NE;
e6e5906b 4848 break;
ba624944
LV		 4849 case 13: /* Unordered or Less or Equal A || Z || N */
4850 case 29: /* Not Greater Than A || Z || N */
dd337bf8
LV		 4851 c->v1 = tcg_temp_new();
4852 c->g1 = 0;
4853 tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A | FPSR_CC_Z | FPSR_CC_N);
4854 c->tcond = TCG_COND_NE;
e6e5906b 4855 break;
ba624944
LV		 4856 case 14: /* Not Equal !Z */
4857 case 30: /* Signaling Not Equal !Z */
dd337bf8
LV		 4858 c->v1 = tcg_temp_new();
4859 c->g1 = 0;
4860 tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_Z);
4861 c->tcond = TCG_COND_EQ;
e6e5906b 4862 break;
ba624944
LV		 4863 case 15: /* True */
4864 case 31: /* Signaling True */
dd337bf8
LV		 4865 c->v1 = c->v2;
4866 c->tcond = TCG_COND_ALWAYS;
e6e5906b
PB		 4867 break;
4868 }
ba624944 4869 tcg_temp_free(fpsr);
dd337bf8
LV		 4870}
4871
4872static void gen_fjmpcc(DisasContext *s, int cond, TCGLabel *l1)
4873{
4874 DisasCompare c;
4875
4876 gen_fcc_cond(&c, s, cond);
7cd7b5ca 4877 update_cc_op(s);
dd337bf8
LV		 4878 tcg_gen_brcond_i32(c.tcond, c.v1, c.v2, l1);
4879 free_cond(&c);
4880}
4881
4882DISAS_INSN(fbcc)
4883{
4884 uint32_t offset;
4885 uint32_t base;
4886 TCGLabel *l1;
4887
4888 base = s->pc;
4889 offset = (int16_t)read_im16(env, s);
4890 if (insn & (1 << 6)) {
4891 offset = (offset << 16) | read_im16(env, s);
4892 }
4893
4894 l1 = gen_new_label();
4895 update_cc_op(s);
4896 gen_fjmpcc(s, insn & 0x3f, l1);
e6e5906b
PB		 4897 gen_jmp_tb(s, 0, s->pc);
4898 gen_set_label(l1);
dd337bf8
LV		 4899 gen_jmp_tb(s, 1, base + offset);
4900}
4901
4902DISAS_INSN(fscc)
4903{
4904 DisasCompare c;
4905 int cond;
4906 TCGv tmp;
4907 uint16_t ext;
4908
4909 ext = read_im16(env, s);
4910 cond = ext & 0x3f;
4911 gen_fcc_cond(&c, s, cond);
4912
4913 tmp = tcg_temp_new();
4914 tcg_gen_setcond_i32(c.tcond, tmp, c.v1, c.v2);
4915 free_cond(&c);
4916
4917 tcg_gen_neg_i32(tmp, tmp);
4918 DEST_EA(env, insn, OS_BYTE, tmp, NULL);
4919 tcg_temp_free(tmp);
e6e5906b
PB		 4920}
4921
0633879f
PB		 4922DISAS_INSN(frestore)
4923{
a47dddd7
AF		 4924 M68kCPU *cpu = m68k_env_get_cpu(env);
4925
0633879f 4926 /* TODO: Implement frestore. */
a47dddd7 4927 cpu_abort(CPU(cpu), "FRESTORE not implemented");
0633879f
PB		 4928}
4929
4930DISAS_INSN(fsave)
4931{
a47dddd7
AF		 4932 M68kCPU *cpu = m68k_env_get_cpu(env);
4933
0633879f 4934 /* TODO: Implement fsave. */
a47dddd7 4935 cpu_abort(CPU(cpu), "FSAVE not implemented");
0633879f
PB		 4936}
4937
e1f3808e 4938static inline TCGv gen_mac_extract_word(DisasContext *s, TCGv val, int upper)
acf930aa 4939{
a7812ae4 4940 TCGv tmp = tcg_temp_new();
acf930aa
PB		 4941 if (s->env->macsr & MACSR_FI) {
4942 if (upper)
e1f3808e 4943 tcg_gen_andi_i32(tmp, val, 0xffff0000);
acf930aa 4944 else
e1f3808e 4945 tcg_gen_shli_i32(tmp, val, 16);
acf930aa
PB		 4946 } else if (s->env->macsr & MACSR_SU) {
4947 if (upper)
e1f3808e 4948 tcg_gen_sari_i32(tmp, val, 16);
acf930aa 4949 else
e1f3808e 4950 tcg_gen_ext16s_i32(tmp, val);
acf930aa
PB		 4951 } else {
4952 if (upper)
e1f3808e 4953 tcg_gen_shri_i32(tmp, val, 16);
acf930aa 4954 else
e1f3808e 4955 tcg_gen_ext16u_i32(tmp, val);
acf930aa
PB		 4956 }
4957 return tmp;
4958}
4959
e1f3808e
PB		 4960static void gen_mac_clear_flags(void)
4961{
4962 tcg_gen_andi_i32(QREG_MACSR, QREG_MACSR,
4963 ~(MACSR_V | MACSR_Z | MACSR_N | MACSR_EV));
4964}
4965
acf930aa
PB		 4966DISAS_INSN(mac)
4967{
e1f3808e
PB		 4968 TCGv rx;
4969 TCGv ry;
acf930aa
PB		 4970 uint16_t ext;
4971 int acc;
e1f3808e
PB		 4972 TCGv tmp;
4973 TCGv addr;
4974 TCGv loadval;
acf930aa 4975 int dual;
e1f3808e
PB		 4976 TCGv saved_flags;
4977
a7812ae4
PB		 4978 if (!s->done_mac) {
4979 s->mactmp = tcg_temp_new_i64();
4980 s->done_mac = 1;
4981 }
acf930aa 4982
28b68cd7 4983 ext = read_im16(env, s);
acf930aa
PB		 4984
4985 acc = ((insn >> 7) & 1) | ((ext >> 3) & 2);
4986 dual = ((insn & 0x30) != 0 && (ext & 3) != 0);
d315c888 4987 if (dual && !m68k_feature(s->env, M68K_FEATURE_CF_EMAC_B)) {
d4d79bb1 4988 disas_undef(env, s, insn);
d315c888
PB		 4989 return;
4990 }
acf930aa
PB		 4991 if (insn & 0x30) {
4992 /* MAC with load. */
d4d79bb1 4993 tmp = gen_lea(env, s, insn, OS_LONG);
a7812ae4 4994 addr = tcg_temp_new();
e1f3808e 4995 tcg_gen_and_i32(addr, tmp, QREG_MAC_MASK);
acf930aa
PB		 4996 /* Load the value now to ensure correct exception behavior.
4997 Perform writeback after reading the MAC inputs. */
4998 loadval = gen_load(s, OS_LONG, addr, 0);
4999
5000 acc ^= 1;
5001 rx = (ext & 0x8000) ? AREG(ext, 12) : DREG(insn, 12);
5002 ry = (ext & 8) ? AREG(ext, 0) : DREG(ext, 0);
5003 } else {
e1f3808e 5004 loadval = addr = NULL_QREG;
acf930aa
PB		 5005 rx = (insn & 0x40) ? AREG(insn, 9) : DREG(insn, 9);
5006 ry = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0);
5007 }
5008
e1f3808e
PB		 5009 gen_mac_clear_flags();
5010#if 0
acf930aa 5011 l1 = -1;
e1f3808e 5012 /* Disabled because conditional branches clobber temporary vars. */
acf930aa
PB		 5013 if ((s->env->macsr & MACSR_OMC) != 0 && !dual) {
5014 /* Skip the multiply if we know we will ignore it. */
5015 l1 = gen_new_label();
a7812ae4 5016 tmp = tcg_temp_new();
e1f3808e 5017 tcg_gen_andi_i32(tmp, QREG_MACSR, 1 << (acc + 8));
acf930aa
PB		 5018 gen_op_jmp_nz32(tmp, l1);
5019 }
e1f3808e 5020#endif
acf930aa
PB		 5021
5022 if ((ext & 0x0800) == 0) {
5023 /* Word. */
5024 rx = gen_mac_extract_word(s, rx, (ext & 0x80) != 0);
5025 ry = gen_mac_extract_word(s, ry, (ext & 0x40) != 0);
5026 }
5027 if (s->env->macsr & MACSR_FI) {
e1f3808e 5028 gen_helper_macmulf(s->mactmp, cpu_env, rx, ry);
acf930aa
PB		 5029 } else {
5030 if (s->env->macsr & MACSR_SU)
e1f3808e 5031 gen_helper_macmuls(s->mactmp, cpu_env, rx, ry);
acf930aa 5032 else
e1f3808e 5033 gen_helper_macmulu(s->mactmp, cpu_env, rx, ry);
acf930aa
PB		 5034 switch ((ext >> 9) & 3) {
5035 case 1:
e1f3808e 5036 tcg_gen_shli_i64(s->mactmp, s->mactmp, 1);
acf930aa
PB		 5037 break;
5038 case 3:
e1f3808e 5039 tcg_gen_shri_i64(s->mactmp, s->mactmp, 1);
acf930aa
PB		 5040 break;
5041 }
5042 }
5043
5044 if (dual) {
5045 /* Save the overflow flag from the multiply. */
a7812ae4 5046 saved_flags = tcg_temp_new();
e1f3808e
PB		 5047 tcg_gen_mov_i32(saved_flags, QREG_MACSR);
5048 } else {
5049 saved_flags = NULL_QREG;
acf930aa
PB		 5050 }
5051
e1f3808e
PB		 5052#if 0
5053 /* Disabled because conditional branches clobber temporary vars. */
acf930aa
PB		 5054 if ((s->env->macsr & MACSR_OMC) != 0 && dual) {
5055 /* Skip the accumulate if the value is already saturated. */
5056 l1 = gen_new_label();
a7812ae4 5057 tmp = tcg_temp_new();
351326a6 5058 gen_op_and32(tmp, QREG_MACSR, tcg_const_i32(MACSR_PAV0 << acc));
acf930aa
PB		 5059 gen_op_jmp_nz32(tmp, l1);
5060 }
e1f3808e 5061#endif
acf930aa
PB		 5062
5063 if (insn & 0x100)
e1f3808e 5064 tcg_gen_sub_i64(MACREG(acc), MACREG(acc), s->mactmp);
acf930aa 5065 else
e1f3808e 5066 tcg_gen_add_i64(MACREG(acc), MACREG(acc), s->mactmp);
acf930aa
PB		 5067
5068 if (s->env->macsr & MACSR_FI)
e1f3808e 5069 gen_helper_macsatf(cpu_env, tcg_const_i32(acc));
acf930aa 5070 else if (s->env->macsr & MACSR_SU)
e1f3808e 5071 gen_helper_macsats(cpu_env, tcg_const_i32(acc));
acf930aa 5072 else
e1f3808e 5073 gen_helper_macsatu(cpu_env, tcg_const_i32(acc));
acf930aa 5074
e1f3808e
PB		 5075#if 0
5076 /* Disabled because conditional branches clobber temporary vars. */
acf930aa
PB		 5077 if (l1 != -1)
5078 gen_set_label(l1);
e1f3808e 5079#endif
acf930aa
PB		 5080
5081 if (dual) {
5082 /* Dual accumulate variant. */
5083 acc = (ext >> 2) & 3;
5084 /* Restore the overflow flag from the multiplier. */
e1f3808e
PB		 5085 tcg_gen_mov_i32(QREG_MACSR, saved_flags);
5086#if 0
5087 /* Disabled because conditional branches clobber temporary vars. */
acf930aa
PB		 5088 if ((s->env->macsr & MACSR_OMC) != 0) {
5089 /* Skip the accumulate if the value is already saturated. */
5090 l1 = gen_new_label();
a7812ae4 5091 tmp = tcg_temp_new();
351326a6 5092 gen_op_and32(tmp, QREG_MACSR, tcg_const_i32(MACSR_PAV0 << acc));
acf930aa
PB		 5093 gen_op_jmp_nz32(tmp, l1);
5094 }
e1f3808e 5095#endif
acf930aa 5096 if (ext & 2)
e1f3808e 5097 tcg_gen_sub_i64(MACREG(acc), MACREG(acc), s->mactmp);
acf930aa 5098 else
e1f3808e 5099 tcg_gen_add_i64(MACREG(acc), MACREG(acc), s->mactmp);
acf930aa 5100 if (s->env->macsr & MACSR_FI)
e1f3808e 5101 gen_helper_macsatf(cpu_env, tcg_const_i32(acc));
acf930aa 5102 else if (s->env->macsr & MACSR_SU)
e1f3808e 5103 gen_helper_macsats(cpu_env, tcg_const_i32(acc));
acf930aa 5104 else
e1f3808e
PB		 5105 gen_helper_macsatu(cpu_env, tcg_const_i32(acc));
5106#if 0
5107 /* Disabled because conditional branches clobber temporary vars. */
acf930aa
PB		 5108 if (l1 != -1)
5109 gen_set_label(l1);
e1f3808e 5110#endif
acf930aa 5111 }
e1f3808e 5112 gen_helper_mac_set_flags(cpu_env, tcg_const_i32(acc));
acf930aa
PB		 5113
5114 if (insn & 0x30) {
e1f3808e 5115 TCGv rw;
acf930aa 5116 rw = (insn & 0x40) ? AREG(insn, 9) : DREG(insn, 9);
e1f3808e 5117 tcg_gen_mov_i32(rw, loadval);
acf930aa
PB		 5118 /* FIXME: Should address writeback happen with the masked or
5119 unmasked value? */
5120 switch ((insn >> 3) & 7) {
5121 case 3: /* Post-increment. */
e1f3808e 5122 tcg_gen_addi_i32(AREG(insn, 0), addr, 4);
acf930aa
PB		 5123 break;
5124 case 4: /* Pre-decrement. */
e1f3808e 5125 tcg_gen_mov_i32(AREG(insn, 0), addr);
acf930aa
PB		 5126 }
5127 }
5128}
5129
5130DISAS_INSN(from_mac)
5131{
e1f3808e 5132 TCGv rx;
a7812ae4 5133 TCGv_i64 acc;
e1f3808e 5134 int accnum;
acf930aa
PB		 5135
5136 rx = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0);
e1f3808e
PB		 5137 accnum = (insn >> 9) & 3;
5138 acc = MACREG(accnum);
acf930aa 5139 if (s->env->macsr & MACSR_FI) {
a7812ae4 5140 gen_helper_get_macf(rx, cpu_env, acc);
acf930aa 5141 } else if ((s->env->macsr & MACSR_OMC) == 0) {
ecc7b3aa 5142 tcg_gen_extrl_i64_i32(rx, acc);
acf930aa 5143 } else if (s->env->macsr & MACSR_SU) {
e1f3808e 5144 gen_helper_get_macs(rx, acc);
acf930aa 5145 } else {
e1f3808e
PB		 5146 gen_helper_get_macu(rx, acc);
5147 }
5148 if (insn & 0x40) {
5149 tcg_gen_movi_i64(acc, 0);
5150 tcg_gen_andi_i32(QREG_MACSR, QREG_MACSR, ~(MACSR_PAV0 << accnum));
acf930aa 5151 }
acf930aa
PB		 5152}
5153
5154DISAS_INSN(move_mac)
5155{
e1f3808e 5156 /* FIXME: This can be done without a helper. */
acf930aa 5157 int src;
e1f3808e 5158 TCGv dest;
acf930aa 5159 src = insn & 3;
e1f3808e
PB		 5160 dest = tcg_const_i32((insn >> 9) & 3);
5161 gen_helper_mac_move(cpu_env, dest, tcg_const_i32(src));
5162 gen_mac_clear_flags();
5163 gen_helper_mac_set_flags(cpu_env, dest);
acf930aa
PB		 5164}
5165
5166DISAS_INSN(from_macsr)
5167{
e1f3808e 5168 TCGv reg;
acf930aa
PB		 5169
5170 reg = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0);
e1f3808e 5171 tcg_gen_mov_i32(reg, QREG_MACSR);
acf930aa
PB		 5172}
5173
5174DISAS_INSN(from_mask)
5175{
e1f3808e 5176 TCGv reg;
acf930aa 5177 reg = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0);
e1f3808e 5178 tcg_gen_mov_i32(reg, QREG_MAC_MASK);
acf930aa
PB		 5179}
5180
5181DISAS_INSN(from_mext)
5182{
e1f3808e
PB		 5183 TCGv reg;
5184 TCGv acc;
acf930aa 5185 reg = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0);
e1f3808e 5186 acc = tcg_const_i32((insn & 0x400) ? 2 : 0);
acf930aa 5187 if (s->env->macsr & MACSR_FI)
e1f3808e 5188 gen_helper_get_mac_extf(reg, cpu_env, acc);
acf930aa 5189 else
e1f3808e 5190 gen_helper_get_mac_exti(reg, cpu_env, acc);
acf930aa
PB		 5191}
5192
5193DISAS_INSN(macsr_to_ccr)
5194{
620c6cf6
RH		 5195 TCGv tmp = tcg_temp_new();
5196 tcg_gen_andi_i32(tmp, QREG_MACSR, 0xf);
5197 gen_helper_set_sr(cpu_env, tmp);
5198 tcg_temp_free(tmp);
9fdb533f 5199 set_cc_op(s, CC_OP_FLAGS);
acf930aa
PB		 5200}
5201
5202DISAS_INSN(to_mac)
5203{
a7812ae4 5204 TCGv_i64 acc;
e1f3808e
PB		 5205 TCGv val;
5206 int accnum;
5207 accnum = (insn >> 9) & 3;
5208 acc = MACREG(accnum);
d4d79bb1 5209 SRC_EA(env, val, OS_LONG, 0, NULL);
acf930aa 5210 if (s->env->macsr & MACSR_FI) {
e1f3808e
PB		 5211 tcg_gen_ext_i32_i64(acc, val);
5212 tcg_gen_shli_i64(acc, acc, 8);
acf930aa 5213 } else if (s->env->macsr & MACSR_SU) {
e1f3808e 5214 tcg_gen_ext_i32_i64(acc, val);
acf930aa 5215 } else {
e1f3808e 5216 tcg_gen_extu_i32_i64(acc, val);
acf930aa 5217 }
e1f3808e
PB		 5218 tcg_gen_andi_i32(QREG_MACSR, QREG_MACSR, ~(MACSR_PAV0 << accnum));
5219 gen_mac_clear_flags();
5220 gen_helper_mac_set_flags(cpu_env, tcg_const_i32(accnum));
acf930aa
PB		 5221}
5222
5223DISAS_INSN(to_macsr)
5224{
e1f3808e 5225 TCGv val;
d4d79bb1 5226 SRC_EA(env, val, OS_LONG, 0, NULL);
e1f3808e 5227 gen_helper_set_macsr(cpu_env, val);
acf930aa
PB		 5228 gen_lookup_tb(s);
5229}
5230
5231DISAS_INSN(to_mask)
5232{
e1f3808e 5233 TCGv val;
d4d79bb1 5234 SRC_EA(env, val, OS_LONG, 0, NULL);
e1f3808e 5235 tcg_gen_ori_i32(QREG_MAC_MASK, val, 0xffff0000);
acf930aa
PB		 5236}
5237
5238DISAS_INSN(to_mext)
5239{
e1f3808e
PB		 5240 TCGv val;
5241 TCGv acc;
d4d79bb1 5242 SRC_EA(env, val, OS_LONG, 0, NULL);
e1f3808e 5243 acc = tcg_const_i32((insn & 0x400) ? 2 : 0);
acf930aa 5244 if (s->env->macsr & MACSR_FI)
e1f3808e 5245 gen_helper_set_mac_extf(cpu_env, val, acc);
acf930aa 5246 else if (s->env->macsr & MACSR_SU)
e1f3808e 5247 gen_helper_set_mac_exts(cpu_env, val, acc);
acf930aa 5248 else
e1f3808e 5249 gen_helper_set_mac_extu(cpu_env, val, acc);
acf930aa
PB		 5250}
5251
e6e5906b
PB		 5252static disas_proc opcode_table[65536];
5253
5254static void
5255register_opcode (disas_proc proc, uint16_t opcode, uint16_t mask)
5256{
5257 int i;
5258 int from;
5259 int to;
5260
5261 /* Sanity check. All set bits must be included in the mask. */
5fc4adf6
PB		 5262 if (opcode & ~mask) {
5263 fprintf(stderr,
5264 "qemu internal error: bogus opcode definition %04x/%04x\n",
5265 opcode, mask);
e6e5906b 5266 abort();
5fc4adf6 5267 }
e6e5906b
PB		 5268 /* This could probably be cleverer. For now just optimize the case where
5269 the top bits are known. */
5270 /* Find the first zero bit in the mask. */
5271 i = 0x8000;
5272 while ((i & mask) != 0)
5273 i >>= 1;
5274 /* Iterate over all combinations of this and lower bits. */
5275 if (i == 0)
5276 i = 1;
5277 else
5278 i <<= 1;
5279 from = opcode & ~(i - 1);
5280 to = from + i;
0633879f 5281 for (i = from; i < to; i++) {
e6e5906b
PB		 5282 if ((i & mask) == opcode)
5283 opcode_table[i] = proc;
0633879f 5284 }
e6e5906b
PB		 5285}
5286
5287/* Register m68k opcode handlers. Order is important.
5288 Later insn override earlier ones. */
0402f767 5289void register_m68k_insns (CPUM68KState *env)
e6e5906b 5290{
b2085257
JPAG		 5291 /* Build the opcode table only once to avoid
5292 multithreading issues. */
5293 if (opcode_table[0] != NULL) {
5294 return;
5295 }
f076803b
LV		 5296
5297 /* use BASE() for instruction available
5298 * for CF_ISA_A and M68000.
5299 */
5300#define BASE(name, opcode, mask) \
5301 register_opcode(disas_##name, 0x##opcode, 0x##mask)
d315c888 5302#define INSN(name, opcode, mask, feature) do { \
0402f767 5303 if (m68k_feature(env, M68K_FEATURE_##feature)) \
f076803b 5304 BASE(name, opcode, mask); \
d315c888 5305 } while(0)
f076803b 5306 BASE(undef, 0000, 0000);
0402f767 5307 INSN(arith_im, 0080, fff8, CF_ISA_A);
f076803b
LV		 5308 INSN(arith_im, 0000, ff00, M68000);
5309 INSN(undef, 00c0, ffc0, M68000);
d315c888 5310 INSN(bitrev, 00c0, fff8, CF_ISA_APLUSC);
f076803b
LV		 5311 BASE(bitop_reg, 0100, f1c0);
5312 BASE(bitop_reg, 0140, f1c0);
5313 BASE(bitop_reg, 0180, f1c0);
5314 BASE(bitop_reg, 01c0, f1c0);
0402f767 5315 INSN(arith_im, 0280, fff8, CF_ISA_A);
f076803b
LV		 5316 INSN(arith_im, 0200, ff00, M68000);
5317 INSN(undef, 02c0, ffc0, M68000);
d315c888 5318 INSN(byterev, 02c0, fff8, CF_ISA_APLUSC);
0402f767 5319 INSN(arith_im, 0480, fff8, CF_ISA_A);
f076803b
LV		 5320 INSN(arith_im, 0400, ff00, M68000);
5321 INSN(undef, 04c0, ffc0, M68000);
5322 INSN(arith_im, 0600, ff00, M68000);
5323 INSN(undef, 06c0, ffc0, M68000);
d315c888 5324 INSN(ff1, 04c0, fff8, CF_ISA_APLUSC);
0402f767 5325 INSN(arith_im, 0680, fff8, CF_ISA_A);
0402f767 5326 INSN(arith_im, 0c00, ff38, CF_ISA_A);
f076803b
LV		 5327 INSN(arith_im, 0c00, ff00, M68000);
5328 BASE(bitop_im, 0800, ffc0);
5329 BASE(bitop_im, 0840, ffc0);
5330 BASE(bitop_im, 0880, ffc0);
5331 BASE(bitop_im, 08c0, ffc0);
5332 INSN(arith_im, 0a80, fff8, CF_ISA_A);
5333 INSN(arith_im, 0a00, ff00, M68000);
14f94406
LV		 5334 INSN(cas, 0ac0, ffc0, CAS);
5335 INSN(cas, 0cc0, ffc0, CAS);
5336 INSN(cas, 0ec0, ffc0, CAS);
5337 INSN(cas2w, 0cfc, ffff, CAS);
5338 INSN(cas2l, 0efc, ffff, CAS);
f076803b
LV		 5339 BASE(move, 1000, f000);
5340 BASE(move, 2000, f000);
5341 BASE(move, 3000, f000);
d315c888 5342 INSN(strldsr, 40e7, ffff, CF_ISA_APLUSC);
0402f767 5343 INSN(negx, 4080, fff8, CF_ISA_A);
a665a820
RH		 5344 INSN(negx, 4000, ff00, M68000);
5345 INSN(undef, 40c0, ffc0, M68000);
0402f767 5346 INSN(move_from_sr, 40c0, fff8, CF_ISA_A);
f076803b
LV		 5347 INSN(move_from_sr, 40c0, ffc0, M68000);
5348 BASE(lea, 41c0, f1c0);
5349 BASE(clr, 4200, ff00);
5350 BASE(undef, 42c0, ffc0);
0402f767 5351 INSN(move_from_ccr, 42c0, fff8, CF_ISA_A);
7c0eb318 5352 INSN(move_from_ccr, 42c0, ffc0, M68000);
0402f767 5353 INSN(neg, 4480, fff8, CF_ISA_A);
f076803b
LV		 5354 INSN(neg, 4400, ff00, M68000);
5355 INSN(undef, 44c0, ffc0, M68000);
5356 BASE(move_to_ccr, 44c0, ffc0);
0402f767 5357 INSN(not, 4680, fff8, CF_ISA_A);
f076803b
LV		 5358 INSN(not, 4600, ff00, M68000);
5359 INSN(undef, 46c0, ffc0, M68000);
0402f767 5360 INSN(move_to_sr, 46c0, ffc0, CF_ISA_A);
fb5543d8 5361 INSN(nbcd, 4800, ffc0, M68000);
c630e436 5362 INSN(linkl, 4808, fff8, M68000);
f076803b
LV		 5363 BASE(pea, 4840, ffc0);
5364 BASE(swap, 4840, fff8);
71600eda 5365 INSN(bkpt, 4848, fff8, BKPT);
7b542eb9
LV		 5366 INSN(movem, 48d0, fbf8, CF_ISA_A);
5367 INSN(movem, 48e8, fbf8, CF_ISA_A);
5368 INSN(movem, 4880, fb80, M68000);
f076803b
LV		 5369 BASE(ext, 4880, fff8);
5370 BASE(ext, 48c0, fff8);
5371 BASE(ext, 49c0, fff8);
5372 BASE(tst, 4a00, ff00);
0402f767 5373 INSN(tas, 4ac0, ffc0, CF_ISA_B);
f076803b 5374 INSN(tas, 4ac0, ffc0, M68000);
0402f767
PB		 5375 INSN(halt, 4ac8, ffff, CF_ISA_A);
5376 INSN(pulse, 4acc, ffff, CF_ISA_A);
f076803b 5377 BASE(illegal, 4afc, ffff);
0402f767 5378 INSN(mull, 4c00, ffc0, CF_ISA_A);
f076803b 5379 INSN(mull, 4c00, ffc0, LONG_MULDIV);
0402f767 5380 INSN(divl, 4c40, ffc0, CF_ISA_A);
f076803b 5381 INSN(divl, 4c40, ffc0, LONG_MULDIV);
0402f767 5382 INSN(sats, 4c80, fff8, CF_ISA_B);
f076803b
LV		 5383 BASE(trap, 4e40, fff0);
5384 BASE(link, 4e50, fff8);
5385 BASE(unlk, 4e58, fff8);
20dcee94
PB		 5386 INSN(move_to_usp, 4e60, fff8, USP);
5387 INSN(move_from_usp, 4e68, fff8, USP);
f076803b
LV		 5388 BASE(nop, 4e71, ffff);
5389 BASE(stop, 4e72, ffff);
5390 BASE(rte, 4e73, ffff);
18059c9e 5391 INSN(rtd, 4e74, ffff, RTD);
f076803b 5392 BASE(rts, 4e75, ffff);
0402f767 5393 INSN(movec, 4e7b, ffff, CF_ISA_A);
f076803b 5394 BASE(jump, 4e80, ffc0);
8a370c6c 5395 BASE(jump, 4ec0, ffc0);
f076803b 5396 INSN(addsubq, 5000, f080, M68000);
8a370c6c 5397 BASE(addsubq, 5080, f0c0);
d5a3cf33
LV		 5398 INSN(scc, 50c0, f0f8, CF_ISA_A); /* Scc.B Dx */
5399 INSN(scc, 50c0, f0c0, M68000); /* Scc.B <EA> */
beff27ab 5400 INSN(dbcc, 50c8, f0f8, M68000);
0402f767 5401 INSN(tpf, 51f8, fff8, CF_ISA_A);
d315c888
PB		 5402
5403 /* Branch instructions. */
f076803b 5404 BASE(branch, 6000, f000);
d315c888 5405 /* Disable long branch instructions, then add back the ones we want. */
f076803b 5406 BASE(undef, 60ff, f0ff); /* All long branches. */
d315c888
PB		 5407 INSN(branch, 60ff, f0ff, CF_ISA_B);
5408 INSN(undef, 60ff, ffff, CF_ISA_B); /* bra.l */
5409 INSN(branch, 60ff, ffff, BRAL);
f076803b 5410 INSN(branch, 60ff, f0ff, BCCL);
d315c888 5411
f076803b 5412 BASE(moveq, 7000, f100);
0402f767 5413 INSN(mvzs, 7100, f100, CF_ISA_B);
f076803b
LV		 5414 BASE(or, 8000, f000);
5415 BASE(divw, 80c0, f0c0);
fb5543d8
LV		 5416 INSN(sbcd_reg, 8100, f1f8, M68000);
5417 INSN(sbcd_mem, 8108, f1f8, M68000);
f076803b 5418 BASE(addsub, 9000, f000);
a665a820
RH		 5419 INSN(undef, 90c0, f0c0, CF_ISA_A);
5420 INSN(subx_reg, 9180, f1f8, CF_ISA_A);
5421 INSN(subx_reg, 9100, f138, M68000);
5422 INSN(subx_mem, 9108, f138, M68000);
0402f767 5423 INSN(suba, 91c0, f1c0, CF_ISA_A);
415f4b62 5424 INSN(suba, 90c0, f0c0, M68000);
acf930aa 5425
f076803b 5426 BASE(undef_mac, a000, f000);
acf930aa
PB		 5427 INSN(mac, a000, f100, CF_EMAC);
5428 INSN(from_mac, a180, f9b0, CF_EMAC);
5429 INSN(move_mac, a110, f9fc, CF_EMAC);
5430 INSN(from_macsr,a980, f9f0, CF_EMAC);
5431 INSN(from_mask, ad80, fff0, CF_EMAC);
5432 INSN(from_mext, ab80, fbf0, CF_EMAC);
5433 INSN(macsr_to_ccr, a9c0, ffff, CF_EMAC);
5434 INSN(to_mac, a100, f9c0, CF_EMAC);
5435 INSN(to_macsr, a900, ffc0, CF_EMAC);
5436 INSN(to_mext, ab00, fbc0, CF_EMAC);
5437 INSN(to_mask, ad00, ffc0, CF_EMAC);
5438
0402f767
PB		 5439 INSN(mov3q, a140, f1c0, CF_ISA_B);
5440 INSN(cmp, b000, f1c0, CF_ISA_B); /* cmp.b */
5441 INSN(cmp, b040, f1c0, CF_ISA_B); /* cmp.w */
5442 INSN(cmpa, b0c0, f1c0, CF_ISA_B); /* cmpa.w */
5443 INSN(cmp, b080, f1c0, CF_ISA_A);
5444 INSN(cmpa, b1c0, f1c0, CF_ISA_A);
f076803b
LV		 5445 INSN(cmp, b000, f100, M68000);
5446 INSN(eor, b100, f100, M68000);
817af1c7 5447 INSN(cmpm, b108, f138, M68000);
f076803b 5448 INSN(cmpa, b0c0, f0c0, M68000);
0402f767 5449 INSN(eor, b180, f1c0, CF_ISA_A);
f076803b 5450 BASE(and, c000, f000);
29cf437d
LV		 5451 INSN(exg_dd, c140, f1f8, M68000);
5452 INSN(exg_aa, c148, f1f8, M68000);
5453 INSN(exg_da, c188, f1f8, M68000);
f076803b 5454 BASE(mulw, c0c0, f0c0);
fb5543d8
LV		 5455 INSN(abcd_reg, c100, f1f8, M68000);
5456 INSN(abcd_mem, c108, f1f8, M68000);
f076803b 5457 BASE(addsub, d000, f000);
a665a820
RH		 5458 INSN(undef, d0c0, f0c0, CF_ISA_A);
5459 INSN(addx_reg, d180, f1f8, CF_ISA_A);
5460 INSN(addx_reg, d100, f138, M68000);
5461 INSN(addx_mem, d108, f138, M68000);
0402f767 5462 INSN(adda, d1c0, f1c0, CF_ISA_A);
f076803b 5463 INSN(adda, d0c0, f0c0, M68000);
0402f767
PB		 5464 INSN(shift_im, e080, f0f0, CF_ISA_A);
5465 INSN(shift_reg, e0a0, f0f0, CF_ISA_A);
367790cc
RH		 5466 INSN(shift8_im, e000, f0f0, M68000);
5467 INSN(shift16_im, e040, f0f0, M68000);
5468 INSN(shift_im, e080, f0f0, M68000);
5469 INSN(shift8_reg, e020, f0f0, M68000);
5470 INSN(shift16_reg, e060, f0f0, M68000);
5471 INSN(shift_reg, e0a0, f0f0, M68000);
5472 INSN(shift_mem, e0c0, fcc0, M68000);
0194cf31
LV		 5473 INSN(rotate_im, e090, f0f0, M68000);
5474 INSN(rotate8_im, e010, f0f0, M68000);
5475 INSN(rotate16_im, e050, f0f0, M68000);
5476 INSN(rotate_reg, e0b0, f0f0, M68000);
5477 INSN(rotate8_reg, e030, f0f0, M68000);
5478 INSN(rotate16_reg, e070, f0f0, M68000);
5479 INSN(rotate_mem, e4c0, fcc0, M68000);
f2224f2c
RH		 5480 INSN(bfext_mem, e9c0, fdc0, BITFIELD); /* bfextu & bfexts */
5481 INSN(bfext_reg, e9c0, fdf8, BITFIELD);
5482 INSN(bfins_mem, efc0, ffc0, BITFIELD);
ac815f46 5483 INSN(bfins_reg, efc0, fff8, BITFIELD);
f2224f2c 5484 INSN(bfop_mem, eac0, ffc0, BITFIELD); /* bfchg */
ac815f46 5485 INSN(bfop_reg, eac0, fff8, BITFIELD); /* bfchg */
f2224f2c 5486 INSN(bfop_mem, ecc0, ffc0, BITFIELD); /* bfclr */
ac815f46 5487 INSN(bfop_reg, ecc0, fff8, BITFIELD); /* bfclr */
a45f1763
RH		 5488 INSN(bfop_mem, edc0, ffc0, BITFIELD); /* bfffo */
5489 INSN(bfop_reg, edc0, fff8, BITFIELD); /* bfffo */
f2224f2c 5490 INSN(bfop_mem, eec0, ffc0, BITFIELD); /* bfset */
ac815f46 5491 INSN(bfop_reg, eec0, fff8, BITFIELD); /* bfset */
f2224f2c 5492 INSN(bfop_mem, e8c0, ffc0, BITFIELD); /* bftst */
ac815f46 5493 INSN(bfop_reg, e8c0, fff8, BITFIELD); /* bftst */
f83311e4 5494 BASE(undef_fpu, f000, f000);
e6e5906b
PB		 5495 INSN(fpu, f200, ffc0, CF_FPU);
5496 INSN(fbcc, f280, ffc0, CF_FPU);
0633879f 5497 INSN(frestore, f340, ffc0, CF_FPU);
f83311e4
LV		 5498 INSN(fsave, f300, ffc0, CF_FPU);
5499 INSN(fpu, f200, ffc0, FPU);
dd337bf8 5500 INSN(fscc, f240, ffc0, FPU);
f83311e4
LV		 5501 INSN(fbcc, f280, ff80, FPU);
5502 INSN(frestore, f340, ffc0, FPU);
5503 INSN(fsave, f300, ffc0, FPU);
0402f767
PB		 5504 INSN(intouch, f340, ffc0, CF_ISA_A);
5505 INSN(cpushl, f428, ff38, CF_ISA_A);
5506 INSN(wddata, fb00, ff00, CF_ISA_A);
5507 INSN(wdebug, fbc0, ffc0, CF_ISA_A);
e6e5906b
PB		 5508#undef INSN
5509}
5510
5511/* ??? Some of this implementation is not exception safe. We should always
5512 write back the result to memory before setting the condition codes. */
2b3e3cfe 5513static void disas_m68k_insn(CPUM68KState * env, DisasContext *s)
e6e5906b 5514{
8a1e52b6 5515 uint16_t insn = read_im16(env, s);
d4d79bb1 5516 opcode_table[insn](env, s, insn);
8a1e52b6 5517 do_writebacks(s);
e6e5906b
PB		 5518}
5519
e6e5906b 5520/* generate intermediate code for basic block 'tb'. */
9c489ea6 5521void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
e6e5906b 5522{
9c489ea6 5523 CPUM68KState *env = cs->env_ptr;
e6e5906b 5524 DisasContext dc1, *dc = &dc1;
e6e5906b
PB		 5525 target_ulong pc_start;
5526 int pc_offset;
2e70f6ef
PB		 5527 int num_insns;
5528 int max_insns;
e6e5906b
PB		 5529
5530 /* generate intermediate code */
5531 pc_start = tb->pc;
3b46e624 5532
e6e5906b
PB		 5533 dc->tb = tb;
5534
e6dbd3b3 5535 dc->env = env;
e6e5906b
PB		 5536 dc->is_jmp = DISAS_NEXT;
5537 dc->pc = pc_start;
5538 dc->cc_op = CC_OP_DYNAMIC;
620c6cf6 5539 dc->cc_op_synced = 1;
ed2803da 5540 dc->singlestep_enabled = cs->singlestep_enabled;
0633879f 5541 dc->user = (env->sr & SR_S) == 0;
a7812ae4 5542 dc->done_mac = 0;
8a1e52b6 5543 dc->writeback_mask = 0;
2e70f6ef 5544 num_insns = 0;
c5a49c63 5545 max_insns = tb_cflags(tb) & CF_COUNT_MASK;
190ce7fb 5546 if (max_insns == 0) {
2e70f6ef 5547 max_insns = CF_COUNT_MASK;
190ce7fb
RH		 5548 }
5549 if (max_insns > TCG_MAX_INSNS) {
5550 max_insns = TCG_MAX_INSNS;
5551 }
2e70f6ef 5552
cd42d5b2 5553 gen_tb_start(tb);
e6e5906b 5554 do {
e6e5906b 5555 pc_offset = dc->pc - pc_start;
20a8856e 5556 tcg_gen_insn_start(dc->pc, dc->cc_op);
959082fc 5557 num_insns++;
667b8e29 5558
b933066a
RH		 5559 if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) {
5560 gen_exception(dc, dc->pc, EXCP_DEBUG);
5561 dc->is_jmp = DISAS_JUMP;
522a0d4e
RH		 5562 /* The address covered by the breakpoint must be included in
5563 [tb->pc, tb->pc + tb->size) in order to for it to be
5564 properly cleared -- thus we increment the PC here so that
5565 the logic setting tb->size below does the right thing. */
5566 dc->pc += 2;
b933066a
RH		 5567 break;
5568 }
5569
c5a49c63 5570 if (num_insns == max_insns && (tb_cflags(tb) & CF_LAST_IO)) {
2e70f6ef 5571 gen_io_start();
667b8e29
RH		 5572 }
5573
510ff0b7 5574 dc->insn_pc = dc->pc;
e6e5906b 5575 disas_m68k_insn(env, dc);
fe700adb 5576 } while (!dc->is_jmp && !tcg_op_buf_full() &&
ed2803da 5577 !cs->singlestep_enabled &&
1b530a6d 5578 !singlestep &&
2e70f6ef
PB		 5579 (pc_offset) < (TARGET_PAGE_SIZE - 32) &&
5580 num_insns < max_insns);
e6e5906b 5581
c5a49c63 5582 if (tb_cflags(tb) & CF_LAST_IO)
2e70f6ef 5583 gen_io_end();
ed2803da 5584 if (unlikely(cs->singlestep_enabled)) {
e6e5906b
PB		 5585 /* Make sure the pc is updated, and raise a debug exception. */
5586 if (!dc->is_jmp) {
9fdb533f 5587 update_cc_op(dc);
e1f3808e 5588 tcg_gen_movi_i32(QREG_PC, dc->pc);
e6e5906b 5589 }
31871141 5590 gen_helper_raise_exception(cpu_env, tcg_const_i32(EXCP_DEBUG));
e6e5906b
PB		 5591 } else {
5592 switch(dc->is_jmp) {
5593 case DISAS_NEXT:
9fdb533f 5594 update_cc_op(dc);
e6e5906b
PB		 5595 gen_jmp_tb(dc, 0, dc->pc);
5596 break;
5597 default:
5598 case DISAS_JUMP:
5599 case DISAS_UPDATE:
9fdb533f 5600 update_cc_op(dc);
e6e5906b 5601 /* indicate that the hash table must be used to find the next TB */
57fec1fe 5602 tcg_gen_exit_tb(0);
e6e5906b
PB		 5603 break;
5604 case DISAS_TB_JUMP:
5605 /* nothing more to generate */
5606 break;
5607 }
5608 }
806f352d 5609 gen_tb_end(tb, num_insns);
e6e5906b
PB		 5610
5611#ifdef DEBUG_DISAS
4910e6e4
RH		 5612 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)
5613 && qemu_log_in_addr_range(pc_start)) {
1ee73216 5614 qemu_log_lock();
93fcfe39
AL		 5615 qemu_log("----------------\n");
5616 qemu_log("IN: %s\n", lookup_symbol(pc_start));
1d48474d 5617 log_target_disas(cs, pc_start, dc->pc - pc_start);
93fcfe39 5618 qemu_log("\n");
1ee73216 5619 qemu_log_unlock();
e6e5906b
PB		 5620 }
5621#endif
4e5e1215
RH		 5622 tb->size = dc->pc - pc_start;
5623 tb->icount = num_insns;
e6e5906b
PB		 5624}
5625
f83311e4
LV		 5626static double floatx80_to_double(CPUM68KState *env, uint16_t high, uint64_t low)
5627{
5628 floatx80 a = { .high = high, .low = low };
5629 union {
5630 float64 f64;
5631 double d;
5632 } u;
5633
5634 u.f64 = floatx80_to_float64(a, &env->fp_status);
5635 return u.d;
5636}
5637
878096ee
AF		 5638void m68k_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
5639 int flags)
e6e5906b 5640{
878096ee
AF		 5641 M68kCPU *cpu = M68K_CPU(cs);
5642 CPUM68KState *env = &cpu->env;
e6e5906b
PB		 5643 int i;
5644 uint16_t sr;
f83311e4
LV		 5645 for (i = 0; i < 8; i++) {
5646 cpu_fprintf(f, "D%d = %08x A%d = %08x "
5647 "F%d = %04x %016"PRIx64" (%12g)\n",
8e394cca 5648 i, env->dregs[i], i, env->aregs[i],
f83311e4
LV		 5649 i, env->fregs[i].l.upper, env->fregs[i].l.lower,
5650 floatx80_to_double(env, env->fregs[i].l.upper,
5651 env->fregs[i].l.lower));
5652 }
e6e5906b 5653 cpu_fprintf (f, "PC = %08x ", env->pc);
99c51448 5654 sr = env->sr | cpu_m68k_get_ccr(env);
8e394cca
RH		 5655 cpu_fprintf(f, "SR = %04x %c%c%c%c%c ", sr, (sr & CCF_X) ? 'X' : '-',
5656 (sr & CCF_N) ? 'N' : '-', (sr & CCF_Z) ? 'Z' : '-',
5657 (sr & CCF_V) ? 'V' : '-', (sr & CCF_C) ? 'C' : '-');
ba624944
LV		 5658 cpu_fprintf(f, "FPSR = %08x %c%c%c%c ", env->fpsr,
5659 (env->fpsr & FPSR_CC_A) ? 'A' : '-',
5660 (env->fpsr & FPSR_CC_I) ? 'I' : '-',
5661 (env->fpsr & FPSR_CC_Z) ? 'Z' : '-',
5662 (env->fpsr & FPSR_CC_N) ? 'N' : '-');
5663 cpu_fprintf(f, "\n "
5664 "FPCR = %04x ", env->fpcr);
5665 switch (env->fpcr & FPCR_PREC_MASK) {
5666 case FPCR_PREC_X:
5667 cpu_fprintf(f, "X ");
5668 break;
5669 case FPCR_PREC_S:
5670 cpu_fprintf(f, "S ");
5671 break;
5672 case FPCR_PREC_D:
5673 cpu_fprintf(f, "D ");
5674 break;
5675 }
5676 switch (env->fpcr & FPCR_RND_MASK) {
5677 case FPCR_RND_N:
5678 cpu_fprintf(f, "RN ");
5679 break;
5680 case FPCR_RND_Z:
5681 cpu_fprintf(f, "RZ ");
5682 break;
5683 case FPCR_RND_M:
5684 cpu_fprintf(f, "RM ");
5685 break;
5686 case FPCR_RND_P:
5687 cpu_fprintf(f, "RP ");
5688 break;
5689 }
e6e5906b
PB		 5690}
5691
bad729e2
RH		 5692void restore_state_to_opc(CPUM68KState *env, TranslationBlock *tb,
5693 target_ulong *data)
d2856f1a 5694{
20a8856e 5695 int cc_op = data[1];
bad729e2 5696 env->pc = data[0];
20a8856e
LV		 5697 if (cc_op != CC_OP_DYNAMIC) {
5698 env->cc_op = cc_op;
5699 }
d2856f1a 5700}
Empty description
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