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target/m68k: add fmovecr
[qemu.git] / target / m68k / translate.c
CommitLineData
e6e5906b
PB		 1/*
2 * m68k translation
5fafdf24 3 *
0633879f 4 * Copyright (c) 2005-2007 CodeSourcery
e6e5906b
PB		 5 * Written by Paul Brook
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
8167ee88 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
e6e5906b 19 */
e6e5906b 20
d8416665 21#include "qemu/osdep.h"
e6e5906b 22#include "cpu.h"
76cad711 23#include "disas/disas.h"
63c91552 24#include "exec/exec-all.h"
57fec1fe 25#include "tcg-op.h"
1de7afc9 26#include "qemu/log.h"
f08b6170 27#include "exec/cpu_ldst.h"
e1f3808e 28
2ef6175a
RH		 29#include "exec/helper-proto.h"
30#include "exec/helper-gen.h"
e6e5906b 31
a7e30d84 32#include "trace-tcg.h"
508127e2 33#include "exec/log.h"
a7e30d84 34
0633879f
PB		 35//#define DEBUG_DISPATCH 1
36
e1f3808e 37#define DEFO32(name, offset) static TCGv QREG_##name;
a7812ae4 38#define DEFO64(name, offset) static TCGv_i64 QREG_##name;
e1f3808e
PB		 39#include "qregs.def"
40#undef DEFO32
41#undef DEFO64
e1f3808e 42
259186a7 43static TCGv_i32 cpu_halted;
27103424 44static TCGv_i32 cpu_exception_index;
259186a7 45
1bcea73e 46static TCGv_env cpu_env;
e1f3808e 47
f83311e4 48static char cpu_reg_names[2 * 8 * 3 + 5 * 4];
e1f3808e
PB		 49static TCGv cpu_dregs[8];
50static TCGv cpu_aregs[8];
a7812ae4 51static TCGv_i64 cpu_macc[4];
e1f3808e 52
8a1e52b6 53#define REG(insn, pos) (((insn) >> (pos)) & 7)
bcc098b0 54#define DREG(insn, pos) cpu_dregs[REG(insn, pos)]
8a1e52b6 55#define AREG(insn, pos) get_areg(s, REG(insn, pos))
8a1e52b6
RH		 56#define MACREG(acc) cpu_macc[acc]
57#define QREG_SP get_areg(s, 7)
e1f3808e
PB		 58
59static TCGv NULL_QREG;
a7812ae4 60#define IS_NULL_QREG(t) (TCGV_EQUAL(t, NULL_QREG))
e1f3808e
PB		 61/* Used to distinguish stores from bad addressing modes. */
62static TCGv store_dummy;
63
022c62cb 64#include "exec/gen-icount.h"
2e70f6ef 65
e1f3808e
PB		 66void m68k_tcg_init(void)
67{
68 char *p;
69 int i;
70
e1ccc054 71 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
7c255043 72 tcg_ctx.tcg_env = cpu_env;
e1ccc054
RH		 73
74#define DEFO32(name, offset) \
75 QREG_##name = tcg_global_mem_new_i32(cpu_env, \
76 offsetof(CPUM68KState, offset), #name);
77#define DEFO64(name, offset) \
78 QREG_##name = tcg_global_mem_new_i64(cpu_env, \
79 offsetof(CPUM68KState, offset), #name);
e1f3808e
PB		 80#include "qregs.def"
81#undef DEFO32
82#undef DEFO64
e1f3808e 83
e1ccc054 84 cpu_halted = tcg_global_mem_new_i32(cpu_env,
259186a7
AF		 85 -offsetof(M68kCPU, env) +
86 offsetof(CPUState, halted), "HALTED");
e1ccc054 87 cpu_exception_index = tcg_global_mem_new_i32(cpu_env,
27103424
AF		 88 -offsetof(M68kCPU, env) +
89 offsetof(CPUState, exception_index),
90 "EXCEPTION");
259186a7 91
e1f3808e
PB		 92 p = cpu_reg_names;
93 for (i = 0; i < 8; i++) {
94 sprintf(p, "D%d", i);
e1ccc054 95 cpu_dregs[i] = tcg_global_mem_new(cpu_env,
e1f3808e
PB		 96 offsetof(CPUM68KState, dregs[i]), p);
97 p += 3;
98 sprintf(p, "A%d", i);
e1ccc054 99 cpu_aregs[i] = tcg_global_mem_new(cpu_env,
e1f3808e
PB		 100 offsetof(CPUM68KState, aregs[i]), p);
101 p += 3;
e1f3808e
PB		 102 }
103 for (i = 0; i < 4; i++) {
104 sprintf(p, "ACC%d", i);
e1ccc054 105 cpu_macc[i] = tcg_global_mem_new_i64(cpu_env,
e1f3808e
PB		 106 offsetof(CPUM68KState, macc[i]), p);
107 p += 5;
108 }
109
e1ccc054
RH		 110 NULL_QREG = tcg_global_mem_new(cpu_env, -4, "NULL");
111 store_dummy = tcg_global_mem_new(cpu_env, -8, "NULL");
e1f3808e
PB		 112}
113
e6e5906b
PB		 114/* internal defines */
115typedef struct DisasContext {
e6dbd3b3 116 CPUM68KState *env;
510ff0b7 117 target_ulong insn_pc; /* Start of the current instruction. */
e6e5906b
PB		 118 target_ulong pc;
119 int is_jmp;
9fdb533f 120 CCOp cc_op; /* Current CC operation */
620c6cf6 121 int cc_op_synced;
0633879f 122 int user;
e6e5906b
PB		 123 struct TranslationBlock *tb;
124 int singlestep_enabled;
a7812ae4
PB		 125 TCGv_i64 mactmp;
126 int done_mac;
8a1e52b6
RH		 127 int writeback_mask;
128 TCGv writeback[8];
e6e5906b
PB		 129} DisasContext;
130
8a1e52b6
RH		 131static TCGv get_areg(DisasContext *s, unsigned regno)
132{
133 if (s->writeback_mask & (1 << regno)) {
134 return s->writeback[regno];
135 } else {
136 return cpu_aregs[regno];
137 }
138}
139
140static void delay_set_areg(DisasContext *s, unsigned regno,
141 TCGv val, bool give_temp)
142{
143 if (s->writeback_mask & (1 << regno)) {
144 if (give_temp) {
145 tcg_temp_free(s->writeback[regno]);
146 s->writeback[regno] = val;
147 } else {
148 tcg_gen_mov_i32(s->writeback[regno], val);
149 }
150 } else {
151 s->writeback_mask |= 1 << regno;
152 if (give_temp) {
153 s->writeback[regno] = val;
154 } else {
155 TCGv tmp = tcg_temp_new();
156 s->writeback[regno] = tmp;
157 tcg_gen_mov_i32(tmp, val);
158 }
159 }
160}
161
162static void do_writebacks(DisasContext *s)
163{
164 unsigned mask = s->writeback_mask;
165 if (mask) {
166 s->writeback_mask = 0;
167 do {
168 unsigned regno = ctz32(mask);
169 tcg_gen_mov_i32(cpu_aregs[regno], s->writeback[regno]);
170 tcg_temp_free(s->writeback[regno]);
171 mask &= mask - 1;
172 } while (mask);
173 }
174}
175
e6e5906b
PB		 176#define DISAS_JUMP_NEXT 4
177
0633879f
PB		 178#if defined(CONFIG_USER_ONLY)
179#define IS_USER(s) 1
180#else
181#define IS_USER(s) s->user
182#endif
183
e6e5906b
PB		 184/* XXX: move that elsewhere */
185/* ??? Fix exceptions. */
186static void *gen_throws_exception;
187#define gen_last_qop NULL
188
d4d79bb1 189typedef void (*disas_proc)(CPUM68KState *env, DisasContext *s, uint16_t insn);
e6e5906b 190
0633879f 191#ifdef DEBUG_DISPATCH
d4d79bb1
BS		 192#define DISAS_INSN(name) \
193 static void real_disas_##name(CPUM68KState *env, DisasContext *s, \
194 uint16_t insn); \
195 static void disas_##name(CPUM68KState *env, DisasContext *s, \
196 uint16_t insn) \
197 { \
198 qemu_log("Dispatch " #name "\n"); \
a1ff1930 199 real_disas_##name(env, s, insn); \
d4d79bb1
BS		 200 } \
201 static void real_disas_##name(CPUM68KState *env, DisasContext *s, \
202 uint16_t insn)
0633879f 203#else
d4d79bb1
BS		 204#define DISAS_INSN(name) \
205 static void disas_##name(CPUM68KState *env, DisasContext *s, \
206 uint16_t insn)
0633879f 207#endif
e6e5906b 208
9fdb533f 209static const uint8_t cc_op_live[CC_OP_NB] = {
620c6cf6 210 [CC_OP_FLAGS] = CCF_C | CCF_V | CCF_Z | CCF_N | CCF_X,
db3d7945
LV		 211 [CC_OP_ADDB ... CC_OP_ADDL] = CCF_X | CCF_N | CCF_V,
212 [CC_OP_SUBB ... CC_OP_SUBL] = CCF_X | CCF_N | CCF_V,
213 [CC_OP_CMPB ... CC_OP_CMPL] = CCF_X | CCF_N | CCF_V,
620c6cf6 214 [CC_OP_LOGIC] = CCF_X | CCF_N
9fdb533f
LV		 215};
216
217static void set_cc_op(DisasContext *s, CCOp op)
218{
620c6cf6 219 CCOp old_op = s->cc_op;
9fdb533f
LV		 220 int dead;
221
620c6cf6 222 if (old_op == op) {
9fdb533f
LV		 223 return;
224 }
620c6cf6
RH		 225 s->cc_op = op;
226 s->cc_op_synced = 0;
9fdb533f 227
620c6cf6
RH		 228 /* Discard CC computation that will no longer be used.
229 Note that X and N are never dead. */
230 dead = cc_op_live[old_op] & ~cc_op_live[op];
231 if (dead & CCF_C) {
232 tcg_gen_discard_i32(QREG_CC_C);
9fdb533f 233 }
620c6cf6
RH		 234 if (dead & CCF_Z) {
235 tcg_gen_discard_i32(QREG_CC_Z);
9fdb533f 236 }
620c6cf6
RH		 237 if (dead & CCF_V) {
238 tcg_gen_discard_i32(QREG_CC_V);
9fdb533f 239 }
9fdb533f
LV		 240}
241
242/* Update the CPU env CC_OP state. */
620c6cf6 243static void update_cc_op(DisasContext *s)
9fdb533f 244{
620c6cf6
RH		 245 if (!s->cc_op_synced) {
246 s->cc_op_synced = 1;
9fdb533f
LV		 247 tcg_gen_movi_i32(QREG_CC_OP, s->cc_op);
248 }
249}
250
f83311e4
LV		 251/* Generate a jump to an immediate address. */
252static void gen_jmp_im(DisasContext *s, uint32_t dest)
253{
254 update_cc_op(s);
255 tcg_gen_movi_i32(QREG_PC, dest);
256 s->is_jmp = DISAS_JUMP;
257}
258
259/* Generate a jump to the address in qreg DEST. */
260static void gen_jmp(DisasContext *s, TCGv dest)
261{
262 update_cc_op(s);
263 tcg_gen_mov_i32(QREG_PC, dest);
264 s->is_jmp = DISAS_JUMP;
265}
266
267static void gen_raise_exception(int nr)
268{
269 TCGv_i32 tmp = tcg_const_i32(nr);
270
271 gen_helper_raise_exception(cpu_env, tmp);
272 tcg_temp_free_i32(tmp);
273}
274
275static void gen_exception(DisasContext *s, uint32_t where, int nr)
276{
277 update_cc_op(s);
278 gen_jmp_im(s, where);
279 gen_raise_exception(nr);
280}
281
282static inline void gen_addr_fault(DisasContext *s)
283{
284 gen_exception(s, s->insn_pc, EXCP_ADDRESS);
285}
286
e6e5906b
PB		 287/* Generate a load from the specified address. Narrow values are
288 sign extended to full register width. */
e1f3808e 289static inline TCGv gen_load(DisasContext * s, int opsize, TCGv addr, int sign)
e6e5906b 290{
e1f3808e
PB		 291 TCGv tmp;
292 int index = IS_USER(s);
a7812ae4 293 tmp = tcg_temp_new_i32();
e6e5906b
PB		 294 switch(opsize) {
295 case OS_BYTE:
e6e5906b 296 if (sign)
e1f3808e 297 tcg_gen_qemu_ld8s(tmp, addr, index);
e6e5906b 298 else
e1f3808e 299 tcg_gen_qemu_ld8u(tmp, addr, index);
e6e5906b
PB		 300 break;
301 case OS_WORD:
e6e5906b 302 if (sign)
e1f3808e 303 tcg_gen_qemu_ld16s(tmp, addr, index);
e6e5906b 304 else
e1f3808e 305 tcg_gen_qemu_ld16u(tmp, addr, index);
e6e5906b
PB		 306 break;
307 case OS_LONG:
a7812ae4 308 tcg_gen_qemu_ld32u(tmp, addr, index);
e6e5906b
PB		 309 break;
310 default:
7372c2b9 311 g_assert_not_reached();
e6e5906b
PB		 312 }
313 gen_throws_exception = gen_last_qop;
314 return tmp;
315}
316
317/* Generate a store. */
e1f3808e 318static inline void gen_store(DisasContext *s, int opsize, TCGv addr, TCGv val)
e6e5906b 319{
e1f3808e 320 int index = IS_USER(s);
e6e5906b
PB		 321 switch(opsize) {
322 case OS_BYTE:
e1f3808e 323 tcg_gen_qemu_st8(val, addr, index);
e6e5906b
PB		 324 break;
325 case OS_WORD:
e1f3808e 326 tcg_gen_qemu_st16(val, addr, index);
e6e5906b
PB		 327 break;
328 case OS_LONG:
a7812ae4 329 tcg_gen_qemu_st32(val, addr, index);
e6e5906b
PB		 330 break;
331 default:
7372c2b9 332 g_assert_not_reached();
e6e5906b
PB		 333 }
334 gen_throws_exception = gen_last_qop;
335}
336
e1f3808e
PB		 337typedef enum {
338 EA_STORE,
339 EA_LOADU,
340 EA_LOADS
341} ea_what;
342
e6e5906b
PB		 343/* Generate an unsigned load if VAL is 0 a signed load if val is -1,
344 otherwise generate a store. */
e1f3808e
PB		 345static TCGv gen_ldst(DisasContext *s, int opsize, TCGv addr, TCGv val,
346 ea_what what)
e6e5906b 347{
e1f3808e 348 if (what == EA_STORE) {
0633879f 349 gen_store(s, opsize, addr, val);
e1f3808e 350 return store_dummy;
e6e5906b 351 } else {
e1f3808e 352 return gen_load(s, opsize, addr, what == EA_LOADS);
e6e5906b
PB		 353 }
354}
355
28b68cd7
LV		 356/* Read a 16-bit immediate constant */
357static inline uint16_t read_im16(CPUM68KState *env, DisasContext *s)
358{
359 uint16_t im;
360 im = cpu_lduw_code(env, s->pc);
361 s->pc += 2;
362 return im;
363}
364
365/* Read an 8-bit immediate constant */
366static inline uint8_t read_im8(CPUM68KState *env, DisasContext *s)
367{
368 return read_im16(env, s);
369}
370
e6dbd3b3 371/* Read a 32-bit immediate constant. */
d4d79bb1 372static inline uint32_t read_im32(CPUM68KState *env, DisasContext *s)
e6dbd3b3
PB		 373{
374 uint32_t im;
28b68cd7
LV		 375 im = read_im16(env, s) << 16;
376 im |= 0xffff & read_im16(env, s);
e6dbd3b3
PB		 377 return im;
378}
379
f83311e4
LV		 380/* Read a 64-bit immediate constant. */
381static inline uint64_t read_im64(CPUM68KState *env, DisasContext *s)
382{
383 uint64_t im;
384 im = (uint64_t)read_im32(env, s) << 32;
385 im |= (uint64_t)read_im32(env, s);
386 return im;
387}
388
e6dbd3b3 389/* Calculate and address index. */
8a1e52b6 390static TCGv gen_addr_index(DisasContext *s, uint16_t ext, TCGv tmp)
e6dbd3b3 391{
e1f3808e 392 TCGv add;
e6dbd3b3
PB		 393 int scale;
394
395 add = (ext & 0x8000) ? AREG(ext, 12) : DREG(ext, 12);
396 if ((ext & 0x800) == 0) {
e1f3808e 397 tcg_gen_ext16s_i32(tmp, add);
e6dbd3b3
PB		 398 add = tmp;
399 }
400 scale = (ext >> 9) & 3;
401 if (scale != 0) {
e1f3808e 402 tcg_gen_shli_i32(tmp, add, scale);
e6dbd3b3
PB		 403 add = tmp;
404 }
405 return add;
406}
407
e1f3808e
PB		 408/* Handle a base + index + displacement effective addresss.
409 A NULL_QREG base means pc-relative. */
a4356126 410static TCGv gen_lea_indexed(CPUM68KState *env, DisasContext *s, TCGv base)
e6e5906b 411{
e6e5906b
PB		 412 uint32_t offset;
413 uint16_t ext;
e1f3808e
PB		 414 TCGv add;
415 TCGv tmp;
e6dbd3b3 416 uint32_t bd, od;
e6e5906b
PB		 417
418 offset = s->pc;
28b68cd7 419 ext = read_im16(env, s);
e6dbd3b3
PB		 420
421 if ((ext & 0x800) == 0 && !m68k_feature(s->env, M68K_FEATURE_WORD_INDEX))
e1f3808e 422 return NULL_QREG;
e6dbd3b3 423
d8633620
LV		 424 if (m68k_feature(s->env, M68K_FEATURE_M68000) &&
425 !m68k_feature(s->env, M68K_FEATURE_SCALED_INDEX)) {
426 ext &= ~(3 << 9);
427 }
428
e6dbd3b3
PB		 429 if (ext & 0x100) {
430 /* full extension word format */
431 if (!m68k_feature(s->env, M68K_FEATURE_EXT_FULL))
e1f3808e 432 return NULL_QREG;
e6dbd3b3
PB		 433
434 if ((ext & 0x30) > 0x10) {
435 /* base displacement */
436 if ((ext & 0x30) == 0x20) {
28b68cd7 437 bd = (int16_t)read_im16(env, s);
e6dbd3b3 438 } else {
d4d79bb1 439 bd = read_im32(env, s);
e6dbd3b3
PB		 440 }
441 } else {
442 bd = 0;
443 }
a7812ae4 444 tmp = tcg_temp_new();
e6dbd3b3
PB		 445 if ((ext & 0x44) == 0) {
446 /* pre-index */
8a1e52b6 447 add = gen_addr_index(s, ext, tmp);
e6dbd3b3 448 } else {
e1f3808e 449 add = NULL_QREG;
e6dbd3b3
PB		 450 }
451 if ((ext & 0x80) == 0) {
452 /* base not suppressed */
e1f3808e 453 if (IS_NULL_QREG(base)) {
351326a6 454 base = tcg_const_i32(offset + bd);
e6dbd3b3
PB		 455 bd = 0;
456 }
e1f3808e
PB		 457 if (!IS_NULL_QREG(add)) {
458 tcg_gen_add_i32(tmp, add, base);
e6dbd3b3
PB		 459 add = tmp;
460 } else {
461 add = base;
462 }
463 }
e1f3808e 464 if (!IS_NULL_QREG(add)) {
e6dbd3b3 465 if (bd != 0) {
e1f3808e 466 tcg_gen_addi_i32(tmp, add, bd);
e6dbd3b3
PB		 467 add = tmp;
468 }
469 } else {
351326a6 470 add = tcg_const_i32(bd);
e6dbd3b3
PB		 471 }
472 if ((ext & 3) != 0) {
473 /* memory indirect */
474 base = gen_load(s, OS_LONG, add, 0);
475 if ((ext & 0x44) == 4) {
8a1e52b6 476 add = gen_addr_index(s, ext, tmp);
e1f3808e 477 tcg_gen_add_i32(tmp, add, base);
e6dbd3b3
PB		 478 add = tmp;
479 } else {
480 add = base;
481 }
482 if ((ext & 3) > 1) {
483 /* outer displacement */
484 if ((ext & 3) == 2) {
28b68cd7 485 od = (int16_t)read_im16(env, s);
e6dbd3b3 486 } else {
d4d79bb1 487 od = read_im32(env, s);
e6dbd3b3
PB		 488 }
489 } else {
490 od = 0;
491 }
492 if (od != 0) {
e1f3808e 493 tcg_gen_addi_i32(tmp, add, od);
e6dbd3b3
PB		 494 add = tmp;
495 }
496 }
e6e5906b 497 } else {
e6dbd3b3 498 /* brief extension word format */
a7812ae4 499 tmp = tcg_temp_new();
8a1e52b6 500 add = gen_addr_index(s, ext, tmp);
e1f3808e
PB		 501 if (!IS_NULL_QREG(base)) {
502 tcg_gen_add_i32(tmp, add, base);
e6dbd3b3 503 if ((int8_t)ext)
e1f3808e 504 tcg_gen_addi_i32(tmp, tmp, (int8_t)ext);
e6dbd3b3 505 } else {
e1f3808e 506 tcg_gen_addi_i32(tmp, add, offset + (int8_t)ext);
e6dbd3b3
PB		 507 }
508 add = tmp;
e6e5906b 509 }
e6dbd3b3 510 return add;
e6e5906b
PB		 511}
512
db3d7945
LV		 513/* Sign or zero extend a value. */
514
515static inline void gen_ext(TCGv res, TCGv val, int opsize, int sign)
516{
517 switch (opsize) {
518 case OS_BYTE:
519 if (sign) {
520 tcg_gen_ext8s_i32(res, val);
521 } else {
522 tcg_gen_ext8u_i32(res, val);
523 }
524 break;
525 case OS_WORD:
526 if (sign) {
527 tcg_gen_ext16s_i32(res, val);
528 } else {
529 tcg_gen_ext16u_i32(res, val);
530 }
531 break;
532 case OS_LONG:
533 tcg_gen_mov_i32(res, val);
534 break;
535 default:
536 g_assert_not_reached();
537 }
538}
539
e6e5906b 540/* Evaluate all the CC flags. */
9fdb533f 541
620c6cf6 542static void gen_flush_flags(DisasContext *s)
e6e5906b 543{
36f0399d 544 TCGv t0, t1;
620c6cf6
RH		 545
546 switch (s->cc_op) {
547 case CC_OP_FLAGS:
e6e5906b 548 return;
36f0399d 549
db3d7945
LV		 550 case CC_OP_ADDB:
551 case CC_OP_ADDW:
552 case CC_OP_ADDL:
36f0399d
RH		 553 tcg_gen_mov_i32(QREG_CC_C, QREG_CC_X);
554 tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N);
555 /* Compute signed overflow for addition. */
556 t0 = tcg_temp_new();
557 t1 = tcg_temp_new();
558 tcg_gen_sub_i32(t0, QREG_CC_N, QREG_CC_V);
db3d7945 559 gen_ext(t0, t0, s->cc_op - CC_OP_ADDB, 1);
36f0399d
RH		 560 tcg_gen_xor_i32(t1, QREG_CC_N, QREG_CC_V);
561 tcg_gen_xor_i32(QREG_CC_V, QREG_CC_V, t0);
562 tcg_temp_free(t0);
563 tcg_gen_andc_i32(QREG_CC_V, t1, QREG_CC_V);
564 tcg_temp_free(t1);
565 break;
566
db3d7945
LV		 567 case CC_OP_SUBB:
568 case CC_OP_SUBW:
569 case CC_OP_SUBL:
36f0399d
RH		 570 tcg_gen_mov_i32(QREG_CC_C, QREG_CC_X);
571 tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N);
572 /* Compute signed overflow for subtraction. */
573 t0 = tcg_temp_new();
574 t1 = tcg_temp_new();
575 tcg_gen_add_i32(t0, QREG_CC_N, QREG_CC_V);
db3d7945 576 gen_ext(t0, t0, s->cc_op - CC_OP_SUBB, 1);
043b936e 577 tcg_gen_xor_i32(t1, QREG_CC_N, t0);
36f0399d
RH		 578 tcg_gen_xor_i32(QREG_CC_V, QREG_CC_V, t0);
579 tcg_temp_free(t0);
580 tcg_gen_and_i32(QREG_CC_V, QREG_CC_V, t1);
581 tcg_temp_free(t1);
582 break;
583
db3d7945
LV		 584 case CC_OP_CMPB:
585 case CC_OP_CMPW:
586 case CC_OP_CMPL:
36f0399d
RH		 587 tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_C, QREG_CC_N, QREG_CC_V);
588 tcg_gen_sub_i32(QREG_CC_Z, QREG_CC_N, QREG_CC_V);
db3d7945 589 gen_ext(QREG_CC_Z, QREG_CC_Z, s->cc_op - CC_OP_CMPB, 1);
36f0399d
RH		 590 /* Compute signed overflow for subtraction. */
591 t0 = tcg_temp_new();
592 tcg_gen_xor_i32(t0, QREG_CC_Z, QREG_CC_N);
593 tcg_gen_xor_i32(QREG_CC_V, QREG_CC_V, QREG_CC_N);
594 tcg_gen_and_i32(QREG_CC_V, QREG_CC_V, t0);
595 tcg_temp_free(t0);
596 tcg_gen_mov_i32(QREG_CC_N, QREG_CC_Z);
597 break;
598
599 case CC_OP_LOGIC:
600 tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N);
601 tcg_gen_movi_i32(QREG_CC_C, 0);
602 tcg_gen_movi_i32(QREG_CC_V, 0);
603 break;
604
620c6cf6
RH		 605 case CC_OP_DYNAMIC:
606 gen_helper_flush_flags(cpu_env, QREG_CC_OP);
695576db 607 s->cc_op_synced = 1;
620c6cf6 608 break;
36f0399d 609
620c6cf6 610 default:
36f0399d
RH		 611 t0 = tcg_const_i32(s->cc_op);
612 gen_helper_flush_flags(cpu_env, t0);
613 tcg_temp_free(t0);
695576db 614 s->cc_op_synced = 1;
620c6cf6
RH		 615 break;
616 }
617
618 /* Note that flush_flags also assigned to env->cc_op. */
619 s->cc_op = CC_OP_FLAGS;
620c6cf6
RH		 620}
621
db3d7945 622static inline TCGv gen_extend(TCGv val, int opsize, int sign)
620c6cf6
RH		 623{
624 TCGv tmp;
625
626 if (opsize == OS_LONG) {
627 tmp = val;
628 } else {
629 tmp = tcg_temp_new();
630 gen_ext(tmp, val, opsize, sign);
631 }
632
633 return tmp;
634}
5dbb6784
LV		 635
636static void gen_logic_cc(DisasContext *s, TCGv val, int opsize)
e1f3808e 637{
620c6cf6
RH		 638 gen_ext(QREG_CC_N, val, opsize, 1);
639 set_cc_op(s, CC_OP_LOGIC);
e1f3808e
PB		 640}
641
ff99b952
LV		 642static void gen_update_cc_cmp(DisasContext *s, TCGv dest, TCGv src, int opsize)
643{
644 tcg_gen_mov_i32(QREG_CC_N, dest);
645 tcg_gen_mov_i32(QREG_CC_V, src);
646 set_cc_op(s, CC_OP_CMPB + opsize);
647}
648
db3d7945 649static void gen_update_cc_add(TCGv dest, TCGv src, int opsize)
e1f3808e 650{
db3d7945 651 gen_ext(QREG_CC_N, dest, opsize, 1);
620c6cf6 652 tcg_gen_mov_i32(QREG_CC_V, src);
e1f3808e
PB		 653}
654
e6e5906b
PB		 655static inline int opsize_bytes(int opsize)
656{
657 switch (opsize) {
658 case OS_BYTE: return 1;
659 case OS_WORD: return 2;
660 case OS_LONG: return 4;
661 case OS_SINGLE: return 4;
662 case OS_DOUBLE: return 8;
7ef25cdd
LV		 663 case OS_EXTENDED: return 12;
664 case OS_PACKED: return 12;
665 default:
666 g_assert_not_reached();
667 }
668}
669
670static inline int insn_opsize(int insn)
671{
672 switch ((insn >> 6) & 3) {
673 case 0: return OS_BYTE;
674 case 1: return OS_WORD;
675 case 2: return OS_LONG;
e6e5906b 676 default:
7372c2b9 677 g_assert_not_reached();
e6e5906b
PB		 678 }
679}
680
69e69822
LV		 681static inline int ext_opsize(int ext, int pos)
682{
683 switch ((ext >> pos) & 7) {
684 case 0: return OS_LONG;
685 case 1: return OS_SINGLE;
686 case 2: return OS_EXTENDED;
687 case 3: return OS_PACKED;
688 case 4: return OS_WORD;
689 case 5: return OS_DOUBLE;
690 case 6: return OS_BYTE;
691 default:
692 g_assert_not_reached();
693 }
694}
695
e6e5906b
PB		 696/* Assign value to a register. If the width is less than the register width
697 only the low part of the register is set. */
e1f3808e 698static void gen_partset_reg(int opsize, TCGv reg, TCGv val)
e6e5906b 699{
e1f3808e 700 TCGv tmp;
e6e5906b
PB		 701 switch (opsize) {
702 case OS_BYTE:
e1f3808e 703 tcg_gen_andi_i32(reg, reg, 0xffffff00);
a7812ae4 704 tmp = tcg_temp_new();
e1f3808e
PB		 705 tcg_gen_ext8u_i32(tmp, val);
706 tcg_gen_or_i32(reg, reg, tmp);
2b5e2170 707 tcg_temp_free(tmp);
e6e5906b
PB		 708 break;
709 case OS_WORD:
e1f3808e 710 tcg_gen_andi_i32(reg, reg, 0xffff0000);
a7812ae4 711 tmp = tcg_temp_new();
e1f3808e
PB		 712 tcg_gen_ext16u_i32(tmp, val);
713 tcg_gen_or_i32(reg, reg, tmp);
2b5e2170 714 tcg_temp_free(tmp);
e6e5906b
PB		 715 break;
716 case OS_LONG:
e6e5906b 717 case OS_SINGLE:
a7812ae4 718 tcg_gen_mov_i32(reg, val);
e6e5906b
PB		 719 break;
720 default:
7372c2b9 721 g_assert_not_reached();
e6e5906b
PB		 722 }
723}
724
e6e5906b 725/* Generate code for an "effective address". Does not adjust the base
1addc7c5 726 register for autoincrement addressing modes. */
f84aab26
RH		 727static TCGv gen_lea_mode(CPUM68KState *env, DisasContext *s,
728 int mode, int reg0, int opsize)
e6e5906b 729{
e1f3808e
PB		 730 TCGv reg;
731 TCGv tmp;
e6e5906b
PB		 732 uint16_t ext;
733 uint32_t offset;
734
f84aab26 735 switch (mode) {
e6e5906b
PB		 736 case 0: /* Data register direct. */
737 case 1: /* Address register direct. */
e1f3808e 738 return NULL_QREG;
e6e5906b 739 case 3: /* Indirect postincrement. */
f2224f2c
RH		 740 if (opsize == OS_UNSIZED) {
741 return NULL_QREG;
742 }
743 /* fallthru */
744 case 2: /* Indirect register */
f84aab26 745 return get_areg(s, reg0);
e6e5906b 746 case 4: /* Indirect predecrememnt. */
f2224f2c
RH		 747 if (opsize == OS_UNSIZED) {
748 return NULL_QREG;
749 }
f84aab26 750 reg = get_areg(s, reg0);
a7812ae4 751 tmp = tcg_temp_new();
727d937b
LV		 752 if (reg0 == 7 && opsize == OS_BYTE &&
753 m68k_feature(s->env, M68K_FEATURE_M68000)) {
754 tcg_gen_subi_i32(tmp, reg, 2);
755 } else {
756 tcg_gen_subi_i32(tmp, reg, opsize_bytes(opsize));
757 }
e6e5906b
PB		 758 return tmp;
759 case 5: /* Indirect displacement. */
f84aab26 760 reg = get_areg(s, reg0);
a7812ae4 761 tmp = tcg_temp_new();
28b68cd7 762 ext = read_im16(env, s);
e1f3808e 763 tcg_gen_addi_i32(tmp, reg, (int16_t)ext);
e6e5906b
PB		 764 return tmp;
765 case 6: /* Indirect index + displacement. */
f84aab26 766 reg = get_areg(s, reg0);
a4356126 767 return gen_lea_indexed(env, s, reg);
e6e5906b 768 case 7: /* Other */
f84aab26 769 switch (reg0) {
e6e5906b 770 case 0: /* Absolute short. */
28b68cd7 771 offset = (int16_t)read_im16(env, s);
351326a6 772 return tcg_const_i32(offset);
e6e5906b 773 case 1: /* Absolute long. */
d4d79bb1 774 offset = read_im32(env, s);
351326a6 775 return tcg_const_i32(offset);
e6e5906b 776 case 2: /* pc displacement */
e6e5906b 777 offset = s->pc;
28b68cd7 778 offset += (int16_t)read_im16(env, s);
351326a6 779 return tcg_const_i32(offset);
e6e5906b 780 case 3: /* pc index+displacement. */
a4356126 781 return gen_lea_indexed(env, s, NULL_QREG);
e6e5906b
PB		 782 case 4: /* Immediate. */
783 default:
e1f3808e 784 return NULL_QREG;
e6e5906b
PB		 785 }
786 }
787 /* Should never happen. */
e1f3808e 788 return NULL_QREG;
e6e5906b
PB		 789}
790
f84aab26
RH		 791static TCGv gen_lea(CPUM68KState *env, DisasContext *s, uint16_t insn,
792 int opsize)
e6e5906b 793{
f84aab26
RH		 794 int mode = extract32(insn, 3, 3);
795 int reg0 = REG(insn, 0);
796 return gen_lea_mode(env, s, mode, reg0, opsize);
e6e5906b
PB		 797}
798
f84aab26 799/* Generate code to load/store a value from/into an EA. If WHAT > 0 this is
e6e5906b
PB		 800 a write otherwise it is a read (0 == sign extend, -1 == zero extend).
801 ADDRP is non-null for readwrite operands. */
f84aab26
RH		 802static TCGv gen_ea_mode(CPUM68KState *env, DisasContext *s, int mode, int reg0,
803 int opsize, TCGv val, TCGv *addrp, ea_what what)
e6e5906b 804{
f84aab26
RH		 805 TCGv reg, tmp, result;
806 int32_t offset;
e6e5906b 807
f84aab26 808 switch (mode) {
e6e5906b 809 case 0: /* Data register direct. */
f84aab26 810 reg = cpu_dregs[reg0];
e1f3808e 811 if (what == EA_STORE) {
e6e5906b 812 gen_partset_reg(opsize, reg, val);
e1f3808e 813 return store_dummy;
e6e5906b 814 } else {
e1f3808e 815 return gen_extend(reg, opsize, what == EA_LOADS);
e6e5906b
PB		 816 }
817 case 1: /* Address register direct. */
f84aab26 818 reg = get_areg(s, reg0);
e1f3808e
PB		 819 if (what == EA_STORE) {
820 tcg_gen_mov_i32(reg, val);
821 return store_dummy;
e6e5906b 822 } else {
e1f3808e 823 return gen_extend(reg, opsize, what == EA_LOADS);
e6e5906b
PB		 824 }
825 case 2: /* Indirect register */
f84aab26 826 reg = get_areg(s, reg0);
e1f3808e 827 return gen_ldst(s, opsize, reg, val, what);
e6e5906b 828 case 3: /* Indirect postincrement. */
f84aab26 829 reg = get_areg(s, reg0);
e1f3808e 830 result = gen_ldst(s, opsize, reg, val, what);
8a1e52b6
RH		 831 if (what == EA_STORE || !addrp) {
832 TCGv tmp = tcg_temp_new();
727d937b
LV		 833 if (reg0 == 7 && opsize == OS_BYTE &&
834 m68k_feature(s->env, M68K_FEATURE_M68000)) {
835 tcg_gen_addi_i32(tmp, reg, 2);
836 } else {
837 tcg_gen_addi_i32(tmp, reg, opsize_bytes(opsize));
838 }
f84aab26 839 delay_set_areg(s, reg0, tmp, true);
8a1e52b6 840 }
e6e5906b
PB		 841 return result;
842 case 4: /* Indirect predecrememnt. */
f84aab26
RH		 843 if (addrp && what == EA_STORE) {
844 tmp = *addrp;
845 } else {
846 tmp = gen_lea_mode(env, s, mode, reg0, opsize);
847 if (IS_NULL_QREG(tmp)) {
848 return tmp;
e6e5906b 849 }
f84aab26
RH		 850 if (addrp) {
851 *addrp = tmp;
e6e5906b
PB		 852 }
853 }
f84aab26
RH		 854 result = gen_ldst(s, opsize, tmp, val, what);
855 if (what == EA_STORE || !addrp) {
856 delay_set_areg(s, reg0, tmp, false);
857 }
e6e5906b
PB		 858 return result;
859 case 5: /* Indirect displacement. */
860 case 6: /* Indirect index + displacement. */
f84aab26
RH		 861 do_indirect:
862 if (addrp && what == EA_STORE) {
863 tmp = *addrp;
864 } else {
865 tmp = gen_lea_mode(env, s, mode, reg0, opsize);
866 if (IS_NULL_QREG(tmp)) {
867 return tmp;
868 }
869 if (addrp) {
870 *addrp = tmp;
871 }
872 }
873 return gen_ldst(s, opsize, tmp, val, what);
e6e5906b 874 case 7: /* Other */
f84aab26 875 switch (reg0) {
e6e5906b
PB		 876 case 0: /* Absolute short. */
877 case 1: /* Absolute long. */
878 case 2: /* pc displacement */
879 case 3: /* pc index+displacement. */
f84aab26 880 goto do_indirect;
e6e5906b
PB		 881 case 4: /* Immediate. */
882 /* Sign extend values for consistency. */
883 switch (opsize) {
884 case OS_BYTE:
31871141 885 if (what == EA_LOADS) {
28b68cd7 886 offset = (int8_t)read_im8(env, s);
31871141 887 } else {
28b68cd7 888 offset = read_im8(env, s);
31871141 889 }
e6e5906b
PB		 890 break;
891 case OS_WORD:
31871141 892 if (what == EA_LOADS) {
28b68cd7 893 offset = (int16_t)read_im16(env, s);
31871141 894 } else {
28b68cd7 895 offset = read_im16(env, s);
31871141 896 }
e6e5906b
PB		 897 break;
898 case OS_LONG:
d4d79bb1 899 offset = read_im32(env, s);
e6e5906b
PB		 900 break;
901 default:
7372c2b9 902 g_assert_not_reached();
e6e5906b 903 }
e1f3808e 904 return tcg_const_i32(offset);
e6e5906b 905 default:
e1f3808e 906 return NULL_QREG;
e6e5906b
PB		 907 }
908 }
909 /* Should never happen. */
e1f3808e 910 return NULL_QREG;
e6e5906b
PB		 911}
912
f84aab26
RH		 913static TCGv gen_ea(CPUM68KState *env, DisasContext *s, uint16_t insn,
914 int opsize, TCGv val, TCGv *addrp, ea_what what)
915{
916 int mode = extract32(insn, 3, 3);
917 int reg0 = REG(insn, 0);
918 return gen_ea_mode(env, s, mode, reg0, opsize, val, addrp, what);
919}
920
f83311e4
LV		 921static TCGv_ptr gen_fp_ptr(int freg)
922{
923 TCGv_ptr fp = tcg_temp_new_ptr();
924 tcg_gen_addi_ptr(fp, cpu_env, offsetof(CPUM68KState, fregs[freg]));
925 return fp;
926}
927
928static TCGv_ptr gen_fp_result_ptr(void)
929{
930 TCGv_ptr fp = tcg_temp_new_ptr();
931 tcg_gen_addi_ptr(fp, cpu_env, offsetof(CPUM68KState, fp_result));
932 return fp;
933}
934
935static void gen_fp_move(TCGv_ptr dest, TCGv_ptr src)
936{
937 TCGv t32;
938 TCGv_i64 t64;
939
940 t32 = tcg_temp_new();
941 tcg_gen_ld16u_i32(t32, src, offsetof(FPReg, l.upper));
942 tcg_gen_st16_i32(t32, dest, offsetof(FPReg, l.upper));
943 tcg_temp_free(t32);
944
945 t64 = tcg_temp_new_i64();
946 tcg_gen_ld_i64(t64, src, offsetof(FPReg, l.lower));
947 tcg_gen_st_i64(t64, dest, offsetof(FPReg, l.lower));
948 tcg_temp_free_i64(t64);
949}
950
951static void gen_load_fp(DisasContext *s, int opsize, TCGv addr, TCGv_ptr fp)
952{
953 TCGv tmp;
954 TCGv_i64 t64;
955 int index = IS_USER(s);
956
957 t64 = tcg_temp_new_i64();
958 tmp = tcg_temp_new();
959 switch (opsize) {
960 case OS_BYTE:
961 tcg_gen_qemu_ld8s(tmp, addr, index);
962 gen_helper_exts32(cpu_env, fp, tmp);
963 break;
964 case OS_WORD:
965 tcg_gen_qemu_ld16s(tmp, addr, index);
966 gen_helper_exts32(cpu_env, fp, tmp);
967 break;
968 case OS_LONG:
969 tcg_gen_qemu_ld32u(tmp, addr, index);
970 gen_helper_exts32(cpu_env, fp, tmp);
971 break;
972 case OS_SINGLE:
973 tcg_gen_qemu_ld32u(tmp, addr, index);
974 gen_helper_extf32(cpu_env, fp, tmp);
975 break;
976 case OS_DOUBLE:
977 tcg_gen_qemu_ld64(t64, addr, index);
978 gen_helper_extf64(cpu_env, fp, t64);
979 tcg_temp_free_i64(t64);
980 break;
981 case OS_EXTENDED:
982 if (m68k_feature(s->env, M68K_FEATURE_CF_FPU)) {
983 gen_exception(s, s->insn_pc, EXCP_FP_UNIMP);
984 break;
985 }
986 tcg_gen_qemu_ld32u(tmp, addr, index);
987 tcg_gen_shri_i32(tmp, tmp, 16);
988 tcg_gen_st16_i32(tmp, fp, offsetof(FPReg, l.upper));
989 tcg_gen_addi_i32(tmp, addr, 4);
990 tcg_gen_qemu_ld64(t64, tmp, index);
991 tcg_gen_st_i64(t64, fp, offsetof(FPReg, l.lower));
992 break;
993 case OS_PACKED:
994 /* unimplemented data type on 68040/ColdFire
995 * FIXME if needed for another FPU
996 */
997 gen_exception(s, s->insn_pc, EXCP_FP_UNIMP);
998 break;
999 default:
1000 g_assert_not_reached();
1001 }
1002 tcg_temp_free(tmp);
1003 tcg_temp_free_i64(t64);
1004 gen_throws_exception = gen_last_qop;
1005}
1006
1007static void gen_store_fp(DisasContext *s, int opsize, TCGv addr, TCGv_ptr fp)
1008{
1009 TCGv tmp;
1010 TCGv_i64 t64;
1011 int index = IS_USER(s);
1012
1013 t64 = tcg_temp_new_i64();
1014 tmp = tcg_temp_new();
1015 switch (opsize) {
1016 case OS_BYTE:
1017 gen_helper_reds32(tmp, cpu_env, fp);
1018 tcg_gen_qemu_st8(tmp, addr, index);
1019 break;
1020 case OS_WORD:
1021 gen_helper_reds32(tmp, cpu_env, fp);
1022 tcg_gen_qemu_st16(tmp, addr, index);
1023 break;
1024 case OS_LONG:
1025 gen_helper_reds32(tmp, cpu_env, fp);
1026 tcg_gen_qemu_st32(tmp, addr, index);
1027 break;
1028 case OS_SINGLE:
1029 gen_helper_redf32(tmp, cpu_env, fp);
1030 tcg_gen_qemu_st32(tmp, addr, index);
1031 break;
1032 case OS_DOUBLE:
1033 gen_helper_redf64(t64, cpu_env, fp);
1034 tcg_gen_qemu_st64(t64, addr, index);
1035 break;
1036 case OS_EXTENDED:
1037 if (m68k_feature(s->env, M68K_FEATURE_CF_FPU)) {
1038 gen_exception(s, s->insn_pc, EXCP_FP_UNIMP);
1039 break;
1040 }
1041 tcg_gen_ld16u_i32(tmp, fp, offsetof(FPReg, l.upper));
1042 tcg_gen_shli_i32(tmp, tmp, 16);
1043 tcg_gen_qemu_st32(tmp, addr, index);
1044 tcg_gen_addi_i32(tmp, addr, 4);
1045 tcg_gen_ld_i64(t64, fp, offsetof(FPReg, l.lower));
1046 tcg_gen_qemu_st64(t64, tmp, index);
1047 break;
1048 case OS_PACKED:
1049 /* unimplemented data type on 68040/ColdFire
1050 * FIXME if needed for another FPU
1051 */
1052 gen_exception(s, s->insn_pc, EXCP_FP_UNIMP);
1053 break;
1054 default:
1055 g_assert_not_reached();
1056 }
1057 tcg_temp_free(tmp);
1058 tcg_temp_free_i64(t64);
1059 gen_throws_exception = gen_last_qop;
1060}
1061
1062static void gen_ldst_fp(DisasContext *s, int opsize, TCGv addr,
1063 TCGv_ptr fp, ea_what what)
1064{
1065 if (what == EA_STORE) {
1066 gen_store_fp(s, opsize, addr, fp);
1067 } else {
1068 gen_load_fp(s, opsize, addr, fp);
1069 }
1070}
1071
1072static int gen_ea_mode_fp(CPUM68KState *env, DisasContext *s, int mode,
1073 int reg0, int opsize, TCGv_ptr fp, ea_what what)
1074{
1075 TCGv reg, addr, tmp;
1076 TCGv_i64 t64;
1077
1078 switch (mode) {
1079 case 0: /* Data register direct. */
1080 reg = cpu_dregs[reg0];
1081 if (what == EA_STORE) {
1082 switch (opsize) {
1083 case OS_BYTE:
1084 case OS_WORD:
1085 case OS_LONG:
1086 gen_helper_reds32(reg, cpu_env, fp);
1087 break;
1088 case OS_SINGLE:
1089 gen_helper_redf32(reg, cpu_env, fp);
1090 break;
1091 default:
1092 g_assert_not_reached();
1093 }
1094 } else {
1095 tmp = tcg_temp_new();
1096 switch (opsize) {
1097 case OS_BYTE:
1098 tcg_gen_ext8s_i32(tmp, reg);
1099 gen_helper_exts32(cpu_env, fp, tmp);
1100 break;
1101 case OS_WORD:
1102 tcg_gen_ext16s_i32(tmp, reg);
1103 gen_helper_exts32(cpu_env, fp, tmp);
1104 break;
1105 case OS_LONG:
1106 gen_helper_exts32(cpu_env, fp, reg);
1107 break;
1108 case OS_SINGLE:
1109 gen_helper_extf32(cpu_env, fp, reg);
1110 break;
1111 default:
1112 g_assert_not_reached();
1113 }
1114 tcg_temp_free(tmp);
1115 }
1116 return 0;
1117 case 1: /* Address register direct. */
1118 return -1;
1119 case 2: /* Indirect register */
1120 addr = get_areg(s, reg0);
1121 gen_ldst_fp(s, opsize, addr, fp, what);
1122 return 0;
1123 case 3: /* Indirect postincrement. */
1124 addr = cpu_aregs[reg0];
1125 gen_ldst_fp(s, opsize, addr, fp, what);
1126 tcg_gen_addi_i32(addr, addr, opsize_bytes(opsize));
1127 return 0;
1128 case 4: /* Indirect predecrememnt. */
1129 addr = gen_lea_mode(env, s, mode, reg0, opsize);
1130 if (IS_NULL_QREG(addr)) {
1131 return -1;
1132 }
1133 gen_ldst_fp(s, opsize, addr, fp, what);
1134 tcg_gen_mov_i32(cpu_aregs[reg0], addr);
1135 return 0;
1136 case 5: /* Indirect displacement. */
1137 case 6: /* Indirect index + displacement. */
1138 do_indirect:
1139 addr = gen_lea_mode(env, s, mode, reg0, opsize);
1140 if (IS_NULL_QREG(addr)) {
1141 return -1;
1142 }
1143 gen_ldst_fp(s, opsize, addr, fp, what);
1144 return 0;
1145 case 7: /* Other */
1146 switch (reg0) {
1147 case 0: /* Absolute short. */
1148 case 1: /* Absolute long. */
1149 case 2: /* pc displacement */
1150 case 3: /* pc index+displacement. */
1151 goto do_indirect;
1152 case 4: /* Immediate. */
1153 if (what == EA_STORE) {
1154 return -1;
1155 }
1156 switch (opsize) {
1157 case OS_BYTE:
1158 tmp = tcg_const_i32((int8_t)read_im8(env, s));
1159 gen_helper_exts32(cpu_env, fp, tmp);
1160 tcg_temp_free(tmp);
1161 break;
1162 case OS_WORD:
1163 tmp = tcg_const_i32((int16_t)read_im16(env, s));
1164 gen_helper_exts32(cpu_env, fp, tmp);
1165 tcg_temp_free(tmp);
1166 break;
1167 case OS_LONG:
1168 tmp = tcg_const_i32(read_im32(env, s));
1169 gen_helper_exts32(cpu_env, fp, tmp);
1170 tcg_temp_free(tmp);
1171 break;
1172 case OS_SINGLE:
1173 tmp = tcg_const_i32(read_im32(env, s));
1174 gen_helper_extf32(cpu_env, fp, tmp);
1175 tcg_temp_free(tmp);
1176 break;
1177 case OS_DOUBLE:
1178 t64 = tcg_const_i64(read_im64(env, s));
1179 gen_helper_extf64(cpu_env, fp, t64);
1180 tcg_temp_free_i64(t64);
1181 break;
1182 case OS_EXTENDED:
1183 if (m68k_feature(s->env, M68K_FEATURE_CF_FPU)) {
1184 gen_exception(s, s->insn_pc, EXCP_FP_UNIMP);
1185 break;
1186 }
1187 tmp = tcg_const_i32(read_im32(env, s) >> 16);
1188 tcg_gen_st16_i32(tmp, fp, offsetof(FPReg, l.upper));
1189 tcg_temp_free(tmp);
1190 t64 = tcg_const_i64(read_im64(env, s));
1191 tcg_gen_st_i64(t64, fp, offsetof(FPReg, l.lower));
1192 tcg_temp_free_i64(t64);
1193 break;
1194 case OS_PACKED:
1195 /* unimplemented data type on 68040/ColdFire
1196 * FIXME if needed for another FPU
1197 */
1198 gen_exception(s, s->insn_pc, EXCP_FP_UNIMP);
1199 break;
1200 default:
1201 g_assert_not_reached();
1202 }
1203 return 0;
1204 default:
1205 return -1;
1206 }
1207 }
1208 return -1;
1209}
1210
1211static int gen_ea_fp(CPUM68KState *env, DisasContext *s, uint16_t insn,
1212 int opsize, TCGv_ptr fp, ea_what what)
1213{
1214 int mode = extract32(insn, 3, 3);
1215 int reg0 = REG(insn, 0);
1216 return gen_ea_mode_fp(env, s, mode, reg0, opsize, fp, what);
1217}
1218
6a432295
RH		 1219typedef struct {
1220 TCGCond tcond;
1221 bool g1;
1222 bool g2;
1223 TCGv v1;
1224 TCGv v2;
1225} DisasCompare;
1226
1227static void gen_cc_cond(DisasCompare *c, DisasContext *s, int cond)
e6e5906b 1228{
620c6cf6
RH		 1229 TCGv tmp, tmp2;
1230 TCGCond tcond;
9d896621 1231 CCOp op = s->cc_op;
e6e5906b 1232
9d896621 1233 /* The CC_OP_CMP form can handle most normal comparisons directly. */
db3d7945 1234 if (op == CC_OP_CMPB || op == CC_OP_CMPW || op == CC_OP_CMPL) {
9d896621
RH		 1235 c->g1 = c->g2 = 1;
1236 c->v1 = QREG_CC_N;
1237 c->v2 = QREG_CC_V;
1238 switch (cond) {
1239 case 2: /* HI */
1240 case 3: /* LS */
1241 tcond = TCG_COND_LEU;
1242 goto done;
1243 case 4: /* CC */
1244 case 5: /* CS */
1245 tcond = TCG_COND_LTU;
1246 goto done;
1247 case 6: /* NE */
1248 case 7: /* EQ */
1249 tcond = TCG_COND_EQ;
1250 goto done;
1251 case 10: /* PL */
1252 case 11: /* MI */
1253 c->g1 = c->g2 = 0;
1254 c->v2 = tcg_const_i32(0);
1255 c->v1 = tmp = tcg_temp_new();
1256 tcg_gen_sub_i32(tmp, QREG_CC_N, QREG_CC_V);
db3d7945 1257 gen_ext(tmp, tmp, op - CC_OP_CMPB, 1);
9d896621
RH		 1258 /* fallthru */
1259 case 12: /* GE */
1260 case 13: /* LT */
1261 tcond = TCG_COND_LT;
1262 goto done;
1263 case 14: /* GT */
1264 case 15: /* LE */
1265 tcond = TCG_COND_LE;
1266 goto done;
1267 }
1268 }
6a432295
RH		 1269
1270 c->g1 = 1;
1271 c->g2 = 0;
1272 c->v2 = tcg_const_i32(0);
1273
e6e5906b
PB		 1274 switch (cond) {
1275 case 0: /* T */
e6e5906b 1276 case 1: /* F */
6a432295
RH		 1277 c->v1 = c->v2;
1278 tcond = TCG_COND_NEVER;
9d896621
RH		 1279 goto done;
1280 case 14: /* GT (!(Z || (N ^ V))) */
1281 case 15: /* LE (Z || (N ^ V)) */
1282 /* Logic operations clear V, which simplifies LE to (Z || N),
1283 and since Z and N are co-located, this becomes a normal
1284 comparison vs N. */
1285 if (op == CC_OP_LOGIC) {
1286 c->v1 = QREG_CC_N;
1287 tcond = TCG_COND_LE;
1288 goto done;
1289 }
6a432295 1290 break;
9d896621
RH		 1291 case 12: /* GE (!(N ^ V)) */
1292 case 13: /* LT (N ^ V) */
1293 /* Logic operations clear V, which simplifies this to N. */
1294 if (op != CC_OP_LOGIC) {
1295 break;
1296 }
1297 /* fallthru */
1298 case 10: /* PL (!N) */
1299 case 11: /* MI (N) */
1300 /* Several cases represent N normally. */
db3d7945
LV		 1301 if (op == CC_OP_ADDB || op == CC_OP_ADDW || op == CC_OP_ADDL ||
1302 op == CC_OP_SUBB || op == CC_OP_SUBW || op == CC_OP_SUBL ||
1303 op == CC_OP_LOGIC) {
9d896621
RH		 1304 c->v1 = QREG_CC_N;
1305 tcond = TCG_COND_LT;
1306 goto done;
1307 }
1308 break;
1309 case 6: /* NE (!Z) */
1310 case 7: /* EQ (Z) */
1311 /* Some cases fold Z into N. */
db3d7945
LV		 1312 if (op == CC_OP_ADDB || op == CC_OP_ADDW || op == CC_OP_ADDL ||
1313 op == CC_OP_SUBB || op == CC_OP_SUBW || op == CC_OP_SUBL ||
1314 op == CC_OP_LOGIC) {
9d896621
RH		 1315 tcond = TCG_COND_EQ;
1316 c->v1 = QREG_CC_N;
1317 goto done;
1318 }
1319 break;
1320 case 4: /* CC (!C) */
1321 case 5: /* CS (C) */
1322 /* Some cases fold C into X. */
db3d7945
LV		 1323 if (op == CC_OP_ADDB || op == CC_OP_ADDW || op == CC_OP_ADDL ||
1324 op == CC_OP_ADDB || op == CC_OP_ADDW || op == CC_OP_ADDL) {
9d896621
RH		 1325 tcond = TCG_COND_NE;
1326 c->v1 = QREG_CC_X;
1327 goto done;
1328 }
1329 /* fallthru */
1330 case 8: /* VC (!V) */
1331 case 9: /* VS (V) */
1332 /* Logic operations clear V and C. */
1333 if (op == CC_OP_LOGIC) {
1334 tcond = TCG_COND_NEVER;
1335 c->v1 = c->v2;
1336 goto done;
1337 }
1338 break;
1339 }
1340
1341 /* Otherwise, flush flag state to CC_OP_FLAGS. */
1342 gen_flush_flags(s);
1343
1344 switch (cond) {
1345 case 0: /* T */
1346 case 1: /* F */
1347 default:
1348 /* Invalid, or handled above. */
1349 abort();
620c6cf6 1350 case 2: /* HI (!C && !Z) -> !(C || Z)*/
e6e5906b 1351 case 3: /* LS (C || Z) */
6a432295
RH		 1352 c->v1 = tmp = tcg_temp_new();
1353 c->g1 = 0;
1354 tcg_gen_setcond_i32(TCG_COND_EQ, tmp, QREG_CC_Z, c->v2);
620c6cf6 1355 tcg_gen_or_i32(tmp, tmp, QREG_CC_C);
6a432295 1356 tcond = TCG_COND_NE;
e6e5906b
PB		 1357 break;
1358 case 4: /* CC (!C) */
e6e5906b 1359 case 5: /* CS (C) */
6a432295
RH		 1360 c->v1 = QREG_CC_C;
1361 tcond = TCG_COND_NE;
e6e5906b
PB		 1362 break;
1363 case 6: /* NE (!Z) */
e6e5906b 1364 case 7: /* EQ (Z) */
6a432295
RH		 1365 c->v1 = QREG_CC_Z;
1366 tcond = TCG_COND_EQ;
e6e5906b
PB		 1367 break;
1368 case 8: /* VC (!V) */
e6e5906b 1369 case 9: /* VS (V) */
6a432295
RH		 1370 c->v1 = QREG_CC_V;
1371 tcond = TCG_COND_LT;
e6e5906b
PB		 1372 break;
1373 case 10: /* PL (!N) */
e6e5906b 1374 case 11: /* MI (N) */
6a432295
RH		 1375 c->v1 = QREG_CC_N;
1376 tcond = TCG_COND_LT;
e6e5906b
PB		 1377 break;
1378 case 12: /* GE (!(N ^ V)) */
e6e5906b 1379 case 13: /* LT (N ^ V) */
6a432295
RH		 1380 c->v1 = tmp = tcg_temp_new();
1381 c->g1 = 0;
620c6cf6 1382 tcg_gen_xor_i32(tmp, QREG_CC_N, QREG_CC_V);
6a432295 1383 tcond = TCG_COND_LT;
e6e5906b
PB		 1384 break;
1385 case 14: /* GT (!(Z || (N ^ V))) */
e6e5906b 1386 case 15: /* LE (Z || (N ^ V)) */
6a432295
RH		 1387 c->v1 = tmp = tcg_temp_new();
1388 c->g1 = 0;
1389 tcg_gen_setcond_i32(TCG_COND_EQ, tmp, QREG_CC_Z, c->v2);
620c6cf6
RH		 1390 tcg_gen_neg_i32(tmp, tmp);
1391 tmp2 = tcg_temp_new();
1392 tcg_gen_xor_i32(tmp2, QREG_CC_N, QREG_CC_V);
1393 tcg_gen_or_i32(tmp, tmp, tmp2);
6a432295
RH		 1394 tcg_temp_free(tmp2);
1395 tcond = TCG_COND_LT;
e6e5906b 1396 break;
e6e5906b 1397 }
9d896621
RH		 1398
1399 done:
6a432295
RH		 1400 if ((cond & 1) == 0) {
1401 tcond = tcg_invert_cond(tcond);
1402 }
1403 c->tcond = tcond;
1404}
1405
1406static void free_cond(DisasCompare *c)
1407{
1408 if (!c->g1) {
1409 tcg_temp_free(c->v1);
1410 }
1411 if (!c->g2) {
1412 tcg_temp_free(c->v2);
1413 }
1414}
1415
1416static void gen_jmpcc(DisasContext *s, int cond, TCGLabel *l1)
1417{
1418 DisasCompare c;
1419
1420 gen_cc_cond(&c, s, cond);
1421 update_cc_op(s);
1422 tcg_gen_brcond_i32(c.tcond, c.v1, c.v2, l1);
1423 free_cond(&c);
e6e5906b
PB		 1424}
1425
0633879f
PB		 1426/* Force a TB lookup after an instruction that changes the CPU state. */
1427static void gen_lookup_tb(DisasContext *s)
1428{
9fdb533f 1429 update_cc_op(s);
e1f3808e 1430 tcg_gen_movi_i32(QREG_PC, s->pc);
0633879f
PB		 1431 s->is_jmp = DISAS_UPDATE;
1432}
1433
d4d79bb1
BS		 1434#define SRC_EA(env, result, opsize, op_sign, addrp) do { \
1435 result = gen_ea(env, s, insn, opsize, NULL_QREG, addrp, \
1436 op_sign ? EA_LOADS : EA_LOADU); \
1437 if (IS_NULL_QREG(result)) { \
1438 gen_addr_fault(s); \
1439 return; \
1440 } \
510ff0b7
PB		 1441 } while (0)
1442
d4d79bb1
BS		 1443#define DEST_EA(env, insn, opsize, val, addrp) do { \
1444 TCGv ea_result = gen_ea(env, s, insn, opsize, val, addrp, EA_STORE); \
1445 if (IS_NULL_QREG(ea_result)) { \
1446 gen_addr_fault(s); \
1447 return; \
1448 } \
510ff0b7
PB		 1449 } while (0)
1450
90aa39a1
SF		 1451static inline bool use_goto_tb(DisasContext *s, uint32_t dest)
1452{
1453#ifndef CONFIG_USER_ONLY
1454 return (s->tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) ||
1455 (s->insn_pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK);
1456#else
1457 return true;
1458#endif
1459}
1460
e6e5906b
PB		 1461/* Generate a jump to an immediate address. */
1462static void gen_jmp_tb(DisasContext *s, int n, uint32_t dest)
1463{
551bd27f 1464 if (unlikely(s->singlestep_enabled)) {
e6e5906b 1465 gen_exception(s, dest, EXCP_DEBUG);
90aa39a1 1466 } else if (use_goto_tb(s, dest)) {
57fec1fe 1467 tcg_gen_goto_tb(n);
e1f3808e 1468 tcg_gen_movi_i32(QREG_PC, dest);
90aa39a1 1469 tcg_gen_exit_tb((uintptr_t)s->tb + n);
e6e5906b 1470 } else {
e1f3808e 1471 gen_jmp_im(s, dest);
57fec1fe 1472 tcg_gen_exit_tb(0);
e6e5906b
PB		 1473 }
1474 s->is_jmp = DISAS_TB_JUMP;
1475}
1476
d5a3cf33
LV		 1477DISAS_INSN(scc)
1478{
1479 DisasCompare c;
1480 int cond;
1481 TCGv tmp;
1482
1483 cond = (insn >> 8) & 0xf;
1484 gen_cc_cond(&c, s, cond);
1485
1486 tmp = tcg_temp_new();
1487 tcg_gen_setcond_i32(c.tcond, tmp, c.v1, c.v2);
1488 free_cond(&c);
1489
1490 tcg_gen_neg_i32(tmp, tmp);
1491 DEST_EA(env, insn, OS_BYTE, tmp, NULL);
1492 tcg_temp_free(tmp);
1493}
1494
beff27ab
LV		 1495DISAS_INSN(dbcc)
1496{
1497 TCGLabel *l1;
1498 TCGv reg;
1499 TCGv tmp;
1500 int16_t offset;
1501 uint32_t base;
1502
1503 reg = DREG(insn, 0);
1504 base = s->pc;
1505 offset = (int16_t)read_im16(env, s);
1506 l1 = gen_new_label();
1507 gen_jmpcc(s, (insn >> 8) & 0xf, l1);
1508
1509 tmp = tcg_temp_new();
1510 tcg_gen_ext16s_i32(tmp, reg);
1511 tcg_gen_addi_i32(tmp, tmp, -1);
1512 gen_partset_reg(OS_WORD, reg, tmp);
1513 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, -1, l1);
1514 gen_jmp_tb(s, 1, base + offset);
1515 gen_set_label(l1);
1516 gen_jmp_tb(s, 0, s->pc);
1517}
1518
e6e5906b
PB		 1519DISAS_INSN(undef_mac)
1520{
1521 gen_exception(s, s->pc - 2, EXCP_LINEA);
1522}
1523
1524DISAS_INSN(undef_fpu)
1525{
1526 gen_exception(s, s->pc - 2, EXCP_LINEF);
1527}
1528
1529DISAS_INSN(undef)
1530{
72d2e4b6
RH		 1531 /* ??? This is both instructions that are as yet unimplemented
1532 for the 680x0 series, as well as those that are implemented
1533 but actually illegal for CPU32 or pre-68020. */
1534 qemu_log_mask(LOG_UNIMP, "Illegal instruction: %04x @ %08x",
1535 insn, s->pc - 2);
e6e5906b 1536 gen_exception(s, s->pc - 2, EXCP_UNSUPPORTED);
e6e5906b
PB		 1537}
1538
1539DISAS_INSN(mulw)
1540{
e1f3808e
PB		 1541 TCGv reg;
1542 TCGv tmp;
1543 TCGv src;
e6e5906b
PB		 1544 int sign;
1545
1546 sign = (insn & 0x100) != 0;
1547 reg = DREG(insn, 9);
a7812ae4 1548 tmp = tcg_temp_new();
e6e5906b 1549 if (sign)
e1f3808e 1550 tcg_gen_ext16s_i32(tmp, reg);
e6e5906b 1551 else
e1f3808e 1552 tcg_gen_ext16u_i32(tmp, reg);
d4d79bb1 1553 SRC_EA(env, src, OS_WORD, sign, NULL);
e1f3808e
PB		 1554 tcg_gen_mul_i32(tmp, tmp, src);
1555 tcg_gen_mov_i32(reg, tmp);
4a18cd44 1556 gen_logic_cc(s, tmp, OS_LONG);
2b5e2170 1557 tcg_temp_free(tmp);
e6e5906b
PB		 1558}
1559
1560DISAS_INSN(divw)
1561{
e6e5906b 1562 int sign;
0ccb9c1d
LV		 1563 TCGv src;
1564 TCGv destr;
1565
1566 /* divX.w <EA>,Dn 32/16 -> 16r:16q */
e6e5906b
PB		 1567
1568 sign = (insn & 0x100) != 0;
0ccb9c1d
LV		 1569
1570 /* dest.l / src.w */
1571
d4d79bb1 1572 SRC_EA(env, src, OS_WORD, sign, NULL);
0ccb9c1d 1573 destr = tcg_const_i32(REG(insn, 9));
e6e5906b 1574 if (sign) {
0ccb9c1d 1575 gen_helper_divsw(cpu_env, destr, src);
e6e5906b 1576 } else {
0ccb9c1d 1577 gen_helper_divuw(cpu_env, destr, src);
e6e5906b 1578 }
0ccb9c1d 1579 tcg_temp_free(destr);
620c6cf6 1580
9fdb533f 1581 set_cc_op(s, CC_OP_FLAGS);
e6e5906b
PB		 1582}
1583
1584DISAS_INSN(divl)
1585{
0ccb9c1d
LV		 1586 TCGv num, reg, den;
1587 int sign;
e6e5906b
PB		 1588 uint16_t ext;
1589
28b68cd7 1590 ext = read_im16(env, s);
0ccb9c1d
LV		 1591
1592 sign = (ext & 0x0800) != 0;
1593
1594 if (ext & 0x400) {
1595 if (!m68k_feature(s->env, M68K_FEATURE_QUAD_MULDIV)) {
1596 gen_exception(s, s->insn_pc, EXCP_ILLEGAL);
1597 return;
1598 }
1599
1600 /* divX.l <EA>, Dr:Dq 64/32 -> 32r:32q */
1601
1602 SRC_EA(env, den, OS_LONG, 0, NULL);
1603 num = tcg_const_i32(REG(ext, 12));
1604 reg = tcg_const_i32(REG(ext, 0));
1605 if (sign) {
1606 gen_helper_divsll(cpu_env, num, reg, den);
1607 } else {
1608 gen_helper_divull(cpu_env, num, reg, den);
1609 }
1610 tcg_temp_free(reg);
1611 tcg_temp_free(num);
1612 set_cc_op(s, CC_OP_FLAGS);
e6e5906b
PB		 1613 return;
1614 }
0ccb9c1d
LV		 1615
1616 /* divX.l <EA>, Dq 32/32 -> 32q */
1617 /* divXl.l <EA>, Dr:Dq 32/32 -> 32r:32q */
1618
d4d79bb1 1619 SRC_EA(env, den, OS_LONG, 0, NULL);
0ccb9c1d
LV		 1620 num = tcg_const_i32(REG(ext, 12));
1621 reg = tcg_const_i32(REG(ext, 0));
1622 if (sign) {
1623 gen_helper_divsl(cpu_env, num, reg, den);
e6e5906b 1624 } else {
0ccb9c1d 1625 gen_helper_divul(cpu_env, num, reg, den);
e6e5906b 1626 }
0ccb9c1d
LV		 1627 tcg_temp_free(reg);
1628 tcg_temp_free(num);
1629
9fdb533f 1630 set_cc_op(s, CC_OP_FLAGS);
e6e5906b
PB		 1631}
1632
fb5543d8
LV		 1633static void bcd_add(TCGv dest, TCGv src)
1634{
1635 TCGv t0, t1;
1636
1637 /* dest10 = dest10 + src10 + X
1638 *
1639 * t1 = src
1640 * t2 = t1 + 0x066
1641 * t3 = t2 + dest + X
1642 * t4 = t2 ^ dest
1643 * t5 = t3 ^ t4
1644 * t6 = ~t5 & 0x110
1645 * t7 = (t6 >> 2) | (t6 >> 3)
1646 * return t3 - t7
1647 */
1648
1649 /* t1 = (src + 0x066) + dest + X
1650 * = result with some possible exceding 0x6
1651 */
1652
1653 t0 = tcg_const_i32(0x066);
1654 tcg_gen_add_i32(t0, t0, src);
1655
1656 t1 = tcg_temp_new();
1657 tcg_gen_add_i32(t1, t0, dest);
1658 tcg_gen_add_i32(t1, t1, QREG_CC_X);
1659
1660 /* we will remove exceding 0x6 where there is no carry */
1661
1662 /* t0 = (src + 0x0066) ^ dest
1663 * = t1 without carries
1664 */
1665
1666 tcg_gen_xor_i32(t0, t0, dest);
1667
1668 /* extract the carries
1669 * t0 = t0 ^ t1
1670 * = only the carries
1671 */
1672
1673 tcg_gen_xor_i32(t0, t0, t1);
1674
1675 /* generate 0x1 where there is no carry
1676 * and for each 0x10, generate a 0x6
1677 */
1678
1679 tcg_gen_shri_i32(t0, t0, 3);
1680 tcg_gen_not_i32(t0, t0);
1681 tcg_gen_andi_i32(t0, t0, 0x22);
1682 tcg_gen_add_i32(dest, t0, t0);
1683 tcg_gen_add_i32(dest, dest, t0);
1684 tcg_temp_free(t0);
1685
1686 /* remove the exceding 0x6
1687 * for digits that have not generated a carry
1688 */
1689
1690 tcg_gen_sub_i32(dest, t1, dest);
1691 tcg_temp_free(t1);
1692}
1693
1694static void bcd_sub(TCGv dest, TCGv src)
1695{
1696 TCGv t0, t1, t2;
1697
1698 /* dest10 = dest10 - src10 - X
1699 * = bcd_add(dest + 1 - X, 0x199 - src)
1700 */
1701
1702 /* t0 = 0x066 + (0x199 - src) */
1703
1704 t0 = tcg_temp_new();
1705 tcg_gen_subfi_i32(t0, 0x1ff, src);
1706
1707 /* t1 = t0 + dest + 1 - X*/
1708
1709 t1 = tcg_temp_new();
1710 tcg_gen_add_i32(t1, t0, dest);
1711 tcg_gen_addi_i32(t1, t1, 1);
1712 tcg_gen_sub_i32(t1, t1, QREG_CC_X);
1713
1714 /* t2 = t0 ^ dest */
1715
1716 t2 = tcg_temp_new();
1717 tcg_gen_xor_i32(t2, t0, dest);
1718
1719 /* t0 = t1 ^ t2 */
1720
1721 tcg_gen_xor_i32(t0, t1, t2);
1722
1723 /* t2 = ~t0 & 0x110
1724 * t0 = (t2 >> 2) | (t2 >> 3)
1725 *
1726 * to fit on 8bit operands, changed in:
1727 *
1728 * t2 = ~(t0 >> 3) & 0x22
1729 * t0 = t2 + t2
1730 * t0 = t0 + t2
1731 */
1732
1733 tcg_gen_shri_i32(t2, t0, 3);
1734 tcg_gen_not_i32(t2, t2);
1735 tcg_gen_andi_i32(t2, t2, 0x22);
1736 tcg_gen_add_i32(t0, t2, t2);
1737 tcg_gen_add_i32(t0, t0, t2);
1738 tcg_temp_free(t2);
1739
1740 /* return t1 - t0 */
1741
1742 tcg_gen_sub_i32(dest, t1, t0);
1743 tcg_temp_free(t0);
1744 tcg_temp_free(t1);
1745}
1746
1747static void bcd_flags(TCGv val)
1748{
1749 tcg_gen_andi_i32(QREG_CC_C, val, 0x0ff);
1750 tcg_gen_or_i32(QREG_CC_Z, QREG_CC_Z, QREG_CC_C);
1751
1752 tcg_gen_shri_i32(QREG_CC_C, val, 8);
1753 tcg_gen_andi_i32(QREG_CC_C, QREG_CC_C, 1);
1754
1755 tcg_gen_mov_i32(QREG_CC_X, QREG_CC_C);
1756}
1757
1758DISAS_INSN(abcd_reg)
1759{
1760 TCGv src;
1761 TCGv dest;
1762
1763 gen_flush_flags(s); /* !Z is sticky */
1764
1765 src = gen_extend(DREG(insn, 0), OS_BYTE, 0);
1766 dest = gen_extend(DREG(insn, 9), OS_BYTE, 0);
1767 bcd_add(dest, src);
1768 gen_partset_reg(OS_BYTE, DREG(insn, 9), dest);
1769
1770 bcd_flags(dest);
1771}
1772
1773DISAS_INSN(abcd_mem)
1774{
1775 TCGv src, dest, addr;
1776
1777 gen_flush_flags(s); /* !Z is sticky */
1778
1779 /* Indirect pre-decrement load (mode 4) */
1780
1781 src = gen_ea_mode(env, s, 4, REG(insn, 0), OS_BYTE,
1782 NULL_QREG, NULL, EA_LOADU);
1783 dest = gen_ea_mode(env, s, 4, REG(insn, 9), OS_BYTE,
1784 NULL_QREG, &addr, EA_LOADU);
1785
1786 bcd_add(dest, src);
1787
1788 gen_ea_mode(env, s, 4, REG(insn, 9), OS_BYTE, dest, &addr, EA_STORE);
1789
1790 bcd_flags(dest);
1791}
1792
1793DISAS_INSN(sbcd_reg)
1794{
1795 TCGv src, dest;
1796
1797 gen_flush_flags(s); /* !Z is sticky */
1798
1799 src = gen_extend(DREG(insn, 0), OS_BYTE, 0);
1800 dest = gen_extend(DREG(insn, 9), OS_BYTE, 0);
1801
1802 bcd_sub(dest, src);
1803
1804 gen_partset_reg(OS_BYTE, DREG(insn, 9), dest);
1805
1806 bcd_flags(dest);
1807}
1808
1809DISAS_INSN(sbcd_mem)
1810{
1811 TCGv src, dest, addr;
1812
1813 gen_flush_flags(s); /* !Z is sticky */
1814
1815 /* Indirect pre-decrement load (mode 4) */
1816
1817 src = gen_ea_mode(env, s, 4, REG(insn, 0), OS_BYTE,
1818 NULL_QREG, NULL, EA_LOADU);
1819 dest = gen_ea_mode(env, s, 4, REG(insn, 9), OS_BYTE,
1820 NULL_QREG, &addr, EA_LOADU);
1821
1822 bcd_sub(dest, src);
1823
1824 gen_ea_mode(env, s, 4, REG(insn, 9), OS_BYTE, dest, &addr, EA_STORE);
1825
1826 bcd_flags(dest);
1827}
1828
1829DISAS_INSN(nbcd)
1830{
1831 TCGv src, dest;
1832 TCGv addr;
1833
1834 gen_flush_flags(s); /* !Z is sticky */
1835
1836 SRC_EA(env, src, OS_BYTE, 0, &addr);
1837
1838 dest = tcg_const_i32(0);
1839 bcd_sub(dest, src);
1840
1841 DEST_EA(env, insn, OS_BYTE, dest, &addr);
1842
1843 bcd_flags(dest);
1844
1845 tcg_temp_free(dest);
1846}
1847
e6e5906b
PB		 1848DISAS_INSN(addsub)
1849{
e1f3808e
PB		 1850 TCGv reg;
1851 TCGv dest;
1852 TCGv src;
1853 TCGv tmp;
1854 TCGv addr;
e6e5906b 1855 int add;
8a370c6c 1856 int opsize;
e6e5906b
PB		 1857
1858 add = (insn & 0x4000) != 0;
8a370c6c
LV		 1859 opsize = insn_opsize(insn);
1860 reg = gen_extend(DREG(insn, 9), opsize, 1);
a7812ae4 1861 dest = tcg_temp_new();
e6e5906b 1862 if (insn & 0x100) {
8a370c6c 1863 SRC_EA(env, tmp, opsize, 1, &addr);
e6e5906b
PB		 1864 src = reg;
1865 } else {
1866 tmp = reg;
8a370c6c 1867 SRC_EA(env, src, opsize, 1, NULL);
e6e5906b
PB		 1868 }
1869 if (add) {
e1f3808e 1870 tcg_gen_add_i32(dest, tmp, src);
f9083519 1871 tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, dest, src);
8a370c6c 1872 set_cc_op(s, CC_OP_ADDB + opsize);
e6e5906b 1873 } else {
f9083519 1874 tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, tmp, src);
e1f3808e 1875 tcg_gen_sub_i32(dest, tmp, src);
8a370c6c 1876 set_cc_op(s, CC_OP_SUBB + opsize);
e6e5906b 1877 }
8a370c6c 1878 gen_update_cc_add(dest, src, opsize);
e6e5906b 1879 if (insn & 0x100) {
8a370c6c 1880 DEST_EA(env, insn, opsize, dest, &addr);
e6e5906b 1881 } else {
8a370c6c 1882 gen_partset_reg(opsize, DREG(insn, 9), dest);
e6e5906b 1883 }
8a370c6c 1884 tcg_temp_free(dest);
e6e5906b
PB		 1885}
1886
e6e5906b
PB		 1887/* Reverse the order of the bits in REG. */
1888DISAS_INSN(bitrev)
1889{
e1f3808e 1890 TCGv reg;
e6e5906b 1891 reg = DREG(insn, 0);
e1f3808e 1892 gen_helper_bitrev(reg, reg);
e6e5906b
PB		 1893}
1894
1895DISAS_INSN(bitop_reg)
1896{
1897 int opsize;
1898 int op;
e1f3808e
PB		 1899 TCGv src1;
1900 TCGv src2;
1901 TCGv tmp;
1902 TCGv addr;
1903 TCGv dest;
e6e5906b
PB		 1904
1905 if ((insn & 0x38) != 0)
1906 opsize = OS_BYTE;
1907 else
1908 opsize = OS_LONG;
1909 op = (insn >> 6) & 3;
d4d79bb1 1910 SRC_EA(env, src1, opsize, 0, op ? &addr: NULL);
e6e5906b 1911
3c980d2e
LV		 1912 gen_flush_flags(s);
1913 src2 = tcg_temp_new();
e6e5906b 1914 if (opsize == OS_BYTE)
3c980d2e 1915 tcg_gen_andi_i32(src2, DREG(insn, 9), 7);
e6e5906b 1916 else
3c980d2e 1917 tcg_gen_andi_i32(src2, DREG(insn, 9), 31);
620c6cf6 1918
3c980d2e
LV		 1919 tmp = tcg_const_i32(1);
1920 tcg_gen_shl_i32(tmp, tmp, src2);
1921 tcg_temp_free(src2);
620c6cf6 1922
3c980d2e 1923 tcg_gen_and_i32(QREG_CC_Z, src1, tmp);
620c6cf6 1924
3c980d2e 1925 dest = tcg_temp_new();
e6e5906b
PB		 1926 switch (op) {
1927 case 1: /* bchg */
3c980d2e 1928 tcg_gen_xor_i32(dest, src1, tmp);
e6e5906b
PB		 1929 break;
1930 case 2: /* bclr */
3c980d2e 1931 tcg_gen_andc_i32(dest, src1, tmp);
e6e5906b
PB		 1932 break;
1933 case 3: /* bset */
3c980d2e 1934 tcg_gen_or_i32(dest, src1, tmp);
e6e5906b
PB		 1935 break;
1936 default: /* btst */
1937 break;
1938 }
3c980d2e 1939 tcg_temp_free(tmp);
620c6cf6 1940 if (op) {
d4d79bb1 1941 DEST_EA(env, insn, opsize, dest, &addr);
620c6cf6
RH		 1942 }
1943 tcg_temp_free(dest);
e6e5906b
PB		 1944}
1945
1946DISAS_INSN(sats)
1947{
e1f3808e 1948 TCGv reg;
e6e5906b 1949 reg = DREG(insn, 0);
e6e5906b 1950 gen_flush_flags(s);
620c6cf6 1951 gen_helper_sats(reg, reg, QREG_CC_V);
5dbb6784 1952 gen_logic_cc(s, reg, OS_LONG);
e6e5906b
PB		 1953}
1954
e1f3808e 1955static void gen_push(DisasContext *s, TCGv val)
e6e5906b 1956{
e1f3808e 1957 TCGv tmp;
e6e5906b 1958
a7812ae4 1959 tmp = tcg_temp_new();
e1f3808e 1960 tcg_gen_subi_i32(tmp, QREG_SP, 4);
0633879f 1961 gen_store(s, OS_LONG, tmp, val);
e1f3808e 1962 tcg_gen_mov_i32(QREG_SP, tmp);
2b5e2170 1963 tcg_temp_free(tmp);
e6e5906b
PB		 1964}
1965
7b542eb9
LV		 1966static TCGv mreg(int reg)
1967{
1968 if (reg < 8) {
1969 /* Dx */
1970 return cpu_dregs[reg];
1971 }
1972 /* Ax */
1973 return cpu_aregs[reg & 7];
1974}
1975
e6e5906b
PB		 1976DISAS_INSN(movem)
1977{
7b542eb9
LV		 1978 TCGv addr, incr, tmp, r[16];
1979 int is_load = (insn & 0x0400) != 0;
1980 int opsize = (insn & 0x40) != 0 ? OS_LONG : OS_WORD;
1981 uint16_t mask = read_im16(env, s);
1982 int mode = extract32(insn, 3, 3);
1983 int reg0 = REG(insn, 0);
e6e5906b 1984 int i;
e6e5906b 1985
7b542eb9
LV		 1986 tmp = cpu_aregs[reg0];
1987
1988 switch (mode) {
1989 case 0: /* data register direct */
1990 case 1: /* addr register direct */
1991 do_addr_fault:
510ff0b7
PB		 1992 gen_addr_fault(s);
1993 return;
7b542eb9
LV		 1994
1995 case 2: /* indirect */
1996 break;
1997
1998 case 3: /* indirect post-increment */
1999 if (!is_load) {
2000 /* post-increment is not allowed */
2001 goto do_addr_fault;
2002 }
2003 break;
2004
2005 case 4: /* indirect pre-decrement */
2006 if (is_load) {
2007 /* pre-decrement is not allowed */
2008 goto do_addr_fault;
2009 }
2010 /* We want a bare copy of the address reg, without any pre-decrement
2011 adjustment, as gen_lea would provide. */
2012 break;
2013
2014 default:
2015 tmp = gen_lea_mode(env, s, mode, reg0, opsize);
2016 if (IS_NULL_QREG(tmp)) {
2017 goto do_addr_fault;
2018 }
2019 break;
510ff0b7 2020 }
7b542eb9 2021
a7812ae4 2022 addr = tcg_temp_new();
e1f3808e 2023 tcg_gen_mov_i32(addr, tmp);
7b542eb9
LV		 2024 incr = tcg_const_i32(opsize_bytes(opsize));
2025
2026 if (is_load) {
2027 /* memory to register */
2028 for (i = 0; i < 16; i++) {
2029 if (mask & (1 << i)) {
2030 r[i] = gen_load(s, opsize, addr, 1);
2031 tcg_gen_add_i32(addr, addr, incr);
2032 }
2033 }
2034 for (i = 0; i < 16; i++) {
2035 if (mask & (1 << i)) {
2036 tcg_gen_mov_i32(mreg(i), r[i]);
2037 tcg_temp_free(r[i]);
2038 }
2039 }
2040 if (mode == 3) {
2041 /* post-increment: movem (An)+,X */
2042 tcg_gen_mov_i32(cpu_aregs[reg0], addr);
2043 }
2044 } else {
2045 /* register to memory */
2046 if (mode == 4) {
2047 /* pre-decrement: movem X,-(An) */
2048 for (i = 15; i >= 0; i--) {
2049 if ((mask << i) & 0x8000) {
2050 tcg_gen_sub_i32(addr, addr, incr);
2051 if (reg0 + 8 == i &&
2052 m68k_feature(s->env, M68K_FEATURE_EXT_FULL)) {
2053 /* M68020+: if the addressing register is the
2054 * register moved to memory, the value written
2055 * is the initial value decremented by the size of
2056 * the operation, regardless of how many actual
2057 * stores have been performed until this point.
2058 * M68000/M68010: the value is the initial value.
2059 */
2060 tmp = tcg_temp_new();
2061 tcg_gen_sub_i32(tmp, cpu_aregs[reg0], incr);
2062 gen_store(s, opsize, addr, tmp);
2063 tcg_temp_free(tmp);
2064 } else {
2065 gen_store(s, opsize, addr, mreg(i));
2066 }
2067 }
2068 }
2069 tcg_gen_mov_i32(cpu_aregs[reg0], addr);
2070 } else {
2071 for (i = 0; i < 16; i++) {
2072 if (mask & (1 << i)) {
2073 gen_store(s, opsize, addr, mreg(i));
2074 tcg_gen_add_i32(addr, addr, incr);
2075 }
e6e5906b 2076 }
e6e5906b
PB		 2077 }
2078 }
7b542eb9
LV		 2079
2080 tcg_temp_free(incr);
2081 tcg_temp_free(addr);
e6e5906b
PB		 2082}
2083
2084DISAS_INSN(bitop_im)
2085{
2086 int opsize;
2087 int op;
e1f3808e 2088 TCGv src1;
e6e5906b
PB		 2089 uint32_t mask;
2090 int bitnum;
e1f3808e
PB		 2091 TCGv tmp;
2092 TCGv addr;
e6e5906b
PB		 2093
2094 if ((insn & 0x38) != 0)
2095 opsize = OS_BYTE;
2096 else
2097 opsize = OS_LONG;
2098 op = (insn >> 6) & 3;
2099
28b68cd7 2100 bitnum = read_im16(env, s);
fe53c2be
LV		 2101 if (m68k_feature(s->env, M68K_FEATURE_M68000)) {
2102 if (bitnum & 0xfe00) {
2103 disas_undef(env, s, insn);
2104 return;
2105 }
2106 } else {
2107 if (bitnum & 0xff00) {
2108 disas_undef(env, s, insn);
2109 return;
2110 }
e6e5906b
PB		 2111 }
2112
d4d79bb1 2113 SRC_EA(env, src1, opsize, 0, op ? &addr: NULL);
e6e5906b 2114
3c980d2e 2115 gen_flush_flags(s);
e6e5906b
PB		 2116 if (opsize == OS_BYTE)
2117 bitnum &= 7;
2118 else
2119 bitnum &= 31;
2120 mask = 1 << bitnum;
2121
3c980d2e 2122 tcg_gen_andi_i32(QREG_CC_Z, src1, mask);
620c6cf6 2123
e1f3808e 2124 if (op) {
620c6cf6 2125 tmp = tcg_temp_new();
e1f3808e
PB		 2126 switch (op) {
2127 case 1: /* bchg */
2128 tcg_gen_xori_i32(tmp, src1, mask);
2129 break;
2130 case 2: /* bclr */
2131 tcg_gen_andi_i32(tmp, src1, ~mask);
2132 break;
2133 case 3: /* bset */
2134 tcg_gen_ori_i32(tmp, src1, mask);
2135 break;
2136 default: /* btst */
2137 break;
2138 }
d4d79bb1 2139 DEST_EA(env, insn, opsize, tmp, &addr);
620c6cf6 2140 tcg_temp_free(tmp);
e6e5906b 2141 }
e6e5906b 2142}
620c6cf6 2143
e6e5906b
PB		 2144DISAS_INSN(arith_im)
2145{
2146 int op;
92c62548 2147 TCGv im;
e1f3808e
PB		 2148 TCGv src1;
2149 TCGv dest;
2150 TCGv addr;
92c62548 2151 int opsize;
e6e5906b
PB		 2152
2153 op = (insn >> 9) & 7;
92c62548
LV		 2154 opsize = insn_opsize(insn);
2155 switch (opsize) {
2156 case OS_BYTE:
2157 im = tcg_const_i32((int8_t)read_im8(env, s));
2158 break;
2159 case OS_WORD:
2160 im = tcg_const_i32((int16_t)read_im16(env, s));
2161 break;
2162 case OS_LONG:
2163 im = tcg_const_i32(read_im32(env, s));
2164 break;
2165 default:
2166 abort();
2167 }
2168 SRC_EA(env, src1, opsize, 1, (op == 6) ? NULL : &addr);
a7812ae4 2169 dest = tcg_temp_new();
e6e5906b
PB		 2170 switch (op) {
2171 case 0: /* ori */
92c62548
LV		 2172 tcg_gen_or_i32(dest, src1, im);
2173 gen_logic_cc(s, dest, opsize);
e6e5906b
PB		 2174 break;
2175 case 1: /* andi */
92c62548
LV		 2176 tcg_gen_and_i32(dest, src1, im);
2177 gen_logic_cc(s, dest, opsize);
e6e5906b
PB		 2178 break;
2179 case 2: /* subi */
92c62548
LV		 2180 tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, src1, im);
2181 tcg_gen_sub_i32(dest, src1, im);
2182 gen_update_cc_add(dest, im, opsize);
2183 set_cc_op(s, CC_OP_SUBB + opsize);
e6e5906b
PB		 2184 break;
2185 case 3: /* addi */
92c62548
LV		 2186 tcg_gen_add_i32(dest, src1, im);
2187 gen_update_cc_add(dest, im, opsize);
2188 tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, dest, im);
2189 set_cc_op(s, CC_OP_ADDB + opsize);
e6e5906b
PB		 2190 break;
2191 case 5: /* eori */
92c62548
LV		 2192 tcg_gen_xor_i32(dest, src1, im);
2193 gen_logic_cc(s, dest, opsize);
e6e5906b
PB		 2194 break;
2195 case 6: /* cmpi */
92c62548 2196 gen_update_cc_cmp(s, src1, im, opsize);
e6e5906b
PB		 2197 break;
2198 default:
2199 abort();
2200 }
92c62548 2201 tcg_temp_free(im);
e6e5906b 2202 if (op != 6) {
92c62548 2203 DEST_EA(env, insn, opsize, dest, &addr);
e6e5906b 2204 }
92c62548 2205 tcg_temp_free(dest);
e6e5906b
PB		 2206}
2207
14f94406
LV		 2208DISAS_INSN(cas)
2209{
2210 int opsize;
2211 TCGv addr;
2212 uint16_t ext;
2213 TCGv load;
2214 TCGv cmp;
2215 TCGMemOp opc;
2216
2217 switch ((insn >> 9) & 3) {
2218 case 1:
2219 opsize = OS_BYTE;
2220 opc = MO_SB;
2221 break;
2222 case 2:
2223 opsize = OS_WORD;
2224 opc = MO_TESW;
2225 break;
2226 case 3:
2227 opsize = OS_LONG;
2228 opc = MO_TESL;
2229 break;
2230 default:
2231 g_assert_not_reached();
2232 }
14f94406
LV		 2233
2234 ext = read_im16(env, s);
2235
2236 /* cas Dc,Du,<EA> */
2237
2238 addr = gen_lea(env, s, insn, opsize);
2239 if (IS_NULL_QREG(addr)) {
2240 gen_addr_fault(s);
2241 return;
2242 }
2243
2244 cmp = gen_extend(DREG(ext, 0), opsize, 1);
2245
2246 /* if <EA> == Dc then
2247 * <EA> = Du
2248 * Dc = <EA> (because <EA> == Dc)
2249 * else
2250 * Dc = <EA>
2251 */
2252
2253 load = tcg_temp_new();
2254 tcg_gen_atomic_cmpxchg_i32(load, addr, cmp, DREG(ext, 6),
2255 IS_USER(s), opc);
2256 /* update flags before setting cmp to load */
2257 gen_update_cc_cmp(s, load, cmp, opsize);
2258 gen_partset_reg(opsize, DREG(ext, 0), load);
2259
2260 tcg_temp_free(load);
308feb93
LV		 2261
2262 switch (extract32(insn, 3, 3)) {
2263 case 3: /* Indirect postincrement. */
2264 tcg_gen_addi_i32(AREG(insn, 0), addr, opsize_bytes(opsize));
2265 break;
2266 case 4: /* Indirect predecrememnt. */
2267 tcg_gen_mov_i32(AREG(insn, 0), addr);
2268 break;
2269 }
14f94406
LV		 2270}
2271
2272DISAS_INSN(cas2w)
2273{
2274 uint16_t ext1, ext2;
2275 TCGv addr1, addr2;
2276 TCGv regs;
2277
2278 /* cas2 Dc1:Dc2,Du1:Du2,(Rn1):(Rn2) */
2279
2280 ext1 = read_im16(env, s);
2281
2282 if (ext1 & 0x8000) {
2283 /* Address Register */
2284 addr1 = AREG(ext1, 12);
2285 } else {
2286 /* Data Register */
2287 addr1 = DREG(ext1, 12);
2288 }
2289
2290 ext2 = read_im16(env, s);
2291 if (ext2 & 0x8000) {
2292 /* Address Register */
2293 addr2 = AREG(ext2, 12);
2294 } else {
2295 /* Data Register */
2296 addr2 = DREG(ext2, 12);
2297 }
2298
2299 /* if (R1) == Dc1 && (R2) == Dc2 then
2300 * (R1) = Du1
2301 * (R2) = Du2
2302 * else
2303 * Dc1 = (R1)
2304 * Dc2 = (R2)
2305 */
2306
2307 regs = tcg_const_i32(REG(ext2, 6) |
2308 (REG(ext1, 6) << 3) |
2309 (REG(ext2, 0) << 6) |
2310 (REG(ext1, 0) << 9));
2311 gen_helper_cas2w(cpu_env, regs, addr1, addr2);
2312 tcg_temp_free(regs);
2313
2314 /* Note that cas2w also assigned to env->cc_op. */
2315 s->cc_op = CC_OP_CMPW;
2316 s->cc_op_synced = 1;
2317}
2318
2319DISAS_INSN(cas2l)
2320{
2321 uint16_t ext1, ext2;
2322 TCGv addr1, addr2, regs;
2323
2324 /* cas2 Dc1:Dc2,Du1:Du2,(Rn1):(Rn2) */
2325
2326 ext1 = read_im16(env, s);
2327
2328 if (ext1 & 0x8000) {
2329 /* Address Register */
2330 addr1 = AREG(ext1, 12);
2331 } else {
2332 /* Data Register */
2333 addr1 = DREG(ext1, 12);
2334 }
2335
2336 ext2 = read_im16(env, s);
2337 if (ext2 & 0x8000) {
2338 /* Address Register */
2339 addr2 = AREG(ext2, 12);
2340 } else {
2341 /* Data Register */
2342 addr2 = DREG(ext2, 12);
2343 }
2344
2345 /* if (R1) == Dc1 && (R2) == Dc2 then
2346 * (R1) = Du1
2347 * (R2) = Du2
2348 * else
2349 * Dc1 = (R1)
2350 * Dc2 = (R2)
2351 */
2352
2353 regs = tcg_const_i32(REG(ext2, 6) |
2354 (REG(ext1, 6) << 3) |
2355 (REG(ext2, 0) << 6) |
2356 (REG(ext1, 0) << 9));
2357 gen_helper_cas2l(cpu_env, regs, addr1, addr2);
2358 tcg_temp_free(regs);
2359
2360 /* Note that cas2l also assigned to env->cc_op. */
2361 s->cc_op = CC_OP_CMPL;
2362 s->cc_op_synced = 1;
2363}
2364
e6e5906b
PB		 2365DISAS_INSN(byterev)
2366{
e1f3808e 2367 TCGv reg;
e6e5906b
PB		 2368
2369 reg = DREG(insn, 0);
66896cb8 2370 tcg_gen_bswap32_i32(reg, reg);
e6e5906b
PB		 2371}
2372
2373DISAS_INSN(move)
2374{
e1f3808e
PB		 2375 TCGv src;
2376 TCGv dest;
e6e5906b
PB		 2377 int op;
2378 int opsize;
2379
2380 switch (insn >> 12) {
2381 case 1: /* move.b */
2382 opsize = OS_BYTE;
2383 break;
2384 case 2: /* move.l */
2385 opsize = OS_LONG;
2386 break;
2387 case 3: /* move.w */
2388 opsize = OS_WORD;
2389 break;
2390 default:
2391 abort();
2392 }
d4d79bb1 2393 SRC_EA(env, src, opsize, 1, NULL);
e6e5906b
PB		 2394 op = (insn >> 6) & 7;
2395 if (op == 1) {
2396 /* movea */
2397 /* The value will already have been sign extended. */
2398 dest = AREG(insn, 9);
e1f3808e 2399 tcg_gen_mov_i32(dest, src);
e6e5906b
PB		 2400 } else {
2401 /* normal move */
2402 uint16_t dest_ea;
2403 dest_ea = ((insn >> 9) & 7) | (op << 3);
d4d79bb1 2404 DEST_EA(env, dest_ea, opsize, src, NULL);
e6e5906b 2405 /* This will be correct because loads sign extend. */
5dbb6784 2406 gen_logic_cc(s, src, opsize);
e6e5906b
PB		 2407 }
2408}
2409
2410DISAS_INSN(negx)
2411{
a665a820
RH		 2412 TCGv z;
2413 TCGv src;
2414 TCGv addr;
2415 int opsize;
e6e5906b 2416
a665a820
RH		 2417 opsize = insn_opsize(insn);
2418 SRC_EA(env, src, opsize, 1, &addr);
2419
2420 gen_flush_flags(s); /* compute old Z */
2421
2422 /* Perform substract with borrow.
2423 * (X, N) = -(src + X);
2424 */
2425
2426 z = tcg_const_i32(0);
2427 tcg_gen_add2_i32(QREG_CC_N, QREG_CC_X, src, z, QREG_CC_X, z);
2428 tcg_gen_sub2_i32(QREG_CC_N, QREG_CC_X, z, z, QREG_CC_N, QREG_CC_X);
2429 tcg_temp_free(z);
2430 gen_ext(QREG_CC_N, QREG_CC_N, opsize, 1);
2431
2432 tcg_gen_andi_i32(QREG_CC_X, QREG_CC_X, 1);
2433
2434 /* Compute signed-overflow for negation. The normal formula for
2435 * subtraction is (res ^ src) & (src ^ dest), but with dest==0
2436 * this simplies to res & src.
2437 */
2438
2439 tcg_gen_and_i32(QREG_CC_V, QREG_CC_N, src);
2440
2441 /* Copy the rest of the results into place. */
2442 tcg_gen_or_i32(QREG_CC_Z, QREG_CC_Z, QREG_CC_N); /* !Z is sticky */
2443 tcg_gen_mov_i32(QREG_CC_C, QREG_CC_X);
2444
2445 set_cc_op(s, CC_OP_FLAGS);
2446
2447 /* result is in QREG_CC_N */
2448
2449 DEST_EA(env, insn, opsize, QREG_CC_N, &addr);
e6e5906b
PB		 2450}
2451
2452DISAS_INSN(lea)
2453{
e1f3808e
PB		 2454 TCGv reg;
2455 TCGv tmp;
e6e5906b
PB		 2456
2457 reg = AREG(insn, 9);
d4d79bb1 2458 tmp = gen_lea(env, s, insn, OS_LONG);
e1f3808e 2459 if (IS_NULL_QREG(tmp)) {
510ff0b7
PB		 2460 gen_addr_fault(s);
2461 return;
2462 }
e1f3808e 2463 tcg_gen_mov_i32(reg, tmp);
e6e5906b
PB		 2464}
2465
2466DISAS_INSN(clr)
2467{
2468 int opsize;
2b5e2170
LV		 2469 TCGv zero;
2470
2471 zero = tcg_const_i32(0);
e6e5906b 2472
7ef25cdd 2473 opsize = insn_opsize(insn);
2b5e2170
LV		 2474 DEST_EA(env, insn, opsize, zero, NULL);
2475 gen_logic_cc(s, zero, opsize);
2476 tcg_temp_free(zero);
e6e5906b
PB		 2477}
2478
e1f3808e 2479static TCGv gen_get_ccr(DisasContext *s)
e6e5906b 2480{
e1f3808e 2481 TCGv dest;
e6e5906b
PB		 2482
2483 gen_flush_flags(s);
620c6cf6 2484 update_cc_op(s);
a7812ae4 2485 dest = tcg_temp_new();
620c6cf6 2486 gen_helper_get_ccr(dest, cpu_env);
0633879f
PB		 2487 return dest;
2488}
2489
2490DISAS_INSN(move_from_ccr)
2491{
e1f3808e 2492 TCGv ccr;
0633879f
PB		 2493
2494 ccr = gen_get_ccr(s);
7c0eb318 2495 DEST_EA(env, insn, OS_WORD, ccr, NULL);
e6e5906b
PB		 2496}
2497
2498DISAS_INSN(neg)
2499{
e1f3808e 2500 TCGv src1;
227de713
LV		 2501 TCGv dest;
2502 TCGv addr;
2503 int opsize;
e6e5906b 2504
227de713
LV		 2505 opsize = insn_opsize(insn);
2506 SRC_EA(env, src1, opsize, 1, &addr);
2507 dest = tcg_temp_new();
2508 tcg_gen_neg_i32(dest, src1);
2509 set_cc_op(s, CC_OP_SUBB + opsize);
2510 gen_update_cc_add(dest, src1, opsize);
2511 tcg_gen_setcondi_i32(TCG_COND_NE, QREG_CC_X, dest, 0);
2512 DEST_EA(env, insn, opsize, dest, &addr);
2513 tcg_temp_free(dest);
e6e5906b
PB		 2514}
2515
0633879f
PB		 2516static void gen_set_sr_im(DisasContext *s, uint16_t val, int ccr_only)
2517{
620c6cf6
RH		 2518 if (ccr_only) {
2519 tcg_gen_movi_i32(QREG_CC_C, val & CCF_C ? 1 : 0);
2520 tcg_gen_movi_i32(QREG_CC_V, val & CCF_V ? -1 : 0);
2521 tcg_gen_movi_i32(QREG_CC_Z, val & CCF_Z ? 0 : 1);
2522 tcg_gen_movi_i32(QREG_CC_N, val & CCF_N ? -1 : 0);
2523 tcg_gen_movi_i32(QREG_CC_X, val & CCF_X ? 1 : 0);
2524 } else {
2525 gen_helper_set_sr(cpu_env, tcg_const_i32(val));
0633879f 2526 }
9fdb533f 2527 set_cc_op(s, CC_OP_FLAGS);
0633879f
PB		 2528}
2529
620c6cf6
RH		 2530static void gen_set_sr(CPUM68KState *env, DisasContext *s, uint16_t insn,
2531 int ccr_only)
e6e5906b 2532{
620c6cf6
RH		 2533 if ((insn & 0x38) == 0) {
2534 if (ccr_only) {
2535 gen_helper_set_ccr(cpu_env, DREG(insn, 0));
2536 } else {
2537 gen_helper_set_sr(cpu_env, DREG(insn, 0));
2538 }
2539 set_cc_op(s, CC_OP_FLAGS);
2540 } else if ((insn & 0x3f) == 0x3c) {
2541 uint16_t val;
2542 val = read_im16(env, s);
2543 gen_set_sr_im(s, val, ccr_only);
2544 } else {
2545 disas_undef(env, s, insn);
7c0eb318
LV		 2546 }
2547}
e6e5906b 2548
7c0eb318 2549
0633879f
PB		 2550DISAS_INSN(move_to_ccr)
2551{
620c6cf6 2552 gen_set_sr(env, s, insn, 1);
0633879f
PB		 2553}
2554
e6e5906b
PB		 2555DISAS_INSN(not)
2556{
ea4f2a84
LV		 2557 TCGv src1;
2558 TCGv dest;
2559 TCGv addr;
2560 int opsize;
e6e5906b 2561
ea4f2a84
LV		 2562 opsize = insn_opsize(insn);
2563 SRC_EA(env, src1, opsize, 1, &addr);
2564 dest = tcg_temp_new();
2565 tcg_gen_not_i32(dest, src1);
2566 DEST_EA(env, insn, opsize, dest, &addr);
2567 gen_logic_cc(s, dest, opsize);
e6e5906b
PB		 2568}
2569
2570DISAS_INSN(swap)
2571{
e1f3808e
PB		 2572 TCGv src1;
2573 TCGv src2;
2574 TCGv reg;
e6e5906b 2575
a7812ae4
PB		 2576 src1 = tcg_temp_new();
2577 src2 = tcg_temp_new();
e6e5906b 2578 reg = DREG(insn, 0);
e1f3808e
PB		 2579 tcg_gen_shli_i32(src1, reg, 16);
2580 tcg_gen_shri_i32(src2, reg, 16);
2581 tcg_gen_or_i32(reg, src1, src2);
2b5e2170
LV		 2582 tcg_temp_free(src2);
2583 tcg_temp_free(src1);
5dbb6784 2584 gen_logic_cc(s, reg, OS_LONG);
e6e5906b
PB		 2585}
2586
71600eda
LV		 2587DISAS_INSN(bkpt)
2588{
2589 gen_exception(s, s->pc - 2, EXCP_DEBUG);
2590}
2591
e6e5906b
PB		 2592DISAS_INSN(pea)
2593{
e1f3808e 2594 TCGv tmp;
e6e5906b 2595
d4d79bb1 2596 tmp = gen_lea(env, s, insn, OS_LONG);
e1f3808e 2597 if (IS_NULL_QREG(tmp)) {
510ff0b7
PB		 2598 gen_addr_fault(s);
2599 return;
2600 }
0633879f 2601 gen_push(s, tmp);
e6e5906b
PB		 2602}
2603
2604DISAS_INSN(ext)
2605{
e6e5906b 2606 int op;
e1f3808e
PB		 2607 TCGv reg;
2608 TCGv tmp;
e6e5906b
PB		 2609
2610 reg = DREG(insn, 0);
2611 op = (insn >> 6) & 7;
a7812ae4 2612 tmp = tcg_temp_new();
e6e5906b 2613 if (op == 3)
e1f3808e 2614 tcg_gen_ext16s_i32(tmp, reg);
e6e5906b 2615 else
e1f3808e 2616 tcg_gen_ext8s_i32(tmp, reg);
e6e5906b
PB		 2617 if (op == 2)
2618 gen_partset_reg(OS_WORD, reg, tmp);
2619 else
e1f3808e 2620 tcg_gen_mov_i32(reg, tmp);
5dbb6784 2621 gen_logic_cc(s, tmp, OS_LONG);
2b5e2170 2622 tcg_temp_free(tmp);
e6e5906b
PB		 2623}
2624
2625DISAS_INSN(tst)
2626{
2627 int opsize;
e1f3808e 2628 TCGv tmp;
e6e5906b 2629
7ef25cdd 2630 opsize = insn_opsize(insn);
d4d79bb1 2631 SRC_EA(env, tmp, opsize, 1, NULL);
5dbb6784 2632 gen_logic_cc(s, tmp, opsize);
e6e5906b
PB		 2633}
2634
2635DISAS_INSN(pulse)
2636{
2637 /* Implemented as a NOP. */
2638}
2639
2640DISAS_INSN(illegal)
2641{
2642 gen_exception(s, s->pc - 2, EXCP_ILLEGAL);
2643}
2644
2645/* ??? This should be atomic. */
2646DISAS_INSN(tas)
2647{
e1f3808e
PB		 2648 TCGv dest;
2649 TCGv src1;
2650 TCGv addr;
e6e5906b 2651
a7812ae4 2652 dest = tcg_temp_new();
d4d79bb1 2653 SRC_EA(env, src1, OS_BYTE, 1, &addr);
5dbb6784 2654 gen_logic_cc(s, src1, OS_BYTE);
e1f3808e 2655 tcg_gen_ori_i32(dest, src1, 0x80);
d4d79bb1 2656 DEST_EA(env, insn, OS_BYTE, dest, &addr);
2b5e2170 2657 tcg_temp_free(dest);
e6e5906b
PB		 2658}
2659
2660DISAS_INSN(mull)
2661{
2662 uint16_t ext;
e1f3808e 2663 TCGv src1;
8be95def 2664 int sign;
e6e5906b 2665
28b68cd7 2666 ext = read_im16(env, s);
8be95def
LV		 2667
2668 sign = ext & 0x800;
2669
2670 if (ext & 0x400) {
2671 if (!m68k_feature(s->env, M68K_FEATURE_QUAD_MULDIV)) {
2672 gen_exception(s, s->pc - 4, EXCP_UNSUPPORTED);
2673 return;
2674 }
2675
2676 SRC_EA(env, src1, OS_LONG, 0, NULL);
2677
2678 if (sign) {
2679 tcg_gen_muls2_i32(QREG_CC_Z, QREG_CC_N, src1, DREG(ext, 12));
2680 } else {
2681 tcg_gen_mulu2_i32(QREG_CC_Z, QREG_CC_N, src1, DREG(ext, 12));
2682 }
2683 /* if Dl == Dh, 68040 returns low word */
2684 tcg_gen_mov_i32(DREG(ext, 0), QREG_CC_N);
2685 tcg_gen_mov_i32(DREG(ext, 12), QREG_CC_Z);
2686 tcg_gen_or_i32(QREG_CC_Z, QREG_CC_Z, QREG_CC_N);
2687
2688 tcg_gen_movi_i32(QREG_CC_V, 0);
2689 tcg_gen_movi_i32(QREG_CC_C, 0);
2690
2691 set_cc_op(s, CC_OP_FLAGS);
e6e5906b
PB		 2692 return;
2693 }
d4d79bb1 2694 SRC_EA(env, src1, OS_LONG, 0, NULL);
8be95def
LV		 2695 if (m68k_feature(s->env, M68K_FEATURE_M68000)) {
2696 tcg_gen_movi_i32(QREG_CC_C, 0);
2697 if (sign) {
2698 tcg_gen_muls2_i32(QREG_CC_N, QREG_CC_V, src1, DREG(ext, 12));
2699 /* QREG_CC_V is -(QREG_CC_V != (QREG_CC_N >> 31)) */
2700 tcg_gen_sari_i32(QREG_CC_Z, QREG_CC_N, 31);
2701 tcg_gen_setcond_i32(TCG_COND_NE, QREG_CC_V, QREG_CC_V, QREG_CC_Z);
2702 } else {
2703 tcg_gen_mulu2_i32(QREG_CC_N, QREG_CC_V, src1, DREG(ext, 12));
2704 /* QREG_CC_V is -(QREG_CC_V != 0), use QREG_CC_C as 0 */
2705 tcg_gen_setcond_i32(TCG_COND_NE, QREG_CC_V, QREG_CC_V, QREG_CC_C);
2706 }
2707 tcg_gen_neg_i32(QREG_CC_V, QREG_CC_V);
2708 tcg_gen_mov_i32(DREG(ext, 12), QREG_CC_N);
2709
2710 tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N);
2711
2712 set_cc_op(s, CC_OP_FLAGS);
2713 } else {
2714 /* The upper 32 bits of the product are discarded, so
2715 muls.l and mulu.l are functionally equivalent. */
2716 tcg_gen_mul_i32(DREG(ext, 12), src1, DREG(ext, 12));
2717 gen_logic_cc(s, DREG(ext, 12), OS_LONG);
2718 }
e6e5906b
PB		 2719}
2720
c630e436 2721static void gen_link(DisasContext *s, uint16_t insn, int32_t offset)
e6e5906b 2722{
e1f3808e
PB		 2723 TCGv reg;
2724 TCGv tmp;
e6e5906b 2725
e6e5906b 2726 reg = AREG(insn, 0);
a7812ae4 2727 tmp = tcg_temp_new();
e1f3808e 2728 tcg_gen_subi_i32(tmp, QREG_SP, 4);
0633879f 2729 gen_store(s, OS_LONG, tmp, reg);
c630e436 2730 if ((insn & 7) != 7) {
e1f3808e 2731 tcg_gen_mov_i32(reg, tmp);
c630e436 2732 }
e1f3808e 2733 tcg_gen_addi_i32(QREG_SP, tmp, offset);
c630e436
LV		 2734 tcg_temp_free(tmp);
2735}
2736
2737DISAS_INSN(link)
2738{
2739 int16_t offset;
2740
2741 offset = read_im16(env, s);
2742 gen_link(s, insn, offset);
2743}
2744
2745DISAS_INSN(linkl)
2746{
2747 int32_t offset;
2748
2749 offset = read_im32(env, s);
2750 gen_link(s, insn, offset);
e6e5906b
PB		 2751}
2752
2753DISAS_INSN(unlk)
2754{
e1f3808e
PB		 2755 TCGv src;
2756 TCGv reg;
2757 TCGv tmp;
e6e5906b 2758
a7812ae4 2759 src = tcg_temp_new();
e6e5906b 2760 reg = AREG(insn, 0);
e1f3808e 2761 tcg_gen_mov_i32(src, reg);
0633879f 2762 tmp = gen_load(s, OS_LONG, src, 0);
e1f3808e
PB		 2763 tcg_gen_mov_i32(reg, tmp);
2764 tcg_gen_addi_i32(QREG_SP, src, 4);
2b5e2170 2765 tcg_temp_free(src);
e6e5906b
PB		 2766}
2767
2768DISAS_INSN(nop)
2769{
2770}
2771
18059c9e
LV		 2772DISAS_INSN(rtd)
2773{
2774 TCGv tmp;
2775 int16_t offset = read_im16(env, s);
2776
2777 tmp = gen_load(s, OS_LONG, QREG_SP, 0);
2778 tcg_gen_addi_i32(QREG_SP, QREG_SP, offset + 4);
2779 gen_jmp(s, tmp);
2780}
2781
e6e5906b
PB		 2782DISAS_INSN(rts)
2783{
e1f3808e 2784 TCGv tmp;
e6e5906b 2785
0633879f 2786 tmp = gen_load(s, OS_LONG, QREG_SP, 0);
e1f3808e 2787 tcg_gen_addi_i32(QREG_SP, QREG_SP, 4);
e6e5906b
PB		 2788 gen_jmp(s, tmp);
2789}
2790
2791DISAS_INSN(jump)
2792{
e1f3808e 2793 TCGv tmp;
e6e5906b
PB		 2794
2795 /* Load the target address first to ensure correct exception
2796 behavior. */
d4d79bb1 2797 tmp = gen_lea(env, s, insn, OS_LONG);
e1f3808e 2798 if (IS_NULL_QREG(tmp)) {
510ff0b7
PB		 2799 gen_addr_fault(s);
2800 return;
2801 }
e6e5906b
PB		 2802 if ((insn & 0x40) == 0) {
2803 /* jsr */
351326a6 2804 gen_push(s, tcg_const_i32(s->pc));
e6e5906b
PB		 2805 }
2806 gen_jmp(s, tmp);
2807}
2808
2809DISAS_INSN(addsubq)
2810{
8a370c6c 2811 TCGv src;
e1f3808e 2812 TCGv dest;
8a370c6c
LV		 2813 TCGv val;
2814 int imm;
e1f3808e 2815 TCGv addr;
8a370c6c 2816 int opsize;
e6e5906b 2817
8a370c6c
LV		 2818 if ((insn & 070) == 010) {
2819 /* Operation on address register is always long. */
2820 opsize = OS_LONG;
2821 } else {
2822 opsize = insn_opsize(insn);
2823 }
2824 SRC_EA(env, src, opsize, 1, &addr);
2825 imm = (insn >> 9) & 7;
2826 if (imm == 0) {
2827 imm = 8;
2828 }
2829 val = tcg_const_i32(imm);
a7812ae4 2830 dest = tcg_temp_new();
8a370c6c 2831 tcg_gen_mov_i32(dest, src);
e6e5906b
PB		 2832 if ((insn & 0x38) == 0x08) {
2833 /* Don't update condition codes if the destination is an
2834 address register. */
2835 if (insn & 0x0100) {
8a370c6c 2836 tcg_gen_sub_i32(dest, dest, val);
e6e5906b 2837 } else {
8a370c6c 2838 tcg_gen_add_i32(dest, dest, val);
e6e5906b
PB		 2839 }
2840 } else {
2841 if (insn & 0x0100) {
8a370c6c
LV		 2842 tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, dest, val);
2843 tcg_gen_sub_i32(dest, dest, val);
2844 set_cc_op(s, CC_OP_SUBB + opsize);
e6e5906b 2845 } else {
8a370c6c
LV		 2846 tcg_gen_add_i32(dest, dest, val);
2847 tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, dest, val);
2848 set_cc_op(s, CC_OP_ADDB + opsize);
e6e5906b 2849 }
8a370c6c 2850 gen_update_cc_add(dest, val, opsize);
e6e5906b 2851 }
2b5e2170 2852 tcg_temp_free(val);
8a370c6c 2853 DEST_EA(env, insn, opsize, dest, &addr);
2b5e2170 2854 tcg_temp_free(dest);
e6e5906b
PB		 2855}
2856
2857DISAS_INSN(tpf)
2858{
2859 switch (insn & 7) {
2860 case 2: /* One extension word. */
2861 s->pc += 2;
2862 break;
2863 case 3: /* Two extension words. */
2864 s->pc += 4;
2865 break;
2866 case 4: /* No extension words. */
2867 break;
2868 default:
d4d79bb1 2869 disas_undef(env, s, insn);
e6e5906b
PB		 2870 }
2871}
2872
2873DISAS_INSN(branch)
2874{
2875 int32_t offset;
2876 uint32_t base;
2877 int op;
42a268c2 2878 TCGLabel *l1;
3b46e624 2879
e6e5906b
PB		 2880 base = s->pc;
2881 op = (insn >> 8) & 0xf;
2882 offset = (int8_t)insn;
2883 if (offset == 0) {
28b68cd7 2884 offset = (int16_t)read_im16(env, s);
e6e5906b 2885 } else if (offset == -1) {
d4d79bb1 2886 offset = read_im32(env, s);
e6e5906b
PB		 2887 }
2888 if (op == 1) {
2889 /* bsr */
351326a6 2890 gen_push(s, tcg_const_i32(s->pc));
e6e5906b 2891 }
e6e5906b
PB		 2892 if (op > 1) {
2893 /* Bcc */
2894 l1 = gen_new_label();
2895 gen_jmpcc(s, ((insn >> 8) & 0xf) ^ 1, l1);
2896 gen_jmp_tb(s, 1, base + offset);
2897 gen_set_label(l1);
2898 gen_jmp_tb(s, 0, s->pc);
2899 } else {
2900 /* Unconditional branch. */
2901 gen_jmp_tb(s, 0, base + offset);
2902 }
2903}
2904
2905DISAS_INSN(moveq)
2906{
2b5e2170
LV		 2907 tcg_gen_movi_i32(DREG(insn, 9), (int8_t)insn);
2908 gen_logic_cc(s, DREG(insn, 9), OS_LONG);
e6e5906b
PB		 2909}
2910
2911DISAS_INSN(mvzs)
2912{
2913 int opsize;
e1f3808e
PB		 2914 TCGv src;
2915 TCGv reg;
e6e5906b
PB		 2916
2917 if (insn & 0x40)
2918 opsize = OS_WORD;
2919 else
2920 opsize = OS_BYTE;
d4d79bb1 2921 SRC_EA(env, src, opsize, (insn & 0x80) == 0, NULL);
e6e5906b 2922 reg = DREG(insn, 9);
e1f3808e 2923 tcg_gen_mov_i32(reg, src);
5dbb6784 2924 gen_logic_cc(s, src, opsize);
e6e5906b
PB		 2925}
2926
2927DISAS_INSN(or)
2928{
e1f3808e
PB		 2929 TCGv reg;
2930 TCGv dest;
2931 TCGv src;
2932 TCGv addr;
020a4659 2933 int opsize;
e6e5906b 2934
020a4659
LV		 2935 opsize = insn_opsize(insn);
2936 reg = gen_extend(DREG(insn, 9), opsize, 0);
a7812ae4 2937 dest = tcg_temp_new();
e6e5906b 2938 if (insn & 0x100) {
020a4659 2939 SRC_EA(env, src, opsize, 0, &addr);
e1f3808e 2940 tcg_gen_or_i32(dest, src, reg);
020a4659 2941 DEST_EA(env, insn, opsize, dest, &addr);
e6e5906b 2942 } else {
020a4659 2943 SRC_EA(env, src, opsize, 0, NULL);
e1f3808e 2944 tcg_gen_or_i32(dest, src, reg);
020a4659 2945 gen_partset_reg(opsize, DREG(insn, 9), dest);
e6e5906b 2946 }
020a4659 2947 gen_logic_cc(s, dest, opsize);
2b5e2170 2948 tcg_temp_free(dest);
e6e5906b
PB		 2949}
2950
2951DISAS_INSN(suba)
2952{
e1f3808e
PB		 2953 TCGv src;
2954 TCGv reg;
e6e5906b 2955
415f4b62 2956 SRC_EA(env, src, (insn & 0x100) ? OS_LONG : OS_WORD, 1, NULL);
e6e5906b 2957 reg = AREG(insn, 9);
e1f3808e 2958 tcg_gen_sub_i32(reg, reg, src);
e6e5906b
PB		 2959}
2960
a665a820 2961static inline void gen_subx(DisasContext *s, TCGv src, TCGv dest, int opsize)
e6e5906b 2962{
a665a820
RH		 2963 TCGv tmp;
2964
2965 gen_flush_flags(s); /* compute old Z */
2966
2967 /* Perform substract with borrow.
2968 * (X, N) = dest - (src + X);
2969 */
2970
2971 tmp = tcg_const_i32(0);
2972 tcg_gen_add2_i32(QREG_CC_N, QREG_CC_X, src, tmp, QREG_CC_X, tmp);
2973 tcg_gen_sub2_i32(QREG_CC_N, QREG_CC_X, dest, tmp, QREG_CC_N, QREG_CC_X);
2974 gen_ext(QREG_CC_N, QREG_CC_N, opsize, 1);
2975 tcg_gen_andi_i32(QREG_CC_X, QREG_CC_X, 1);
2976
2977 /* Compute signed-overflow for substract. */
2978
2979 tcg_gen_xor_i32(QREG_CC_V, QREG_CC_N, dest);
2980 tcg_gen_xor_i32(tmp, dest, src);
2981 tcg_gen_and_i32(QREG_CC_V, QREG_CC_V, tmp);
2982 tcg_temp_free(tmp);
2983
2984 /* Copy the rest of the results into place. */
2985 tcg_gen_or_i32(QREG_CC_Z, QREG_CC_Z, QREG_CC_N); /* !Z is sticky */
2986 tcg_gen_mov_i32(QREG_CC_C, QREG_CC_X);
2987
2988 set_cc_op(s, CC_OP_FLAGS);
2989
2990 /* result is in QREG_CC_N */
2991}
2992
2993DISAS_INSN(subx_reg)
2994{
2995 TCGv dest;
e1f3808e 2996 TCGv src;
a665a820 2997 int opsize;
e6e5906b 2998
a665a820
RH		 2999 opsize = insn_opsize(insn);
3000
3001 src = gen_extend(DREG(insn, 0), opsize, 1);
3002 dest = gen_extend(DREG(insn, 9), opsize, 1);
3003
3004 gen_subx(s, src, dest, opsize);
3005
3006 gen_partset_reg(opsize, DREG(insn, 9), QREG_CC_N);
3007}
3008
3009DISAS_INSN(subx_mem)
3010{
3011 TCGv src;
3012 TCGv addr_src;
3013 TCGv dest;
3014 TCGv addr_dest;
3015 int opsize;
3016
3017 opsize = insn_opsize(insn);
3018
3019 addr_src = AREG(insn, 0);
3020 tcg_gen_subi_i32(addr_src, addr_src, opsize);
3021 src = gen_load(s, opsize, addr_src, 1);
3022
3023 addr_dest = AREG(insn, 9);
3024 tcg_gen_subi_i32(addr_dest, addr_dest, opsize);
3025 dest = gen_load(s, opsize, addr_dest, 1);
3026
3027 gen_subx(s, src, dest, opsize);
3028
3029 gen_store(s, opsize, addr_dest, QREG_CC_N);
e6e5906b
PB		 3030}
3031
3032DISAS_INSN(mov3q)
3033{
e1f3808e 3034 TCGv src;
e6e5906b
PB		 3035 int val;
3036
3037 val = (insn >> 9) & 7;
3038 if (val == 0)
3039 val = -1;
351326a6 3040 src = tcg_const_i32(val);
5dbb6784 3041 gen_logic_cc(s, src, OS_LONG);
d4d79bb1 3042 DEST_EA(env, insn, OS_LONG, src, NULL);
2b5e2170 3043 tcg_temp_free(src);
e6e5906b
PB		 3044}
3045
3046DISAS_INSN(cmp)
3047{
e1f3808e
PB		 3048 TCGv src;
3049 TCGv reg;
e6e5906b
PB		 3050 int opsize;
3051
5dbb6784 3052 opsize = insn_opsize(insn);
ff99b952
LV		 3053 SRC_EA(env, src, opsize, 1, NULL);
3054 reg = gen_extend(DREG(insn, 9), opsize, 1);
3055 gen_update_cc_cmp(s, reg, src, opsize);
e6e5906b
PB		 3056}
3057
3058DISAS_INSN(cmpa)
3059{
3060 int opsize;
e1f3808e
PB		 3061 TCGv src;
3062 TCGv reg;
e6e5906b
PB		 3063
3064 if (insn & 0x100) {
3065 opsize = OS_LONG;
3066 } else {
3067 opsize = OS_WORD;
3068 }
d4d79bb1 3069 SRC_EA(env, src, opsize, 1, NULL);
e6e5906b 3070 reg = AREG(insn, 9);
5436c29d 3071 gen_update_cc_cmp(s, reg, src, OS_LONG);
e6e5906b
PB		 3072}
3073
817af1c7
LV		 3074DISAS_INSN(cmpm)
3075{
3076 int opsize = insn_opsize(insn);
3077 TCGv src, dst;
3078
3079 /* Post-increment load (mode 3) from Ay. */
3080 src = gen_ea_mode(env, s, 3, REG(insn, 0), opsize,
3081 NULL_QREG, NULL, EA_LOADS);
3082 /* Post-increment load (mode 3) from Ax. */
3083 dst = gen_ea_mode(env, s, 3, REG(insn, 9), opsize,
3084 NULL_QREG, NULL, EA_LOADS);
3085
3086 gen_update_cc_cmp(s, dst, src, opsize);
3087}
3088
e6e5906b
PB		 3089DISAS_INSN(eor)
3090{
e1f3808e 3091 TCGv src;
e1f3808e
PB		 3092 TCGv dest;
3093 TCGv addr;
eec37aec 3094 int opsize;
e6e5906b 3095
eec37aec
LV		 3096 opsize = insn_opsize(insn);
3097
3098 SRC_EA(env, src, opsize, 0, &addr);
a7812ae4 3099 dest = tcg_temp_new();
eec37aec
LV		 3100 tcg_gen_xor_i32(dest, src, DREG(insn, 9));
3101 gen_logic_cc(s, dest, opsize);
3102 DEST_EA(env, insn, opsize, dest, &addr);
2b5e2170 3103 tcg_temp_free(dest);
e6e5906b
PB		 3104}
3105
29cf437d
LV		 3106static void do_exg(TCGv reg1, TCGv reg2)
3107{
3108 TCGv temp = tcg_temp_new();
3109 tcg_gen_mov_i32(temp, reg1);
3110 tcg_gen_mov_i32(reg1, reg2);
3111 tcg_gen_mov_i32(reg2, temp);
3112 tcg_temp_free(temp);
3113}
3114
c090c97d 3115DISAS_INSN(exg_dd)
29cf437d
LV		 3116{
3117 /* exchange Dx and Dy */
3118 do_exg(DREG(insn, 9), DREG(insn, 0));
3119}
3120
c090c97d 3121DISAS_INSN(exg_aa)
29cf437d
LV		 3122{
3123 /* exchange Ax and Ay */
3124 do_exg(AREG(insn, 9), AREG(insn, 0));
3125}
3126
3127DISAS_INSN(exg_da)
3128{
3129 /* exchange Dx and Ay */
3130 do_exg(DREG(insn, 9), AREG(insn, 0));
3131}
3132
e6e5906b
PB		 3133DISAS_INSN(and)
3134{
e1f3808e
PB		 3135 TCGv src;
3136 TCGv reg;
3137 TCGv dest;
3138 TCGv addr;
52dc23c5 3139 int opsize;
e6e5906b 3140
a7812ae4 3141 dest = tcg_temp_new();
52dc23c5
LV		 3142
3143 opsize = insn_opsize(insn);
3144 reg = DREG(insn, 9);
e6e5906b 3145 if (insn & 0x100) {
52dc23c5 3146 SRC_EA(env, src, opsize, 0, &addr);
e1f3808e 3147 tcg_gen_and_i32(dest, src, reg);
52dc23c5 3148 DEST_EA(env, insn, opsize, dest, &addr);
e6e5906b 3149 } else {
52dc23c5 3150 SRC_EA(env, src, opsize, 0, NULL);
e1f3808e 3151 tcg_gen_and_i32(dest, src, reg);
52dc23c5 3152 gen_partset_reg(opsize, reg, dest);
e6e5906b 3153 }
52dc23c5 3154 gen_logic_cc(s, dest, opsize);
2b5e2170 3155 tcg_temp_free(dest);
e6e5906b
PB		 3156}
3157
3158DISAS_INSN(adda)
3159{
e1f3808e
PB		 3160 TCGv src;
3161 TCGv reg;
e6e5906b 3162
415f4b62 3163 SRC_EA(env, src, (insn & 0x100) ? OS_LONG : OS_WORD, 1, NULL);
e6e5906b 3164 reg = AREG(insn, 9);
e1f3808e 3165 tcg_gen_add_i32(reg, reg, src);
e6e5906b
PB		 3166}
3167
a665a820 3168static inline void gen_addx(DisasContext *s, TCGv src, TCGv dest, int opsize)
e6e5906b 3169{
a665a820
RH		 3170 TCGv tmp;
3171
3172 gen_flush_flags(s); /* compute old Z */
3173
3174 /* Perform addition with carry.
3175 * (X, N) = src + dest + X;
3176 */
3177
3178 tmp = tcg_const_i32(0);
3179 tcg_gen_add2_i32(QREG_CC_N, QREG_CC_X, QREG_CC_X, tmp, dest, tmp);
3180 tcg_gen_add2_i32(QREG_CC_N, QREG_CC_X, QREG_CC_N, QREG_CC_X, src, tmp);
3181 gen_ext(QREG_CC_N, QREG_CC_N, opsize, 1);
3182
3183 /* Compute signed-overflow for addition. */
3184
3185 tcg_gen_xor_i32(QREG_CC_V, QREG_CC_N, src);
3186 tcg_gen_xor_i32(tmp, dest, src);
3187 tcg_gen_andc_i32(QREG_CC_V, QREG_CC_V, tmp);
3188 tcg_temp_free(tmp);
3189
3190 /* Copy the rest of the results into place. */
3191 tcg_gen_or_i32(QREG_CC_Z, QREG_CC_Z, QREG_CC_N); /* !Z is sticky */
3192 tcg_gen_mov_i32(QREG_CC_C, QREG_CC_X);
3193
3194 set_cc_op(s, CC_OP_FLAGS);
3195
3196 /* result is in QREG_CC_N */
3197}
3198
3199DISAS_INSN(addx_reg)
3200{
3201 TCGv dest;
e1f3808e 3202 TCGv src;
a665a820 3203 int opsize;
e6e5906b 3204
a665a820
RH		 3205 opsize = insn_opsize(insn);
3206
3207 dest = gen_extend(DREG(insn, 9), opsize, 1);
3208 src = gen_extend(DREG(insn, 0), opsize, 1);
3209
3210 gen_addx(s, src, dest, opsize);
3211
3212 gen_partset_reg(opsize, DREG(insn, 9), QREG_CC_N);
3213}
3214
3215DISAS_INSN(addx_mem)
3216{
3217 TCGv src;
3218 TCGv addr_src;
3219 TCGv dest;
3220 TCGv addr_dest;
3221 int opsize;
3222
3223 opsize = insn_opsize(insn);
3224
3225 addr_src = AREG(insn, 0);
3226 tcg_gen_subi_i32(addr_src, addr_src, opsize_bytes(opsize));
3227 src = gen_load(s, opsize, addr_src, 1);
3228
3229 addr_dest = AREG(insn, 9);
3230 tcg_gen_subi_i32(addr_dest, addr_dest, opsize_bytes(opsize));
3231 dest = gen_load(s, opsize, addr_dest, 1);
3232
3233 gen_addx(s, src, dest, opsize);
3234
3235 gen_store(s, opsize, addr_dest, QREG_CC_N);
e6e5906b
PB		 3236}
3237
367790cc 3238static inline void shift_im(DisasContext *s, uint16_t insn, int opsize)
e6e5906b 3239{
367790cc
RH		 3240 int count = (insn >> 9) & 7;
3241 int logical = insn & 8;
3242 int left = insn & 0x100;
3243 int bits = opsize_bytes(opsize) * 8;
3244 TCGv reg = gen_extend(DREG(insn, 0), opsize, !logical);
3245
3246 if (count == 0) {
3247 count = 8;
3248 }
3249
3250 tcg_gen_movi_i32(QREG_CC_V, 0);
3251 if (left) {
3252 tcg_gen_shri_i32(QREG_CC_C, reg, bits - count);
3253 tcg_gen_shli_i32(QREG_CC_N, reg, count);
3254
3255 /* Note that ColdFire always clears V (done above),
3256 while M68000 sets if the most significant bit is changed at
3257 any time during the shift operation */
3258 if (!logical && m68k_feature(s->env, M68K_FEATURE_M68000)) {
3259 /* if shift count >= bits, V is (reg != 0) */
3260 if (count >= bits) {
3261 tcg_gen_setcond_i32(TCG_COND_NE, QREG_CC_V, reg, QREG_CC_V);
3262 } else {
3263 TCGv t0 = tcg_temp_new();
3264 tcg_gen_sari_i32(QREG_CC_V, reg, bits - 1);
3265 tcg_gen_sari_i32(t0, reg, bits - count - 1);
3266 tcg_gen_setcond_i32(TCG_COND_NE, QREG_CC_V, QREG_CC_V, t0);
3267 tcg_temp_free(t0);
3268 }
3269 tcg_gen_neg_i32(QREG_CC_V, QREG_CC_V);
3270 }
3271 } else {
3272 tcg_gen_shri_i32(QREG_CC_C, reg, count - 1);
3273 if (logical) {
3274 tcg_gen_shri_i32(QREG_CC_N, reg, count);
3275 } else {
3276 tcg_gen_sari_i32(QREG_CC_N, reg, count);
3277 }
3278 }
3279
3280 gen_ext(QREG_CC_N, QREG_CC_N, opsize, 1);
3281 tcg_gen_andi_i32(QREG_CC_C, QREG_CC_C, 1);
3282 tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N);
3283 tcg_gen_mov_i32(QREG_CC_X, QREG_CC_C);
e6e5906b 3284
367790cc 3285 gen_partset_reg(opsize, DREG(insn, 0), QREG_CC_N);
620c6cf6 3286 set_cc_op(s, CC_OP_FLAGS);
367790cc 3287}
620c6cf6 3288
367790cc
RH		 3289static inline void shift_reg(DisasContext *s, uint16_t insn, int opsize)
3290{
3291 int logical = insn & 8;
3292 int left = insn & 0x100;
3293 int bits = opsize_bytes(opsize) * 8;
3294 TCGv reg = gen_extend(DREG(insn, 0), opsize, !logical);
3295 TCGv s32;
3296 TCGv_i64 t64, s64;
3297
3298 t64 = tcg_temp_new_i64();
3299 s64 = tcg_temp_new_i64();
3300 s32 = tcg_temp_new();
3301
3302 /* Note that m68k truncates the shift count modulo 64, not 32.
3303 In addition, a 64-bit shift makes it easy to find "the last
3304 bit shifted out", for the carry flag. */
3305 tcg_gen_andi_i32(s32, DREG(insn, 9), 63);
3306 tcg_gen_extu_i32_i64(s64, s32);
3307 tcg_gen_extu_i32_i64(t64, reg);
3308
3309 /* Optimistically set V=0. Also used as a zero source below. */
3310 tcg_gen_movi_i32(QREG_CC_V, 0);
3311 if (left) {
3312 tcg_gen_shl_i64(t64, t64, s64);
3313
3314 if (opsize == OS_LONG) {
3315 tcg_gen_extr_i64_i32(QREG_CC_N, QREG_CC_C, t64);
3316 /* Note that C=0 if shift count is 0, and we get that for free. */
3317 } else {
3318 TCGv zero = tcg_const_i32(0);
3319 tcg_gen_extrl_i64_i32(QREG_CC_N, t64);
3320 tcg_gen_shri_i32(QREG_CC_C, QREG_CC_N, bits);
3321 tcg_gen_movcond_i32(TCG_COND_EQ, QREG_CC_C,
3322 s32, zero, zero, QREG_CC_C);
3323 tcg_temp_free(zero);
3324 }
3325 tcg_gen_andi_i32(QREG_CC_C, QREG_CC_C, 1);
3326
3327 /* X = C, but only if the shift count was non-zero. */
3328 tcg_gen_movcond_i32(TCG_COND_NE, QREG_CC_X, s32, QREG_CC_V,
3329 QREG_CC_C, QREG_CC_X);
3330
3331 /* M68000 sets V if the most significant bit is changed at
3332 * any time during the shift operation. Do this via creating
3333 * an extension of the sign bit, comparing, and discarding
3334 * the bits below the sign bit. I.e.
3335 * int64_t s = (intN_t)reg;
3336 * int64_t t = (int64_t)(intN_t)reg << count;
3337 * V = ((s ^ t) & (-1 << (bits - 1))) != 0
3338 */
3339 if (!logical && m68k_feature(s->env, M68K_FEATURE_M68000)) {
3340 TCGv_i64 tt = tcg_const_i64(32);
3341 /* if shift is greater than 32, use 32 */
3342 tcg_gen_movcond_i64(TCG_COND_GT, s64, s64, tt, tt, s64);
3343 tcg_temp_free_i64(tt);
3344 /* Sign extend the input to 64 bits; re-do the shift. */
3345 tcg_gen_ext_i32_i64(t64, reg);
3346 tcg_gen_shl_i64(s64, t64, s64);
3347 /* Clear all bits that are unchanged. */
3348 tcg_gen_xor_i64(t64, t64, s64);
3349 /* Ignore the bits below the sign bit. */
3350 tcg_gen_andi_i64(t64, t64, -1ULL << (bits - 1));
3351 /* If any bits remain set, we have overflow. */
3352 tcg_gen_setcondi_i64(TCG_COND_NE, t64, t64, 0);
3353 tcg_gen_extrl_i64_i32(QREG_CC_V, t64);
3354 tcg_gen_neg_i32(QREG_CC_V, QREG_CC_V);
3355 }
e6e5906b 3356 } else {
367790cc
RH		 3357 tcg_gen_shli_i64(t64, t64, 32);
3358 if (logical) {
3359 tcg_gen_shr_i64(t64, t64, s64);
e6e5906b 3360 } else {
367790cc 3361 tcg_gen_sar_i64(t64, t64, s64);
e6e5906b 3362 }
367790cc
RH		 3363 tcg_gen_extr_i64_i32(QREG_CC_C, QREG_CC_N, t64);
3364
3365 /* Note that C=0 if shift count is 0, and we get that for free. */
3366 tcg_gen_shri_i32(QREG_CC_C, QREG_CC_C, 31);
3367
3368 /* X = C, but only if the shift count was non-zero. */
3369 tcg_gen_movcond_i32(TCG_COND_NE, QREG_CC_X, s32, QREG_CC_V,
3370 QREG_CC_C, QREG_CC_X);
e6e5906b 3371 }
367790cc
RH		 3372 gen_ext(QREG_CC_N, QREG_CC_N, opsize, 1);
3373 tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N);
3374
3375 tcg_temp_free(s32);
3376 tcg_temp_free_i64(s64);
3377 tcg_temp_free_i64(t64);
3378
3379 /* Write back the result. */
3380 gen_partset_reg(opsize, DREG(insn, 0), QREG_CC_N);
3381 set_cc_op(s, CC_OP_FLAGS);
3382}
3383
3384DISAS_INSN(shift8_im)
3385{
3386 shift_im(s, insn, OS_BYTE);
3387}
3388
3389DISAS_INSN(shift16_im)
3390{
3391 shift_im(s, insn, OS_WORD);
3392}
3393
3394DISAS_INSN(shift_im)
3395{
3396 shift_im(s, insn, OS_LONG);
3397}
3398
3399DISAS_INSN(shift8_reg)
3400{
3401 shift_reg(s, insn, OS_BYTE);
3402}
3403
3404DISAS_INSN(shift16_reg)
3405{
3406 shift_reg(s, insn, OS_WORD);
e6e5906b
PB		 3407}
3408
3409DISAS_INSN(shift_reg)
3410{
367790cc
RH		 3411 shift_reg(s, insn, OS_LONG);
3412}
e6e5906b 3413
367790cc
RH		 3414DISAS_INSN(shift_mem)
3415{
3416 int logical = insn & 8;
3417 int left = insn & 0x100;
3418 TCGv src;
3419 TCGv addr;
3420
3421 SRC_EA(env, src, OS_WORD, !logical, &addr);
3422 tcg_gen_movi_i32(QREG_CC_V, 0);
3423 if (left) {
3424 tcg_gen_shri_i32(QREG_CC_C, src, 15);
3425 tcg_gen_shli_i32(QREG_CC_N, src, 1);
3426
3427 /* Note that ColdFire always clears V,
3428 while M68000 sets if the most significant bit is changed at
3429 any time during the shift operation */
3430 if (!logical && m68k_feature(s->env, M68K_FEATURE_M68000)) {
3431 src = gen_extend(src, OS_WORD, 1);
3432 tcg_gen_xor_i32(QREG_CC_V, QREG_CC_N, src);
3433 }
e6e5906b 3434 } else {
367790cc
RH		 3435 tcg_gen_mov_i32(QREG_CC_C, src);
3436 if (logical) {
3437 tcg_gen_shri_i32(QREG_CC_N, src, 1);
e6e5906b 3438 } else {
367790cc 3439 tcg_gen_sari_i32(QREG_CC_N, src, 1);
e6e5906b
PB		 3440 }
3441 }
367790cc
RH		 3442
3443 gen_ext(QREG_CC_N, QREG_CC_N, OS_WORD, 1);
3444 tcg_gen_andi_i32(QREG_CC_C, QREG_CC_C, 1);
3445 tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N);
3446 tcg_gen_mov_i32(QREG_CC_X, QREG_CC_C);
3447
3448 DEST_EA(env, insn, OS_WORD, QREG_CC_N, &addr);
620c6cf6 3449 set_cc_op(s, CC_OP_FLAGS);
e6e5906b
PB		 3450}
3451
0194cf31
LV		 3452static void rotate(TCGv reg, TCGv shift, int left, int size)
3453{
3454 switch (size) {
3455 case 8:
3456 /* Replicate the 8-bit input so that a 32-bit rotate works. */
3457 tcg_gen_ext8u_i32(reg, reg);
3458 tcg_gen_muli_i32(reg, reg, 0x01010101);
3459 goto do_long;
3460 case 16:
3461 /* Replicate the 16-bit input so that a 32-bit rotate works. */
3462 tcg_gen_deposit_i32(reg, reg, reg, 16, 16);
3463 goto do_long;
3464 do_long:
3465 default:
3466 if (left) {
3467 tcg_gen_rotl_i32(reg, reg, shift);
3468 } else {
3469 tcg_gen_rotr_i32(reg, reg, shift);
3470 }
3471 }
3472
3473 /* compute flags */
3474
3475 switch (size) {
3476 case 8:
3477 tcg_gen_ext8s_i32(reg, reg);
3478 break;
3479 case 16:
3480 tcg_gen_ext16s_i32(reg, reg);
3481 break;
3482 default:
3483 break;
3484 }
3485
3486 /* QREG_CC_X is not affected */
3487
3488 tcg_gen_mov_i32(QREG_CC_N, reg);
3489 tcg_gen_mov_i32(QREG_CC_Z, reg);
3490
3491 if (left) {
3492 tcg_gen_andi_i32(QREG_CC_C, reg, 1);
3493 } else {
3494 tcg_gen_shri_i32(QREG_CC_C, reg, 31);
3495 }
3496
3497 tcg_gen_movi_i32(QREG_CC_V, 0); /* always cleared */
3498}
3499
3500static void rotate_x_flags(TCGv reg, TCGv X, int size)
3501{
3502 switch (size) {
3503 case 8:
3504 tcg_gen_ext8s_i32(reg, reg);
3505 break;
3506 case 16:
3507 tcg_gen_ext16s_i32(reg, reg);
3508 break;
3509 default:
3510 break;
3511 }
3512 tcg_gen_mov_i32(QREG_CC_N, reg);
3513 tcg_gen_mov_i32(QREG_CC_Z, reg);
3514 tcg_gen_mov_i32(QREG_CC_X, X);
3515 tcg_gen_mov_i32(QREG_CC_C, X);
3516 tcg_gen_movi_i32(QREG_CC_V, 0);
3517}
3518
3519/* Result of rotate_x() is valid if 0 <= shift <= size */
3520static TCGv rotate_x(TCGv reg, TCGv shift, int left, int size)
3521{
3522 TCGv X, shl, shr, shx, sz, zero;
3523
3524 sz = tcg_const_i32(size);
3525
3526 shr = tcg_temp_new();
3527 shl = tcg_temp_new();
3528 shx = tcg_temp_new();
3529 if (left) {
3530 tcg_gen_mov_i32(shl, shift); /* shl = shift */
3531 tcg_gen_movi_i32(shr, size + 1);
3532 tcg_gen_sub_i32(shr, shr, shift); /* shr = size + 1 - shift */
3533 tcg_gen_subi_i32(shx, shift, 1); /* shx = shift - 1 */
3534 /* shx = shx < 0 ? size : shx; */
3535 zero = tcg_const_i32(0);
3536 tcg_gen_movcond_i32(TCG_COND_LT, shx, shx, zero, sz, shx);
3537 tcg_temp_free(zero);
3538 } else {
3539 tcg_gen_mov_i32(shr, shift); /* shr = shift */
3540 tcg_gen_movi_i32(shl, size + 1);
3541 tcg_gen_sub_i32(shl, shl, shift); /* shl = size + 1 - shift */
3542 tcg_gen_sub_i32(shx, sz, shift); /* shx = size - shift */
3543 }
3544
3545 /* reg = (reg << shl) | (reg >> shr) | (x << shx); */
3546
3547 tcg_gen_shl_i32(shl, reg, shl);
3548 tcg_gen_shr_i32(shr, reg, shr);
3549 tcg_gen_or_i32(reg, shl, shr);
3550 tcg_temp_free(shl);
3551 tcg_temp_free(shr);
3552 tcg_gen_shl_i32(shx, QREG_CC_X, shx);
3553 tcg_gen_or_i32(reg, reg, shx);
3554 tcg_temp_free(shx);
3555
3556 /* X = (reg >> size) & 1 */
3557
3558 X = tcg_temp_new();
3559 tcg_gen_shr_i32(X, reg, sz);
3560 tcg_gen_andi_i32(X, X, 1);
3561 tcg_temp_free(sz);
3562
3563 return X;
3564}
3565
3566/* Result of rotate32_x() is valid if 0 <= shift < 33 */
3567static TCGv rotate32_x(TCGv reg, TCGv shift, int left)
3568{
3569 TCGv_i64 t0, shift64;
3570 TCGv X, lo, hi, zero;
3571
3572 shift64 = tcg_temp_new_i64();
3573 tcg_gen_extu_i32_i64(shift64, shift);
3574
3575 t0 = tcg_temp_new_i64();
3576
3577 X = tcg_temp_new();
3578 lo = tcg_temp_new();
3579 hi = tcg_temp_new();
3580
3581 if (left) {
3582 /* create [reg:X:..] */
3583
3584 tcg_gen_shli_i32(lo, QREG_CC_X, 31);
3585 tcg_gen_concat_i32_i64(t0, lo, reg);
3586
3587 /* rotate */
3588
3589 tcg_gen_rotl_i64(t0, t0, shift64);
3590 tcg_temp_free_i64(shift64);
3591
3592 /* result is [reg:..:reg:X] */
3593
3594 tcg_gen_extr_i64_i32(lo, hi, t0);
3595 tcg_gen_andi_i32(X, lo, 1);
3596
3597 tcg_gen_shri_i32(lo, lo, 1);
3598 } else {
3599 /* create [..:X:reg] */
3600
3601 tcg_gen_concat_i32_i64(t0, reg, QREG_CC_X);
3602
3603 tcg_gen_rotr_i64(t0, t0, shift64);
3604 tcg_temp_free_i64(shift64);
3605
3606 /* result is value: [X:reg:..:reg] */
3607
3608 tcg_gen_extr_i64_i32(lo, hi, t0);
3609
3610 /* extract X */
3611
3612 tcg_gen_shri_i32(X, hi, 31);
3613
3614 /* extract result */
3615
3616 tcg_gen_shli_i32(hi, hi, 1);
3617 }
3618 tcg_temp_free_i64(t0);
3619 tcg_gen_or_i32(lo, lo, hi);
3620 tcg_temp_free(hi);
3621
3622 /* if shift == 0, register and X are not affected */
3623
3624 zero = tcg_const_i32(0);
3625 tcg_gen_movcond_i32(TCG_COND_EQ, X, shift, zero, QREG_CC_X, X);
3626 tcg_gen_movcond_i32(TCG_COND_EQ, reg, shift, zero, reg, lo);
3627 tcg_temp_free(zero);
3628 tcg_temp_free(lo);
3629
3630 return X;
3631}
3632
3633DISAS_INSN(rotate_im)
3634{
3635 TCGv shift;
3636 int tmp;
3637 int left = (insn & 0x100);
3638
3639 tmp = (insn >> 9) & 7;
3640 if (tmp == 0) {
3641 tmp = 8;
3642 }
3643
3644 shift = tcg_const_i32(tmp);
3645 if (insn & 8) {
3646 rotate(DREG(insn, 0), shift, left, 32);
3647 } else {
3648 TCGv X = rotate32_x(DREG(insn, 0), shift, left);
3649 rotate_x_flags(DREG(insn, 0), X, 32);
3650 tcg_temp_free(X);
3651 }
3652 tcg_temp_free(shift);
3653
3654 set_cc_op(s, CC_OP_FLAGS);
3655}
3656
3657DISAS_INSN(rotate8_im)
3658{
3659 int left = (insn & 0x100);
3660 TCGv reg;
3661 TCGv shift;
3662 int tmp;
3663
3664 reg = gen_extend(DREG(insn, 0), OS_BYTE, 0);
3665
3666 tmp = (insn >> 9) & 7;
3667 if (tmp == 0) {
3668 tmp = 8;
3669 }
3670
3671 shift = tcg_const_i32(tmp);
3672 if (insn & 8) {
3673 rotate(reg, shift, left, 8);
3674 } else {
3675 TCGv X = rotate_x(reg, shift, left, 8);
3676 rotate_x_flags(reg, X, 8);
3677 tcg_temp_free(X);
3678 }
3679 tcg_temp_free(shift);
3680 gen_partset_reg(OS_BYTE, DREG(insn, 0), reg);
3681 set_cc_op(s, CC_OP_FLAGS);
3682}
3683
3684DISAS_INSN(rotate16_im)
3685{
3686 int left = (insn & 0x100);
3687 TCGv reg;
3688 TCGv shift;
3689 int tmp;
3690
3691 reg = gen_extend(DREG(insn, 0), OS_WORD, 0);
3692 tmp = (insn >> 9) & 7;
3693 if (tmp == 0) {
3694 tmp = 8;
3695 }
3696
3697 shift = tcg_const_i32(tmp);
3698 if (insn & 8) {
3699 rotate(reg, shift, left, 16);
3700 } else {
3701 TCGv X = rotate_x(reg, shift, left, 16);
3702 rotate_x_flags(reg, X, 16);
3703 tcg_temp_free(X);
3704 }
3705 tcg_temp_free(shift);
3706 gen_partset_reg(OS_WORD, DREG(insn, 0), reg);
3707 set_cc_op(s, CC_OP_FLAGS);
3708}
3709
3710DISAS_INSN(rotate_reg)
3711{
3712 TCGv reg;
3713 TCGv src;
3714 TCGv t0, t1;
3715 int left = (insn & 0x100);
3716
3717 reg = DREG(insn, 0);
3718 src = DREG(insn, 9);
3719 /* shift in [0..63] */
3720 t0 = tcg_temp_new();
3721 tcg_gen_andi_i32(t0, src, 63);
3722 t1 = tcg_temp_new_i32();
3723 if (insn & 8) {
3724 tcg_gen_andi_i32(t1, src, 31);
3725 rotate(reg, t1, left, 32);
3726 /* if shift == 0, clear C */
3727 tcg_gen_movcond_i32(TCG_COND_EQ, QREG_CC_C,
3728 t0, QREG_CC_V /* 0 */,
3729 QREG_CC_V /* 0 */, QREG_CC_C);
3730 } else {
3731 TCGv X;
3732 /* modulo 33 */
3733 tcg_gen_movi_i32(t1, 33);
3734 tcg_gen_remu_i32(t1, t0, t1);
3735 X = rotate32_x(DREG(insn, 0), t1, left);
3736 rotate_x_flags(DREG(insn, 0), X, 32);
3737 tcg_temp_free(X);
3738 }
3739 tcg_temp_free(t1);
3740 tcg_temp_free(t0);
3741 set_cc_op(s, CC_OP_FLAGS);
3742}
3743
3744DISAS_INSN(rotate8_reg)
3745{
3746 TCGv reg;
3747 TCGv src;
3748 TCGv t0, t1;
3749 int left = (insn & 0x100);
3750
3751 reg = gen_extend(DREG(insn, 0), OS_BYTE, 0);
3752 src = DREG(insn, 9);
3753 /* shift in [0..63] */
3754 t0 = tcg_temp_new_i32();
3755 tcg_gen_andi_i32(t0, src, 63);
3756 t1 = tcg_temp_new_i32();
3757 if (insn & 8) {
3758 tcg_gen_andi_i32(t1, src, 7);
3759 rotate(reg, t1, left, 8);
3760 /* if shift == 0, clear C */
3761 tcg_gen_movcond_i32(TCG_COND_EQ, QREG_CC_C,
3762 t0, QREG_CC_V /* 0 */,
3763 QREG_CC_V /* 0 */, QREG_CC_C);
3764 } else {
3765 TCGv X;
3766 /* modulo 9 */
3767 tcg_gen_movi_i32(t1, 9);
3768 tcg_gen_remu_i32(t1, t0, t1);
3769 X = rotate_x(reg, t1, left, 8);
3770 rotate_x_flags(reg, X, 8);
3771 tcg_temp_free(X);
3772 }
3773 tcg_temp_free(t1);
3774 tcg_temp_free(t0);
3775 gen_partset_reg(OS_BYTE, DREG(insn, 0), reg);
3776 set_cc_op(s, CC_OP_FLAGS);
3777}
3778
3779DISAS_INSN(rotate16_reg)
3780{
3781 TCGv reg;
3782 TCGv src;
3783 TCGv t0, t1;
3784 int left = (insn & 0x100);
3785
3786 reg = gen_extend(DREG(insn, 0), OS_WORD, 0);
3787 src = DREG(insn, 9);
3788 /* shift in [0..63] */
3789 t0 = tcg_temp_new_i32();
3790 tcg_gen_andi_i32(t0, src, 63);
3791 t1 = tcg_temp_new_i32();
3792 if (insn & 8) {
3793 tcg_gen_andi_i32(t1, src, 15);
3794 rotate(reg, t1, left, 16);
3795 /* if shift == 0, clear C */
3796 tcg_gen_movcond_i32(TCG_COND_EQ, QREG_CC_C,
3797 t0, QREG_CC_V /* 0 */,
3798 QREG_CC_V /* 0 */, QREG_CC_C);
3799 } else {
3800 TCGv X;
3801 /* modulo 17 */
3802 tcg_gen_movi_i32(t1, 17);
3803 tcg_gen_remu_i32(t1, t0, t1);
3804 X = rotate_x(reg, t1, left, 16);
3805 rotate_x_flags(reg, X, 16);
3806 tcg_temp_free(X);
3807 }
3808 tcg_temp_free(t1);
3809 tcg_temp_free(t0);
3810 gen_partset_reg(OS_WORD, DREG(insn, 0), reg);
3811 set_cc_op(s, CC_OP_FLAGS);
3812}
3813
3814DISAS_INSN(rotate_mem)
3815{
3816 TCGv src;
3817 TCGv addr;
3818 TCGv shift;
3819 int left = (insn & 0x100);
3820
3821 SRC_EA(env, src, OS_WORD, 0, &addr);
3822
3823 shift = tcg_const_i32(1);
3824 if (insn & 0x0200) {
3825 rotate(src, shift, left, 16);
3826 } else {
3827 TCGv X = rotate_x(src, shift, left, 16);
3828 rotate_x_flags(src, X, 16);
3829 tcg_temp_free(X);
3830 }
3831 tcg_temp_free(shift);
3832 DEST_EA(env, insn, OS_WORD, src, &addr);
3833 set_cc_op(s, CC_OP_FLAGS);
3834}
3835
ac815f46
RH		 3836DISAS_INSN(bfext_reg)
3837{
3838 int ext = read_im16(env, s);
3839 int is_sign = insn & 0x200;
3840 TCGv src = DREG(insn, 0);
3841 TCGv dst = DREG(ext, 12);
3842 int len = ((extract32(ext, 0, 5) - 1) & 31) + 1;
3843 int ofs = extract32(ext, 6, 5); /* big bit-endian */
3844 int pos = 32 - ofs - len; /* little bit-endian */
3845 TCGv tmp = tcg_temp_new();
3846 TCGv shift;
3847
3848 /* In general, we're going to rotate the field so that it's at the
3849 top of the word and then right-shift by the compliment of the
3850 width to extend the field. */
3851 if (ext & 0x20) {
3852 /* Variable width. */
3853 if (ext & 0x800) {
3854 /* Variable offset. */
3855 tcg_gen_andi_i32(tmp, DREG(ext, 6), 31);
3856 tcg_gen_rotl_i32(tmp, src, tmp);
3857 } else {
3858 tcg_gen_rotli_i32(tmp, src, ofs);
3859 }
3860
3861 shift = tcg_temp_new();
3862 tcg_gen_neg_i32(shift, DREG(ext, 0));
3863 tcg_gen_andi_i32(shift, shift, 31);
3864 tcg_gen_sar_i32(QREG_CC_N, tmp, shift);
3865 if (is_sign) {
3866 tcg_gen_mov_i32(dst, QREG_CC_N);
3867 } else {
3868 tcg_gen_shr_i32(dst, tmp, shift);
3869 }
3870 tcg_temp_free(shift);
3871 } else {
3872 /* Immediate width. */
3873 if (ext & 0x800) {
3874 /* Variable offset */
3875 tcg_gen_andi_i32(tmp, DREG(ext, 6), 31);
3876 tcg_gen_rotl_i32(tmp, src, tmp);
3877 src = tmp;
3878 pos = 32 - len;
3879 } else {
3880 /* Immediate offset. If the field doesn't wrap around the
3881 end of the word, rely on (s)extract completely. */
3882 if (pos < 0) {
3883 tcg_gen_rotli_i32(tmp, src, ofs);
3884 src = tmp;
3885 pos = 32 - len;
3886 }
3887 }
3888
3889 tcg_gen_sextract_i32(QREG_CC_N, src, pos, len);
3890 if (is_sign) {
3891 tcg_gen_mov_i32(dst, QREG_CC_N);
3892 } else {
3893 tcg_gen_extract_i32(dst, src, pos, len);
3894 }
3895 }
3896
3897 tcg_temp_free(tmp);
3898 set_cc_op(s, CC_OP_LOGIC);
3899}
3900
f2224f2c
RH		 3901DISAS_INSN(bfext_mem)
3902{
3903 int ext = read_im16(env, s);
3904 int is_sign = insn & 0x200;
3905 TCGv dest = DREG(ext, 12);
3906 TCGv addr, len, ofs;
3907
3908 addr = gen_lea(env, s, insn, OS_UNSIZED);
3909 if (IS_NULL_QREG(addr)) {
3910 gen_addr_fault(s);
3911 return;
3912 }
3913
3914 if (ext & 0x20) {
3915 len = DREG(ext, 0);
3916 } else {
3917 len = tcg_const_i32(extract32(ext, 0, 5));
3918 }
3919 if (ext & 0x800) {
3920 ofs = DREG(ext, 6);
3921 } else {
3922 ofs = tcg_const_i32(extract32(ext, 6, 5));
3923 }
3924
3925 if (is_sign) {
3926 gen_helper_bfexts_mem(dest, cpu_env, addr, ofs, len);
3927 tcg_gen_mov_i32(QREG_CC_N, dest);
3928 } else {
3929 TCGv_i64 tmp = tcg_temp_new_i64();
3930 gen_helper_bfextu_mem(tmp, cpu_env, addr, ofs, len);
3931 tcg_gen_extr_i64_i32(dest, QREG_CC_N, tmp);
3932 tcg_temp_free_i64(tmp);
3933 }
3934 set_cc_op(s, CC_OP_LOGIC);
3935
3936 if (!(ext & 0x20)) {
3937 tcg_temp_free(len);
3938 }
3939 if (!(ext & 0x800)) {
3940 tcg_temp_free(ofs);
3941 }
3942}
3943
ac815f46
RH		 3944DISAS_INSN(bfop_reg)
3945{
3946 int ext = read_im16(env, s);
3947 TCGv src = DREG(insn, 0);
3948 int len = ((extract32(ext, 0, 5) - 1) & 31) + 1;
3949 int ofs = extract32(ext, 6, 5); /* big bit-endian */
a45f1763
RH		 3950 TCGv mask, tofs, tlen;
3951
3952 TCGV_UNUSED(tofs);
3953 TCGV_UNUSED(tlen);
3954 if ((insn & 0x0f00) == 0x0d00) { /* bfffo */
3955 tofs = tcg_temp_new();
3956 tlen = tcg_temp_new();
3957 }
ac815f46
RH		 3958
3959 if ((ext & 0x820) == 0) {
3960 /* Immediate width and offset. */
3961 uint32_t maski = 0x7fffffffu >> (len - 1);
3962 if (ofs + len <= 32) {
3963 tcg_gen_shli_i32(QREG_CC_N, src, ofs);
3964 } else {
3965 tcg_gen_rotli_i32(QREG_CC_N, src, ofs);
3966 }
3967 tcg_gen_andi_i32(QREG_CC_N, QREG_CC_N, ~maski);
3968 mask = tcg_const_i32(ror32(maski, ofs));
a45f1763
RH		 3969 if (!TCGV_IS_UNUSED(tofs)) {
3970 tcg_gen_movi_i32(tofs, ofs);
3971 tcg_gen_movi_i32(tlen, len);
3972 }
ac815f46
RH		 3973 } else {
3974 TCGv tmp = tcg_temp_new();
3975 if (ext & 0x20) {
3976 /* Variable width */
3977 tcg_gen_subi_i32(tmp, DREG(ext, 0), 1);
3978 tcg_gen_andi_i32(tmp, tmp, 31);
3979 mask = tcg_const_i32(0x7fffffffu);
3980 tcg_gen_shr_i32(mask, mask, tmp);
a45f1763
RH		 3981 if (!TCGV_IS_UNUSED(tlen)) {
3982 tcg_gen_addi_i32(tlen, tmp, 1);
3983 }
ac815f46
RH		 3984 } else {
3985 /* Immediate width */
3986 mask = tcg_const_i32(0x7fffffffu >> (len - 1));
a45f1763
RH		 3987 if (!TCGV_IS_UNUSED(tlen)) {
3988 tcg_gen_movi_i32(tlen, len);
3989 }
ac815f46
RH		 3990 }
3991 if (ext & 0x800) {
3992 /* Variable offset */
3993 tcg_gen_andi_i32(tmp, DREG(ext, 6), 31);
3994 tcg_gen_rotl_i32(QREG_CC_N, src, tmp);
3995 tcg_gen_andc_i32(QREG_CC_N, QREG_CC_N, mask);
3996 tcg_gen_rotr_i32(mask, mask, tmp);
a45f1763
RH		 3997 if (!TCGV_IS_UNUSED(tofs)) {
3998 tcg_gen_mov_i32(tofs, tmp);
3999 }
ac815f46
RH		 4000 } else {
4001 /* Immediate offset (and variable width) */
4002 tcg_gen_rotli_i32(QREG_CC_N, src, ofs);
4003 tcg_gen_andc_i32(QREG_CC_N, QREG_CC_N, mask);
4004 tcg_gen_rotri_i32(mask, mask, ofs);
a45f1763
RH		 4005 if (!TCGV_IS_UNUSED(tofs)) {
4006 tcg_gen_movi_i32(tofs, ofs);
4007 }
ac815f46
RH		 4008 }
4009 tcg_temp_free(tmp);
4010 }
4011 set_cc_op(s, CC_OP_LOGIC);
4012
4013 switch (insn & 0x0f00) {
4014 case 0x0a00: /* bfchg */
4015 tcg_gen_eqv_i32(src, src, mask);
4016 break;
4017 case 0x0c00: /* bfclr */
4018 tcg_gen_and_i32(src, src, mask);
4019 break;
a45f1763
RH		 4020 case 0x0d00: /* bfffo */
4021 gen_helper_bfffo_reg(DREG(ext, 12), QREG_CC_N, tofs, tlen);
4022 tcg_temp_free(tlen);
4023 tcg_temp_free(tofs);
4024 break;
ac815f46
RH		 4025 case 0x0e00: /* bfset */
4026 tcg_gen_orc_i32(src, src, mask);
4027 break;
4028 case 0x0800: /* bftst */
4029 /* flags already set; no other work to do. */
4030 break;
4031 default:
4032 g_assert_not_reached();
4033 }
4034 tcg_temp_free(mask);
4035}
4036
f2224f2c
RH		 4037DISAS_INSN(bfop_mem)
4038{
4039 int ext = read_im16(env, s);
4040 TCGv addr, len, ofs;
a45f1763 4041 TCGv_i64 t64;
f2224f2c
RH		 4042
4043 addr = gen_lea(env, s, insn, OS_UNSIZED);
4044 if (IS_NULL_QREG(addr)) {
4045 gen_addr_fault(s);
4046 return;
4047 }
4048
4049 if (ext & 0x20) {
4050 len = DREG(ext, 0);
4051 } else {
4052 len = tcg_const_i32(extract32(ext, 0, 5));
4053 }
4054 if (ext & 0x800) {
4055 ofs = DREG(ext, 6);
4056 } else {
4057 ofs = tcg_const_i32(extract32(ext, 6, 5));
4058 }
4059
4060 switch (insn & 0x0f00) {
4061 case 0x0a00: /* bfchg */
4062 gen_helper_bfchg_mem(QREG_CC_N, cpu_env, addr, ofs, len);
4063 break;
4064 case 0x0c00: /* bfclr */
4065 gen_helper_bfclr_mem(QREG_CC_N, cpu_env, addr, ofs, len);
4066 break;
a45f1763
RH		 4067 case 0x0d00: /* bfffo */
4068 t64 = tcg_temp_new_i64();
4069 gen_helper_bfffo_mem(t64, cpu_env, addr, ofs, len);
4070 tcg_gen_extr_i64_i32(DREG(ext, 12), QREG_CC_N, t64);
4071 tcg_temp_free_i64(t64);
4072 break;
f2224f2c
RH		 4073 case 0x0e00: /* bfset */
4074 gen_helper_bfset_mem(QREG_CC_N, cpu_env, addr, ofs, len);
4075 break;
4076 case 0x0800: /* bftst */
4077 gen_helper_bfexts_mem(QREG_CC_N, cpu_env, addr, ofs, len);
4078 break;
4079 default:
4080 g_assert_not_reached();
4081 }
4082 set_cc_op(s, CC_OP_LOGIC);
4083
4084 if (!(ext & 0x20)) {
4085 tcg_temp_free(len);
4086 }
4087 if (!(ext & 0x800)) {
4088 tcg_temp_free(ofs);
4089 }
4090}
4091
ac815f46
RH		 4092DISAS_INSN(bfins_reg)
4093{
4094 int ext = read_im16(env, s);
4095 TCGv dst = DREG(insn, 0);
4096 TCGv src = DREG(ext, 12);
4097 int len = ((extract32(ext, 0, 5) - 1) & 31) + 1;
4098 int ofs = extract32(ext, 6, 5); /* big bit-endian */
4099 int pos = 32 - ofs - len; /* little bit-endian */
4100 TCGv tmp;
4101
4102 tmp = tcg_temp_new();
4103
4104 if (ext & 0x20) {
4105 /* Variable width */
4106 tcg_gen_neg_i32(tmp, DREG(ext, 0));
4107 tcg_gen_andi_i32(tmp, tmp, 31);
4108 tcg_gen_shl_i32(QREG_CC_N, src, tmp);
4109 } else {
4110 /* Immediate width */
4111 tcg_gen_shli_i32(QREG_CC_N, src, 32 - len);
4112 }
4113 set_cc_op(s, CC_OP_LOGIC);
4114
4115 /* Immediate width and offset */
4116 if ((ext & 0x820) == 0) {
4117 /* Check for suitability for deposit. */
4118 if (pos >= 0) {
4119 tcg_gen_deposit_i32(dst, dst, src, pos, len);
4120 } else {
4121 uint32_t maski = -2U << (len - 1);
4122 uint32_t roti = (ofs + len) & 31;
4123 tcg_gen_andi_i32(tmp, src, ~maski);
4124 tcg_gen_rotri_i32(tmp, tmp, roti);
4125 tcg_gen_andi_i32(dst, dst, ror32(maski, roti));
4126 tcg_gen_or_i32(dst, dst, tmp);
4127 }
4128 } else {
4129 TCGv mask = tcg_temp_new();
4130 TCGv rot = tcg_temp_new();
4131
4132 if (ext & 0x20) {
4133 /* Variable width */
4134 tcg_gen_subi_i32(rot, DREG(ext, 0), 1);
4135 tcg_gen_andi_i32(rot, rot, 31);
4136 tcg_gen_movi_i32(mask, -2);
4137 tcg_gen_shl_i32(mask, mask, rot);
4138 tcg_gen_mov_i32(rot, DREG(ext, 0));
4139 tcg_gen_andc_i32(tmp, src, mask);
4140 } else {
4141 /* Immediate width (variable offset) */
4142 uint32_t maski = -2U << (len - 1);
4143 tcg_gen_andi_i32(tmp, src, ~maski);
4144 tcg_gen_movi_i32(mask, maski);
4145 tcg_gen_movi_i32(rot, len & 31);
4146 }
4147 if (ext & 0x800) {
4148 /* Variable offset */
4149 tcg_gen_add_i32(rot, rot, DREG(ext, 6));
4150 } else {
4151 /* Immediate offset (variable width) */
4152 tcg_gen_addi_i32(rot, rot, ofs);
4153 }
4154 tcg_gen_andi_i32(rot, rot, 31);
4155 tcg_gen_rotr_i32(mask, mask, rot);
4156 tcg_gen_rotr_i32(tmp, tmp, rot);
4157 tcg_gen_and_i32(dst, dst, mask);
4158 tcg_gen_or_i32(dst, dst, tmp);
4159
4160 tcg_temp_free(rot);
4161 tcg_temp_free(mask);
4162 }
4163 tcg_temp_free(tmp);
4164}
4165
f2224f2c
RH		 4166DISAS_INSN(bfins_mem)
4167{
4168 int ext = read_im16(env, s);
4169 TCGv src = DREG(ext, 12);
4170 TCGv addr, len, ofs;
4171
4172 addr = gen_lea(env, s, insn, OS_UNSIZED);
4173 if (IS_NULL_QREG(addr)) {
4174 gen_addr_fault(s);
4175 return;
4176 }
4177
4178 if (ext & 0x20) {
4179 len = DREG(ext, 0);
4180 } else {
4181 len = tcg_const_i32(extract32(ext, 0, 5));
4182 }
4183 if (ext & 0x800) {
4184 ofs = DREG(ext, 6);
4185 } else {
4186 ofs = tcg_const_i32(extract32(ext, 6, 5));
4187 }
4188
4189 gen_helper_bfins_mem(QREG_CC_N, cpu_env, addr, src, ofs, len);
4190 set_cc_op(s, CC_OP_LOGIC);
4191
4192 if (!(ext & 0x20)) {
4193 tcg_temp_free(len);
4194 }
4195 if (!(ext & 0x800)) {
4196 tcg_temp_free(ofs);
4197 }
4198}
4199
e6e5906b
PB		 4200DISAS_INSN(ff1)
4201{
e1f3808e 4202 TCGv reg;
821f7e76 4203 reg = DREG(insn, 0);
5dbb6784 4204 gen_logic_cc(s, reg, OS_LONG);
e1f3808e 4205 gen_helper_ff1(reg, reg);
e6e5906b
PB		 4206}
4207
e1f3808e 4208static TCGv gen_get_sr(DisasContext *s)
0633879f 4209{
e1f3808e
PB		 4210 TCGv ccr;
4211 TCGv sr;
0633879f
PB		 4212
4213 ccr = gen_get_ccr(s);
a7812ae4 4214 sr = tcg_temp_new();
e1f3808e
PB		 4215 tcg_gen_andi_i32(sr, QREG_SR, 0xffe0);
4216 tcg_gen_or_i32(sr, sr, ccr);
0633879f
PB		 4217 return sr;
4218}
4219
e6e5906b
PB		 4220DISAS_INSN(strldsr)
4221{
4222 uint16_t ext;
4223 uint32_t addr;
4224
4225 addr = s->pc - 2;
28b68cd7 4226 ext = read_im16(env, s);
0633879f 4227 if (ext != 0x46FC) {
e6e5906b 4228 gen_exception(s, addr, EXCP_UNSUPPORTED);
0633879f
PB		 4229 return;
4230 }
28b68cd7 4231 ext = read_im16(env, s);
0633879f 4232 if (IS_USER(s) || (ext & SR_S) == 0) {
e6e5906b 4233 gen_exception(s, addr, EXCP_PRIVILEGE);
0633879f
PB		 4234 return;
4235 }
4236 gen_push(s, gen_get_sr(s));
4237 gen_set_sr_im(s, ext, 0);
e6e5906b
PB		 4238}
4239
4240DISAS_INSN(move_from_sr)
4241{
e1f3808e 4242 TCGv sr;
0633879f 4243
7c0eb318 4244 if (IS_USER(s) && !m68k_feature(env, M68K_FEATURE_M68000)) {
0633879f
PB		 4245 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
4246 return;
4247 }
4248 sr = gen_get_sr(s);
7c0eb318 4249 DEST_EA(env, insn, OS_WORD, sr, NULL);
e6e5906b
PB		 4250}
4251
4252DISAS_INSN(move_to_sr)
4253{
0633879f
PB		 4254 if (IS_USER(s)) {
4255 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
4256 return;
4257 }
620c6cf6 4258 gen_set_sr(env, s, insn, 0);
0633879f 4259 gen_lookup_tb(s);
e6e5906b
PB		 4260}
4261
4262DISAS_INSN(move_from_usp)
4263{
0633879f
PB		 4264 if (IS_USER(s)) {
4265 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
4266 return;
4267 }
2a8327e8
GU		 4268 tcg_gen_ld_i32(AREG(insn, 0), cpu_env,
4269 offsetof(CPUM68KState, sp[M68K_USP]));
e6e5906b
PB		 4270}
4271
4272DISAS_INSN(move_to_usp)
4273{
0633879f
PB		 4274 if (IS_USER(s)) {
4275 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
4276 return;
4277 }
2a8327e8
GU		 4278 tcg_gen_st_i32(AREG(insn, 0), cpu_env,
4279 offsetof(CPUM68KState, sp[M68K_USP]));
e6e5906b
PB		 4280}
4281
4282DISAS_INSN(halt)
4283{
e1f3808e 4284 gen_exception(s, s->pc, EXCP_HALT_INSN);
e6e5906b
PB		 4285}
4286
4287DISAS_INSN(stop)
4288{
0633879f
PB		 4289 uint16_t ext;
4290
4291 if (IS_USER(s)) {
4292 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
4293 return;
4294 }
4295
28b68cd7 4296 ext = read_im16(env, s);
0633879f
PB		 4297
4298 gen_set_sr_im(s, ext, 0);
259186a7 4299 tcg_gen_movi_i32(cpu_halted, 1);
e1f3808e 4300 gen_exception(s, s->pc, EXCP_HLT);
e6e5906b
PB		 4301}
4302
4303DISAS_INSN(rte)
4304{
0633879f
PB		 4305 if (IS_USER(s)) {
4306 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
4307 return;
4308 }
4309 gen_exception(s, s->pc - 2, EXCP_RTE);
e6e5906b
PB		 4310}
4311
4312DISAS_INSN(movec)
4313{
0633879f 4314 uint16_t ext;
e1f3808e 4315 TCGv reg;
0633879f
PB		 4316
4317 if (IS_USER(s)) {
4318 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
4319 return;
4320 }
4321
28b68cd7 4322 ext = read_im16(env, s);
0633879f
PB		 4323
4324 if (ext & 0x8000) {
4325 reg = AREG(ext, 12);
4326 } else {
4327 reg = DREG(ext, 12);
4328 }
e1f3808e 4329 gen_helper_movec(cpu_env, tcg_const_i32(ext & 0xfff), reg);
0633879f 4330 gen_lookup_tb(s);
e6e5906b
PB		 4331}
4332
4333DISAS_INSN(intouch)
4334{
0633879f
PB		 4335 if (IS_USER(s)) {
4336 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
4337 return;
4338 }
4339 /* ICache fetch. Implement as no-op. */
e6e5906b
PB		 4340}
4341
4342DISAS_INSN(cpushl)
4343{
0633879f
PB		 4344 if (IS_USER(s)) {
4345 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
4346 return;
4347 }
4348 /* Cache push/invalidate. Implement as no-op. */
e6e5906b
PB		 4349}
4350
4351DISAS_INSN(wddata)
4352{
4353 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
4354}
4355
4356DISAS_INSN(wdebug)
4357{
a47dddd7
AF		 4358 M68kCPU *cpu = m68k_env_get_cpu(env);
4359
0633879f
PB		 4360 if (IS_USER(s)) {
4361 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
4362 return;
4363 }
4364 /* TODO: Implement wdebug. */
a47dddd7 4365 cpu_abort(CPU(cpu), "WDEBUG not implemented");
e6e5906b
PB		 4366}
4367
4368DISAS_INSN(trap)
4369{
4370 gen_exception(s, s->pc - 2, EXCP_TRAP0 + (insn & 0xf));
4371}
4372
ba624944
LV		 4373static void gen_load_fcr(DisasContext *s, TCGv res, int reg)
4374{
4375 switch (reg) {
4376 case M68K_FPIAR:
4377 tcg_gen_movi_i32(res, 0);
4378 break;
4379 case M68K_FPSR:
4380 tcg_gen_ld_i32(res, cpu_env, offsetof(CPUM68KState, fpsr));
4381 break;
4382 case M68K_FPCR:
4383 tcg_gen_ld_i32(res, cpu_env, offsetof(CPUM68KState, fpcr));
4384 break;
4385 }
4386}
4387
4388static void gen_store_fcr(DisasContext *s, TCGv val, int reg)
4389{
4390 switch (reg) {
4391 case M68K_FPIAR:
4392 break;
4393 case M68K_FPSR:
4394 tcg_gen_st_i32(val, cpu_env, offsetof(CPUM68KState, fpsr));
4395 break;
4396 case M68K_FPCR:
4397 gen_helper_set_fpcr(cpu_env, val);
4398 break;
4399 }
4400}
4401
4402static void gen_qemu_store_fcr(DisasContext *s, TCGv addr, int reg)
4403{
4404 int index = IS_USER(s);
4405 TCGv tmp;
4406
4407 tmp = tcg_temp_new();
4408 gen_load_fcr(s, tmp, reg);
4409 tcg_gen_qemu_st32(tmp, addr, index);
4410 tcg_temp_free(tmp);
4411}
4412
4413static void gen_qemu_load_fcr(DisasContext *s, TCGv addr, int reg)
4414{
4415 int index = IS_USER(s);
4416 TCGv tmp;
4417
4418 tmp = tcg_temp_new();
4419 tcg_gen_qemu_ld32u(tmp, addr, index);
4420 gen_store_fcr(s, tmp, reg);
4421 tcg_temp_free(tmp);
4422}
4423
4424
860b9ac7
LV		 4425static void gen_op_fmove_fcr(CPUM68KState *env, DisasContext *s,
4426 uint32_t insn, uint32_t ext)
4427{
4428 int mask = (ext >> 10) & 7;
4429 int is_write = (ext >> 13) & 1;
ba624944
LV		 4430 int mode = extract32(insn, 3, 3);
4431 int i;
4432 TCGv addr, tmp;
860b9ac7 4433
ba624944
LV		 4434 switch (mode) {
4435 case 0: /* Dn */
4436 if (mask != M68K_FPIAR && mask != M68K_FPSR && mask != M68K_FPCR) {
4437 gen_exception(s, s->insn_pc, EXCP_ILLEGAL);
4438 return;
4439 }
860b9ac7 4440 if (is_write) {
ba624944
LV		 4441 gen_load_fcr(s, DREG(insn, 0), mask);
4442 } else {
4443 gen_store_fcr(s, DREG(insn, 0), mask);
860b9ac7 4444 }
ba624944
LV		 4445 return;
4446 case 1: /* An, only with FPIAR */
4447 if (mask != M68K_FPIAR) {
4448 gen_exception(s, s->insn_pc, EXCP_ILLEGAL);
4449 return;
4450 }
4451 if (is_write) {
4452 gen_load_fcr(s, AREG(insn, 0), mask);
4453 } else {
4454 gen_store_fcr(s, AREG(insn, 0), mask);
4455 }
4456 return;
4457 default:
860b9ac7
LV		 4458 break;
4459 }
ba624944
LV		 4460
4461 tmp = gen_lea(env, s, insn, OS_LONG);
4462 if (IS_NULL_QREG(tmp)) {
4463 gen_addr_fault(s);
4464 return;
4465 }
4466
4467 addr = tcg_temp_new();
4468 tcg_gen_mov_i32(addr, tmp);
4469
4470 /* mask:
4471 *
4472 * 0b100 Floating-Point Control Register
4473 * 0b010 Floating-Point Status Register
4474 * 0b001 Floating-Point Instruction Address Register
4475 *
4476 */
4477
4478 if (is_write && mode == 4) {
4479 for (i = 2; i >= 0; i--, mask >>= 1) {
4480 if (mask & 1) {
4481 gen_qemu_store_fcr(s, addr, 1 << i);
4482 if (mask != 1) {
4483 tcg_gen_subi_i32(addr, addr, opsize_bytes(OS_LONG));
4484 }
4485 }
4486 }
4487 tcg_gen_mov_i32(AREG(insn, 0), addr);
4488 } else {
4489 for (i = 0; i < 3; i++, mask >>= 1) {
4490 if (mask & 1) {
4491 if (is_write) {
4492 gen_qemu_store_fcr(s, addr, 1 << i);
4493 } else {
4494 gen_qemu_load_fcr(s, addr, 1 << i);
4495 }
4496 if (mask != 1 || mode == 3) {
4497 tcg_gen_addi_i32(addr, addr, opsize_bytes(OS_LONG));
4498 }
4499 }
4500 }
4501 if (mode == 3) {
4502 tcg_gen_mov_i32(AREG(insn, 0), addr);
4503 }
4504 }
4505 tcg_temp_free_i32(addr);
860b9ac7
LV		 4506}
4507
e6e5906b
PB		 4508/* ??? FP exceptions are not implemented. Most exceptions are deferred until
4509 immediately before the next FP instruction is executed. */
4510DISAS_INSN(fpu)
4511{
4512 uint16_t ext;
4513 int opmode;
a7812ae4 4514 TCGv tmp32;
e6e5906b 4515 int opsize;
f83311e4 4516 TCGv_ptr cpu_src, cpu_dest;
e6e5906b 4517
28b68cd7 4518 ext = read_im16(env, s);
e6e5906b
PB		 4519 opmode = ext & 0x7f;
4520 switch ((ext >> 13) & 7) {
9d403660 4521 case 0:
e6e5906b
PB		 4522 break;
4523 case 1:
4524 goto undef;
9d403660
LV		 4525 case 2:
4526 if (insn == 0xf200 && (ext & 0xfc00) == 0x5c00) {
4527 /* fmovecr */
4528 TCGv rom_offset = tcg_const_i32(opmode);
4529 cpu_dest = gen_fp_ptr(REG(ext, 7));
4530 gen_helper_fconst(cpu_env, cpu_dest, rom_offset);
4531 tcg_temp_free_ptr(cpu_dest);
4532 tcg_temp_free(rom_offset);
4533 return;
4534 }
4535 break;
e6e5906b 4536 case 3: /* fmove out */
f83311e4 4537 cpu_src = gen_fp_ptr(REG(ext, 7));
69e69822 4538 opsize = ext_opsize(ext, 10);
f83311e4
LV		 4539 if (gen_ea_fp(env, s, insn, opsize, cpu_src, EA_STORE) == -1) {
4540 gen_addr_fault(s);
e6e5906b 4541 }
ba624944 4542 gen_helper_ftst(cpu_env, cpu_src);
f83311e4 4543 tcg_temp_free_ptr(cpu_src);
e6e5906b
PB		 4544 return;
4545 case 4: /* fmove to control register. */
e6e5906b 4546 case 5: /* fmove from control register. */
860b9ac7
LV		 4547 gen_op_fmove_fcr(env, s, insn, ext);
4548 return;
5fafdf24 4549 case 6: /* fmovem */
e6e5906b
PB		 4550 case 7:
4551 {
e1f3808e 4552 TCGv addr;
f83311e4 4553 TCGv_ptr fp;
e1f3808e
PB		 4554 uint16_t mask;
4555 int i;
4556 if ((ext & 0x1f00) != 0x1000 || (ext & 0xff) == 0)
4557 goto undef;
d4d79bb1 4558 tmp32 = gen_lea(env, s, insn, OS_LONG);
a7812ae4 4559 if (IS_NULL_QREG(tmp32)) {
e1f3808e
PB		 4560 gen_addr_fault(s);
4561 return;
4562 }
a7812ae4
PB		 4563 addr = tcg_temp_new_i32();
4564 tcg_gen_mov_i32(addr, tmp32);
e1f3808e 4565 mask = 0x80;
f83311e4 4566 fp = tcg_temp_new_ptr();
e1f3808e
PB		 4567 for (i = 0; i < 8; i++) {
4568 if (ext & mask) {
f83311e4
LV		 4569 tcg_gen_addi_ptr(fp, cpu_env,
4570 offsetof(CPUM68KState, fregs[i]));
4571 gen_ldst_fp(s, OS_DOUBLE, addr, fp,
4572 (ext & (1 << 13)) ? EA_STORE : EA_LOADS);
e1f3808e
PB		 4573 if (ext & (mask - 1))
4574 tcg_gen_addi_i32(addr, addr, 8);
e6e5906b 4575 }
e1f3808e 4576 mask >>= 1;
e6e5906b 4577 }
18307f26 4578 tcg_temp_free_i32(addr);
f83311e4 4579 tcg_temp_free_ptr(fp);
e6e5906b
PB		 4580 }
4581 return;
4582 }
4583 if (ext & (1 << 14)) {
e6e5906b 4584 /* Source effective address. */
69e69822 4585 opsize = ext_opsize(ext, 10);
f83311e4
LV		 4586 cpu_src = gen_fp_result_ptr();
4587 if (gen_ea_fp(env, s, insn, opsize, cpu_src, EA_LOADS) == -1) {
4588 gen_addr_fault(s);
4589 return;
e6e5906b
PB		 4590 }
4591 } else {
4592 /* Source register. */
f83311e4
LV		 4593 opsize = OS_EXTENDED;
4594 cpu_src = gen_fp_ptr(REG(ext, 10));
e6e5906b 4595 }
f83311e4 4596 cpu_dest = gen_fp_ptr(REG(ext, 7));
e6e5906b
PB		 4597 switch (opmode) {
4598 case 0: case 0x40: case 0x44: /* fmove */
f83311e4 4599 gen_fp_move(cpu_dest, cpu_src);
e6e5906b
PB		 4600 break;
4601 case 1: /* fint */
f83311e4 4602 gen_helper_firound(cpu_env, cpu_dest, cpu_src);
e6e5906b
PB		 4603 break;
4604 case 3: /* fintrz */
f83311e4 4605 gen_helper_fitrunc(cpu_env, cpu_dest, cpu_src);
e6e5906b
PB		 4606 break;
4607 case 4: case 0x41: case 0x45: /* fsqrt */
f83311e4 4608 gen_helper_fsqrt(cpu_env, cpu_dest, cpu_src);
e6e5906b
PB		 4609 break;
4610 case 0x18: case 0x58: case 0x5c: /* fabs */
f83311e4 4611 gen_helper_fabs(cpu_env, cpu_dest, cpu_src);
e6e5906b
PB		 4612 break;
4613 case 0x1a: case 0x5a: case 0x5e: /* fneg */
f83311e4 4614 gen_helper_fchs(cpu_env, cpu_dest, cpu_src);
e6e5906b
PB		 4615 break;
4616 case 0x20: case 0x60: case 0x64: /* fdiv */
f83311e4 4617 gen_helper_fdiv(cpu_env, cpu_dest, cpu_src, cpu_dest);
e6e5906b
PB		 4618 break;
4619 case 0x22: case 0x62: case 0x66: /* fadd */
f83311e4 4620 gen_helper_fadd(cpu_env, cpu_dest, cpu_src, cpu_dest);
e6e5906b
PB		 4621 break;
4622 case 0x23: case 0x63: case 0x67: /* fmul */
f83311e4 4623 gen_helper_fmul(cpu_env, cpu_dest, cpu_src, cpu_dest);
e6e5906b
PB		 4624 break;
4625 case 0x28: case 0x68: case 0x6c: /* fsub */
f83311e4 4626 gen_helper_fsub(cpu_env, cpu_dest, cpu_src, cpu_dest);
e6e5906b
PB		 4627 break;
4628 case 0x38: /* fcmp */
ba624944
LV		 4629 gen_helper_fcmp(cpu_env, cpu_src, cpu_dest);
4630 return;
e6e5906b 4631 case 0x3a: /* ftst */
ba624944
LV		 4632 gen_helper_ftst(cpu_env, cpu_src);
4633 return;
e6e5906b
PB		 4634 default:
4635 goto undef;
4636 }
f83311e4 4637 tcg_temp_free_ptr(cpu_src);
ba624944 4638 gen_helper_ftst(cpu_env, cpu_dest);
f83311e4 4639 tcg_temp_free_ptr(cpu_dest);
e6e5906b
PB		 4640 return;
4641undef:
a7812ae4 4642 /* FIXME: Is this right for offset addressing modes? */
e6e5906b 4643 s->pc -= 2;
d4d79bb1 4644 disas_undef_fpu(env, s, insn);
e6e5906b
PB		 4645}
4646
dd337bf8 4647static void gen_fcc_cond(DisasCompare *c, DisasContext *s, int cond)
e6e5906b 4648{
dd337bf8 4649 TCGv fpsr;
e6e5906b 4650
dd337bf8
LV		 4651 c->g1 = 1;
4652 c->v2 = tcg_const_i32(0);
4653 c->g2 = 0;
4654 /* TODO: Raise BSUN exception. */
ba624944
LV		 4655 fpsr = tcg_temp_new();
4656 gen_load_fcr(s, fpsr, M68K_FPSR);
dd337bf8 4657 switch (cond) {
ba624944
LV		 4658 case 0: /* False */
4659 case 16: /* Signaling False */
dd337bf8
LV		 4660 c->v1 = c->v2;
4661 c->tcond = TCG_COND_NEVER;
e6e5906b 4662 break;
ba624944
LV		 4663 case 1: /* EQual Z */
4664 case 17: /* Signaling EQual Z */
dd337bf8
LV		 4665 c->v1 = tcg_temp_new();
4666 c->g1 = 0;
4667 tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_Z);
4668 c->tcond = TCG_COND_NE;
e6e5906b 4669 break;
ba624944
LV		 4670 case 2: /* Ordered Greater Than !(A || Z || N) */
4671 case 18: /* Greater Than !(A || Z || N) */
dd337bf8
LV		 4672 c->v1 = tcg_temp_new();
4673 c->g1 = 0;
4674 tcg_gen_andi_i32(c->v1, fpsr,
ba624944 4675 FPSR_CC_A | FPSR_CC_Z | FPSR_CC_N);
dd337bf8 4676 c->tcond = TCG_COND_EQ;
e6e5906b 4677 break;
ba624944
LV		 4678 case 3: /* Ordered Greater than or Equal Z || !(A || N) */
4679 case 19: /* Greater than or Equal Z || !(A || N) */
dd337bf8
LV		 4680 c->v1 = tcg_temp_new();
4681 c->g1 = 0;
4682 tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A);
4683 tcg_gen_shli_i32(c->v1, c->v1, ctz32(FPSR_CC_N) - ctz32(FPSR_CC_A));
4684 tcg_gen_andi_i32(fpsr, fpsr, FPSR_CC_Z | FPSR_CC_N);
4685 tcg_gen_or_i32(c->v1, c->v1, fpsr);
4686 tcg_gen_xori_i32(c->v1, c->v1, FPSR_CC_N);
4687 c->tcond = TCG_COND_NE;
e6e5906b 4688 break;
ba624944
LV		 4689 case 4: /* Ordered Less Than !(!N || A || Z); */
4690 case 20: /* Less Than !(!N || A || Z); */
dd337bf8
LV		 4691 c->v1 = tcg_temp_new();
4692 c->g1 = 0;
4693 tcg_gen_xori_i32(c->v1, fpsr, FPSR_CC_N);
4694 tcg_gen_andi_i32(c->v1, c->v1, FPSR_CC_N | FPSR_CC_A | FPSR_CC_Z);
4695 c->tcond = TCG_COND_EQ;
e6e5906b 4696 break;
ba624944
LV		 4697 case 5: /* Ordered Less than or Equal Z || (N && !A) */
4698 case 21: /* Less than or Equal Z || (N && !A) */
dd337bf8
LV		 4699 c->v1 = tcg_temp_new();
4700 c->g1 = 0;
4701 tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A);
4702 tcg_gen_shli_i32(c->v1, c->v1, ctz32(FPSR_CC_N) - ctz32(FPSR_CC_A));
4703 tcg_gen_andc_i32(c->v1, fpsr, c->v1);
4704 tcg_gen_andi_i32(c->v1, c->v1, FPSR_CC_Z | FPSR_CC_N);
4705 c->tcond = TCG_COND_NE;
e6e5906b 4706 break;
ba624944
LV		 4707 case 6: /* Ordered Greater or Less than !(A || Z) */
4708 case 22: /* Greater or Less than !(A || Z) */
dd337bf8
LV		 4709 c->v1 = tcg_temp_new();
4710 c->g1 = 0;
4711 tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A | FPSR_CC_Z);
4712 c->tcond = TCG_COND_EQ;
e6e5906b 4713 break;
ba624944
LV		 4714 case 7: /* Ordered !A */
4715 case 23: /* Greater, Less or Equal !A */
dd337bf8
LV		 4716 c->v1 = tcg_temp_new();
4717 c->g1 = 0;
4718 tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A);
4719 c->tcond = TCG_COND_EQ;
e6e5906b 4720 break;
ba624944
LV		 4721 case 8: /* Unordered A */
4722 case 24: /* Not Greater, Less or Equal A */
dd337bf8
LV		 4723 c->v1 = tcg_temp_new();
4724 c->g1 = 0;
4725 tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A);
4726 c->tcond = TCG_COND_NE;
e6e5906b 4727 break;
ba624944
LV		 4728 case 9: /* Unordered or Equal A || Z */
4729 case 25: /* Not Greater or Less then A || Z */
dd337bf8
LV		 4730 c->v1 = tcg_temp_new();
4731 c->g1 = 0;
4732 tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A | FPSR_CC_Z);
4733 c->tcond = TCG_COND_NE;
e6e5906b 4734 break;
ba624944
LV		 4735 case 10: /* Unordered or Greater Than A || !(N || Z)) */
4736 case 26: /* Not Less or Equal A || !(N || Z)) */
dd337bf8
LV		 4737 c->v1 = tcg_temp_new();
4738 c->g1 = 0;
4739 tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_Z);
4740 tcg_gen_shli_i32(c->v1, c->v1, ctz32(FPSR_CC_N) - ctz32(FPSR_CC_Z));
4741 tcg_gen_andi_i32(fpsr, fpsr, FPSR_CC_A | FPSR_CC_N);
4742 tcg_gen_or_i32(c->v1, c->v1, fpsr);
4743 tcg_gen_xori_i32(c->v1, c->v1, FPSR_CC_N);
4744 c->tcond = TCG_COND_NE;
e6e5906b 4745 break;
ba624944
LV		 4746 case 11: /* Unordered or Greater or Equal A || Z || !N */
4747 case 27: /* Not Less Than A || Z || !N */
dd337bf8
LV		 4748 c->v1 = tcg_temp_new();
4749 c->g1 = 0;
4750 tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A | FPSR_CC_Z | FPSR_CC_N);
4751 tcg_gen_xori_i32(c->v1, c->v1, FPSR_CC_N);
4752 c->tcond = TCG_COND_NE;
e6e5906b 4753 break;
ba624944
LV		 4754 case 12: /* Unordered or Less Than A || (N && !Z) */
4755 case 28: /* Not Greater than or Equal A || (N && !Z) */
dd337bf8
LV		 4756 c->v1 = tcg_temp_new();
4757 c->g1 = 0;
4758 tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_Z);
4759 tcg_gen_shli_i32(c->v1, c->v1, ctz32(FPSR_CC_N) - ctz32(FPSR_CC_Z));
4760 tcg_gen_andc_i32(c->v1, fpsr, c->v1);
4761 tcg_gen_andi_i32(c->v1, c->v1, FPSR_CC_A | FPSR_CC_N);
4762 c->tcond = TCG_COND_NE;
e6e5906b 4763 break;
ba624944
LV		 4764 case 13: /* Unordered or Less or Equal A || Z || N */
4765 case 29: /* Not Greater Than A || Z || N */
dd337bf8
LV		 4766 c->v1 = tcg_temp_new();
4767 c->g1 = 0;
4768 tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A | FPSR_CC_Z | FPSR_CC_N);
4769 c->tcond = TCG_COND_NE;
e6e5906b 4770 break;
ba624944
LV		 4771 case 14: /* Not Equal !Z */
4772 case 30: /* Signaling Not Equal !Z */
dd337bf8
LV		 4773 c->v1 = tcg_temp_new();
4774 c->g1 = 0;
4775 tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_Z);
4776 c->tcond = TCG_COND_EQ;
e6e5906b 4777 break;
ba624944
LV		 4778 case 15: /* True */
4779 case 31: /* Signaling True */
dd337bf8
LV		 4780 c->v1 = c->v2;
4781 c->tcond = TCG_COND_ALWAYS;
e6e5906b
PB		 4782 break;
4783 }
ba624944 4784 tcg_temp_free(fpsr);
dd337bf8
LV		 4785}
4786
4787static void gen_fjmpcc(DisasContext *s, int cond, TCGLabel *l1)
4788{
4789 DisasCompare c;
4790
4791 gen_fcc_cond(&c, s, cond);
4792 tcg_gen_brcond_i32(c.tcond, c.v1, c.v2, l1);
4793 free_cond(&c);
4794}
4795
4796DISAS_INSN(fbcc)
4797{
4798 uint32_t offset;
4799 uint32_t base;
4800 TCGLabel *l1;
4801
4802 base = s->pc;
4803 offset = (int16_t)read_im16(env, s);
4804 if (insn & (1 << 6)) {
4805 offset = (offset << 16) | read_im16(env, s);
4806 }
4807
4808 l1 = gen_new_label();
4809 update_cc_op(s);
4810 gen_fjmpcc(s, insn & 0x3f, l1);
e6e5906b
PB		 4811 gen_jmp_tb(s, 0, s->pc);
4812 gen_set_label(l1);
dd337bf8
LV		 4813 gen_jmp_tb(s, 1, base + offset);
4814}
4815
4816DISAS_INSN(fscc)
4817{
4818 DisasCompare c;
4819 int cond;
4820 TCGv tmp;
4821 uint16_t ext;
4822
4823 ext = read_im16(env, s);
4824 cond = ext & 0x3f;
4825 gen_fcc_cond(&c, s, cond);
4826
4827 tmp = tcg_temp_new();
4828 tcg_gen_setcond_i32(c.tcond, tmp, c.v1, c.v2);
4829 free_cond(&c);
4830
4831 tcg_gen_neg_i32(tmp, tmp);
4832 DEST_EA(env, insn, OS_BYTE, tmp, NULL);
4833 tcg_temp_free(tmp);
e6e5906b
PB		 4834}
4835
0633879f
PB		 4836DISAS_INSN(frestore)
4837{
a47dddd7
AF		 4838 M68kCPU *cpu = m68k_env_get_cpu(env);
4839
0633879f 4840 /* TODO: Implement frestore. */
a47dddd7 4841 cpu_abort(CPU(cpu), "FRESTORE not implemented");
0633879f
PB		 4842}
4843
4844DISAS_INSN(fsave)
4845{
a47dddd7
AF		 4846 M68kCPU *cpu = m68k_env_get_cpu(env);
4847
0633879f 4848 /* TODO: Implement fsave. */
a47dddd7 4849 cpu_abort(CPU(cpu), "FSAVE not implemented");
0633879f
PB		 4850}
4851
e1f3808e 4852static inline TCGv gen_mac_extract_word(DisasContext *s, TCGv val, int upper)
acf930aa 4853{
a7812ae4 4854 TCGv tmp = tcg_temp_new();
acf930aa
PB		 4855 if (s->env->macsr & MACSR_FI) {
4856 if (upper)
e1f3808e 4857 tcg_gen_andi_i32(tmp, val, 0xffff0000);
acf930aa 4858 else
e1f3808e 4859 tcg_gen_shli_i32(tmp, val, 16);
acf930aa
PB		 4860 } else if (s->env->macsr & MACSR_SU) {
4861 if (upper)
e1f3808e 4862 tcg_gen_sari_i32(tmp, val, 16);
acf930aa 4863 else
e1f3808e 4864 tcg_gen_ext16s_i32(tmp, val);
acf930aa
PB		 4865 } else {
4866 if (upper)
e1f3808e 4867 tcg_gen_shri_i32(tmp, val, 16);
acf930aa 4868 else
e1f3808e 4869 tcg_gen_ext16u_i32(tmp, val);
acf930aa
PB		 4870 }
4871 return tmp;
4872}
4873
e1f3808e
PB		 4874static void gen_mac_clear_flags(void)
4875{
4876 tcg_gen_andi_i32(QREG_MACSR, QREG_MACSR,
4877 ~(MACSR_V | MACSR_Z | MACSR_N | MACSR_EV));
4878}
4879
acf930aa
PB		 4880DISAS_INSN(mac)
4881{
e1f3808e
PB		 4882 TCGv rx;
4883 TCGv ry;
acf930aa
PB		 4884 uint16_t ext;
4885 int acc;
e1f3808e
PB		 4886 TCGv tmp;
4887 TCGv addr;
4888 TCGv loadval;
acf930aa 4889 int dual;
e1f3808e
PB		 4890 TCGv saved_flags;
4891
a7812ae4
PB		 4892 if (!s->done_mac) {
4893 s->mactmp = tcg_temp_new_i64();
4894 s->done_mac = 1;
4895 }
acf930aa 4896
28b68cd7 4897 ext = read_im16(env, s);
acf930aa
PB		 4898
4899 acc = ((insn >> 7) & 1) | ((ext >> 3) & 2);
4900 dual = ((insn & 0x30) != 0 && (ext & 3) != 0);
d315c888 4901 if (dual && !m68k_feature(s->env, M68K_FEATURE_CF_EMAC_B)) {
d4d79bb1 4902 disas_undef(env, s, insn);
d315c888
PB		 4903 return;
4904 }
acf930aa
PB		 4905 if (insn & 0x30) {
4906 /* MAC with load. */
d4d79bb1 4907 tmp = gen_lea(env, s, insn, OS_LONG);
a7812ae4 4908 addr = tcg_temp_new();
e1f3808e 4909 tcg_gen_and_i32(addr, tmp, QREG_MAC_MASK);
acf930aa
PB		 4910 /* Load the value now to ensure correct exception behavior.
4911 Perform writeback after reading the MAC inputs. */
4912 loadval = gen_load(s, OS_LONG, addr, 0);
4913
4914 acc ^= 1;
4915 rx = (ext & 0x8000) ? AREG(ext, 12) : DREG(insn, 12);
4916 ry = (ext & 8) ? AREG(ext, 0) : DREG(ext, 0);
4917 } else {
e1f3808e 4918 loadval = addr = NULL_QREG;
acf930aa
PB		 4919 rx = (insn & 0x40) ? AREG(insn, 9) : DREG(insn, 9);
4920 ry = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0);
4921 }
4922
e1f3808e
PB		 4923 gen_mac_clear_flags();
4924#if 0
acf930aa 4925 l1 = -1;
e1f3808e 4926 /* Disabled because conditional branches clobber temporary vars. */
acf930aa
PB		 4927 if ((s->env->macsr & MACSR_OMC) != 0 && !dual) {
4928 /* Skip the multiply if we know we will ignore it. */
4929 l1 = gen_new_label();
a7812ae4 4930 tmp = tcg_temp_new();
e1f3808e 4931 tcg_gen_andi_i32(tmp, QREG_MACSR, 1 << (acc + 8));
acf930aa
PB		 4932 gen_op_jmp_nz32(tmp, l1);
4933 }
e1f3808e 4934#endif
acf930aa
PB		 4935
4936 if ((ext & 0x0800) == 0) {
4937 /* Word. */
4938 rx = gen_mac_extract_word(s, rx, (ext & 0x80) != 0);
4939 ry = gen_mac_extract_word(s, ry, (ext & 0x40) != 0);
4940 }
4941 if (s->env->macsr & MACSR_FI) {
e1f3808e 4942 gen_helper_macmulf(s->mactmp, cpu_env, rx, ry);
acf930aa
PB		 4943 } else {
4944 if (s->env->macsr & MACSR_SU)
e1f3808e 4945 gen_helper_macmuls(s->mactmp, cpu_env, rx, ry);
acf930aa 4946 else
e1f3808e 4947 gen_helper_macmulu(s->mactmp, cpu_env, rx, ry);
acf930aa
PB		 4948 switch ((ext >> 9) & 3) {
4949 case 1:
e1f3808e 4950 tcg_gen_shli_i64(s->mactmp, s->mactmp, 1);
acf930aa
PB		 4951 break;
4952 case 3:
e1f3808e 4953 tcg_gen_shri_i64(s->mactmp, s->mactmp, 1);
acf930aa
PB		 4954 break;
4955 }
4956 }
4957
4958 if (dual) {
4959 /* Save the overflow flag from the multiply. */
a7812ae4 4960 saved_flags = tcg_temp_new();
e1f3808e
PB		 4961 tcg_gen_mov_i32(saved_flags, QREG_MACSR);
4962 } else {
4963 saved_flags = NULL_QREG;
acf930aa
PB		 4964 }
4965
e1f3808e
PB		 4966#if 0
4967 /* Disabled because conditional branches clobber temporary vars. */
acf930aa
PB		 4968 if ((s->env->macsr & MACSR_OMC) != 0 && dual) {
4969 /* Skip the accumulate if the value is already saturated. */
4970 l1 = gen_new_label();
a7812ae4 4971 tmp = tcg_temp_new();
351326a6 4972 gen_op_and32(tmp, QREG_MACSR, tcg_const_i32(MACSR_PAV0 << acc));
acf930aa
PB		 4973 gen_op_jmp_nz32(tmp, l1);
4974 }
e1f3808e 4975#endif
acf930aa
PB		 4976
4977 if (insn & 0x100)
e1f3808e 4978 tcg_gen_sub_i64(MACREG(acc), MACREG(acc), s->mactmp);
acf930aa 4979 else
e1f3808e 4980 tcg_gen_add_i64(MACREG(acc), MACREG(acc), s->mactmp);
acf930aa
PB		 4981
4982 if (s->env->macsr & MACSR_FI)
e1f3808e 4983 gen_helper_macsatf(cpu_env, tcg_const_i32(acc));
acf930aa 4984 else if (s->env->macsr & MACSR_SU)
e1f3808e 4985 gen_helper_macsats(cpu_env, tcg_const_i32(acc));
acf930aa 4986 else
e1f3808e 4987 gen_helper_macsatu(cpu_env, tcg_const_i32(acc));
acf930aa 4988
e1f3808e
PB		 4989#if 0
4990 /* Disabled because conditional branches clobber temporary vars. */
acf930aa
PB		 4991 if (l1 != -1)
4992 gen_set_label(l1);
e1f3808e 4993#endif
acf930aa
PB		 4994
4995 if (dual) {
4996 /* Dual accumulate variant. */
4997 acc = (ext >> 2) & 3;
4998 /* Restore the overflow flag from the multiplier. */
e1f3808e
PB		 4999 tcg_gen_mov_i32(QREG_MACSR, saved_flags);
5000#if 0
5001 /* Disabled because conditional branches clobber temporary vars. */
acf930aa
PB		 5002 if ((s->env->macsr & MACSR_OMC) != 0) {
5003 /* Skip the accumulate if the value is already saturated. */
5004 l1 = gen_new_label();
a7812ae4 5005 tmp = tcg_temp_new();
351326a6 5006 gen_op_and32(tmp, QREG_MACSR, tcg_const_i32(MACSR_PAV0 << acc));
acf930aa
PB		 5007 gen_op_jmp_nz32(tmp, l1);
5008 }
e1f3808e 5009#endif
acf930aa 5010 if (ext & 2)
e1f3808e 5011 tcg_gen_sub_i64(MACREG(acc), MACREG(acc), s->mactmp);
acf930aa 5012 else
e1f3808e 5013 tcg_gen_add_i64(MACREG(acc), MACREG(acc), s->mactmp);
acf930aa 5014 if (s->env->macsr & MACSR_FI)
e1f3808e 5015 gen_helper_macsatf(cpu_env, tcg_const_i32(acc));
acf930aa 5016 else if (s->env->macsr & MACSR_SU)
e1f3808e 5017 gen_helper_macsats(cpu_env, tcg_const_i32(acc));
acf930aa 5018 else
e1f3808e
PB		 5019 gen_helper_macsatu(cpu_env, tcg_const_i32(acc));
5020#if 0
5021 /* Disabled because conditional branches clobber temporary vars. */
acf930aa
PB		 5022 if (l1 != -1)
5023 gen_set_label(l1);
e1f3808e 5024#endif
acf930aa 5025 }
e1f3808e 5026 gen_helper_mac_set_flags(cpu_env, tcg_const_i32(acc));
acf930aa
PB		 5027
5028 if (insn & 0x30) {
e1f3808e 5029 TCGv rw;
acf930aa 5030 rw = (insn & 0x40) ? AREG(insn, 9) : DREG(insn, 9);
e1f3808e 5031 tcg_gen_mov_i32(rw, loadval);
acf930aa
PB		 5032 /* FIXME: Should address writeback happen with the masked or
5033 unmasked value? */
5034 switch ((insn >> 3) & 7) {
5035 case 3: /* Post-increment. */
e1f3808e 5036 tcg_gen_addi_i32(AREG(insn, 0), addr, 4);
acf930aa
PB		 5037 break;
5038 case 4: /* Pre-decrement. */
e1f3808e 5039 tcg_gen_mov_i32(AREG(insn, 0), addr);
acf930aa
PB		 5040 }
5041 }
5042}
5043
5044DISAS_INSN(from_mac)
5045{
e1f3808e 5046 TCGv rx;
a7812ae4 5047 TCGv_i64 acc;
e1f3808e 5048 int accnum;
acf930aa
PB		 5049
5050 rx = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0);
e1f3808e
PB		 5051 accnum = (insn >> 9) & 3;
5052 acc = MACREG(accnum);
acf930aa 5053 if (s->env->macsr & MACSR_FI) {
a7812ae4 5054 gen_helper_get_macf(rx, cpu_env, acc);
acf930aa 5055 } else if ((s->env->macsr & MACSR_OMC) == 0) {
ecc7b3aa 5056 tcg_gen_extrl_i64_i32(rx, acc);
acf930aa 5057 } else if (s->env->macsr & MACSR_SU) {
e1f3808e 5058 gen_helper_get_macs(rx, acc);
acf930aa 5059 } else {
e1f3808e
PB		 5060 gen_helper_get_macu(rx, acc);
5061 }
5062 if (insn & 0x40) {
5063 tcg_gen_movi_i64(acc, 0);
5064 tcg_gen_andi_i32(QREG_MACSR, QREG_MACSR, ~(MACSR_PAV0 << accnum));
acf930aa 5065 }
acf930aa
PB		 5066}
5067
5068DISAS_INSN(move_mac)
5069{
e1f3808e 5070 /* FIXME: This can be done without a helper. */
acf930aa 5071 int src;
e1f3808e 5072 TCGv dest;
acf930aa 5073 src = insn & 3;
e1f3808e
PB		 5074 dest = tcg_const_i32((insn >> 9) & 3);
5075 gen_helper_mac_move(cpu_env, dest, tcg_const_i32(src));
5076 gen_mac_clear_flags();
5077 gen_helper_mac_set_flags(cpu_env, dest);
acf930aa
PB		 5078}
5079
5080DISAS_INSN(from_macsr)
5081{
e1f3808e 5082 TCGv reg;
acf930aa
PB		 5083
5084 reg = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0);
e1f3808e 5085 tcg_gen_mov_i32(reg, QREG_MACSR);
acf930aa
PB		 5086}
5087
5088DISAS_INSN(from_mask)
5089{
e1f3808e 5090 TCGv reg;
acf930aa 5091 reg = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0);
e1f3808e 5092 tcg_gen_mov_i32(reg, QREG_MAC_MASK);
acf930aa
PB		 5093}
5094
5095DISAS_INSN(from_mext)
5096{
e1f3808e
PB		 5097 TCGv reg;
5098 TCGv acc;
acf930aa 5099 reg = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0);
e1f3808e 5100 acc = tcg_const_i32((insn & 0x400) ? 2 : 0);
acf930aa 5101 if (s->env->macsr & MACSR_FI)
e1f3808e 5102 gen_helper_get_mac_extf(reg, cpu_env, acc);
acf930aa 5103 else
e1f3808e 5104 gen_helper_get_mac_exti(reg, cpu_env, acc);
acf930aa
PB		 5105}
5106
5107DISAS_INSN(macsr_to_ccr)
5108{
620c6cf6
RH		 5109 TCGv tmp = tcg_temp_new();
5110 tcg_gen_andi_i32(tmp, QREG_MACSR, 0xf);
5111 gen_helper_set_sr(cpu_env, tmp);
5112 tcg_temp_free(tmp);
9fdb533f 5113 set_cc_op(s, CC_OP_FLAGS);
acf930aa
PB		 5114}
5115
5116DISAS_INSN(to_mac)
5117{
a7812ae4 5118 TCGv_i64 acc;
e1f3808e
PB		 5119 TCGv val;
5120 int accnum;
5121 accnum = (insn >> 9) & 3;
5122 acc = MACREG(accnum);
d4d79bb1 5123 SRC_EA(env, val, OS_LONG, 0, NULL);
acf930aa 5124 if (s->env->macsr & MACSR_FI) {
e1f3808e
PB		 5125 tcg_gen_ext_i32_i64(acc, val);
5126 tcg_gen_shli_i64(acc, acc, 8);
acf930aa 5127 } else if (s->env->macsr & MACSR_SU) {
e1f3808e 5128 tcg_gen_ext_i32_i64(acc, val);
acf930aa 5129 } else {
e1f3808e 5130 tcg_gen_extu_i32_i64(acc, val);
acf930aa 5131 }
e1f3808e
PB		 5132 tcg_gen_andi_i32(QREG_MACSR, QREG_MACSR, ~(MACSR_PAV0 << accnum));
5133 gen_mac_clear_flags();
5134 gen_helper_mac_set_flags(cpu_env, tcg_const_i32(accnum));
acf930aa
PB		 5135}
5136
5137DISAS_INSN(to_macsr)
5138{
e1f3808e 5139 TCGv val;
d4d79bb1 5140 SRC_EA(env, val, OS_LONG, 0, NULL);
e1f3808e 5141 gen_helper_set_macsr(cpu_env, val);
acf930aa
PB		 5142 gen_lookup_tb(s);
5143}
5144
5145DISAS_INSN(to_mask)
5146{
e1f3808e 5147 TCGv val;
d4d79bb1 5148 SRC_EA(env, val, OS_LONG, 0, NULL);
e1f3808e 5149 tcg_gen_ori_i32(QREG_MAC_MASK, val, 0xffff0000);
acf930aa
PB		 5150}
5151
5152DISAS_INSN(to_mext)
5153{
e1f3808e
PB		 5154 TCGv val;
5155 TCGv acc;
d4d79bb1 5156 SRC_EA(env, val, OS_LONG, 0, NULL);
e1f3808e 5157 acc = tcg_const_i32((insn & 0x400) ? 2 : 0);
acf930aa 5158 if (s->env->macsr & MACSR_FI)
e1f3808e 5159 gen_helper_set_mac_extf(cpu_env, val, acc);
acf930aa 5160 else if (s->env->macsr & MACSR_SU)
e1f3808e 5161 gen_helper_set_mac_exts(cpu_env, val, acc);
acf930aa 5162 else
e1f3808e 5163 gen_helper_set_mac_extu(cpu_env, val, acc);
acf930aa
PB		 5164}
5165
e6e5906b
PB		 5166static disas_proc opcode_table[65536];
5167
5168static void
5169register_opcode (disas_proc proc, uint16_t opcode, uint16_t mask)
5170{
5171 int i;
5172 int from;
5173 int to;
5174
5175 /* Sanity check. All set bits must be included in the mask. */
5fc4adf6
PB		 5176 if (opcode & ~mask) {
5177 fprintf(stderr,
5178 "qemu internal error: bogus opcode definition %04x/%04x\n",
5179 opcode, mask);
e6e5906b 5180 abort();
5fc4adf6 5181 }
e6e5906b
PB		 5182 /* This could probably be cleverer. For now just optimize the case where
5183 the top bits are known. */
5184 /* Find the first zero bit in the mask. */
5185 i = 0x8000;
5186 while ((i & mask) != 0)
5187 i >>= 1;
5188 /* Iterate over all combinations of this and lower bits. */
5189 if (i == 0)
5190 i = 1;
5191 else
5192 i <<= 1;
5193 from = opcode & ~(i - 1);
5194 to = from + i;
0633879f 5195 for (i = from; i < to; i++) {
e6e5906b
PB		 5196 if ((i & mask) == opcode)
5197 opcode_table[i] = proc;
0633879f 5198 }
e6e5906b
PB		 5199}
5200
5201/* Register m68k opcode handlers. Order is important.
5202 Later insn override earlier ones. */
0402f767 5203void register_m68k_insns (CPUM68KState *env)
e6e5906b 5204{
b2085257
JPAG		 5205 /* Build the opcode table only once to avoid
5206 multithreading issues. */
5207 if (opcode_table[0] != NULL) {
5208 return;
5209 }
f076803b
LV		 5210
5211 /* use BASE() for instruction available
5212 * for CF_ISA_A and M68000.
5213 */
5214#define BASE(name, opcode, mask) \
5215 register_opcode(disas_##name, 0x##opcode, 0x##mask)
d315c888 5216#define INSN(name, opcode, mask, feature) do { \
0402f767 5217 if (m68k_feature(env, M68K_FEATURE_##feature)) \
f076803b 5218 BASE(name, opcode, mask); \
d315c888 5219 } while(0)
f076803b 5220 BASE(undef, 0000, 0000);
0402f767 5221 INSN(arith_im, 0080, fff8, CF_ISA_A);
f076803b
LV		 5222 INSN(arith_im, 0000, ff00, M68000);
5223 INSN(undef, 00c0, ffc0, M68000);
d315c888 5224 INSN(bitrev, 00c0, fff8, CF_ISA_APLUSC);
f076803b
LV		 5225 BASE(bitop_reg, 0100, f1c0);
5226 BASE(bitop_reg, 0140, f1c0);
5227 BASE(bitop_reg, 0180, f1c0);
5228 BASE(bitop_reg, 01c0, f1c0);
0402f767 5229 INSN(arith_im, 0280, fff8, CF_ISA_A);
f076803b
LV		 5230 INSN(arith_im, 0200, ff00, M68000);
5231 INSN(undef, 02c0, ffc0, M68000);
d315c888 5232 INSN(byterev, 02c0, fff8, CF_ISA_APLUSC);
0402f767 5233 INSN(arith_im, 0480, fff8, CF_ISA_A);
f076803b
LV		 5234 INSN(arith_im, 0400, ff00, M68000);
5235 INSN(undef, 04c0, ffc0, M68000);
5236 INSN(arith_im, 0600, ff00, M68000);
5237 INSN(undef, 06c0, ffc0, M68000);
d315c888 5238 INSN(ff1, 04c0, fff8, CF_ISA_APLUSC);
0402f767 5239 INSN(arith_im, 0680, fff8, CF_ISA_A);
0402f767 5240 INSN(arith_im, 0c00, ff38, CF_ISA_A);
f076803b
LV		 5241 INSN(arith_im, 0c00, ff00, M68000);
5242 BASE(bitop_im, 0800, ffc0);
5243 BASE(bitop_im, 0840, ffc0);
5244 BASE(bitop_im, 0880, ffc0);
5245 BASE(bitop_im, 08c0, ffc0);
5246 INSN(arith_im, 0a80, fff8, CF_ISA_A);
5247 INSN(arith_im, 0a00, ff00, M68000);
14f94406
LV		 5248 INSN(cas, 0ac0, ffc0, CAS);
5249 INSN(cas, 0cc0, ffc0, CAS);
5250 INSN(cas, 0ec0, ffc0, CAS);
5251 INSN(cas2w, 0cfc, ffff, CAS);
5252 INSN(cas2l, 0efc, ffff, CAS);
f076803b
LV		 5253 BASE(move, 1000, f000);
5254 BASE(move, 2000, f000);
5255 BASE(move, 3000, f000);
d315c888 5256 INSN(strldsr, 40e7, ffff, CF_ISA_APLUSC);
0402f767 5257 INSN(negx, 4080, fff8, CF_ISA_A);
a665a820
RH		 5258 INSN(negx, 4000, ff00, M68000);
5259 INSN(undef, 40c0, ffc0, M68000);
0402f767 5260 INSN(move_from_sr, 40c0, fff8, CF_ISA_A);
f076803b
LV		 5261 INSN(move_from_sr, 40c0, ffc0, M68000);
5262 BASE(lea, 41c0, f1c0);
5263 BASE(clr, 4200, ff00);
5264 BASE(undef, 42c0, ffc0);
0402f767 5265 INSN(move_from_ccr, 42c0, fff8, CF_ISA_A);
7c0eb318 5266 INSN(move_from_ccr, 42c0, ffc0, M68000);
0402f767 5267 INSN(neg, 4480, fff8, CF_ISA_A);
f076803b
LV		 5268 INSN(neg, 4400, ff00, M68000);
5269 INSN(undef, 44c0, ffc0, M68000);
5270 BASE(move_to_ccr, 44c0, ffc0);
0402f767 5271 INSN(not, 4680, fff8, CF_ISA_A);
f076803b
LV		 5272 INSN(not, 4600, ff00, M68000);
5273 INSN(undef, 46c0, ffc0, M68000);
0402f767 5274 INSN(move_to_sr, 46c0, ffc0, CF_ISA_A);
fb5543d8 5275 INSN(nbcd, 4800, ffc0, M68000);
c630e436 5276 INSN(linkl, 4808, fff8, M68000);
f076803b
LV		 5277 BASE(pea, 4840, ffc0);
5278 BASE(swap, 4840, fff8);
71600eda 5279 INSN(bkpt, 4848, fff8, BKPT);
7b542eb9
LV		 5280 INSN(movem, 48d0, fbf8, CF_ISA_A);
5281 INSN(movem, 48e8, fbf8, CF_ISA_A);
5282 INSN(movem, 4880, fb80, M68000);
f076803b
LV		 5283 BASE(ext, 4880, fff8);
5284 BASE(ext, 48c0, fff8);
5285 BASE(ext, 49c0, fff8);
5286 BASE(tst, 4a00, ff00);
0402f767 5287 INSN(tas, 4ac0, ffc0, CF_ISA_B);
f076803b 5288 INSN(tas, 4ac0, ffc0, M68000);
0402f767
PB		 5289 INSN(halt, 4ac8, ffff, CF_ISA_A);
5290 INSN(pulse, 4acc, ffff, CF_ISA_A);
f076803b 5291 BASE(illegal, 4afc, ffff);
0402f767 5292 INSN(mull, 4c00, ffc0, CF_ISA_A);
f076803b 5293 INSN(mull, 4c00, ffc0, LONG_MULDIV);
0402f767 5294 INSN(divl, 4c40, ffc0, CF_ISA_A);
f076803b 5295 INSN(divl, 4c40, ffc0, LONG_MULDIV);
0402f767 5296 INSN(sats, 4c80, fff8, CF_ISA_B);
f076803b
LV		 5297 BASE(trap, 4e40, fff0);
5298 BASE(link, 4e50, fff8);
5299 BASE(unlk, 4e58, fff8);
20dcee94
PB		 5300 INSN(move_to_usp, 4e60, fff8, USP);
5301 INSN(move_from_usp, 4e68, fff8, USP);
f076803b
LV		 5302 BASE(nop, 4e71, ffff);
5303 BASE(stop, 4e72, ffff);
5304 BASE(rte, 4e73, ffff);
18059c9e 5305 INSN(rtd, 4e74, ffff, RTD);
f076803b 5306 BASE(rts, 4e75, ffff);
0402f767 5307 INSN(movec, 4e7b, ffff, CF_ISA_A);
f076803b 5308 BASE(jump, 4e80, ffc0);
8a370c6c 5309 BASE(jump, 4ec0, ffc0);
f076803b 5310 INSN(addsubq, 5000, f080, M68000);
8a370c6c 5311 BASE(addsubq, 5080, f0c0);
d5a3cf33
LV		 5312 INSN(scc, 50c0, f0f8, CF_ISA_A); /* Scc.B Dx */
5313 INSN(scc, 50c0, f0c0, M68000); /* Scc.B <EA> */
beff27ab 5314 INSN(dbcc, 50c8, f0f8, M68000);
0402f767 5315 INSN(tpf, 51f8, fff8, CF_ISA_A);
d315c888
PB		 5316
5317 /* Branch instructions. */
f076803b 5318 BASE(branch, 6000, f000);
d315c888 5319 /* Disable long branch instructions, then add back the ones we want. */
f076803b 5320 BASE(undef, 60ff, f0ff); /* All long branches. */
d315c888
PB		 5321 INSN(branch, 60ff, f0ff, CF_ISA_B);
5322 INSN(undef, 60ff, ffff, CF_ISA_B); /* bra.l */
5323 INSN(branch, 60ff, ffff, BRAL);
f076803b 5324 INSN(branch, 60ff, f0ff, BCCL);
d315c888 5325
f076803b 5326 BASE(moveq, 7000, f100);
0402f767 5327 INSN(mvzs, 7100, f100, CF_ISA_B);
f076803b
LV		 5328 BASE(or, 8000, f000);
5329 BASE(divw, 80c0, f0c0);
fb5543d8
LV		 5330 INSN(sbcd_reg, 8100, f1f8, M68000);
5331 INSN(sbcd_mem, 8108, f1f8, M68000);
f076803b 5332 BASE(addsub, 9000, f000);
a665a820
RH		 5333 INSN(undef, 90c0, f0c0, CF_ISA_A);
5334 INSN(subx_reg, 9180, f1f8, CF_ISA_A);
5335 INSN(subx_reg, 9100, f138, M68000);
5336 INSN(subx_mem, 9108, f138, M68000);
0402f767 5337 INSN(suba, 91c0, f1c0, CF_ISA_A);
415f4b62 5338 INSN(suba, 90c0, f0c0, M68000);
acf930aa 5339
f076803b 5340 BASE(undef_mac, a000, f000);
acf930aa
PB		 5341 INSN(mac, a000, f100, CF_EMAC);
5342 INSN(from_mac, a180, f9b0, CF_EMAC);
5343 INSN(move_mac, a110, f9fc, CF_EMAC);
5344 INSN(from_macsr,a980, f9f0, CF_EMAC);
5345 INSN(from_mask, ad80, fff0, CF_EMAC);
5346 INSN(from_mext, ab80, fbf0, CF_EMAC);
5347 INSN(macsr_to_ccr, a9c0, ffff, CF_EMAC);
5348 INSN(to_mac, a100, f9c0, CF_EMAC);
5349 INSN(to_macsr, a900, ffc0, CF_EMAC);
5350 INSN(to_mext, ab00, fbc0, CF_EMAC);
5351 INSN(to_mask, ad00, ffc0, CF_EMAC);
5352
0402f767
PB		 5353 INSN(mov3q, a140, f1c0, CF_ISA_B);
5354 INSN(cmp, b000, f1c0, CF_ISA_B); /* cmp.b */
5355 INSN(cmp, b040, f1c0, CF_ISA_B); /* cmp.w */
5356 INSN(cmpa, b0c0, f1c0, CF_ISA_B); /* cmpa.w */
5357 INSN(cmp, b080, f1c0, CF_ISA_A);
5358 INSN(cmpa, b1c0, f1c0, CF_ISA_A);
f076803b
LV		 5359 INSN(cmp, b000, f100, M68000);
5360 INSN(eor, b100, f100, M68000);
817af1c7 5361 INSN(cmpm, b108, f138, M68000);
f076803b 5362 INSN(cmpa, b0c0, f0c0, M68000);
0402f767 5363 INSN(eor, b180, f1c0, CF_ISA_A);
f076803b 5364 BASE(and, c000, f000);
29cf437d
LV		 5365 INSN(exg_dd, c140, f1f8, M68000);
5366 INSN(exg_aa, c148, f1f8, M68000);
5367 INSN(exg_da, c188, f1f8, M68000);
f076803b 5368 BASE(mulw, c0c0, f0c0);
fb5543d8
LV		 5369 INSN(abcd_reg, c100, f1f8, M68000);
5370 INSN(abcd_mem, c108, f1f8, M68000);
f076803b 5371 BASE(addsub, d000, f000);
a665a820
RH		 5372 INSN(undef, d0c0, f0c0, CF_ISA_A);
5373 INSN(addx_reg, d180, f1f8, CF_ISA_A);
5374 INSN(addx_reg, d100, f138, M68000);
5375 INSN(addx_mem, d108, f138, M68000);
0402f767 5376 INSN(adda, d1c0, f1c0, CF_ISA_A);
f076803b 5377 INSN(adda, d0c0, f0c0, M68000);
0402f767
PB		 5378 INSN(shift_im, e080, f0f0, CF_ISA_A);
5379 INSN(shift_reg, e0a0, f0f0, CF_ISA_A);
367790cc
RH		 5380 INSN(shift8_im, e000, f0f0, M68000);
5381 INSN(shift16_im, e040, f0f0, M68000);
5382 INSN(shift_im, e080, f0f0, M68000);
5383 INSN(shift8_reg, e020, f0f0, M68000);
5384 INSN(shift16_reg, e060, f0f0, M68000);
5385 INSN(shift_reg, e0a0, f0f0, M68000);
5386 INSN(shift_mem, e0c0, fcc0, M68000);
0194cf31
LV		 5387 INSN(rotate_im, e090, f0f0, M68000);
5388 INSN(rotate8_im, e010, f0f0, M68000);
5389 INSN(rotate16_im, e050, f0f0, M68000);
5390 INSN(rotate_reg, e0b0, f0f0, M68000);
5391 INSN(rotate8_reg, e030, f0f0, M68000);
5392 INSN(rotate16_reg, e070, f0f0, M68000);
5393 INSN(rotate_mem, e4c0, fcc0, M68000);
f2224f2c
RH		 5394 INSN(bfext_mem, e9c0, fdc0, BITFIELD); /* bfextu & bfexts */
5395 INSN(bfext_reg, e9c0, fdf8, BITFIELD);
5396 INSN(bfins_mem, efc0, ffc0, BITFIELD);
ac815f46 5397 INSN(bfins_reg, efc0, fff8, BITFIELD);
f2224f2c 5398 INSN(bfop_mem, eac0, ffc0, BITFIELD); /* bfchg */
ac815f46 5399 INSN(bfop_reg, eac0, fff8, BITFIELD); /* bfchg */
f2224f2c 5400 INSN(bfop_mem, ecc0, ffc0, BITFIELD); /* bfclr */
ac815f46 5401 INSN(bfop_reg, ecc0, fff8, BITFIELD); /* bfclr */
a45f1763
RH		 5402 INSN(bfop_mem, edc0, ffc0, BITFIELD); /* bfffo */
5403 INSN(bfop_reg, edc0, fff8, BITFIELD); /* bfffo */
f2224f2c 5404 INSN(bfop_mem, eec0, ffc0, BITFIELD); /* bfset */
ac815f46 5405 INSN(bfop_reg, eec0, fff8, BITFIELD); /* bfset */
f2224f2c 5406 INSN(bfop_mem, e8c0, ffc0, BITFIELD); /* bftst */
ac815f46 5407 INSN(bfop_reg, e8c0, fff8, BITFIELD); /* bftst */
f83311e4 5408 BASE(undef_fpu, f000, f000);
e6e5906b
PB		 5409 INSN(fpu, f200, ffc0, CF_FPU);
5410 INSN(fbcc, f280, ffc0, CF_FPU);
0633879f 5411 INSN(frestore, f340, ffc0, CF_FPU);
f83311e4
LV		 5412 INSN(fsave, f300, ffc0, CF_FPU);
5413 INSN(fpu, f200, ffc0, FPU);
dd337bf8 5414 INSN(fscc, f240, ffc0, FPU);
f83311e4
LV		 5415 INSN(fbcc, f280, ff80, FPU);
5416 INSN(frestore, f340, ffc0, FPU);
5417 INSN(fsave, f300, ffc0, FPU);
0402f767
PB		 5418 INSN(intouch, f340, ffc0, CF_ISA_A);
5419 INSN(cpushl, f428, ff38, CF_ISA_A);
5420 INSN(wddata, fb00, ff00, CF_ISA_A);
5421 INSN(wdebug, fbc0, ffc0, CF_ISA_A);
e6e5906b
PB		 5422#undef INSN
5423}
5424
5425/* ??? Some of this implementation is not exception safe. We should always
5426 write back the result to memory before setting the condition codes. */
2b3e3cfe 5427static void disas_m68k_insn(CPUM68KState * env, DisasContext *s)
e6e5906b 5428{
8a1e52b6 5429 uint16_t insn = read_im16(env, s);
d4d79bb1 5430 opcode_table[insn](env, s, insn);
8a1e52b6 5431 do_writebacks(s);
e6e5906b
PB		 5432}
5433
e6e5906b 5434/* generate intermediate code for basic block 'tb'. */
4e5e1215 5435void gen_intermediate_code(CPUM68KState *env, TranslationBlock *tb)
e6e5906b 5436{
4e5e1215 5437 M68kCPU *cpu = m68k_env_get_cpu(env);
ed2803da 5438 CPUState *cs = CPU(cpu);
e6e5906b 5439 DisasContext dc1, *dc = &dc1;
e6e5906b
PB		 5440 target_ulong pc_start;
5441 int pc_offset;
2e70f6ef
PB		 5442 int num_insns;
5443 int max_insns;
e6e5906b
PB		 5444
5445 /* generate intermediate code */
5446 pc_start = tb->pc;
3b46e624 5447
e6e5906b
PB		 5448 dc->tb = tb;
5449
e6dbd3b3 5450 dc->env = env;
e6e5906b
PB		 5451 dc->is_jmp = DISAS_NEXT;
5452 dc->pc = pc_start;
5453 dc->cc_op = CC_OP_DYNAMIC;
620c6cf6 5454 dc->cc_op_synced = 1;
ed2803da 5455 dc->singlestep_enabled = cs->singlestep_enabled;
0633879f 5456 dc->user = (env->sr & SR_S) == 0;
a7812ae4 5457 dc->done_mac = 0;
8a1e52b6 5458 dc->writeback_mask = 0;
2e70f6ef
PB		 5459 num_insns = 0;
5460 max_insns = tb->cflags & CF_COUNT_MASK;
190ce7fb 5461 if (max_insns == 0) {
2e70f6ef 5462 max_insns = CF_COUNT_MASK;
190ce7fb
RH		 5463 }
5464 if (max_insns > TCG_MAX_INSNS) {
5465 max_insns = TCG_MAX_INSNS;
5466 }
2e70f6ef 5467
cd42d5b2 5468 gen_tb_start(tb);
e6e5906b 5469 do {
e6e5906b
PB		 5470 pc_offset = dc->pc - pc_start;
5471 gen_throws_exception = NULL;
20a8856e 5472 tcg_gen_insn_start(dc->pc, dc->cc_op);
959082fc 5473 num_insns++;
667b8e29 5474
b933066a
RH		 5475 if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) {
5476 gen_exception(dc, dc->pc, EXCP_DEBUG);
5477 dc->is_jmp = DISAS_JUMP;
522a0d4e
RH		 5478 /* The address covered by the breakpoint must be included in
5479 [tb->pc, tb->pc + tb->size) in order to for it to be
5480 properly cleared -- thus we increment the PC here so that
5481 the logic setting tb->size below does the right thing. */
5482 dc->pc += 2;
b933066a
RH		 5483 break;
5484 }
5485
959082fc 5486 if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
2e70f6ef 5487 gen_io_start();
667b8e29
RH		 5488 }
5489
510ff0b7 5490 dc->insn_pc = dc->pc;
e6e5906b 5491 disas_m68k_insn(env, dc);
fe700adb 5492 } while (!dc->is_jmp && !tcg_op_buf_full() &&
ed2803da 5493 !cs->singlestep_enabled &&
1b530a6d 5494 !singlestep &&
2e70f6ef
PB		 5495 (pc_offset) < (TARGET_PAGE_SIZE - 32) &&
5496 num_insns < max_insns);
e6e5906b 5497
2e70f6ef
PB		 5498 if (tb->cflags & CF_LAST_IO)
5499 gen_io_end();
ed2803da 5500 if (unlikely(cs->singlestep_enabled)) {
e6e5906b
PB		 5501 /* Make sure the pc is updated, and raise a debug exception. */
5502 if (!dc->is_jmp) {
9fdb533f 5503 update_cc_op(dc);
e1f3808e 5504 tcg_gen_movi_i32(QREG_PC, dc->pc);
e6e5906b 5505 }
31871141 5506 gen_helper_raise_exception(cpu_env, tcg_const_i32(EXCP_DEBUG));
e6e5906b
PB		 5507 } else {
5508 switch(dc->is_jmp) {
5509 case DISAS_NEXT:
9fdb533f 5510 update_cc_op(dc);
e6e5906b
PB		 5511 gen_jmp_tb(dc, 0, dc->pc);
5512 break;
5513 default:
5514 case DISAS_JUMP:
5515 case DISAS_UPDATE:
9fdb533f 5516 update_cc_op(dc);
e6e5906b 5517 /* indicate that the hash table must be used to find the next TB */
57fec1fe 5518 tcg_gen_exit_tb(0);
e6e5906b
PB		 5519 break;
5520 case DISAS_TB_JUMP:
5521 /* nothing more to generate */
5522 break;
5523 }
5524 }
806f352d 5525 gen_tb_end(tb, num_insns);
e6e5906b
PB		 5526
5527#ifdef DEBUG_DISAS
4910e6e4
RH		 5528 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)
5529 && qemu_log_in_addr_range(pc_start)) {
1ee73216 5530 qemu_log_lock();
93fcfe39
AL		 5531 qemu_log("----------------\n");
5532 qemu_log("IN: %s\n", lookup_symbol(pc_start));
d49190c4 5533 log_target_disas(cs, pc_start, dc->pc - pc_start, 0);
93fcfe39 5534 qemu_log("\n");
1ee73216 5535 qemu_log_unlock();
e6e5906b
PB		 5536 }
5537#endif
4e5e1215
RH		 5538 tb->size = dc->pc - pc_start;
5539 tb->icount = num_insns;
e6e5906b
PB		 5540}
5541
f83311e4
LV		 5542static double floatx80_to_double(CPUM68KState *env, uint16_t high, uint64_t low)
5543{
5544 floatx80 a = { .high = high, .low = low };
5545 union {
5546 float64 f64;
5547 double d;
5548 } u;
5549
5550 u.f64 = floatx80_to_float64(a, &env->fp_status);
5551 return u.d;
5552}
5553
878096ee
AF		 5554void m68k_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
5555 int flags)
e6e5906b 5556{
878096ee
AF		 5557 M68kCPU *cpu = M68K_CPU(cs);
5558 CPUM68KState *env = &cpu->env;
e6e5906b
PB		 5559 int i;
5560 uint16_t sr;
f83311e4
LV		 5561 for (i = 0; i < 8; i++) {
5562 cpu_fprintf(f, "D%d = %08x A%d = %08x "
5563 "F%d = %04x %016"PRIx64" (%12g)\n",
8e394cca 5564 i, env->dregs[i], i, env->aregs[i],
f83311e4
LV		 5565 i, env->fregs[i].l.upper, env->fregs[i].l.lower,
5566 floatx80_to_double(env, env->fregs[i].l.upper,
5567 env->fregs[i].l.lower));
5568 }
e6e5906b 5569 cpu_fprintf (f, "PC = %08x ", env->pc);
99c51448 5570 sr = env->sr | cpu_m68k_get_ccr(env);
8e394cca
RH		 5571 cpu_fprintf(f, "SR = %04x %c%c%c%c%c ", sr, (sr & CCF_X) ? 'X' : '-',
5572 (sr & CCF_N) ? 'N' : '-', (sr & CCF_Z) ? 'Z' : '-',
5573 (sr & CCF_V) ? 'V' : '-', (sr & CCF_C) ? 'C' : '-');
ba624944
LV		 5574 cpu_fprintf(f, "FPSR = %08x %c%c%c%c ", env->fpsr,
5575 (env->fpsr & FPSR_CC_A) ? 'A' : '-',
5576 (env->fpsr & FPSR_CC_I) ? 'I' : '-',
5577 (env->fpsr & FPSR_CC_Z) ? 'Z' : '-',
5578 (env->fpsr & FPSR_CC_N) ? 'N' : '-');
5579 cpu_fprintf(f, "\n "
5580 "FPCR = %04x ", env->fpcr);
5581 switch (env->fpcr & FPCR_PREC_MASK) {
5582 case FPCR_PREC_X:
5583 cpu_fprintf(f, "X ");
5584 break;
5585 case FPCR_PREC_S:
5586 cpu_fprintf(f, "S ");
5587 break;
5588 case FPCR_PREC_D:
5589 cpu_fprintf(f, "D ");
5590 break;
5591 }
5592 switch (env->fpcr & FPCR_RND_MASK) {
5593 case FPCR_RND_N:
5594 cpu_fprintf(f, "RN ");
5595 break;
5596 case FPCR_RND_Z:
5597 cpu_fprintf(f, "RZ ");
5598 break;
5599 case FPCR_RND_M:
5600 cpu_fprintf(f, "RM ");
5601 break;
5602 case FPCR_RND_P:
5603 cpu_fprintf(f, "RP ");
5604 break;
5605 }
e6e5906b
PB		 5606}
5607
bad729e2
RH		 5608void restore_state_to_opc(CPUM68KState *env, TranslationBlock *tb,
5609 target_ulong *data)
d2856f1a 5610{
20a8856e 5611 int cc_op = data[1];
bad729e2 5612 env->pc = data[0];
20a8856e
LV		 5613 if (cc_op != CC_OP_DYNAMIC) {
5614 env->cc_op = cc_op;
5615 }
d2856f1a 5616}
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