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Move QOM typedefs and add missing includes
[qemu.git] / hw / display / qxl.c
CommitLineData
a19cbfb3
GH		 1/*
2 * Copyright (C) 2010 Red Hat, Inc.
3 *
4 * written by Yaniv Kamay, Izik Eidus, Gerd Hoffmann
5 * maintained by Gerd Hoffmann <[email protected]>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 or
10 * (at your option) version 3 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, see <http://www.gnu.org/licenses/>.
19 */
20
47df5154 21#include "qemu/osdep.h"
f0353b0d 22#include "qemu/units.h"
a639ab04
AL		 23#include <zlib.h>
24
e688df6b 25#include "qapi/error.h"
1de7afc9
PB		 26#include "qemu/timer.h"
27#include "qemu/queue.h"
5444e768 28#include "qemu/atomic.h"
db725815 29#include "qemu/main-loop.h"
0b8fa32f 30#include "qemu/module.h"
a27bd6c7 31#include "hw/qdev-properties.h"
54d31236 32#include "sysemu/runstate.h"
795c40b8 33#include "migration/blocker.h"
d6454270 34#include "migration/vmstate.h"
c480bb7d 35#include "trace.h"
a19cbfb3 36
47b43a1f 37#include "qxl.h"
a19cbfb3 38
a19cbfb3 39#undef SPICE_RING_CONS_ITEM
0b81c478 40#define SPICE_RING_CONS_ITEM(qxl, r, ret) { \
a19cbfb3 41 uint32_t cons = (r)->cons & SPICE_RING_INDEX_MASK(r); \
bc5f92e5 42 if (cons >= ARRAY_SIZE((r)->items)) { \
0a530548 43 qxl_set_guest_bug(qxl, "SPICE_RING_CONS_ITEM indices mismatch " \
bc5f92e5 44 "%u >= %zu", cons, ARRAY_SIZE((r)->items)); \
0b81c478
AL		 45 ret = NULL; \
46 } else { \
bc5f92e5 47 ret = &(r)->items[cons].el; \
a19cbfb3 48 } \
a19cbfb3
GH		 49 }
50
51#undef ALIGN
52#define ALIGN(a, b) (((a) + ((b) - 1)) & ~((b) - 1))
53
54#define PIXEL_SIZE 0.2936875 //1280x1024 is 14.8" x 11.9"
55
56#define QXL_MODE(_x, _y, _b, _o) \
57 { .x_res = _x, \
58 .y_res = _y, \
59 .bits = _b, \
60 .stride = (_x) * (_b) / 8, \
61 .x_mili = PIXEL_SIZE * (_x), \
62 .y_mili = PIXEL_SIZE * (_y), \
63 .orientation = _o, \
64 }
65
66#define QXL_MODE_16_32(x_res, y_res, orientation) \
67 QXL_MODE(x_res, y_res, 16, orientation), \
68 QXL_MODE(x_res, y_res, 32, orientation)
69
70#define QXL_MODE_EX(x_res, y_res) \
71 QXL_MODE_16_32(x_res, y_res, 0), \
038c1879 72 QXL_MODE_16_32(x_res, y_res, 1)
a19cbfb3
GH		 73
74static QXLMode qxl_modes[] = {
75 QXL_MODE_EX(640, 480),
76 QXL_MODE_EX(800, 480),
77 QXL_MODE_EX(800, 600),
78 QXL_MODE_EX(832, 624),
79 QXL_MODE_EX(960, 640),
80 QXL_MODE_EX(1024, 600),
81 QXL_MODE_EX(1024, 768),
82 QXL_MODE_EX(1152, 864),
83 QXL_MODE_EX(1152, 870),
84 QXL_MODE_EX(1280, 720),
85 QXL_MODE_EX(1280, 760),
86 QXL_MODE_EX(1280, 768),
87 QXL_MODE_EX(1280, 800),
88 QXL_MODE_EX(1280, 960),
89 QXL_MODE_EX(1280, 1024),
90 QXL_MODE_EX(1360, 768),
91 QXL_MODE_EX(1366, 768),
92 QXL_MODE_EX(1400, 1050),
93 QXL_MODE_EX(1440, 900),
94 QXL_MODE_EX(1600, 900),
95 QXL_MODE_EX(1600, 1200),
96 QXL_MODE_EX(1680, 1050),
97 QXL_MODE_EX(1920, 1080),
a19cbfb3
GH		 98 /* these modes need more than 8 MB video memory */
99 QXL_MODE_EX(1920, 1200),
100 QXL_MODE_EX(1920, 1440),
5c74fb27 101 QXL_MODE_EX(2000, 2000),
a19cbfb3 102 QXL_MODE_EX(2048, 1536),
5c74fb27 103 QXL_MODE_EX(2048, 2048),
a19cbfb3
GH		 104 QXL_MODE_EX(2560, 1440),
105 QXL_MODE_EX(2560, 1600),
a19cbfb3
GH		 106 /* these modes need more than 16 MB video memory */
107 QXL_MODE_EX(2560, 2048),
108 QXL_MODE_EX(2800, 2100),
109 QXL_MODE_EX(3200, 2400),
03d9825d 110 /* these modes need more than 32 MB video memory */
d4bcb199
GH		 111 QXL_MODE_EX(3840, 2160), /* 4k mainstream */
112 QXL_MODE_EX(4096, 2160), /* 4k */
03d9825d 113 /* these modes need more than 64 MB video memory */
d4bcb199 114 QXL_MODE_EX(7680, 4320), /* 8k mainstream */
03d9825d 115 /* these modes need more than 128 MB video memory */
d4bcb199 116 QXL_MODE_EX(8192, 4320), /* 8k */
a19cbfb3
GH		 117};
118
a19cbfb3 119static void qxl_send_events(PCIQXLDevice *d, uint32_t events);
5ff4e36c 120static int qxl_destroy_primary(PCIQXLDevice *d, qxl_async_io async);
a19cbfb3
GH		 121static void qxl_reset_memslots(PCIQXLDevice *d);
122static void qxl_reset_surfaces(PCIQXLDevice *d);
123static void qxl_ring_set_dirty(PCIQXLDevice *qxl);
124
15162335
GH		 125static void qxl_hw_update(void *opaque);
126
0a530548 127void qxl_set_guest_bug(PCIQXLDevice *qxl, const char *msg, ...)
2bce0400 128{
917ae08c 129 trace_qxl_set_guest_bug(qxl->id);
2bce0400 130 qxl_send_events(qxl, QXL_INTERRUPT_ERROR);
087e6a42 131 qxl->guest_bug = 1;
2bce0400 132 if (qxl->guestdebug) {
7635392c
AL		 133 va_list ap;
134 va_start(ap, msg);
135 fprintf(stderr, "qxl-%d: guest bug: ", qxl->id);
136 vfprintf(stderr, msg, ap);
137 fprintf(stderr, "\n");
138 va_end(ap);
2bce0400
GH		 139 }
140}
141
087e6a42
AL		 142static void qxl_clear_guest_bug(PCIQXLDevice *qxl)
143{
144 qxl->guest_bug = 0;
145}
aee32bf3
GH		 146
147void qxl_spice_update_area(PCIQXLDevice *qxl, uint32_t surface_id,
148 struct QXLRect *area, struct QXLRect *dirty_rects,
149 uint32_t num_dirty_rects,
5ff4e36c 150 uint32_t clear_dirty_region,
2e1a98c9 151 qxl_async_io async, struct QXLCookie *cookie)
aee32bf3 152{
c480bb7d
AL		 153 trace_qxl_spice_update_area(qxl->id, surface_id, area->left, area->right,
154 area->top, area->bottom);
155 trace_qxl_spice_update_area_rest(qxl->id, num_dirty_rects,
156 clear_dirty_region);
5ff4e36c 157 if (async == QXL_SYNC) {
26defe81 158 spice_qxl_update_area(&qxl->ssd.qxl, surface_id, area,
5ff4e36c
AL		 159 dirty_rects, num_dirty_rects, clear_dirty_region);
160 } else {
2e1a98c9 161 assert(cookie != NULL);
5ff4e36c 162 spice_qxl_update_area_async(&qxl->ssd.qxl, surface_id, area,
5dba0d45 163 clear_dirty_region, (uintptr_t)cookie);
5ff4e36c 164 }
aee32bf3
GH		 165}
166
5ff4e36c
AL		 167static void qxl_spice_destroy_surface_wait_complete(PCIQXLDevice *qxl,
168 uint32_t id)
aee32bf3 169{
c480bb7d 170 trace_qxl_spice_destroy_surface_wait_complete(qxl->id, id);
14898cf6 171 qemu_mutex_lock(&qxl->track_lock);
14898cf6
GH		 172 qxl->guest_surfaces.cmds[id] = 0;
173 qxl->guest_surfaces.count--;
174 qemu_mutex_unlock(&qxl->track_lock);
aee32bf3
GH		 175}
176
5ff4e36c
AL		 177static void qxl_spice_destroy_surface_wait(PCIQXLDevice *qxl, uint32_t id,
178 qxl_async_io async)
179{
2e1a98c9
AL		 180 QXLCookie *cookie;
181
c480bb7d 182 trace_qxl_spice_destroy_surface_wait(qxl->id, id, async);
5ff4e36c 183 if (async) {
2e1a98c9
AL		 184 cookie = qxl_cookie_new(QXL_COOKIE_TYPE_IO,
185 QXL_IO_DESTROY_SURFACE_ASYNC);
186 cookie->u.surface_id = id;
5dba0d45 187 spice_qxl_destroy_surface_async(&qxl->ssd.qxl, id, (uintptr_t)cookie);
5ff4e36c 188 } else {
26defe81 189 spice_qxl_destroy_surface_wait(&qxl->ssd.qxl, id);
753b8b0d 190 qxl_spice_destroy_surface_wait_complete(qxl, id);
5ff4e36c
AL		 191 }
192}
193
3e16b9c5
AL		 194static void qxl_spice_flush_surfaces_async(PCIQXLDevice *qxl)
195{
c480bb7d
AL		 196 trace_qxl_spice_flush_surfaces_async(qxl->id, qxl->guest_surfaces.count,
197 qxl->num_free_res);
2e1a98c9 198 spice_qxl_flush_surfaces_async(&qxl->ssd.qxl,
5dba0d45
PM		 199 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO,
200 QXL_IO_FLUSH_SURFACES_ASYNC));
3e16b9c5 201}
3e16b9c5 202
aee32bf3
GH		 203void qxl_spice_loadvm_commands(PCIQXLDevice *qxl, struct QXLCommandExt *ext,
204 uint32_t count)
205{
c480bb7d 206 trace_qxl_spice_loadvm_commands(qxl->id, ext, count);
26defe81 207 spice_qxl_loadvm_commands(&qxl->ssd.qxl, ext, count);
aee32bf3
GH		 208}
209
210void qxl_spice_oom(PCIQXLDevice *qxl)
211{
c480bb7d 212 trace_qxl_spice_oom(qxl->id);
26defe81 213 spice_qxl_oom(&qxl->ssd.qxl);
aee32bf3
GH		 214}
215
216void qxl_spice_reset_memslots(PCIQXLDevice *qxl)
217{
c480bb7d 218 trace_qxl_spice_reset_memslots(qxl->id);
26defe81 219 spice_qxl_reset_memslots(&qxl->ssd.qxl);
aee32bf3
GH		 220}
221
5ff4e36c 222static void qxl_spice_destroy_surfaces_complete(PCIQXLDevice *qxl)
aee32bf3 223{
c480bb7d 224 trace_qxl_spice_destroy_surfaces_complete(qxl->id);
14898cf6 225 qemu_mutex_lock(&qxl->track_lock);
ddd8fdc7 226 memset(qxl->guest_surfaces.cmds, 0,
8bb9f51c 227 sizeof(qxl->guest_surfaces.cmds[0]) * qxl->ssd.num_surfaces);
14898cf6
GH		 228 qxl->guest_surfaces.count = 0;
229 qemu_mutex_unlock(&qxl->track_lock);
aee32bf3
GH		 230}
231
5ff4e36c
AL		 232static void qxl_spice_destroy_surfaces(PCIQXLDevice *qxl, qxl_async_io async)
233{
c480bb7d 234 trace_qxl_spice_destroy_surfaces(qxl->id, async);
5ff4e36c 235 if (async) {
2e1a98c9 236 spice_qxl_destroy_surfaces_async(&qxl->ssd.qxl,
5dba0d45
PM		 237 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO,
238 QXL_IO_DESTROY_ALL_SURFACES_ASYNC));
5ff4e36c 239 } else {
26defe81 240 spice_qxl_destroy_surfaces(&qxl->ssd.qxl);
5ff4e36c
AL		 241 qxl_spice_destroy_surfaces_complete(qxl);
242 }
243}
244
020af1c4
AL		 245static void qxl_spice_monitors_config_async(PCIQXLDevice *qxl, int replay)
246{
979f7ef8
GH		 247 QXLMonitorsConfig *cfg;
248
020af1c4 249 trace_qxl_spice_monitors_config(qxl->id);
020af1c4
AL		 250 if (replay) {
251 /*
252 * don't use QXL_COOKIE_TYPE_IO:
253 * - we are not running yet (post_load), we will assert
254 * in send_events
255 * - this is not a guest io, but a reply, so async_io isn't set.
256 */
257 spice_qxl_monitors_config_async(&qxl->ssd.qxl,
258 qxl->guest_monitors_config,
259 MEMSLOT_GROUP_GUEST,
260 (uintptr_t)qxl_cookie_new(
261 QXL_COOKIE_TYPE_POST_LOAD_MONITORS_CONFIG,
262 0));
263 } else {
be812c0a
LH		 264/* >= release 0.12.6, < release 0.14.2 */
265#if SPICE_SERVER_VERSION >= 0x000c06 && SPICE_SERVER_VERSION < 0x000e02
567161fd 266 if (qxl->max_outputs) {
a52b2cbf 267 spice_qxl_set_max_monitors(&qxl->ssd.qxl, qxl->max_outputs);
567161fd
FZ		 268 }
269#endif
020af1c4
AL		 270 qxl->guest_monitors_config = qxl->ram->monitors_config;
271 spice_qxl_monitors_config_async(&qxl->ssd.qxl,
272 qxl->ram->monitors_config,
273 MEMSLOT_GROUP_GUEST,
274 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO,
275 QXL_IO_MONITORS_CONFIG_ASYNC));
276 }
979f7ef8
GH		 277
278 cfg = qxl_phys2virt(qxl, qxl->guest_monitors_config, MEMSLOT_GROUP_GUEST);
2f99f80c 279 if (cfg != NULL && cfg->count == 1) {
979f7ef8
GH		 280 qxl->guest_primary.resized = 1;
281 qxl->guest_head0_width = cfg->heads[0].width;
282 qxl->guest_head0_height = cfg->heads[0].height;
283 } else {
284 qxl->guest_head0_width = 0;
285 qxl->guest_head0_height = 0;
286 }
020af1c4
AL		 287}
288
aee32bf3
GH		 289void qxl_spice_reset_image_cache(PCIQXLDevice *qxl)
290{
c480bb7d 291 trace_qxl_spice_reset_image_cache(qxl->id);
26defe81 292 spice_qxl_reset_image_cache(&qxl->ssd.qxl);
aee32bf3
GH		 293}
294
295void qxl_spice_reset_cursor(PCIQXLDevice *qxl)
296{
c480bb7d 297 trace_qxl_spice_reset_cursor(qxl->id);
26defe81 298 spice_qxl_reset_cursor(&qxl->ssd.qxl);
30f6da66
YH		 299 qemu_mutex_lock(&qxl->track_lock);
300 qxl->guest_cursor = 0;
301 qemu_mutex_unlock(&qxl->track_lock);
958c2bce
GH		 302 if (qxl->ssd.cursor) {
303 cursor_put(qxl->ssd.cursor);
304 }
305 qxl->ssd.cursor = cursor_builtin_hidden();
aee32bf3
GH		 306}
307
6f663d7b
GH		 308static uint32_t qxl_crc32(const uint8_t *p, unsigned len)
309{
310 /*
311 * zlib xors the seed with 0xffffffff, and xors the result
312 * again with 0xffffffff; Both are not done with linux's crc32,
313 * which we want to be compatible with, so undo that.
314 */
315 return crc32(0xffffffff, p, len) ^ 0xffffffff;
316}
317
a19cbfb3
GH		 318static ram_addr_t qxl_rom_size(void)
319{
df45892c
MT		 320#define QXL_REQUIRED_SZ (sizeof(QXLRom) + sizeof(QXLModes) + sizeof(qxl_modes))
321#define QXL_ROM_SZ 8192
13d1fd44 322
df45892c
MT		 323 QEMU_BUILD_BUG_ON(QXL_REQUIRED_SZ > QXL_ROM_SZ);
324 return QXL_ROM_SZ;
a19cbfb3
GH		 325}
326
327static void init_qxl_rom(PCIQXLDevice *d)
328{
b1950430 329 QXLRom *rom = memory_region_get_ram_ptr(&d->rom_bar);
a19cbfb3
GH		 330 QXLModes *modes = (QXLModes *)(rom + 1);
331 uint32_t ram_header_size;
332 uint32_t surface0_area_size;
333 uint32_t num_pages;
13d1fd44
AL		 334 uint32_t fb;
335 int i, n;
a19cbfb3
GH		 336
337 memset(rom, 0, d->rom_size);
338
339 rom->magic = cpu_to_le32(QXL_ROM_MAGIC);
340 rom->id = cpu_to_le32(d->id);
341 rom->log_level = cpu_to_le32(d->guestdebug);
342 rom->modes_offset = cpu_to_le32(sizeof(QXLRom));
343
344 rom->slot_gen_bits = MEMSLOT_GENERATION_BITS;
345 rom->slot_id_bits = MEMSLOT_SLOT_BITS;
346 rom->slots_start = 1;
347 rom->slots_end = NUM_MEMSLOTS - 1;
ddd8fdc7 348 rom->n_surfaces = cpu_to_le32(d->ssd.num_surfaces);
a19cbfb3 349
13d1fd44 350 for (i = 0, n = 0; i < ARRAY_SIZE(qxl_modes); i++) {
a19cbfb3 351 fb = qxl_modes[i].y_res * qxl_modes[i].stride;
13d1fd44
AL		 352 if (fb > d->vgamem_size) {
353 continue;
a19cbfb3 354 }
13d1fd44
AL		 355 modes->modes[n].id = cpu_to_le32(i);
356 modes->modes[n].x_res = cpu_to_le32(qxl_modes[i].x_res);
357 modes->modes[n].y_res = cpu_to_le32(qxl_modes[i].y_res);
358 modes->modes[n].bits = cpu_to_le32(qxl_modes[i].bits);
359 modes->modes[n].stride = cpu_to_le32(qxl_modes[i].stride);
360 modes->modes[n].x_mili = cpu_to_le32(qxl_modes[i].x_mili);
361 modes->modes[n].y_mili = cpu_to_le32(qxl_modes[i].y_mili);
362 modes->modes[n].orientation = cpu_to_le32(qxl_modes[i].orientation);
363 n++;
364 }
365 modes->n_modes = cpu_to_le32(n);
a19cbfb3
GH		 366
367 ram_header_size = ALIGN(sizeof(QXLRam), 4096);
13d1fd44 368 surface0_area_size = ALIGN(d->vgamem_size, 4096);
a19cbfb3
GH		 369 num_pages = d->vga.vram_size;
370 num_pages -= ram_header_size;
371 num_pages -= surface0_area_size;
9efc2d8d 372 num_pages = num_pages / QXL_PAGE_SIZE;
a19cbfb3 373
876d5163
RK		 374 assert(ram_header_size + surface0_area_size <= d->vga.vram_size);
375
a19cbfb3
GH		 376 rom->draw_area_offset = cpu_to_le32(0);
377 rom->surface0_area_size = cpu_to_le32(surface0_area_size);
378 rom->pages_offset = cpu_to_le32(surface0_area_size);
379 rom->num_pages = cpu_to_le32(num_pages);
380 rom->ram_header_offset = cpu_to_le32(d->vga.vram_size - ram_header_size);
381
6f663d7b
GH		 382 if (d->xres && d->yres) {
383 /* needs linux kernel 4.12+ to work */
384 rom->client_monitors_config.count = 1;
385 rom->client_monitors_config.heads[0].left = 0;
386 rom->client_monitors_config.heads[0].top = 0;
387 rom->client_monitors_config.heads[0].right = cpu_to_le32(d->xres);
388 rom->client_monitors_config.heads[0].bottom = cpu_to_le32(d->yres);
389 rom->client_monitors_config_crc = qxl_crc32(
390 (const uint8_t *)&rom->client_monitors_config,
391 sizeof(rom->client_monitors_config));
392 }
393
a19cbfb3
GH		 394 d->shadow_rom = *rom;
395 d->rom = rom;
396 d->modes = modes;
397}
398
399static void init_qxl_ram(PCIQXLDevice *d)
400{
401 uint8_t *buf;
94932c95
DB		 402 uint32_t prod;
403 QXLReleaseRing *ring;
a19cbfb3
GH		 404
405 buf = d->vga.vram_ptr;
406 d->ram = (QXLRam *)(buf + le32_to_cpu(d->shadow_rom.ram_header_offset));
407 d->ram->magic = cpu_to_le32(QXL_RAM_MAGIC);
408 d->ram->int_pending = cpu_to_le32(0);
409 d->ram->int_mask = cpu_to_le32(0);
9f0f352d 410 d->ram->update_surface = 0;
329f97fc 411 d->ram->monitors_config = 0;
a19cbfb3
GH		 412 SPICE_RING_INIT(&d->ram->cmd_ring);
413 SPICE_RING_INIT(&d->ram->cursor_ring);
414 SPICE_RING_INIT(&d->ram->release_ring);
94932c95
DB		 415
416 ring = &d->ram->release_ring;
417 prod = ring->prod & SPICE_RING_INDEX_MASK(ring);
418 assert(prod < ARRAY_SIZE(ring->items));
419 ring->items[prod].el = 0;
420
a19cbfb3
GH		 421 qxl_ring_set_dirty(d);
422}
423
424/* can be called from spice server thread context */
b1950430 425static void qxl_set_dirty(MemoryRegion *mr, ram_addr_t addr, ram_addr_t end)
a19cbfb3 426{
fd4aa979 427 memory_region_set_dirty(mr, addr, end - addr);
a19cbfb3
GH		 428}
429
430static void qxl_rom_set_dirty(PCIQXLDevice *qxl)
431{
b1950430 432 qxl_set_dirty(&qxl->rom_bar, 0, qxl->rom_size);
a19cbfb3
GH		 433}
434
435/* called from spice server thread context only */
436static void qxl_ram_set_dirty(PCIQXLDevice *qxl, void *ptr)
437{
a19cbfb3
GH		 438 void *base = qxl->vga.vram_ptr;
439 intptr_t offset;
440
441 offset = ptr - base;
a19cbfb3 442 assert(offset < qxl->vga.vram_size);
b0297b4a 443 qxl_set_dirty(&qxl->vga.vram, offset, offset + 3);
a19cbfb3
GH		 444}
445
446/* can be called from spice server thread context */
447static void qxl_ring_set_dirty(PCIQXLDevice *qxl)
448{
b1950430
AK		 449 ram_addr_t addr = qxl->shadow_rom.ram_header_offset;
450 ram_addr_t end = qxl->vga.vram_size;
451 qxl_set_dirty(&qxl->vga.vram, addr, end);
a19cbfb3
GH		 452}
453
454/*
455 * keep track of some command state, for savevm/loadvm.
456 * called from spice server thread context only
457 */
fae2afb1 458static int qxl_track_command(PCIQXLDevice *qxl, struct QXLCommandExt *ext)
a19cbfb3
GH		 459{
460 switch (le32_to_cpu(ext->cmd.type)) {
461 case QXL_CMD_SURFACE:
462 {
463 QXLSurfaceCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id);
fae2afb1
AL		 464
465 if (!cmd) {
466 return 1;
467 }
a19cbfb3 468 uint32_t id = le32_to_cpu(cmd->surface_id);
47eddfbf 469
ddd8fdc7 470 if (id >= qxl->ssd.num_surfaces) {
0a530548 471 qxl_set_guest_bug(qxl, "QXL_CMD_SURFACE id %d >= %d", id,
ddd8fdc7 472 qxl->ssd.num_surfaces);
47eddfbf
AL		 473 return 1;
474 }
48f4ba67
AL		 475 if (cmd->type == QXL_SURFACE_CMD_CREATE &&
476 (cmd->u.surface_create.stride & 0x03) != 0) {
477 qxl_set_guest_bug(qxl, "QXL_CMD_SURFACE stride = %d %% 4 != 0\n",
478 cmd->u.surface_create.stride);
479 return 1;
480 }
6e8a355d
DB		 481 WITH_QEMU_LOCK_GUARD(&qxl->track_lock) {
482 if (cmd->type == QXL_SURFACE_CMD_CREATE) {
483 qxl->guest_surfaces.cmds[id] = ext->cmd.data;
484 qxl->guest_surfaces.count++;
485 if (qxl->guest_surfaces.max < qxl->guest_surfaces.count) {
486 qxl->guest_surfaces.max = qxl->guest_surfaces.count;
487 }
488 }
489 if (cmd->type == QXL_SURFACE_CMD_DESTROY) {
490 qxl->guest_surfaces.cmds[id] = 0;
491 qxl->guest_surfaces.count--;
492 }
a19cbfb3
GH		 493 }
494 break;
495 }
496 case QXL_CMD_CURSOR:
497 {
498 QXLCursorCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id);
fae2afb1
AL		 499
500 if (!cmd) {
501 return 1;
502 }
a19cbfb3 503 if (cmd->type == QXL_CURSOR_SET) {
30f6da66 504 qemu_mutex_lock(&qxl->track_lock);
a19cbfb3 505 qxl->guest_cursor = ext->cmd.data;
30f6da66 506 qemu_mutex_unlock(&qxl->track_lock);
a19cbfb3 507 }
dbb5fb8d
GH		 508 if (cmd->type == QXL_CURSOR_HIDE) {
509 qemu_mutex_lock(&qxl->track_lock);
510 qxl->guest_cursor = 0;
511 qemu_mutex_unlock(&qxl->track_lock);
512 }
a19cbfb3
GH		 513 break;
514 }
515 }
fae2afb1 516 return 0;
a19cbfb3
GH		 517}
518
519/* spice display interface callbacks */
520
521static void interface_attach_worker(QXLInstance *sin, QXLWorker *qxl_worker)
522{
523 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
524
c480bb7d 525 trace_qxl_interface_attach_worker(qxl->id);
a19cbfb3
GH		 526}
527
528static void interface_set_compression_level(QXLInstance *sin, int level)
529{
530 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
531
c480bb7d 532 trace_qxl_interface_set_compression_level(qxl->id, level);
a19cbfb3
GH		 533 qxl->shadow_rom.compression_level = cpu_to_le32(level);
534 qxl->rom->compression_level = cpu_to_le32(level);
535 qxl_rom_set_dirty(qxl);
536}
537
015e02f8 538#if SPICE_NEEDS_SET_MM_TIME
a19cbfb3
GH		 539static void interface_set_mm_time(QXLInstance *sin, uint32_t mm_time)
540{
541 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
542
641381c1
GH		 543 if (!qemu_spice_display_is_running(&qxl->ssd)) {
544 return;
545 }
546
c480bb7d 547 trace_qxl_interface_set_mm_time(qxl->id, mm_time);
a19cbfb3
GH		 548 qxl->shadow_rom.mm_clock = cpu_to_le32(mm_time);
549 qxl->rom->mm_clock = cpu_to_le32(mm_time);
550 qxl_rom_set_dirty(qxl);
551}
015e02f8 552#endif
a19cbfb3
GH		 553
554static void interface_get_init_info(QXLInstance *sin, QXLDevInitInfo *info)
555{
556 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
557
c480bb7d 558 trace_qxl_interface_get_init_info(qxl->id);
a19cbfb3
GH		 559 info->memslot_gen_bits = MEMSLOT_GENERATION_BITS;
560 info->memslot_id_bits = MEMSLOT_SLOT_BITS;
561 info->num_memslots = NUM_MEMSLOTS;
562 info->num_memslots_groups = NUM_MEMSLOTS_GROUPS;
563 info->internal_groupslot_id = 0;
9efc2d8d
GH		 564 info->qxl_ram_size =
565 le32_to_cpu(qxl->shadow_rom.num_pages) << QXL_PAGE_BITS;
ddd8fdc7 566 info->n_surfaces = qxl->ssd.num_surfaces;
a19cbfb3
GH		 567}
568
5b77870c
AL		 569static const char *qxl_mode_to_string(int mode)
570{
571 switch (mode) {
572 case QXL_MODE_COMPAT:
573 return "compat";
574 case QXL_MODE_NATIVE:
575 return "native";
576 case QXL_MODE_UNDEFINED:
577 return "undefined";
578 case QXL_MODE_VGA:
579 return "vga";
580 }
581 return "INVALID";
582}
583
8b92e298
AL		 584static const char *io_port_to_string(uint32_t io_port)
585{
586 if (io_port >= QXL_IO_RANGE_SIZE) {
587 return "out of range";
588 }
589 static const char *io_port_to_string[QXL_IO_RANGE_SIZE + 1] = {
590 [QXL_IO_NOTIFY_CMD] = "QXL_IO_NOTIFY_CMD",
591 [QXL_IO_NOTIFY_CURSOR] = "QXL_IO_NOTIFY_CURSOR",
592 [QXL_IO_UPDATE_AREA] = "QXL_IO_UPDATE_AREA",
593 [QXL_IO_UPDATE_IRQ] = "QXL_IO_UPDATE_IRQ",
594 [QXL_IO_NOTIFY_OOM] = "QXL_IO_NOTIFY_OOM",
595 [QXL_IO_RESET] = "QXL_IO_RESET",
596 [QXL_IO_SET_MODE] = "QXL_IO_SET_MODE",
597 [QXL_IO_LOG] = "QXL_IO_LOG",
598 [QXL_IO_MEMSLOT_ADD] = "QXL_IO_MEMSLOT_ADD",
599 [QXL_IO_MEMSLOT_DEL] = "QXL_IO_MEMSLOT_DEL",
600 [QXL_IO_DETACH_PRIMARY] = "QXL_IO_DETACH_PRIMARY",
601 [QXL_IO_ATTACH_PRIMARY] = "QXL_IO_ATTACH_PRIMARY",
602 [QXL_IO_CREATE_PRIMARY] = "QXL_IO_CREATE_PRIMARY",
603 [QXL_IO_DESTROY_PRIMARY] = "QXL_IO_DESTROY_PRIMARY",
604 [QXL_IO_DESTROY_SURFACE_WAIT] = "QXL_IO_DESTROY_SURFACE_WAIT",
605 [QXL_IO_DESTROY_ALL_SURFACES] = "QXL_IO_DESTROY_ALL_SURFACES",
8b92e298
AL		 606 [QXL_IO_UPDATE_AREA_ASYNC] = "QXL_IO_UPDATE_AREA_ASYNC",
607 [QXL_IO_MEMSLOT_ADD_ASYNC] = "QXL_IO_MEMSLOT_ADD_ASYNC",
608 [QXL_IO_CREATE_PRIMARY_ASYNC] = "QXL_IO_CREATE_PRIMARY_ASYNC",
609 [QXL_IO_DESTROY_PRIMARY_ASYNC] = "QXL_IO_DESTROY_PRIMARY_ASYNC",
610 [QXL_IO_DESTROY_SURFACE_ASYNC] = "QXL_IO_DESTROY_SURFACE_ASYNC",
611 [QXL_IO_DESTROY_ALL_SURFACES_ASYNC]
612 = "QXL_IO_DESTROY_ALL_SURFACES_ASYNC",
613 [QXL_IO_FLUSH_SURFACES_ASYNC] = "QXL_IO_FLUSH_SURFACES_ASYNC",
614 [QXL_IO_FLUSH_RELEASE] = "QXL_IO_FLUSH_RELEASE",
020af1c4 615 [QXL_IO_MONITORS_CONFIG_ASYNC] = "QXL_IO_MONITORS_CONFIG_ASYNC",
8b92e298
AL		 616 };
617 return io_port_to_string[io_port];
618}
619
a19cbfb3
GH		 620/* called from spice server thread context only */
621static int interface_get_command(QXLInstance *sin, struct QXLCommandExt *ext)
622{
623 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
624 SimpleSpiceUpdate *update;
625 QXLCommandRing *ring;
626 QXLCommand *cmd;
e0c64d08 627 int notify, ret;
a19cbfb3 628
c480bb7d
AL		 629 trace_qxl_ring_command_check(qxl->id, qxl_mode_to_string(qxl->mode));
630
a19cbfb3
GH		 631 switch (qxl->mode) {
632 case QXL_MODE_VGA:
e0c64d08
GH		 633 ret = false;
634 qemu_mutex_lock(&qxl->ssd.lock);
b1af98ba
GH		 635 update = QTAILQ_FIRST(&qxl->ssd.updates);
636 if (update != NULL) {
637 QTAILQ_REMOVE(&qxl->ssd.updates, update, next);
e0c64d08
GH		 638 *ext = update->ext;
639 ret = true;
a19cbfb3 640 }
e0c64d08 641 qemu_mutex_unlock(&qxl->ssd.lock);
212496c9 642 if (ret) {
c480bb7d 643 trace_qxl_ring_command_get(qxl->id, qxl_mode_to_string(qxl->mode));
212496c9
AL		 644 qxl_log_command(qxl, "vga", ext);
645 }
e0c64d08 646 return ret;
a19cbfb3
GH		 647 case QXL_MODE_COMPAT:
648 case QXL_MODE_NATIVE:
649 case QXL_MODE_UNDEFINED:
a19cbfb3 650 ring = &qxl->ram->cmd_ring;
087e6a42 651 if (qxl->guest_bug || SPICE_RING_IS_EMPTY(ring)) {
a19cbfb3
GH		 652 return false;
653 }
0b81c478
AL		 654 SPICE_RING_CONS_ITEM(qxl, ring, cmd);
655 if (!cmd) {
656 return false;
657 }
a19cbfb3
GH		 658 ext->cmd = *cmd;
659 ext->group_id = MEMSLOT_GROUP_GUEST;
660 ext->flags = qxl->cmdflags;
661 SPICE_RING_POP(ring, notify);
662 qxl_ring_set_dirty(qxl);
663 if (notify) {
664 qxl_send_events(qxl, QXL_INTERRUPT_DISPLAY);
665 }
666 qxl->guest_primary.commands++;
667 qxl_track_command(qxl, ext);
668 qxl_log_command(qxl, "cmd", ext);
86dbcdd9
GH		 669 {
670 /*
671 * Windows 8 drivers place qxl commands in the vram
672 * (instead of the ram) bar. We can't live migrate such a
673 * guest, so add a migration blocker in case we detect
674 * this, to avoid triggering the assert in pre_save().
675 *
676 * https://cgit.freedesktop.org/spice/win32/qxl-wddm-dod/commit/?id=f6e099db39e7d0787f294d5fd0dce328b5210faa
677 */
678 void *msg = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id);
679 if (msg != NULL && (
680 msg < (void *)qxl->vga.vram_ptr ||
681 msg > ((void *)qxl->vga.vram_ptr + qxl->vga.vram_size))) {
682 if (!qxl->migration_blocker) {
683 Error *local_err = NULL;
684 error_setg(&qxl->migration_blocker,
685 "qxl: guest bug: command not in ram bar");
686 migrate_add_blocker(qxl->migration_blocker, &local_err);
687 if (local_err) {
688 error_report_err(local_err);
689 }
690 }
691 }
692 }
0b81c478 693 trace_qxl_ring_command_get(qxl->id, qxl_mode_to_string(qxl->mode));
a19cbfb3
GH		 694 return true;
695 default:
696 return false;
697 }
698}
699
700/* called from spice server thread context only */
701static int interface_req_cmd_notification(QXLInstance *sin)
702{
703 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
704 int wait = 1;
705
c480bb7d 706 trace_qxl_ring_command_req_notification(qxl->id);
a19cbfb3
GH		 707 switch (qxl->mode) {
708 case QXL_MODE_COMPAT:
709 case QXL_MODE_NATIVE:
710 case QXL_MODE_UNDEFINED:
711 SPICE_RING_CONS_WAIT(&qxl->ram->cmd_ring, wait);
712 qxl_ring_set_dirty(qxl);
713 break;
714 default:
715 /* nothing */
716 break;
717 }
718 return wait;
719}
720
721/* called from spice server thread context only */
722static inline void qxl_push_free_res(PCIQXLDevice *d, int flush)
723{
724 QXLReleaseRing *ring = &d->ram->release_ring;
94932c95 725 uint32_t prod;
a19cbfb3
GH		 726 int notify;
727
728#define QXL_FREE_BUNCH_SIZE 32
729
730 if (ring->prod - ring->cons + 1 == ring->num_items) {
731 /* ring full -- can't push */
732 return;
733 }
734 if (!flush && d->oom_running) {
735 /* collect everything from oom handler before pushing */
736 return;
737 }
738 if (!flush && d->num_free_res < QXL_FREE_BUNCH_SIZE) {
739 /* collect a bit more before pushing */
740 return;
741 }
742
743 SPICE_RING_PUSH(ring, notify);
c480bb7d
AL		 744 trace_qxl_ring_res_push(d->id, qxl_mode_to_string(d->mode),
745 d->guest_surfaces.count, d->num_free_res,
746 d->last_release, notify ? "yes" : "no");
747 trace_qxl_ring_res_push_rest(d->id, ring->prod - ring->cons,
748 ring->num_items, ring->prod, ring->cons);
a19cbfb3
GH		 749 if (notify) {
750 qxl_send_events(d, QXL_INTERRUPT_DISPLAY);
751 }
94932c95
DB		 752
753 ring = &d->ram->release_ring;
754 prod = ring->prod & SPICE_RING_INDEX_MASK(ring);
755 if (prod >= ARRAY_SIZE(ring->items)) {
756 qxl_set_guest_bug(d, "SPICE_RING_PROD_ITEM indices mismatch "
757 "%u >= %zu", prod, ARRAY_SIZE(ring->items));
0b81c478
AL		 758 return;
759 }
94932c95 760 ring->items[prod].el = 0;
a19cbfb3
GH		 761 d->num_free_res = 0;
762 d->last_release = NULL;
763 qxl_ring_set_dirty(d);
764}
765
766/* called from spice server thread context only */
767static void interface_release_resource(QXLInstance *sin,
c9f88ce3 768 QXLReleaseInfoExt ext)
a19cbfb3
GH		 769{
770 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
771 QXLReleaseRing *ring;
94932c95
DB		 772 uint32_t prod;
773 uint64_t id;
a19cbfb3 774
d52680fc
PP		 775 if (!ext.info) {
776 return;
777 }
a19cbfb3
GH		 778 if (ext.group_id == MEMSLOT_GROUP_HOST) {
779 /* host group -> vga mode update request */
e8e23b7d 780 QXLCommandExt *cmdext = (void *)(intptr_t)(ext.info->id);
5643fc01
GH		 781 SimpleSpiceUpdate *update;
782 g_assert(cmdext->cmd.type == QXL_CMD_DRAW);
783 update = container_of(cmdext, SimpleSpiceUpdate, ext);
784 qemu_spice_destroy_update(&qxl->ssd, update);
a19cbfb3
GH		 785 return;
786 }
787
788 /*
789 * ext->info points into guest-visible memory
790 * pci bar 0, $command.release_info
791 */
792 ring = &qxl->ram->release_ring;
94932c95
DB		 793 prod = ring->prod & SPICE_RING_INDEX_MASK(ring);
794 if (prod >= ARRAY_SIZE(ring->items)) {
795 qxl_set_guest_bug(qxl, "SPICE_RING_PROD_ITEM indices mismatch "
796 "%u >= %zu", prod, ARRAY_SIZE(ring->items));
0b81c478
AL		 797 return;
798 }
94932c95 799 if (ring->items[prod].el == 0) {
a19cbfb3
GH		 800 /* stick head into the ring */
801 id = ext.info->id;
802 ext.info->next = 0;
803 qxl_ram_set_dirty(qxl, &ext.info->next);
94932c95 804 ring->items[prod].el = id;
a19cbfb3
GH		 805 qxl_ring_set_dirty(qxl);
806 } else {
807 /* append item to the list */
808 qxl->last_release->next = ext.info->id;
809 qxl_ram_set_dirty(qxl, &qxl->last_release->next);
810 ext.info->next = 0;
811 qxl_ram_set_dirty(qxl, &ext.info->next);
812 }
813 qxl->last_release = ext.info;
814 qxl->num_free_res++;
c480bb7d 815 trace_qxl_ring_res_put(qxl->id, qxl->num_free_res);
a19cbfb3
GH		 816 qxl_push_free_res(qxl, 0);
817}
818
819/* called from spice server thread context only */
820static int interface_get_cursor_command(QXLInstance *sin, struct QXLCommandExt *ext)
821{
822 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
823 QXLCursorRing *ring;
824 QXLCommand *cmd;
825 int notify;
826
c480bb7d
AL		 827 trace_qxl_ring_cursor_check(qxl->id, qxl_mode_to_string(qxl->mode));
828
a19cbfb3
GH		 829 switch (qxl->mode) {
830 case QXL_MODE_COMPAT:
831 case QXL_MODE_NATIVE:
832 case QXL_MODE_UNDEFINED:
833 ring = &qxl->ram->cursor_ring;
834 if (SPICE_RING_IS_EMPTY(ring)) {
835 return false;
836 }
0b81c478
AL		 837 SPICE_RING_CONS_ITEM(qxl, ring, cmd);
838 if (!cmd) {
839 return false;
840 }
a19cbfb3
GH		 841 ext->cmd = *cmd;
842 ext->group_id = MEMSLOT_GROUP_GUEST;
843 ext->flags = qxl->cmdflags;
844 SPICE_RING_POP(ring, notify);
845 qxl_ring_set_dirty(qxl);
846 if (notify) {
847 qxl_send_events(qxl, QXL_INTERRUPT_CURSOR);
848 }
849 qxl->guest_primary.commands++;
850 qxl_track_command(qxl, ext);
851 qxl_log_command(qxl, "csr", ext);
60e94e43 852 if (qxl->have_vga) {
a19cbfb3
GH		 853 qxl_render_cursor(qxl, ext);
854 }
c480bb7d 855 trace_qxl_ring_cursor_get(qxl->id, qxl_mode_to_string(qxl->mode));
a19cbfb3
GH		 856 return true;
857 default:
858 return false;
859 }
860}
861
862/* called from spice server thread context only */
863static int interface_req_cursor_notification(QXLInstance *sin)
864{
865 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
866 int wait = 1;
867
c480bb7d 868 trace_qxl_ring_cursor_req_notification(qxl->id);
a19cbfb3
GH		 869 switch (qxl->mode) {
870 case QXL_MODE_COMPAT:
871 case QXL_MODE_NATIVE:
872 case QXL_MODE_UNDEFINED:
873 SPICE_RING_CONS_WAIT(&qxl->ram->cursor_ring, wait);
874 qxl_ring_set_dirty(qxl);
875 break;
876 default:
877 /* nothing */
878 break;
879 }
880 return wait;
881}
882
883/* called from spice server thread context */
884static void interface_notify_update(QXLInstance *sin, uint32_t update_id)
885{
baeae407
AL		 886 /*
887 * Called by spice-server as a result of a QXL_CMD_UPDATE which is not in
888 * use by xf86-video-qxl and is defined out in the qxl windows driver.
889 * Probably was at some earlier version that is prior to git start (2009),
890 * and is still guest trigerrable.
891 */
892 fprintf(stderr, "%s: deprecated\n", __func__);
a19cbfb3
GH		 893}
894
895/* called from spice server thread context only */
896static int interface_flush_resources(QXLInstance *sin)
897{
898 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
899 int ret;
900
a19cbfb3
GH		 901 ret = qxl->num_free_res;
902 if (ret) {
903 qxl_push_free_res(qxl, 1);
904 }
905 return ret;
906}
907
5ff4e36c
AL		 908static void qxl_create_guest_primary_complete(PCIQXLDevice *d);
909
5ff4e36c 910/* called from spice server thread context only */
2e1a98c9 911static void interface_async_complete_io(PCIQXLDevice *qxl, QXLCookie *cookie)
5ff4e36c 912{
5ff4e36c
AL		 913 uint32_t current_async;
914
915 qemu_mutex_lock(&qxl->async_lock);
916 current_async = qxl->current_async;
917 qxl->current_async = QXL_UNDEFINED_IO;
918 qemu_mutex_unlock(&qxl->async_lock);
919
c480bb7d 920 trace_qxl_interface_async_complete_io(qxl->id, current_async, cookie);
2e1a98c9
AL		 921 if (!cookie) {
922 fprintf(stderr, "qxl: %s: error, cookie is NULL\n", __func__);
923 return;
924 }
925 if (cookie && current_async != cookie->io) {
926 fprintf(stderr,
2fce7edf
AL		 927 "qxl: %s: error: current_async = %d != %"
928 PRId64 " = cookie->io\n", __func__, current_async, cookie->io);
2e1a98c9 929 }
5ff4e36c 930 switch (current_async) {
81fb6f15
AL		 931 case QXL_IO_MEMSLOT_ADD_ASYNC:
932 case QXL_IO_DESTROY_PRIMARY_ASYNC:
933 case QXL_IO_UPDATE_AREA_ASYNC:
934 case QXL_IO_FLUSH_SURFACES_ASYNC:
020af1c4 935 case QXL_IO_MONITORS_CONFIG_ASYNC:
81fb6f15 936 break;
5ff4e36c
AL		 937 case QXL_IO_CREATE_PRIMARY_ASYNC:
938 qxl_create_guest_primary_complete(qxl);
939 break;
940 case QXL_IO_DESTROY_ALL_SURFACES_ASYNC:
941 qxl_spice_destroy_surfaces_complete(qxl);
942 break;
943 case QXL_IO_DESTROY_SURFACE_ASYNC:
2e1a98c9 944 qxl_spice_destroy_surface_wait_complete(qxl, cookie->u.surface_id);
5ff4e36c 945 break;
81fb6f15
AL		 946 default:
947 fprintf(stderr, "qxl: %s: unexpected current_async %d\n", __func__,
948 current_async);
5ff4e36c
AL		 949 }
950 qxl_send_events(qxl, QXL_INTERRUPT_IO_CMD);
951}
952
81fb6f15
AL		 953/* called from spice server thread context only */
954static void interface_update_area_complete(QXLInstance *sin,
955 uint32_t surface_id,
956 QXLRect *dirty, uint32_t num_updated_rects)
957{
958 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
959 int i;
960 int qxl_i;
961
6e8a355d 962 QEMU_LOCK_GUARD(&qxl->ssd.lock);
2f5ae772
GH		 963 if (surface_id != 0 || !num_updated_rects ||
964 !qxl->render_update_cookie_num) {
81fb6f15
AL		 965 return;
966 }
c480bb7d
AL		 967 trace_qxl_interface_update_area_complete(qxl->id, surface_id, dirty->left,
968 dirty->right, dirty->top, dirty->bottom);
969 trace_qxl_interface_update_area_complete_rest(qxl->id, num_updated_rects);
81fb6f15
AL		 970 if (qxl->num_dirty_rects + num_updated_rects > QXL_NUM_DIRTY_RECTS) {
971 /*
972 * overflow - treat this as a full update. Not expected to be common.
973 */
c480bb7d
AL		 974 trace_qxl_interface_update_area_complete_overflow(qxl->id,
975 QXL_NUM_DIRTY_RECTS);
81fb6f15
AL		 976 qxl->guest_primary.resized = 1;
977 }
978 if (qxl->guest_primary.resized) {
979 /*
980 * Don't bother copying or scheduling the bh since we will flip
981 * the whole area anyway on completion of the update_area async call
982 */
81fb6f15
AL		 983 return;
984 }
985 qxl_i = qxl->num_dirty_rects;
986 for (i = 0; i < num_updated_rects; i++) {
987 qxl->dirty[qxl_i++] = dirty[i];
988 }
989 qxl->num_dirty_rects += num_updated_rects;
c480bb7d
AL		 990 trace_qxl_interface_update_area_complete_schedule_bh(qxl->id,
991 qxl->num_dirty_rects);
81fb6f15 992 qemu_bh_schedule(qxl->update_area_bh);
81fb6f15
AL		 993}
994
2e1a98c9
AL		 995/* called from spice server thread context only */
996static void interface_async_complete(QXLInstance *sin, uint64_t cookie_token)
997{
998 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
5dba0d45 999 QXLCookie *cookie = (QXLCookie *)(uintptr_t)cookie_token;
2e1a98c9
AL		 1000
1001 switch (cookie->type) {
1002 case QXL_COOKIE_TYPE_IO:
1003 interface_async_complete_io(qxl, cookie);
81fb6f15
AL		 1004 g_free(cookie);
1005 break;
1006 case QXL_COOKIE_TYPE_RENDER_UPDATE_AREA:
1007 qxl_render_update_area_done(qxl, cookie);
2e1a98c9 1008 break;
020af1c4
AL		 1009 case QXL_COOKIE_TYPE_POST_LOAD_MONITORS_CONFIG:
1010 break;
2e1a98c9
AL		 1011 default:
1012 fprintf(stderr, "qxl: %s: unexpected cookie type %d\n",
1013 __func__, cookie->type);
81fb6f15 1014 g_free(cookie);
2e1a98c9 1015 }
2e1a98c9
AL		 1016}
1017
c10018d6
SSP		 1018/* called from spice server thread context only */
1019static void interface_set_client_capabilities(QXLInstance *sin,
1020 uint8_t client_present,
1021 uint8_t caps[58])
1022{
1023 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
1024
e0ac6097
AL		 1025 if (qxl->revision < 4) {
1026 trace_qxl_set_client_capabilities_unsupported_by_revision(qxl->id,
1027 qxl->revision);
1028 return;
1029 }
1030
ab902981
HG		 1031 if (runstate_check(RUN_STATE_INMIGRATE) ||
1032 runstate_check(RUN_STATE_POSTMIGRATE)) {
1033 return;
1034 }
1035
c10018d6 1036 qxl->shadow_rom.client_present = client_present;
08688af0
MA		 1037 memcpy(qxl->shadow_rom.client_capabilities, caps,
1038 sizeof(qxl->shadow_rom.client_capabilities));
c10018d6 1039 qxl->rom->client_present = client_present;
08688af0
MA		 1040 memcpy(qxl->rom->client_capabilities, caps,
1041 sizeof(qxl->rom->client_capabilities));
c10018d6
SSP		 1042 qxl_rom_set_dirty(qxl);
1043
1044 qxl_send_events(qxl, QXL_INTERRUPT_CLIENT);
1045}
1046
6c756502
CF		 1047static bool qxl_rom_monitors_config_changed(QXLRom *rom,
1048 VDAgentMonitorsConfig *monitors_config,
1049 unsigned int max_outputs)
1050{
1051 int i;
1052 unsigned int monitors_count;
1053
1054 monitors_count = MIN(monitors_config->num_of_monitors, max_outputs);
1055
1056 if (rom->client_monitors_config.count != monitors_count) {
1057 return true;
1058 }
1059
1060 for (i = 0 ; i < rom->client_monitors_config.count ; ++i) {
1061 VDAgentMonConfig *monitor = &monitors_config->monitors[i];
1062 QXLURect *rect = &rom->client_monitors_config.heads[i];
1063 /* monitor->depth ignored */
1064 if ((rect->left != monitor->x) ||
1065 (rect->top != monitor->y) ||
1066 (rect->right != monitor->x + monitor->width) ||
1067 (rect->bottom != monitor->y + monitor->height)) {
1068 return true;
1069 }
1070 }
1071
1072 return false;
1073}
1074
a639ab04
AL		 1075/* called from main context only */
1076static int interface_client_monitors_config(QXLInstance *sin,
1077 VDAgentMonitorsConfig *monitors_config)
1078{
1079 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
1080 QXLRom *rom = memory_region_get_ram_ptr(&qxl->rom_bar);
1081 int i;
567161fd 1082 unsigned max_outputs = ARRAY_SIZE(rom->client_monitors_config.heads);
6c756502 1083 bool config_changed = false;
a639ab04 1084
e0ac6097
AL		 1085 if (qxl->revision < 4) {
1086 trace_qxl_client_monitors_config_unsupported_by_device(qxl->id,
1087 qxl->revision);
1088 return 0;
1089 }
a639ab04
AL		 1090 /*
1091 * Older windows drivers set int_mask to 0 when their ISR is called,
1092 * then later set it to ~0. So it doesn't relate to the actual interrupts
1093 * handled. However, they are old, so clearly they don't support this
1094 * interrupt
1095 */
1096 if (qxl->ram->int_mask == 0 || qxl->ram->int_mask == ~0 ||
1097 !(qxl->ram->int_mask & QXL_INTERRUPT_CLIENT_MONITORS_CONFIG)) {
1098 trace_qxl_client_monitors_config_unsupported_by_guest(qxl->id,
1099 qxl->ram->int_mask,
1100 monitors_config);
1101 return 0;
1102 }
1103 if (!monitors_config) {
1104 return 1;
1105 }
567161fd
FZ		 1106
1107#if SPICE_SERVER_VERSION >= 0x000c06 /* release 0.12.6 */
1108 /* limit number of outputs based on setting limit */
1109 if (qxl->max_outputs && qxl->max_outputs <= max_outputs) {
1110 max_outputs = qxl->max_outputs;
1111 }
1112#endif
1113
6c756502
CF		 1114 config_changed = qxl_rom_monitors_config_changed(rom,
1115 monitors_config,
1116 max_outputs);
1117
a639ab04
AL		 1118 memset(&rom->client_monitors_config, 0,
1119 sizeof(rom->client_monitors_config));
1120 rom->client_monitors_config.count = monitors_config->num_of_monitors;
1121 /* monitors_config->flags ignored */
567161fd 1122 if (rom->client_monitors_config.count >= max_outputs) {
a639ab04
AL		 1123 trace_qxl_client_monitors_config_capped(qxl->id,
1124 monitors_config->num_of_monitors,
567161fd
FZ		 1125 max_outputs);
1126 rom->client_monitors_config.count = max_outputs;
a639ab04
AL		 1127 }
1128 for (i = 0 ; i < rom->client_monitors_config.count ; ++i) {
1129 VDAgentMonConfig *monitor = &monitors_config->monitors[i];
1130 QXLURect *rect = &rom->client_monitors_config.heads[i];
1131 /* monitor->depth ignored */
1132 rect->left = monitor->x;
1133 rect->top = monitor->y;
1134 rect->right = monitor->x + monitor->width;
1135 rect->bottom = monitor->y + monitor->height;
1136 }
1137 rom->client_monitors_config_crc = qxl_crc32(
1138 (const uint8_t *)&rom->client_monitors_config,
1139 sizeof(rom->client_monitors_config));
1140 trace_qxl_client_monitors_config_crc(qxl->id,
1141 sizeof(rom->client_monitors_config),
1142 rom->client_monitors_config_crc);
1143
1144 trace_qxl_interrupt_client_monitors_config(qxl->id,
1145 rom->client_monitors_config.count,
1146 rom->client_monitors_config.heads);
6c756502
CF		 1147 if (config_changed) {
1148 qxl_send_events(qxl, QXL_INTERRUPT_CLIENT_MONITORS_CONFIG);
1149 }
a639ab04
AL		 1150 return 1;
1151}
a639ab04 1152
a19cbfb3
GH		 1153static const QXLInterface qxl_interface = {
1154 .base.type = SPICE_INTERFACE_QXL,
1155 .base.description = "qxl gpu",
1156 .base.major_version = SPICE_INTERFACE_QXL_MAJOR,
1157 .base.minor_version = SPICE_INTERFACE_QXL_MINOR,
1158
1159 .attache_worker = interface_attach_worker,
1160 .set_compression_level = interface_set_compression_level,
015e02f8 1161#if SPICE_NEEDS_SET_MM_TIME
a19cbfb3 1162 .set_mm_time = interface_set_mm_time,
015e02f8 1163#endif
a19cbfb3
GH		 1164 .get_init_info = interface_get_init_info,
1165
1166 /* the callbacks below are called from spice server thread context */
1167 .get_command = interface_get_command,
1168 .req_cmd_notification = interface_req_cmd_notification,
1169 .release_resource = interface_release_resource,
1170 .get_cursor_command = interface_get_cursor_command,
1171 .req_cursor_notification = interface_req_cursor_notification,
1172 .notify_update = interface_notify_update,
1173 .flush_resources = interface_flush_resources,
5ff4e36c 1174 .async_complete = interface_async_complete,
81fb6f15 1175 .update_area_complete = interface_update_area_complete,
c10018d6 1176 .set_client_capabilities = interface_set_client_capabilities,
a639ab04 1177 .client_monitors_config = interface_client_monitors_config,
a19cbfb3
GH		 1178};
1179
15162335
GH		 1180static const GraphicHwOps qxl_ops = {
1181 .gfx_update = qxl_hw_update,
4d631621 1182 .gfx_update_async = true,
15162335
GH		 1183};
1184
a19cbfb3
GH		 1185static void qxl_enter_vga_mode(PCIQXLDevice *d)
1186{
1187 if (d->mode == QXL_MODE_VGA) {
1188 return;
1189 }
c480bb7d 1190 trace_qxl_enter_vga_mode(d->id);
0a2b5e3a 1191 spice_qxl_driver_unload(&d->ssd.qxl);
15162335 1192 graphic_console_set_hwops(d->ssd.dcl.con, d->vga.hw_ops, &d->vga);
3dcadce5 1193 update_displaychangelistener(&d->ssd.dcl, GUI_REFRESH_INTERVAL_DEFAULT);
a19cbfb3
GH		 1194 qemu_spice_create_host_primary(&d->ssd);
1195 d->mode = QXL_MODE_VGA;
a703d3ae 1196 qemu_spice_display_switch(&d->ssd, d->ssd.ds);
0f7bfd81 1197 vga_dirty_log_start(&d->vga);
1dbfa005 1198 graphic_hw_update(d->vga.con);
a19cbfb3
GH		 1199}
1200
1201static void qxl_exit_vga_mode(PCIQXLDevice *d)
1202{
1203 if (d->mode != QXL_MODE_VGA) {
1204 return;
1205 }
c480bb7d 1206 trace_qxl_exit_vga_mode(d->id);
15162335 1207 graphic_console_set_hwops(d->ssd.dcl.con, &qxl_ops, d);
3dcadce5 1208 update_displaychangelistener(&d->ssd.dcl, GUI_REFRESH_INTERVAL_IDLE);
0f7bfd81 1209 vga_dirty_log_stop(&d->vga);
5ff4e36c 1210 qxl_destroy_primary(d, QXL_SYNC);
a19cbfb3
GH		 1211}
1212
40010aea 1213static void qxl_update_irq(PCIQXLDevice *d)
a19cbfb3
GH		 1214{
1215 uint32_t pending = le32_to_cpu(d->ram->int_pending);
1216 uint32_t mask = le32_to_cpu(d->ram->int_mask);
1217 int level = !!(pending & mask);
9e64f8a3 1218 pci_set_irq(&d->pci, level);
a19cbfb3
GH		 1219 qxl_ring_set_dirty(d);
1220}
1221
a19cbfb3
GH		 1222static void qxl_check_state(PCIQXLDevice *d)
1223{
1224 QXLRam *ram = d->ram;
71d388d4 1225 int spice_display_running = qemu_spice_display_is_running(&d->ssd);
a19cbfb3 1226
71d388d4
YH		 1227 assert(!spice_display_running || SPICE_RING_IS_EMPTY(&ram->cmd_ring));
1228 assert(!spice_display_running || SPICE_RING_IS_EMPTY(&ram->cursor_ring));
a19cbfb3
GH		 1229}
1230
1231static void qxl_reset_state(PCIQXLDevice *d)
1232{
a19cbfb3
GH		 1233 QXLRom *rom = d->rom;
1234
be48e995 1235 qxl_check_state(d);
a19cbfb3
GH		 1236 d->shadow_rom.update_id = cpu_to_le32(0);
1237 *rom = d->shadow_rom;
1238 qxl_rom_set_dirty(d);
1239 init_qxl_ram(d);
1240 d->num_free_res = 0;
1241 d->last_release = NULL;
1242 memset(&d->ssd.dirty, 0, sizeof(d->ssd.dirty));
f06b8521 1243 qxl_update_irq(d);
a19cbfb3
GH		 1244}
1245
1246static void qxl_soft_reset(PCIQXLDevice *d)
1247{
c480bb7d 1248 trace_qxl_soft_reset(d->id);
a19cbfb3 1249 qxl_check_state(d);
087e6a42 1250 qxl_clear_guest_bug(d);
05fa1c74 1251 qemu_mutex_lock(&d->async_lock);
a5f68c22 1252 d->current_async = QXL_UNDEFINED_IO;
05fa1c74 1253 qemu_mutex_unlock(&d->async_lock);
a19cbfb3 1254
60e94e43 1255 if (d->have_vga) {
a19cbfb3
GH		 1256 qxl_enter_vga_mode(d);
1257 } else {
1258 d->mode = QXL_MODE_UNDEFINED;
1259 }
1260}
1261
1262static void qxl_hard_reset(PCIQXLDevice *d, int loadvm)
1263{
75c70e37
GH		 1264 bool startstop = qemu_spice_display_is_running(&d->ssd);
1265
c480bb7d 1266 trace_qxl_hard_reset(d->id, loadvm);
a19cbfb3 1267
75c70e37
GH		 1268 if (startstop) {
1269 qemu_spice_display_stop();
1270 }
1271
aee32bf3
GH		 1272 qxl_spice_reset_cursor(d);
1273 qxl_spice_reset_image_cache(d);
a19cbfb3
GH		 1274 qxl_reset_surfaces(d);
1275 qxl_reset_memslots(d);
1276
1277 /* pre loadvm reset must not touch QXLRam. This lives in
1278 * device memory, is migrated together with RAM and thus
1279 * already loaded at this point */
1280 if (!loadvm) {
1281 qxl_reset_state(d);
1282 }
1283 qemu_spice_create_host_memslot(&d->ssd);
1284 qxl_soft_reset(d);
75c70e37 1285
86dbcdd9
GH		 1286 if (d->migration_blocker) {
1287 migrate_del_blocker(d->migration_blocker);
1288 error_free(d->migration_blocker);
1289 d->migration_blocker = NULL;
1290 }
1291
75c70e37
GH		 1292 if (startstop) {
1293 qemu_spice_display_start();
1294 }
a19cbfb3
GH		 1295}
1296
1297static void qxl_reset_handler(DeviceState *dev)
1298{
c69f6c7d 1299 PCIQXLDevice *d = PCI_QXL(PCI_DEVICE(dev));
c480bb7d 1300
a19cbfb3
GH		 1301 qxl_hard_reset(d, 0);
1302}
1303
1304static void qxl_vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
1305{
1306 VGACommonState *vga = opaque;
1307 PCIQXLDevice *qxl = container_of(vga, PCIQXLDevice, vga);
1308
c480bb7d 1309 trace_qxl_io_write_vga(qxl->id, qxl_mode_to_string(qxl->mode), addr, val);
ed71c09f
GH		 1310 if (qxl->mode != QXL_MODE_VGA &&
1311 qxl->revision <= QXL_REVISION_STABLE_V12) {
5ff4e36c 1312 qxl_destroy_primary(qxl, QXL_SYNC);
a19cbfb3
GH		 1313 qxl_soft_reset(qxl);
1314 }
1315 vga_ioport_write(opaque, addr, val);
1316}
1317
f67ab77a
GH		 1318static const MemoryRegionPortio qxl_vga_portio_list[] = {
1319 { 0x04, 2, 1, .read = vga_ioport_read,
1320 .write = qxl_vga_ioport_write }, /* 3b4 */
1321 { 0x0a, 1, 1, .read = vga_ioport_read,
1322 .write = qxl_vga_ioport_write }, /* 3ba */
1323 { 0x10, 16, 1, .read = vga_ioport_read,
1324 .write = qxl_vga_ioport_write }, /* 3c0 */
1325 { 0x24, 2, 1, .read = vga_ioport_read,
1326 .write = qxl_vga_ioport_write }, /* 3d4 */
1327 { 0x2a, 1, 1, .read = vga_ioport_read,
1328 .write = qxl_vga_ioport_write }, /* 3da */
1329 PORTIO_END_OF_LIST(),
1330};
1331
e954ea28
AL		 1332static int qxl_add_memslot(PCIQXLDevice *d, uint32_t slot_id, uint64_t delta,
1333 qxl_async_io async)
a19cbfb3
GH		 1334{
1335 static const int regions[] = {
1336 QXL_RAM_RANGE_INDEX,
1337 QXL_VRAM_RANGE_INDEX,
6f2b175a 1338 QXL_VRAM64_RANGE_INDEX,
a19cbfb3
GH		 1339 };
1340 uint64_t guest_start;
1341 uint64_t guest_end;
1342 int pci_region;
1343 pcibus_t pci_start;
1344 pcibus_t pci_end;
3cb5158f 1345 MemoryRegion *mr;
a19cbfb3
GH		 1346 intptr_t virt_start;
1347 QXLDevMemSlot memslot;
1348 int i;
1349
1350 guest_start = le64_to_cpu(d->guest_slots[slot_id].slot.mem_start);
1351 guest_end = le64_to_cpu(d->guest_slots[slot_id].slot.mem_end);
1352
c480bb7d 1353 trace_qxl_memslot_add_guest(d->id, slot_id, guest_start, guest_end);
a19cbfb3 1354
e954ea28 1355 if (slot_id >= NUM_MEMSLOTS) {
0a530548 1356 qxl_set_guest_bug(d, "%s: slot_id >= NUM_MEMSLOTS %d >= %d", __func__,
e954ea28
AL		 1357 slot_id, NUM_MEMSLOTS);
1358 return 1;
1359 }
1360 if (guest_start > guest_end) {
0a530548 1361 qxl_set_guest_bug(d, "%s: guest_start > guest_end 0x%" PRIx64
e954ea28
AL		 1362 " > 0x%" PRIx64, __func__, guest_start, guest_end);
1363 return 1;
1364 }
a19cbfb3
GH		 1365
1366 for (i = 0; i < ARRAY_SIZE(regions); i++) {
1367 pci_region = regions[i];
1368 pci_start = d->pci.io_regions[pci_region].addr;
1369 pci_end = pci_start + d->pci.io_regions[pci_region].size;
1370 /* mapped? */
1371 if (pci_start == -1) {
1372 continue;
1373 }
1374 /* start address in range ? */
1375 if (guest_start < pci_start || guest_start > pci_end) {
1376 continue;
1377 }
1378 /* end address in range ? */
1379 if (guest_end > pci_end) {
1380 continue;
1381 }
1382 /* passed */
1383 break;
1384 }
e954ea28 1385 if (i == ARRAY_SIZE(regions)) {
0a530548 1386 qxl_set_guest_bug(d, "%s: finished loop without match", __func__);
e954ea28
AL		 1387 return 1;
1388 }
a19cbfb3
GH		 1389
1390 switch (pci_region) {
1391 case QXL_RAM_RANGE_INDEX:
3cb5158f 1392 mr = &d->vga.vram;
a19cbfb3
GH		 1393 break;
1394 case QXL_VRAM_RANGE_INDEX:
6f2b175a 1395 case 4 /* vram 64bit */:
3cb5158f 1396 mr = &d->vram_bar;
a19cbfb3
GH		 1397 break;
1398 default:
1399 /* should not happen */
0a530548 1400 qxl_set_guest_bug(d, "%s: pci_region = %d", __func__, pci_region);
e954ea28 1401 return 1;
a19cbfb3
GH		 1402 }
1403
3cb5158f 1404 virt_start = (intptr_t)memory_region_get_ram_ptr(mr);
a19cbfb3
GH		 1405 memslot.slot_id = slot_id;
1406 memslot.slot_group_id = MEMSLOT_GROUP_GUEST; /* guest group */
1407 memslot.virt_start = virt_start + (guest_start - pci_start);
1408 memslot.virt_end = virt_start + (guest_end - pci_start);
1409 memslot.addr_delta = memslot.virt_start - delta;
1410 memslot.generation = d->rom->slot_generation = 0;
1411 qxl_rom_set_dirty(d);
1412
5ff4e36c 1413 qemu_spice_add_memslot(&d->ssd, &memslot, async);
3cb5158f
GH		 1414 d->guest_slots[slot_id].mr = mr;
1415 d->guest_slots[slot_id].offset = memslot.virt_start - virt_start;
a19cbfb3
GH		 1416 d->guest_slots[slot_id].size = memslot.virt_end - memslot.virt_start;
1417 d->guest_slots[slot_id].delta = delta;
1418 d->guest_slots[slot_id].active = 1;
e954ea28 1419 return 0;
a19cbfb3
GH		 1420}
1421
1422static void qxl_del_memslot(PCIQXLDevice *d, uint32_t slot_id)
1423{
5c59d118 1424 qemu_spice_del_memslot(&d->ssd, MEMSLOT_GROUP_HOST, slot_id);
a19cbfb3
GH		 1425 d->guest_slots[slot_id].active = 0;
1426}
1427
1428static void qxl_reset_memslots(PCIQXLDevice *d)
1429{
aee32bf3 1430 qxl_spice_reset_memslots(d);
a19cbfb3
GH		 1431 memset(&d->guest_slots, 0, sizeof(d->guest_slots));
1432}
1433
1434static void qxl_reset_surfaces(PCIQXLDevice *d)
1435{
c480bb7d 1436 trace_qxl_reset_surfaces(d->id);
a19cbfb3 1437 d->mode = QXL_MODE_UNDEFINED;
5ff4e36c 1438 qxl_spice_destroy_surfaces(d, QXL_SYNC);
a19cbfb3
GH		 1439}
1440
e25139b3 1441/* can be also called from spice server thread context */
726bdf65
GH		 1442static bool qxl_get_check_slot_offset(PCIQXLDevice *qxl, QXLPHYSICAL pqxl,
1443 uint32_t *s, uint64_t *o)
a19cbfb3
GH		 1444{
1445 uint64_t phys = le64_to_cpu(pqxl);
1446 uint32_t slot = (phys >> (64 - 8)) & 0xff;
1447 uint64_t offset = phys & 0xffffffffffff;
1448
726bdf65
GH		 1449 if (slot >= NUM_MEMSLOTS) {
1450 qxl_set_guest_bug(qxl, "slot too large %d >= %d", slot,
1451 NUM_MEMSLOTS);
1452 return false;
1453 }
1454 if (!qxl->guest_slots[slot].active) {
1455 qxl_set_guest_bug(qxl, "inactive slot %d\n", slot);
1456 return false;
1457 }
1458 if (offset < qxl->guest_slots[slot].delta) {
1459 qxl_set_guest_bug(qxl,
0a530548 1460 "slot %d offset %"PRIu64" < delta %"PRIu64"\n",
4b635c59 1461 slot, offset, qxl->guest_slots[slot].delta);
726bdf65
GH		 1462 return false;
1463 }
1464 offset -= qxl->guest_slots[slot].delta;
1465 if (offset > qxl->guest_slots[slot].size) {
1466 qxl_set_guest_bug(qxl,
0a530548 1467 "slot %d offset %"PRIu64" > size %"PRIu64"\n",
4b635c59 1468 slot, offset, qxl->guest_slots[slot].size);
726bdf65
GH		 1469 return false;
1470 }
1471
1472 *s = slot;
1473 *o = offset;
1474 return true;
1475}
1476
1477/* can be also called from spice server thread context */
1478void *qxl_phys2virt(PCIQXLDevice *qxl, QXLPHYSICAL pqxl, int group_id)
1479{
1480 uint64_t offset;
1481 uint32_t slot;
3cb5158f 1482 void *ptr;
726bdf65
GH		 1483
1484 switch (group_id) {
1485 case MEMSLOT_GROUP_HOST:
1486 offset = le64_to_cpu(pqxl) & 0xffffffffffff;
1487 return (void *)(intptr_t)offset;
1488 case MEMSLOT_GROUP_GUEST:
1489 if (!qxl_get_check_slot_offset(qxl, pqxl, &slot, &offset)) {
4b635c59
AL		 1490 return NULL;
1491 }
3cb5158f
GH		 1492 ptr = memory_region_get_ram_ptr(qxl->guest_slots[slot].mr);
1493 ptr += qxl->guest_slots[slot].offset;
1494 ptr += offset;
1495 return ptr;
a19cbfb3 1496 }
4b635c59 1497 return NULL;
a19cbfb3
GH		 1498}
1499
5ff4e36c
AL		 1500static void qxl_create_guest_primary_complete(PCIQXLDevice *qxl)
1501{
1502 /* for local rendering */
1503 qxl_render_resize(qxl);
1504}
1505
1506static void qxl_create_guest_primary(PCIQXLDevice *qxl, int loadvm,
1507 qxl_async_io async)
a19cbfb3
GH		 1508{
1509 QXLDevSurfaceCreate surface;
1510 QXLSurfaceCreate *sc = &qxl->guest_primary.surface;
3761abb1 1511 uint32_t requested_height = le32_to_cpu(sc->height);
13d1fd44
AL		 1512 int requested_stride = le32_to_cpu(sc->stride);
1513
3761abb1
AL		 1514 if (requested_stride == INT32_MIN ||
1515 abs(requested_stride) * (uint64_t)requested_height
1516 > qxl->vgamem_size) {
1517 qxl_set_guest_bug(qxl, "%s: requested primary larger than framebuffer"
1518 " stride %d x height %" PRIu32 " > %" PRIu32,
1519 __func__, requested_stride, requested_height,
1520 qxl->vgamem_size);
13d1fd44
AL		 1521 return;
1522 }
a19cbfb3 1523
ddf9f4b7 1524 if (qxl->mode == QXL_MODE_NATIVE) {
0a530548 1525 qxl_set_guest_bug(qxl, "%s: nop since already in QXL_MODE_NATIVE",
ddf9f4b7
AL		 1526 __func__);
1527 }
a19cbfb3
GH		 1528 qxl_exit_vga_mode(qxl);
1529
a19cbfb3
GH		 1530 surface.format = le32_to_cpu(sc->format);
1531 surface.height = le32_to_cpu(sc->height);
1532 surface.mem = le64_to_cpu(sc->mem);
1533 surface.position = le32_to_cpu(sc->position);
1534 surface.stride = le32_to_cpu(sc->stride);
1535 surface.width = le32_to_cpu(sc->width);
1536 surface.type = le32_to_cpu(sc->type);
1537 surface.flags = le32_to_cpu(sc->flags);
c480bb7d
AL		 1538 trace_qxl_create_guest_primary(qxl->id, sc->width, sc->height, sc->mem,
1539 sc->format, sc->position);
1540 trace_qxl_create_guest_primary_rest(qxl->id, sc->stride, sc->type,
1541 sc->flags);
a19cbfb3 1542
48f4ba67
AL		 1543 if ((surface.stride & 0x3) != 0) {
1544 qxl_set_guest_bug(qxl, "primary surface stride = %d %% 4 != 0",
1545 surface.stride);
1546 return;
1547 }
1548
a19cbfb3
GH		 1549 surface.mouse_mode = true;
1550 surface.group_id = MEMSLOT_GROUP_GUEST;
1551 if (loadvm) {
1552 surface.flags |= QXL_SURF_FLAG_KEEP_DATA;
1553 }
1554
1555 qxl->mode = QXL_MODE_NATIVE;
1556 qxl->cmdflags = 0;
5ff4e36c 1557 qemu_spice_create_primary_surface(&qxl->ssd, 0, &surface, async);
a19cbfb3 1558
5ff4e36c
AL		 1559 if (async == QXL_SYNC) {
1560 qxl_create_guest_primary_complete(qxl);
1561 }
a19cbfb3
GH		 1562}
1563
5ff4e36c
AL		 1564/* return 1 if surface destoy was initiated (in QXL_ASYNC case) or
1565 * done (in QXL_SYNC case), 0 otherwise. */
1566static int qxl_destroy_primary(PCIQXLDevice *d, qxl_async_io async)
a19cbfb3
GH		 1567{
1568 if (d->mode == QXL_MODE_UNDEFINED) {
5ff4e36c 1569 return 0;
a19cbfb3 1570 }
c480bb7d 1571 trace_qxl_destroy_primary(d->id);
a19cbfb3 1572 d->mode = QXL_MODE_UNDEFINED;
5ff4e36c 1573 qemu_spice_destroy_primary_surface(&d->ssd, 0, async);
30f6da66 1574 qxl_spice_reset_cursor(d);
5ff4e36c 1575 return 1;
a19cbfb3
GH		 1576}
1577
9c70434f 1578static void qxl_set_mode(PCIQXLDevice *d, unsigned int modenr, int loadvm)
a19cbfb3
GH		 1579{
1580 pcibus_t start = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr;
1581 pcibus_t end = d->pci.io_regions[QXL_RAM_RANGE_INDEX].size + start;
1582 QXLMode *mode = d->modes->modes + modenr;
1583 uint64_t devmem = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr;
1584 QXLMemSlot slot = {
1585 .mem_start = start,
1586 .mem_end = end
1587 };
9c70434f
GH		 1588
1589 if (modenr >= d->modes->n_modes) {
1590 qxl_set_guest_bug(d, "mode number out of range");
1591 return;
1592 }
1593
a19cbfb3
GH		 1594 QXLSurfaceCreate surface = {
1595 .width = mode->x_res,
1596 .height = mode->y_res,
1597 .stride = -mode->x_res * 4,
1598 .format = SPICE_SURFACE_FMT_32_xRGB,
1599 .flags = loadvm ? QXL_SURF_FLAG_KEEP_DATA : 0,
1600 .mouse_mode = true,
1601 .mem = devmem + d->shadow_rom.draw_area_offset,
1602 };
1603
c480bb7d
AL		 1604 trace_qxl_set_mode(d->id, modenr, mode->x_res, mode->y_res, mode->bits,
1605 devmem);
a19cbfb3
GH		 1606 if (!loadvm) {
1607 qxl_hard_reset(d, 0);
1608 }
1609
1610 d->guest_slots[0].slot = slot;
e954ea28 1611 assert(qxl_add_memslot(d, 0, devmem, QXL_SYNC) == 0);
a19cbfb3
GH		 1612
1613 d->guest_primary.surface = surface;
5ff4e36c 1614 qxl_create_guest_primary(d, 0, QXL_SYNC);
a19cbfb3
GH		 1615
1616 d->mode = QXL_MODE_COMPAT;
1617 d->cmdflags = QXL_COMMAND_FLAG_COMPAT;
a19cbfb3
GH		 1618 if (mode->bits == 16) {
1619 d->cmdflags |= QXL_COMMAND_FLAG_COMPAT_16BPP;
1620 }
a19cbfb3
GH		 1621 d->shadow_rom.mode = cpu_to_le32(modenr);
1622 d->rom->mode = cpu_to_le32(modenr);
1623 qxl_rom_set_dirty(d);
1624}
1625
a8170e5e 1626static void ioport_write(void *opaque, hwaddr addr,
b1950430 1627 uint64_t val, unsigned size)
a19cbfb3
GH		 1628{
1629 PCIQXLDevice *d = opaque;
b1950430 1630 uint32_t io_port = addr;
5ff4e36c 1631 qxl_async_io async = QXL_SYNC;
380e6d81 1632 uint32_t orig_io_port;
a19cbfb3 1633
d96aafca 1634 if (d->guest_bug && io_port != QXL_IO_RESET) {
087e6a42
AL		 1635 return;
1636 }
1637
020af1c4 1638 if (d->revision <= QXL_REVISION_STABLE_V10 &&
ffe01e59 1639 io_port > QXL_IO_FLUSH_RELEASE) {
020af1c4
AL		 1640 qxl_set_guest_bug(d, "unsupported io %d for revision %d\n",
1641 io_port, d->revision);
1642 return;
1643 }
1644
a19cbfb3
GH		 1645 switch (io_port) {
1646 case QXL_IO_RESET:
1647 case QXL_IO_SET_MODE:
1648 case QXL_IO_MEMSLOT_ADD:
1649 case QXL_IO_MEMSLOT_DEL:
1650 case QXL_IO_CREATE_PRIMARY:
81144d1a 1651 case QXL_IO_UPDATE_IRQ:
a3d14054 1652 case QXL_IO_LOG:
5ff4e36c
AL		 1653 case QXL_IO_MEMSLOT_ADD_ASYNC:
1654 case QXL_IO_CREATE_PRIMARY_ASYNC:
a19cbfb3
GH		 1655 break;
1656 default:
e21a298a 1657 if (d->mode != QXL_MODE_VGA) {
a19cbfb3 1658 break;
e21a298a 1659 }
c480bb7d 1660 trace_qxl_io_unexpected_vga_mode(d->id,
917ae08c 1661 addr, val, io_port_to_string(io_port));
5ff4e36c
AL		 1662 /* be nice to buggy guest drivers */
1663 if (io_port >= QXL_IO_UPDATE_AREA_ASYNC &&
020af1c4 1664 io_port < QXL_IO_RANGE_SIZE) {
5ff4e36c
AL		 1665 qxl_send_events(d, QXL_INTERRUPT_IO_CMD);
1666 }
a19cbfb3
GH		 1667 return;
1668 }
1669
5ff4e36c
AL		 1670 /* we change the io_port to avoid ifdeffery in the main switch */
1671 orig_io_port = io_port;
1672 switch (io_port) {
1673 case QXL_IO_UPDATE_AREA_ASYNC:
1674 io_port = QXL_IO_UPDATE_AREA;
1675 goto async_common;
1676 case QXL_IO_MEMSLOT_ADD_ASYNC:
1677 io_port = QXL_IO_MEMSLOT_ADD;
1678 goto async_common;
1679 case QXL_IO_CREATE_PRIMARY_ASYNC:
1680 io_port = QXL_IO_CREATE_PRIMARY;
1681 goto async_common;
1682 case QXL_IO_DESTROY_PRIMARY_ASYNC:
1683 io_port = QXL_IO_DESTROY_PRIMARY;
1684 goto async_common;
1685 case QXL_IO_DESTROY_SURFACE_ASYNC:
1686 io_port = QXL_IO_DESTROY_SURFACE_WAIT;
1687 goto async_common;
1688 case QXL_IO_DESTROY_ALL_SURFACES_ASYNC:
1689 io_port = QXL_IO_DESTROY_ALL_SURFACES;
3e16b9c5
AL		 1690 goto async_common;
1691 case QXL_IO_FLUSH_SURFACES_ASYNC:
020af1c4 1692 case QXL_IO_MONITORS_CONFIG_ASYNC:
5ff4e36c
AL		 1693async_common:
1694 async = QXL_ASYNC;
6e8a355d
DB		 1695 WITH_QEMU_LOCK_GUARD(&d->async_lock) {
1696 if (d->current_async != QXL_UNDEFINED_IO) {
1697 qxl_set_guest_bug(d, "%d async started before last (%d) complete",
1698 io_port, d->current_async);
1699 return;
1700 }
1701 d->current_async = orig_io_port;
5ff4e36c 1702 }
5ff4e36c
AL		 1703 break;
1704 default:
1705 break;
1706 }
18b20385
GH		 1707 trace_qxl_io_write(d->id, qxl_mode_to_string(d->mode),
1708 addr, io_port_to_string(addr),
1709 val, size, async);
5ff4e36c 1710
a19cbfb3
GH		 1711 switch (io_port) {
1712 case QXL_IO_UPDATE_AREA:
1713 {
81fb6f15 1714 QXLCookie *cookie = NULL;
a19cbfb3 1715 QXLRect update = d->ram->update_area;
81fb6f15 1716
ddd8fdc7 1717 if (d->ram->update_surface > d->ssd.num_surfaces) {
511b13e2
AL		 1718 qxl_set_guest_bug(d, "QXL_IO_UPDATE_AREA: invalid surface id %d\n",
1719 d->ram->update_surface);
36a03e0b 1720 break;
511b13e2 1721 }
36a03e0b
MT		 1722 if (update.left >= update.right || update.top >= update.bottom ||
1723 update.left < 0 || update.top < 0) {
511b13e2
AL		 1724 qxl_set_guest_bug(d,
1725 "QXL_IO_UPDATE_AREA: invalid area (%ux%u)x(%ux%u)\n",
1726 update.left, update.top, update.right, update.bottom);
9e5a25f1
MAL		 1727 if (update.left == update.right || update.top == update.bottom) {
1728 /* old drivers may provide empty area, keep going */
1729 qxl_clear_guest_bug(d);
1730 goto cancel_async;
1731 }
ccc2960d
DH		 1732 break;
1733 }
81fb6f15
AL		 1734 if (async == QXL_ASYNC) {
1735 cookie = qxl_cookie_new(QXL_COOKIE_TYPE_IO,
1736 QXL_IO_UPDATE_AREA_ASYNC);
1737 cookie->u.area = update;
1738 }
aee32bf3 1739 qxl_spice_update_area(d, d->ram->update_surface,
81fb6f15
AL		 1740 cookie ? &cookie->u.area : &update,
1741 NULL, 0, 0, async, cookie);
a19cbfb3
GH		 1742 break;
1743 }
1744 case QXL_IO_NOTIFY_CMD:
5c59d118 1745 qemu_spice_wakeup(&d->ssd);
a19cbfb3
GH		 1746 break;
1747 case QXL_IO_NOTIFY_CURSOR:
5c59d118 1748 qemu_spice_wakeup(&d->ssd);
a19cbfb3
GH		 1749 break;
1750 case QXL_IO_UPDATE_IRQ:
40010aea 1751 qxl_update_irq(d);
a19cbfb3
GH		 1752 break;
1753 case QXL_IO_NOTIFY_OOM:
a19cbfb3
GH		 1754 if (!SPICE_RING_IS_EMPTY(&d->ram->release_ring)) {
1755 break;
1756 }
1757 d->oom_running = 1;
aee32bf3 1758 qxl_spice_oom(d);
a19cbfb3
GH		 1759 d->oom_running = 0;
1760 break;
1761 case QXL_IO_SET_MODE:
a19cbfb3
GH		 1762 qxl_set_mode(d, val, 0);
1763 break;
1764 case QXL_IO_LOG:
d97df4b8
GH		 1765#ifdef CONFIG_MODULES
1766 /*
1767 * FIXME
1768 * trace_event_get_state_backends() does not work for modules,
1769 * it leads to "undefined symbol: qemu_qxl_io_log_semaphore"
1770 */
1771 if (true) {
1772#else
d4aceb2e 1773 if (trace_event_get_state_backends(TRACE_QXL_IO_LOG) || d->guestdebug) {
d97df4b8 1774#endif
00f42697
DB		 1775 /* We cannot trust the guest to NUL terminate d->ram->log_buf */
1776 char *log_buf = g_strndup((const char *)d->ram->log_buf,
1777 sizeof(d->ram->log_buf));
1778 trace_qxl_io_log(d->id, log_buf);
1779 if (d->guestdebug) {
1780 fprintf(stderr, "qxl/guest-%d: %" PRId64 ": %s", d->id,
1781 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), log_buf);
1782 }
1783 g_free(log_buf);
a19cbfb3
GH		 1784 }
1785 break;
1786 case QXL_IO_RESET:
a19cbfb3
GH		 1787 qxl_hard_reset(d, 0);
1788 break;
1789 case QXL_IO_MEMSLOT_ADD:
2bce0400 1790 if (val >= NUM_MEMSLOTS) {
0a530548 1791 qxl_set_guest_bug(d, "QXL_IO_MEMSLOT_ADD: val out of range");
2bce0400
GH		 1792 break;
1793 }
1794 if (d->guest_slots[val].active) {
0a530548
AL		 1795 qxl_set_guest_bug(d,
1796 "QXL_IO_MEMSLOT_ADD: memory slot already active");
2bce0400
GH		 1797 break;
1798 }
a19cbfb3 1799 d->guest_slots[val].slot = d->ram->mem_slot;
5ff4e36c 1800 qxl_add_memslot(d, val, 0, async);
a19cbfb3
GH		 1801 break;
1802 case QXL_IO_MEMSLOT_DEL:
2bce0400 1803 if (val >= NUM_MEMSLOTS) {
0a530548 1804 qxl_set_guest_bug(d, "QXL_IO_MEMSLOT_DEL: val out of range");
2bce0400
GH		 1805 break;
1806 }
a19cbfb3
GH		 1807 qxl_del_memslot(d, val);
1808 break;
1809 case QXL_IO_CREATE_PRIMARY:
2bce0400 1810 if (val != 0) {
0a530548 1811 qxl_set_guest_bug(d, "QXL_IO_CREATE_PRIMARY (async=%d): val != 0",
5ff4e36c
AL		 1812 async);
1813 goto cancel_async;
2bce0400 1814 }
a19cbfb3 1815 d->guest_primary.surface = d->ram->create_surface;
5ff4e36c 1816 qxl_create_guest_primary(d, 0, async);
a19cbfb3
GH		 1817 break;
1818 case QXL_IO_DESTROY_PRIMARY:
2bce0400 1819 if (val != 0) {
0a530548 1820 qxl_set_guest_bug(d, "QXL_IO_DESTROY_PRIMARY (async=%d): val != 0",
5ff4e36c
AL		 1821 async);
1822 goto cancel_async;
1823 }
5ff4e36c 1824 if (!qxl_destroy_primary(d, async)) {
c480bb7d
AL		 1825 trace_qxl_io_destroy_primary_ignored(d->id,
1826 qxl_mode_to_string(d->mode));
5ff4e36c 1827 goto cancel_async;
2bce0400 1828 }
a19cbfb3
GH		 1829 break;
1830 case QXL_IO_DESTROY_SURFACE_WAIT:
ddd8fdc7 1831 if (val >= d->ssd.num_surfaces) {
0a530548 1832 qxl_set_guest_bug(d, "QXL_IO_DESTROY_SURFACE (async=%d):"
5f8daf2e 1833 "%" PRIu64 " >= NUM_SURFACES", async, val);
5ff4e36c
AL		 1834 goto cancel_async;
1835 }
1836 qxl_spice_destroy_surface_wait(d, val, async);
a19cbfb3 1837 break;
3e16b9c5
AL		 1838 case QXL_IO_FLUSH_RELEASE: {
1839 QXLReleaseRing *ring = &d->ram->release_ring;
1840 if (ring->prod - ring->cons + 1 == ring->num_items) {
1841 fprintf(stderr,
1842 "ERROR: no flush, full release ring [p%d,%dc]\n",
1843 ring->prod, ring->cons);
1844 }
1845 qxl_push_free_res(d, 1 /* flush */);
3e16b9c5
AL		 1846 break;
1847 }
1848 case QXL_IO_FLUSH_SURFACES_ASYNC:
3e16b9c5
AL		 1849 qxl_spice_flush_surfaces_async(d);
1850 break;
a19cbfb3 1851 case QXL_IO_DESTROY_ALL_SURFACES:
5ff4e36c
AL		 1852 d->mode = QXL_MODE_UNDEFINED;
1853 qxl_spice_destroy_surfaces(d, async);
a19cbfb3 1854 break;
020af1c4
AL		 1855 case QXL_IO_MONITORS_CONFIG_ASYNC:
1856 qxl_spice_monitors_config_async(d, 0);
1857 break;
a19cbfb3 1858 default:
0a530548 1859 qxl_set_guest_bug(d, "%s: unexpected ioport=0x%x\n", __func__, io_port);
a19cbfb3 1860 }
5ff4e36c
AL		 1861 return;
1862cancel_async:
5ff4e36c
AL		 1863 if (async) {
1864 qxl_send_events(d, QXL_INTERRUPT_IO_CMD);
1865 qemu_mutex_lock(&d->async_lock);
1866 d->current_async = QXL_UNDEFINED_IO;
1867 qemu_mutex_unlock(&d->async_lock);
1868 }
a19cbfb3
GH		 1869}
1870
a8170e5e 1871static uint64_t ioport_read(void *opaque, hwaddr addr,
b1950430 1872 unsigned size)
a19cbfb3 1873{
917ae08c 1874 PCIQXLDevice *qxl = opaque;
a19cbfb3 1875
917ae08c 1876 trace_qxl_io_read_unexpected(qxl->id);
a19cbfb3
GH		 1877 return 0xff;
1878}
1879
b1950430
AK		 1880static const MemoryRegionOps qxl_io_ops = {
1881 .read = ioport_read,
1882 .write = ioport_write,
1883 .valid = {
1884 .min_access_size = 1,
1885 .max_access_size = 1,
1886 },
1887};
a19cbfb3 1888
4a46c99c 1889static void qxl_update_irq_bh(void *opaque)
a19cbfb3
GH		 1890{
1891 PCIQXLDevice *d = opaque;
40010aea 1892 qxl_update_irq(d);
a19cbfb3
GH		 1893}
1894
a19cbfb3
GH		 1895static void qxl_send_events(PCIQXLDevice *d, uint32_t events)
1896{
1897 uint32_t old_pending;
1898 uint32_t le_events = cpu_to_le32(events);
1899
917ae08c 1900 trace_qxl_send_events(d->id, events);
511aefb0
AL		 1901 if (!qemu_spice_display_is_running(&d->ssd)) {
1902 /* spice-server tracks guest running state and should not do this */
1903 fprintf(stderr, "%s: spice-server bug: guest stopped, ignoring\n",
1904 __func__);
1905 trace_qxl_send_events_vm_stopped(d->id, events);
1906 return;
1907 }
5a358b39
PM		 1908 /*
1909 * Older versions of Spice forgot to define the QXLRam struct
1910 * with the '__aligned__(4)' attribute. clang 7 and newer will
1911 * thus warn that atomic_fetch_or(&d->ram->int_pending, ...)
1912 * might be a misaligned atomic access, and will generate an
1913 * out-of-line call for it, which results in a link error since
1914 * we don't currently link against libatomic.
1915 *
1916 * In fact we set up d->ram in init_qxl_ram() so it always starts
1917 * at a 4K boundary, so we know that &d->ram->int_pending is
1918 * naturally aligned for a uint32_t. Newer Spice versions
1919 * (with Spice commit beda5ec7a6848be20c0cac2a9a8ef2a41e8069c1)
1920 * will fix the bug directly. To deal with older versions,
1921 * we tell the compiler to assume the address really is aligned.
1922 * Any compiler which cares about the misalignment will have
1923 * __builtin_assume_aligned.
1924 */
1925#ifdef HAS_ASSUME_ALIGNED
1926#define ALIGNED_UINT32_PTR(P) ((uint32_t *)__builtin_assume_aligned(P, 4))
1927#else
1928#define ALIGNED_UINT32_PTR(P) ((uint32_t *)P)
1929#endif
1930
1931 old_pending = atomic_fetch_or(ALIGNED_UINT32_PTR(&d->ram->int_pending),
1932 le_events);
a19cbfb3
GH		 1933 if ((old_pending & le_events) == le_events) {
1934 return;
1935 }
4a46c99c 1936 qemu_bh_schedule(d->update_irq);
a19cbfb3
GH		 1937}
1938
1939/* graphics console */
1940
1941static void qxl_hw_update(void *opaque)
1942{
1943 PCIQXLDevice *qxl = opaque;
a19cbfb3 1944
15162335 1945 qxl_render_update(qxl);
a19cbfb3
GH		 1946}
1947
1331eab2
GH		 1948static void qxl_dirty_one_surface(PCIQXLDevice *qxl, QXLPHYSICAL pqxl,
1949 uint32_t height, int32_t stride)
1950{
e0127d2e
GH		 1951 uint64_t offset, size;
1952 uint32_t slot;
1331eab2
GH		 1953 bool rc;
1954
1955 rc = qxl_get_check_slot_offset(qxl, pqxl, &slot, &offset);
1956 assert(rc == true);
e0127d2e
GH		 1957 size = (uint64_t)height * abs(stride);
1958 trace_qxl_surfaces_dirty(qxl->id, offset, size);
1331eab2 1959 qxl_set_dirty(qxl->guest_slots[slot].mr,
e0127d2e
GH		 1960 qxl->guest_slots[slot].offset + offset,
1961 qxl->guest_slots[slot].offset + offset + size);
1331eab2
GH		 1962}
1963
e25139b3
YH		 1964static void qxl_dirty_surfaces(PCIQXLDevice *qxl)
1965{
e25139b3
YH		 1966 int i;
1967
2aa9e85c 1968 if (qxl->mode != QXL_MODE_NATIVE && qxl->mode != QXL_MODE_COMPAT) {
e25139b3
YH		 1969 return;
1970 }
1971
1972 /* dirty the primary surface */
1331eab2
GH		 1973 qxl_dirty_one_surface(qxl, qxl->guest_primary.surface.mem,
1974 qxl->guest_primary.surface.height,
1975 qxl->guest_primary.surface.stride);
e25139b3
YH		 1976
1977 /* dirty the off-screen surfaces */
ddd8fdc7 1978 for (i = 0; i < qxl->ssd.num_surfaces; i++) {
e25139b3 1979 QXLSurfaceCmd *cmd;
e25139b3
YH		 1980
1981 if (qxl->guest_surfaces.cmds[i] == 0) {
1982 continue;
1983 }
1984
1985 cmd = qxl_phys2virt(qxl, qxl->guest_surfaces.cmds[i],
1986 MEMSLOT_GROUP_GUEST);
fae2afb1 1987 assert(cmd);
e25139b3 1988 assert(cmd->type == QXL_SURFACE_CMD_CREATE);
1331eab2
GH		 1989 qxl_dirty_one_surface(qxl, cmd->u.surface_create.data,
1990 cmd->u.surface_create.height,
1991 cmd->u.surface_create.stride);
e25139b3
YH		 1992 }
1993}
1994
1dfb4dd9
LC		 1995static void qxl_vm_change_state_handler(void *opaque, int running,
1996 RunState state)
a19cbfb3
GH		 1997{
1998 PCIQXLDevice *qxl = opaque;
a19cbfb3 1999
efbf2950
YH		 2000 if (running) {
2001 /*
2002 * if qxl_send_events was called from spice server context before
40010aea 2003 * migration ended, qxl_update_irq for these events might not have been
efbf2950
YH		 2004 * called
2005 */
40010aea 2006 qxl_update_irq(qxl);
e25139b3
YH		 2007 } else {
2008 /* make sure surfaces are saved before migration */
2009 qxl_dirty_surfaces(qxl);
a19cbfb3
GH		 2010 }
2011}
2012
2013/* display change listener */
2014
7c20b4a3 2015static void display_update(DisplayChangeListener *dcl,
7c20b4a3 2016 int x, int y, int w, int h)
a19cbfb3 2017{
c6c06853
GH		 2018 PCIQXLDevice *qxl = container_of(dcl, PCIQXLDevice, ssd.dcl);
2019
2020 if (qxl->mode == QXL_MODE_VGA) {
2021 qemu_spice_display_update(&qxl->ssd, x, y, w, h);
a19cbfb3
GH		 2022 }
2023}
2024
c12aeb86 2025static void display_switch(DisplayChangeListener *dcl,
c12aeb86 2026 struct DisplaySurface *surface)
a19cbfb3 2027{
c6c06853
GH		 2028 PCIQXLDevice *qxl = container_of(dcl, PCIQXLDevice, ssd.dcl);
2029
71874c17 2030 qxl->ssd.ds = surface;
c6c06853 2031 if (qxl->mode == QXL_MODE_VGA) {
c12aeb86 2032 qemu_spice_display_switch(&qxl->ssd, surface);
a19cbfb3
GH		 2033 }
2034}
2035
bc2ed970 2036static void display_refresh(DisplayChangeListener *dcl)
a19cbfb3 2037{
c6c06853
GH		 2038 PCIQXLDevice *qxl = container_of(dcl, PCIQXLDevice, ssd.dcl);
2039
2040 if (qxl->mode == QXL_MODE_VGA) {
2041 qemu_spice_display_refresh(&qxl->ssd);
a19cbfb3
GH		 2042 }
2043}
2044
7c20b4a3
GH		 2045static DisplayChangeListenerOps display_listener_ops = {
2046 .dpy_name = "spice/qxl",
a93a4a22 2047 .dpy_gfx_update = display_update,
c12aeb86 2048 .dpy_gfx_switch = display_switch,
7c20b4a3 2049 .dpy_refresh = display_refresh,
a19cbfb3
GH		 2050};
2051
13d1fd44 2052static void qxl_init_ramsize(PCIQXLDevice *qxl)
a974192c 2053{
13d1fd44
AL		 2054 /* vga mode framebuffer / primary surface (bar 0, first part) */
2055 if (qxl->vgamem_size_mb < 8) {
2056 qxl->vgamem_size_mb = 8;
2057 }
876d5163
RK		 2058 /* XXX: we round vgamem_size_mb up to a nearest power of two and it must be
2059 * less than vga_common_init()'s maximum on qxl->vga.vram_size (512 now).
2060 */
2061 if (qxl->vgamem_size_mb > 256) {
2062 qxl->vgamem_size_mb = 256;
2063 }
f0353b0d 2064 qxl->vgamem_size = qxl->vgamem_size_mb * MiB;
13d1fd44
AL		 2065
2066 /* vga ram (bar 0, total) */
017438ee 2067 if (qxl->ram_size_mb != -1) {
f0353b0d 2068 qxl->vga.vram_size = qxl->ram_size_mb * MiB;
017438ee 2069 }
13d1fd44
AL		 2070 if (qxl->vga.vram_size < qxl->vgamem_size * 2) {
2071 qxl->vga.vram_size = qxl->vgamem_size * 2;
a974192c
GH		 2072 }
2073
6f2b175a
GH		 2074 /* vram32 (surfaces, 32bit, bar 1) */
2075 if (qxl->vram32_size_mb != -1) {
f0353b0d 2076 qxl->vram32_size = qxl->vram32_size_mb * MiB;
6f2b175a
GH		 2077 }
2078 if (qxl->vram32_size < 4096) {
2079 qxl->vram32_size = 4096;
2080 }
2081
2082 /* vram (surfaces, 64bit, bar 4+5) */
017438ee 2083 if (qxl->vram_size_mb != -1) {
f0353b0d 2084 qxl->vram_size = (uint64_t)qxl->vram_size_mb * MiB;
017438ee 2085 }
6f2b175a
GH		 2086 if (qxl->vram_size < qxl->vram32_size) {
2087 qxl->vram_size = qxl->vram32_size;
a974192c 2088 }
6f2b175a 2089
a974192c 2090 if (qxl->revision == 1) {
6f2b175a 2091 qxl->vram32_size = 4096;
a974192c
GH		 2092 qxl->vram_size = 4096;
2093 }
bb7443f6
RK		 2094 qxl->vgamem_size = pow2ceil(qxl->vgamem_size);
2095 qxl->vga.vram_size = pow2ceil(qxl->vga.vram_size);
2096 qxl->vram32_size = pow2ceil(qxl->vram32_size);
2097 qxl->vram_size = pow2ceil(qxl->vram_size);
a974192c
GH		 2098}
2099
042a24db 2100static void qxl_realize_common(PCIQXLDevice *qxl, Error **errp)
a19cbfb3
GH		 2101{
2102 uint8_t* config = qxl->pci.config;
a19cbfb3
GH		 2103 uint32_t pci_device_rev;
2104 uint32_t io_size;
2105
47025a01 2106 qemu_spice_display_init_common(&qxl->ssd);
a19cbfb3 2107 qxl->mode = QXL_MODE_UNDEFINED;
a19cbfb3 2108 qxl->num_memslots = NUM_MEMSLOTS;
14898cf6 2109 qemu_mutex_init(&qxl->track_lock);
5ff4e36c
AL		 2110 qemu_mutex_init(&qxl->async_lock);
2111 qxl->current_async = QXL_UNDEFINED_IO;
087e6a42 2112 qxl->guest_bug = 0;
a19cbfb3
GH		 2113
2114 switch (qxl->revision) {
2115 case 1: /* spice 0.4 -- qxl-1 */
a19cbfb3 2116 pci_device_rev = QXL_REVISION_STABLE_V04;
3f6297b9 2117 io_size = 8;
a19cbfb3
GH		 2118 break;
2119 case 2: /* spice 0.6 -- qxl-2 */
a19cbfb3 2120 pci_device_rev = QXL_REVISION_STABLE_V06;
3f6297b9 2121 io_size = 16;
a19cbfb3 2122 break;
9197a7c8 2123 case 3: /* qxl-3 */
020af1c4
AL		 2124 pci_device_rev = QXL_REVISION_STABLE_V10;
2125 io_size = 32; /* PCI region size must be pow2 */
2126 break;
020af1c4
AL		 2127 case 4: /* qxl-4 */
2128 pci_device_rev = QXL_REVISION_STABLE_V12;
bb7443f6 2129 io_size = pow2ceil(QXL_IO_RANGE_SIZE);
ed71c09f
GH		 2130 break;
2131 case 5: /* qxl-5 */
2132 pci_device_rev = QXL_REVISION_STABLE_V12 + 1;
2133 io_size = pow2ceil(QXL_IO_RANGE_SIZE);
9197a7c8 2134 break;
36839d35 2135 default:
042a24db
MA		 2136 error_setg(errp, "Invalid revision %d for qxl device (max %d)",
2137 qxl->revision, QXL_DEFAULT_REVISION);
2138 return;
a19cbfb3
GH		 2139 }
2140
a19cbfb3
GH		 2141 pci_set_byte(&config[PCI_REVISION_ID], pci_device_rev);
2142 pci_set_byte(&config[PCI_INTERRUPT_PIN], 1);
2143
2144 qxl->rom_size = qxl_rom_size();
44b5c1eb 2145 memory_region_init_rom(&qxl->rom_bar, OBJECT(qxl), "qxl.vrom",
f8ed85ac 2146 qxl->rom_size, &error_fatal);
a19cbfb3
GH		 2147 init_qxl_rom(qxl);
2148 init_qxl_ram(qxl);
2149
ddd8fdc7 2150 qxl->guest_surfaces.cmds = g_new0(QXLPHYSICAL, qxl->ssd.num_surfaces);
ce66d778 2151 memory_region_init_ram(&qxl->vram_bar, OBJECT(qxl), "qxl.vram",
f8ed85ac 2152 qxl->vram_size, &error_fatal);
3eadad55
PB		 2153 memory_region_init_alias(&qxl->vram32_bar, OBJECT(qxl), "qxl.vram32",
2154 &qxl->vram_bar, 0, qxl->vram32_size);
a19cbfb3 2155
3eadad55 2156 memory_region_init_io(&qxl->io_bar, OBJECT(qxl), &qxl_io_ops, qxl,
b1950430 2157 "qxl-ioports", io_size);
60e94e43 2158 if (qxl->have_vga) {
b1950430
AK		 2159 vga_dirty_log_start(&qxl->vga);
2160 }
bd8f2f5d 2161 memory_region_set_flush_coalesced(&qxl->io_bar);
b1950430
AK		 2162
2163
e824b2cc
AK		 2164 pci_register_bar(&qxl->pci, QXL_IO_RANGE_INDEX,
2165 PCI_BASE_ADDRESS_SPACE_IO, &qxl->io_bar);
a19cbfb3 2166
e824b2cc
AK		 2167 pci_register_bar(&qxl->pci, QXL_ROM_RANGE_INDEX,
2168 PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->rom_bar);
a19cbfb3 2169
e824b2cc
AK		 2170 pci_register_bar(&qxl->pci, QXL_RAM_RANGE_INDEX,
2171 PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->vga.vram);
a19cbfb3 2172
e824b2cc 2173 pci_register_bar(&qxl->pci, QXL_VRAM_RANGE_INDEX,
6f2b175a
GH		 2174 PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->vram32_bar);
2175
2176 if (qxl->vram32_size < qxl->vram_size) {
2177 /*
2178 * Make the 64bit vram bar show up only in case it is
2179 * configured to be larger than the 32bit vram bar.
2180 */
2181 pci_register_bar(&qxl->pci, QXL_VRAM64_RANGE_INDEX,
2182 PCI_BASE_ADDRESS_SPACE_MEMORY |
2183 PCI_BASE_ADDRESS_MEM_TYPE_64 |
2184 PCI_BASE_ADDRESS_MEM_PREFETCH,
2185 &qxl->vram_bar);
2186 }
2187
2188 /* print pci bar details */
f0353b0d 2189 dprint(qxl, 1, "ram/%s: %" PRId64 " MB [region 0]\n",
60e94e43 2190 qxl->have_vga ? "pri" : "sec", qxl->vga.vram_size / MiB);
f0353b0d
PMD		 2191 dprint(qxl, 1, "vram/32: %" PRIx64 " MB [region 1]\n",
2192 qxl->vram32_size / MiB);
2193 dprint(qxl, 1, "vram/64: %" PRIx64 " MB %s\n",
2194 qxl->vram_size / MiB,
6f2b175a 2195 qxl->vram32_size < qxl->vram_size ? "[region 4]" : "[unmapped]");
a19cbfb3
GH		 2196
2197 qxl->ssd.qxl.base.sif = &qxl_interface.base;
9fa03286 2198 if (qemu_spice_add_display_interface(&qxl->ssd.qxl, qxl->vga.con) != 0) {
042a24db
MA		 2199 error_setg(errp, "qxl interface %d.%d not supported by spice-server",
2200 SPICE_INTERFACE_QXL_MAJOR, SPICE_INTERFACE_QXL_MINOR);
2201 return;
e25a0651 2202 }
be812c0a
LH		 2203
2204#if SPICE_SERVER_VERSION >= 0x000e02 /* release 0.14.2 */
2205 char device_address[256] = "";
2206 if (qemu_spice_fill_device_address(qxl->vga.con, device_address, 256)) {
2207 spice_qxl_set_device_info(&qxl->ssd.qxl,
2208 device_address,
2209 0,
2210 qxl->max_outputs);
2211 }
2212#endif
2213
a19cbfb3
GH		 2214 qemu_add_vm_change_state_handler(qxl_vm_change_state_handler, qxl);
2215
4a46c99c 2216 qxl->update_irq = qemu_bh_new(qxl_update_irq_bh, qxl);
a19cbfb3
GH		 2217 qxl_reset_state(qxl);
2218
81fb6f15 2219 qxl->update_area_bh = qemu_bh_new(qxl_render_update_area_bh, qxl);
0b2824e5 2220 qxl->ssd.cursor_bh = qemu_bh_new(qemu_spice_cursor_refresh_bh, &qxl->ssd);
a19cbfb3
GH		 2221}
2222
042a24db 2223static void qxl_realize_primary(PCIDevice *dev, Error **errp)
a19cbfb3 2224{
c69f6c7d 2225 PCIQXLDevice *qxl = PCI_QXL(dev);
a19cbfb3 2226 VGACommonState *vga = &qxl->vga;
042a24db 2227 Error *local_err = NULL;
a19cbfb3 2228
13d1fd44 2229 qxl_init_ramsize(qxl);
54a85d46 2230 vga->vbe_size = qxl->vgamem_size;
f0353b0d 2231 vga->vram_size_mb = qxl->vga.vram_size / MiB;
1fcfdc43 2232 vga_common_init(vga, OBJECT(dev));
712f0cc7
PB		 2233 vga_init(vga, OBJECT(dev),
2234 pci_address_space(dev), pci_address_space_io(dev), false);
848696bf 2235 portio_list_init(&qxl->vga_port_list, OBJECT(dev), qxl_vga_portio_list,
db10ca90 2236 vga, "vga");
848696bf
KB		 2237 portio_list_set_flush_coalesced(&qxl->vga_port_list);
2238 portio_list_add(&qxl->vga_port_list, pci_address_space_io(dev), 0x3b0);
60e94e43 2239 qxl->have_vga = true;
a19cbfb3 2240
5643706a 2241 vga->con = graphic_console_init(DEVICE(dev), 0, &qxl_ops, qxl);
60e94e43
GH		 2242 qxl->id = qemu_console_get_index(vga->con); /* == channel_id */
2243 if (qxl->id != 0) {
2244 error_setg(errp, "primary qxl-vga device must be console 0 "
2245 "(first display device on the command line)");
2246 return;
2247 }
a19cbfb3 2248
042a24db
MA		 2249 qxl_realize_common(qxl, &local_err);
2250 if (local_err) {
2251 error_propagate(errp, local_err);
2252 return;
bdd4df33
GH		 2253 }
2254
7c20b4a3 2255 qxl->ssd.dcl.ops = &display_listener_ops;
284d1c6b 2256 qxl->ssd.dcl.con = vga->con;
5209089f 2257 register_displaychangelistener(&qxl->ssd.dcl);
a19cbfb3
GH		 2258}
2259
042a24db 2260static void qxl_realize_secondary(PCIDevice *dev, Error **errp)
a19cbfb3 2261{
c69f6c7d 2262 PCIQXLDevice *qxl = PCI_QXL(dev);
a19cbfb3 2263
13d1fd44 2264 qxl_init_ramsize(qxl);
ce66d778 2265 memory_region_init_ram(&qxl->vga.vram, OBJECT(dev), "qxl.vgavram",
f8ed85ac 2266 qxl->vga.vram_size, &error_fatal);
b1950430 2267 qxl->vga.vram_ptr = memory_region_get_ram_ptr(&qxl->vga.vram);
5643706a 2268 qxl->vga.con = graphic_console_init(DEVICE(dev), 0, &qxl_ops, qxl);
60e94e43 2269 qxl->id = qemu_console_get_index(qxl->vga.con); /* == channel_id */
a19cbfb3 2270
042a24db 2271 qxl_realize_common(qxl, errp);
a19cbfb3
GH		 2272}
2273
44b1ff31 2274static int qxl_pre_save(void *opaque)
a19cbfb3
GH		 2275{
2276 PCIQXLDevice* d = opaque;
2277 uint8_t *ram_start = d->vga.vram_ptr;
2278
c480bb7d 2279 trace_qxl_pre_save(d->id);
a19cbfb3
GH		 2280 if (d->last_release == NULL) {
2281 d->last_release_offset = 0;
2282 } else {
2283 d->last_release_offset = (uint8_t *)d->last_release - ram_start;
2284 }
2285 assert(d->last_release_offset < d->vga.vram_size);
44b1ff31
DDAG		 2286
2287 return 0;
a19cbfb3
GH		 2288}
2289
2290static int qxl_pre_load(void *opaque)
2291{
2292 PCIQXLDevice* d = opaque;
2293
c480bb7d 2294 trace_qxl_pre_load(d->id);
a19cbfb3
GH		 2295 qxl_hard_reset(d, 1);
2296 qxl_exit_vga_mode(d);
a19cbfb3
GH		 2297 return 0;
2298}
2299
54825d2e
AL		 2300static void qxl_create_memslots(PCIQXLDevice *d)
2301{
2302 int i;
2303
2304 for (i = 0; i < NUM_MEMSLOTS; i++) {
2305 if (!d->guest_slots[i].active) {
2306 continue;
2307 }
54825d2e
AL		 2308 qxl_add_memslot(d, i, 0, QXL_SYNC);
2309 }
2310}
2311
a19cbfb3
GH		 2312static int qxl_post_load(void *opaque, int version)
2313{
2314 PCIQXLDevice* d = opaque;
2315 uint8_t *ram_start = d->vga.vram_ptr;
2316 QXLCommandExt *cmds;
54825d2e 2317 int in, out, newmode;
a19cbfb3 2318
a19cbfb3
GH		 2319 assert(d->last_release_offset < d->vga.vram_size);
2320 if (d->last_release_offset == 0) {
2321 d->last_release = NULL;
2322 } else {
2323 d->last_release = (QXLReleaseInfo *)(ram_start + d->last_release_offset);
2324 }
2325
2326 d->modes = (QXLModes*)((uint8_t*)d->rom + d->rom->modes_offset);
2327
c480bb7d 2328 trace_qxl_post_load(d->id, qxl_mode_to_string(d->mode));
a19cbfb3
GH		 2329 newmode = d->mode;
2330 d->mode = QXL_MODE_UNDEFINED;
54825d2e 2331
a19cbfb3
GH		 2332 switch (newmode) {
2333 case QXL_MODE_UNDEFINED:
fa98efe9 2334 qxl_create_memslots(d);
a19cbfb3
GH		 2335 break;
2336 case QXL_MODE_VGA:
54825d2e 2337 qxl_create_memslots(d);
a19cbfb3
GH		 2338 qxl_enter_vga_mode(d);
2339 break;
2340 case QXL_MODE_NATIVE:
54825d2e 2341 qxl_create_memslots(d);
5ff4e36c 2342 qxl_create_guest_primary(d, 1, QXL_SYNC);
a19cbfb3
GH		 2343
2344 /* replay surface-create and cursor-set commands */
9de68637 2345 cmds = g_new0(QXLCommandExt, d->ssd.num_surfaces + 1);
ddd8fdc7 2346 for (in = 0, out = 0; in < d->ssd.num_surfaces; in++) {
a19cbfb3
GH		 2347 if (d->guest_surfaces.cmds[in] == 0) {
2348 continue;
2349 }
2350 cmds[out].cmd.data = d->guest_surfaces.cmds[in];
2351 cmds[out].cmd.type = QXL_CMD_SURFACE;
2352 cmds[out].group_id = MEMSLOT_GROUP_GUEST;
2353 out++;
2354 }
30f6da66
YH		 2355 if (d->guest_cursor) {
2356 cmds[out].cmd.data = d->guest_cursor;
2357 cmds[out].cmd.type = QXL_CMD_CURSOR;
2358 cmds[out].group_id = MEMSLOT_GROUP_GUEST;
2359 out++;
2360 }
aee32bf3 2361 qxl_spice_loadvm_commands(d, cmds, out);
7267c094 2362 g_free(cmds);
020af1c4
AL		 2363 if (d->guest_monitors_config) {
2364 qxl_spice_monitors_config_async(d, 1);
2365 }
a19cbfb3
GH		 2366 break;
2367 case QXL_MODE_COMPAT:
54825d2e
AL		 2368 /* note: no need to call qxl_create_memslots, qxl_set_mode
2369 * creates the mem slot. */
a19cbfb3
GH		 2370 qxl_set_mode(d, d->shadow_rom.mode, 1);
2371 break;
2372 }
a19cbfb3
GH		 2373 return 0;
2374}
2375
b67737a6 2376#define QXL_SAVE_VERSION 21
a19cbfb3 2377
020af1c4
AL		 2378static bool qxl_monitors_config_needed(void *opaque)
2379{
2380 PCIQXLDevice *qxl = opaque;
2381
2382 return qxl->guest_monitors_config != 0;
2383}
2384
2385
a19cbfb3
GH		 2386static VMStateDescription qxl_memslot = {
2387 .name = "qxl-memslot",
2388 .version_id = QXL_SAVE_VERSION,
2389 .minimum_version_id = QXL_SAVE_VERSION,
2390 .fields = (VMStateField[]) {
2391 VMSTATE_UINT64(slot.mem_start, struct guest_slots),
2392 VMSTATE_UINT64(slot.mem_end, struct guest_slots),
2393 VMSTATE_UINT32(active, struct guest_slots),
2394 VMSTATE_END_OF_LIST()
2395 }
2396};
2397
2398static VMStateDescription qxl_surface = {
2399 .name = "qxl-surface",
2400 .version_id = QXL_SAVE_VERSION,
2401 .minimum_version_id = QXL_SAVE_VERSION,
2402 .fields = (VMStateField[]) {
2403 VMSTATE_UINT32(width, QXLSurfaceCreate),
2404 VMSTATE_UINT32(height, QXLSurfaceCreate),
2405 VMSTATE_INT32(stride, QXLSurfaceCreate),
2406 VMSTATE_UINT32(format, QXLSurfaceCreate),
2407 VMSTATE_UINT32(position, QXLSurfaceCreate),
2408 VMSTATE_UINT32(mouse_mode, QXLSurfaceCreate),
2409 VMSTATE_UINT32(flags, QXLSurfaceCreate),
2410 VMSTATE_UINT32(type, QXLSurfaceCreate),
2411 VMSTATE_UINT64(mem, QXLSurfaceCreate),
2412 VMSTATE_END_OF_LIST()
2413 }
2414};
2415
020af1c4
AL		 2416static VMStateDescription qxl_vmstate_monitors_config = {
2417 .name = "qxl/monitors-config",
2418 .version_id = 1,
2419 .minimum_version_id = 1,
5cd8cada 2420 .needed = qxl_monitors_config_needed,
020af1c4
AL		 2421 .fields = (VMStateField[]) {
2422 VMSTATE_UINT64(guest_monitors_config, PCIQXLDevice),
2423 VMSTATE_END_OF_LIST()
2424 },
2425};
2426
a19cbfb3
GH		 2427static VMStateDescription qxl_vmstate = {
2428 .name = "qxl",
2429 .version_id = QXL_SAVE_VERSION,
2430 .minimum_version_id = QXL_SAVE_VERSION,
2431 .pre_save = qxl_pre_save,
2432 .pre_load = qxl_pre_load,
2433 .post_load = qxl_post_load,
020af1c4 2434 .fields = (VMStateField[]) {
a19cbfb3
GH		 2435 VMSTATE_PCI_DEVICE(pci, PCIQXLDevice),
2436 VMSTATE_STRUCT(vga, PCIQXLDevice, 0, vmstate_vga_common, VGACommonState),
2437 VMSTATE_UINT32(shadow_rom.mode, PCIQXLDevice),
2438 VMSTATE_UINT32(num_free_res, PCIQXLDevice),
2439 VMSTATE_UINT32(last_release_offset, PCIQXLDevice),
2440 VMSTATE_UINT32(mode, PCIQXLDevice),
2441 VMSTATE_UINT32(ssd.unique, PCIQXLDevice),
d2164ad3 2442 VMSTATE_INT32_EQUAL(num_memslots, PCIQXLDevice, NULL),
b67737a6
GH		 2443 VMSTATE_STRUCT_ARRAY(guest_slots, PCIQXLDevice, NUM_MEMSLOTS, 0,
2444 qxl_memslot, struct guest_slots),
2445 VMSTATE_STRUCT(guest_primary.surface, PCIQXLDevice, 0,
2446 qxl_surface, QXLSurfaceCreate),
d2164ad3 2447 VMSTATE_INT32_EQUAL(ssd.num_surfaces, PCIQXLDevice, NULL),
ddd8fdc7
GH		 2448 VMSTATE_VARRAY_INT32(guest_surfaces.cmds, PCIQXLDevice,
2449 ssd.num_surfaces, 0,
2450 vmstate_info_uint64, uint64_t),
b67737a6 2451 VMSTATE_UINT64(guest_cursor, PCIQXLDevice),
a19cbfb3
GH		 2452 VMSTATE_END_OF_LIST()
2453 },
5cd8cada
JQ		 2454 .subsections = (const VMStateDescription*[]) {
2455 &qxl_vmstate_monitors_config,
2456 NULL
020af1c4 2457 }
a19cbfb3
GH		 2458};
2459
78e60ba5 2460static Property qxl_properties[] = {
f0353b0d
PMD		 2461 DEFINE_PROP_UINT32("ram_size", PCIQXLDevice, vga.vram_size, 64 * MiB),
2462 DEFINE_PROP_UINT64("vram_size", PCIQXLDevice, vram32_size, 64 * MiB),
78e60ba5
GH		 2463 DEFINE_PROP_UINT32("revision", PCIQXLDevice, revision,
2464 QXL_DEFAULT_REVISION),
2465 DEFINE_PROP_UINT32("debug", PCIQXLDevice, debug, 0),
2466 DEFINE_PROP_UINT32("guestdebug", PCIQXLDevice, guestdebug, 0),
2467 DEFINE_PROP_UINT32("cmdlog", PCIQXLDevice, cmdlog, 0),
017438ee 2468 DEFINE_PROP_UINT32("ram_size_mb", PCIQXLDevice, ram_size_mb, -1),
79ce3567
AL		 2469 DEFINE_PROP_UINT32("vram_size_mb", PCIQXLDevice, vram32_size_mb, -1),
2470 DEFINE_PROP_UINT32("vram64_size_mb", PCIQXLDevice, vram_size_mb, -1),
9e56edcf 2471 DEFINE_PROP_UINT32("vgamem_mb", PCIQXLDevice, vgamem_size_mb, 16),
ddd8fdc7 2472 DEFINE_PROP_INT32("surfaces", PCIQXLDevice, ssd.num_surfaces, 1024),
567161fd
FZ		 2473#if SPICE_SERVER_VERSION >= 0x000c06 /* release 0.12.6 */
2474 DEFINE_PROP_UINT16("max_outputs", PCIQXLDevice, max_outputs, 0),
2475#endif
6f663d7b
GH		 2476 DEFINE_PROP_UINT32("xres", PCIQXLDevice, xres, 0),
2477 DEFINE_PROP_UINT32("yres", PCIQXLDevice, yres, 0),
1fcfdc43 2478 DEFINE_PROP_BOOL("global-vmstate", PCIQXLDevice, vga.global_vmstate, false),
78e60ba5
GH		 2479 DEFINE_PROP_END_OF_LIST(),
2480};
2481
c69f6c7d 2482static void qxl_pci_class_init(ObjectClass *klass, void *data)
40021f08 2483{
39bffca2 2484 DeviceClass *dc = DEVICE_CLASS(klass);
40021f08
AL		 2485 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
2486
40021f08
AL		 2487 k->vendor_id = REDHAT_PCI_VENDOR_ID;
2488 k->device_id = QXL_DEVICE_ID_STABLE;
125ee0ed 2489 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
39bffca2
AL		 2490 dc->reset = qxl_reset_handler;
2491 dc->vmsd = &qxl_vmstate;
4f67d30b 2492 device_class_set_props(dc, qxl_properties);
c69f6c7d
GA		 2493}
2494
2495static const TypeInfo qxl_pci_type_info = {
2496 .name = TYPE_PCI_QXL,
2497 .parent = TYPE_PCI_DEVICE,
2498 .instance_size = sizeof(PCIQXLDevice),
2499 .abstract = true,
2500 .class_init = qxl_pci_class_init,
fd3b02c8
EH		 2501 .interfaces = (InterfaceInfo[]) {
2502 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
2503 { },
2504 },
c69f6c7d
GA		 2505};
2506
2507static void qxl_primary_class_init(ObjectClass *klass, void *data)
2508{
2509 DeviceClass *dc = DEVICE_CLASS(klass);
2510 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
2511
2512 k->realize = qxl_realize_primary;
2513 k->romfile = "vgabios-qxl.bin";
2514 k->class_id = PCI_CLASS_DISPLAY_VGA;
2515 dc->desc = "Spice QXL GPU (primary, vga compatible)";
2897ae02 2516 dc->hotpluggable = false;
40021f08
AL		 2517}
2518
8c43a6f0 2519static const TypeInfo qxl_primary_info = {
39bffca2 2520 .name = "qxl-vga",
c69f6c7d 2521 .parent = TYPE_PCI_QXL,
39bffca2 2522 .class_init = qxl_primary_class_init,
a19cbfb3
GH		 2523};
2524
40021f08
AL		 2525static void qxl_secondary_class_init(ObjectClass *klass, void *data)
2526{
39bffca2 2527 DeviceClass *dc = DEVICE_CLASS(klass);
40021f08
AL		 2528 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
2529
042a24db 2530 k->realize = qxl_realize_secondary;
40021f08 2531 k->class_id = PCI_CLASS_DISPLAY_OTHER;
39bffca2 2532 dc->desc = "Spice QXL GPU (secondary)";
40021f08
AL		 2533}
2534
8c43a6f0 2535static const TypeInfo qxl_secondary_info = {
39bffca2 2536 .name = "qxl",
c69f6c7d 2537 .parent = TYPE_PCI_QXL,
39bffca2 2538 .class_init = qxl_secondary_class_init,
a19cbfb3
GH		 2539};
2540
83f7d43a 2541static void qxl_register_types(void)
a19cbfb3 2542{
c69f6c7d 2543 type_register_static(&qxl_pci_type_info);
39bffca2
AL		 2544 type_register_static(&qxl_primary_info);
2545 type_register_static(&qxl_secondary_info);
a19cbfb3
GH		 2546}
2547
83f7d43a 2548type_init(qxl_register_types)
Empty description
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