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i386: make hyperv_expand_features() return bool
[qemu.git] / target / i386 / cpu.c
CommitLineData
c6dc6f63 1/*
79f1a68a 2 * i386 CPUID, CPU class, definitions, models
c6dc6f63
AP		 3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
d9ff33ad 9 * version 2.1 of the License, or (at your option) any later version.
c6dc6f63
AP		 10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
e688df6b 19
1ef26b1f 20#include "qemu/osdep.h"
6a4e0614 21#include "qemu/units.h"
f348b6d1 22#include "qemu/cutils.h"
0442428a 23#include "qemu/qemu-print.h"
c6dc6f63 24#include "cpu.h"
ed69e831 25#include "tcg/helper-tcg.h"
71e8a915 26#include "sysemu/reset.h"
d6dcc558 27#include "sysemu/hvf.h"
a9dc68d9 28#include "kvm/kvm_i386.h"
6cb8f2a6 29#include "sev_i386.h"
8ac25c84 30#include "qapi/qapi-visit-machine.h"
7b1b5d19 31#include "qapi/qmp/qerror.h"
7f7b4e7a 32#include "qapi/qapi-commands-machine-target.h"
1814eab6 33#include "standard-headers/asm-x86/kvm_para.h"
53a89e26 34#include "hw/qdev-properties.h"
5232d00a 35#include "hw/i386/topology.h"
bdeec802 36#ifndef CONFIG_USER_ONLY
2001d0cd 37#include "exec/address-spaces.h"
0e11fc69 38#include "hw/boards.h"
bdeec802
IM		 39#endif
40
b666d2a4 41#include "disas/capstone.h"
79f1a68a 42#include "cpu-internal.h"
b666d2a4 43
7e3482f8
EH		 44/* Helpers for building CPUID[2] descriptors: */
45
46struct CPUID2CacheDescriptorInfo {
47 enum CacheType type;
48 int level;
49 int size;
50 int line_size;
51 int associativity;
52};
5e891bf8 53
7e3482f8
EH		 54/*
55 * Known CPUID 2 cache descriptors.
56 * From Intel SDM Volume 2A, CPUID instruction
57 */
58struct CPUID2CacheDescriptorInfo cpuid2_cache_descriptors[] = {
5f00335a 59 [0x06] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 8 * KiB,
7e3482f8 60 .associativity = 4, .line_size = 32, },
5f00335a 61 [0x08] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 16 * KiB,
7e3482f8 62 .associativity = 4, .line_size = 32, },
5f00335a 63 [0x09] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB,
7e3482f8 64 .associativity = 4, .line_size = 64, },
5f00335a 65 [0x0A] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB,
7e3482f8 66 .associativity = 2, .line_size = 32, },
5f00335a 67 [0x0C] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
7e3482f8 68 .associativity = 4, .line_size = 32, },
5f00335a 69 [0x0D] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
7e3482f8 70 .associativity = 4, .line_size = 64, },
5f00335a 71 [0x0E] = { .level = 1, .type = DATA_CACHE, .size = 24 * KiB,
7e3482f8 72 .associativity = 6, .line_size = 64, },
5f00335a 73 [0x1D] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB,
7e3482f8 74 .associativity = 2, .line_size = 64, },
5f00335a 75 [0x21] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
7e3482f8
EH		 76 .associativity = 8, .line_size = 64, },
77 /* lines per sector is not supported cpuid2_cache_descriptor(),
78 * so descriptors 0x22, 0x23 are not included
79 */
5f00335a 80 [0x24] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8
EH		 81 .associativity = 16, .line_size = 64, },
82 /* lines per sector is not supported cpuid2_cache_descriptor(),
83 * so descriptors 0x25, 0x20 are not included
84 */
5f00335a 85 [0x2C] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB,
7e3482f8 86 .associativity = 8, .line_size = 64, },
5f00335a 87 [0x30] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB,
7e3482f8 88 .associativity = 8, .line_size = 64, },
5f00335a 89 [0x41] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB,
7e3482f8 90 .associativity = 4, .line_size = 32, },
5f00335a 91 [0x42] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
7e3482f8 92 .associativity = 4, .line_size = 32, },
5f00335a 93 [0x43] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
7e3482f8 94 .associativity = 4, .line_size = 32, },
5f00335a 95 [0x44] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8 96 .associativity = 4, .line_size = 32, },
5f00335a 97 [0x45] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
7e3482f8 98 .associativity = 4, .line_size = 32, },
5f00335a 99 [0x46] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
7e3482f8 100 .associativity = 4, .line_size = 64, },
5f00335a 101 [0x47] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
7e3482f8 102 .associativity = 8, .line_size = 64, },
5f00335a 103 [0x48] = { .level = 2, .type = UNIFIED_CACHE, .size = 3 * MiB,
7e3482f8
EH		 104 .associativity = 12, .line_size = 64, },
105 /* Descriptor 0x49 depends on CPU family/model, so it is not included */
5f00335a 106 [0x4A] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB,
7e3482f8 107 .associativity = 12, .line_size = 64, },
5f00335a 108 [0x4B] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
7e3482f8 109 .associativity = 16, .line_size = 64, },
5f00335a 110 [0x4C] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB,
7e3482f8 111 .associativity = 12, .line_size = 64, },
5f00335a 112 [0x4D] = { .level = 3, .type = UNIFIED_CACHE, .size = 16 * MiB,
7e3482f8 113 .associativity = 16, .line_size = 64, },
5f00335a 114 [0x4E] = { .level = 2, .type = UNIFIED_CACHE, .size = 6 * MiB,
7e3482f8 115 .associativity = 24, .line_size = 64, },
5f00335a 116 [0x60] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
7e3482f8 117 .associativity = 8, .line_size = 64, },
5f00335a 118 [0x66] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB,
7e3482f8 119 .associativity = 4, .line_size = 64, },
5f00335a 120 [0x67] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
7e3482f8 121 .associativity = 4, .line_size = 64, },
5f00335a 122 [0x68] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB,
7e3482f8 123 .associativity = 4, .line_size = 64, },
5f00335a 124 [0x78] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8
EH		 125 .associativity = 4, .line_size = 64, },
126 /* lines per sector is not supported cpuid2_cache_descriptor(),
127 * so descriptors 0x79, 0x7A, 0x7B, 0x7C are not included.
128 */
5f00335a 129 [0x7D] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
7e3482f8 130 .associativity = 8, .line_size = 64, },
5f00335a 131 [0x7F] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
7e3482f8 132 .associativity = 2, .line_size = 64, },
5f00335a 133 [0x80] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
7e3482f8 134 .associativity = 8, .line_size = 64, },
5f00335a 135 [0x82] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
7e3482f8 136 .associativity = 8, .line_size = 32, },
5f00335a 137 [0x83] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
7e3482f8 138 .associativity = 8, .line_size = 32, },
5f00335a 139 [0x84] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8 140 .associativity = 8, .line_size = 32, },
5f00335a 141 [0x85] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
7e3482f8 142 .associativity = 8, .line_size = 32, },
5f00335a 143 [0x86] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
7e3482f8 144 .associativity = 4, .line_size = 64, },
5f00335a 145 [0x87] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8 146 .associativity = 8, .line_size = 64, },
5f00335a 147 [0xD0] = { .level = 3, .type = UNIFIED_CACHE, .size = 512 * KiB,
7e3482f8 148 .associativity = 4, .line_size = 64, },
5f00335a 149 [0xD1] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8 150 .associativity = 4, .line_size = 64, },
5f00335a 151 [0xD2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
7e3482f8 152 .associativity = 4, .line_size = 64, },
5f00335a 153 [0xD6] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8 154 .associativity = 8, .line_size = 64, },
5f00335a 155 [0xD7] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
7e3482f8 156 .associativity = 8, .line_size = 64, },
5f00335a 157 [0xD8] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
7e3482f8 158 .associativity = 8, .line_size = 64, },
5f00335a 159 [0xDC] = { .level = 3, .type = UNIFIED_CACHE, .size = 1.5 * MiB,
7e3482f8 160 .associativity = 12, .line_size = 64, },
5f00335a 161 [0xDD] = { .level = 3, .type = UNIFIED_CACHE, .size = 3 * MiB,
7e3482f8 162 .associativity = 12, .line_size = 64, },
5f00335a 163 [0xDE] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB,
7e3482f8 164 .associativity = 12, .line_size = 64, },
5f00335a 165 [0xE2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
7e3482f8 166 .associativity = 16, .line_size = 64, },
5f00335a 167 [0xE3] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
7e3482f8 168 .associativity = 16, .line_size = 64, },
5f00335a 169 [0xE4] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
7e3482f8 170 .associativity = 16, .line_size = 64, },
5f00335a 171 [0xEA] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB,
7e3482f8 172 .associativity = 24, .line_size = 64, },
5f00335a 173 [0xEB] = { .level = 3, .type = UNIFIED_CACHE, .size = 18 * MiB,
7e3482f8 174 .associativity = 24, .line_size = 64, },
5f00335a 175 [0xEC] = { .level = 3, .type = UNIFIED_CACHE, .size = 24 * MiB,
7e3482f8
EH		 176 .associativity = 24, .line_size = 64, },
177};
178
179/*
180 * "CPUID leaf 2 does not report cache descriptor information,
181 * use CPUID leaf 4 to query cache parameters"
182 */
183#define CACHE_DESCRIPTOR_UNAVAILABLE 0xFF
5e891bf8 184
7e3482f8
EH		 185/*
186 * Return a CPUID 2 cache descriptor for a given cache.
187 * If no known descriptor is found, return CACHE_DESCRIPTOR_UNAVAILABLE
188 */
189static uint8_t cpuid2_cache_descriptor(CPUCacheInfo *cache)
190{
191 int i;
192
193 assert(cache->size > 0);
194 assert(cache->level > 0);
195 assert(cache->line_size > 0);
196 assert(cache->associativity > 0);
197 for (i = 0; i < ARRAY_SIZE(cpuid2_cache_descriptors); i++) {
198 struct CPUID2CacheDescriptorInfo *d = &cpuid2_cache_descriptors[i];
199 if (d->level == cache->level && d->type == cache->type &&
200 d->size == cache->size && d->line_size == cache->line_size &&
201 d->associativity == cache->associativity) {
202 return i;
203 }
204 }
5e891bf8 205
7e3482f8
EH		 206 return CACHE_DESCRIPTOR_UNAVAILABLE;
207}
5e891bf8
EH		 208
209/* CPUID Leaf 4 constants: */
210
211/* EAX: */
7e3482f8
EH		 212#define CACHE_TYPE_D 1
213#define CACHE_TYPE_I 2
214#define CACHE_TYPE_UNIFIED 3
5e891bf8 215
7e3482f8 216#define CACHE_LEVEL(l) (l << 5)
5e891bf8 217
7e3482f8 218#define CACHE_SELF_INIT_LEVEL (1 << 8)
5e891bf8
EH		 219
220/* EDX: */
7e3482f8
EH		 221#define CACHE_NO_INVD_SHARING (1 << 0)
222#define CACHE_INCLUSIVE (1 << 1)
223#define CACHE_COMPLEX_IDX (1 << 2)
224
225/* Encode CacheType for CPUID[4].EAX */
5f00335a
EH		 226#define CACHE_TYPE(t) (((t) == DATA_CACHE) ? CACHE_TYPE_D : \
227 ((t) == INSTRUCTION_CACHE) ? CACHE_TYPE_I : \
228 ((t) == UNIFIED_CACHE) ? CACHE_TYPE_UNIFIED : \
229 0 /* Invalid value */)
7e3482f8
EH		 230
231
232/* Encode cache info for CPUID[4] */
233static void encode_cache_cpuid4(CPUCacheInfo *cache,
234 int num_apic_ids, int num_cores,
235 uint32_t *eax, uint32_t *ebx,
236 uint32_t *ecx, uint32_t *edx)
237{
238 assert(cache->size == cache->line_size * cache->associativity *
239 cache->partitions * cache->sets);
240
241 assert(num_apic_ids > 0);
242 *eax = CACHE_TYPE(cache->type) |
243 CACHE_LEVEL(cache->level) |
244 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0) |
245 ((num_cores - 1) << 26) |
246 ((num_apic_ids - 1) << 14);
247
248 assert(cache->line_size > 0);
249 assert(cache->partitions > 0);
250 assert(cache->associativity > 0);
251 /* We don't implement fully-associative caches */
252 assert(cache->associativity < cache->sets);
253 *ebx = (cache->line_size - 1) |
254 ((cache->partitions - 1) << 12) |
255 ((cache->associativity - 1) << 22);
256
257 assert(cache->sets > 0);
258 *ecx = cache->sets - 1;
259
260 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) |
261 (cache->inclusive ? CACHE_INCLUSIVE : 0) |
262 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0);
263}
264
265/* Encode cache info for CPUID[0x80000005].ECX or CPUID[0x80000005].EDX */
266static uint32_t encode_cache_cpuid80000005(CPUCacheInfo *cache)
267{
268 assert(cache->size % 1024 == 0);
269 assert(cache->lines_per_tag > 0);
270 assert(cache->associativity > 0);
271 assert(cache->line_size > 0);
272 return ((cache->size / 1024) << 24) | (cache->associativity << 16) |
273 (cache->lines_per_tag << 8) | (cache->line_size);
274}
5e891bf8
EH		 275
276#define ASSOC_FULL 0xFF
277
278/* AMD associativity encoding used on CPUID Leaf 0x80000006: */
279#define AMD_ENC_ASSOC(a) (a <= 1 ? a : \
280 a == 2 ? 0x2 : \
281 a == 4 ? 0x4 : \
282 a == 8 ? 0x6 : \
283 a == 16 ? 0x8 : \
284 a == 32 ? 0xA : \
285 a == 48 ? 0xB : \
286 a == 64 ? 0xC : \
287 a == 96 ? 0xD : \
288 a == 128 ? 0xE : \
289 a == ASSOC_FULL ? 0xF : \
290 0 /* invalid value */)
291
7e3482f8
EH		 292/*
293 * Encode cache info for CPUID[0x80000006].ECX and CPUID[0x80000006].EDX
294 * @l3 can be NULL.
295 */
296static void encode_cache_cpuid80000006(CPUCacheInfo *l2,
297 CPUCacheInfo *l3,
298 uint32_t *ecx, uint32_t *edx)
299{
300 assert(l2->size % 1024 == 0);
301 assert(l2->associativity > 0);
302 assert(l2->lines_per_tag > 0);
303 assert(l2->line_size > 0);
304 *ecx = ((l2->size / 1024) << 16) |
305 (AMD_ENC_ASSOC(l2->associativity) << 12) |
306 (l2->lines_per_tag << 8) | (l2->line_size);
307
308 if (l3) {
309 assert(l3->size % (512 * 1024) == 0);
310 assert(l3->associativity > 0);
311 assert(l3->lines_per_tag > 0);
312 assert(l3->line_size > 0);
313 *edx = ((l3->size / (512 * 1024)) << 18) |
314 (AMD_ENC_ASSOC(l3->associativity) << 12) |
315 (l3->lines_per_tag << 8) | (l3->line_size);
316 } else {
317 *edx = 0;
318 }
319}
5e891bf8 320
8f4202fb 321/* Encode cache info for CPUID[8000001D] */
2f084d1e
BM		 322static void encode_cache_cpuid8000001d(CPUCacheInfo *cache,
323 X86CPUTopoInfo *topo_info,
324 uint32_t *eax, uint32_t *ebx,
325 uint32_t *ecx, uint32_t *edx)
8f4202fb 326{
2f084d1e 327 uint32_t l3_threads;
8f4202fb
BM		 328 assert(cache->size == cache->line_size * cache->associativity *
329 cache->partitions * cache->sets);
330
331 *eax = CACHE_TYPE(cache->type) | CACHE_LEVEL(cache->level) |
332 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0);
333
334 /* L3 is shared among multiple cores */
335 if (cache->level == 3) {
2f084d1e
BM		 336 l3_threads = topo_info->cores_per_die * topo_info->threads_per_core;
337 *eax |= (l3_threads - 1) << 14;
8f4202fb 338 } else {
2f084d1e 339 *eax |= ((topo_info->threads_per_core - 1) << 14);
8f4202fb
BM		 340 }
341
342 assert(cache->line_size > 0);
343 assert(cache->partitions > 0);
344 assert(cache->associativity > 0);
345 /* We don't implement fully-associative caches */
346 assert(cache->associativity < cache->sets);
347 *ebx = (cache->line_size - 1) |
348 ((cache->partitions - 1) << 12) |
349 ((cache->associativity - 1) << 22);
350
351 assert(cache->sets > 0);
352 *ecx = cache->sets - 1;
353
354 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) |
355 (cache->inclusive ? CACHE_INCLUSIVE : 0) |
356 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0);
357}
358
ed78467a 359/* Encode cache info for CPUID[8000001E] */
31ada106
BM		 360static void encode_topo_cpuid8000001e(X86CPU *cpu, X86CPUTopoInfo *topo_info,
361 uint32_t *eax, uint32_t *ebx,
362 uint32_t *ecx, uint32_t *edx)
ed78467a 363{
31ada106
BM		 364 X86CPUTopoIDs topo_ids;
365
366 x86_topo_ids_from_apicid(cpu->apic_id, topo_info, &topo_ids);
ed78467a 367
ed78467a 368 *eax = cpu->apic_id;
31ada106 369
ed78467a 370 /*
31ada106
BM		 371 * CPUID_Fn8000001E_EBX [Core Identifiers] (CoreId)
372 * Read-only. Reset: 0000_XXXXh.
373 * See Core::X86::Cpuid::ExtApicId.
374 * Core::X86::Cpuid::CoreId_lthree[1:0]_core[3:0]_thread[1:0];
375 * Bits Description
376 * 31:16 Reserved.
377 * 15:8 ThreadsPerCore: threads per core. Read-only. Reset: XXh.
378 * The number of threads per core is ThreadsPerCore+1.
379 * 7:0 CoreId: core ID. Read-only. Reset: XXh.
380 *
381 * NOTE: CoreId is already part of apic_id. Just use it. We can
382 * use all the 8 bits to represent the core_id here.
ed78467a 383 */
31ada106
BM		 384 *ebx = ((topo_info->threads_per_core - 1) << 8) | (topo_ids.core_id & 0xFF);
385
ed78467a 386 /*
31ada106
BM		 387 * CPUID_Fn8000001E_ECX [Node Identifiers] (NodeId)
388 * Read-only. Reset: 0000_0XXXh.
389 * Core::X86::Cpuid::NodeId_lthree[1:0]_core[3:0]_thread[1:0];
390 * Bits Description
391 * 31:11 Reserved.
392 * 10:8 NodesPerProcessor: Node per processor. Read-only. Reset: XXXb.
393 * ValidValues:
394 * Value Description
395 * 000b 1 node per processor.
396 * 001b 2 nodes per processor.
397 * 010b Reserved.
398 * 011b 4 nodes per processor.
399 * 111b-100b Reserved.
400 * 7:0 NodeId: Node ID. Read-only. Reset: XXh.
401 *
402 * NOTE: Hardware reserves 3 bits for number of nodes per processor.
403 * But users can create more nodes than the actual hardware can
404 * support. To genaralize we can use all the upper 8 bits for nodes.
405 * NodeId is combination of node and socket_id which is already decoded
406 * in apic_id. Just use it by shifting.
ed78467a 407 */
31ada106
BM		 408 *ecx = ((topo_info->dies_per_pkg - 1) << 8) |
409 ((cpu->apic_id >> apicid_die_offset(topo_info)) & 0xFF);
410
ed78467a
BM		 411 *edx = 0;
412}
413
ab8f992e
BM		 414/*
415 * Definitions of the hardcoded cache entries we expose:
416 * These are legacy cache values. If there is a need to change any
417 * of these values please use builtin_x86_defs
418 */
5e891bf8
EH		 419
420/* L1 data cache: */
ab8f992e 421static CPUCacheInfo legacy_l1d_cache = {
5f00335a 422 .type = DATA_CACHE,
7e3482f8
EH		 423 .level = 1,
424 .size = 32 * KiB,
425 .self_init = 1,
426 .line_size = 64,
427 .associativity = 8,
428 .sets = 64,
429 .partitions = 1,
430 .no_invd_sharing = true,
431};
432
5e891bf8 433/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
ab8f992e 434static CPUCacheInfo legacy_l1d_cache_amd = {
5f00335a 435 .type = DATA_CACHE,
7e3482f8
EH		 436 .level = 1,
437 .size = 64 * KiB,
438 .self_init = 1,
439 .line_size = 64,
440 .associativity = 2,
441 .sets = 512,
442 .partitions = 1,
443 .lines_per_tag = 1,
444 .no_invd_sharing = true,
445};
5e891bf8
EH		 446
447/* L1 instruction cache: */
ab8f992e 448static CPUCacheInfo legacy_l1i_cache = {
5f00335a 449 .type = INSTRUCTION_CACHE,
7e3482f8
EH		 450 .level = 1,
451 .size = 32 * KiB,
452 .self_init = 1,
453 .line_size = 64,
454 .associativity = 8,
455 .sets = 64,
456 .partitions = 1,
457 .no_invd_sharing = true,
458};
459
5e891bf8 460/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
ab8f992e 461static CPUCacheInfo legacy_l1i_cache_amd = {
5f00335a 462 .type = INSTRUCTION_CACHE,
7e3482f8
EH		 463 .level = 1,
464 .size = 64 * KiB,
465 .self_init = 1,
466 .line_size = 64,
467 .associativity = 2,
468 .sets = 512,
469 .partitions = 1,
470 .lines_per_tag = 1,
471 .no_invd_sharing = true,
472};
5e891bf8
EH		 473
474/* Level 2 unified cache: */
ab8f992e 475static CPUCacheInfo legacy_l2_cache = {
7e3482f8
EH		 476 .type = UNIFIED_CACHE,
477 .level = 2,
478 .size = 4 * MiB,
479 .self_init = 1,
480 .line_size = 64,
481 .associativity = 16,
482 .sets = 4096,
483 .partitions = 1,
484 .no_invd_sharing = true,
485};
486
5e891bf8 487/*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
ab8f992e 488static CPUCacheInfo legacy_l2_cache_cpuid2 = {
7e3482f8
EH		 489 .type = UNIFIED_CACHE,
490 .level = 2,
491 .size = 2 * MiB,
492 .line_size = 64,
493 .associativity = 8,
494};
495
496
5e891bf8 497/*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
ab8f992e 498static CPUCacheInfo legacy_l2_cache_amd = {
7e3482f8
EH		 499 .type = UNIFIED_CACHE,
500 .level = 2,
501 .size = 512 * KiB,
502 .line_size = 64,
503 .lines_per_tag = 1,
504 .associativity = 16,
505 .sets = 512,
506 .partitions = 1,
507};
5e891bf8 508
14c985cf 509/* Level 3 unified cache: */
ab8f992e 510static CPUCacheInfo legacy_l3_cache = {
7e3482f8
EH		 511 .type = UNIFIED_CACHE,
512 .level = 3,
513 .size = 16 * MiB,
514 .line_size = 64,
515 .associativity = 16,
516 .sets = 16384,
517 .partitions = 1,
518 .lines_per_tag = 1,
519 .self_init = true,
520 .inclusive = true,
521 .complex_indexing = true,
522};
5e891bf8
EH		 523
524/* TLB definitions: */
525
526#define L1_DTLB_2M_ASSOC 1
527#define L1_DTLB_2M_ENTRIES 255
528#define L1_DTLB_4K_ASSOC 1
529#define L1_DTLB_4K_ENTRIES 255
530
531#define L1_ITLB_2M_ASSOC 1
532#define L1_ITLB_2M_ENTRIES 255
533#define L1_ITLB_4K_ASSOC 1
534#define L1_ITLB_4K_ENTRIES 255
535
536#define L2_DTLB_2M_ASSOC 0 /* disabled */
537#define L2_DTLB_2M_ENTRIES 0 /* disabled */
538#define L2_DTLB_4K_ASSOC 4
539#define L2_DTLB_4K_ENTRIES 512
540
541#define L2_ITLB_2M_ASSOC 0 /* disabled */
542#define L2_ITLB_2M_ENTRIES 0 /* disabled */
543#define L2_ITLB_4K_ASSOC 4
544#define L2_ITLB_4K_ENTRIES 512
545
e37a5c7f
CP		 546/* CPUID Leaf 0x14 constants: */
547#define INTEL_PT_MAX_SUBLEAF 0x1
548/*
549 * bit[00]: IA32_RTIT_CTL.CR3 filter can be set to 1 and IA32_RTIT_CR3_MATCH
550 * MSR can be accessed;
551 * bit[01]: Support Configurable PSB and Cycle-Accurate Mode;
552 * bit[02]: Support IP Filtering, TraceStop filtering, and preservation
553 * of Intel PT MSRs across warm reset;
554 * bit[03]: Support MTC timing packet and suppression of COFI-based packets;
555 */
556#define INTEL_PT_MINIMAL_EBX 0xf
557/*
558 * bit[00]: Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1 and
559 * IA32_RTIT_OUTPUT_BASE and IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be
560 * accessed;
561 * bit[01]: ToPA tables can hold any number of output entries, up to the
562 * maximum allowed by the MaskOrTableOffset field of
563 * IA32_RTIT_OUTPUT_MASK_PTRS;
564 * bit[02]: Support Single-Range Output scheme;
565 */
566#define INTEL_PT_MINIMAL_ECX 0x7
c078ca96
LK		 567/* generated packets which contain IP payloads have LIP values */
568#define INTEL_PT_IP_LIP (1 << 31)
e37a5c7f
CP		 569#define INTEL_PT_ADDR_RANGES_NUM 0x2 /* Number of configurable address ranges */
570#define INTEL_PT_ADDR_RANGES_NUM_MASK 0x3
571#define INTEL_PT_MTC_BITMAP (0x0249 << 16) /* Support ART(0,3,6,9) */
572#define INTEL_PT_CYCLE_BITMAP 0x1fff /* Support 0,2^(0~11) */
573#define INTEL_PT_PSB_BITMAP (0x003f << 16) /* Support 2K,4K,8K,16K,32K,64K */
5e891bf8 574
f5cc5a5c
CF		 575void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
576 uint32_t vendor2, uint32_t vendor3)
99b88a17
IM		 577{
578 int i;
579 for (i = 0; i < 4; i++) {
580 dst[i] = vendor1 >> (8 * i);
581 dst[i + 4] = vendor2 >> (8 * i);
582 dst[i + 8] = vendor3 >> (8 * i);
583 }
584 dst[CPUID_VENDOR_SZ] = '\0';
585}
586
621626ce
EH		 587#define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
588#define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
589 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
590#define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
591 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
592 CPUID_PSE36 | CPUID_FXSR)
593#define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
594#define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
595 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
596 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
597 CPUID_PAE | CPUID_SEP | CPUID_APIC)
598
599#define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
600 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
601 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
602 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
b6c5a6f0 603 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE)
621626ce
EH		 604 /* partly implemented:
605 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */
606 /* missing:
607 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
608#define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
609 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
610 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
19dc85db 611 CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \
369fd5ca
RH		 612 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR | \
613 CPUID_EXT_RDRAND)
621626ce
EH		 614 /* missing:
615 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
616 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
617 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
19dc85db 618 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_AVX,
369fd5ca 619 CPUID_EXT_F16C */
621626ce
EH		 620
621#ifdef TARGET_X86_64
622#define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM)
623#else
624#define TCG_EXT2_X86_64_FEATURES 0
625#endif
626
627#define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
628 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
629 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \
630 TCG_EXT2_X86_64_FEATURES)
631#define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
632 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
633#define TCG_EXT4_FEATURES 0
fe441054 634#define TCG_SVM_FEATURES CPUID_SVM_NPT
621626ce
EH		 635#define TCG_KVM_FEATURES 0
636#define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \
0c47242b
XG		 637 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \
638 CPUID_7_0_EBX_PCOMMIT | CPUID_7_0_EBX_CLFLUSHOPT | \
7eb24386
PB		 639 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \
640 CPUID_7_0_EBX_ERMS)
621626ce 641 /* missing:
07929f2a 642 CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
7eb24386 643 CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
621626ce 644 CPUID_7_0_EBX_RDSEED */
9ccb9784
EH		 645#define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_PKU | \
646 /* CPUID_7_0_ECX_OSPKE is dynamic */ \
e7e7bdab 647 CPUID_7_0_ECX_LA57 | CPUID_7_0_ECX_PKS)
95ea69fb 648#define TCG_7_0_EDX_FEATURES 0
80db491d 649#define TCG_7_1_EAX_FEATURES 0
303752a9 650#define TCG_APM_FEATURES 0
28b8e4d0 651#define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT
c9cfe8f9
RH		 652#define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1)
653 /* missing:
654 CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */
d1615ea5 655#define TCG_14_0_ECX_FEATURES 0
621626ce 656
79f1a68a 657FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
bffd67b0 658 [FEAT_1_EDX] = {
07585923 659 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 660 .feat_names = {
661 "fpu", "vme", "de", "pse",
662 "tsc", "msr", "pae", "mce",
663 "cx8", "apic", NULL, "sep",
664 "mtrr", "pge", "mca", "cmov",
665 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
666 NULL, "ds" /* Intel dts */, "acpi", "mmx",
667 "fxsr", "sse", "sse2", "ss",
668 "ht" /* Intel htt */, "tm", "ia64", "pbe",
669 },
07585923 670 .cpuid = {.eax = 1, .reg = R_EDX, },
37ce3522 671 .tcg_features = TCG_FEATURES,
bffd67b0
EH		 672 },
673 [FEAT_1_ECX] = {
07585923 674 .type = CPUID_FEATURE_WORD,
2d5312da 675 .feat_names = {
16d2fcaa 676 "pni" /* Intel,AMD sse3 */, "pclmulqdq", "dtes64", "monitor",
fc7dfd20 677 "ds-cpl", "vmx", "smx", "est",
2d5312da
EH		 678 "tm2", "ssse3", "cid", NULL,
679 "fma", "cx16", "xtpr", "pdcm",
16d2fcaa
EH		 680 NULL, "pcid", "dca", "sse4.1",
681 "sse4.2", "x2apic", "movbe", "popcnt",
f1a23522 682 "tsc-deadline", "aes", "xsave", NULL /* osxsave */,
2d5312da
EH		 683 "avx", "f16c", "rdrand", "hypervisor",
684 },
07585923 685 .cpuid = { .eax = 1, .reg = R_ECX, },
37ce3522 686 .tcg_features = TCG_EXT_FEATURES,
bffd67b0 687 },
2d5312da
EH		 688 /* Feature names that are already defined on feature_name[] but
689 * are set on CPUID[8000_0001].EDX on AMD CPUs don't have their
690 * names on feat_names below. They are copied automatically
691 * to features[FEAT_8000_0001_EDX] if and only if CPU vendor is AMD.
692 */
bffd67b0 693 [FEAT_8000_0001_EDX] = {
07585923 694 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 695 .feat_names = {
696 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
697 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
698 NULL /* cx8 */, NULL /* apic */, NULL, "syscall",
699 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
700 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
16d2fcaa
EH		 701 "nx", NULL, "mmxext", NULL /* mmx */,
702 NULL /* fxsr */, "fxsr-opt", "pdpe1gb", "rdtscp",
703 NULL, "lm", "3dnowext", "3dnow",
2d5312da 704 },
07585923 705 .cpuid = { .eax = 0x80000001, .reg = R_EDX, },
37ce3522 706 .tcg_features = TCG_EXT2_FEATURES,
bffd67b0
EH		 707 },
708 [FEAT_8000_0001_ECX] = {
07585923 709 .type = CPUID_FEATURE_WORD,
2d5312da 710 .feat_names = {
fc7dfd20 711 "lahf-lm", "cmp-legacy", "svm", "extapic",
2d5312da
EH		 712 "cr8legacy", "abm", "sse4a", "misalignsse",
713 "3dnowprefetch", "osvw", "ibs", "xop",
714 "skinit", "wdt", NULL, "lwp",
fc7dfd20
EH		 715 "fma4", "tce", NULL, "nodeid-msr",
716 NULL, "tbm", "topoext", "perfctr-core",
717 "perfctr-nb", NULL, NULL, NULL,
2d5312da
EH		 718 NULL, NULL, NULL, NULL,
719 },
07585923 720 .cpuid = { .eax = 0x80000001, .reg = R_ECX, },
37ce3522 721 .tcg_features = TCG_EXT3_FEATURES,
7210a02c
EH		 722 /*
723 * TOPOEXT is always allowed but can't be enabled blindly by
724 * "-cpu host", as it requires consistent cache topology info
725 * to be provided so it doesn't confuse guests.
726 */
727 .no_autoenable_flags = CPUID_EXT3_TOPOEXT,
bffd67b0 728 },
89e49c8b 729 [FEAT_C000_0001_EDX] = {
07585923 730 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 731 .feat_names = {
732 NULL, NULL, "xstore", "xstore-en",
733 NULL, NULL, "xcrypt", "xcrypt-en",
734 "ace2", "ace2-en", "phe", "phe-en",
735 "pmm", "pmm-en", NULL, NULL,
736 NULL, NULL, NULL, NULL,
737 NULL, NULL, NULL, NULL,
738 NULL, NULL, NULL, NULL,
739 NULL, NULL, NULL, NULL,
740 },
07585923 741 .cpuid = { .eax = 0xC0000001, .reg = R_EDX, },
37ce3522 742 .tcg_features = TCG_EXT4_FEATURES,
89e49c8b 743 },
bffd67b0 744 [FEAT_KVM] = {
07585923 745 .type = CPUID_FEATURE_WORD,
2d5312da 746 .feat_names = {
fc7dfd20
EH		 747 "kvmclock", "kvm-nopiodelay", "kvm-mmu", "kvmclock",
748 "kvm-asyncpf", "kvm-steal-time", "kvm-pv-eoi", "kvm-pv-unhalt",
7f710c32 749 NULL, "kvm-pv-tlb-flush", NULL, "kvm-pv-ipi",
c1bb5418 750 "kvm-poll-control", "kvm-pv-sched-yield", "kvm-asyncpf-int", "kvm-msi-ext-dest-id",
2d5312da
EH		 751 NULL, NULL, NULL, NULL,
752 NULL, NULL, NULL, NULL,
753 "kvmclock-stable-bit", NULL, NULL, NULL,
754 NULL, NULL, NULL, NULL,
755 },
07585923 756 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EAX, },
37ce3522 757 .tcg_features = TCG_KVM_FEATURES,
bffd67b0 758 },
be777326 759 [FEAT_KVM_HINTS] = {
07585923 760 .type = CPUID_FEATURE_WORD,
be777326
WL		 761 .feat_names = {
762 "kvm-hint-dedicated", NULL, NULL, NULL,
763 NULL, NULL, NULL, NULL,
764 NULL, NULL, NULL, NULL,
765 NULL, NULL, NULL, NULL,
766 NULL, NULL, NULL, NULL,
767 NULL, NULL, NULL, NULL,
768 NULL, NULL, NULL, NULL,
769 NULL, NULL, NULL, NULL,
770 },
07585923 771 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EDX, },
be777326 772 .tcg_features = TCG_KVM_FEATURES,
0d914f39
EH		 773 /*
774 * KVM hints aren't auto-enabled by -cpu host, they need to be
775 * explicitly enabled in the command-line.
776 */
777 .no_autoenable_flags = ~0U,
be777326 778 },
bffd67b0 779 [FEAT_SVM] = {
07585923 780 .type = CPUID_FEATURE_WORD,
2d5312da 781 .feat_names = {
fc7dfd20
EH		 782 "npt", "lbrv", "svm-lock", "nrip-save",
783 "tsc-scale", "vmcb-clean", "flushbyasid", "decodeassists",
784 NULL, NULL, "pause-filter", NULL,
5447089c
WH		 785 "pfthreshold", "avic", NULL, "v-vmsave-vmload",
786 "vgif", NULL, NULL, NULL,
2d5312da
EH		 787 NULL, NULL, NULL, NULL,
788 NULL, NULL, NULL, NULL,
5447089c 789 "svme-addr-chk", NULL, NULL, NULL,
2d5312da 790 },
07585923 791 .cpuid = { .eax = 0x8000000A, .reg = R_EDX, },
37ce3522 792 .tcg_features = TCG_SVM_FEATURES,
bffd67b0
EH		 793 },
794 [FEAT_7_0_EBX] = {
07585923 795 .type = CPUID_FEATURE_WORD,
2d5312da 796 .feat_names = {
fc7dfd20 797 "fsgsbase", "tsc-adjust", NULL, "bmi1",
2d5312da
EH		 798 "hle", "avx2", NULL, "smep",
799 "bmi2", "erms", "invpcid", "rtm",
800 NULL, NULL, "mpx", NULL,
801 "avx512f", "avx512dq", "rdseed", "adx",
802 "smap", "avx512ifma", "pcommit", "clflushopt",
e37a5c7f 803 "clwb", "intel-pt", "avx512pf", "avx512er",
638cbd45 804 "avx512cd", "sha-ni", "avx512bw", "avx512vl",
2d5312da 805 },
07585923
RH		 806 .cpuid = {
807 .eax = 7,
808 .needs_ecx = true, .ecx = 0,
809 .reg = R_EBX,
810 },
37ce3522 811 .tcg_features = TCG_7_0_EBX_FEATURES,
bffd67b0 812 },
f74eefe0 813 [FEAT_7_0_ECX] = {
07585923 814 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 815 .feat_names = {
816 NULL, "avx512vbmi", "umip", "pku",
67192a29 817 NULL /* ospke */, "waitpkg", "avx512vbmi2", NULL,
aff9e6e4
YZ		 818 "gfni", "vaes", "vpclmulqdq", "avx512vnni",
819 "avx512bitalg", NULL, "avx512-vpopcntdq", NULL,
6c7c3c21 820 "la57", NULL, NULL, NULL,
2d5312da 821 NULL, NULL, "rdpid", NULL,
06e878b4 822 "bus-lock-detect", "cldemote", NULL, "movdiri",
e7e7bdab 823 "movdir64b", NULL, NULL, "pks",
2d5312da 824 },
07585923
RH		 825 .cpuid = {
826 .eax = 7,
827 .needs_ecx = true, .ecx = 0,
828 .reg = R_ECX,
829 },
f74eefe0
HH		 830 .tcg_features = TCG_7_0_ECX_FEATURES,
831 },
95ea69fb 832 [FEAT_7_0_EDX] = {
07585923 833 .type = CPUID_FEATURE_WORD,
95ea69fb
LK		 834 .feat_names = {
835 NULL, NULL, "avx512-4vnniw", "avx512-4fmaps",
5cb287d2 836 "fsrm", NULL, NULL, NULL,
353f98c9 837 "avx512-vp2intersect", NULL, "md-clear", NULL,
5dd13f2a 838 NULL, NULL, "serialize", NULL,
b3c7344e 839 "tsx-ldtrk", NULL, NULL /* pconfig */, NULL,
40399ecb 840 NULL, NULL, NULL, "avx512-fp16",
0e891658 841 NULL, NULL, "spec-ctrl", "stibp",
597360c0 842 NULL, "arch-capabilities", "core-capability", "ssbd",
95ea69fb 843 },
07585923
RH		 844 .cpuid = {
845 .eax = 7,
846 .needs_ecx = true, .ecx = 0,
847 .reg = R_EDX,
848 },
95ea69fb
LK		 849 .tcg_features = TCG_7_0_EDX_FEATURES,
850 },
80db491d
JL		 851 [FEAT_7_1_EAX] = {
852 .type = CPUID_FEATURE_WORD,
853 .feat_names = {
854 NULL, NULL, NULL, NULL,
c1826ea6 855 "avx-vnni", "avx512-bf16", NULL, NULL,
80db491d
JL		 856 NULL, NULL, NULL, NULL,
857 NULL, NULL, NULL, NULL,
858 NULL, NULL, NULL, NULL,
859 NULL, NULL, NULL, NULL,
860 NULL, NULL, NULL, NULL,
861 NULL, NULL, NULL, NULL,
862 },
863 .cpuid = {
864 .eax = 7,
865 .needs_ecx = true, .ecx = 1,
866 .reg = R_EAX,
867 },
868 .tcg_features = TCG_7_1_EAX_FEATURES,
869 },
303752a9 870 [FEAT_8000_0007_EDX] = {
07585923 871 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 872 .feat_names = {
873 NULL, NULL, NULL, NULL,
874 NULL, NULL, NULL, NULL,
875 "invtsc", NULL, NULL, NULL,
876 NULL, NULL, NULL, NULL,
877 NULL, NULL, NULL, NULL,
878 NULL, NULL, NULL, NULL,
879 NULL, NULL, NULL, NULL,
880 NULL, NULL, NULL, NULL,
881 },
07585923 882 .cpuid = { .eax = 0x80000007, .reg = R_EDX, },
303752a9
MT		 883 .tcg_features = TCG_APM_FEATURES,
884 .unmigratable_flags = CPUID_APM_INVTSC,
885 },
1b3420e1 886 [FEAT_8000_0008_EBX] = {
07585923 887 .type = CPUID_FEATURE_WORD,
1b3420e1 888 .feat_names = {
e900135d 889 "clzero", NULL, "xsaveerptr", NULL,
1b3420e1 890 NULL, NULL, NULL, NULL,
59a80a19 891 NULL, "wbnoinvd", NULL, NULL,
623972ce 892 "ibpb", NULL, "ibrs", "amd-stibp",
1b3420e1
EH		 893 NULL, NULL, NULL, NULL,
894 NULL, NULL, NULL, NULL,
254790a9 895 "amd-ssbd", "virt-ssbd", "amd-no-ssb", NULL,
1b3420e1
EH		 896 NULL, NULL, NULL, NULL,
897 },
07585923 898 .cpuid = { .eax = 0x80000008, .reg = R_EBX, },
1b3420e1
EH		 899 .tcg_features = 0,
900 .unmigratable_flags = 0,
901 },
0bb0b2d2 902 [FEAT_XSAVE] = {
07585923 903 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 904 .feat_names = {
905 "xsaveopt", "xsavec", "xgetbv1", "xsaves",
906 NULL, NULL, NULL, NULL,
907 NULL, NULL, NULL, NULL,
908 NULL, NULL, NULL, NULL,
909 NULL, NULL, NULL, NULL,
910 NULL, NULL, NULL, NULL,
911 NULL, NULL, NULL, NULL,
912 NULL, NULL, NULL, NULL,
913 },
07585923
RH		 914 .cpuid = {
915 .eax = 0xd,
916 .needs_ecx = true, .ecx = 1,
917 .reg = R_EAX,
918 },
c9cfe8f9 919 .tcg_features = TCG_XSAVE_FEATURES,
0bb0b2d2 920 },
28b8e4d0 921 [FEAT_6_EAX] = {
07585923 922 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 923 .feat_names = {
924 NULL, NULL, "arat", NULL,
925 NULL, NULL, NULL, NULL,
926 NULL, NULL, NULL, NULL,
927 NULL, NULL, NULL, NULL,
928 NULL, NULL, NULL, NULL,
929 NULL, NULL, NULL, NULL,
930 NULL, NULL, NULL, NULL,
931 NULL, NULL, NULL, NULL,
932 },
07585923 933 .cpuid = { .eax = 6, .reg = R_EAX, },
28b8e4d0
JK		 934 .tcg_features = TCG_6_EAX_FEATURES,
935 },
96193c22 936 [FEAT_XSAVE_COMP_LO] = {
07585923
RH		 937 .type = CPUID_FEATURE_WORD,
938 .cpuid = {
939 .eax = 0xD,
940 .needs_ecx = true, .ecx = 0,
941 .reg = R_EAX,
942 },
96193c22 943 .tcg_features = ~0U,
6fb2fff7
EH		 944 .migratable_flags = XSTATE_FP_MASK | XSTATE_SSE_MASK |
945 XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK |
946 XSTATE_OPMASK_MASK | XSTATE_ZMM_Hi256_MASK | XSTATE_Hi16_ZMM_MASK |
947 XSTATE_PKRU_MASK,
96193c22
EH		 948 },
949 [FEAT_XSAVE_COMP_HI] = {
07585923
RH		 950 .type = CPUID_FEATURE_WORD,
951 .cpuid = {
952 .eax = 0xD,
953 .needs_ecx = true, .ecx = 0,
954 .reg = R_EDX,
955 },
96193c22
EH		 956 .tcg_features = ~0U,
957 },
d86f9636
RH		 958 /*Below are MSR exposed features*/
959 [FEAT_ARCH_CAPABILITIES] = {
960 .type = MSR_FEATURE_WORD,
961 .feat_names = {
962 "rdctl-no", "ibrs-all", "rsba", "skip-l1dfl-vmentry",
2a9758c5 963 "ssb-no", "mds-no", "pschange-mc-no", "tsx-ctrl",
7fac3863 964 "taa-no", NULL, NULL, NULL,
d86f9636
RH		 965 NULL, NULL, NULL, NULL,
966 NULL, NULL, NULL, NULL,
967 NULL, NULL, NULL, NULL,
968 NULL, NULL, NULL, NULL,
969 NULL, NULL, NULL, NULL,
970 },
971 .msr = {
972 .index = MSR_IA32_ARCH_CAPABILITIES,
d86f9636
RH		 973 },
974 },
597360c0
XL		 975 [FEAT_CORE_CAPABILITY] = {
976 .type = MSR_FEATURE_WORD,
977 .feat_names = {
978 NULL, NULL, NULL, NULL,
979 NULL, "split-lock-detect", NULL, NULL,
980 NULL, NULL, NULL, NULL,
981 NULL, NULL, NULL, NULL,
982 NULL, NULL, NULL, NULL,
983 NULL, NULL, NULL, NULL,
984 NULL, NULL, NULL, NULL,
985 NULL, NULL, NULL, NULL,
986 },
987 .msr = {
988 .index = MSR_IA32_CORE_CAPABILITY,
597360c0
XL		 989 },
990 },
ea39f9b6
LX		 991 [FEAT_PERF_CAPABILITIES] = {
992 .type = MSR_FEATURE_WORD,
993 .feat_names = {
994 NULL, NULL, NULL, NULL,
995 NULL, NULL, NULL, NULL,
996 NULL, NULL, NULL, NULL,
997 NULL, "full-width-write", NULL, NULL,
998 NULL, NULL, NULL, NULL,
999 NULL, NULL, NULL, NULL,
1000 NULL, NULL, NULL, NULL,
1001 NULL, NULL, NULL, NULL,
1002 },
1003 .msr = {
1004 .index = MSR_IA32_PERF_CAPABILITIES,
1005 },
1006 },
20a78b02
PB		 1007
1008 [FEAT_VMX_PROCBASED_CTLS] = {
1009 .type = MSR_FEATURE_WORD,
1010 .feat_names = {
1011 NULL, NULL, "vmx-vintr-pending", "vmx-tsc-offset",
1012 NULL, NULL, NULL, "vmx-hlt-exit",
1013 NULL, "vmx-invlpg-exit", "vmx-mwait-exit", "vmx-rdpmc-exit",
1014 "vmx-rdtsc-exit", NULL, NULL, "vmx-cr3-load-noexit",
1015 "vmx-cr3-store-noexit", NULL, NULL, "vmx-cr8-load-exit",
1016 "vmx-cr8-store-exit", "vmx-flexpriority", "vmx-vnmi-pending", "vmx-movdr-exit",
1017 "vmx-io-exit", "vmx-io-bitmap", NULL, "vmx-mtf",
1018 "vmx-msr-bitmap", "vmx-monitor-exit", "vmx-pause-exit", "vmx-secondary-ctls",
1019 },
1020 .msr = {
1021 .index = MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1022 }
1023 },
1024
1025 [FEAT_VMX_SECONDARY_CTLS] = {
1026 .type = MSR_FEATURE_WORD,
1027 .feat_names = {
1028 "vmx-apicv-xapic", "vmx-ept", "vmx-desc-exit", "vmx-rdtscp-exit",
1029 "vmx-apicv-x2apic", "vmx-vpid", "vmx-wbinvd-exit", "vmx-unrestricted-guest",
1030 "vmx-apicv-register", "vmx-apicv-vid", "vmx-ple", "vmx-rdrand-exit",
1031 "vmx-invpcid-exit", "vmx-vmfunc", "vmx-shadow-vmcs", "vmx-encls-exit",
1032 "vmx-rdseed-exit", "vmx-pml", NULL, NULL,
1033 "vmx-xsaves", NULL, NULL, NULL,
9ce8af4d 1034 NULL, "vmx-tsc-scaling", NULL, NULL,
20a78b02
PB		 1035 NULL, NULL, NULL, NULL,
1036 },
1037 .msr = {
1038 .index = MSR_IA32_VMX_PROCBASED_CTLS2,
1039 }
1040 },
1041
1042 [FEAT_VMX_PINBASED_CTLS] = {
1043 .type = MSR_FEATURE_WORD,
1044 .feat_names = {
1045 "vmx-intr-exit", NULL, NULL, "vmx-nmi-exit",
1046 NULL, "vmx-vnmi", "vmx-preemption-timer", "vmx-posted-intr",
1047 NULL, NULL, NULL, NULL,
1048 NULL, NULL, NULL, NULL,
1049 NULL, NULL, NULL, NULL,
1050 NULL, NULL, NULL, NULL,
1051 NULL, NULL, NULL, NULL,
1052 NULL, NULL, NULL, NULL,
1053 },
1054 .msr = {
1055 .index = MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1056 }
1057 },
1058
1059 [FEAT_VMX_EXIT_CTLS] = {
1060 .type = MSR_FEATURE_WORD,
1061 /*
1062 * VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE is copied from
1063 * the LM CPUID bit.
1064 */
1065 .feat_names = {
1066 NULL, NULL, "vmx-exit-nosave-debugctl", NULL,
1067 NULL, NULL, NULL, NULL,
1068 NULL, NULL /* vmx-exit-host-addr-space-size */, NULL, NULL,
1069 "vmx-exit-load-perf-global-ctrl", NULL, NULL, "vmx-exit-ack-intr",
1070 NULL, NULL, "vmx-exit-save-pat", "vmx-exit-load-pat",
1071 "vmx-exit-save-efer", "vmx-exit-load-efer",
1072 "vmx-exit-save-preemption-timer", "vmx-exit-clear-bndcfgs",
1073 NULL, "vmx-exit-clear-rtit-ctl", NULL, NULL,
52a44ad2 1074 NULL, "vmx-exit-load-pkrs", NULL, NULL,
20a78b02
PB		 1075 },
1076 .msr = {
1077 .index = MSR_IA32_VMX_TRUE_EXIT_CTLS,
1078 }
1079 },
1080
1081 [FEAT_VMX_ENTRY_CTLS] = {
1082 .type = MSR_FEATURE_WORD,
1083 .feat_names = {
1084 NULL, NULL, "vmx-entry-noload-debugctl", NULL,
1085 NULL, NULL, NULL, NULL,
1086 NULL, "vmx-entry-ia32e-mode", NULL, NULL,
1087 NULL, "vmx-entry-load-perf-global-ctrl", "vmx-entry-load-pat", "vmx-entry-load-efer",
1088 "vmx-entry-load-bndcfgs", NULL, "vmx-entry-load-rtit-ctl", NULL,
52a44ad2 1089 NULL, NULL, "vmx-entry-load-pkrs", NULL,
20a78b02
PB		 1090 NULL, NULL, NULL, NULL,
1091 NULL, NULL, NULL, NULL,
1092 },
1093 .msr = {
1094 .index = MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1095 }
1096 },
1097
1098 [FEAT_VMX_MISC] = {
1099 .type = MSR_FEATURE_WORD,
1100 .feat_names = {
1101 NULL, NULL, NULL, NULL,
1102 NULL, "vmx-store-lma", "vmx-activity-hlt", "vmx-activity-shutdown",
1103 "vmx-activity-wait-sipi", NULL, NULL, NULL,
1104 NULL, NULL, NULL, NULL,
1105 NULL, NULL, NULL, NULL,
1106 NULL, NULL, NULL, NULL,
1107 NULL, NULL, NULL, NULL,
1108 NULL, "vmx-vmwrite-vmexit-fields", "vmx-zero-len-inject", NULL,
1109 },
1110 .msr = {
1111 .index = MSR_IA32_VMX_MISC,
1112 }
1113 },
1114
1115 [FEAT_VMX_EPT_VPID_CAPS] = {
1116 .type = MSR_FEATURE_WORD,
1117 .feat_names = {
1118 "vmx-ept-execonly", NULL, NULL, NULL,
1119 NULL, NULL, "vmx-page-walk-4", "vmx-page-walk-5",
1120 NULL, NULL, NULL, NULL,
1121 NULL, NULL, NULL, NULL,
1122 "vmx-ept-2mb", "vmx-ept-1gb", NULL, NULL,
1123 "vmx-invept", "vmx-eptad", "vmx-ept-advanced-exitinfo", NULL,
1124 NULL, "vmx-invept-single-context", "vmx-invept-all-context", NULL,
1125 NULL, NULL, NULL, NULL,
1126 "vmx-invvpid", NULL, NULL, NULL,
1127 NULL, NULL, NULL, NULL,
1128 "vmx-invvpid-single-addr", "vmx-invept-single-context",
1129 "vmx-invvpid-all-context", "vmx-invept-single-context-noglobals",
1130 NULL, NULL, NULL, NULL,
1131 NULL, NULL, NULL, NULL,
1132 NULL, NULL, NULL, NULL,
1133 NULL, NULL, NULL, NULL,
1134 NULL, NULL, NULL, NULL,
1135 },
1136 .msr = {
1137 .index = MSR_IA32_VMX_EPT_VPID_CAP,
1138 }
1139 },
1140
1141 [FEAT_VMX_BASIC] = {
1142 .type = MSR_FEATURE_WORD,
1143 .feat_names = {
1144 [54] = "vmx-ins-outs",
1145 [55] = "vmx-true-ctls",
1146 },
1147 .msr = {
1148 .index = MSR_IA32_VMX_BASIC,
1149 },
1150 /* Just to be safe - we don't support setting the MSEG version field. */
1151 .no_autoenable_flags = MSR_VMX_BASIC_DUAL_MONITOR,
1152 },
1153
1154 [FEAT_VMX_VMFUNC] = {
1155 .type = MSR_FEATURE_WORD,
1156 .feat_names = {
1157 [0] = "vmx-eptp-switching",
1158 },
1159 .msr = {
1160 .index = MSR_IA32_VMX_VMFUNC,
1161 }
1162 },
1163
d1615ea5
LK		 1164 [FEAT_14_0_ECX] = {
1165 .type = CPUID_FEATURE_WORD,
1166 .feat_names = {
1167 NULL, NULL, NULL, NULL,
1168 NULL, NULL, NULL, NULL,
1169 NULL, NULL, NULL, NULL,
1170 NULL, NULL, NULL, NULL,
1171 NULL, NULL, NULL, NULL,
1172 NULL, NULL, NULL, NULL,
1173 NULL, NULL, NULL, NULL,
1174 NULL, NULL, NULL, "intel-pt-lip",
1175 },
1176 .cpuid = {
1177 .eax = 0x14,
1178 .needs_ecx = true, .ecx = 0,
1179 .reg = R_ECX,
1180 },
1181 .tcg_features = TCG_14_0_ECX_FEATURES,
1182 },
1183
5ef57876
EH		 1184};
1185
99e24dbd
PB		 1186typedef struct FeatureMask {
1187 FeatureWord index;
ede146c2 1188 uint64_t mask;
99e24dbd
PB		 1189} FeatureMask;
1190
1191typedef struct FeatureDep {
1192 FeatureMask from, to;
1193} FeatureDep;
1194
1195static FeatureDep feature_dependencies[] = {
1196 {
1197 .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_ARCH_CAPABILITIES },
ede146c2 1198 .to = { FEAT_ARCH_CAPABILITIES, ~0ull },
99e24dbd
PB		 1199 },
1200 {
1201 .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_CORE_CAPABILITY },
ede146c2 1202 .to = { FEAT_CORE_CAPABILITY, ~0ull },
99e24dbd 1203 },
ea39f9b6
LX		 1204 {
1205 .from = { FEAT_1_ECX, CPUID_EXT_PDCM },
1206 .to = { FEAT_PERF_CAPABILITIES, ~0ull },
1207 },
20a78b02
PB		 1208 {
1209 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1210 .to = { FEAT_VMX_PROCBASED_CTLS, ~0ull },
1211 },
1212 {
1213 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1214 .to = { FEAT_VMX_PINBASED_CTLS, ~0ull },
1215 },
1216 {
1217 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1218 .to = { FEAT_VMX_EXIT_CTLS, ~0ull },
1219 },
1220 {
1221 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1222 .to = { FEAT_VMX_ENTRY_CTLS, ~0ull },
1223 },
1224 {
1225 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1226 .to = { FEAT_VMX_MISC, ~0ull },
1227 },
1228 {
1229 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1230 .to = { FEAT_VMX_BASIC, ~0ull },
1231 },
1232 {
1233 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_LM },
1234 .to = { FEAT_VMX_ENTRY_CTLS, VMX_VM_ENTRY_IA32E_MODE },
1235 },
1236 {
1237 .from = { FEAT_VMX_PROCBASED_CTLS, VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS },
1238 .to = { FEAT_VMX_SECONDARY_CTLS, ~0ull },
1239 },
1240 {
1241 .from = { FEAT_XSAVE, CPUID_XSAVE_XSAVES },
1242 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_XSAVES },
1243 },
1244 {
1245 .from = { FEAT_1_ECX, CPUID_EXT_RDRAND },
1246 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDRAND_EXITING },
1247 },
1248 {
1249 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_INVPCID },
1250 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_INVPCID },
1251 },
1252 {
1253 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_RDSEED },
1254 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDSEED_EXITING },
1255 },
d1615ea5
LK		 1256 {
1257 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT },
1258 .to = { FEAT_14_0_ECX, ~0ull },
1259 },
20a78b02
PB		 1260 {
1261 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_RDTSCP },
1262 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDTSCP },
1263 },
1264 {
1265 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_EPT },
1266 .to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull },
1267 },
1268 {
1269 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_EPT },
1270 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST },
1271 },
1272 {
1273 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_VPID },
1274 .to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull << 32 },
1275 },
1276 {
1277 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_VMFUNC },
1278 .to = { FEAT_VMX_VMFUNC, ~0ull },
1279 },
730319ae
EH		 1280 {
1281 .from = { FEAT_8000_0001_ECX, CPUID_EXT3_SVM },
1282 .to = { FEAT_SVM, ~0ull },
1283 },
99e24dbd
PB		 1284};
1285
8e8aba50
EH		 1286typedef struct X86RegisterInfo32 {
1287 /* Name of register */
1288 const char *name;
1289 /* QAPI enum value register */
1290 X86CPURegister32 qapi_enum;
1291} X86RegisterInfo32;
1292
1293#define REGISTER(reg) \
5d371f41 1294 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
a443bc34 1295static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
8e8aba50
EH		 1296 REGISTER(EAX),
1297 REGISTER(ECX),
1298 REGISTER(EDX),
1299 REGISTER(EBX),
1300 REGISTER(ESP),
1301 REGISTER(EBP),
1302 REGISTER(ESI),
1303 REGISTER(EDI),
1304};
1305#undef REGISTER
1306
fea45008 1307ExtSaveArea x86_ext_save_areas[XSAVE_STATE_AREA_COUNT] = {
e3c9022b
EH		 1308 [XSTATE_FP_BIT] = {
1309 /* x87 FP state component is always enabled if XSAVE is supported */
1310 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE,
e3c9022b
EH		 1311 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader),
1312 },
1313 [XSTATE_SSE_BIT] = {
1314 /* SSE state component is always enabled if XSAVE is supported */
1315 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE,
e3c9022b
EH		 1316 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader),
1317 },
cfc3b074
PB		 1318 [XSTATE_YMM_BIT] =
1319 { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
ee1b09f6 1320 .size = sizeof(XSaveAVX) },
cfc3b074
PB		 1321 [XSTATE_BNDREGS_BIT] =
1322 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
ee1b09f6 1323 .size = sizeof(XSaveBNDREG) },
cfc3b074
PB		 1324 [XSTATE_BNDCSR_BIT] =
1325 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
ee1b09f6 1326 .size = sizeof(XSaveBNDCSR) },
cfc3b074
PB		 1327 [XSTATE_OPMASK_BIT] =
1328 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6 1329 .size = sizeof(XSaveOpmask) },
cfc3b074
PB		 1330 [XSTATE_ZMM_Hi256_BIT] =
1331 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6 1332 .size = sizeof(XSaveZMM_Hi256) },
cfc3b074
PB		 1333 [XSTATE_Hi16_ZMM_BIT] =
1334 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6 1335 .size = sizeof(XSaveHi16_ZMM) },
cfc3b074
PB		 1336 [XSTATE_PKRU_BIT] =
1337 { .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU,
ee1b09f6 1338 .size = sizeof(XSavePKRU) },
2560f19f 1339};
8e8aba50 1340
1fda6198
EH		 1341static uint32_t xsave_area_size(uint64_t mask)
1342{
1343 int i;
e3c9022b 1344 uint64_t ret = 0;
1fda6198 1345
e3c9022b 1346 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
1fda6198
EH		 1347 const ExtSaveArea *esa = &x86_ext_save_areas[i];
1348 if ((mask >> i) & 1) {
1349 ret = MAX(ret, esa->offset + esa->size);
1350 }
1351 }
1352 return ret;
1353}
1354
d6dcc558
SAGDR		 1355static inline bool accel_uses_host_cpuid(void)
1356{
1357 return kvm_enabled() || hvf_enabled();
1358}
1359
96193c22
EH		 1360static inline uint64_t x86_cpu_xsave_components(X86CPU *cpu)
1361{
1362 return ((uint64_t)cpu->env.features[FEAT_XSAVE_COMP_HI]) << 32 |
1363 cpu->env.features[FEAT_XSAVE_COMP_LO];
1364}
1365
ed69e831
CF		 1366/* Return name of 32-bit register, from a R_* constant */
1367static const char *get_register_name_32(unsigned int reg)
8b4beddc 1368{
31ccdde2 1369 if (reg >= CPU_NB_REGS32) {
8b4beddc
EH		 1370 return NULL;
1371 }
8e8aba50 1372 return x86_reg_info_32[reg].name;
8b4beddc
EH		 1373}
1374
84f1b92f
EH		 1375/*
1376 * Returns the set of feature flags that are supported and migratable by
1377 * QEMU, for a given FeatureWord.
1378 */
ede146c2 1379static uint64_t x86_cpu_get_migratable_flags(FeatureWord w)
84f1b92f
EH		 1380{
1381 FeatureWordInfo *wi = &feature_word_info[w];
ede146c2 1382 uint64_t r = 0;
84f1b92f
EH		 1383 int i;
1384
ede146c2
PB		 1385 for (i = 0; i < 64; i++) {
1386 uint64_t f = 1ULL << i;
6fb2fff7
EH		 1387
1388 /* If the feature name is known, it is implicitly considered migratable,
1389 * unless it is explicitly set in unmigratable_flags */
1390 if ((wi->migratable_flags & f) ||
1391 (wi->feat_names[i] && !(wi->unmigratable_flags & f))) {
1392 r |= f;
84f1b92f 1393 }
84f1b92f
EH		 1394 }
1395 return r;
1396}
1397
bb44e0d1
JK		 1398void host_cpuid(uint32_t function, uint32_t count,
1399 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
bdde476a 1400{
a1fd24af
AL		 1401 uint32_t vec[4];
1402
1403#ifdef __x86_64__
1404 asm volatile("cpuid"
1405 : "=a"(vec[0]), "=b"(vec[1]),
1406 "=c"(vec[2]), "=d"(vec[3])
1407 : "0"(function), "c"(count) : "cc");
c1f41226 1408#elif defined(__i386__)
a1fd24af
AL		 1409 asm volatile("pusha \n\t"
1410 "cpuid \n\t"
1411 "mov %%eax, 0(%2) \n\t"
1412 "mov %%ebx, 4(%2) \n\t"
1413 "mov %%ecx, 8(%2) \n\t"
1414 "mov %%edx, 12(%2) \n\t"
1415 "popa"
1416 : : "a"(function), "c"(count), "S"(vec)
1417 : "memory", "cc");
c1f41226
EH		 1418#else
1419 abort();
a1fd24af
AL		 1420#endif
1421
bdde476a 1422 if (eax)
a1fd24af 1423 *eax = vec[0];
bdde476a 1424 if (ebx)
a1fd24af 1425 *ebx = vec[1];
bdde476a 1426 if (ecx)
a1fd24af 1427 *ecx = vec[2];
bdde476a 1428 if (edx)
a1fd24af 1429 *edx = vec[3];
bdde476a 1430}
c6dc6f63 1431
d940ee9b
EH		 1432/* CPU class name definitions: */
1433
d940ee9b
EH		 1434/* Return type name for a given CPU model name
1435 * Caller is responsible for freeing the returned string.
1436 */
1437static char *x86_cpu_type_name(const char *model_name)
1438{
1439 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name);
1440}
1441
500050d1
AF		 1442static ObjectClass *x86_cpu_class_by_name(const char *cpu_model)
1443{
88703ce2
EH		 1444 g_autofree char *typename = x86_cpu_type_name(cpu_model);
1445 return object_class_by_name(typename);
500050d1
AF		 1446}
1447
104494ea
IM		 1448static char *x86_cpu_class_get_model_name(X86CPUClass *cc)
1449{
1450 const char *class_name = object_class_get_name(OBJECT_CLASS(cc));
1451 assert(g_str_has_suffix(class_name, X86_CPU_TYPE_SUFFIX));
1452 return g_strndup(class_name,
1453 strlen(class_name) - strlen(X86_CPU_TYPE_SUFFIX));
1454}
1455
dcafd1ef
EH		 1456typedef struct X86CPUVersionDefinition {
1457 X86CPUVersion version;
53db89d9 1458 const char *alias;
c63938df 1459 const char *note;
dcafd1ef
EH		 1460 PropValue *props;
1461} X86CPUVersionDefinition;
1462
1463/* Base definition for a CPU model */
1464typedef struct X86CPUDefinition {
c6dc6f63
AP		 1465 const char *name;
1466 uint32_t level;
90e4b0c3 1467 uint32_t xlevel;
99b88a17
IM		 1468 /* vendor is zero-terminated, 12 character ASCII string */
1469 char vendor[CPUID_VENDOR_SZ + 1];
c6dc6f63
AP		 1470 int family;
1471 int model;
1472 int stepping;
0514ef2f 1473 FeatureWordArray features;
807e9869 1474 const char *model_id;
e845de38 1475 const CPUCaches *const cache_info;
dcafd1ef
EH		 1476 /*
1477 * Definitions for alternative versions of CPU model.
1478 * List is terminated by item with version == 0.
1479 * If NULL, version 1 will be registered automatically.
1480 */
1481 const X86CPUVersionDefinition *versions;
61ad65d0 1482 const char *deprecation_note;
dcafd1ef
EH		 1483} X86CPUDefinition;
1484
1485/* Reference to a specific CPU model version */
1486struct X86CPUModel {
1487 /* Base CPU definition */
e11fd689 1488 const X86CPUDefinition *cpudef;
dcafd1ef
EH		 1489 /* CPU model version */
1490 X86CPUVersion version;
c63938df 1491 const char *note;
0788a56b
EH		 1492 /*
1493 * If true, this is an alias CPU model.
1494 * This matters only for "-cpu help" and query-cpu-definitions
1495 */
1496 bool is_alias;
d940ee9b 1497};
c6dc6f63 1498
dcafd1ef 1499/* Get full model name for CPU version */
e11fd689 1500static char *x86_cpu_versioned_model_name(const X86CPUDefinition *cpudef,
dcafd1ef
EH		 1501 X86CPUVersion version)
1502{
1503 assert(version > 0);
1504 return g_strdup_printf("%s-v%d", cpudef->name, (int)version);
1505}
1506
e11fd689
PMD		 1507static const X86CPUVersionDefinition *
1508x86_cpu_def_get_versions(const X86CPUDefinition *def)
dcafd1ef
EH		 1509{
1510 /* When X86CPUDefinition::versions is NULL, we register only v1 */
1511 static const X86CPUVersionDefinition default_version_list[] = {
1512 { 1 },
1513 { /* end of list */ }
1514 };
1515
1516 return def->versions ?: default_version_list;
1517}
1518
e845de38 1519static const CPUCaches epyc_cache_info = {
a9f27ea9 1520 .l1d_cache = &(CPUCacheInfo) {
5f00335a 1521 .type = DATA_CACHE,
fe52acd2
BM		 1522 .level = 1,
1523 .size = 32 * KiB,
1524 .line_size = 64,
1525 .associativity = 8,
1526 .partitions = 1,
1527 .sets = 64,
1528 .lines_per_tag = 1,
1529 .self_init = 1,
1530 .no_invd_sharing = true,
1531 },
a9f27ea9 1532 .l1i_cache = &(CPUCacheInfo) {
5f00335a 1533 .type = INSTRUCTION_CACHE,
fe52acd2
BM		 1534 .level = 1,
1535 .size = 64 * KiB,
1536 .line_size = 64,
1537 .associativity = 4,
1538 .partitions = 1,
1539 .sets = 256,
1540 .lines_per_tag = 1,
1541 .self_init = 1,
1542 .no_invd_sharing = true,
1543 },
a9f27ea9 1544 .l2_cache = &(CPUCacheInfo) {
fe52acd2
BM		 1545 .type = UNIFIED_CACHE,
1546 .level = 2,
1547 .size = 512 * KiB,
1548 .line_size = 64,
1549 .associativity = 8,
1550 .partitions = 1,
1551 .sets = 1024,
1552 .lines_per_tag = 1,
1553 },
a9f27ea9 1554 .l3_cache = &(CPUCacheInfo) {
fe52acd2
BM		 1555 .type = UNIFIED_CACHE,
1556 .level = 3,
1557 .size = 8 * MiB,
1558 .line_size = 64,
1559 .associativity = 16,
1560 .partitions = 1,
1561 .sets = 8192,
1562 .lines_per_tag = 1,
1563 .self_init = true,
1564 .inclusive = true,
1565 .complex_indexing = true,
1566 },
1567};
1568
e845de38 1569static const CPUCaches epyc_rome_cache_info = {
143c30d4
MB		 1570 .l1d_cache = &(CPUCacheInfo) {
1571 .type = DATA_CACHE,
1572 .level = 1,
1573 .size = 32 * KiB,
1574 .line_size = 64,
1575 .associativity = 8,
1576 .partitions = 1,
1577 .sets = 64,
1578 .lines_per_tag = 1,
1579 .self_init = 1,
1580 .no_invd_sharing = true,
1581 },
1582 .l1i_cache = &(CPUCacheInfo) {
1583 .type = INSTRUCTION_CACHE,
1584 .level = 1,
1585 .size = 32 * KiB,
1586 .line_size = 64,
1587 .associativity = 8,
1588 .partitions = 1,
1589 .sets = 64,
1590 .lines_per_tag = 1,
1591 .self_init = 1,
1592 .no_invd_sharing = true,
1593 },
1594 .l2_cache = &(CPUCacheInfo) {
1595 .type = UNIFIED_CACHE,
1596 .level = 2,
1597 .size = 512 * KiB,
1598 .line_size = 64,
1599 .associativity = 8,
1600 .partitions = 1,
1601 .sets = 1024,
1602 .lines_per_tag = 1,
1603 },
1604 .l3_cache = &(CPUCacheInfo) {
1605 .type = UNIFIED_CACHE,
1606 .level = 3,
1607 .size = 16 * MiB,
1608 .line_size = 64,
1609 .associativity = 16,
1610 .partitions = 1,
1611 .sets = 16384,
1612 .lines_per_tag = 1,
1613 .self_init = true,
1614 .inclusive = true,
1615 .complex_indexing = true,
1616 },
1617};
1618
e845de38 1619static const CPUCaches epyc_milan_cache_info = {
623972ce
BM		 1620 .l1d_cache = &(CPUCacheInfo) {
1621 .type = DATA_CACHE,
1622 .level = 1,
1623 .size = 32 * KiB,
1624 .line_size = 64,
1625 .associativity = 8,
1626 .partitions = 1,
1627 .sets = 64,
1628 .lines_per_tag = 1,
1629 .self_init = 1,
1630 .no_invd_sharing = true,
1631 },
1632 .l1i_cache = &(CPUCacheInfo) {
1633 .type = INSTRUCTION_CACHE,
1634 .level = 1,
1635 .size = 32 * KiB,
1636 .line_size = 64,
1637 .associativity = 8,
1638 .partitions = 1,
1639 .sets = 64,
1640 .lines_per_tag = 1,
1641 .self_init = 1,
1642 .no_invd_sharing = true,
1643 },
1644 .l2_cache = &(CPUCacheInfo) {
1645 .type = UNIFIED_CACHE,
1646 .level = 2,
1647 .size = 512 * KiB,
1648 .line_size = 64,
1649 .associativity = 8,
1650 .partitions = 1,
1651 .sets = 1024,
1652 .lines_per_tag = 1,
1653 },
1654 .l3_cache = &(CPUCacheInfo) {
1655 .type = UNIFIED_CACHE,
1656 .level = 3,
1657 .size = 32 * MiB,
1658 .line_size = 64,
1659 .associativity = 16,
1660 .partitions = 1,
1661 .sets = 32768,
1662 .lines_per_tag = 1,
1663 .self_init = true,
1664 .inclusive = true,
1665 .complex_indexing = true,
1666 },
1667};
1668
0723cc8a
PB		 1669/* The following VMX features are not supported by KVM and are left out in the
1670 * CPU definitions:
1671 *
1672 * Dual-monitor support (all processors)
1673 * Entry to SMM
1674 * Deactivate dual-monitor treatment
1675 * Number of CR3-target values
1676 * Shutdown activity state
1677 * Wait-for-SIPI activity state
1678 * PAUSE-loop exiting (Westmere and newer)
1679 * EPT-violation #VE (Broadwell and newer)
1680 * Inject event with insn length=0 (Skylake and newer)
1681 * Conceal non-root operation from PT
1682 * Conceal VM exits from PT
1683 * Conceal VM entries from PT
1684 * Enable ENCLS exiting
1685 * Mode-based execute control (XS/XU)
1686 s TSC scaling (Skylake Server and newer)
1687 * GPA translation for PT (IceLake and newer)
1688 * User wait and pause
1689 * ENCLV exiting
1690 * Load IA32_RTIT_CTL
1691 * Clear IA32_RTIT_CTL
1692 * Advanced VM-exit information for EPT violations
1693 * Sub-page write permissions
1694 * PT in VMX operation
1695 */
1696
e11fd689 1697static const X86CPUDefinition builtin_x86_defs[] = {
c6dc6f63
AP		 1698 {
1699 .name = "qemu64",
3046bb5d 1700 .level = 0xd,
99b88a17 1701 .vendor = CPUID_VENDOR_AMD,
b7c29017
DB		 1702 .family = 15,
1703 .model = 107,
1704 .stepping = 1,
0514ef2f 1705 .features[FEAT_1_EDX] =
27861ecc 1706 PPRO_FEATURES |
c6dc6f63 1707 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
c6dc6f63 1708 CPUID_PSE36,
0514ef2f 1709 .features[FEAT_1_ECX] =
6aa91e4a 1710 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
0514ef2f 1711 .features[FEAT_8000_0001_EDX] =
c6dc6f63 1712 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 1713 .features[FEAT_8000_0001_ECX] =
71195672 1714 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM,
c6dc6f63 1715 .xlevel = 0x8000000A,
9cf2cc3d 1716 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63
AP		 1717 },
1718 {
1719 .name = "phenom",
1720 .level = 5,
99b88a17 1721 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 1722 .family = 16,
1723 .model = 2,
1724 .stepping = 3,
b9fc20bc 1725 /* Missing: CPUID_HT */
0514ef2f 1726 .features[FEAT_1_EDX] =
27861ecc 1727 PPRO_FEATURES |
c6dc6f63 1728 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
b9fc20bc 1729 CPUID_PSE36 | CPUID_VME,
0514ef2f 1730 .features[FEAT_1_ECX] =
27861ecc 1731 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
c6dc6f63 1732 CPUID_EXT_POPCNT,
0514ef2f 1733 .features[FEAT_8000_0001_EDX] =
c6dc6f63
AP		 1734 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
1735 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
8560efed 1736 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
c6dc6f63
AP		 1737 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
1738 CPUID_EXT3_CR8LEG,
1739 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
1740 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
0514ef2f 1741 .features[FEAT_8000_0001_ECX] =
27861ecc 1742 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
c6dc6f63 1743 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
b9fc20bc 1744 /* Missing: CPUID_SVM_LBRV */
0514ef2f 1745 .features[FEAT_SVM] =
b9fc20bc 1746 CPUID_SVM_NPT,
c6dc6f63
AP		 1747 .xlevel = 0x8000001A,
1748 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
1749 },
1750 {
1751 .name = "core2duo",
1752 .level = 10,
99b88a17 1753 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 1754 .family = 6,
1755 .model = 15,
1756 .stepping = 11,
b9fc20bc 1757 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 1758 .features[FEAT_1_EDX] =
27861ecc 1759 PPRO_FEATURES |
c6dc6f63 1760 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
b9fc20bc
EH		 1761 CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS,
1762 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST,
e93abc14 1763 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */
0514ef2f 1764 .features[FEAT_1_ECX] =
27861ecc 1765 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
e93abc14 1766 CPUID_EXT_CX16,
0514ef2f 1767 .features[FEAT_8000_0001_EDX] =
27861ecc 1768 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 1769 .features[FEAT_8000_0001_ECX] =
27861ecc 1770 CPUID_EXT3_LAHF_LM,
0723cc8a
PB		 1771 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS,
1772 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
1773 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
1774 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
1775 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
1776 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS,
1777 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
1778 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
1779 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
1780 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
1781 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
1782 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
1783 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
1784 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
1785 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
1786 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
1787 .features[FEAT_VMX_SECONDARY_CTLS] =
1788 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES,
c6dc6f63
AP		 1789 .xlevel = 0x80000008,
1790 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
1791 },
1792 {
1793 .name = "kvm64",
3046bb5d 1794 .level = 0xd,
99b88a17 1795 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 1796 .family = 15,
1797 .model = 6,
1798 .stepping = 1,
b3a4f0b1 1799 /* Missing: CPUID_HT */
0514ef2f 1800 .features[FEAT_1_EDX] =
b3a4f0b1 1801 PPRO_FEATURES | CPUID_VME |
c6dc6f63
AP		 1802 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
1803 CPUID_PSE36,
1804 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
0514ef2f 1805 .features[FEAT_1_ECX] =
27861ecc 1806 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
c6dc6f63 1807 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
0514ef2f 1808 .features[FEAT_8000_0001_EDX] =
c6dc6f63
AP		 1809 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1810 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
1811 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
1812 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
1813 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
0514ef2f 1814 .features[FEAT_8000_0001_ECX] =
27861ecc 1815 0,
0723cc8a
PB		 1816 /* VMX features from Cedar Mill/Prescott */
1817 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
1818 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
1819 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
1820 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
1821 VMX_PIN_BASED_NMI_EXITING,
1822 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
1823 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
1824 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
1825 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
1826 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
1827 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
1828 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
1829 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING,
c6dc6f63
AP		 1830 .xlevel = 0x80000008,
1831 .model_id = "Common KVM processor"
1832 },
c6dc6f63
AP		 1833 {
1834 .name = "qemu32",
1835 .level = 4,
99b88a17 1836 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 1837 .family = 6,
f8e6a11a 1838 .model = 6,
c6dc6f63 1839 .stepping = 3,
0514ef2f 1840 .features[FEAT_1_EDX] =
27861ecc 1841 PPRO_FEATURES,
0514ef2f 1842 .features[FEAT_1_ECX] =
6aa91e4a 1843 CPUID_EXT_SSE3,
58012d66 1844 .xlevel = 0x80000004,
9cf2cc3d 1845 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63 1846 },
eafaf1e5
AP		 1847 {
1848 .name = "kvm32",
1849 .level = 5,
99b88a17 1850 .vendor = CPUID_VENDOR_INTEL,
eafaf1e5
AP		 1851 .family = 15,
1852 .model = 6,
1853 .stepping = 1,
0514ef2f 1854 .features[FEAT_1_EDX] =
b3a4f0b1 1855 PPRO_FEATURES | CPUID_VME |
eafaf1e5 1856 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
0514ef2f 1857 .features[FEAT_1_ECX] =
27861ecc 1858 CPUID_EXT_SSE3,
0514ef2f 1859 .features[FEAT_8000_0001_ECX] =
27861ecc 1860 0,
0723cc8a
PB		 1861 /* VMX features from Yonah */
1862 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
1863 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
1864 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
1865 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
1866 VMX_PIN_BASED_NMI_EXITING,
1867 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
1868 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
1869 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
1870 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
1871 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING |
1872 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING |
1873 VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS,
eafaf1e5
AP		 1874 .xlevel = 0x80000008,
1875 .model_id = "Common 32-bit KVM processor"
1876 },
c6dc6f63
AP		 1877 {
1878 .name = "coreduo",
1879 .level = 10,
99b88a17 1880 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 1881 .family = 6,
1882 .model = 14,
1883 .stepping = 8,
b9fc20bc 1884 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 1885 .features[FEAT_1_EDX] =
27861ecc 1886 PPRO_FEATURES | CPUID_VME |
b9fc20bc
EH		 1887 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI |
1888 CPUID_SS,
1889 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR,
e93abc14 1890 * CPUID_EXT_PDCM, CPUID_EXT_VMX */
0514ef2f 1891 .features[FEAT_1_ECX] =
e93abc14 1892 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR,
0514ef2f 1893 .features[FEAT_8000_0001_EDX] =
27861ecc 1894 CPUID_EXT2_NX,
0723cc8a
PB		 1895 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
1896 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
1897 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
1898 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
1899 VMX_PIN_BASED_NMI_EXITING,
1900 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
1901 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
1902 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
1903 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
1904 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING |
1905 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING |
1906 VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS,
c6dc6f63
AP		 1907 .xlevel = 0x80000008,
1908 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
1909 },
1910 {
1911 .name = "486",
58012d66 1912 .level = 1,
99b88a17 1913 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 1914 .family = 4,
b2a856d9 1915 .model = 8,
c6dc6f63 1916 .stepping = 0,
0514ef2f 1917 .features[FEAT_1_EDX] =
27861ecc 1918 I486_FEATURES,
c6dc6f63 1919 .xlevel = 0,
807e9869 1920 .model_id = "",
c6dc6f63
AP		 1921 },
1922 {
1923 .name = "pentium",
1924 .level = 1,
99b88a17 1925 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 1926 .family = 5,
1927 .model = 4,
1928 .stepping = 3,
0514ef2f 1929 .features[FEAT_1_EDX] =
27861ecc 1930 PENTIUM_FEATURES,
c6dc6f63 1931 .xlevel = 0,
807e9869 1932 .model_id = "",
c6dc6f63
AP		 1933 },
1934 {
1935 .name = "pentium2",
1936 .level = 2,
99b88a17 1937 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 1938 .family = 6,
1939 .model = 5,
1940 .stepping = 2,
0514ef2f 1941 .features[FEAT_1_EDX] =
27861ecc 1942 PENTIUM2_FEATURES,
c6dc6f63 1943 .xlevel = 0,
807e9869 1944 .model_id = "",
c6dc6f63
AP		 1945 },
1946 {
1947 .name = "pentium3",
3046bb5d 1948 .level = 3,
99b88a17 1949 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 1950 .family = 6,
1951 .model = 7,
1952 .stepping = 3,
0514ef2f 1953 .features[FEAT_1_EDX] =
27861ecc 1954 PENTIUM3_FEATURES,
c6dc6f63 1955 .xlevel = 0,
807e9869 1956 .model_id = "",
c6dc6f63
AP		 1957 },
1958 {
1959 .name = "athlon",
1960 .level = 2,
99b88a17 1961 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 1962 .family = 6,
1963 .model = 2,
1964 .stepping = 3,
0514ef2f 1965 .features[FEAT_1_EDX] =
27861ecc 1966 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
60032ac0 1967 CPUID_MCA,
0514ef2f 1968 .features[FEAT_8000_0001_EDX] =
60032ac0 1969 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
c6dc6f63 1970 .xlevel = 0x80000008,
9cf2cc3d 1971 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63
AP		 1972 },
1973 {
1974 .name = "n270",
3046bb5d 1975 .level = 10,
99b88a17 1976 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 1977 .family = 6,
1978 .model = 28,
1979 .stepping = 2,
b9fc20bc 1980 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 1981 .features[FEAT_1_EDX] =
27861ecc 1982 PPRO_FEATURES |
b9fc20bc
EH		 1983 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME |
1984 CPUID_ACPI | CPUID_SS,
c6dc6f63 1985 /* Some CPUs got no CPUID_SEP */
b9fc20bc
EH		 1986 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2,
1987 * CPUID_EXT_XTPR */
0514ef2f 1988 .features[FEAT_1_ECX] =
27861ecc 1989 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
4458c236 1990 CPUID_EXT_MOVBE,
0514ef2f 1991 .features[FEAT_8000_0001_EDX] =
60032ac0 1992 CPUID_EXT2_NX,
0514ef2f 1993 .features[FEAT_8000_0001_ECX] =
27861ecc 1994 CPUID_EXT3_LAHF_LM,
3046bb5d 1995 .xlevel = 0x80000008,
c6dc6f63
AP		 1996 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
1997 },
3eca4642
EH		 1998 {
1999 .name = "Conroe",
3046bb5d 2000 .level = 10,
99b88a17 2001 .vendor = CPUID_VENDOR_INTEL,
3eca4642 2002 .family = 6,
ffce9ebb 2003 .model = 15,
3eca4642 2004 .stepping = 3,
0514ef2f 2005 .features[FEAT_1_EDX] =
b3a4f0b1 2006 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2007 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2008 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2009 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2010 CPUID_DE | CPUID_FP87,
0514ef2f 2011 .features[FEAT_1_ECX] =
27861ecc 2012 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 2013 .features[FEAT_8000_0001_EDX] =
27861ecc 2014 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 2015 .features[FEAT_8000_0001_ECX] =
27861ecc 2016 CPUID_EXT3_LAHF_LM,
0723cc8a
PB		 2017 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS,
2018 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
2019 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
2020 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
2021 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2022 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS,
2023 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2024 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2025 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2026 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2027 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2028 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2029 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2030 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2031 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2032 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2033 .features[FEAT_VMX_SECONDARY_CTLS] =
2034 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES,
3046bb5d 2035 .xlevel = 0x80000008,
3eca4642
EH		 2036 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
2037 },
2038 {
2039 .name = "Penryn",
3046bb5d 2040 .level = 10,
99b88a17 2041 .vendor = CPUID_VENDOR_INTEL,
3eca4642 2042 .family = 6,
ffce9ebb 2043 .model = 23,
3eca4642 2044 .stepping = 3,
0514ef2f 2045 .features[FEAT_1_EDX] =
b3a4f0b1 2046 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2047 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2048 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2049 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2050 CPUID_DE | CPUID_FP87,
0514ef2f 2051 .features[FEAT_1_ECX] =
27861ecc 2052 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
b3fb3a20 2053 CPUID_EXT_SSE3,
0514ef2f 2054 .features[FEAT_8000_0001_EDX] =
27861ecc 2055 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 2056 .features[FEAT_8000_0001_ECX] =
27861ecc 2057 CPUID_EXT3_LAHF_LM,
0723cc8a
PB		 2058 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS,
2059 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2060 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
2061 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT |
2062 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
2063 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
2064 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2065 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS,
2066 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2067 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2068 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2069 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2070 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2071 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2072 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2073 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2074 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2075 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2076 .features[FEAT_VMX_SECONDARY_CTLS] =
2077 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2078 VMX_SECONDARY_EXEC_WBINVD_EXITING,
3046bb5d 2079 .xlevel = 0x80000008,
3eca4642
EH		 2080 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
2081 },
2082 {
2083 .name = "Nehalem",
3046bb5d 2084 .level = 11,
99b88a17 2085 .vendor = CPUID_VENDOR_INTEL,
3eca4642 2086 .family = 6,
ffce9ebb 2087 .model = 26,
3eca4642 2088 .stepping = 3,
0514ef2f 2089 .features[FEAT_1_EDX] =
b3a4f0b1 2090 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2091 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2092 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2093 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2094 CPUID_DE | CPUID_FP87,
0514ef2f 2095 .features[FEAT_1_ECX] =
27861ecc 2096 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
b3fb3a20 2097 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 2098 .features[FEAT_8000_0001_EDX] =
27861ecc 2099 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 2100 .features[FEAT_8000_0001_ECX] =
27861ecc 2101 CPUID_EXT3_LAHF_LM,
0723cc8a
PB		 2102 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2103 MSR_VMX_BASIC_TRUE_CTLS,
2104 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2105 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2106 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2107 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2108 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2109 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2110 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2111 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2112 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2113 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
2114 .features[FEAT_VMX_EXIT_CTLS] =
2115 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2116 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2117 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2118 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2119 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2120 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
2121 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2122 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2123 VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
2124 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2125 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2126 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2127 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2128 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2129 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2130 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2131 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2132 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2133 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2134 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2135 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2136 .features[FEAT_VMX_SECONDARY_CTLS] =
2137 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2138 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2139 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2140 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2141 VMX_SECONDARY_EXEC_ENABLE_VPID,
3046bb5d 2142 .xlevel = 0x80000008,
3eca4642 2143 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
d86a7088
EH		 2144 .versions = (X86CPUVersionDefinition[]) {
2145 { .version = 1 },
2146 {
2147 .version = 2,
53db89d9 2148 .alias = "Nehalem-IBRS",
d86a7088
EH		 2149 .props = (PropValue[]) {
2150 { "spec-ctrl", "on" },
2151 { "model-id",
2152 "Intel Core i7 9xx (Nehalem Core i7, IBRS update)" },
2153 { /* end of list */ }
2154 }
2155 },
2156 { /* end of list */ }
2157 }
3eca4642
EH		 2158 },
2159 {
2160 .name = "Westmere",
2161 .level = 11,
99b88a17 2162 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 2163 .family = 6,
2164 .model = 44,
2165 .stepping = 1,
0514ef2f 2166 .features[FEAT_1_EDX] =
b3a4f0b1 2167 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2168 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2169 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2170 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2171 CPUID_DE | CPUID_FP87,
0514ef2f 2172 .features[FEAT_1_ECX] =
27861ecc 2173 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
b3fb3a20
EH		 2174 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2175 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
0514ef2f 2176 .features[FEAT_8000_0001_EDX] =
27861ecc 2177 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 2178 .features[FEAT_8000_0001_ECX] =
27861ecc 2179 CPUID_EXT3_LAHF_LM,
28b8e4d0
JK		 2180 .features[FEAT_6_EAX] =
2181 CPUID_6_EAX_ARAT,
0723cc8a
PB		 2182 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2183 MSR_VMX_BASIC_TRUE_CTLS,
2184 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2185 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2186 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2187 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2188 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2189 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2190 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2191 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2192 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2193 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
2194 .features[FEAT_VMX_EXIT_CTLS] =
2195 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2196 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2197 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2198 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2199 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2200 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2201 MSR_VMX_MISC_STORE_LMA,
2202 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2203 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2204 VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
2205 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2206 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2207 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2208 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2209 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2210 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2211 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2212 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2213 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2214 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2215 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2216 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2217 .features[FEAT_VMX_SECONDARY_CTLS] =
2218 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2219 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2220 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2221 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2222 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST,
3046bb5d 2223 .xlevel = 0x80000008,
3eca4642 2224 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
d86a7088
EH		 2225 .versions = (X86CPUVersionDefinition[]) {
2226 { .version = 1 },
2227 {
2228 .version = 2,
53db89d9 2229 .alias = "Westmere-IBRS",
d86a7088
EH		 2230 .props = (PropValue[]) {
2231 { "spec-ctrl", "on" },
2232 { "model-id",
2233 "Westmere E56xx/L56xx/X56xx (IBRS update)" },
2234 { /* end of list */ }
2235 }
2236 },
2237 { /* end of list */ }
2238 }
3eca4642
EH		 2239 },
2240 {
2241 .name = "SandyBridge",
2242 .level = 0xd,
99b88a17 2243 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 2244 .family = 6,
2245 .model = 42,
2246 .stepping = 1,
0514ef2f 2247 .features[FEAT_1_EDX] =
b3a4f0b1 2248 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2249 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2250 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2251 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2252 CPUID_DE | CPUID_FP87,
0514ef2f 2253 .features[FEAT_1_ECX] =
27861ecc 2254 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 2255 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
2256 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
2257 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
2258 CPUID_EXT_SSE3,
0514ef2f 2259 .features[FEAT_8000_0001_EDX] =
27861ecc 2260 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
b3fb3a20 2261 CPUID_EXT2_SYSCALL,
0514ef2f 2262 .features[FEAT_8000_0001_ECX] =
27861ecc 2263 CPUID_EXT3_LAHF_LM,
0bb0b2d2
PB		 2264 .features[FEAT_XSAVE] =
2265 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 2266 .features[FEAT_6_EAX] =
2267 CPUID_6_EAX_ARAT,
0723cc8a
PB		 2268 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2269 MSR_VMX_BASIC_TRUE_CTLS,
2270 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2271 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2272 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2273 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2274 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2275 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2276 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2277 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2278 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2279 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
2280 .features[FEAT_VMX_EXIT_CTLS] =
2281 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2282 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2283 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2284 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2285 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2286 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2287 MSR_VMX_MISC_STORE_LMA,
2288 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2289 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2290 VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
2291 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2292 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2293 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2294 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2295 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2296 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2297 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2298 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2299 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2300 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2301 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2302 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2303 .features[FEAT_VMX_SECONDARY_CTLS] =
2304 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2305 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2306 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2307 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2308 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST,
3046bb5d 2309 .xlevel = 0x80000008,
3eca4642 2310 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
d86a7088
EH		 2311 .versions = (X86CPUVersionDefinition[]) {
2312 { .version = 1 },
2313 {
2314 .version = 2,
53db89d9 2315 .alias = "SandyBridge-IBRS",
d86a7088
EH		 2316 .props = (PropValue[]) {
2317 { "spec-ctrl", "on" },
2318 { "model-id",
2319 "Intel Xeon E312xx (Sandy Bridge, IBRS update)" },
2320 { /* end of list */ }
2321 }
2322 },
2323 { /* end of list */ }
2324 }
3eca4642 2325 },
2f9ac42a
PB		 2326 {
2327 .name = "IvyBridge",
2328 .level = 0xd,
2329 .vendor = CPUID_VENDOR_INTEL,
2330 .family = 6,
2331 .model = 58,
2332 .stepping = 9,
2333 .features[FEAT_1_EDX] =
2334 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2335 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2336 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2337 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2338 CPUID_DE | CPUID_FP87,
2339 .features[FEAT_1_ECX] =
2340 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2341 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
2342 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
2343 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
2344 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2345 .features[FEAT_7_0_EBX] =
2346 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP |
2347 CPUID_7_0_EBX_ERMS,
2348 .features[FEAT_8000_0001_EDX] =
2349 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2350 CPUID_EXT2_SYSCALL,
2351 .features[FEAT_8000_0001_ECX] =
2352 CPUID_EXT3_LAHF_LM,
2353 .features[FEAT_XSAVE] =
2354 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 2355 .features[FEAT_6_EAX] =
2356 CPUID_6_EAX_ARAT,
0723cc8a
PB		 2357 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2358 MSR_VMX_BASIC_TRUE_CTLS,
2359 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2360 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2361 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2362 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2363 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2364 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2365 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2366 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2367 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2368 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
2369 .features[FEAT_VMX_EXIT_CTLS] =
2370 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2371 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2372 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2373 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2374 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2375 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2376 MSR_VMX_MISC_STORE_LMA,
2377 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2378 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2379 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
2380 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2381 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2382 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2383 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2384 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2385 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2386 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2387 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2388 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2389 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2390 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2391 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2392 .features[FEAT_VMX_SECONDARY_CTLS] =
2393 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2394 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2395 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2396 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2397 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
2398 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
2399 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2400 VMX_SECONDARY_EXEC_RDRAND_EXITING,
3046bb5d 2401 .xlevel = 0x80000008,
2f9ac42a 2402 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)",
d86a7088
EH		 2403 .versions = (X86CPUVersionDefinition[]) {
2404 { .version = 1 },
2405 {
2406 .version = 2,
53db89d9 2407 .alias = "IvyBridge-IBRS",
d86a7088
EH		 2408 .props = (PropValue[]) {
2409 { "spec-ctrl", "on" },
2410 { "model-id",
2411 "Intel Xeon E3-12xx v2 (Ivy Bridge, IBRS)" },
2412 { /* end of list */ }
2413 }
2414 },
2415 { /* end of list */ }
2416 }
2f9ac42a 2417 },
ac96c413 2418 {
37507094
EH		 2419 .name = "Haswell",
2420 .level = 0xd,
99b88a17 2421 .vendor = CPUID_VENDOR_INTEL,
37507094
EH		 2422 .family = 6,
2423 .model = 60,
ec56a4a7 2424 .stepping = 4,
0514ef2f 2425 .features[FEAT_1_EDX] =
b3a4f0b1 2426 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2427 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2428 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2429 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2430 CPUID_DE | CPUID_FP87,
0514ef2f 2431 .features[FEAT_1_ECX] =
27861ecc 2432 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 2433 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2434 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2435 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2436 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
78a611f1 2437 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
0514ef2f 2438 .features[FEAT_8000_0001_EDX] =
27861ecc 2439 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
b3fb3a20 2440 CPUID_EXT2_SYSCALL,
0514ef2f 2441 .features[FEAT_8000_0001_ECX] =
becb6667 2442 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
0514ef2f 2443 .features[FEAT_7_0_EBX] =
27861ecc 2444 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1ee91598
EH		 2445 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2446 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2447 CPUID_7_0_EBX_RTM,
0bb0b2d2
PB		 2448 .features[FEAT_XSAVE] =
2449 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 2450 .features[FEAT_6_EAX] =
2451 CPUID_6_EAX_ARAT,
0723cc8a
PB		 2452 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2453 MSR_VMX_BASIC_TRUE_CTLS,
2454 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2455 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2456 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2457 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2458 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2459 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2460 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2461 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2462 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2463 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
2464 .features[FEAT_VMX_EXIT_CTLS] =
2465 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2466 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2467 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2468 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2469 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2470 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2471 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
2472 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2473 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2474 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
2475 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2476 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2477 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2478 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2479 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2480 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2481 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2482 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2483 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2484 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2485 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2486 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2487 .features[FEAT_VMX_SECONDARY_CTLS] =
2488 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2489 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2490 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2491 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2492 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
2493 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
2494 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2495 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
2496 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS,
2497 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
3046bb5d 2498 .xlevel = 0x80000008,
37507094 2499 .model_id = "Intel Core Processor (Haswell)",
d86a7088
EH		 2500 .versions = (X86CPUVersionDefinition[]) {
2501 { .version = 1 },
2502 {
2503 .version = 2,
53db89d9 2504 .alias = "Haswell-noTSX",
d86a7088
EH		 2505 .props = (PropValue[]) {
2506 { "hle", "off" },
2507 { "rtm", "off" },
2508 { "stepping", "1" },
2509 { "model-id", "Intel Core Processor (Haswell, no TSX)", },
2510 { /* end of list */ }
2511 },
2512 },
2513 {
2514 .version = 3,
53db89d9 2515 .alias = "Haswell-IBRS",
d86a7088
EH		 2516 .props = (PropValue[]) {
2517 /* Restore TSX features removed by -v2 above */
2518 { "hle", "on" },
2519 { "rtm", "on" },
2520 /*
2521 * Haswell and Haswell-IBRS had stepping=4 in
2522 * QEMU 4.0 and older
2523 */
2524 { "stepping", "4" },
2525 { "spec-ctrl", "on" },
2526 { "model-id",
2527 "Intel Core Processor (Haswell, IBRS)" },
2528 { /* end of list */ }
2529 }
2530 },
2531 {
2532 .version = 4,
53db89d9 2533 .alias = "Haswell-noTSX-IBRS",
d86a7088
EH		 2534 .props = (PropValue[]) {
2535 { "hle", "off" },
2536 { "rtm", "off" },
2537 /* spec-ctrl was already enabled by -v3 above */
2538 { "stepping", "1" },
2539 { "model-id",
2540 "Intel Core Processor (Haswell, no TSX, IBRS)" },
2541 { /* end of list */ }
2542 }
2543 },
2544 { /* end of list */ }
2545 }
37507094 2546 },
ece01354
EH		 2547 {
2548 .name = "Broadwell",
2549 .level = 0xd,
2550 .vendor = CPUID_VENDOR_INTEL,
2551 .family = 6,
2552 .model = 61,
2553 .stepping = 2,
2554 .features[FEAT_1_EDX] =
b3a4f0b1 2555 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
ece01354
EH		 2556 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2557 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2558 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2559 CPUID_DE | CPUID_FP87,
2560 .features[FEAT_1_ECX] =
2561 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2562 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2563 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2564 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2565 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
78a611f1 2566 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
ece01354
EH		 2567 .features[FEAT_8000_0001_EDX] =
2568 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2569 CPUID_EXT2_SYSCALL,
2570 .features[FEAT_8000_0001_ECX] =
becb6667 2571 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
ece01354
EH		 2572 .features[FEAT_7_0_EBX] =
2573 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1ee91598 2574 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
ece01354 2575 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1ee91598 2576 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
ece01354 2577 CPUID_7_0_EBX_SMAP,
0bb0b2d2
PB		 2578 .features[FEAT_XSAVE] =
2579 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 2580 .features[FEAT_6_EAX] =
2581 CPUID_6_EAX_ARAT,
0723cc8a
PB		 2582 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2583 MSR_VMX_BASIC_TRUE_CTLS,
2584 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2585 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2586 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2587 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2588 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2589 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2590 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2591 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2592 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2593 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
2594 .features[FEAT_VMX_EXIT_CTLS] =
2595 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2596 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2597 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2598 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2599 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2600 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2601 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
2602 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2603 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2604 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
2605 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2606 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2607 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2608 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2609 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2610 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2611 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2612 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2613 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2614 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2615 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2616 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2617 .features[FEAT_VMX_SECONDARY_CTLS] =
2618 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2619 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2620 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2621 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2622 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
2623 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
2624 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2625 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
2626 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
2627 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
2628 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
3046bb5d 2629 .xlevel = 0x80000008,
ece01354 2630 .model_id = "Intel Core Processor (Broadwell)",
d86a7088
EH		 2631 .versions = (X86CPUVersionDefinition[]) {
2632 { .version = 1 },
2633 {
2634 .version = 2,
53db89d9 2635 .alias = "Broadwell-noTSX",
d86a7088
EH		 2636 .props = (PropValue[]) {
2637 { "hle", "off" },
2638 { "rtm", "off" },
2639 { "model-id", "Intel Core Processor (Broadwell, no TSX)", },
2640 { /* end of list */ }
2641 },
2642 },
2643 {
2644 .version = 3,
53db89d9 2645 .alias = "Broadwell-IBRS",
d86a7088
EH		 2646 .props = (PropValue[]) {
2647 /* Restore TSX features removed by -v2 above */
2648 { "hle", "on" },
2649 { "rtm", "on" },
2650 { "spec-ctrl", "on" },
2651 { "model-id",
2652 "Intel Core Processor (Broadwell, IBRS)" },
2653 { /* end of list */ }
2654 }
2655 },
2656 {
2657 .version = 4,
53db89d9 2658 .alias = "Broadwell-noTSX-IBRS",
d86a7088
EH		 2659 .props = (PropValue[]) {
2660 { "hle", "off" },
2661 { "rtm", "off" },
2662 /* spec-ctrl was already enabled by -v3 above */
2663 { "model-id",
2664 "Intel Core Processor (Broadwell, no TSX, IBRS)" },
2665 { /* end of list */ }
2666 }
2667 },
2668 { /* end of list */ }
2669 }
ece01354 2670 },
f6f949e9
EH		 2671 {
2672 .name = "Skylake-Client",
2673 .level = 0xd,
2674 .vendor = CPUID_VENDOR_INTEL,
2675 .family = 6,
2676 .model = 94,
2677 .stepping = 3,
2678 .features[FEAT_1_EDX] =
2679 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2680 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2681 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2682 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2683 CPUID_DE | CPUID_FP87,
2684 .features[FEAT_1_ECX] =
2685 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2686 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2687 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2688 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2689 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2690 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2691 .features[FEAT_8000_0001_EDX] =
2692 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2693 CPUID_EXT2_SYSCALL,
2694 .features[FEAT_8000_0001_ECX] =
2695 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2696 .features[FEAT_7_0_EBX] =
2697 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2698 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2699 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2700 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
ecb85fe4 2701 CPUID_7_0_EBX_SMAP,
7bde6b18 2702 /* XSAVES is added in version 4 */
f6f949e9
EH		 2703 .features[FEAT_XSAVE] =
2704 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2705 CPUID_XSAVE_XGETBV1,
2706 .features[FEAT_6_EAX] =
2707 CPUID_6_EAX_ARAT,
0723cc8a
PB		 2708 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
2709 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2710 MSR_VMX_BASIC_TRUE_CTLS,
2711 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2712 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2713 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2714 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2715 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2716 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2717 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2718 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2719 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2720 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
2721 .features[FEAT_VMX_EXIT_CTLS] =
2722 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2723 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2724 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2725 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2726 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2727 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2728 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
2729 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2730 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2731 VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
2732 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2733 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2734 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2735 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2736 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2737 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2738 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2739 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2740 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2741 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2742 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2743 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2744 .features[FEAT_VMX_SECONDARY_CTLS] =
2745 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2746 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2747 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2748 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
2749 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
2750 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
2751 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
2752 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
f6f949e9
EH		 2753 .xlevel = 0x80000008,
2754 .model_id = "Intel Core Processor (Skylake)",
d86a7088
EH		 2755 .versions = (X86CPUVersionDefinition[]) {
2756 { .version = 1 },
2757 {
2758 .version = 2,
53db89d9 2759 .alias = "Skylake-Client-IBRS",
d86a7088
EH		 2760 .props = (PropValue[]) {
2761 { "spec-ctrl", "on" },
2762 { "model-id",
2763 "Intel Core Processor (Skylake, IBRS)" },
2764 { /* end of list */ }
2765 }
2766 },
9ab2237f
EH		 2767 {
2768 .version = 3,
02fa60d1 2769 .alias = "Skylake-Client-noTSX-IBRS",
9ab2237f
EH		 2770 .props = (PropValue[]) {
2771 { "hle", "off" },
2772 { "rtm", "off" },
673b0add
KC		 2773 { "model-id",
2774 "Intel Core Processor (Skylake, IBRS, no TSX)" },
9ab2237f
EH		 2775 { /* end of list */ }
2776 }
2777 },
7bde6b18
VK		 2778 {
2779 .version = 4,
2780 .note = "IBRS, XSAVES, no TSX",
2781 .props = (PropValue[]) {
2782 { "xsaves", "on" },
2783 { "vmx-xsaves", "on" },
2784 { /* end of list */ }
2785 }
2786 },
d86a7088
EH		 2787 { /* end of list */ }
2788 }
f6f949e9 2789 },
53f9a6f4
BF		 2790 {
2791 .name = "Skylake-Server",
2792 .level = 0xd,
2793 .vendor = CPUID_VENDOR_INTEL,
2794 .family = 6,
2795 .model = 85,
2796 .stepping = 4,
2797 .features[FEAT_1_EDX] =
2798 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2799 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2800 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2801 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2802 CPUID_DE | CPUID_FP87,
2803 .features[FEAT_1_ECX] =
2804 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2805 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2806 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2807 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2808 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2809 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2810 .features[FEAT_8000_0001_EDX] =
2811 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
2812 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2813 .features[FEAT_8000_0001_ECX] =
2814 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2815 .features[FEAT_7_0_EBX] =
2816 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2817 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2818 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2819 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
ecb85fe4 2820 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
53f9a6f4
BF		 2821 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
2822 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
c68bcb3a 2823 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
09b9ee64
TX		 2824 .features[FEAT_7_0_ECX] =
2825 CPUID_7_0_ECX_PKU,
7bde6b18 2826 /* XSAVES is added in version 5 */
53f9a6f4
BF		 2827 .features[FEAT_XSAVE] =
2828 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2829 CPUID_XSAVE_XGETBV1,
2830 .features[FEAT_6_EAX] =
2831 CPUID_6_EAX_ARAT,
0723cc8a
PB		 2832 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
2833 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2834 MSR_VMX_BASIC_TRUE_CTLS,
2835 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2836 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2837 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2838 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2839 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2840 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2841 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2842 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2843 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2844 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
2845 .features[FEAT_VMX_EXIT_CTLS] =
2846 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2847 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2848 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2849 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2850 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2851 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2852 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
2853 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2854 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2855 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
2856 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2857 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2858 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2859 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2860 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2861 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2862 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2863 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2864 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2865 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2866 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2867 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2868 .features[FEAT_VMX_SECONDARY_CTLS] =
2869 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2870 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2871 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2872 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2873 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
2874 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
2875 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2876 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
c6f3215f
PB		 2877 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
2878 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
53f9a6f4
BF		 2879 .xlevel = 0x80000008,
2880 .model_id = "Intel Xeon Processor (Skylake)",
d86a7088
EH		 2881 .versions = (X86CPUVersionDefinition[]) {
2882 { .version = 1 },
2883 {
2884 .version = 2,
53db89d9 2885 .alias = "Skylake-Server-IBRS",
d86a7088
EH		 2886 .props = (PropValue[]) {
2887 /* clflushopt was not added to Skylake-Server-IBRS */
2888 /* TODO: add -v3 including clflushopt */
2889 { "clflushopt", "off" },
2890 { "spec-ctrl", "on" },
2891 { "model-id",
2892 "Intel Xeon Processor (Skylake, IBRS)" },
2893 { /* end of list */ }
2894 }
2895 },
9ab2237f
EH		 2896 {
2897 .version = 3,
02fa60d1 2898 .alias = "Skylake-Server-noTSX-IBRS",
9ab2237f
EH		 2899 .props = (PropValue[]) {
2900 { "hle", "off" },
2901 { "rtm", "off" },
673b0add
KC		 2902 { "model-id",
2903 "Intel Xeon Processor (Skylake, IBRS, no TSX)" },
9ab2237f
EH		 2904 { /* end of list */ }
2905 }
2906 },
644e3c5d
CQ		 2907 {
2908 .version = 4,
2909 .props = (PropValue[]) {
2910 { "vmx-eptp-switching", "on" },
2911 { /* end of list */ }
2912 }
2913 },
7bde6b18
VK		 2914 {
2915 .version = 5,
2916 .note = "IBRS, XSAVES, EPT switching, no TSX",
2917 .props = (PropValue[]) {
2918 { "xsaves", "on" },
2919 { "vmx-xsaves", "on" },
2920 { /* end of list */ }
2921 }
2922 },
d86a7088
EH		 2923 { /* end of list */ }
2924 }
53f9a6f4 2925 },
c7a88b52
TX		 2926 {
2927 .name = "Cascadelake-Server",
2928 .level = 0xd,
2929 .vendor = CPUID_VENDOR_INTEL,
2930 .family = 6,
2931 .model = 85,
b0a19803 2932 .stepping = 6,
c7a88b52
TX		 2933 .features[FEAT_1_EDX] =
2934 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2935 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2936 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2937 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2938 CPUID_DE | CPUID_FP87,
2939 .features[FEAT_1_ECX] =
2940 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2941 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2942 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2943 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2944 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2945 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2946 .features[FEAT_8000_0001_EDX] =
2947 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
2948 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2949 .features[FEAT_8000_0001_ECX] =
2950 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2951 .features[FEAT_7_0_EBX] =
2952 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2953 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2954 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2955 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
ecb85fe4 2956 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
c7a88b52
TX		 2957 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
2958 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
4c257911 2959 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
c7a88b52 2960 .features[FEAT_7_0_ECX] =
bb4928c7 2961 CPUID_7_0_ECX_PKU |
c7a88b52
TX		 2962 CPUID_7_0_ECX_AVX512VNNI,
2963 .features[FEAT_7_0_EDX] =
2964 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
7bde6b18 2965 /* XSAVES is added in version 5 */
c7a88b52
TX		 2966 .features[FEAT_XSAVE] =
2967 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2968 CPUID_XSAVE_XGETBV1,
2969 .features[FEAT_6_EAX] =
2970 CPUID_6_EAX_ARAT,
0723cc8a
PB		 2971 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
2972 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2973 MSR_VMX_BASIC_TRUE_CTLS,
2974 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2975 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2976 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2977 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2978 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2979 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2980 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2981 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2982 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2983 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
2984 .features[FEAT_VMX_EXIT_CTLS] =
2985 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2986 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2987 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2988 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2989 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2990 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2991 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
2992 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2993 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2994 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
2995 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2996 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2997 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2998 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2999 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3000 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
3001 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
3002 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
3003 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
3004 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3005 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3006 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3007 .features[FEAT_VMX_SECONDARY_CTLS] =
3008 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3009 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3010 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3011 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3012 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3013 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
3014 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3015 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
c6f3215f
PB		 3016 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
3017 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
c7a88b52
TX		 3018 .xlevel = 0x80000008,
3019 .model_id = "Intel Xeon Processor (Cascadelake)",
fd63c6d1
EH		 3020 .versions = (X86CPUVersionDefinition[]) {
3021 { .version = 1 },
3022 { .version = 2,
47f0d11d 3023 .note = "ARCH_CAPABILITIES",
fd63c6d1
EH		 3024 .props = (PropValue[]) {
3025 { "arch-capabilities", "on" },
3026 { "rdctl-no", "on" },
3027 { "ibrs-all", "on" },
3028 { "skip-l1dfl-vmentry", "on" },
3029 { "mds-no", "on" },
3030 { /* end of list */ }
3031 },
3032 },
9ab2237f 3033 { .version = 3,
02fa60d1 3034 .alias = "Cascadelake-Server-noTSX",
47f0d11d 3035 .note = "ARCH_CAPABILITIES, no TSX",
9ab2237f
EH		 3036 .props = (PropValue[]) {
3037 { "hle", "off" },
3038 { "rtm", "off" },
3039 { /* end of list */ }
3040 },
3041 },
644e3c5d
CQ		 3042 { .version = 4,
3043 .note = "ARCH_CAPABILITIES, no TSX",
3044 .props = (PropValue[]) {
3045 { "vmx-eptp-switching", "on" },
3046 { /* end of list */ }
3047 },
3048 },
7bde6b18
VK		 3049 { .version = 5,
3050 .note = "ARCH_CAPABILITIES, EPT switching, XSAVES, no TSX",
3051 .props = (PropValue[]) {
3052 { "xsaves", "on" },
3053 { "vmx-xsaves", "on" },
3054 { /* end of list */ }
3055 },
3056 },
fd63c6d1
EH		 3057 { /* end of list */ }
3058 }
c7a88b52 3059 },
22a866b6
CZ		 3060 {
3061 .name = "Cooperlake",
3062 .level = 0xd,
3063 .vendor = CPUID_VENDOR_INTEL,
3064 .family = 6,
3065 .model = 85,
3066 .stepping = 10,
3067 .features[FEAT_1_EDX] =
3068 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3069 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3070 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3071 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3072 CPUID_DE | CPUID_FP87,
3073 .features[FEAT_1_ECX] =
3074 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3075 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
3076 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
3077 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
3078 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
3079 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
3080 .features[FEAT_8000_0001_EDX] =
3081 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
3082 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3083 .features[FEAT_8000_0001_ECX] =
3084 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
3085 .features[FEAT_7_0_EBX] =
3086 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
3087 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
3088 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
3089 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
3090 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
3091 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
3092 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
3093 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
3094 .features[FEAT_7_0_ECX] =
3095 CPUID_7_0_ECX_PKU |
3096 CPUID_7_0_ECX_AVX512VNNI,
3097 .features[FEAT_7_0_EDX] =
3098 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_STIBP |
3099 CPUID_7_0_EDX_SPEC_CTRL_SSBD | CPUID_7_0_EDX_ARCH_CAPABILITIES,
3100 .features[FEAT_ARCH_CAPABILITIES] =
3101 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL |
2dea9d9c
XL		 3102 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO |
3103 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO,
22a866b6 3104 .features[FEAT_7_1_EAX] =
c1826ea6 3105 CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_AVX512_BF16,
7bde6b18 3106 /* XSAVES is added in version 2 */
22a866b6
CZ		 3107 .features[FEAT_XSAVE] =
3108 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
3109 CPUID_XSAVE_XGETBV1,
3110 .features[FEAT_6_EAX] =
3111 CPUID_6_EAX_ARAT,
2dea9d9c
XL		 3112 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
3113 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
3114 MSR_VMX_BASIC_TRUE_CTLS,
3115 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
3116 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
3117 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
3118 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
3119 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
3120 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
3121 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3122 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3123 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3124 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
3125 .features[FEAT_VMX_EXIT_CTLS] =
3126 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3127 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3128 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
3129 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3130 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3131 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
3132 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
3133 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
3134 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
3135 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
3136 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3137 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3138 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3139 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3140 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3141 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
3142 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
3143 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
3144 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
3145 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3146 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3147 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3148 .features[FEAT_VMX_SECONDARY_CTLS] =
3149 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3150 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3151 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3152 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3153 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3154 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
3155 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3156 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
3157 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
3158 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
3159 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
22a866b6
CZ		 3160 .xlevel = 0x80000008,
3161 .model_id = "Intel Xeon Processor (Cooperlake)",
7bde6b18
VK		 3162 .versions = (X86CPUVersionDefinition[]) {
3163 { .version = 1 },
3164 { .version = 2,
3165 .note = "XSAVES",
3166 .props = (PropValue[]) {
3167 { "xsaves", "on" },
3168 { "vmx-xsaves", "on" },
3169 { /* end of list */ }
3170 },
3171 },
3172 { /* end of list */ }
3173 }
22a866b6 3174 },
8a11c62d
RH		 3175 {
3176 .name = "Icelake-Client",
3177 .level = 0xd,
3178 .vendor = CPUID_VENDOR_INTEL,
3179 .family = 6,
3180 .model = 126,
3181 .stepping = 0,
3182 .features[FEAT_1_EDX] =
3183 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3184 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3185 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3186 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3187 CPUID_DE | CPUID_FP87,
3188 .features[FEAT_1_ECX] =
3189 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3190 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
3191 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
3192 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
3193 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
3194 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
3195 .features[FEAT_8000_0001_EDX] =
3196 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
3197 CPUID_EXT2_SYSCALL,
3198 .features[FEAT_8000_0001_ECX] =
3199 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
3200 .features[FEAT_8000_0008_EBX] =
3201 CPUID_8000_0008_EBX_WBNOINVD,
3202 .features[FEAT_7_0_EBX] =
3203 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
3204 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
3205 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
3206 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
4c257911 3207 CPUID_7_0_EBX_SMAP,
8a11c62d 3208 .features[FEAT_7_0_ECX] =
e7694a5e
TX		 3209 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU |
3210 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI |
8a11c62d
RH		 3211 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ |
3212 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG |
3213 CPUID_7_0_ECX_AVX512_VPOPCNTDQ,
3214 .features[FEAT_7_0_EDX] =
3215 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
7bde6b18 3216 /* XSAVES is added in version 3 */
8a11c62d
RH		 3217 .features[FEAT_XSAVE] =
3218 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
3219 CPUID_XSAVE_XGETBV1,
3220 .features[FEAT_6_EAX] =
3221 CPUID_6_EAX_ARAT,
0723cc8a
PB		 3222 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
3223 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
3224 MSR_VMX_BASIC_TRUE_CTLS,
3225 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
3226 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
3227 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
3228 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
3229 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
3230 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
3231 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3232 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3233 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3234 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
3235 .features[FEAT_VMX_EXIT_CTLS] =
3236 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3237 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3238 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
3239 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3240 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3241 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
3242 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
3243 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
3244 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
3245 VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
3246 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3247 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3248 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3249 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3250 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3251 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
3252 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
3253 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
3254 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
3255 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3256 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3257 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3258 .features[FEAT_VMX_SECONDARY_CTLS] =
3259 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3260 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3261 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3262 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3263 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
3264 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
3265 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
3266 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
8a11c62d
RH		 3267 .xlevel = 0x80000008,
3268 .model_id = "Intel Core Processor (Icelake)",
9ab2237f 3269 .versions = (X86CPUVersionDefinition[]) {
3e6a015c
RH		 3270 {
3271 .version = 1,
3272 .note = "deprecated"
3273 },
9ab2237f
EH		 3274 {
3275 .version = 2,
3e6a015c 3276 .note = "no TSX, deprecated",
02fa60d1 3277 .alias = "Icelake-Client-noTSX",
9ab2237f
EH		 3278 .props = (PropValue[]) {
3279 { "hle", "off" },
3280 { "rtm", "off" },
3281 { /* end of list */ }
3282 },
3283 },
7bde6b18
VK		 3284 {
3285 .version = 3,
3286 .note = "no TSX, XSAVES, deprecated",
3287 .props = (PropValue[]) {
3288 { "xsaves", "on" },
3289 { "vmx-xsaves", "on" },
3290 { /* end of list */ }
3291 },
3292 },
9ab2237f 3293 { /* end of list */ }
3e6a015c
RH		 3294 },
3295 .deprecation_note = "use Icelake-Server instead"
8a11c62d
RH		 3296 },
3297 {
3298 .name = "Icelake-Server",
3299 .level = 0xd,
3300 .vendor = CPUID_VENDOR_INTEL,
3301 .family = 6,
3302 .model = 134,
3303 .stepping = 0,
3304 .features[FEAT_1_EDX] =
3305 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3306 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3307 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3308 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3309 CPUID_DE | CPUID_FP87,
3310 .features[FEAT_1_ECX] =
3311 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3312 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
3313 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
3314 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
3315 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
3316 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
3317 .features[FEAT_8000_0001_EDX] =
3318 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
3319 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3320 .features[FEAT_8000_0001_ECX] =
3321 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
3322 .features[FEAT_8000_0008_EBX] =
3323 CPUID_8000_0008_EBX_WBNOINVD,
3324 .features[FEAT_7_0_EBX] =
3325 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
3326 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
3327 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
3328 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
ecb85fe4 3329 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
8a11c62d
RH		 3330 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
3331 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
4c257911 3332 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
8a11c62d 3333 .features[FEAT_7_0_ECX] =
e7694a5e
TX		 3334 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU |
3335 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI |
8a11c62d
RH		 3336 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ |
3337 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG |
3338 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57,
3339 .features[FEAT_7_0_EDX] =
76e5a4d5 3340 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
7bde6b18 3341 /* XSAVES is added in version 5 */
8a11c62d
RH		 3342 .features[FEAT_XSAVE] =
3343 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
3344 CPUID_XSAVE_XGETBV1,
3345 .features[FEAT_6_EAX] =
3346 CPUID_6_EAX_ARAT,
0723cc8a
PB		 3347 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
3348 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
3349 MSR_VMX_BASIC_TRUE_CTLS,
3350 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
3351 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
3352 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
3353 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
3354 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
3355 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
3356 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3357 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3358 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3359 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
3360 .features[FEAT_VMX_EXIT_CTLS] =
3361 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3362 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3363 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
3364 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3365 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3366 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
3367 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
3368 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
3369 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
3370 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
3371 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3372 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3373 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3374 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3375 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3376 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
3377 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
3378 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
3379 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
3380 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3381 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3382 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3383 .features[FEAT_VMX_SECONDARY_CTLS] =
3384 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3385 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3386 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3387 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3388 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3389 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
3390 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3391 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
3392 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS,
8a11c62d
RH		 3393 .xlevel = 0x80000008,
3394 .model_id = "Intel Xeon Processor (Icelake)",
9ab2237f
EH		 3395 .versions = (X86CPUVersionDefinition[]) {
3396 { .version = 1 },
3397 {
3398 .version = 2,
47f0d11d 3399 .note = "no TSX",
02fa60d1 3400 .alias = "Icelake-Server-noTSX",
9ab2237f
EH		 3401 .props = (PropValue[]) {
3402 { "hle", "off" },
3403 { "rtm", "off" },
3404 { /* end of list */ }
3405 },
3406 },
d965dc35
XL		 3407 {
3408 .version = 3,
3409 .props = (PropValue[]) {
3410 { "arch-capabilities", "on" },
3411 { "rdctl-no", "on" },
3412 { "ibrs-all", "on" },
3413 { "skip-l1dfl-vmentry", "on" },
3414 { "mds-no", "on" },
3415 { "pschange-mc-no", "on" },
3416 { "taa-no", "on" },
3417 { /* end of list */ }
3418 },
3419 },
e0013791
CQ		 3420 {
3421 .version = 4,
3422 .props = (PropValue[]) {
3423 { "sha-ni", "on" },
3424 { "avx512ifma", "on" },
3425 { "rdpid", "on" },
3426 { "fsrm", "on" },
3427 { "vmx-rdseed-exit", "on" },
3428 { "vmx-pml", "on" },
3429 { "vmx-eptp-switching", "on" },
3430 { "model", "106" },
3431 { /* end of list */ }
3432 },
3433 },
7bde6b18
VK		 3434 {
3435 .version = 5,
3436 .note = "XSAVES",
3437 .props = (PropValue[]) {
3438 { "xsaves", "on" },
3439 { "vmx-xsaves", "on" },
3440 { /* end of list */ }
3441 },
3442 },
9ab2237f
EH		 3443 { /* end of list */ }
3444 }
8a11c62d 3445 },
8b44d860
TX		 3446 {
3447 .name = "Denverton",
3448 .level = 21,
3449 .vendor = CPUID_VENDOR_INTEL,
3450 .family = 6,
3451 .model = 95,
3452 .stepping = 1,
3453 .features[FEAT_1_EDX] =
3454 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC |
3455 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC |
3456 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV |
3457 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR |
3458 CPUID_SSE | CPUID_SSE2,
3459 .features[FEAT_1_ECX] =
3460 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR |
3461 CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | CPUID_EXT_SSE41 |
3462 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE |
3463 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER |
3464 CPUID_EXT_AES | CPUID_EXT_XSAVE | CPUID_EXT_RDRAND,
3465 .features[FEAT_8000_0001_EDX] =
3466 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB |
3467 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM,
3468 .features[FEAT_8000_0001_ECX] =
3469 CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
3470 .features[FEAT_7_0_EBX] =
3471 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_ERMS |
3472 CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_SMAP |
3473 CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_SHA_NI,
3474 .features[FEAT_7_0_EDX] =
3475 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_ARCH_CAPABILITIES |
3476 CPUID_7_0_EDX_SPEC_CTRL_SSBD,
7bde6b18 3477 /* XSAVES is added in version 3 */
8b44d860
TX		 3478 .features[FEAT_XSAVE] =
3479 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | CPUID_XSAVE_XGETBV1,
3480 .features[FEAT_6_EAX] =
3481 CPUID_6_EAX_ARAT,
3482 .features[FEAT_ARCH_CAPABILITIES] =
3483 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY,
0723cc8a
PB		 3484 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
3485 MSR_VMX_BASIC_TRUE_CTLS,
3486 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
3487 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
3488 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
3489 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
3490 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
3491 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
3492 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3493 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3494 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3495 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
3496 .features[FEAT_VMX_EXIT_CTLS] =
3497 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3498 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3499 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
3500 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3501 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3502 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
3503 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
3504 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
3505 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
3506 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
3507 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3508 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3509 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3510 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3511 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3512 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
3513 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
3514 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
3515 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
3516 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3517 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3518 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3519 .features[FEAT_VMX_SECONDARY_CTLS] =
3520 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3521 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3522 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3523 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3524 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3525 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
3526 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3527 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
3528 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
3529 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
3530 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
8b44d860
TX		 3531 .xlevel = 0x80000008,
3532 .model_id = "Intel Atom Processor (Denverton)",
ab0c942c
TX		 3533 .versions = (X86CPUVersionDefinition[]) {
3534 { .version = 1 },
3535 {
3536 .version = 2,
47f0d11d 3537 .note = "no MPX, no MONITOR",
ab0c942c
TX		 3538 .props = (PropValue[]) {
3539 { "monitor", "off" },
3540 { "mpx", "off" },
3541 { /* end of list */ },
3542 },
3543 },
7bde6b18
VK		 3544 {
3545 .version = 3,
3546 .note = "XSAVES, no MPX, no MONITOR",
3547 .props = (PropValue[]) {
3548 { "xsaves", "on" },
3549 { "vmx-xsaves", "on" },
3550 { /* end of list */ },
3551 },
3552 },
ab0c942c
TX		 3553 { /* end of list */ },
3554 },
8b44d860 3555 },
0b18874b 3556 {
ff656fcd 3557 .name = "Snowridge",
0b18874b
PL		 3558 .level = 27,
3559 .vendor = CPUID_VENDOR_INTEL,
3560 .family = 6,
3561 .model = 134,
3562 .stepping = 1,
3563 .features[FEAT_1_EDX] =
3564 /* missing: CPUID_PN CPUID_IA64 */
3565 /* missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
3566 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE |
3567 CPUID_TSC | CPUID_MSR | CPUID_PAE | CPUID_MCE |
3568 CPUID_CX8 | CPUID_APIC | CPUID_SEP |
3569 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV |
3570 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH |
3571 CPUID_MMX |
3572 CPUID_FXSR | CPUID_SSE | CPUID_SSE2,
3573 .features[FEAT_1_ECX] =
3574 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR |
0b18874b
PL		 3575 CPUID_EXT_SSSE3 |
3576 CPUID_EXT_CX16 |
3577 CPUID_EXT_SSE41 |
3578 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE |
3579 CPUID_EXT_POPCNT |
3580 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | CPUID_EXT_XSAVE |
3581 CPUID_EXT_RDRAND,
3582 .features[FEAT_8000_0001_EDX] =
3583 CPUID_EXT2_SYSCALL |
3584 CPUID_EXT2_NX |
3585 CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
3586 CPUID_EXT2_LM,
3587 .features[FEAT_8000_0001_ECX] =
3588 CPUID_EXT3_LAHF_LM |
3589 CPUID_EXT3_3DNOWPREFETCH,
3590 .features[FEAT_7_0_EBX] =
3591 CPUID_7_0_EBX_FSGSBASE |
3592 CPUID_7_0_EBX_SMEP |
3593 CPUID_7_0_EBX_ERMS |
3594 CPUID_7_0_EBX_MPX | /* missing bits 13, 15 */
3595 CPUID_7_0_EBX_RDSEED |
3596 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
3597 CPUID_7_0_EBX_CLWB |
3598 CPUID_7_0_EBX_SHA_NI,
3599 .features[FEAT_7_0_ECX] =
3600 CPUID_7_0_ECX_UMIP |
3601 /* missing bit 5 */
3602 CPUID_7_0_ECX_GFNI |
3603 CPUID_7_0_ECX_MOVDIRI | CPUID_7_0_ECX_CLDEMOTE |
3604 CPUID_7_0_ECX_MOVDIR64B,
3605 .features[FEAT_7_0_EDX] =
3606 CPUID_7_0_EDX_SPEC_CTRL |
3607 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD |
3608 CPUID_7_0_EDX_CORE_CAPABILITY,
3609 .features[FEAT_CORE_CAPABILITY] =
3610 MSR_CORE_CAP_SPLIT_LOCK_DETECT,
7bde6b18 3611 /* XSAVES is is added in version 3 */
0b18874b
PL		 3612 .features[FEAT_XSAVE] =
3613 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
3614 CPUID_XSAVE_XGETBV1,
3615 .features[FEAT_6_EAX] =
3616 CPUID_6_EAX_ARAT,
0723cc8a
PB		 3617 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
3618 MSR_VMX_BASIC_TRUE_CTLS,
3619 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
3620 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
3621 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
3622 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
3623 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
3624 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
3625 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3626 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3627 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3628 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
3629 .features[FEAT_VMX_EXIT_CTLS] =
3630 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3631 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3632 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
3633 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3634 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3635 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
3636 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
3637 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
3638 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
3639 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
3640 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3641 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3642 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3643 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3644 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3645 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
3646 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
3647 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
3648 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
3649 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3650 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3651 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3652 .features[FEAT_VMX_SECONDARY_CTLS] =
3653 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3654 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3655 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3656 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3657 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3658 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
3659 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3660 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
3661 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
3662 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
3663 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
0b18874b
PL		 3664 .xlevel = 0x80000008,
3665 .model_id = "Intel Atom Processor (SnowRidge)",
69edb0f3
XL		 3666 .versions = (X86CPUVersionDefinition[]) {
3667 { .version = 1 },
3668 {
3669 .version = 2,
3670 .props = (PropValue[]) {
3671 { "mpx", "off" },
3672 { "model-id", "Intel Atom Processor (Snowridge, no MPX)" },
3673 { /* end of list */ },
3674 },
3675 },
7bde6b18
VK		 3676 {
3677 .version = 3,
3678 .note = "XSAVES, no MPX",
3679 .props = (PropValue[]) {
3680 { "xsaves", "on" },
3681 { "vmx-xsaves", "on" },
3682 { /* end of list */ },
3683 },
3684 },
69edb0f3
XL		 3685 { /* end of list */ },
3686 },
0b18874b 3687 },
a1849515
BF		 3688 {
3689 .name = "KnightsMill",
3690 .level = 0xd,
3691 .vendor = CPUID_VENDOR_INTEL,
3692 .family = 6,
3693 .model = 133,
3694 .stepping = 0,
3695 .features[FEAT_1_EDX] =
3696 CPUID_VME | CPUID_SS | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR |
3697 CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV |
3698 CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC |
3699 CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC |
3700 CPUID_PSE | CPUID_DE | CPUID_FP87,
3701 .features[FEAT_1_ECX] =
3702 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3703 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
3704 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
3705 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
3706 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
3707 CPUID_EXT_F16C | CPUID_EXT_RDRAND,
3708 .features[FEAT_8000_0001_EDX] =
3709 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
3710 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3711 .features[FEAT_8000_0001_ECX] =
3712 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
3713 .features[FEAT_7_0_EBX] =
3714 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
3715 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS |
3716 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_AVX512F |
3717 CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_AVX512PF |
3718 CPUID_7_0_EBX_AVX512ER,
3719 .features[FEAT_7_0_ECX] =
3720 CPUID_7_0_ECX_AVX512_VPOPCNTDQ,
3721 .features[FEAT_7_0_EDX] =
3722 CPUID_7_0_EDX_AVX512_4VNNIW | CPUID_7_0_EDX_AVX512_4FMAPS,
3723 .features[FEAT_XSAVE] =
3724 CPUID_XSAVE_XSAVEOPT,
3725 .features[FEAT_6_EAX] =
3726 CPUID_6_EAX_ARAT,
3727 .xlevel = 0x80000008,
3728 .model_id = "Intel Xeon Phi Processor (Knights Mill)",
3729 },
3eca4642
EH		 3730 {
3731 .name = "Opteron_G1",
3732 .level = 5,
99b88a17 3733 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 3734 .family = 15,
3735 .model = 6,
3736 .stepping = 1,
0514ef2f 3737 .features[FEAT_1_EDX] =
b3a4f0b1 3738 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 3739 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3740 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3741 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3742 CPUID_DE | CPUID_FP87,
0514ef2f 3743 .features[FEAT_1_ECX] =
27861ecc 3744 CPUID_EXT_SSE3,
0514ef2f 3745 .features[FEAT_8000_0001_EDX] =
2a923a29 3746 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3eca4642
EH		 3747 .xlevel = 0x80000008,
3748 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
3749 },
3750 {
3751 .name = "Opteron_G2",
3752 .level = 5,
99b88a17 3753 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 3754 .family = 15,
3755 .model = 6,
3756 .stepping = 1,
0514ef2f 3757 .features[FEAT_1_EDX] =
b3a4f0b1 3758 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 3759 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3760 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3761 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3762 CPUID_DE | CPUID_FP87,
0514ef2f 3763 .features[FEAT_1_ECX] =
27861ecc 3764 CPUID_EXT_CX16 | CPUID_EXT_SSE3,
0514ef2f 3765 .features[FEAT_8000_0001_EDX] =
2a923a29 3766 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 3767 .features[FEAT_8000_0001_ECX] =
27861ecc 3768 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH		 3769 .xlevel = 0x80000008,
3770 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
3771 },
3772 {
3773 .name = "Opteron_G3",
3774 .level = 5,
99b88a17 3775 .vendor = CPUID_VENDOR_AMD,
339892d7
EY		 3776 .family = 16,
3777 .model = 2,
3778 .stepping = 3,
0514ef2f 3779 .features[FEAT_1_EDX] =
b3a4f0b1 3780 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 3781 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3782 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3783 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3784 CPUID_DE | CPUID_FP87,
0514ef2f 3785 .features[FEAT_1_ECX] =
27861ecc 3786 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
b3fb3a20 3787 CPUID_EXT_SSE3,
0514ef2f 3788 .features[FEAT_8000_0001_EDX] =
483c6ad4
BP		 3789 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL |
3790 CPUID_EXT2_RDTSCP,
0514ef2f 3791 .features[FEAT_8000_0001_ECX] =
27861ecc 3792 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
b3fb3a20 3793 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH		 3794 .xlevel = 0x80000008,
3795 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
3796 },
3797 {
3798 .name = "Opteron_G4",
3799 .level = 0xd,
99b88a17 3800 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 3801 .family = 21,
3802 .model = 1,
3803 .stepping = 2,
0514ef2f 3804 .features[FEAT_1_EDX] =
b3a4f0b1 3805 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 3806 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3807 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3808 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3809 CPUID_DE | CPUID_FP87,
0514ef2f 3810 .features[FEAT_1_ECX] =
27861ecc 3811 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 3812 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
3813 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
3814 CPUID_EXT_SSE3,
0514ef2f 3815 .features[FEAT_8000_0001_EDX] =
2a923a29 3816 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX |
483c6ad4 3817 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP,
0514ef2f 3818 .features[FEAT_8000_0001_ECX] =
27861ecc 3819 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
b3fb3a20
EH		 3820 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
3821 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
3822 CPUID_EXT3_LAHF_LM,
9fe8b7be
VK		 3823 .features[FEAT_SVM] =
3824 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
0bb0b2d2 3825 /* no xsaveopt! */
3eca4642
EH		 3826 .xlevel = 0x8000001A,
3827 .model_id = "AMD Opteron 62xx class CPU",
3828 },
021941b9
AP		 3829 {
3830 .name = "Opteron_G5",
3831 .level = 0xd,
99b88a17 3832 .vendor = CPUID_VENDOR_AMD,
021941b9
AP		 3833 .family = 21,
3834 .model = 2,
3835 .stepping = 0,
0514ef2f 3836 .features[FEAT_1_EDX] =
b3a4f0b1 3837 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 3838 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3839 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3840 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3841 CPUID_DE | CPUID_FP87,
0514ef2f 3842 .features[FEAT_1_ECX] =
27861ecc 3843 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
b3fb3a20
EH		 3844 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
3845 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
3846 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
0514ef2f 3847 .features[FEAT_8000_0001_EDX] =
2a923a29 3848 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX |
483c6ad4 3849 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP,
0514ef2f 3850 .features[FEAT_8000_0001_ECX] =
27861ecc 3851 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
b3fb3a20
EH		 3852 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
3853 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
3854 CPUID_EXT3_LAHF_LM,
9fe8b7be
VK		 3855 .features[FEAT_SVM] =
3856 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
0bb0b2d2 3857 /* no xsaveopt! */
021941b9
AP		 3858 .xlevel = 0x8000001A,
3859 .model_id = "AMD Opteron 63xx class CPU",
3860 },
2e2efc7d
BS		 3861 {
3862 .name = "EPYC",
3863 .level = 0xd,
3864 .vendor = CPUID_VENDOR_AMD,
3865 .family = 23,
3866 .model = 1,
3867 .stepping = 2,
3868 .features[FEAT_1_EDX] =
3869 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
3870 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
3871 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
3872 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
3873 CPUID_VME | CPUID_FP87,
3874 .features[FEAT_1_ECX] =
3875 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
3876 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT |
3877 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
3878 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
3879 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
3880 .features[FEAT_8000_0001_EDX] =
3881 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
3882 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
3883 CPUID_EXT2_SYSCALL,
3884 .features[FEAT_8000_0001_ECX] =
3885 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
3886 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
e0051647
BM		 3887 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |
3888 CPUID_EXT3_TOPOEXT,
2e2efc7d
BS		 3889 .features[FEAT_7_0_EBX] =
3890 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
3891 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
3892 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
3893 CPUID_7_0_EBX_SHA_NI,
2e2efc7d
BS		 3894 .features[FEAT_XSAVE] =
3895 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
3896 CPUID_XSAVE_XGETBV1,
3897 .features[FEAT_6_EAX] =
3898 CPUID_6_EAX_ARAT,
9fe8b7be
VK		 3899 .features[FEAT_SVM] =
3900 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
e0051647 3901 .xlevel = 0x8000001E,
2e2efc7d 3902 .model_id = "AMD EPYC Processor",
fe52acd2 3903 .cache_info = &epyc_cache_info,
d86a7088
EH		 3904 .versions = (X86CPUVersionDefinition[]) {
3905 { .version = 1 },
3906 {
3907 .version = 2,
53db89d9 3908 .alias = "EPYC-IBPB",
d86a7088
EH		 3909 .props = (PropValue[]) {
3910 { "ibpb", "on" },
3911 { "model-id",
3912 "AMD EPYC Processor (with IBPB)" },
3913 { /* end of list */ }
3914 }
3915 },
a16e8dbc
MB		 3916 {
3917 .version = 3,
3918 .props = (PropValue[]) {
3919 { "ibpb", "on" },
3920 { "perfctr-core", "on" },
3921 { "clzero", "on" },
3922 { "xsaveerptr", "on" },
3923 { "xsaves", "on" },
3924 { "model-id",
3925 "AMD EPYC Processor" },
3926 { /* end of list */ }
3927 }
3928 },
d86a7088
EH		 3929 { /* end of list */ }
3930 }
2e2efc7d 3931 },
8d031cec
PW		 3932 {
3933 .name = "Dhyana",
3934 .level = 0xd,
3935 .vendor = CPUID_VENDOR_HYGON,
3936 .family = 24,
3937 .model = 0,
3938 .stepping = 1,
3939 .features[FEAT_1_EDX] =
3940 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
3941 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
3942 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
3943 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
3944 CPUID_VME | CPUID_FP87,
3945 .features[FEAT_1_ECX] =
3946 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
3947 CPUID_EXT_XSAVE | CPUID_EXT_POPCNT |
3948 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
3949 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
3950 CPUID_EXT_MONITOR | CPUID_EXT_SSE3,
3951 .features[FEAT_8000_0001_EDX] =
3952 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
3953 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
3954 CPUID_EXT2_SYSCALL,
3955 .features[FEAT_8000_0001_ECX] =
3956 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
3957 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
3958 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |
3959 CPUID_EXT3_TOPOEXT,
3960 .features[FEAT_8000_0008_EBX] =
3961 CPUID_8000_0008_EBX_IBPB,
3962 .features[FEAT_7_0_EBX] =
3963 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
3964 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
3965 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT,
7bde6b18 3966 /* XSAVES is added in version 2 */
8d031cec
PW		 3967 .features[FEAT_XSAVE] =
3968 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
3969 CPUID_XSAVE_XGETBV1,
3970 .features[FEAT_6_EAX] =
3971 CPUID_6_EAX_ARAT,
3972 .features[FEAT_SVM] =
3973 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
3974 .xlevel = 0x8000001E,
3975 .model_id = "Hygon Dhyana Processor",
3976 .cache_info = &epyc_cache_info,
7bde6b18
VK		 3977 .versions = (X86CPUVersionDefinition[]) {
3978 { .version = 1 },
3979 { .version = 2,
3980 .note = "XSAVES",
3981 .props = (PropValue[]) {
3982 { "xsaves", "on" },
3983 { /* end of list */ }
3984 },
3985 },
3986 { /* end of list */ }
3987 }
8d031cec 3988 },
143c30d4
MB		 3989 {
3990 .name = "EPYC-Rome",
3991 .level = 0xd,
3992 .vendor = CPUID_VENDOR_AMD,
3993 .family = 23,
3994 .model = 49,
3995 .stepping = 0,
3996 .features[FEAT_1_EDX] =
3997 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
3998 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
3999 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
4000 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
4001 CPUID_VME | CPUID_FP87,
4002 .features[FEAT_1_ECX] =
4003 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
4004 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT |
4005 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
4006 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
4007 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
4008 .features[FEAT_8000_0001_EDX] =
4009 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
4010 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
4011 CPUID_EXT2_SYSCALL,
4012 .features[FEAT_8000_0001_ECX] =
4013 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
4014 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
4015 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |
4016 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE,
4017 .features[FEAT_8000_0008_EBX] =
4018 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR |
4019 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB |
4020 CPUID_8000_0008_EBX_STIBP,
4021 .features[FEAT_7_0_EBX] =
4022 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
4023 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
4024 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
4025 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_CLWB,
4026 .features[FEAT_7_0_ECX] =
4027 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_RDPID,
4028 .features[FEAT_XSAVE] =
4029 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
4030 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES,
4031 .features[FEAT_6_EAX] =
4032 CPUID_6_EAX_ARAT,
4033 .features[FEAT_SVM] =
4034 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
4035 .xlevel = 0x8000001E,
4036 .model_id = "AMD EPYC-Rome Processor",
4037 .cache_info = &epyc_rome_cache_info,
cdeaed27
BM		 4038 .versions = (X86CPUVersionDefinition[]) {
4039 { .version = 1 },
4040 {
4041 .version = 2,
4042 .props = (PropValue[]) {
4043 { "ibrs", "on" },
4044 { "amd-ssbd", "on" },
4045 { /* end of list */ }
4046 }
4047 },
4048 { /* end of list */ }
4049 }
143c30d4 4050 },
623972ce
BM		 4051 {
4052 .name = "EPYC-Milan",
4053 .level = 0xd,
4054 .vendor = CPUID_VENDOR_AMD,
4055 .family = 25,
4056 .model = 1,
4057 .stepping = 1,
4058 .features[FEAT_1_EDX] =
4059 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
4060 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
4061 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
4062 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
4063 CPUID_VME | CPUID_FP87,
4064 .features[FEAT_1_ECX] =
4065 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
4066 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT |
4067 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
4068 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
4069 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
4070 CPUID_EXT_PCID,
4071 .features[FEAT_8000_0001_EDX] =
4072 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
4073 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
4074 CPUID_EXT2_SYSCALL,
4075 .features[FEAT_8000_0001_ECX] =
4076 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
4077 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
4078 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |
4079 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE,
4080 .features[FEAT_8000_0008_EBX] =
4081 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR |
4082 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB |
4083 CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP |
4084 CPUID_8000_0008_EBX_AMD_SSBD,
4085 .features[FEAT_7_0_EBX] =
4086 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
4087 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
4088 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
4089 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_ERMS |
4090 CPUID_7_0_EBX_INVPCID,
4091 .features[FEAT_7_0_ECX] =
4092 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_PKU,
4093 .features[FEAT_7_0_EDX] =
4094 CPUID_7_0_EDX_FSRM,
4095 .features[FEAT_XSAVE] =
4096 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
4097 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES,
4098 .features[FEAT_6_EAX] =
4099 CPUID_6_EAX_ARAT,
4100 .features[FEAT_SVM] =
4101 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE | CPUID_SVM_SVME_ADDR_CHK,
4102 .xlevel = 0x8000001E,
4103 .model_id = "AMD EPYC-Milan Processor",
4104 .cache_info = &epyc_milan_cache_info,
4105 },
c6dc6f63
AP		 4106};
4107
ad183928
EH		 4108/*
4109 * We resolve CPU model aliases using -v1 when using "-machine
4110 * none", but this is just for compatibility while libvirt isn't
4111 * adapted to resolve CPU model versions before creating VMs.
32048d72
MA		 4112 * See "Runnability guarantee of CPU models" at
4113 * docs/system/deprecated.rst.
ad183928
EH		 4114 */
4115X86CPUVersion default_cpu_version = 1;
0788a56b
EH		 4116
4117void x86_cpu_set_default_version(X86CPUVersion version)
4118{
4119 /* Translating CPU_VERSION_AUTO to CPU_VERSION_AUTO doesn't make sense */
4120 assert(version != CPU_VERSION_AUTO);
4121 default_cpu_version = version;
4122}
4123
dcafd1ef
EH		 4124static X86CPUVersion x86_cpu_model_last_version(const X86CPUModel *model)
4125{
4126 int v = 0;
4127 const X86CPUVersionDefinition *vdef =
4128 x86_cpu_def_get_versions(model->cpudef);
4129 while (vdef->version) {
4130 v = vdef->version;
4131 vdef++;
4132 }
4133 return v;
4134}
4135
4136/* Return the actual version being used for a specific CPU model */
4137static X86CPUVersion x86_cpu_model_resolve_version(const X86CPUModel *model)
4138{
4139 X86CPUVersion v = model->version;
0788a56b
EH		 4140 if (v == CPU_VERSION_AUTO) {
4141 v = default_cpu_version;
4142 }
dcafd1ef
EH		 4143 if (v == CPU_VERSION_LATEST) {
4144 return x86_cpu_model_last_version(model);
4145 }
4146 return v;
4147}
4148
c62f2630 4149static Property max_x86_cpu_properties[] = {
120eee7d 4150 DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true),
e265e3e4 4151 DEFINE_PROP_BOOL("host-cache-info", X86CPU, cache_info_passthrough, false),
84f1b92f
EH		 4152 DEFINE_PROP_END_OF_LIST()
4153};
4154
c62f2630 4155static void max_x86_cpu_class_init(ObjectClass *oc, void *data)
c6dc6f63 4156{
84f1b92f 4157 DeviceClass *dc = DEVICE_CLASS(oc);
d940ee9b 4158 X86CPUClass *xcc = X86_CPU_CLASS(oc);
c6dc6f63 4159
f48c8837 4160 xcc->ordering = 9;
6e746f30 4161
ee465a3e 4162 xcc->model_description =
c62f2630 4163 "Enables all features supported by the accelerator in the current host";
d940ee9b 4164
4f67d30b 4165 device_class_set_props(dc, max_x86_cpu_properties);
d940ee9b
EH		 4166}
4167
c62f2630 4168static void max_x86_cpu_initfn(Object *obj)
d940ee9b
EH		 4169{
4170 X86CPU *cpu = X86_CPU(obj);
d940ee9b 4171
4d1b279b
EH		 4172 /* We can't fill the features array here because we don't know yet if
4173 * "migratable" is true or false.
4174 */
44bd8e53 4175 cpu->max_features = true;
5325cc34 4176 object_property_set_bool(OBJECT(cpu), "pmu", true, &error_abort);
f5cc5a5c
CF		 4177
4178 /*
4179 * these defaults are used for TCG and all other accelerators
4180 * besides KVM and HVF, which overwrite these values
4181 */
4182 object_property_set_str(OBJECT(cpu), "vendor", CPUID_VENDOR_AMD,
4183 &error_abort);
40b3cc35
DB		 4184#ifdef TARGET_X86_64
4185 object_property_set_int(OBJECT(cpu), "family", 15, &error_abort);
4186 object_property_set_int(OBJECT(cpu), "model", 107, &error_abort);
4187 object_property_set_int(OBJECT(cpu), "stepping", 1, &error_abort);
4188#else
f5cc5a5c
CF		 4189 object_property_set_int(OBJECT(cpu), "family", 6, &error_abort);
4190 object_property_set_int(OBJECT(cpu), "model", 6, &error_abort);
4191 object_property_set_int(OBJECT(cpu), "stepping", 3, &error_abort);
40b3cc35 4192#endif
f5cc5a5c
CF		 4193 object_property_set_str(OBJECT(cpu), "model-id",
4194 "QEMU TCG CPU version " QEMU_HW_VERSION,
4195 &error_abort);
c6dc6f63
AP		 4196}
4197
c62f2630
EH		 4198static const TypeInfo max_x86_cpu_type_info = {
4199 .name = X86_CPU_TYPE_NAME("max"),
4200 .parent = TYPE_X86_CPU,
4201 .instance_init = max_x86_cpu_initfn,
4202 .class_init = max_x86_cpu_class_init,
4203};
4204
07585923
RH		 4205static char *feature_word_description(FeatureWordInfo *f, uint32_t bit)
4206{
4207 assert(f->type == CPUID_FEATURE_WORD || f->type == MSR_FEATURE_WORD);
4208
4209 switch (f->type) {
4210 case CPUID_FEATURE_WORD:
4211 {
4212 const char *reg = get_register_name_32(f->cpuid.reg);
4213 assert(reg);
4214 return g_strdup_printf("CPUID.%02XH:%s",
4215 f->cpuid.eax, reg);
4216 }
4217 case MSR_FEATURE_WORD:
4218 return g_strdup_printf("MSR(%02XH)",
4219 f->msr.index);
4220 }
4221
4222 return NULL;
4223}
4224
245edd0c 4225static bool x86_cpu_have_filtered_features(X86CPU *cpu)
c6dc6f63 4226{
245edd0c
PB		 4227 FeatureWord w;
4228
4229 for (w = 0; w < FEATURE_WORDS; w++) {
4230 if (cpu->filtered_features[w]) {
4231 return true;
4232 }
4233 }
4234
4235 return false;
4236}
4237
ede146c2 4238static void mark_unavailable_features(X86CPU *cpu, FeatureWord w, uint64_t mask,
245edd0c
PB		 4239 const char *verbose_prefix)
4240{
4241 CPUX86State *env = &cpu->env;
8459e396 4242 FeatureWordInfo *f = &feature_word_info[w];
c6dc6f63
AP		 4243 int i;
4244
245edd0c
PB		 4245 if (!cpu->force_features) {
4246 env->features[w] &= ~mask;
4247 }
4248 cpu->filtered_features[w] |= mask;
4249
4250 if (!verbose_prefix) {
4251 return;
4252 }
4253
ede146c2
PB		 4254 for (i = 0; i < 64; ++i) {
4255 if ((1ULL << i) & mask) {
88703ce2 4256 g_autofree char *feat_word_str = feature_word_description(f, i);
245edd0c
PB		 4257 warn_report("%s: %s%s%s [bit %d]",
4258 verbose_prefix,
07585923 4259 feat_word_str,
8297be80
AF		 4260 f->feat_names[i] ? "." : "",
4261 f->feat_names[i] ? f->feat_names[i] : "", i);
c6dc6f63 4262 }
857aee33 4263 }
c6dc6f63
AP		 4264}
4265
d7bce999
EB		 4266static void x86_cpuid_version_get_family(Object *obj, Visitor *v,
4267 const char *name, void *opaque,
4268 Error **errp)
95b8519d
AF		 4269{
4270 X86CPU *cpu = X86_CPU(obj);
4271 CPUX86State *env = &cpu->env;
4272 int64_t value;
4273
4274 value = (env->cpuid_version >> 8) & 0xf;
4275 if (value == 0xf) {
4276 value += (env->cpuid_version >> 20) & 0xff;
4277 }
51e72bc1 4278 visit_type_int(v, name, &value, errp);
95b8519d
AF		 4279}
4280
d7bce999
EB		 4281static void x86_cpuid_version_set_family(Object *obj, Visitor *v,
4282 const char *name, void *opaque,
4283 Error **errp)
ed5e1ec3 4284{
71ad61d3
AF		 4285 X86CPU *cpu = X86_CPU(obj);
4286 CPUX86State *env = &cpu->env;
4287 const int64_t min = 0;
4288 const int64_t max = 0xff + 0xf;
4289 int64_t value;
4290
668f62ec 4291 if (!visit_type_int(v, name, &value, errp)) {
71ad61d3
AF		 4292 return;
4293 }
4294 if (value < min || value > max) {
c6bd8c70
MA		 4295 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
4296 name ? name : "null", value, min, max);
71ad61d3
AF		 4297 return;
4298 }
4299
ed5e1ec3 4300 env->cpuid_version &= ~0xff00f00;
71ad61d3
AF		 4301 if (value > 0x0f) {
4302 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
ed5e1ec3 4303 } else {
71ad61d3 4304 env->cpuid_version |= value << 8;
ed5e1ec3
AF		 4305 }
4306}
4307
d7bce999
EB		 4308static void x86_cpuid_version_get_model(Object *obj, Visitor *v,
4309 const char *name, void *opaque,
4310 Error **errp)
67e30c83
AF		 4311{
4312 X86CPU *cpu = X86_CPU(obj);
4313 CPUX86State *env = &cpu->env;
4314 int64_t value;
4315
4316 value = (env->cpuid_version >> 4) & 0xf;
4317 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
51e72bc1 4318 visit_type_int(v, name, &value, errp);
67e30c83
AF		 4319}
4320
d7bce999
EB		 4321static void x86_cpuid_version_set_model(Object *obj, Visitor *v,
4322 const char *name, void *opaque,
4323 Error **errp)
b0704cbd 4324{
c5291a4f
AF		 4325 X86CPU *cpu = X86_CPU(obj);
4326 CPUX86State *env = &cpu->env;
4327 const int64_t min = 0;
4328 const int64_t max = 0xff;
4329 int64_t value;
4330
668f62ec 4331 if (!visit_type_int(v, name, &value, errp)) {
c5291a4f
AF		 4332 return;
4333 }
4334 if (value < min || value > max) {
c6bd8c70
MA		 4335 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
4336 name ? name : "null", value, min, max);
c5291a4f
AF		 4337 return;
4338 }
4339
b0704cbd 4340 env->cpuid_version &= ~0xf00f0;
c5291a4f 4341 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
b0704cbd
AF		 4342}
4343
35112e41 4344static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
d7bce999 4345 const char *name, void *opaque,
35112e41
AF		 4346 Error **errp)
4347{
4348 X86CPU *cpu = X86_CPU(obj);
4349 CPUX86State *env = &cpu->env;
4350 int64_t value;
4351
4352 value = env->cpuid_version & 0xf;
51e72bc1 4353 visit_type_int(v, name, &value, errp);
35112e41
AF		 4354}
4355
036e2222 4356static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
d7bce999 4357 const char *name, void *opaque,
036e2222 4358 Error **errp)
38c3dc46 4359{
036e2222
AF		 4360 X86CPU *cpu = X86_CPU(obj);
4361 CPUX86State *env = &cpu->env;
4362 const int64_t min = 0;
4363 const int64_t max = 0xf;
4364 int64_t value;
4365
668f62ec 4366 if (!visit_type_int(v, name, &value, errp)) {
036e2222
AF		 4367 return;
4368 }
4369 if (value < min || value > max) {
c6bd8c70
MA		 4370 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
4371 name ? name : "null", value, min, max);
036e2222
AF		 4372 return;
4373 }
4374
38c3dc46 4375 env->cpuid_version &= ~0xf;
036e2222 4376 env->cpuid_version |= value & 0xf;
38c3dc46
AF		 4377}
4378
d480e1af
AF		 4379static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
4380{
4381 X86CPU *cpu = X86_CPU(obj);
4382 CPUX86State *env = &cpu->env;
4383 char *value;
d480e1af 4384
e42a92ae 4385 value = g_malloc(CPUID_VENDOR_SZ + 1);
99b88a17
IM		 4386 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2,
4387 env->cpuid_vendor3);
d480e1af
AF		 4388 return value;
4389}
4390
4391static void x86_cpuid_set_vendor(Object *obj, const char *value,
4392 Error **errp)
4393{
4394 X86CPU *cpu = X86_CPU(obj);
4395 CPUX86State *env = &cpu->env;
4396 int i;
4397
9df694ee 4398 if (strlen(value) != CPUID_VENDOR_SZ) {
c6bd8c70 4399 error_setg(errp, QERR_PROPERTY_VALUE_BAD, "", "vendor", value);
d480e1af
AF		 4400 return;
4401 }
4402
4403 env->cpuid_vendor1 = 0;
4404 env->cpuid_vendor2 = 0;
4405 env->cpuid_vendor3 = 0;
4406 for (i = 0; i < 4; i++) {
4407 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
4408 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
4409 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
4410 }
d480e1af
AF		 4411}
4412
63e886eb
AF		 4413static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
4414{
4415 X86CPU *cpu = X86_CPU(obj);
4416 CPUX86State *env = &cpu->env;
4417 char *value;
4418 int i;
4419
4420 value = g_malloc(48 + 1);
4421 for (i = 0; i < 48; i++) {
4422 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
4423 }
4424 value[48] = '\0';
4425 return value;
4426}
4427
938d4c25
AF		 4428static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
4429 Error **errp)
dcce6675 4430{
938d4c25
AF		 4431 X86CPU *cpu = X86_CPU(obj);
4432 CPUX86State *env = &cpu->env;
dcce6675
AF		 4433 int c, len, i;
4434
4435 if (model_id == NULL) {
4436 model_id = "";
4437 }
4438 len = strlen(model_id);
d0a6acf4 4439 memset(env->cpuid_model, 0, 48);
dcce6675
AF		 4440 for (i = 0; i < 48; i++) {
4441 if (i >= len) {
4442 c = '\0';
4443 } else {
4444 c = (uint8_t)model_id[i];
4445 }
4446 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
4447 }
4448}
4449
d7bce999
EB		 4450static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, const char *name,
4451 void *opaque, Error **errp)
89e48965
AF		 4452{
4453 X86CPU *cpu = X86_CPU(obj);
4454 int64_t value;
4455
4456 value = cpu->env.tsc_khz * 1000;
51e72bc1 4457 visit_type_int(v, name, &value, errp);
89e48965
AF		 4458}
4459
d7bce999
EB		 4460static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, const char *name,
4461 void *opaque, Error **errp)
89e48965
AF		 4462{
4463 X86CPU *cpu = X86_CPU(obj);
4464 const int64_t min = 0;
2e84849a 4465 const int64_t max = INT64_MAX;
89e48965
AF		 4466 int64_t value;
4467
668f62ec 4468 if (!visit_type_int(v, name, &value, errp)) {
89e48965
AF		 4469 return;
4470 }
4471 if (value < min || value > max) {
c6bd8c70
MA		 4472 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
4473 name ? name : "null", value, min, max);
89e48965
AF		 4474 return;
4475 }
4476
36f96c4b 4477 cpu->env.tsc_khz = cpu->env.user_tsc_khz = value / 1000;
89e48965
AF		 4478}
4479
7e5292b5 4480/* Generic getter for "feature-words" and "filtered-features" properties */
d7bce999
EB		 4481static void x86_cpu_get_feature_words(Object *obj, Visitor *v,
4482 const char *name, void *opaque,
4483 Error **errp)
8e8aba50 4484{
ede146c2 4485 uint64_t *array = (uint64_t *)opaque;
8e8aba50 4486 FeatureWord w;
8e8aba50
EH		 4487 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { };
4488 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { };
4489 X86CPUFeatureWordInfoList *list = NULL;
4490
4491 for (w = 0; w < FEATURE_WORDS; w++) {
4492 FeatureWordInfo *wi = &feature_word_info[w];
07585923
RH		 4493 /*
4494 * We didn't have MSR features when "feature-words" was
4495 * introduced. Therefore skipped other type entries.
4496 */
4497 if (wi->type != CPUID_FEATURE_WORD) {
4498 continue;
4499 }
8e8aba50 4500 X86CPUFeatureWordInfo *qwi = &word_infos[w];
07585923
RH		 4501 qwi->cpuid_input_eax = wi->cpuid.eax;
4502 qwi->has_cpuid_input_ecx = wi->cpuid.needs_ecx;
4503 qwi->cpuid_input_ecx = wi->cpuid.ecx;
4504 qwi->cpuid_register = x86_reg_info_32[wi->cpuid.reg].qapi_enum;
7e5292b5 4505 qwi->features = array[w];
8e8aba50
EH		 4506
4507 /* List will be in reverse order, but order shouldn't matter */
4508 list_entries[w].next = list;
4509 list_entries[w].value = &word_infos[w];
4510 list = &list_entries[w];
4511 }
4512
6b62d961 4513 visit_type_X86CPUFeatureWordInfoList(v, "feature-words", &list, errp);
8e8aba50
EH		 4514}
4515
72ac2e87
IM		 4516/* Convert all '_' in a feature string option name to '-', to make feature
4517 * name conform to QOM property naming rule, which uses '-' instead of '_'.
4518 */
4519static inline void feat2prop(char *s)
4520{
4521 while ((s = strchr(s, '_'))) {
4522 *s = '-';
4523 }
4524}
4525
b54c9377
EH		 4526/* Return the feature property name for a feature flag bit */
4527static const char *x86_cpu_feature_name(FeatureWord w, int bitnr)
4528{
ede146c2 4529 const char *name;
b54c9377
EH		 4530 /* XSAVE components are automatically enabled by other features,
4531 * so return the original feature name instead
4532 */
4533 if (w == FEAT_XSAVE_COMP_LO || w == FEAT_XSAVE_COMP_HI) {
4534 int comp = (w == FEAT_XSAVE_COMP_HI) ? bitnr + 32 : bitnr;
4535
4536 if (comp < ARRAY_SIZE(x86_ext_save_areas) &&
4537 x86_ext_save_areas[comp].bits) {
4538 w = x86_ext_save_areas[comp].feature;
4539 bitnr = ctz32(x86_ext_save_areas[comp].bits);
4540 }
4541 }
4542
ede146c2 4543 assert(bitnr < 64);
b54c9377 4544 assert(w < FEATURE_WORDS);
ede146c2
PB		 4545 name = feature_word_info[w].feat_names[bitnr];
4546 assert(bitnr < 32 || !(name && feature_word_info[w].type == CPUID_FEATURE_WORD));
4547 return name;
b54c9377
EH		 4548}
4549
dc15c051
IM		 4550/* Compatibily hack to maintain legacy +-feat semantic,
4551 * where +-feat overwrites any feature set by
4552 * feat=on|feat even if the later is parsed after +-feat
4553 * (i.e. "-x2apic,x2apic=on" will result in x2apic disabled)
4554 */
2fae0d96 4555static GList *plus_features, *minus_features;
dc15c051 4556
83a00f60
EH		 4557static gint compare_string(gconstpointer a, gconstpointer b)
4558{
4559 return g_strcmp0(a, b);
4560}
4561
8f961357
EH		 4562/* Parse "+feature,-feature,feature=foo" CPU feature string
4563 */
62a48a2a 4564static void x86_cpu_parse_featurestr(const char *typename, char *features,
94a444b2 4565 Error **errp)
8f961357 4566{
8f961357 4567 char *featurestr; /* Single 'key=value" string being parsed */
62a48a2a 4568 static bool cpu_globals_initialized;
83a00f60 4569 bool ambiguous = false;
62a48a2a
IM		 4570
4571 if (cpu_globals_initialized) {
4572 return;
4573 }
4574 cpu_globals_initialized = true;
8f961357 4575
f6750e95
EH		 4576 if (!features) {
4577 return;
4578 }
4579
4580 for (featurestr = strtok(features, ",");
685479bd 4581 featurestr;
f6750e95
EH		 4582 featurestr = strtok(NULL, ",")) {
4583 const char *name;
4584 const char *val = NULL;
4585 char *eq = NULL;
cf2887c9 4586 char num[32];
62a48a2a 4587 GlobalProperty *prop;
c6dc6f63 4588
f6750e95 4589 /* Compatibility syntax: */
c6dc6f63 4590 if (featurestr[0] == '+') {
2fae0d96
EH		 4591 plus_features = g_list_append(plus_features,
4592 g_strdup(featurestr + 1));
f6750e95 4593 continue;
c6dc6f63 4594 } else if (featurestr[0] == '-') {
2fae0d96
EH		 4595 minus_features = g_list_append(minus_features,
4596 g_strdup(featurestr + 1));
f6750e95
EH		 4597 continue;
4598 }
4599
4600 eq = strchr(featurestr, '=');
4601 if (eq) {
4602 *eq++ = 0;
4603 val = eq;
c6dc6f63 4604 } else {
f6750e95 4605 val = "on";
a91987c2 4606 }
f6750e95
EH		 4607
4608 feat2prop(featurestr);
4609 name = featurestr;
4610
83a00f60 4611 if (g_list_find_custom(plus_features, name, compare_string)) {
3dc6f869
AF		 4612 warn_report("Ambiguous CPU model string. "
4613 "Don't mix both \"+%s\" and \"%s=%s\"",
4614 name, name, val);
83a00f60
EH		 4615 ambiguous = true;
4616 }
4617 if (g_list_find_custom(minus_features, name, compare_string)) {
3dc6f869
AF		 4618 warn_report("Ambiguous CPU model string. "
4619 "Don't mix both \"-%s\" and \"%s=%s\"",
4620 name, name, val);
83a00f60
EH		 4621 ambiguous = true;
4622 }
4623
f6750e95
EH		 4624 /* Special case: */
4625 if (!strcmp(name, "tsc-freq")) {
f17fd4fd 4626 int ret;
f46bfdbf 4627 uint64_t tsc_freq;
f6750e95 4628
f17fd4fd 4629 ret = qemu_strtosz_metric(val, NULL, &tsc_freq);
f46bfdbf 4630 if (ret < 0 || tsc_freq > INT64_MAX) {
f6750e95
EH		 4631 error_setg(errp, "bad numerical value %s", val);
4632 return;
4633 }
4634 snprintf(num, sizeof(num), "%" PRId64, tsc_freq);
4635 val = num;
4636 name = "tsc-frequency";
c6dc6f63 4637 }
f6750e95 4638
62a48a2a
IM		 4639 prop = g_new0(typeof(*prop), 1);
4640 prop->driver = typename;
4641 prop->property = g_strdup(name);
4642 prop->value = g_strdup(val);
62a48a2a 4643 qdev_prop_register_global(prop);
f6750e95
EH		 4644 }
4645
83a00f60 4646 if (ambiguous) {
3dc6f869
AF		 4647 warn_report("Compatibility of ambiguous CPU model "
4648 "strings won't be kept on future QEMU versions");
83a00f60 4649 }
c6dc6f63
AP		 4650}
4651
245edd0c 4652static void x86_cpu_filter_features(X86CPU *cpu, bool verbose);
b54c9377 4653
5a853fc5
EH		 4654/* Build a list with the name of all features on a feature word array */
4655static void x86_cpu_list_feature_names(FeatureWordArray features,
c3033fd3 4656 strList **list)
5a853fc5 4657{
c3033fd3 4658 strList **tail = list;
5a853fc5 4659 FeatureWord w;
5a853fc5
EH		 4660
4661 for (w = 0; w < FEATURE_WORDS; w++) {
ede146c2 4662 uint64_t filtered = features[w];
5a853fc5 4663 int i;
ede146c2
PB		 4664 for (i = 0; i < 64; i++) {
4665 if (filtered & (1ULL << i)) {
c3033fd3 4666 QAPI_LIST_APPEND(tail, g_strdup(x86_cpu_feature_name(w, i)));
5a853fc5
EH		 4667 }
4668 }
4669 }
4670}
4671
506174bf
EH		 4672static void x86_cpu_get_unavailable_features(Object *obj, Visitor *v,
4673 const char *name, void *opaque,
4674 Error **errp)
4675{
4676 X86CPU *xc = X86_CPU(obj);
4677 strList *result = NULL;
4678
4679 x86_cpu_list_feature_names(xc->filtered_features, &result);
4680 visit_type_strList(v, "unavailable-features", &result, errp);
4681}
4682
b54c9377
EH		 4683/* Check for missing features that may prevent the CPU class from
4684 * running using the current machine and accelerator.
4685 */
4686static void x86_cpu_class_check_missing_features(X86CPUClass *xcc,
c3033fd3 4687 strList **list)
b54c9377 4688{
c3033fd3 4689 strList **tail = list;
b54c9377 4690 X86CPU *xc;
b54c9377 4691 Error *err = NULL;
b54c9377 4692
d6dcc558 4693 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) {
c3033fd3 4694 QAPI_LIST_APPEND(tail, g_strdup("kvm"));
b54c9377
EH		 4695 return;
4696 }
4697
3c75e12e 4698 xc = X86_CPU(object_new_with_class(OBJECT_CLASS(xcc)));
b54c9377 4699
b8d834a0 4700 x86_cpu_expand_features(xc, &err);
b54c9377 4701 if (err) {
b8d834a0 4702 /* Errors at x86_cpu_expand_features should never happen,
b54c9377
EH		 4703 * but in case it does, just report the model as not
4704 * runnable at all using the "type" property.
4705 */
c3033fd3 4706 QAPI_LIST_APPEND(tail, g_strdup("type"));
3aa8203e 4707 error_free(err);
b54c9377
EH		 4708 }
4709
245edd0c 4710 x86_cpu_filter_features(xc, false);
b54c9377 4711
c3033fd3 4712 x86_cpu_list_feature_names(xc->filtered_features, tail);
b54c9377
EH		 4713
4714 object_unref(OBJECT(xc));
4715}
4716
8c3329e5 4717/* Print all cpuid feature names in featureset
c6dc6f63 4718 */
0442428a 4719static void listflags(GList *features)
0856579c 4720{
cc643b1e
DB		 4721 size_t len = 0;
4722 GList *tmp;
4723
4724 for (tmp = features; tmp; tmp = tmp->next) {
4725 const char *name = tmp->data;
4726 if ((len + strlen(name) + 1) >= 75) {
0442428a 4727 qemu_printf("\n");
cc643b1e 4728 len = 0;
c6dc6f63 4729 }
0442428a 4730 qemu_printf("%s%s", len == 0 ? " " : " ", name);
cc643b1e 4731 len += strlen(name) + 1;
8c3329e5 4732 }
0442428a 4733 qemu_printf("\n");
c6dc6f63
AP		 4734}
4735
f48c8837 4736/* Sort alphabetically by type name, respecting X86CPUClass::ordering. */
ee465a3e
EH		 4737static gint x86_cpu_list_compare(gconstpointer a, gconstpointer b)
4738{
4739 ObjectClass *class_a = (ObjectClass *)a;
4740 ObjectClass *class_b = (ObjectClass *)b;
4741 X86CPUClass *cc_a = X86_CPU_CLASS(class_a);
4742 X86CPUClass *cc_b = X86_CPU_CLASS(class_b);
c7dbff4b 4743 int ret;
ee465a3e 4744
f48c8837 4745 if (cc_a->ordering != cc_b->ordering) {
c7dbff4b 4746 ret = cc_a->ordering - cc_b->ordering;
ee465a3e 4747 } else {
88703ce2
EH		 4748 g_autofree char *name_a = x86_cpu_class_get_model_name(cc_a);
4749 g_autofree char *name_b = x86_cpu_class_get_model_name(cc_b);
c7dbff4b 4750 ret = strcmp(name_a, name_b);
ee465a3e 4751 }
c7dbff4b 4752 return ret;
ee465a3e
EH		 4753}
4754
4755static GSList *get_sorted_cpu_model_list(void)
4756{
4757 GSList *list = object_class_get_list(TYPE_X86_CPU, false);
4758 list = g_slist_sort(list, x86_cpu_list_compare);
4759 return list;
4760}
4761
164e779c
EH		 4762static char *x86_cpu_class_get_model_id(X86CPUClass *xc)
4763{
3c75e12e 4764 Object *obj = object_new_with_class(OBJECT_CLASS(xc));
164e779c
EH		 4765 char *r = object_property_get_str(obj, "model-id", &error_abort);
4766 object_unref(obj);
4767 return r;
4768}
4769
0788a56b
EH		 4770static char *x86_cpu_class_get_alias_of(X86CPUClass *cc)
4771{
4772 X86CPUVersion version;
4773
4774 if (!cc->model || !cc->model->is_alias) {
4775 return NULL;
4776 }
4777 version = x86_cpu_model_resolve_version(cc->model);
4778 if (version <= 0) {
4779 return NULL;
4780 }
4781 return x86_cpu_versioned_model_name(cc->model->cpudef, version);
4782}
4783
ee465a3e
EH		 4784static void x86_cpu_list_entry(gpointer data, gpointer user_data)
4785{
4786 ObjectClass *oc = data;
4787 X86CPUClass *cc = X86_CPU_CLASS(oc);
88703ce2
EH		 4788 g_autofree char *name = x86_cpu_class_get_model_name(cc);
4789 g_autofree char *desc = g_strdup(cc->model_description);
4790 g_autofree char *alias_of = x86_cpu_class_get_alias_of(cc);
c63938df 4791 g_autofree char *model_id = x86_cpu_class_get_model_id(cc);
164e779c 4792
0788a56b
EH		 4793 if (!desc && alias_of) {
4794 if (cc->model && cc->model->version == CPU_VERSION_AUTO) {
4795 desc = g_strdup("(alias configured by machine type)");
4796 } else {
4797 desc = g_strdup_printf("(alias of %s)", alias_of);
4798 }
4799 }
c63938df
TX		 4800 if (!desc && cc->model && cc->model->note) {
4801 desc = g_strdup_printf("%s [%s]", model_id, cc->model->note);
4802 }
164e779c 4803 if (!desc) {
c63938df 4804 desc = g_strdup_printf("%s", model_id);
ee465a3e
EH		 4805 }
4806
c63938df 4807 qemu_printf("x86 %-20s %-58s\n", name, desc);
ee465a3e
EH		 4808}
4809
4810/* list available CPU models and flags */
0442428a 4811void x86_cpu_list(void)
c6dc6f63 4812{
cc643b1e 4813 int i, j;
ee465a3e 4814 GSList *list;
cc643b1e 4815 GList *names = NULL;
c6dc6f63 4816
0442428a 4817 qemu_printf("Available CPUs:\n");
ee465a3e 4818 list = get_sorted_cpu_model_list();
0442428a 4819 g_slist_foreach(list, x86_cpu_list_entry, NULL);
ee465a3e 4820 g_slist_free(list);
21ad7789 4821
cc643b1e 4822 names = NULL;
3af60be2
JK		 4823 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) {
4824 FeatureWordInfo *fw = &feature_word_info[i];
ede146c2 4825 for (j = 0; j < 64; j++) {
cc643b1e
DB		 4826 if (fw->feat_names[j]) {
4827 names = g_list_append(names, (gpointer)fw->feat_names[j]);
4828 }
4829 }
3af60be2 4830 }
cc643b1e
DB		 4831
4832 names = g_list_sort(names, (GCompareFunc)strcmp);
4833
0442428a
MA		 4834 qemu_printf("\nRecognized CPUID flags:\n");
4835 listflags(names);
4836 qemu_printf("\n");
cc643b1e 4837 g_list_free(names);
c6dc6f63
AP		 4838}
4839
ee465a3e
EH		 4840static void x86_cpu_definition_entry(gpointer data, gpointer user_data)
4841{
4842 ObjectClass *oc = data;
4843 X86CPUClass *cc = X86_CPU_CLASS(oc);
4844 CpuDefinitionInfoList **cpu_list = user_data;
ee465a3e
EH		 4845 CpuDefinitionInfo *info;
4846
4847 info = g_malloc0(sizeof(*info));
4848 info->name = x86_cpu_class_get_model_name(cc);
b54c9377
EH		 4849 x86_cpu_class_check_missing_features(cc, &info->unavailable_features);
4850 info->has_unavailable_features = true;
8ed877b7 4851 info->q_typename = g_strdup(object_class_get_name(oc));
bd72159d
EH		 4852 info->migration_safe = cc->migration_safe;
4853 info->has_migration_safe = true;
5adbed30 4854 info->q_static = cc->static_model;
61ad65d0
RH		 4855 if (cc->model && cc->model->cpudef->deprecation_note) {
4856 info->deprecated = true;
4857 } else {
4858 info->deprecated = false;
4859 }
0788a56b
EH		 4860 /*
4861 * Old machine types won't report aliases, so that alias translation
4862 * doesn't break compatibility with previous QEMU versions.
4863 */
4864 if (default_cpu_version != CPU_VERSION_LEGACY) {
4865 info->alias_of = x86_cpu_class_get_alias_of(cc);
4866 info->has_alias_of = !!info->alias_of;
4867 }
ee465a3e 4868
54aa3de7 4869 QAPI_LIST_PREPEND(*cpu_list, info);
ee465a3e
EH		 4870}
4871
25a9d6ca 4872CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
e3966126
AL		 4873{
4874 CpuDefinitionInfoList *cpu_list = NULL;
ee465a3e
EH		 4875 GSList *list = get_sorted_cpu_model_list();
4876 g_slist_foreach(list, x86_cpu_definition_entry, &cpu_list);
4877 g_slist_free(list);
e3966126
AL		 4878 return cpu_list;
4879}
4880
ede146c2 4881static uint64_t x86_cpu_get_supported_feature_word(FeatureWord w,
84f1b92f 4882 bool migratable_only)
27418adf
EH		 4883{
4884 FeatureWordInfo *wi = &feature_word_info[w];
ede146c2 4885 uint64_t r = 0;
27418adf 4886
fefb41bf 4887 if (kvm_enabled()) {
07585923
RH		 4888 switch (wi->type) {
4889 case CPUID_FEATURE_WORD:
4890 r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid.eax,
4891 wi->cpuid.ecx,
4892 wi->cpuid.reg);
4893 break;
4894 case MSR_FEATURE_WORD:
d86f9636
RH		 4895 r = kvm_arch_get_supported_msr_feature(kvm_state,
4896 wi->msr.index);
07585923
RH		 4897 break;
4898 }
d6dcc558 4899 } else if (hvf_enabled()) {
07585923
RH		 4900 if (wi->type != CPUID_FEATURE_WORD) {
4901 return 0;
4902 }
4903 r = hvf_get_supported_cpuid(wi->cpuid.eax,
4904 wi->cpuid.ecx,
4905 wi->cpuid.reg);
fefb41bf 4906 } else if (tcg_enabled()) {
84f1b92f 4907 r = wi->tcg_features;
fefb41bf
EH		 4908 } else {
4909 return ~0;
4910 }
5ea9e9e2
PB		 4911#ifndef TARGET_X86_64
4912 if (w == FEAT_8000_0001_EDX) {
4913 r &= ~CPUID_EXT2_LM;
4914 }
4915#endif
84f1b92f
EH		 4916 if (migratable_only) {
4917 r &= x86_cpu_get_migratable_flags(w);
4918 }
4919 return r;
27418adf
EH		 4920}
4921
f5cc5a5c 4922void x86_cpu_apply_props(X86CPU *cpu, PropValue *props)
5114e842
EH		 4923{
4924 PropValue *pv;
4925 for (pv = props; pv->prop; pv++) {
4926 if (!pv->value) {
4927 continue;
4928 }
5325cc34 4929 object_property_parse(OBJECT(cpu), pv->prop, pv->value,
5114e842
EH		 4930 &error_abort);
4931 }
4932}
4933
dcafd1ef
EH		 4934/* Apply properties for the CPU model version specified in model */
4935static void x86_cpu_apply_version_props(X86CPU *cpu, X86CPUModel *model)
4936{
4937 const X86CPUVersionDefinition *vdef;
4938 X86CPUVersion version = x86_cpu_model_resolve_version(model);
4939
4940 if (version == CPU_VERSION_LEGACY) {
4941 return;
4942 }
4943
4944 for (vdef = x86_cpu_def_get_versions(model->cpudef); vdef->version; vdef++) {
4945 PropValue *p;
4946
4947 for (p = vdef->props; p && p->prop; p++) {
5325cc34 4948 object_property_parse(OBJECT(cpu), p->prop, p->value,
dcafd1ef
EH		 4949 &error_abort);
4950 }
4951
4952 if (vdef->version == version) {
4953 break;
4954 }
4955 }
4956
4957 /*
4958 * If we reached the end of the list, version number was invalid
4959 */
4960 assert(vdef->version == version);
4961}
4962
f99fd7ca 4963/* Load data from X86CPUDefinition into a X86CPU object
c080e30e 4964 */
49e2fa85 4965static void x86_cpu_load_model(X86CPU *cpu, X86CPUModel *model)
c6dc6f63 4966{
e11fd689 4967 const X86CPUDefinition *def = model->cpudef;
61dcd775 4968 CPUX86State *env = &cpu->env;
e1c224b4 4969 FeatureWord w;
c6dc6f63 4970
f99fd7ca
EH		 4971 /*NOTE: any property set by this function should be returned by
4972 * x86_cpu_static_props(), so static expansion of
4973 * query-cpu-model-expansion is always complete.
4974 */
4975
c39c0edf 4976 /* CPU models only set _minimum_ values for level/xlevel: */
5325cc34 4977 object_property_set_uint(OBJECT(cpu), "min-level", def->level,
49e2fa85 4978 &error_abort);
5325cc34 4979 object_property_set_uint(OBJECT(cpu), "min-xlevel", def->xlevel,
49e2fa85
MA		 4980 &error_abort);
4981
5325cc34
MA		 4982 object_property_set_int(OBJECT(cpu), "family", def->family, &error_abort);
4983 object_property_set_int(OBJECT(cpu), "model", def->model, &error_abort);
4984 object_property_set_int(OBJECT(cpu), "stepping", def->stepping,
49e2fa85 4985 &error_abort);
5325cc34 4986 object_property_set_str(OBJECT(cpu), "model-id", def->model_id,
49e2fa85 4987 &error_abort);
e1c224b4
EH		 4988 for (w = 0; w < FEATURE_WORDS; w++) {
4989 env->features[w] = def->features[w];
4990 }
82beb536 4991
a9f27ea9
EH		 4992 /* legacy-cache defaults to 'off' if CPU model provides cache info */
4993 cpu->legacy_cache = !def->cache_info;
ab8f992e 4994
82beb536 4995 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR;
7c08db30
EH		 4996
4997 /* sysenter isn't supported in compatibility mode on AMD,
4998 * syscall isn't supported in compatibility mode on Intel.
4999 * Normally we advertise the actual CPU vendor, but you can
5000 * override this using the 'vendor' property if you want to use
5001 * KVM's sysenter/syscall emulation in compatibility mode and
5002 * when doing cross vendor migration
5003 */
7c08db30 5004
f5cc5a5c
CF		 5005 /*
5006 * vendor property is set here but then overloaded with the
5007 * host cpu vendor for KVM and HVF.
5008 */
5009 object_property_set_str(OBJECT(cpu), "vendor", def->vendor, &error_abort);
7c08db30 5010
dcafd1ef 5011 x86_cpu_apply_version_props(cpu, model);
1f43671a
XL		 5012
5013 /*
5014 * Properties in versioned CPU model are not user specified features.
5015 * We can simply clear env->user_features here since it will be filled later
5016 * in x86_cpu_expand_features() based on plus_features and minus_features.
5017 */
5018 memset(&env->user_features, 0, sizeof(env->user_features));
c6dc6f63
AP		 5019}
5020
00fcd100
AB		 5021static gchar *x86_gdb_arch_name(CPUState *cs)
5022{
5023#ifdef TARGET_X86_64
5024 return g_strdup("i386:x86-64");
5025#else
5026 return g_strdup("i386");
5027#endif
5028}
5029
d940ee9b
EH		 5030static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data)
5031{
dcafd1ef 5032 X86CPUModel *model = data;
d940ee9b 5033 X86CPUClass *xcc = X86_CPU_CLASS(oc);
61ad65d0 5034 CPUClass *cc = CPU_CLASS(oc);
d940ee9b 5035
dcafd1ef 5036 xcc->model = model;
bd72159d 5037 xcc->migration_safe = true;
61ad65d0 5038 cc->deprecation_note = model->cpudef->deprecation_note;
d940ee9b
EH		 5039}
5040
dcafd1ef 5041static void x86_register_cpu_model_type(const char *name, X86CPUModel *model)
d940ee9b 5042{
88703ce2 5043 g_autofree char *typename = x86_cpu_type_name(name);
d940ee9b
EH		 5044 TypeInfo ti = {
5045 .name = typename,
5046 .parent = TYPE_X86_CPU,
5047 .class_init = x86_cpu_cpudef_class_init,
dcafd1ef 5048 .class_data = model,
d940ee9b
EH		 5049 };
5050
dcafd1ef 5051 type_register(&ti);
dcafd1ef
EH		 5052}
5053
e11fd689 5054static void x86_register_cpudef_types(const X86CPUDefinition *def)
dcafd1ef
EH		 5055{
5056 X86CPUModel *m;
5057 const X86CPUVersionDefinition *vdef;
dcafd1ef 5058
2a923a29
EH		 5059 /* AMD aliases are handled at runtime based on CPUID vendor, so
5060 * they shouldn't be set on the CPU model table.
5061 */
5062 assert(!(def->features[FEAT_8000_0001_EDX] & CPUID_EXT2_AMD_ALIASES));
807e9869
EH		 5063 /* catch mistakes instead of silently truncating model_id when too long */
5064 assert(def->model_id && strlen(def->model_id) <= 48);
5065
dcafd1ef
EH		 5066 /* Unversioned model: */
5067 m = g_new0(X86CPUModel, 1);
5068 m->cpudef = def;
0788a56b
EH		 5069 m->version = CPU_VERSION_AUTO;
5070 m->is_alias = true;
dcafd1ef
EH		 5071 x86_register_cpu_model_type(def->name, m);
5072
5073 /* Versioned models: */
5074
5075 for (vdef = x86_cpu_def_get_versions(def); vdef->version; vdef++) {
5076 X86CPUModel *m = g_new0(X86CPUModel, 1);
88703ce2
EH		 5077 g_autofree char *name =
5078 x86_cpu_versioned_model_name(def, vdef->version);
dcafd1ef
EH		 5079 m->cpudef = def;
5080 m->version = vdef->version;
c63938df 5081 m->note = vdef->note;
dcafd1ef 5082 x86_register_cpu_model_type(name, m);
53db89d9
EH		 5083
5084 if (vdef->alias) {
5085 X86CPUModel *am = g_new0(X86CPUModel, 1);
5086 am->cpudef = def;
5087 am->version = vdef->version;
0788a56b 5088 am->is_alias = true;
53db89d9
EH		 5089 x86_register_cpu_model_type(vdef->alias, am);
5090 }
dcafd1ef 5091 }
2a923a29 5092
d940ee9b
EH		 5093}
5094
c6dc6f63
AP		 5095void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
5096 uint32_t *eax, uint32_t *ebx,
5097 uint32_t *ecx, uint32_t *edx)
5098{
6aa9e42f
RH		 5099 X86CPU *cpu = env_archcpu(env);
5100 CPUState *cs = env_cpu(env);
d65af288 5101 uint32_t die_offset;
4ed3d478 5102 uint32_t limit;
1ce36bfe 5103 uint32_t signature[3];
f20dec0b
BM		 5104 X86CPUTopoInfo topo_info;
5105
5106 topo_info.dies_per_pkg = env->nr_dies;
5107 topo_info.cores_per_die = cs->nr_cores;
5108 topo_info.threads_per_core = cs->nr_threads;
a60f24b5 5109
4ed3d478
DB		 5110 /* Calculate & apply limits for different index ranges */
5111 if (index >= 0xC0000000) {
5112 limit = env->cpuid_xlevel2;
5113 } else if (index >= 0x80000000) {
5114 limit = env->cpuid_xlevel;
1ce36bfe
DB		 5115 } else if (index >= 0x40000000) {
5116 limit = 0x40000001;
c6dc6f63 5117 } else {
4ed3d478
DB		 5118 limit = env->cpuid_level;
5119 }
5120
5121 if (index > limit) {
5122 /* Intel documentation states that invalid EAX input will
5123 * return the same information as EAX=cpuid_level
5124 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
5125 */
5126 index = env->cpuid_level;
c6dc6f63
AP		 5127 }
5128
5129 switch(index) {
5130 case 0:
5131 *eax = env->cpuid_level;
5eb2f7a4
EH		 5132 *ebx = env->cpuid_vendor1;
5133 *edx = env->cpuid_vendor2;
5134 *ecx = env->cpuid_vendor3;
c6dc6f63
AP		 5135 break;
5136 case 1:
5137 *eax = env->cpuid_version;
7e72a45c
EH		 5138 *ebx = (cpu->apic_id << 24) |
5139 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
0514ef2f 5140 *ecx = env->features[FEAT_1_ECX];
19dc85db
RH		 5141 if ((*ecx & CPUID_EXT_XSAVE) && (env->cr[4] & CR4_OSXSAVE_MASK)) {
5142 *ecx |= CPUID_EXT_OSXSAVE;
5143 }
0514ef2f 5144 *edx = env->features[FEAT_1_EDX];
ce3960eb
AF		 5145 if (cs->nr_cores * cs->nr_threads > 1) {
5146 *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
19dc85db 5147 *edx |= CPUID_HT;
c6dc6f63 5148 }
ea39f9b6
LX		 5149 if (!cpu->enable_pmu) {
5150 *ecx &= ~CPUID_EXT_PDCM;
5151 }
c6dc6f63
AP		 5152 break;
5153 case 2:
5154 /* cache info: needed for Pentium Pro compatibility */
787aaf57
BC		 5155 if (cpu->cache_info_passthrough) {
5156 host_cpuid(index, 0, eax, ebx, ecx, edx);
5157 break;
5158 }
5e891bf8 5159 *eax = 1; /* Number of CPUID[EAX=2] calls required */
c6dc6f63 5160 *ebx = 0;
14c985cf
LM		 5161 if (!cpu->enable_l3_cache) {
5162 *ecx = 0;
5163 } else {
a9f27ea9 5164 *ecx = cpuid2_cache_descriptor(env->cache_info_cpuid2.l3_cache);
14c985cf 5165 }
a9f27ea9
EH		 5166 *edx = (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1d_cache) << 16) |
5167 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1i_cache) << 8) |
5168 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l2_cache));
c6dc6f63
AP		 5169 break;
5170 case 4:
5171 /* cache info: needed for Core compatibility */
787aaf57
BC		 5172 if (cpu->cache_info_passthrough) {
5173 host_cpuid(index, count, eax, ebx, ecx, edx);
7e3482f8 5174 /* QEMU gives out its own APIC IDs, never pass down bits 31..26. */
76c2975a 5175 *eax &= ~0xFC000000;
7e3482f8
EH		 5176 if ((*eax & 31) && cs->nr_cores > 1) {
5177 *eax |= (cs->nr_cores - 1) << 26;
5178 }
c6dc6f63 5179 } else {
2f7a21c4 5180 *eax = 0;
76c2975a 5181 switch (count) {
c6dc6f63 5182 case 0: /* L1 dcache info */
a9f27ea9
EH		 5183 encode_cache_cpuid4(env->cache_info_cpuid4.l1d_cache,
5184 1, cs->nr_cores,
7e3482f8 5185 eax, ebx, ecx, edx);
c6dc6f63
AP		 5186 break;
5187 case 1: /* L1 icache info */
a9f27ea9
EH		 5188 encode_cache_cpuid4(env->cache_info_cpuid4.l1i_cache,
5189 1, cs->nr_cores,
7e3482f8 5190 eax, ebx, ecx, edx);
c6dc6f63
AP		 5191 break;
5192 case 2: /* L2 cache info */
a9f27ea9
EH		 5193 encode_cache_cpuid4(env->cache_info_cpuid4.l2_cache,
5194 cs->nr_threads, cs->nr_cores,
7e3482f8 5195 eax, ebx, ecx, edx);
c6dc6f63 5196 break;
14c985cf 5197 case 3: /* L3 cache info */
f20dec0b 5198 die_offset = apicid_die_offset(&topo_info);
7e3482f8 5199 if (cpu->enable_l3_cache) {
a9f27ea9 5200 encode_cache_cpuid4(env->cache_info_cpuid4.l3_cache,
d65af288 5201 (1 << die_offset), cs->nr_cores,
7e3482f8 5202 eax, ebx, ecx, edx);
14c985cf
LM		 5203 break;
5204 }
7e3482f8 5205 /* fall through */
c6dc6f63 5206 default: /* end of info */
7e3482f8 5207 *eax = *ebx = *ecx = *edx = 0;
c6dc6f63 5208 break;
76c2975a
PB		 5209 }
5210 }
c6dc6f63
AP		 5211 break;
5212 case 5:
2266d443
MT		 5213 /* MONITOR/MWAIT Leaf */
5214 *eax = cpu->mwait.eax; /* Smallest monitor-line size in bytes */
5215 *ebx = cpu->mwait.ebx; /* Largest monitor-line size in bytes */
5216 *ecx = cpu->mwait.ecx; /* flags */
5217 *edx = cpu->mwait.edx; /* mwait substates */
c6dc6f63
AP		 5218 break;
5219 case 6:
5220 /* Thermal and Power Leaf */
28b8e4d0 5221 *eax = env->features[FEAT_6_EAX];
c6dc6f63
AP		 5222 *ebx = 0;
5223 *ecx = 0;
5224 *edx = 0;
5225 break;
f7911686 5226 case 7:
13526728
EH		 5227 /* Structured Extended Feature Flags Enumeration Leaf */
5228 if (count == 0) {
80db491d
JL		 5229 /* Maximum ECX value for sub-leaves */
5230 *eax = env->cpuid_level_func7;
0514ef2f 5231 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */
f74eefe0 5232 *ecx = env->features[FEAT_7_0_ECX]; /* Feature flags */
0f70ed47
PB		 5233 if ((*ecx & CPUID_7_0_ECX_PKU) && env->cr[4] & CR4_PKE_MASK) {
5234 *ecx |= CPUID_7_0_ECX_OSPKE;
5235 }
95ea69fb 5236 *edx = env->features[FEAT_7_0_EDX]; /* Feature flags */
80db491d
JL		 5237 } else if (count == 1) {
5238 *eax = env->features[FEAT_7_1_EAX];
5239 *ebx = 0;
5240 *ecx = 0;
5241 *edx = 0;
f7911686
YW		 5242 } else {
5243 *eax = 0;
5244 *ebx = 0;
5245 *ecx = 0;
5246 *edx = 0;
5247 }
5248 break;
c6dc6f63
AP		 5249 case 9:
5250 /* Direct Cache Access Information Leaf */
5251 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
5252 *ebx = 0;
5253 *ecx = 0;
5254 *edx = 0;
5255 break;
5256 case 0xA:
5257 /* Architectural Performance Monitoring Leaf */
9337e3b6 5258 if (kvm_enabled() && cpu->enable_pmu) {
a60f24b5 5259 KVMState *s = cs->kvm_state;
a0fa8208
GN		 5260
5261 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
5262 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
5263 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
5264 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
d6dcc558
SAGDR		 5265 } else if (hvf_enabled() && cpu->enable_pmu) {
5266 *eax = hvf_get_supported_cpuid(0xA, count, R_EAX);
5267 *ebx = hvf_get_supported_cpuid(0xA, count, R_EBX);
5268 *ecx = hvf_get_supported_cpuid(0xA, count, R_ECX);
5269 *edx = hvf_get_supported_cpuid(0xA, count, R_EDX);
a0fa8208
GN		 5270 } else {
5271 *eax = 0;
5272 *ebx = 0;
5273 *ecx = 0;
5274 *edx = 0;
5275 }
c6dc6f63 5276 break;
5232d00a
RK		 5277 case 0xB:
5278 /* Extended Topology Enumeration Leaf */
5279 if (!cpu->enable_cpuid_0xb) {
5280 *eax = *ebx = *ecx = *edx = 0;
5281 break;
5282 }
5283
5284 *ecx = count & 0xff;
5285 *edx = cpu->apic_id;
5286
5287 switch (count) {
5288 case 0:
f20dec0b 5289 *eax = apicid_core_offset(&topo_info);
eab60fb9 5290 *ebx = cs->nr_threads;
5232d00a
RK		 5291 *ecx |= CPUID_TOPOLOGY_LEVEL_SMT;
5292 break;
5293 case 1:
fb49865d 5294 *eax = apicid_pkg_offset(&topo_info);
eab60fb9 5295 *ebx = cs->nr_cores * cs->nr_threads;
5232d00a
RK		 5296 *ecx |= CPUID_TOPOLOGY_LEVEL_CORE;
5297 break;
5298 default:
5299 *eax = 0;
5300 *ebx = 0;
5301 *ecx |= CPUID_TOPOLOGY_LEVEL_INVALID;
5302 }
5303
a94e1428
LX		 5304 assert(!(*eax & ~0x1f));
5305 *ebx &= 0xffff; /* The count doesn't need to be reliable. */
5306 break;
5307 case 0x1F:
5308 /* V2 Extended Topology Enumeration Leaf */
5309 if (env->nr_dies < 2) {
5310 *eax = *ebx = *ecx = *edx = 0;
5311 break;
5312 }
5313
5314 *ecx = count & 0xff;
5315 *edx = cpu->apic_id;
5316 switch (count) {
5317 case 0:
f20dec0b 5318 *eax = apicid_core_offset(&topo_info);
a94e1428
LX		 5319 *ebx = cs->nr_threads;
5320 *ecx |= CPUID_TOPOLOGY_LEVEL_SMT;
5321 break;
5322 case 1:
f20dec0b 5323 *eax = apicid_die_offset(&topo_info);
a94e1428
LX		 5324 *ebx = cs->nr_cores * cs->nr_threads;
5325 *ecx |= CPUID_TOPOLOGY_LEVEL_CORE;
5326 break;
5327 case 2:
fb49865d 5328 *eax = apicid_pkg_offset(&topo_info);
a94e1428
LX		 5329 *ebx = env->nr_dies * cs->nr_cores * cs->nr_threads;
5330 *ecx |= CPUID_TOPOLOGY_LEVEL_DIE;
5331 break;
5332 default:
5333 *eax = 0;
5334 *ebx = 0;
5335 *ecx |= CPUID_TOPOLOGY_LEVEL_INVALID;
5336 }
5232d00a
RK		 5337 assert(!(*eax & ~0x1f));
5338 *ebx &= 0xffff; /* The count doesn't need to be reliable. */
5339 break;
2560f19f 5340 case 0xD: {
51e49430 5341 /* Processor Extended State */
2560f19f
PB		 5342 *eax = 0;
5343 *ebx = 0;
5344 *ecx = 0;
5345 *edx = 0;
19dc85db 5346 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
51e49430
SY		 5347 break;
5348 }
4928cd6d 5349
2560f19f 5350 if (count == 0) {
96193c22
EH		 5351 *ecx = xsave_area_size(x86_cpu_xsave_components(cpu));
5352 *eax = env->features[FEAT_XSAVE_COMP_LO];
5353 *edx = env->features[FEAT_XSAVE_COMP_HI];
76ecd7a5
BS		 5354 /*
5355 * The initial value of xcr0 and ebx == 0, On host without kvm
5356 * commit 412a3c41(e.g., CentOS 6), the ebx's value always == 0
5357 * even through guest update xcr0, this will crash some legacy guest
5358 * (e.g., CentOS 6), So set ebx == ecx to workaroud it.
5359 */
5360 *ebx = kvm_enabled() ? *ecx : xsave_area_size(env->xcr0);
2560f19f 5361 } else if (count == 1) {
0bb0b2d2 5362 *eax = env->features[FEAT_XSAVE];
f4f1110e 5363 } else if (count < ARRAY_SIZE(x86_ext_save_areas)) {
96193c22
EH		 5364 if ((x86_cpu_xsave_components(cpu) >> count) & 1) {
5365 const ExtSaveArea *esa = &x86_ext_save_areas[count];
33f373d7
LJ		 5366 *eax = esa->size;
5367 *ebx = esa->offset;
2560f19f 5368 }
51e49430
SY		 5369 }
5370 break;
2560f19f 5371 }
e37a5c7f
CP		 5372 case 0x14: {
5373 /* Intel Processor Trace Enumeration */
5374 *eax = 0;
5375 *ebx = 0;
5376 *ecx = 0;
5377 *edx = 0;
5378 if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) ||
5379 !kvm_enabled()) {
5380 break;
5381 }
5382
5383 if (count == 0) {
5384 *eax = INTEL_PT_MAX_SUBLEAF;
5385 *ebx = INTEL_PT_MINIMAL_EBX;
5386 *ecx = INTEL_PT_MINIMAL_ECX;
d1615ea5
LK		 5387 if (env->features[FEAT_14_0_ECX] & CPUID_14_0_ECX_LIP) {
5388 *ecx |= CPUID_14_0_ECX_LIP;
5389 }
e37a5c7f
CP		 5390 } else if (count == 1) {
5391 *eax = INTEL_PT_MTC_BITMAP | INTEL_PT_ADDR_RANGES_NUM;
5392 *ebx = INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP;
5393 }
5394 break;
5395 }
1ce36bfe
DB		 5396 case 0x40000000:
5397 /*
5398 * CPUID code in kvm_arch_init_vcpu() ignores stuff
5399 * set here, but we restrict to TCG none the less.
5400 */
5401 if (tcg_enabled() && cpu->expose_tcg) {
5402 memcpy(signature, "TCGTCGTCGTCG", 12);
5403 *eax = 0x40000001;
5404 *ebx = signature[0];
5405 *ecx = signature[1];
5406 *edx = signature[2];
5407 } else {
5408 *eax = 0;
5409 *ebx = 0;
5410 *ecx = 0;
5411 *edx = 0;
5412 }
5413 break;
5414 case 0x40000001:
5415 *eax = 0;
5416 *ebx = 0;
5417 *ecx = 0;
5418 *edx = 0;
5419 break;
c6dc6f63
AP		 5420 case 0x80000000:
5421 *eax = env->cpuid_xlevel;
5422 *ebx = env->cpuid_vendor1;
5423 *edx = env->cpuid_vendor2;
5424 *ecx = env->cpuid_vendor3;
5425 break;
5426 case 0x80000001:
5427 *eax = env->cpuid_version;
5428 *ebx = 0;
0514ef2f
EH		 5429 *ecx = env->features[FEAT_8000_0001_ECX];
5430 *edx = env->features[FEAT_8000_0001_EDX];
c6dc6f63
AP		 5431
5432 /* The Linux kernel checks for the CMPLegacy bit and
5433 * discards multiple thread information if it is set.
cb8d4c8f 5434 * So don't set it here for Intel to make Linux guests happy.
c6dc6f63 5435 */
ce3960eb 5436 if (cs->nr_cores * cs->nr_threads > 1) {
5eb2f7a4
EH		 5437 if (env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1 ||
5438 env->cpuid_vendor2 != CPUID_VENDOR_INTEL_2 ||
5439 env->cpuid_vendor3 != CPUID_VENDOR_INTEL_3) {
c6dc6f63
AP		 5440 *ecx |= 1 << 1; /* CmpLegacy bit */
5441 }
5442 }
c6dc6f63
AP		 5443 break;
5444 case 0x80000002:
5445 case 0x80000003:
5446 case 0x80000004:
5447 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
5448 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
5449 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
5450 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
5451 break;
5452 case 0x80000005:
5453 /* cache info (L1 cache) */
787aaf57
BC		 5454 if (cpu->cache_info_passthrough) {
5455 host_cpuid(index, 0, eax, ebx, ecx, edx);
5456 break;
5457 }
78ee6bd0 5458 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) |
5e891bf8 5459 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES);
78ee6bd0 5460 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) |
5e891bf8 5461 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES);
a9f27ea9
EH		 5462 *ecx = encode_cache_cpuid80000005(env->cache_info_amd.l1d_cache);
5463 *edx = encode_cache_cpuid80000005(env->cache_info_amd.l1i_cache);
c6dc6f63
AP		 5464 break;
5465 case 0x80000006:
5466 /* cache info (L2 cache) */
787aaf57
BC		 5467 if (cpu->cache_info_passthrough) {
5468 host_cpuid(index, 0, eax, ebx, ecx, edx);
5469 break;
5470 }
78ee6bd0
PMD		 5471 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) |
5472 (L2_DTLB_2M_ENTRIES << 16) |
5473 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) |
5e891bf8 5474 (L2_ITLB_2M_ENTRIES);
78ee6bd0
PMD		 5475 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) |
5476 (L2_DTLB_4K_ENTRIES << 16) |
5477 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) |
5e891bf8 5478 (L2_ITLB_4K_ENTRIES);
a9f27ea9
EH		 5479 encode_cache_cpuid80000006(env->cache_info_amd.l2_cache,
5480 cpu->enable_l3_cache ?
5481 env->cache_info_amd.l3_cache : NULL,
5482 ecx, edx);
c6dc6f63 5483 break;
303752a9
MT		 5484 case 0x80000007:
5485 *eax = 0;
5486 *ebx = 0;
5487 *ecx = 0;
5488 *edx = env->features[FEAT_8000_0007_EDX];
5489 break;
c6dc6f63
AP		 5490 case 0x80000008:
5491 /* virtual & phys address size in low 2 bytes. */
0514ef2f 5492 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
6c7c3c21
KS		 5493 /* 64 bit processor */
5494 *eax = cpu->phys_bits; /* configurable physical bits */
5495 if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_LA57) {
5496 *eax |= 0x00003900; /* 57 bits virtual */
5497 } else {
5498 *eax |= 0x00003000; /* 48 bits virtual */
5499 }
c6dc6f63 5500 } else {
af45907a 5501 *eax = cpu->phys_bits;
c6dc6f63 5502 }
1b3420e1 5503 *ebx = env->features[FEAT_8000_0008_EBX];
ce3960eb 5504 if (cs->nr_cores * cs->nr_threads > 1) {
cac9edfc
BM		 5505 /*
5506 * Bits 15:12 is "The number of bits in the initial
5507 * Core::X86::Apic::ApicId[ApicId] value that indicate
fb49865d 5508 * thread ID within a package".
cac9edfc
BM		 5509 * Bits 7:0 is "The number of threads in the package is NC+1"
5510 */
fb49865d 5511 *ecx = (apicid_pkg_offset(&topo_info) << 12) |
cac9edfc
BM		 5512 ((cs->nr_cores * cs->nr_threads) - 1);
5513 } else {
5514 *ecx = 0;
c6dc6f63 5515 }
cac9edfc 5516 *edx = 0;
c6dc6f63
AP		 5517 break;
5518 case 0x8000000A:
0514ef2f 5519 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
9f3fb565
EH		 5520 *eax = 0x00000001; /* SVM Revision */
5521 *ebx = 0x00000010; /* nr of ASIDs */
5522 *ecx = 0;
0514ef2f 5523 *edx = env->features[FEAT_SVM]; /* optional features */
9f3fb565
EH		 5524 } else {
5525 *eax = 0;
5526 *ebx = 0;
5527 *ecx = 0;
5528 *edx = 0;
5529 }
c6dc6f63 5530 break;
8f4202fb
BM		 5531 case 0x8000001D:
5532 *eax = 0;
a4e0b436
SL		 5533 if (cpu->cache_info_passthrough) {
5534 host_cpuid(index, count, eax, ebx, ecx, edx);
5535 break;
5536 }
8f4202fb
BM		 5537 switch (count) {
5538 case 0: /* L1 dcache info */
2f084d1e
BM		 5539 encode_cache_cpuid8000001d(env->cache_info_amd.l1d_cache,
5540 &topo_info, eax, ebx, ecx, edx);
8f4202fb
BM		 5541 break;
5542 case 1: /* L1 icache info */
2f084d1e
BM		 5543 encode_cache_cpuid8000001d(env->cache_info_amd.l1i_cache,
5544 &topo_info, eax, ebx, ecx, edx);
8f4202fb
BM		 5545 break;
5546 case 2: /* L2 cache info */
2f084d1e
BM		 5547 encode_cache_cpuid8000001d(env->cache_info_amd.l2_cache,
5548 &topo_info, eax, ebx, ecx, edx);
8f4202fb
BM		 5549 break;
5550 case 3: /* L3 cache info */
2f084d1e
BM		 5551 encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache,
5552 &topo_info, eax, ebx, ecx, edx);
8f4202fb
BM		 5553 break;
5554 default: /* end of info */
5555 *eax = *ebx = *ecx = *edx = 0;
5556 break;
5557 }
5558 break;
ed78467a 5559 case 0x8000001E:
35ac5dfb
BM		 5560 if (cpu->core_id <= 255) {
5561 encode_topo_cpuid8000001e(cpu, &topo_info, eax, ebx, ecx, edx);
5562 } else {
5563 *eax = 0;
5564 *ebx = 0;
5565 *ecx = 0;
5566 *edx = 0;
5567 }
ed78467a 5568 break;
b3baa152
BW		 5569 case 0xC0000000:
5570 *eax = env->cpuid_xlevel2;
5571 *ebx = 0;
5572 *ecx = 0;
5573 *edx = 0;
5574 break;
5575 case 0xC0000001:
5576 /* Support for VIA CPU's CPUID instruction */
5577 *eax = env->cpuid_version;
5578 *ebx = 0;
5579 *ecx = 0;
0514ef2f 5580 *edx = env->features[FEAT_C000_0001_EDX];
b3baa152
BW		 5581 break;
5582 case 0xC0000002:
5583 case 0xC0000003:
5584 case 0xC0000004:
5585 /* Reserved for the future, and now filled with zero */
5586 *eax = 0;
5587 *ebx = 0;
5588 *ecx = 0;
5589 *edx = 0;
5590 break;
6cb8f2a6
BS		 5591 case 0x8000001F:
5592 *eax = sev_enabled() ? 0x2 : 0;
6b98e96f 5593 *eax |= sev_es_enabled() ? 0x8 : 0;
6cb8f2a6
BS		 5594 *ebx = sev_get_cbit_position();
5595 *ebx |= sev_get_reduced_phys_bits() << 6;
5596 *ecx = 0;
5597 *edx = 0;
5598 break;
c6dc6f63
AP		 5599 default:
5600 /* reserved values: zero */
5601 *eax = 0;
5602 *ebx = 0;
5603 *ecx = 0;
5604 *edx = 0;
5605 break;
5606 }
5607}
5fd2087a 5608
781c67ca 5609static void x86_cpu_reset(DeviceState *dev)
5fd2087a 5610{
781c67ca 5611 CPUState *s = CPU(dev);
5fd2087a
AF		 5612 X86CPU *cpu = X86_CPU(s);
5613 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
5614 CPUX86State *env = &cpu->env;
a114d25d
RH		 5615 target_ulong cr4;
5616 uint64_t xcr0;
c1958aea
AF		 5617 int i;
5618
781c67ca 5619 xcc->parent_reset(dev);
5fd2087a 5620
5e992a8e 5621 memset(env, 0, offsetof(CPUX86State, end_reset_fields));
c1958aea 5622
c1958aea
AF		 5623 env->old_exception = -1;
5624
5625 /* init to reset state */
5626
c1958aea 5627 env->hflags2 |= HF2_GIF_MASK;
b16c0e20 5628 env->hflags &= ~HF_GUEST_MASK;
c1958aea
AF		 5629
5630 cpu_x86_update_cr0(env, 0x60000010);
5631 env->a20_mask = ~0x0;
5632 env->smbase = 0x30000;
e13713db 5633 env->msr_smi_count = 0;
c1958aea
AF		 5634
5635 env->idt.limit = 0xffff;
5636 env->gdt.limit = 0xffff;
5637 env->ldt.limit = 0xffff;
5638 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
5639 env->tr.limit = 0xffff;
5640 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
5641
5642 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
5643 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
5644 DESC_R_MASK | DESC_A_MASK);
5645 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
5646 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
5647 DESC_A_MASK);
5648 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
5649 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
5650 DESC_A_MASK);
5651 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
5652 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
5653 DESC_A_MASK);
5654 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
5655 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
5656 DESC_A_MASK);
5657 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
5658 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
5659 DESC_A_MASK);
5660
5661 env->eip = 0xfff0;
5662 env->regs[R_EDX] = env->cpuid_version;
5663
5664 env->eflags = 0x2;
5665
5666 /* FPU init */
5667 for (i = 0; i < 8; i++) {
5668 env->fptags[i] = 1;
5669 }
5bde1407 5670 cpu_set_fpuc(env, 0x37f);
c1958aea
AF		 5671
5672 env->mxcsr = 0x1f80;
a114d25d
RH		 5673 /* All units are in INIT state. */
5674 env->xstate_bv = 0;
c1958aea
AF		 5675
5676 env->pat = 0x0007040600070406ULL;
5677 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
4cfd7bab
WL		 5678 if (env->features[FEAT_1_ECX] & CPUID_EXT_MONITOR) {
5679 env->msr_ia32_misc_enable |= MSR_IA32_MISC_ENABLE_MWAIT;
5680 }
c1958aea
AF		 5681
5682 memset(env->dr, 0, sizeof(env->dr));
5683 env->dr[6] = DR6_FIXED_1;
5684 env->dr[7] = DR7_FIXED_1;
b3310ab3 5685 cpu_breakpoint_remove_all(s, BP_CPU);
75a34036 5686 cpu_watchpoint_remove_all(s, BP_CPU);
dd673288 5687
a114d25d 5688 cr4 = 0;
cfc3b074 5689 xcr0 = XSTATE_FP_MASK;
a114d25d
RH		 5690
5691#ifdef CONFIG_USER_ONLY
5692 /* Enable all the features for user-mode. */
5693 if (env->features[FEAT_1_EDX] & CPUID_SSE) {
cfc3b074 5694 xcr0 |= XSTATE_SSE_MASK;
a114d25d 5695 }
0f70ed47
PB		 5696 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
5697 const ExtSaveArea *esa = &x86_ext_save_areas[i];
9646f492 5698 if (env->features[esa->feature] & esa->bits) {
0f70ed47
PB		 5699 xcr0 |= 1ull << i;
5700 }
a114d25d 5701 }
0f70ed47 5702
a114d25d
RH		 5703 if (env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) {
5704 cr4 |= CR4_OSFXSR_MASK | CR4_OSXSAVE_MASK;
5705 }
07929f2a
RH		 5706 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE) {
5707 cr4 |= CR4_FSGSBASE_MASK;
5708 }
a114d25d
RH		 5709#endif
5710
5711 env->xcr0 = xcr0;
5712 cpu_x86_update_cr4(env, cr4);
0522604b 5713
9db2efd9
AW		 5714 /*
5715 * SDM 11.11.5 requires:
5716 * - IA32_MTRR_DEF_TYPE MSR.E = 0
5717 * - IA32_MTRR_PHYSMASKn.V = 0
5718 * All other bits are undefined. For simplification, zero it all.
5719 */
5720 env->mtrr_deftype = 0;
5721 memset(env->mtrr_var, 0, sizeof(env->mtrr_var));
5722 memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed));
5723
b7394c83 5724 env->interrupt_injected = -1;
fd13f23b
LA		 5725 env->exception_nr = -1;
5726 env->exception_pending = 0;
5727 env->exception_injected = 0;
5728 env->exception_has_payload = false;
5729 env->exception_payload = 0;
b7394c83 5730 env->nmi_injected = false;
dd673288
IM		 5731#if !defined(CONFIG_USER_ONLY)
5732 /* We hard-wire the BSP to the first CPU. */
9cb11fd7 5733 apic_designate_bsp(cpu->apic_state, s->cpu_index == 0);
dd673288 5734
259186a7 5735 s->halted = !cpu_is_bsp(cpu);
50a2c6e5
PB		 5736
5737 if (kvm_enabled()) {
5738 kvm_arch_reset_vcpu(cpu);
5739 }
dd673288 5740#endif
5fd2087a
AF		 5741}
5742
de024815
AF		 5743static void mce_init(X86CPU *cpu)
5744{
5745 CPUX86State *cenv = &cpu->env;
5746 unsigned int bank;
5747
5748 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
0514ef2f 5749 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
de024815 5750 (CPUID_MCE | CPUID_MCA)) {
87f8b626
AR		 5751 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF |
5752 (cpu->enable_lmce ? MCG_LMCE_P : 0);
de024815
AF		 5753 cenv->mcg_ctl = ~(uint64_t)0;
5754 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
5755 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
5756 }
5757 }
5758}
5759
c39c0edf
EH		 5760static void x86_cpu_adjust_level(X86CPU *cpu, uint32_t *min, uint32_t value)
5761{
5762 if (*min < value) {
5763 *min = value;
5764 }
5765}
5766
5767/* Increase cpuid_min_{level,xlevel,xlevel2} automatically, if appropriate */
5768static void x86_cpu_adjust_feat_level(X86CPU *cpu, FeatureWord w)
5769{
5770 CPUX86State *env = &cpu->env;
5771 FeatureWordInfo *fi = &feature_word_info[w];
07585923 5772 uint32_t eax = fi->cpuid.eax;
c39c0edf
EH		 5773 uint32_t region = eax & 0xF0000000;
5774
07585923 5775 assert(feature_word_info[w].type == CPUID_FEATURE_WORD);
c39c0edf
EH		 5776 if (!env->features[w]) {
5777 return;
5778 }
5779
5780 switch (region) {
5781 case 0x00000000:
5782 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, eax);
5783 break;
5784 case 0x80000000:
5785 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, eax);
5786 break;
5787 case 0xC0000000:
5788 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel2, eax);
5789 break;
5790 }
80db491d
JL		 5791
5792 if (eax == 7) {
5793 x86_cpu_adjust_level(cpu, &env->cpuid_min_level_func7,
5794 fi->cpuid.ecx);
5795 }
c39c0edf
EH		 5796}
5797
2ca8a8be
EH		 5798/* Calculate XSAVE components based on the configured CPU feature flags */
5799static void x86_cpu_enable_xsave_components(X86CPU *cpu)
5800{
5801 CPUX86State *env = &cpu->env;
5802 int i;
96193c22 5803 uint64_t mask;
2ca8a8be
EH		 5804
5805 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
19ca8285
XL		 5806 env->features[FEAT_XSAVE_COMP_LO] = 0;
5807 env->features[FEAT_XSAVE_COMP_HI] = 0;
2ca8a8be
EH		 5808 return;
5809 }
5810
e3c9022b
EH		 5811 mask = 0;
5812 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
2ca8a8be
EH		 5813 const ExtSaveArea *esa = &x86_ext_save_areas[i];
5814 if (env->features[esa->feature] & esa->bits) {
96193c22 5815 mask |= (1ULL << i);
2ca8a8be
EH		 5816 }
5817 }
5818
96193c22
EH		 5819 env->features[FEAT_XSAVE_COMP_LO] = mask;
5820 env->features[FEAT_XSAVE_COMP_HI] = mask >> 32;
2ca8a8be
EH		 5821}
5822
b8d834a0
EH		 5823/***** Steps involved on loading and filtering CPUID data
5824 *
5825 * When initializing and realizing a CPU object, the steps
5826 * involved in setting up CPUID data are:
5827 *
5828 * 1) Loading CPU model definition (X86CPUDefinition). This is
dcafd1ef 5829 * implemented by x86_cpu_load_model() and should be completely
b8d834a0
EH		 5830 * transparent, as it is done automatically by instance_init.
5831 * No code should need to look at X86CPUDefinition structs
5832 * outside instance_init.
5833 *
5834 * 2) CPU expansion. This is done by realize before CPUID
5835 * filtering, and will make sure host/accelerator data is
5836 * loaded for CPU models that depend on host capabilities
5837 * (e.g. "host"). Done by x86_cpu_expand_features().
5838 *
5839 * 3) CPUID filtering. This initializes extra data related to
5840 * CPUID, and checks if the host supports all capabilities
5841 * required by the CPU. Runnability of a CPU model is
5842 * determined at this step. Done by x86_cpu_filter_features().
5843 *
5844 * Some operations don't require all steps to be performed.
5845 * More precisely:
5846 *
5847 * - CPU instance creation (instance_init) will run only CPU
5848 * model loading. CPU expansion can't run at instance_init-time
5849 * because host/accelerator data may be not available yet.
5850 * - CPU realization will perform both CPU model expansion and CPUID
5851 * filtering, and return an error in case one of them fails.
5852 * - query-cpu-definitions needs to run all 3 steps. It needs
5853 * to run CPUID filtering, as the 'unavailable-features'
5854 * field is set based on the filtering results.
5855 * - The query-cpu-model-expansion QMP command only needs to run
5856 * CPU model loading and CPU expansion. It should not filter
5857 * any CPUID data based on host capabilities.
5858 */
5859
5860/* Expand CPU configuration data, based on configured features
5861 * and host/accelerator capabilities when appropriate.
5862 */
79f1a68a 5863void x86_cpu_expand_features(X86CPU *cpu, Error **errp)
7a059953 5864{
b34d12d1 5865 CPUX86State *env = &cpu->env;
dc15c051 5866 FeatureWord w;
99e24dbd 5867 int i;
2fae0d96 5868 GList *l;
9886e834 5869
99e24dbd
PB		 5870 for (l = plus_features; l; l = l->next) {
5871 const char *prop = l->data;
992861fb
MA		 5872 if (!object_property_set_bool(OBJECT(cpu), prop, true, errp)) {
5873 return;
99e24dbd
PB		 5874 }
5875 }
5876
5877 for (l = minus_features; l; l = l->next) {
5878 const char *prop = l->data;
992861fb
MA		 5879 if (!object_property_set_bool(OBJECT(cpu), prop, false, errp)) {
5880 return;
99e24dbd
PB		 5881 }
5882 }
5883
d4a606b3
EH		 5884 /*TODO: Now cpu->max_features doesn't overwrite features
5885 * set using QOM properties, and we can convert
dc15c051
IM		 5886 * plus_features & minus_features to global properties
5887 * inside x86_cpu_parse_featurestr() too.
5888 */
44bd8e53 5889 if (cpu->max_features) {
dc15c051 5890 for (w = 0; w < FEATURE_WORDS; w++) {
d4a606b3
EH		 5891 /* Override only features that weren't set explicitly
5892 * by the user.
5893 */
5894 env->features[w] |=
5895 x86_cpu_get_supported_feature_word(w, cpu->migratable) &
78ee6bd0 5896 ~env->user_features[w] &
0d914f39 5897 ~feature_word_info[w].no_autoenable_flags;
dc15c051
IM		 5898 }
5899 }
5900
99e24dbd
PB		 5901 for (i = 0; i < ARRAY_SIZE(feature_dependencies); i++) {
5902 FeatureDep *d = &feature_dependencies[i];
5903 if (!(env->features[d->from.index] & d->from.mask)) {
ede146c2 5904 uint64_t unavailable_features = env->features[d->to.index] & d->to.mask;
2fae0d96 5905
99e24dbd
PB		 5906 /* Not an error unless the dependent feature was added explicitly. */
5907 mark_unavailable_features(cpu, d->to.index,
5908 unavailable_features & env->user_features[d->to.index],
5909 "This feature depends on other features that were not requested");
5910
99e24dbd 5911 env->features[d->to.index] &= ~unavailable_features;
2fae0d96 5912 }
dc15c051
IM		 5913 }
5914
aec661de
EH		 5915 if (!kvm_enabled() || !cpu->expose_kvm) {
5916 env->features[FEAT_KVM] = 0;
5917 }
5918
2ca8a8be 5919 x86_cpu_enable_xsave_components(cpu);
c39c0edf
EH		 5920
5921 /* CPUID[EAX=7,ECX=0].EBX always increased level automatically: */
5922 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_EBX);
5923 if (cpu->full_cpuid_auto_level) {
5924 x86_cpu_adjust_feat_level(cpu, FEAT_1_EDX);
5925 x86_cpu_adjust_feat_level(cpu, FEAT_1_ECX);
5926 x86_cpu_adjust_feat_level(cpu, FEAT_6_EAX);
5927 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_ECX);
80db491d 5928 x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EAX);
c39c0edf
EH		 5929 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_EDX);
5930 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_ECX);
5931 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0007_EDX);
1b3420e1 5932 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0008_EBX);
c39c0edf
EH		 5933 x86_cpu_adjust_feat_level(cpu, FEAT_C000_0001_EDX);
5934 x86_cpu_adjust_feat_level(cpu, FEAT_SVM);
5935 x86_cpu_adjust_feat_level(cpu, FEAT_XSAVE);
f24c3a79
LK		 5936
5937 /* Intel Processor Trace requires CPUID[0x14] */
ddc2fc9e
LK		 5938 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT)) {
5939 if (cpu->intel_pt_auto_level) {
5940 x86_cpu_adjust_level(cpu, &cpu->env.cpuid_min_level, 0x14);
5941 } else if (cpu->env.cpuid_min_level < 0x14) {
5942 mark_unavailable_features(cpu, FEAT_7_0_EBX,
5943 CPUID_7_0_EBX_INTEL_PT,
b7d77f5a 5944 "Intel PT need CPUID leaf 0x14, please set by \"-cpu ...,intel-pt=on,min-level=0x14\"");
ddc2fc9e 5945 }
f24c3a79
LK		 5946 }
5947
a94e1428
LX		 5948 /* CPU topology with multi-dies support requires CPUID[0x1F] */
5949 if (env->nr_dies > 1) {
5950 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x1F);
5951 }
5952
0c3d7c00
EH		 5953 /* SVM requires CPUID[0x8000000A] */
5954 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
5955 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A);
5956 }
6cb8f2a6
BS		 5957
5958 /* SEV requires CPUID[0x8000001F] */
5959 if (sev_enabled()) {
5960 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000001F);
5961 }
c39c0edf
EH		 5962 }
5963
5964 /* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set */
80db491d
JL		 5965 if (env->cpuid_level_func7 == UINT32_MAX) {
5966 env->cpuid_level_func7 = env->cpuid_min_level_func7;
5967 }
c39c0edf
EH		 5968 if (env->cpuid_level == UINT32_MAX) {
5969 env->cpuid_level = env->cpuid_min_level;
5970 }
5971 if (env->cpuid_xlevel == UINT32_MAX) {
5972 env->cpuid_xlevel = env->cpuid_min_xlevel;
5973 }
5974 if (env->cpuid_xlevel2 == UINT32_MAX) {
5975 env->cpuid_xlevel2 = env->cpuid_min_xlevel2;
b34d12d1 5976 }
41f3d4d6
EH		 5977}
5978
b8d834a0
EH		 5979/*
5980 * Finishes initialization of CPUID data, filters CPU feature
5981 * words based on host availability of each feature.
5982 *
5983 * Returns: 0 if all flags are supported by the host, non-zero otherwise.
5984 */
245edd0c 5985static void x86_cpu_filter_features(X86CPU *cpu, bool verbose)
b8d834a0
EH		 5986{
5987 CPUX86State *env = &cpu->env;
5988 FeatureWord w;
245edd0c
PB		 5989 const char *prefix = NULL;
5990
5991 if (verbose) {
5992 prefix = accel_uses_host_cpuid()
5993 ? "host doesn't support requested feature"
5994 : "TCG doesn't support requested feature";
5995 }
b8d834a0
EH		 5996
5997 for (w = 0; w < FEATURE_WORDS; w++) {
ede146c2 5998 uint64_t host_feat =
b8d834a0 5999 x86_cpu_get_supported_feature_word(w, false);
ede146c2
PB		 6000 uint64_t requested_features = env->features[w];
6001 uint64_t unavailable_features = requested_features & ~host_feat;
245edd0c 6002 mark_unavailable_features(cpu, w, unavailable_features, prefix);
b8d834a0
EH		 6003 }
6004
e37a5c7f
CP		 6005 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) &&
6006 kvm_enabled()) {
6007 KVMState *s = CPU(cpu)->kvm_state;
6008 uint32_t eax_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_EAX);
6009 uint32_t ebx_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_EBX);
6010 uint32_t ecx_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_ECX);
6011 uint32_t eax_1 = kvm_arch_get_supported_cpuid(s, 0x14, 1, R_EAX);
6012 uint32_t ebx_1 = kvm_arch_get_supported_cpuid(s, 0x14, 1, R_EBX);
6013
6014 if (!eax_0 ||
6015 ((ebx_0 & INTEL_PT_MINIMAL_EBX) != INTEL_PT_MINIMAL_EBX) ||
6016 ((ecx_0 & INTEL_PT_MINIMAL_ECX) != INTEL_PT_MINIMAL_ECX) ||
6017 ((eax_1 & INTEL_PT_MTC_BITMAP) != INTEL_PT_MTC_BITMAP) ||
6018 ((eax_1 & INTEL_PT_ADDR_RANGES_NUM_MASK) <
6019 INTEL_PT_ADDR_RANGES_NUM) ||
6020 ((ebx_1 & (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) !=
c078ca96 6021 (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) ||
d1615ea5
LK		 6022 ((ecx_0 & CPUID_14_0_ECX_LIP) !=
6023 (env->features[FEAT_14_0_ECX] & CPUID_14_0_ECX_LIP))) {
e37a5c7f
CP		 6024 /*
6025 * Processor Trace capabilities aren't configurable, so if the
6026 * host can't emulate the capabilities we report on
6027 * cpu_x86_cpuid(), intel-pt can't be enabled on the current host.
6028 */
245edd0c 6029 mark_unavailable_features(cpu, FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT, prefix);
e37a5c7f
CP		 6030 }
6031 }
b8d834a0
EH		 6032}
6033
08856771
VK		 6034static void x86_cpu_hyperv_realize(X86CPU *cpu)
6035{
6036 size_t len;
6037
6038 /* Hyper-V vendor id */
6039 if (!cpu->hyperv_vendor) {
4519259a
VK		 6040 object_property_set_str(OBJECT(cpu), "hv-vendor-id", "Microsoft Hv",
6041 &error_abort);
6042 }
6043 len = strlen(cpu->hyperv_vendor);
6044 if (len > 12) {
6045 warn_report("hv-vendor-id truncated to 12 characters");
6046 len = 12;
08856771 6047 }
4519259a
VK		 6048 memset(cpu->hyperv_vendor_id, 0, 12);
6049 memcpy(cpu->hyperv_vendor_id, cpu->hyperv_vendor, len);
735db465
VK		 6050
6051 /* 'Hv#1' interface identification*/
6052 cpu->hyperv_interface_id[0] = 0x31237648;
6053 cpu->hyperv_interface_id[1] = 0;
6054 cpu->hyperv_interface_id[2] = 0;
6055 cpu->hyperv_interface_id[3] = 0;
fb7e31aa
VK		 6056
6057 /* Hypervisor system identity */
6058 cpu->hyperv_version_id[0] = 0x00001bbc;
6059 cpu->hyperv_version_id[1] = 0x00060001;
23eb5d03
VK		 6060
6061 /* Hypervisor implementation limits */
6062 cpu->hyperv_limits[0] = 64;
6063 cpu->hyperv_limits[1] = 0;
6064 cpu->hyperv_limits[2] = 0;
08856771
VK		 6065}
6066
41f3d4d6
EH		 6067static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
6068{
6069 CPUState *cs = CPU(dev);
6070 X86CPU *cpu = X86_CPU(dev);
6071 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
6072 CPUX86State *env = &cpu->env;
6073 Error *local_err = NULL;
6074 static bool ht_warned;
6075
41f3d4d6
EH		 6076 if (cpu->apic_id == UNASSIGNED_APIC_ID) {
6077 error_setg(errp, "apic-id property was not initialized properly");
6078 return;
6079 }
6080
662175b9
CF		 6081 /*
6082 * Process Hyper-V enlightenments.
6083 * Note: this currently has to happen before the expansion of CPU features.
6084 */
6085 x86_cpu_hyperv_realize(cpu);
6086
b8d834a0 6087 x86_cpu_expand_features(cpu, &local_err);
41f3d4d6
EH		 6088 if (local_err) {
6089 goto out;
6090 }
6091
245edd0c
PB		 6092 x86_cpu_filter_features(cpu, cpu->check_cpuid || cpu->enforce_cpuid);
6093
6094 if (cpu->enforce_cpuid && x86_cpu_have_filtered_features(cpu)) {
6095 error_setg(&local_err,
6096 accel_uses_host_cpuid() ?
6097 "Host doesn't support requested features" :
6098 "TCG doesn't support requested features");
6099 goto out;
9997cf7b
EH		 6100 }
6101
9b15cd9e
IM		 6102 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
6103 * CPUID[1].EDX.
6104 */
e48638fd 6105 if (IS_AMD_CPU(env)) {
0514ef2f
EH		 6106 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES;
6107 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX]
9b15cd9e
IM		 6108 & CPUID_EXT2_AMD_ALIASES);
6109 }
6110
662175b9
CF		 6111 /*
6112 * note: the call to the framework needs to happen after feature expansion,
6113 * but before the checks/modifications to ucode_rev, mwait, phys_bits.
6114 * These may be set by the accel-specific code,
6115 * and the results are subsequently checked / assumed in this function.
6116 */
6117 cpu_exec_realizefn(cs, &local_err);
6118 if (local_err != NULL) {
6119 error_propagate(errp, local_err);
6120 return;
6121 }
6122
6123 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) {
6124 g_autofree char *name = x86_cpu_class_get_model_name(xcc);
6125 error_setg(&local_err, "CPU model '%s' requires KVM or HVF", name);
6126 goto out;
6127 }
6128
6129 if (cpu->ucode_rev == 0) {
6130 /*
6131 * The default is the same as KVM's. Note that this check
6132 * needs to happen after the evenual setting of ucode_rev in
6133 * accel-specific code in cpu_exec_realizefn.
6134 */
6135 if (IS_AMD_CPU(env)) {
6136 cpu->ucode_rev = 0x01000065;
6137 } else {
6138 cpu->ucode_rev = 0x100000000ULL;
6139 }
6140 }
6141
6142 /*
6143 * mwait extended info: needed for Core compatibility
6144 * We always wake on interrupt even if host does not have the capability.
6145 *
6146 * requires the accel-specific code in cpu_exec_realizefn to
6147 * have already acquired the CPUID data into cpu->mwait.
6148 */
6149 cpu->mwait.ecx |= CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
6150
11f6fee5
DDAG		 6151 /* For 64bit systems think about the number of physical bits to present.
6152 * ideally this should be the same as the host; anything other than matching
6153 * the host can cause incorrect guest behaviour.
6154 * QEMU used to pick the magic value of 40 bits that corresponds to
6155 * consumer AMD devices but nothing else.
662175b9
CF		 6156 *
6157 * Note that this code assumes features expansion has already been done
6158 * (as it checks for CPUID_EXT2_LM), and also assumes that potential
6159 * phys_bits adjustments to match the host have been already done in
6160 * accel-specific code in cpu_exec_realizefn.
11f6fee5 6161 */
af45907a 6162 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
b8184135
PB		 6163 if (cpu->phys_bits &&
6164 (cpu->phys_bits > TARGET_PHYS_ADDR_SPACE_BITS ||
6165 cpu->phys_bits < 32)) {
6166 error_setg(errp, "phys-bits should be between 32 and %u "
6167 " (but is %u)",
6168 TARGET_PHYS_ADDR_SPACE_BITS, cpu->phys_bits);
6169 return;
af45907a 6170 }
f5cc5a5c
CF		 6171 /*
6172 * 0 means it was not explicitly set by the user (or by machine
6173 * compat_props or by the host code in host-cpu.c).
6174 * In this case, the default is the value used by TCG (40).
11f6fee5
DDAG		 6175 */
6176 if (cpu->phys_bits == 0) {
6177 cpu->phys_bits = TCG_PHYS_ADDR_BITS;
6178 }
af45907a
DDAG		 6179 } else {
6180 /* For 32 bit systems don't use the user set value, but keep
6181 * phys_bits consistent with what we tell the guest.
6182 */
6183 if (cpu->phys_bits != 0) {
6184 error_setg(errp, "phys-bits is not user-configurable in 32 bit");
6185 return;
6186 }
fefb41bf 6187
af45907a
DDAG		 6188 if (env->features[FEAT_1_EDX] & CPUID_PSE36) {
6189 cpu->phys_bits = 36;
6190 } else {
6191 cpu->phys_bits = 32;
6192 }
6193 }
a9f27ea9
EH		 6194
6195 /* Cache information initialization */
6196 if (!cpu->legacy_cache) {
dcafd1ef 6197 if (!xcc->model || !xcc->model->cpudef->cache_info) {
88703ce2 6198 g_autofree char *name = x86_cpu_class_get_model_name(xcc);
a9f27ea9
EH		 6199 error_setg(errp,
6200 "CPU model '%s' doesn't support legacy-cache=off", name);
a9f27ea9
EH		 6201 return;
6202 }
6203 env->cache_info_cpuid2 = env->cache_info_cpuid4 = env->cache_info_amd =
dcafd1ef 6204 *xcc->model->cpudef->cache_info;
a9f27ea9
EH		 6205 } else {
6206 /* Build legacy cache information */
6207 env->cache_info_cpuid2.l1d_cache = &legacy_l1d_cache;
6208 env->cache_info_cpuid2.l1i_cache = &legacy_l1i_cache;
6209 env->cache_info_cpuid2.l2_cache = &legacy_l2_cache_cpuid2;
6210 env->cache_info_cpuid2.l3_cache = &legacy_l3_cache;
6211
6212 env->cache_info_cpuid4.l1d_cache = &legacy_l1d_cache;
6213 env->cache_info_cpuid4.l1i_cache = &legacy_l1i_cache;
6214 env->cache_info_cpuid4.l2_cache = &legacy_l2_cache;
6215 env->cache_info_cpuid4.l3_cache = &legacy_l3_cache;
6216
6217 env->cache_info_amd.l1d_cache = &legacy_l1d_cache_amd;
6218 env->cache_info_amd.l1i_cache = &legacy_l1i_cache_amd;
6219 env->cache_info_amd.l2_cache = &legacy_l2_cache_amd;
6220 env->cache_info_amd.l3_cache = &legacy_l3_cache;
6221 }
6222
65dee380 6223#ifndef CONFIG_USER_ONLY
0e11fc69 6224 MachineState *ms = MACHINE(qdev_get_machine());
65dee380 6225 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
bdeec802 6226
0e11fc69 6227 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || ms->smp.cpus > 1) {
d3c64d6a 6228 x86_cpu_apic_create(cpu, &local_err);
2b6f294c 6229 if (local_err != NULL) {
4dc1f449 6230 goto out;
bdeec802
IM		 6231 }
6232 }
65dee380
IM		 6233#endif
6234
7a059953 6235 mce_init(cpu);
2001d0cd 6236
14a10fc3 6237 qemu_init_vcpu(cs);
d3c64d6a 6238
6b2942f9
BM		 6239 /*
6240 * Most Intel and certain AMD CPUs support hyperthreading. Even though QEMU
6241 * fixes this issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX
6242 * based on inputs (sockets,cores,threads), it is still better to give
e48638fd
WH		 6243 * users a warning.
6244 *
6245 * NOTE: the following code has to follow qemu_init_vcpu(). Otherwise
6246 * cs->nr_threads hasn't be populated yet and the checking is incorrect.
6247 */
0765691e
MA		 6248 if (IS_AMD_CPU(env) &&
6249 !(env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_TOPOEXT) &&
6250 cs->nr_threads > 1 && !ht_warned) {
6251 warn_report("This family of AMD CPU doesn't support "
6252 "hyperthreading(%d)",
6253 cs->nr_threads);
6254 error_printf("Please configure -smp options properly"
6255 " or try enabling topoext feature.\n");
6256 ht_warned = true;
e48638fd
WH		 6257 }
6258
79f1a68a 6259#ifndef CONFIG_USER_ONLY
d3c64d6a
IM		 6260 x86_cpu_apic_realize(cpu, &local_err);
6261 if (local_err != NULL) {
6262 goto out;
6263 }
79f1a68a 6264#endif /* !CONFIG_USER_ONLY */
14a10fc3 6265 cpu_reset(cs);
2b6f294c 6266
4dc1f449 6267 xcc->parent_realize(dev, &local_err);
2001d0cd 6268
4dc1f449
IM		 6269out:
6270 if (local_err != NULL) {
6271 error_propagate(errp, local_err);
6272 return;
6273 }
7a059953
AF		 6274}
6275
b69c3c21 6276static void x86_cpu_unrealizefn(DeviceState *dev)
c884776e
IM		 6277{
6278 X86CPU *cpu = X86_CPU(dev);
7bbc124e 6279 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
c884776e
IM		 6280
6281#ifndef CONFIG_USER_ONLY
6282 cpu_remove_sync(CPU(dev));
6283 qemu_unregister_reset(x86_cpu_machine_reset_cb, dev);
6284#endif
6285
6286 if (cpu->apic_state) {
6287 object_unparent(OBJECT(cpu->apic_state));
6288 cpu->apic_state = NULL;
6289 }
7bbc124e 6290
b69c3c21 6291 xcc->parent_unrealize(dev);
c884776e
IM		 6292}
6293
38e5c119 6294typedef struct BitProperty {
a7b0ffac 6295 FeatureWord w;
ede146c2 6296 uint64_t mask;
38e5c119
EH		 6297} BitProperty;
6298
d7bce999
EB		 6299static void x86_cpu_get_bit_prop(Object *obj, Visitor *v, const char *name,
6300 void *opaque, Error **errp)
38e5c119 6301{
a7b0ffac 6302 X86CPU *cpu = X86_CPU(obj);
38e5c119 6303 BitProperty *fp = opaque;
ede146c2 6304 uint64_t f = cpu->env.features[fp->w];
a7b0ffac 6305 bool value = (f & fp->mask) == fp->mask;
51e72bc1 6306 visit_type_bool(v, name, &value, errp);
38e5c119
EH		 6307}
6308
d7bce999
EB		 6309static void x86_cpu_set_bit_prop(Object *obj, Visitor *v, const char *name,
6310 void *opaque, Error **errp)
38e5c119
EH		 6311{
6312 DeviceState *dev = DEVICE(obj);
a7b0ffac 6313 X86CPU *cpu = X86_CPU(obj);
38e5c119 6314 BitProperty *fp = opaque;
38e5c119
EH		 6315 bool value;
6316
6317 if (dev->realized) {
6318 qdev_prop_set_after_realize(dev, name, errp);
6319 return;
6320 }
6321
668f62ec 6322 if (!visit_type_bool(v, name, &value, errp)) {
38e5c119
EH		 6323 return;
6324 }
6325
6326 if (value) {
a7b0ffac 6327 cpu->env.features[fp->w] |= fp->mask;
38e5c119 6328 } else {
a7b0ffac 6329 cpu->env.features[fp->w] &= ~fp->mask;
38e5c119 6330 }
d4a606b3 6331 cpu->env.user_features[fp->w] |= fp->mask;
38e5c119
EH		 6332}
6333
38e5c119
EH		 6334/* Register a boolean property to get/set a single bit in a uint32_t field.
6335 *
6336 * The same property name can be registered multiple times to make it affect
6337 * multiple bits in the same FeatureWord. In that case, the getter will return
6338 * true only if all bits are set.
6339 */
f5730c69 6340static void x86_cpu_register_bit_prop(X86CPUClass *xcc,
38e5c119 6341 const char *prop_name,
a7b0ffac 6342 FeatureWord w,
38e5c119
EH		 6343 int bitnr)
6344{
f5730c69 6345 ObjectClass *oc = OBJECT_CLASS(xcc);
38e5c119
EH		 6346 BitProperty *fp;
6347 ObjectProperty *op;
ede146c2 6348 uint64_t mask = (1ULL << bitnr);
38e5c119 6349
f5730c69 6350 op = object_class_property_find(oc, prop_name);
38e5c119
EH		 6351 if (op) {
6352 fp = op->opaque;
a7b0ffac 6353 assert(fp->w == w);
38e5c119
EH		 6354 fp->mask |= mask;
6355 } else {
6356 fp = g_new0(BitProperty, 1);
a7b0ffac 6357 fp->w = w;
38e5c119 6358 fp->mask = mask;
f5730c69
EH		 6359 object_class_property_add(oc, prop_name, "bool",
6360 x86_cpu_get_bit_prop,
6361 x86_cpu_set_bit_prop,
6362 NULL, fp);
38e5c119
EH		 6363 }
6364}
6365
f5730c69 6366static void x86_cpu_register_feature_bit_props(X86CPUClass *xcc,
38e5c119
EH		 6367 FeatureWord w,
6368 int bitnr)
6369{
38e5c119 6370 FeatureWordInfo *fi = &feature_word_info[w];
16d2fcaa 6371 const char *name = fi->feat_names[bitnr];
38e5c119 6372
16d2fcaa 6373 if (!name) {
38e5c119
EH		 6374 return;
6375 }
6376
fc7dfd20
EH		 6377 /* Property names should use "-" instead of "_".
6378 * Old names containing underscores are registered as aliases
6379 * using object_property_add_alias()
6380 */
16d2fcaa
EH		 6381 assert(!strchr(name, '_'));
6382 /* aliases don't use "|" delimiters anymore, they are registered
6383 * manually using object_property_add_alias() */
6384 assert(!strchr(name, '|'));
f5730c69 6385 x86_cpu_register_bit_prop(xcc, name, w, bitnr);
38e5c119
EH		 6386}
6387
4db4385a
CF		 6388static void x86_cpu_post_initfn(Object *obj)
6389{
6390 accel_cpu_instance_init(CPU(obj));
6391}
6392
de024815
AF		 6393static void x86_cpu_initfn(Object *obj)
6394{
6395 X86CPU *cpu = X86_CPU(obj);
d940ee9b 6396 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj);
de024815
AF		 6397 CPUX86State *env = &cpu->env;
6398
c26ae610 6399 env->nr_dies = 1;
7506ed90 6400 cpu_set_cpustate_pointers(cpu);
71ad61d3 6401
8e8aba50
EH		 6402 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo",
6403 x86_cpu_get_feature_words,
d2623129 6404 NULL, NULL, (void *)env->features);
7e5292b5
EH		 6405 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo",
6406 x86_cpu_get_feature_words,
d2623129 6407 NULL, NULL, (void *)cpu->filtered_features);
d187e08d 6408
d2623129
MA		 6409 object_property_add_alias(obj, "sse3", obj, "pni");
6410 object_property_add_alias(obj, "pclmuldq", obj, "pclmulqdq");
6411 object_property_add_alias(obj, "sse4-1", obj, "sse4.1");
6412 object_property_add_alias(obj, "sse4-2", obj, "sse4.2");
6413 object_property_add_alias(obj, "xd", obj, "nx");
6414 object_property_add_alias(obj, "ffxsr", obj, "fxsr-opt");
6415 object_property_add_alias(obj, "i64", obj, "lm");
6416
6417 object_property_add_alias(obj, "ds_cpl", obj, "ds-cpl");
6418 object_property_add_alias(obj, "tsc_adjust", obj, "tsc-adjust");
6419 object_property_add_alias(obj, "fxsr_opt", obj, "fxsr-opt");
6420 object_property_add_alias(obj, "lahf_lm", obj, "lahf-lm");
6421 object_property_add_alias(obj, "cmp_legacy", obj, "cmp-legacy");
6422 object_property_add_alias(obj, "nodeid_msr", obj, "nodeid-msr");
6423 object_property_add_alias(obj, "perfctr_core", obj, "perfctr-core");
6424 object_property_add_alias(obj, "perfctr_nb", obj, "perfctr-nb");
6425 object_property_add_alias(obj, "kvm_nopiodelay", obj, "kvm-nopiodelay");
6426 object_property_add_alias(obj, "kvm_mmu", obj, "kvm-mmu");
6427 object_property_add_alias(obj, "kvm_asyncpf", obj, "kvm-asyncpf");
db5daafa 6428 object_property_add_alias(obj, "kvm_asyncpf_int", obj, "kvm-asyncpf-int");
d2623129
MA		 6429 object_property_add_alias(obj, "kvm_steal_time", obj, "kvm-steal-time");
6430 object_property_add_alias(obj, "kvm_pv_eoi", obj, "kvm-pv-eoi");
6431 object_property_add_alias(obj, "kvm_pv_unhalt", obj, "kvm-pv-unhalt");
6432 object_property_add_alias(obj, "kvm_poll_control", obj, "kvm-poll-control");
6433 object_property_add_alias(obj, "svm_lock", obj, "svm-lock");
6434 object_property_add_alias(obj, "nrip_save", obj, "nrip-save");
6435 object_property_add_alias(obj, "tsc_scale", obj, "tsc-scale");
6436 object_property_add_alias(obj, "vmcb_clean", obj, "vmcb-clean");
6437 object_property_add_alias(obj, "pause_filter", obj, "pause-filter");
6438 object_property_add_alias(obj, "sse4_1", obj, "sse4.1");
6439 object_property_add_alias(obj, "sse4_2", obj, "sse4.2");
54b8dc7c 6440
dcafd1ef 6441 if (xcc->model) {
49e2fa85 6442 x86_cpu_load_model(cpu, xcc->model);
0bacd8b3 6443 }
de024815
AF		 6444}
6445
997395d3
IM		 6446static int64_t x86_cpu_get_arch_id(CPUState *cs)
6447{
6448 X86CPU *cpu = X86_CPU(cs);
997395d3 6449
7e72a45c 6450 return cpu->apic_id;
997395d3
IM		 6451}
6452
6bc0d6a0 6453#if !defined(CONFIG_USER_ONLY)
444d5590
AF		 6454static bool x86_cpu_get_paging_enabled(const CPUState *cs)
6455{
6456 X86CPU *cpu = X86_CPU(cs);
6457
6458 return cpu->env.cr[0] & CR0_PG_MASK;
6459}
6bc0d6a0 6460#endif /* !CONFIG_USER_ONLY */
444d5590 6461
f45748f1
AF		 6462static void x86_cpu_set_pc(CPUState *cs, vaddr value)
6463{
6464 X86CPU *cpu = X86_CPU(cs);
6465
6466 cpu->env.eip = value;
6467}
6468
92d5f1a4 6469int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request)
8c2e1b00
AF		 6470{
6471 X86CPU *cpu = X86_CPU(cs);
6472 CPUX86State *env = &cpu->env;
6473
92d5f1a4
PB		 6474#if !defined(CONFIG_USER_ONLY)
6475 if (interrupt_request & CPU_INTERRUPT_POLL) {
6476 return CPU_INTERRUPT_POLL;
6477 }
6478#endif
6479 if (interrupt_request & CPU_INTERRUPT_SIPI) {
6480 return CPU_INTERRUPT_SIPI;
6481 }
6482
6483 if (env->hflags2 & HF2_GIF_MASK) {
6484 if ((interrupt_request & CPU_INTERRUPT_SMI) &&
6485 !(env->hflags & HF_SMM_MASK)) {
6486 return CPU_INTERRUPT_SMI;
6487 } else if ((interrupt_request & CPU_INTERRUPT_NMI) &&
6488 !(env->hflags2 & HF2_NMI_MASK)) {
6489 return CPU_INTERRUPT_NMI;
6490 } else if (interrupt_request & CPU_INTERRUPT_MCE) {
6491 return CPU_INTERRUPT_MCE;
6492 } else if ((interrupt_request & CPU_INTERRUPT_HARD) &&
6493 (((env->hflags2 & HF2_VINTR_MASK) &&
6494 (env->hflags2 & HF2_HIF_MASK)) ||
6495 (!(env->hflags2 & HF2_VINTR_MASK) &&
6496 (env->eflags & IF_MASK &&
6497 !(env->hflags & HF_INHIBIT_IRQ_MASK))))) {
6498 return CPU_INTERRUPT_HARD;
6499#if !defined(CONFIG_USER_ONLY)
6500 } else if ((interrupt_request & CPU_INTERRUPT_VIRQ) &&
6501 (env->eflags & IF_MASK) &&
6502 !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
6503 return CPU_INTERRUPT_VIRQ;
6504#endif
6505 }
6506 }
6507
6508 return 0;
6509}
6510
6511static bool x86_cpu_has_work(CPUState *cs)
6512{
6513 return x86_cpu_pending_interrupt(cs, cs->interrupt_request) != 0;
8c2e1b00
AF		 6514}
6515
f50f3dd5
RH		 6516static void x86_disas_set_info(CPUState *cs, disassemble_info *info)
6517{
6518 X86CPU *cpu = X86_CPU(cs);
6519 CPUX86State *env = &cpu->env;
6520
6521 info->mach = (env->hflags & HF_CS64_MASK ? bfd_mach_x86_64
6522 : env->hflags & HF_CS32_MASK ? bfd_mach_i386_i386
6523 : bfd_mach_i386_i8086);
6524 info->print_insn = print_insn_i386;
b666d2a4
RH		 6525
6526 info->cap_arch = CS_ARCH_X86;
6527 info->cap_mode = (env->hflags & HF_CS64_MASK ? CS_MODE_64
6528 : env->hflags & HF_CS32_MASK ? CS_MODE_32
6529 : CS_MODE_16);
15fa1a0a
RH		 6530 info->cap_insn_unit = 1;
6531 info->cap_insn_split = 8;
f50f3dd5
RH		 6532}
6533
35b1b927
TW		 6534void x86_update_hflags(CPUX86State *env)
6535{
6536 uint32_t hflags;
6537#define HFLAG_COPY_MASK \
6538 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
6539 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
6540 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
6541 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
6542
6543 hflags = env->hflags & HFLAG_COPY_MASK;
6544 hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
6545 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
6546 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
6547 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
6548 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
6549
6550 if (env->cr[4] & CR4_OSFXSR_MASK) {
6551 hflags |= HF_OSFXSR_MASK;
6552 }
6553
6554 if (env->efer & MSR_EFER_LMA) {
6555 hflags |= HF_LMA_MASK;
6556 }
6557
6558 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
6559 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
6560 } else {
6561 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
6562 (DESC_B_SHIFT - HF_CS32_SHIFT);
6563 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
6564 (DESC_B_SHIFT - HF_SS32_SHIFT);
6565 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
6566 !(hflags & HF_CS32_MASK)) {
6567 hflags |= HF_ADDSEG_MASK;
6568 } else {
6569 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
6570 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
6571 }
6572 }
6573 env->hflags = hflags;
6574}
6575
9337e3b6 6576static Property x86_cpu_properties[] = {
2da00e31
IM		 6577#ifdef CONFIG_USER_ONLY
6578 /* apic_id = 0 by default for *-user, see commit 9886e834 */
6579 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, 0),
d89c2b8b
IM		 6580 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, 0),
6581 DEFINE_PROP_INT32("core-id", X86CPU, core_id, 0),
176d2cda 6582 DEFINE_PROP_INT32("die-id", X86CPU, die_id, 0),
d89c2b8b 6583 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, 0),
2da00e31
IM		 6584#else
6585 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, UNASSIGNED_APIC_ID),
d89c2b8b
IM		 6586 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, -1),
6587 DEFINE_PROP_INT32("core-id", X86CPU, core_id, -1),
176d2cda 6588 DEFINE_PROP_INT32("die-id", X86CPU, die_id, -1),
d89c2b8b 6589 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, -1),
2da00e31 6590#endif
15f8b142 6591 DEFINE_PROP_INT32("node-id", X86CPU, node_id, CPU_UNSET_NUMA_NODE_ID),
9337e3b6 6592 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false),
2d384d7c 6593
915aee93 6594 DEFINE_PROP_UINT32("hv-spinlocks", X86CPU, hyperv_spinlock_attempts,
f701c082 6595 HYPERV_SPINLOCK_NEVER_NOTIFY),
2d384d7c
VK		 6596 DEFINE_PROP_BIT64("hv-relaxed", X86CPU, hyperv_features,
6597 HYPERV_FEAT_RELAXED, 0),
6598 DEFINE_PROP_BIT64("hv-vapic", X86CPU, hyperv_features,
6599 HYPERV_FEAT_VAPIC, 0),
6600 DEFINE_PROP_BIT64("hv-time", X86CPU, hyperv_features,
6601 HYPERV_FEAT_TIME, 0),
6602 DEFINE_PROP_BIT64("hv-crash", X86CPU, hyperv_features,
6603 HYPERV_FEAT_CRASH, 0),
6604 DEFINE_PROP_BIT64("hv-reset", X86CPU, hyperv_features,
6605 HYPERV_FEAT_RESET, 0),
6606 DEFINE_PROP_BIT64("hv-vpindex", X86CPU, hyperv_features,
6607 HYPERV_FEAT_VPINDEX, 0),
6608 DEFINE_PROP_BIT64("hv-runtime", X86CPU, hyperv_features,
6609 HYPERV_FEAT_RUNTIME, 0),
6610 DEFINE_PROP_BIT64("hv-synic", X86CPU, hyperv_features,
6611 HYPERV_FEAT_SYNIC, 0),
6612 DEFINE_PROP_BIT64("hv-stimer", X86CPU, hyperv_features,
6613 HYPERV_FEAT_STIMER, 0),
6614 DEFINE_PROP_BIT64("hv-frequencies", X86CPU, hyperv_features,
6615 HYPERV_FEAT_FREQUENCIES, 0),
6616 DEFINE_PROP_BIT64("hv-reenlightenment", X86CPU, hyperv_features,
6617 HYPERV_FEAT_REENLIGHTENMENT, 0),
6618 DEFINE_PROP_BIT64("hv-tlbflush", X86CPU, hyperv_features,
6619 HYPERV_FEAT_TLBFLUSH, 0),
6620 DEFINE_PROP_BIT64("hv-evmcs", X86CPU, hyperv_features,
6621 HYPERV_FEAT_EVMCS, 0),
6622 DEFINE_PROP_BIT64("hv-ipi", X86CPU, hyperv_features,
6623 HYPERV_FEAT_IPI, 0),
128531d9
VK		 6624 DEFINE_PROP_BIT64("hv-stimer-direct", X86CPU, hyperv_features,
6625 HYPERV_FEAT_STIMER_DIRECT, 0),
30d6ff66
VK		 6626 DEFINE_PROP_ON_OFF_AUTO("hv-no-nonarch-coresharing", X86CPU,
6627 hyperv_no_nonarch_cs, ON_OFF_AUTO_OFF),
e48ddcc6 6628 DEFINE_PROP_BOOL("hv-passthrough", X86CPU, hyperv_passthrough, false),
2d384d7c 6629
15e41345 6630 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, true),
912ffc47 6631 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false),
dac1deae 6632 DEFINE_PROP_BOOL("x-force-features", X86CPU, force_features, false),
f522d2ac 6633 DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true),
af45907a 6634 DEFINE_PROP_UINT32("phys-bits", X86CPU, phys_bits, 0),
11f6fee5 6635 DEFINE_PROP_BOOL("host-phys-bits", X86CPU, host_phys_bits, false),
258fe08b 6636 DEFINE_PROP_UINT8("host-phys-bits-limit", X86CPU, host_phys_bits_limit, 0),
fcc35e7c 6637 DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU, fill_mtrr_mask, true),
80db491d
JL		 6638 DEFINE_PROP_UINT32("level-func7", X86CPU, env.cpuid_level_func7,
6639 UINT32_MAX),
c39c0edf
EH		 6640 DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, UINT32_MAX),
6641 DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, UINT32_MAX),
6642 DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, UINT32_MAX),
6643 DEFINE_PROP_UINT32("min-level", X86CPU, env.cpuid_min_level, 0),
6644 DEFINE_PROP_UINT32("min-xlevel", X86CPU, env.cpuid_min_xlevel, 0),
6645 DEFINE_PROP_UINT32("min-xlevel2", X86CPU, env.cpuid_min_xlevel2, 0),
4e45aff3 6646 DEFINE_PROP_UINT64("ucode-rev", X86CPU, ucode_rev, 0),
c39c0edf 6647 DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_level, true),
08856771 6648 DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor),
5232d00a 6649 DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true),
87f8b626 6650 DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false),
14c985cf 6651 DEFINE_PROP_BOOL("l3-cache", X86CPU, enable_l3_cache, true),
fc3a1fd7
DDAG		 6652 DEFINE_PROP_BOOL("kvm-no-smi-migration", X86CPU, kvm_no_smi_migration,
6653 false),
0b564e6f 6654 DEFINE_PROP_BOOL("vmware-cpuid-freq", X86CPU, vmware_cpuid_freq, true),
1ce36bfe 6655 DEFINE_PROP_BOOL("tcg-cpuid", X86CPU, expose_tcg, true),
990e0be2
PB		 6656 DEFINE_PROP_BOOL("x-migrate-smi-count", X86CPU, migrate_smi_count,
6657 true),
ab8f992e 6658 /*
a9f27ea9
EH		 6659 * lecacy_cache defaults to true unless the CPU model provides its
6660 * own cache information (see x86_cpu_load_def()).
ab8f992e 6661 */
a9f27ea9 6662 DEFINE_PROP_BOOL("legacy-cache", X86CPU, legacy_cache, true),
6c69dfb6
GA		 6663
6664 /*
6665 * From "Requirements for Implementing the Microsoft
6666 * Hypervisor Interface":
6667 * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs
6668 *
6669 * "Starting with Windows Server 2012 and Windows 8, if
6670 * CPUID.40000005.EAX contains a value of -1, Windows assumes that
6671 * the hypervisor imposes no specific limit to the number of VPs.
6672 * In this case, Windows Server 2012 guest VMs may use more than
6673 * 64 VPs, up to the maximum supported number of processors applicable
6674 * to the specific Windows version being used."
6675 */
6676 DEFINE_PROP_INT32("x-hv-max-vps", X86CPU, hv_max_vps, -1),
9b4cf107
RK		 6677 DEFINE_PROP_BOOL("x-hv-synic-kvm-only", X86CPU, hyperv_synic_kvm_only,
6678 false),
f24c3a79
LK		 6679 DEFINE_PROP_BOOL("x-intel-pt-auto-level", X86CPU, intel_pt_auto_level,
6680 true),
9337e3b6
EH		 6681 DEFINE_PROP_END_OF_LIST()
6682};
6683
8b80bd28
PMD		 6684#ifndef CONFIG_USER_ONLY
6685#include "hw/core/sysemu-cpu-ops.h"
6686
6687static const struct SysemuCPUOps i386_sysemu_ops = {
2b60b62e 6688 .get_memory_mapping = x86_cpu_get_memory_mapping,
6bc0d6a0 6689 .get_paging_enabled = x86_cpu_get_paging_enabled,
08928c6d 6690 .get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug,
faf39e82 6691 .asidx_from_attrs = x86_asidx_from_attrs,
83ec01b6 6692 .get_crash_info = x86_cpu_get_crash_info,
715e3c1a
PMD		 6693 .write_elf32_note = x86_cpu_write_elf32_note,
6694 .write_elf64_note = x86_cpu_write_elf64_note,
6695 .write_elf32_qemunote = x86_cpu_write_elf32_qemunote,
6696 .write_elf64_qemunote = x86_cpu_write_elf64_qemunote,
feece4d0 6697 .legacy_vmsd = &vmstate_x86_cpu,
8b80bd28
PMD		 6698};
6699#endif
6700
5fd2087a
AF		 6701static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
6702{
6703 X86CPUClass *xcc = X86_CPU_CLASS(oc);
6704 CPUClass *cc = CPU_CLASS(oc);
2b6f294c 6705 DeviceClass *dc = DEVICE_CLASS(oc);
f5730c69 6706 FeatureWord w;
2b6f294c 6707
bf853881
PMD		 6708 device_class_set_parent_realize(dc, x86_cpu_realizefn,
6709 &xcc->parent_realize);
6710 device_class_set_parent_unrealize(dc, x86_cpu_unrealizefn,
6711 &xcc->parent_unrealize);
4f67d30b 6712 device_class_set_props(dc, x86_cpu_properties);
5fd2087a 6713
781c67ca 6714 device_class_set_parent_reset(dc, x86_cpu_reset, &xcc->parent_reset);
91b1df8c 6715 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP;
f56e3a14 6716
500050d1 6717 cc->class_by_name = x86_cpu_class_by_name;
94a444b2 6718 cc->parse_features = x86_cpu_parse_featurestr;
8c2e1b00 6719 cc->has_work = x86_cpu_has_work;
878096ee 6720 cc->dump_state = x86_cpu_dump_state;
f45748f1 6721 cc->set_pc = x86_cpu_set_pc;
5b50e790
AF		 6722 cc->gdb_read_register = x86_cpu_gdb_read_register;
6723 cc->gdb_write_register = x86_cpu_gdb_write_register;
444d5590 6724 cc->get_arch_id = x86_cpu_get_arch_id;
ed69e831 6725
5d004421 6726#ifndef CONFIG_USER_ONLY
8b80bd28 6727 cc->sysemu_ops = &i386_sysemu_ops;
ed69e831
CF		 6728#endif /* !CONFIG_USER_ONLY */
6729
00fcd100
AB		 6730 cc->gdb_arch_name = x86_gdb_arch_name;
6731#ifdef TARGET_X86_64
b8158192 6732 cc->gdb_core_xml_file = "i386-64bit.xml";
7b0f97ba 6733 cc->gdb_num_core_regs = 66;
00fcd100 6734#else
b8158192 6735 cc->gdb_core_xml_file = "i386-32bit.xml";
7b0f97ba 6736 cc->gdb_num_core_regs = 50;
74d7fc7f 6737#endif
f50f3dd5 6738 cc->disas_set_info = x86_disas_set_info;
4c315c27 6739
e90f2a8c 6740 dc->user_creatable = true;
3e0dceaf
EH		 6741
6742 object_class_property_add(oc, "family", "int",
6743 x86_cpuid_version_get_family,
6744 x86_cpuid_version_set_family, NULL, NULL);
6745 object_class_property_add(oc, "model", "int",
6746 x86_cpuid_version_get_model,
6747 x86_cpuid_version_set_model, NULL, NULL);
6748 object_class_property_add(oc, "stepping", "int",
6749 x86_cpuid_version_get_stepping,
6750 x86_cpuid_version_set_stepping, NULL, NULL);
6751 object_class_property_add_str(oc, "vendor",
6752 x86_cpuid_get_vendor,
6753 x86_cpuid_set_vendor);
6754 object_class_property_add_str(oc, "model-id",
6755 x86_cpuid_get_model_id,
6756 x86_cpuid_set_model_id);
6757 object_class_property_add(oc, "tsc-frequency", "int",
6758 x86_cpuid_get_tsc_freq,
6759 x86_cpuid_set_tsc_freq, NULL, NULL);
6760 /*
6761 * The "unavailable-features" property has the same semantics as
6762 * CpuDefinitionInfo.unavailable-features on the "query-cpu-definitions"
6763 * QMP command: they list the features that would have prevented the
6764 * CPU from running if the "enforce" flag was set.
6765 */
6766 object_class_property_add(oc, "unavailable-features", "strList",
6767 x86_cpu_get_unavailable_features,
6768 NULL, NULL, NULL);
6769
6770#if !defined(CONFIG_USER_ONLY)
6771 object_class_property_add(oc, "crash-information", "GuestPanicInformation",
6772 x86_cpu_get_crash_info_qom, NULL, NULL, NULL);
6773#endif
6774
f5730c69
EH		 6775 for (w = 0; w < FEATURE_WORDS; w++) {
6776 int bitnr;
6777 for (bitnr = 0; bitnr < 64; bitnr++) {
6778 x86_cpu_register_feature_bit_props(xcc, w, bitnr);
6779 }
6780 }
5fd2087a
AF		 6781}
6782
6783static const TypeInfo x86_cpu_type_info = {
6784 .name = TYPE_X86_CPU,
6785 .parent = TYPE_CPU,
6786 .instance_size = sizeof(X86CPU),
de024815 6787 .instance_init = x86_cpu_initfn,
4db4385a
CF		 6788 .instance_post_init = x86_cpu_post_initfn,
6789
d940ee9b 6790 .abstract = true,
5fd2087a
AF		 6791 .class_size = sizeof(X86CPUClass),
6792 .class_init = x86_cpu_common_class_init,
6793};
6794
5adbed30
EH		 6795
6796/* "base" CPU model, used by query-cpu-model-expansion */
6797static void x86_cpu_base_class_init(ObjectClass *oc, void *data)
6798{
6799 X86CPUClass *xcc = X86_CPU_CLASS(oc);
6800
6801 xcc->static_model = true;
6802 xcc->migration_safe = true;
6803 xcc->model_description = "base CPU model type with no features enabled";
6804 xcc->ordering = 8;
6805}
6806
6807static const TypeInfo x86_base_cpu_type_info = {
6808 .name = X86_CPU_TYPE_NAME("base"),
6809 .parent = TYPE_X86_CPU,
6810 .class_init = x86_cpu_base_class_init,
6811};
6812
5fd2087a
AF		 6813static void x86_cpu_register_types(void)
6814{
d940ee9b
EH		 6815 int i;
6816
5fd2087a 6817 type_register_static(&x86_cpu_type_info);
d940ee9b 6818 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
dcafd1ef 6819 x86_register_cpudef_types(&builtin_x86_defs[i]);
d940ee9b 6820 }
c62f2630 6821 type_register_static(&max_x86_cpu_type_info);
5adbed30 6822 type_register_static(&x86_base_cpu_type_info);
5fd2087a
AF		 6823}
6824
6825type_init(x86_cpu_register_types)
Empty description
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