]> Git Repo - qemu.git/blame - target-i386/cpu.c
projects / qemu.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
pc: Add 2.7 machine
[qemu.git] / target-i386 / cpu.c
CommitLineData
c6dc6f63
AP		 1/*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
1ef26b1f 19#include "qemu/osdep.h"
f348b6d1 20#include "qemu/cutils.h"
c6dc6f63
AP		 21
22#include "cpu.h"
63c91552 23#include "exec/exec-all.h"
9c17d615 24#include "sysemu/kvm.h"
8932cfdf 25#include "sysemu/cpus.h"
50a2c6e5 26#include "kvm_i386.h"
c6dc6f63 27
d49b6836 28#include "qemu/error-report.h"
1de7afc9
PB		 29#include "qemu/option.h"
30#include "qemu/config-file.h"
7b1b5d19 31#include "qapi/qmp/qerror.h"
c6dc6f63 32
8e8aba50
EH		 33#include "qapi-types.h"
34#include "qapi-visit.h"
7b1b5d19 35#include "qapi/visitor.h"
9c17d615 36#include "sysemu/arch_init.h"
71ad61d3 37
b834b508 38#if defined(CONFIG_KVM)
ef8621b1 39#include <linux/kvm_para.h>
b834b508 40#endif
65dee380 41
9c17d615 42#include "sysemu/sysemu.h"
53a89e26 43#include "hw/qdev-properties.h"
bdeec802 44#ifndef CONFIG_USER_ONLY
2001d0cd 45#include "exec/address-spaces.h"
741da0d3 46#include "hw/hw.h"
0d09e41a 47#include "hw/xen/xen.h"
0d09e41a 48#include "hw/i386/apic_internal.h"
bdeec802
IM		 49#endif
50
5e891bf8
EH		 51
52/* Cache topology CPUID constants: */
53
54/* CPUID Leaf 2 Descriptors */
55
56#define CPUID_2_L1D_32KB_8WAY_64B 0x2c
57#define CPUID_2_L1I_32KB_8WAY_64B 0x30
58#define CPUID_2_L2_2MB_8WAY_64B 0x7d
59
60
61/* CPUID Leaf 4 constants: */
62
63/* EAX: */
64#define CPUID_4_TYPE_DCACHE 1
65#define CPUID_4_TYPE_ICACHE 2
66#define CPUID_4_TYPE_UNIFIED 3
67
68#define CPUID_4_LEVEL(l) ((l) << 5)
69
70#define CPUID_4_SELF_INIT_LEVEL (1 << 8)
71#define CPUID_4_FULLY_ASSOC (1 << 9)
72
73/* EDX: */
74#define CPUID_4_NO_INVD_SHARING (1 << 0)
75#define CPUID_4_INCLUSIVE (1 << 1)
76#define CPUID_4_COMPLEX_IDX (1 << 2)
77
78#define ASSOC_FULL 0xFF
79
80/* AMD associativity encoding used on CPUID Leaf 0x80000006: */
81#define AMD_ENC_ASSOC(a) (a <= 1 ? a : \
82 a == 2 ? 0x2 : \
83 a == 4 ? 0x4 : \
84 a == 8 ? 0x6 : \
85 a == 16 ? 0x8 : \
86 a == 32 ? 0xA : \
87 a == 48 ? 0xB : \
88 a == 64 ? 0xC : \
89 a == 96 ? 0xD : \
90 a == 128 ? 0xE : \
91 a == ASSOC_FULL ? 0xF : \
92 0 /* invalid value */)
93
94
95/* Definitions of the hardcoded cache entries we expose: */
96
97/* L1 data cache: */
98#define L1D_LINE_SIZE 64
99#define L1D_ASSOCIATIVITY 8
100#define L1D_SETS 64
101#define L1D_PARTITIONS 1
102/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
103#define L1D_DESCRIPTOR CPUID_2_L1D_32KB_8WAY_64B
104/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
105#define L1D_LINES_PER_TAG 1
106#define L1D_SIZE_KB_AMD 64
107#define L1D_ASSOCIATIVITY_AMD 2
108
109/* L1 instruction cache: */
110#define L1I_LINE_SIZE 64
111#define L1I_ASSOCIATIVITY 8
112#define L1I_SETS 64
113#define L1I_PARTITIONS 1
114/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
115#define L1I_DESCRIPTOR CPUID_2_L1I_32KB_8WAY_64B
116/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
117#define L1I_LINES_PER_TAG 1
118#define L1I_SIZE_KB_AMD 64
119#define L1I_ASSOCIATIVITY_AMD 2
120
121/* Level 2 unified cache: */
122#define L2_LINE_SIZE 64
123#define L2_ASSOCIATIVITY 16
124#define L2_SETS 4096
125#define L2_PARTITIONS 1
126/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 4MiB */
127/*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
128#define L2_DESCRIPTOR CPUID_2_L2_2MB_8WAY_64B
129/*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
130#define L2_LINES_PER_TAG 1
131#define L2_SIZE_KB_AMD 512
132
133/* No L3 cache: */
134#define L3_SIZE_KB 0 /* disabled */
135#define L3_ASSOCIATIVITY 0 /* disabled */
136#define L3_LINES_PER_TAG 0 /* disabled */
137#define L3_LINE_SIZE 0 /* disabled */
138
139/* TLB definitions: */
140
141#define L1_DTLB_2M_ASSOC 1
142#define L1_DTLB_2M_ENTRIES 255
143#define L1_DTLB_4K_ASSOC 1
144#define L1_DTLB_4K_ENTRIES 255
145
146#define L1_ITLB_2M_ASSOC 1
147#define L1_ITLB_2M_ENTRIES 255
148#define L1_ITLB_4K_ASSOC 1
149#define L1_ITLB_4K_ENTRIES 255
150
151#define L2_DTLB_2M_ASSOC 0 /* disabled */
152#define L2_DTLB_2M_ENTRIES 0 /* disabled */
153#define L2_DTLB_4K_ASSOC 4
154#define L2_DTLB_4K_ENTRIES 512
155
156#define L2_ITLB_2M_ASSOC 0 /* disabled */
157#define L2_ITLB_2M_ENTRIES 0 /* disabled */
158#define L2_ITLB_4K_ASSOC 4
159#define L2_ITLB_4K_ENTRIES 512
160
161
162
99b88a17
IM		 163static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
164 uint32_t vendor2, uint32_t vendor3)
165{
166 int i;
167 for (i = 0; i < 4; i++) {
168 dst[i] = vendor1 >> (8 * i);
169 dst[i + 4] = vendor2 >> (8 * i);
170 dst[i + 8] = vendor3 >> (8 * i);
171 }
172 dst[CPUID_VENDOR_SZ] = '\0';
173}
174
c6dc6f63
AP		 175/* feature flags taken from "Intel Processor Identification and the CPUID
176 * Instruction" and AMD's "CPUID Specification". In cases of disagreement
177 * between feature naming conventions, aliases may be added.
178 */
179static const char *feature_name[] = {
180 "fpu", "vme", "de", "pse",
181 "tsc", "msr", "pae", "mce",
182 "cx8", "apic", NULL, "sep",
183 "mtrr", "pge", "mca", "cmov",
184 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
185 NULL, "ds" /* Intel dts */, "acpi", "mmx",
186 "fxsr", "sse", "sse2", "ss",
187 "ht" /* Intel htt */, "tm", "ia64", "pbe",
188};
189static const char *ext_feature_name[] = {
f370be3c 190 "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
e117f772 191 "ds_cpl", "vmx", "smx", "est",
c6dc6f63 192 "tm2", "ssse3", "cid", NULL,
e117f772 193 "fma", "cx16", "xtpr", "pdcm",
434acb81 194 NULL, "pcid", "dca", "sse4.1|sse4_1",
e117f772 195 "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
eaf3f097 196 "tsc-deadline", "aes", "xsave", "osxsave",
c8acc380 197 "avx", "f16c", "rdrand", "hypervisor",
c6dc6f63 198};
3b671a40
EH		 199/* Feature names that are already defined on feature_name[] but are set on
200 * CPUID[8000_0001].EDX on AMD CPUs don't have their names on
201 * ext2_feature_name[]. They are copied automatically to cpuid_ext2_features
202 * if and only if CPU vendor is AMD.
203 */
c6dc6f63 204static const char *ext2_feature_name[] = {
3b671a40
EH		 205 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
206 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
207 NULL /* cx8 */ /* AMD CMPXCHG8B */, NULL /* apic */, NULL, "syscall",
208 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
209 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
210 "nx|xd", NULL, "mmxext", NULL /* mmx */,
211 NULL /* fxsr */, "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
01f590d5 212 NULL, "lm|i64", "3dnowext", "3dnow",
c6dc6f63
AP		 213};
214static const char *ext3_feature_name[] = {
215 "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
216 "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
e117f772 217 "3dnowprefetch", "osvw", "ibs", "xop",
c8acc380
AP		 218 "skinit", "wdt", NULL, "lwp",
219 "fma4", "tce", NULL, "nodeid_msr",
220 NULL, "tbm", "topoext", "perfctr_core",
221 "perfctr_nb", NULL, NULL, NULL,
c6dc6f63
AP		 222 NULL, NULL, NULL, NULL,
223};
224
89e49c8b
EH		 225static const char *ext4_feature_name[] = {
226 NULL, NULL, "xstore", "xstore-en",
227 NULL, NULL, "xcrypt", "xcrypt-en",
228 "ace2", "ace2-en", "phe", "phe-en",
229 "pmm", "pmm-en", NULL, NULL,
230 NULL, NULL, NULL, NULL,
231 NULL, NULL, NULL, NULL,
232 NULL, NULL, NULL, NULL,
233 NULL, NULL, NULL, NULL,
234};
235
c6dc6f63 236static const char *kvm_feature_name[] = {
c3d39807 237 "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock",
f010bc64 238 "kvm_asyncpf", "kvm_steal_time", "kvm_pv_eoi", "kvm_pv_unhalt",
c3d39807
DS		 239 NULL, NULL, NULL, NULL,
240 NULL, NULL, NULL, NULL,
241 NULL, NULL, NULL, NULL,
242 NULL, NULL, NULL, NULL,
8248c36a 243 "kvmclock-stable-bit", NULL, NULL, NULL,
c3d39807 244 NULL, NULL, NULL, NULL,
c6dc6f63
AP		 245};
246
296acb64
JR		 247static const char *svm_feature_name[] = {
248 "npt", "lbrv", "svm_lock", "nrip_save",
249 "tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists",
250 NULL, NULL, "pause_filter", NULL,
251 "pfthreshold", NULL, NULL, NULL,
252 NULL, NULL, NULL, NULL,
253 NULL, NULL, NULL, NULL,
254 NULL, NULL, NULL, NULL,
255 NULL, NULL, NULL, NULL,
256};
257
a9321a4d 258static const char *cpuid_7_0_ebx_feature_name[] = {
7b458bfd 259 "fsgsbase", "tsc_adjust", NULL, "bmi1", "hle", "avx2", NULL, "smep",
5bd8ff07 260 "bmi2", "erms", "invpcid", "rtm", NULL, NULL, "mpx", NULL,
f7fda280
XG		 261 "avx512f", NULL, "rdseed", "adx", "smap", NULL, "pcommit", "clflushopt",
262 "clwb", NULL, "avx512pf", "avx512er", "avx512cd", NULL, NULL, NULL,
a9321a4d
PA		 263};
264
f74eefe0
HH		 265static const char *cpuid_7_0_ecx_feature_name[] = {
266 NULL, NULL, NULL, "pku",
267 "ospke", NULL, NULL, NULL,
268 NULL, NULL, NULL, NULL,
269 NULL, NULL, NULL, NULL,
270 NULL, NULL, NULL, NULL,
271 NULL, NULL, NULL, NULL,
272 NULL, NULL, NULL, NULL,
273 NULL, NULL, NULL, NULL,
274};
275
303752a9
MT		 276static const char *cpuid_apm_edx_feature_name[] = {
277 NULL, NULL, NULL, NULL,
278 NULL, NULL, NULL, NULL,
279 "invtsc", NULL, NULL, NULL,
280 NULL, NULL, NULL, NULL,
281 NULL, NULL, NULL, NULL,
282 NULL, NULL, NULL, NULL,
283 NULL, NULL, NULL, NULL,
284 NULL, NULL, NULL, NULL,
285};
286
0bb0b2d2
PB		 287static const char *cpuid_xsave_feature_name[] = {
288 "xsaveopt", "xsavec", "xgetbv1", "xsaves",
289 NULL, NULL, NULL, NULL,
290 NULL, NULL, NULL, NULL,
291 NULL, NULL, NULL, NULL,
292 NULL, NULL, NULL, NULL,
293 NULL, NULL, NULL, NULL,
294 NULL, NULL, NULL, NULL,
295 NULL, NULL, NULL, NULL,
296};
297
28b8e4d0
JK		 298static const char *cpuid_6_feature_name[] = {
299 NULL, NULL, "arat", NULL,
300 NULL, NULL, NULL, NULL,
301 NULL, NULL, NULL, NULL,
302 NULL, NULL, NULL, NULL,
303 NULL, NULL, NULL, NULL,
304 NULL, NULL, NULL, NULL,
305 NULL, NULL, NULL, NULL,
306 NULL, NULL, NULL, NULL,
307};
308
621626ce
EH		 309#define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
310#define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
311 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
312#define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
313 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
314 CPUID_PSE36 | CPUID_FXSR)
315#define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
316#define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
317 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
318 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
319 CPUID_PAE | CPUID_SEP | CPUID_APIC)
320
321#define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
322 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
323 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
324 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
b6c5a6f0 325 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE)
621626ce
EH		 326 /* partly implemented:
327 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */
328 /* missing:
329 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
330#define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
331 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
332 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
19dc85db 333 CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \
621626ce
EH		 334 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR)
335 /* missing:
336 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
337 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
338 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
19dc85db
RH		 339 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_AVX,
340 CPUID_EXT_F16C, CPUID_EXT_RDRAND */
621626ce
EH		 341
342#ifdef TARGET_X86_64
343#define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM)
344#else
345#define TCG_EXT2_X86_64_FEATURES 0
346#endif
347
348#define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
349 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
350 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \
351 TCG_EXT2_X86_64_FEATURES)
352#define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
353 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
354#define TCG_EXT4_FEATURES 0
355#define TCG_SVM_FEATURES 0
356#define TCG_KVM_FEATURES 0
357#define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \
0c47242b
XG		 358 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \
359 CPUID_7_0_EBX_PCOMMIT | CPUID_7_0_EBX_CLFLUSHOPT | \
07929f2a 360 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE)
621626ce 361 /* missing:
07929f2a 362 CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
621626ce
EH		 363 CPUID_7_0_EBX_ERMS, CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
364 CPUID_7_0_EBX_RDSEED */
0f70ed47 365#define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_PKU | CPUID_7_0_ECX_OSPKE)
303752a9 366#define TCG_APM_FEATURES 0
28b8e4d0 367#define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT
c9cfe8f9
RH		 368#define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1)
369 /* missing:
370 CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */
621626ce 371
5ef57876
EH		 372typedef struct FeatureWordInfo {
373 const char **feat_names;
04d104b6
EH		 374 uint32_t cpuid_eax; /* Input EAX for CPUID */
375 bool cpuid_needs_ecx; /* CPUID instruction uses ECX as input */
376 uint32_t cpuid_ecx; /* Input ECX value for CPUID */
377 int cpuid_reg; /* output register (R_* constant) */
37ce3522 378 uint32_t tcg_features; /* Feature flags supported by TCG */
84f1b92f 379 uint32_t unmigratable_flags; /* Feature flags known to be unmigratable */
5ef57876
EH		 380} FeatureWordInfo;
381
382static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
bffd67b0
EH		 383 [FEAT_1_EDX] = {
384 .feat_names = feature_name,
385 .cpuid_eax = 1, .cpuid_reg = R_EDX,
37ce3522 386 .tcg_features = TCG_FEATURES,
bffd67b0
EH		 387 },
388 [FEAT_1_ECX] = {
389 .feat_names = ext_feature_name,
390 .cpuid_eax = 1, .cpuid_reg = R_ECX,
37ce3522 391 .tcg_features = TCG_EXT_FEATURES,
bffd67b0
EH		 392 },
393 [FEAT_8000_0001_EDX] = {
394 .feat_names = ext2_feature_name,
395 .cpuid_eax = 0x80000001, .cpuid_reg = R_EDX,
37ce3522 396 .tcg_features = TCG_EXT2_FEATURES,
bffd67b0
EH		 397 },
398 [FEAT_8000_0001_ECX] = {
399 .feat_names = ext3_feature_name,
400 .cpuid_eax = 0x80000001, .cpuid_reg = R_ECX,
37ce3522 401 .tcg_features = TCG_EXT3_FEATURES,
bffd67b0 402 },
89e49c8b
EH		 403 [FEAT_C000_0001_EDX] = {
404 .feat_names = ext4_feature_name,
405 .cpuid_eax = 0xC0000001, .cpuid_reg = R_EDX,
37ce3522 406 .tcg_features = TCG_EXT4_FEATURES,
89e49c8b 407 },
bffd67b0
EH		 408 [FEAT_KVM] = {
409 .feat_names = kvm_feature_name,
410 .cpuid_eax = KVM_CPUID_FEATURES, .cpuid_reg = R_EAX,
37ce3522 411 .tcg_features = TCG_KVM_FEATURES,
bffd67b0
EH		 412 },
413 [FEAT_SVM] = {
414 .feat_names = svm_feature_name,
415 .cpuid_eax = 0x8000000A, .cpuid_reg = R_EDX,
37ce3522 416 .tcg_features = TCG_SVM_FEATURES,
bffd67b0
EH		 417 },
418 [FEAT_7_0_EBX] = {
419 .feat_names = cpuid_7_0_ebx_feature_name,
04d104b6
EH		 420 .cpuid_eax = 7,
421 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
422 .cpuid_reg = R_EBX,
37ce3522 423 .tcg_features = TCG_7_0_EBX_FEATURES,
bffd67b0 424 },
f74eefe0
HH		 425 [FEAT_7_0_ECX] = {
426 .feat_names = cpuid_7_0_ecx_feature_name,
427 .cpuid_eax = 7,
428 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
429 .cpuid_reg = R_ECX,
430 .tcg_features = TCG_7_0_ECX_FEATURES,
431 },
303752a9
MT		 432 [FEAT_8000_0007_EDX] = {
433 .feat_names = cpuid_apm_edx_feature_name,
434 .cpuid_eax = 0x80000007,
435 .cpuid_reg = R_EDX,
436 .tcg_features = TCG_APM_FEATURES,
437 .unmigratable_flags = CPUID_APM_INVTSC,
438 },
0bb0b2d2
PB		 439 [FEAT_XSAVE] = {
440 .feat_names = cpuid_xsave_feature_name,
441 .cpuid_eax = 0xd,
442 .cpuid_needs_ecx = true, .cpuid_ecx = 1,
443 .cpuid_reg = R_EAX,
c9cfe8f9 444 .tcg_features = TCG_XSAVE_FEATURES,
0bb0b2d2 445 },
28b8e4d0
JK		 446 [FEAT_6_EAX] = {
447 .feat_names = cpuid_6_feature_name,
448 .cpuid_eax = 6, .cpuid_reg = R_EAX,
449 .tcg_features = TCG_6_EAX_FEATURES,
450 },
5ef57876
EH		 451};
452
8e8aba50
EH		 453typedef struct X86RegisterInfo32 {
454 /* Name of register */
455 const char *name;
456 /* QAPI enum value register */
457 X86CPURegister32 qapi_enum;
458} X86RegisterInfo32;
459
460#define REGISTER(reg) \
5d371f41 461 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
a443bc34 462static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
8e8aba50
EH		 463 REGISTER(EAX),
464 REGISTER(ECX),
465 REGISTER(EDX),
466 REGISTER(EBX),
467 REGISTER(ESP),
468 REGISTER(EBP),
469 REGISTER(ESI),
470 REGISTER(EDI),
471};
472#undef REGISTER
473
f4f1110e 474const ExtSaveArea x86_ext_save_areas[] = {
cfc3b074
PB		 475 [XSTATE_YMM_BIT] =
476 { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
ee1b09f6
EH		 477 .offset = offsetof(X86XSaveArea, avx_state),
478 .size = sizeof(XSaveAVX) },
cfc3b074
PB		 479 [XSTATE_BNDREGS_BIT] =
480 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
ee1b09f6
EH		 481 .offset = offsetof(X86XSaveArea, bndreg_state),
482 .size = sizeof(XSaveBNDREG) },
cfc3b074
PB		 483 [XSTATE_BNDCSR_BIT] =
484 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
ee1b09f6
EH		 485 .offset = offsetof(X86XSaveArea, bndcsr_state),
486 .size = sizeof(XSaveBNDCSR) },
cfc3b074
PB		 487 [XSTATE_OPMASK_BIT] =
488 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6
EH		 489 .offset = offsetof(X86XSaveArea, opmask_state),
490 .size = sizeof(XSaveOpmask) },
cfc3b074
PB		 491 [XSTATE_ZMM_Hi256_BIT] =
492 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6
EH		 493 .offset = offsetof(X86XSaveArea, zmm_hi256_state),
494 .size = sizeof(XSaveZMM_Hi256) },
cfc3b074
PB		 495 [XSTATE_Hi16_ZMM_BIT] =
496 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6
EH		 497 .offset = offsetof(X86XSaveArea, hi16_zmm_state),
498 .size = sizeof(XSaveHi16_ZMM) },
cfc3b074
PB		 499 [XSTATE_PKRU_BIT] =
500 { .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU,
ee1b09f6
EH		 501 .offset = offsetof(X86XSaveArea, pkru_state),
502 .size = sizeof(XSavePKRU) },
2560f19f 503};
8e8aba50 504
8b4beddc
EH		 505const char *get_register_name_32(unsigned int reg)
506{
31ccdde2 507 if (reg >= CPU_NB_REGS32) {
8b4beddc
EH		 508 return NULL;
509 }
8e8aba50 510 return x86_reg_info_32[reg].name;
8b4beddc
EH		 511}
512
84f1b92f
EH		 513/*
514 * Returns the set of feature flags that are supported and migratable by
515 * QEMU, for a given FeatureWord.
516 */
517static uint32_t x86_cpu_get_migratable_flags(FeatureWord w)
518{
519 FeatureWordInfo *wi = &feature_word_info[w];
520 uint32_t r = 0;
521 int i;
522
523 for (i = 0; i < 32; i++) {
524 uint32_t f = 1U << i;
525 /* If the feature name is unknown, it is not supported by QEMU yet */
526 if (!wi->feat_names[i]) {
527 continue;
528 }
529 /* Skip features known to QEMU, but explicitly marked as unmigratable */
530 if (wi->unmigratable_flags & f) {
531 continue;
532 }
533 r |= f;
534 }
535 return r;
536}
537
bb44e0d1
JK		 538void host_cpuid(uint32_t function, uint32_t count,
539 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
bdde476a 540{
a1fd24af
AL		 541 uint32_t vec[4];
542
543#ifdef __x86_64__
544 asm volatile("cpuid"
545 : "=a"(vec[0]), "=b"(vec[1]),
546 "=c"(vec[2]), "=d"(vec[3])
547 : "0"(function), "c"(count) : "cc");
c1f41226 548#elif defined(__i386__)
a1fd24af
AL		 549 asm volatile("pusha \n\t"
550 "cpuid \n\t"
551 "mov %%eax, 0(%2) \n\t"
552 "mov %%ebx, 4(%2) \n\t"
553 "mov %%ecx, 8(%2) \n\t"
554 "mov %%edx, 12(%2) \n\t"
555 "popa"
556 : : "a"(function), "c"(count), "S"(vec)
557 : "memory", "cc");
c1f41226
EH		 558#else
559 abort();
a1fd24af
AL		 560#endif
561
bdde476a 562 if (eax)
a1fd24af 563 *eax = vec[0];
bdde476a 564 if (ebx)
a1fd24af 565 *ebx = vec[1];
bdde476a 566 if (ecx)
a1fd24af 567 *ecx = vec[2];
bdde476a 568 if (edx)
a1fd24af 569 *edx = vec[3];
bdde476a 570}
c6dc6f63
AP		 571
572#define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
573
574/* general substring compare of *[s1..e1) and *[s2..e2). sx is start of
575 * a substring. ex if !NULL points to the first char after a substring,
576 * otherwise the string is assumed to sized by a terminating nul.
577 * Return lexical ordering of *s1:*s2.
578 */
8f9d989c
CF		 579static int sstrcmp(const char *s1, const char *e1,
580 const char *s2, const char *e2)
c6dc6f63
AP		 581{
582 for (;;) {
583 if (!*s1 || !*s2 || *s1 != *s2)
584 return (*s1 - *s2);
585 ++s1, ++s2;
586 if (s1 == e1 && s2 == e2)
587 return (0);
588 else if (s1 == e1)
589 return (*s2);
590 else if (s2 == e2)
591 return (*s1);
592 }
593}
594
595/* compare *[s..e) to *altstr. *altstr may be a simple string or multiple
596 * '|' delimited (possibly empty) strings in which case search for a match
597 * within the alternatives proceeds left to right. Return 0 for success,
598 * non-zero otherwise.
599 */
600static int altcmp(const char *s, const char *e, const char *altstr)
601{
602 const char *p, *q;
603
604 for (q = p = altstr; ; ) {
605 while (*p && *p != '|')
606 ++p;
607 if ((q == p && !*s) || (q != p && !sstrcmp(s, e, q, p)))
608 return (0);
609 if (!*p)
610 return (1);
611 else
612 q = ++p;
613 }
614}
615
616/* search featureset for flag *[s..e), if found set corresponding bit in
e41e0fc6 617 * *pval and return true, otherwise return false
c6dc6f63 618 */
e41e0fc6
JK		 619static bool lookup_feature(uint32_t *pval, const char *s, const char *e,
620 const char **featureset)
c6dc6f63
AP		 621{
622 uint32_t mask;
623 const char **ppc;
e41e0fc6 624 bool found = false;
c6dc6f63 625
e41e0fc6 626 for (mask = 1, ppc = featureset; mask; mask <<= 1, ++ppc) {
c6dc6f63
AP		 627 if (*ppc && !altcmp(s, e, *ppc)) {
628 *pval |= mask;
e41e0fc6 629 found = true;
c6dc6f63 630 }
e41e0fc6
JK		 631 }
632 return found;
c6dc6f63
AP		 633}
634
5ef57876 635static void add_flagname_to_bitmaps(const char *flagname,
c00c94ab
EH		 636 FeatureWordArray words,
637 Error **errp)
c6dc6f63 638{
5ef57876
EH		 639 FeatureWord w;
640 for (w = 0; w < FEATURE_WORDS; w++) {
641 FeatureWordInfo *wi = &feature_word_info[w];
642 if (wi->feat_names &&
643 lookup_feature(&words[w], flagname, NULL, wi->feat_names)) {
644 break;
645 }
646 }
647 if (w == FEATURE_WORDS) {
c00c94ab 648 error_setg(errp, "CPU feature %s not found", flagname);
5ef57876 649 }
c6dc6f63
AP		 650}
651
d940ee9b
EH		 652/* CPU class name definitions: */
653
654#define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU
655#define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX)
656
657/* Return type name for a given CPU model name
658 * Caller is responsible for freeing the returned string.
659 */
660static char *x86_cpu_type_name(const char *model_name)
661{
662 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name);
663}
664
500050d1
AF		 665static ObjectClass *x86_cpu_class_by_name(const char *cpu_model)
666{
d940ee9b
EH		 667 ObjectClass *oc;
668 char *typename;
669
500050d1
AF		 670 if (cpu_model == NULL) {
671 return NULL;
672 }
673
d940ee9b
EH		 674 typename = x86_cpu_type_name(cpu_model);
675 oc = object_class_by_name(typename);
676 g_free(typename);
677 return oc;
500050d1
AF		 678}
679
d940ee9b 680struct X86CPUDefinition {
c6dc6f63
AP		 681 const char *name;
682 uint32_t level;
90e4b0c3
EH		 683 uint32_t xlevel;
684 uint32_t xlevel2;
99b88a17
IM		 685 /* vendor is zero-terminated, 12 character ASCII string */
686 char vendor[CPUID_VENDOR_SZ + 1];
c6dc6f63
AP		 687 int family;
688 int model;
689 int stepping;
0514ef2f 690 FeatureWordArray features;
c6dc6f63 691 char model_id[48];
d940ee9b 692};
c6dc6f63 693
9576de75 694static X86CPUDefinition builtin_x86_defs[] = {
c6dc6f63
AP		 695 {
696 .name = "qemu64",
3046bb5d 697 .level = 0xd,
99b88a17 698 .vendor = CPUID_VENDOR_AMD,
c6dc6f63 699 .family = 6,
f8e6a11a 700 .model = 6,
c6dc6f63 701 .stepping = 3,
0514ef2f 702 .features[FEAT_1_EDX] =
27861ecc 703 PPRO_FEATURES |
c6dc6f63 704 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
c6dc6f63 705 CPUID_PSE36,
0514ef2f 706 .features[FEAT_1_ECX] =
6aa91e4a 707 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
0514ef2f 708 .features[FEAT_8000_0001_EDX] =
c6dc6f63 709 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 710 .features[FEAT_8000_0001_ECX] =
71195672 711 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM,
c6dc6f63 712 .xlevel = 0x8000000A,
9cf2cc3d 713 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63
AP		 714 },
715 {
716 .name = "phenom",
717 .level = 5,
99b88a17 718 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 719 .family = 16,
720 .model = 2,
721 .stepping = 3,
b9fc20bc 722 /* Missing: CPUID_HT */
0514ef2f 723 .features[FEAT_1_EDX] =
27861ecc 724 PPRO_FEATURES |
c6dc6f63 725 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
b9fc20bc 726 CPUID_PSE36 | CPUID_VME,
0514ef2f 727 .features[FEAT_1_ECX] =
27861ecc 728 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
c6dc6f63 729 CPUID_EXT_POPCNT,
0514ef2f 730 .features[FEAT_8000_0001_EDX] =
c6dc6f63
AP		 731 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
732 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
8560efed 733 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
c6dc6f63
AP		 734 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
735 CPUID_EXT3_CR8LEG,
736 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
737 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
0514ef2f 738 .features[FEAT_8000_0001_ECX] =
27861ecc 739 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
c6dc6f63 740 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
b9fc20bc 741 /* Missing: CPUID_SVM_LBRV */
0514ef2f 742 .features[FEAT_SVM] =
b9fc20bc 743 CPUID_SVM_NPT,
c6dc6f63
AP		 744 .xlevel = 0x8000001A,
745 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
746 },
747 {
748 .name = "core2duo",
749 .level = 10,
99b88a17 750 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 751 .family = 6,
752 .model = 15,
753 .stepping = 11,
b9fc20bc 754 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 755 .features[FEAT_1_EDX] =
27861ecc 756 PPRO_FEATURES |
c6dc6f63 757 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
b9fc20bc
EH		 758 CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS,
759 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST,
e93abc14 760 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */
0514ef2f 761 .features[FEAT_1_ECX] =
27861ecc 762 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
e93abc14 763 CPUID_EXT_CX16,
0514ef2f 764 .features[FEAT_8000_0001_EDX] =
27861ecc 765 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 766 .features[FEAT_8000_0001_ECX] =
27861ecc 767 CPUID_EXT3_LAHF_LM,
c6dc6f63
AP		 768 .xlevel = 0x80000008,
769 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
770 },
771 {
772 .name = "kvm64",
3046bb5d 773 .level = 0xd,
99b88a17 774 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 775 .family = 15,
776 .model = 6,
777 .stepping = 1,
b3a4f0b1 778 /* Missing: CPUID_HT */
0514ef2f 779 .features[FEAT_1_EDX] =
b3a4f0b1 780 PPRO_FEATURES | CPUID_VME |
c6dc6f63
AP		 781 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
782 CPUID_PSE36,
783 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
0514ef2f 784 .features[FEAT_1_ECX] =
27861ecc 785 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
c6dc6f63 786 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
0514ef2f 787 .features[FEAT_8000_0001_EDX] =
c6dc6f63
AP		 788 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
789 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
790 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
791 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
792 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
0514ef2f 793 .features[FEAT_8000_0001_ECX] =
27861ecc 794 0,
c6dc6f63
AP		 795 .xlevel = 0x80000008,
796 .model_id = "Common KVM processor"
797 },
c6dc6f63
AP		 798 {
799 .name = "qemu32",
800 .level = 4,
99b88a17 801 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 802 .family = 6,
f8e6a11a 803 .model = 6,
c6dc6f63 804 .stepping = 3,
0514ef2f 805 .features[FEAT_1_EDX] =
27861ecc 806 PPRO_FEATURES,
0514ef2f 807 .features[FEAT_1_ECX] =
6aa91e4a 808 CPUID_EXT_SSE3,
58012d66 809 .xlevel = 0x80000004,
9cf2cc3d 810 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63 811 },
eafaf1e5
AP		 812 {
813 .name = "kvm32",
814 .level = 5,
99b88a17 815 .vendor = CPUID_VENDOR_INTEL,
eafaf1e5
AP		 816 .family = 15,
817 .model = 6,
818 .stepping = 1,
0514ef2f 819 .features[FEAT_1_EDX] =
b3a4f0b1 820 PPRO_FEATURES | CPUID_VME |
eafaf1e5 821 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
0514ef2f 822 .features[FEAT_1_ECX] =
27861ecc 823 CPUID_EXT_SSE3,
0514ef2f 824 .features[FEAT_8000_0001_ECX] =
27861ecc 825 0,
eafaf1e5
AP		 826 .xlevel = 0x80000008,
827 .model_id = "Common 32-bit KVM processor"
828 },
c6dc6f63
AP		 829 {
830 .name = "coreduo",
831 .level = 10,
99b88a17 832 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 833 .family = 6,
834 .model = 14,
835 .stepping = 8,
b9fc20bc 836 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 837 .features[FEAT_1_EDX] =
27861ecc 838 PPRO_FEATURES | CPUID_VME |
b9fc20bc
EH		 839 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI |
840 CPUID_SS,
841 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR,
e93abc14 842 * CPUID_EXT_PDCM, CPUID_EXT_VMX */
0514ef2f 843 .features[FEAT_1_ECX] =
e93abc14 844 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR,
0514ef2f 845 .features[FEAT_8000_0001_EDX] =
27861ecc 846 CPUID_EXT2_NX,
c6dc6f63
AP		 847 .xlevel = 0x80000008,
848 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
849 },
850 {
851 .name = "486",
58012d66 852 .level = 1,
99b88a17 853 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 854 .family = 4,
b2a856d9 855 .model = 8,
c6dc6f63 856 .stepping = 0,
0514ef2f 857 .features[FEAT_1_EDX] =
27861ecc 858 I486_FEATURES,
c6dc6f63
AP		 859 .xlevel = 0,
860 },
861 {
862 .name = "pentium",
863 .level = 1,
99b88a17 864 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 865 .family = 5,
866 .model = 4,
867 .stepping = 3,
0514ef2f 868 .features[FEAT_1_EDX] =
27861ecc 869 PENTIUM_FEATURES,
c6dc6f63
AP		 870 .xlevel = 0,
871 },
872 {
873 .name = "pentium2",
874 .level = 2,
99b88a17 875 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 876 .family = 6,
877 .model = 5,
878 .stepping = 2,
0514ef2f 879 .features[FEAT_1_EDX] =
27861ecc 880 PENTIUM2_FEATURES,
c6dc6f63
AP		 881 .xlevel = 0,
882 },
883 {
884 .name = "pentium3",
3046bb5d 885 .level = 3,
99b88a17 886 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 887 .family = 6,
888 .model = 7,
889 .stepping = 3,
0514ef2f 890 .features[FEAT_1_EDX] =
27861ecc 891 PENTIUM3_FEATURES,
c6dc6f63
AP		 892 .xlevel = 0,
893 },
894 {
895 .name = "athlon",
896 .level = 2,
99b88a17 897 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 898 .family = 6,
899 .model = 2,
900 .stepping = 3,
0514ef2f 901 .features[FEAT_1_EDX] =
27861ecc 902 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
60032ac0 903 CPUID_MCA,
0514ef2f 904 .features[FEAT_8000_0001_EDX] =
60032ac0 905 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
c6dc6f63 906 .xlevel = 0x80000008,
9cf2cc3d 907 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63
AP		 908 },
909 {
910 .name = "n270",
3046bb5d 911 .level = 10,
99b88a17 912 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 913 .family = 6,
914 .model = 28,
915 .stepping = 2,
b9fc20bc 916 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 917 .features[FEAT_1_EDX] =
27861ecc 918 PPRO_FEATURES |
b9fc20bc
EH		 919 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME |
920 CPUID_ACPI | CPUID_SS,
c6dc6f63 921 /* Some CPUs got no CPUID_SEP */
b9fc20bc
EH		 922 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2,
923 * CPUID_EXT_XTPR */
0514ef2f 924 .features[FEAT_1_ECX] =
27861ecc 925 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
4458c236 926 CPUID_EXT_MOVBE,
0514ef2f 927 .features[FEAT_8000_0001_EDX] =
60032ac0 928 CPUID_EXT2_NX,
0514ef2f 929 .features[FEAT_8000_0001_ECX] =
27861ecc 930 CPUID_EXT3_LAHF_LM,
3046bb5d 931 .xlevel = 0x80000008,
c6dc6f63
AP		 932 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
933 },
3eca4642
EH		 934 {
935 .name = "Conroe",
3046bb5d 936 .level = 10,
99b88a17 937 .vendor = CPUID_VENDOR_INTEL,
3eca4642 938 .family = 6,
ffce9ebb 939 .model = 15,
3eca4642 940 .stepping = 3,
0514ef2f 941 .features[FEAT_1_EDX] =
b3a4f0b1 942 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 943 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
944 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
945 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
946 CPUID_DE | CPUID_FP87,
0514ef2f 947 .features[FEAT_1_ECX] =
27861ecc 948 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 949 .features[FEAT_8000_0001_EDX] =
27861ecc 950 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 951 .features[FEAT_8000_0001_ECX] =
27861ecc 952 CPUID_EXT3_LAHF_LM,
3046bb5d 953 .xlevel = 0x80000008,
3eca4642
EH		 954 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
955 },
956 {
957 .name = "Penryn",
3046bb5d 958 .level = 10,
99b88a17 959 .vendor = CPUID_VENDOR_INTEL,
3eca4642 960 .family = 6,
ffce9ebb 961 .model = 23,
3eca4642 962 .stepping = 3,
0514ef2f 963 .features[FEAT_1_EDX] =
b3a4f0b1 964 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 965 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
966 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
967 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
968 CPUID_DE | CPUID_FP87,
0514ef2f 969 .features[FEAT_1_ECX] =
27861ecc 970 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
b3fb3a20 971 CPUID_EXT_SSE3,
0514ef2f 972 .features[FEAT_8000_0001_EDX] =
27861ecc 973 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 974 .features[FEAT_8000_0001_ECX] =
27861ecc 975 CPUID_EXT3_LAHF_LM,
3046bb5d 976 .xlevel = 0x80000008,
3eca4642
EH		 977 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
978 },
979 {
980 .name = "Nehalem",
3046bb5d 981 .level = 11,
99b88a17 982 .vendor = CPUID_VENDOR_INTEL,
3eca4642 983 .family = 6,
ffce9ebb 984 .model = 26,
3eca4642 985 .stepping = 3,
0514ef2f 986 .features[FEAT_1_EDX] =
b3a4f0b1 987 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 988 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
989 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
990 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
991 CPUID_DE | CPUID_FP87,
0514ef2f 992 .features[FEAT_1_ECX] =
27861ecc 993 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
b3fb3a20 994 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 995 .features[FEAT_8000_0001_EDX] =
27861ecc 996 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 997 .features[FEAT_8000_0001_ECX] =
27861ecc 998 CPUID_EXT3_LAHF_LM,
3046bb5d 999 .xlevel = 0x80000008,
3eca4642
EH		 1000 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
1001 },
1002 {
1003 .name = "Westmere",
1004 .level = 11,
99b88a17 1005 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 1006 .family = 6,
1007 .model = 44,
1008 .stepping = 1,
0514ef2f 1009 .features[FEAT_1_EDX] =
b3a4f0b1 1010 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1011 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1012 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1013 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1014 CPUID_DE | CPUID_FP87,
0514ef2f 1015 .features[FEAT_1_ECX] =
27861ecc 1016 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
b3fb3a20
EH		 1017 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1018 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
0514ef2f 1019 .features[FEAT_8000_0001_EDX] =
27861ecc 1020 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 1021 .features[FEAT_8000_0001_ECX] =
27861ecc 1022 CPUID_EXT3_LAHF_LM,
28b8e4d0
JK		 1023 .features[FEAT_6_EAX] =
1024 CPUID_6_EAX_ARAT,
3046bb5d 1025 .xlevel = 0x80000008,
3eca4642
EH		 1026 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
1027 },
1028 {
1029 .name = "SandyBridge",
1030 .level = 0xd,
99b88a17 1031 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 1032 .family = 6,
1033 .model = 42,
1034 .stepping = 1,
0514ef2f 1035 .features[FEAT_1_EDX] =
b3a4f0b1 1036 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1037 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1038 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1039 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1040 CPUID_DE | CPUID_FP87,
0514ef2f 1041 .features[FEAT_1_ECX] =
27861ecc 1042 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 1043 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1044 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1045 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1046 CPUID_EXT_SSE3,
0514ef2f 1047 .features[FEAT_8000_0001_EDX] =
27861ecc 1048 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
b3fb3a20 1049 CPUID_EXT2_SYSCALL,
0514ef2f 1050 .features[FEAT_8000_0001_ECX] =
27861ecc 1051 CPUID_EXT3_LAHF_LM,
0bb0b2d2
PB		 1052 .features[FEAT_XSAVE] =
1053 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1054 .features[FEAT_6_EAX] =
1055 CPUID_6_EAX_ARAT,
3046bb5d 1056 .xlevel = 0x80000008,
3eca4642
EH		 1057 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
1058 },
2f9ac42a
PB		 1059 {
1060 .name = "IvyBridge",
1061 .level = 0xd,
1062 .vendor = CPUID_VENDOR_INTEL,
1063 .family = 6,
1064 .model = 58,
1065 .stepping = 9,
1066 .features[FEAT_1_EDX] =
1067 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1068 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1069 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1070 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1071 CPUID_DE | CPUID_FP87,
1072 .features[FEAT_1_ECX] =
1073 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1074 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1075 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1076 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1077 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1078 .features[FEAT_7_0_EBX] =
1079 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP |
1080 CPUID_7_0_EBX_ERMS,
1081 .features[FEAT_8000_0001_EDX] =
1082 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1083 CPUID_EXT2_SYSCALL,
1084 .features[FEAT_8000_0001_ECX] =
1085 CPUID_EXT3_LAHF_LM,
1086 .features[FEAT_XSAVE] =
1087 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1088 .features[FEAT_6_EAX] =
1089 CPUID_6_EAX_ARAT,
3046bb5d 1090 .xlevel = 0x80000008,
2f9ac42a
PB		 1091 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)",
1092 },
37507094 1093 {
a356850b
EH		 1094 .name = "Haswell-noTSX",
1095 .level = 0xd,
1096 .vendor = CPUID_VENDOR_INTEL,
1097 .family = 6,
1098 .model = 60,
1099 .stepping = 1,
1100 .features[FEAT_1_EDX] =
1101 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1102 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1103 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1104 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1105 CPUID_DE | CPUID_FP87,
1106 .features[FEAT_1_ECX] =
1107 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1108 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1109 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1110 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1111 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1112 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1113 .features[FEAT_8000_0001_EDX] =
1114 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1115 CPUID_EXT2_SYSCALL,
1116 .features[FEAT_8000_0001_ECX] =
becb6667 1117 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
a356850b
EH		 1118 .features[FEAT_7_0_EBX] =
1119 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1120 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1121 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID,
1122 .features[FEAT_XSAVE] =
1123 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1124 .features[FEAT_6_EAX] =
1125 CPUID_6_EAX_ARAT,
3046bb5d 1126 .xlevel = 0x80000008,
a356850b
EH		 1127 .model_id = "Intel Core Processor (Haswell, no TSX)",
1128 }, {
37507094
EH		 1129 .name = "Haswell",
1130 .level = 0xd,
99b88a17 1131 .vendor = CPUID_VENDOR_INTEL,
37507094
EH		 1132 .family = 6,
1133 .model = 60,
1134 .stepping = 1,
0514ef2f 1135 .features[FEAT_1_EDX] =
b3a4f0b1 1136 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1137 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1138 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1139 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1140 CPUID_DE | CPUID_FP87,
0514ef2f 1141 .features[FEAT_1_ECX] =
27861ecc 1142 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 1143 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1144 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1145 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1146 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
78a611f1 1147 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
0514ef2f 1148 .features[FEAT_8000_0001_EDX] =
27861ecc 1149 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
b3fb3a20 1150 CPUID_EXT2_SYSCALL,
0514ef2f 1151 .features[FEAT_8000_0001_ECX] =
becb6667 1152 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
0514ef2f 1153 .features[FEAT_7_0_EBX] =
27861ecc 1154 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1ee91598
EH		 1155 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1156 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1157 CPUID_7_0_EBX_RTM,
0bb0b2d2
PB		 1158 .features[FEAT_XSAVE] =
1159 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1160 .features[FEAT_6_EAX] =
1161 CPUID_6_EAX_ARAT,
3046bb5d 1162 .xlevel = 0x80000008,
37507094
EH		 1163 .model_id = "Intel Core Processor (Haswell)",
1164 },
a356850b
EH		 1165 {
1166 .name = "Broadwell-noTSX",
1167 .level = 0xd,
1168 .vendor = CPUID_VENDOR_INTEL,
1169 .family = 6,
1170 .model = 61,
1171 .stepping = 2,
1172 .features[FEAT_1_EDX] =
1173 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1174 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1175 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1176 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1177 CPUID_DE | CPUID_FP87,
1178 .features[FEAT_1_ECX] =
1179 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1180 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1181 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1182 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1183 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1184 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1185 .features[FEAT_8000_0001_EDX] =
1186 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1187 CPUID_EXT2_SYSCALL,
1188 .features[FEAT_8000_0001_ECX] =
becb6667 1189 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
a356850b
EH		 1190 .features[FEAT_7_0_EBX] =
1191 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1192 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1193 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1194 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
1195 CPUID_7_0_EBX_SMAP,
1196 .features[FEAT_XSAVE] =
1197 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1198 .features[FEAT_6_EAX] =
1199 CPUID_6_EAX_ARAT,
3046bb5d 1200 .xlevel = 0x80000008,
a356850b
EH		 1201 .model_id = "Intel Core Processor (Broadwell, no TSX)",
1202 },
ece01354
EH		 1203 {
1204 .name = "Broadwell",
1205 .level = 0xd,
1206 .vendor = CPUID_VENDOR_INTEL,
1207 .family = 6,
1208 .model = 61,
1209 .stepping = 2,
1210 .features[FEAT_1_EDX] =
b3a4f0b1 1211 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
ece01354
EH		 1212 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1213 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1214 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1215 CPUID_DE | CPUID_FP87,
1216 .features[FEAT_1_ECX] =
1217 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1218 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1219 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1220 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1221 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
78a611f1 1222 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
ece01354
EH		 1223 .features[FEAT_8000_0001_EDX] =
1224 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1225 CPUID_EXT2_SYSCALL,
1226 .features[FEAT_8000_0001_ECX] =
becb6667 1227 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
ece01354
EH		 1228 .features[FEAT_7_0_EBX] =
1229 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1ee91598 1230 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
ece01354 1231 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1ee91598 1232 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
ece01354 1233 CPUID_7_0_EBX_SMAP,
0bb0b2d2
PB		 1234 .features[FEAT_XSAVE] =
1235 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1236 .features[FEAT_6_EAX] =
1237 CPUID_6_EAX_ARAT,
3046bb5d 1238 .xlevel = 0x80000008,
ece01354
EH		 1239 .model_id = "Intel Core Processor (Broadwell)",
1240 },
f6f949e9
EH		 1241 {
1242 .name = "Skylake-Client",
1243 .level = 0xd,
1244 .vendor = CPUID_VENDOR_INTEL,
1245 .family = 6,
1246 .model = 94,
1247 .stepping = 3,
1248 .features[FEAT_1_EDX] =
1249 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1250 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1251 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1252 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1253 CPUID_DE | CPUID_FP87,
1254 .features[FEAT_1_ECX] =
1255 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1256 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1257 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1258 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1259 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1260 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1261 .features[FEAT_8000_0001_EDX] =
1262 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1263 CPUID_EXT2_SYSCALL,
1264 .features[FEAT_8000_0001_ECX] =
1265 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
1266 .features[FEAT_7_0_EBX] =
1267 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1268 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1269 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1270 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
1271 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_MPX,
1272 /* Missing: XSAVES (not supported by some Linux versions,
1273 * including v4.1 to v4.6).
1274 * KVM doesn't yet expose any XSAVES state save component,
1275 * and the only one defined in Skylake (processor tracing)
1276 * probably will block migration anyway.
1277 */
1278 .features[FEAT_XSAVE] =
1279 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
1280 CPUID_XSAVE_XGETBV1,
1281 .features[FEAT_6_EAX] =
1282 CPUID_6_EAX_ARAT,
1283 .xlevel = 0x80000008,
1284 .model_id = "Intel Core Processor (Skylake)",
1285 },
3eca4642
EH		 1286 {
1287 .name = "Opteron_G1",
1288 .level = 5,
99b88a17 1289 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1290 .family = 15,
1291 .model = 6,
1292 .stepping = 1,
0514ef2f 1293 .features[FEAT_1_EDX] =
b3a4f0b1 1294 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1295 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1296 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1297 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1298 CPUID_DE | CPUID_FP87,
0514ef2f 1299 .features[FEAT_1_ECX] =
27861ecc 1300 CPUID_EXT_SSE3,
0514ef2f 1301 .features[FEAT_8000_0001_EDX] =
27861ecc 1302 CPUID_EXT2_LM | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
b3fb3a20
EH		 1303 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1304 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1305 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1306 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1307 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
3eca4642
EH		 1308 .xlevel = 0x80000008,
1309 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
1310 },
1311 {
1312 .name = "Opteron_G2",
1313 .level = 5,
99b88a17 1314 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1315 .family = 15,
1316 .model = 6,
1317 .stepping = 1,
0514ef2f 1318 .features[FEAT_1_EDX] =
b3a4f0b1 1319 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1320 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1321 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1322 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1323 CPUID_DE | CPUID_FP87,
0514ef2f 1324 .features[FEAT_1_ECX] =
27861ecc 1325 CPUID_EXT_CX16 | CPUID_EXT_SSE3,
33b5e8c0 1326 /* Missing: CPUID_EXT2_RDTSCP */
0514ef2f 1327 .features[FEAT_8000_0001_EDX] =
33b5e8c0 1328 CPUID_EXT2_LM | CPUID_EXT2_FXSR |
b3fb3a20
EH		 1329 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
1330 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
1331 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
1332 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
1333 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
1334 CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1335 .features[FEAT_8000_0001_ECX] =
27861ecc 1336 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH		 1337 .xlevel = 0x80000008,
1338 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
1339 },
1340 {
1341 .name = "Opteron_G3",
1342 .level = 5,
99b88a17 1343 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1344 .family = 15,
1345 .model = 6,
1346 .stepping = 1,
0514ef2f 1347 .features[FEAT_1_EDX] =
b3a4f0b1 1348 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1349 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1350 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1351 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1352 CPUID_DE | CPUID_FP87,
0514ef2f 1353 .features[FEAT_1_ECX] =
27861ecc 1354 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
b3fb3a20 1355 CPUID_EXT_SSE3,
33b5e8c0 1356 /* Missing: CPUID_EXT2_RDTSCP */
0514ef2f 1357 .features[FEAT_8000_0001_EDX] =
33b5e8c0 1358 CPUID_EXT2_LM | CPUID_EXT2_FXSR |
b3fb3a20
EH		 1359 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
1360 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
1361 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
1362 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
1363 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
1364 CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1365 .features[FEAT_8000_0001_ECX] =
27861ecc 1366 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
b3fb3a20 1367 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH		 1368 .xlevel = 0x80000008,
1369 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
1370 },
1371 {
1372 .name = "Opteron_G4",
1373 .level = 0xd,
99b88a17 1374 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1375 .family = 21,
1376 .model = 1,
1377 .stepping = 2,
0514ef2f 1378 .features[FEAT_1_EDX] =
b3a4f0b1 1379 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1380 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1381 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1382 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1383 CPUID_DE | CPUID_FP87,
0514ef2f 1384 .features[FEAT_1_ECX] =
27861ecc 1385 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 1386 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1387 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1388 CPUID_EXT_SSE3,
33b5e8c0 1389 /* Missing: CPUID_EXT2_RDTSCP */
0514ef2f 1390 .features[FEAT_8000_0001_EDX] =
33b5e8c0 1391 CPUID_EXT2_LM |
b3fb3a20
EH		 1392 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1393 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1394 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1395 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1396 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1397 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1398 .features[FEAT_8000_0001_ECX] =
27861ecc 1399 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
b3fb3a20
EH		 1400 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1401 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1402 CPUID_EXT3_LAHF_LM,
0bb0b2d2 1403 /* no xsaveopt! */
3eca4642
EH		 1404 .xlevel = 0x8000001A,
1405 .model_id = "AMD Opteron 62xx class CPU",
1406 },
021941b9
AP		 1407 {
1408 .name = "Opteron_G5",
1409 .level = 0xd,
99b88a17 1410 .vendor = CPUID_VENDOR_AMD,
021941b9
AP		 1411 .family = 21,
1412 .model = 2,
1413 .stepping = 0,
0514ef2f 1414 .features[FEAT_1_EDX] =
b3a4f0b1 1415 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1416 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1417 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1418 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1419 CPUID_DE | CPUID_FP87,
0514ef2f 1420 .features[FEAT_1_ECX] =
27861ecc 1421 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
b3fb3a20
EH		 1422 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
1423 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
1424 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
33b5e8c0 1425 /* Missing: CPUID_EXT2_RDTSCP */
0514ef2f 1426 .features[FEAT_8000_0001_EDX] =
33b5e8c0 1427 CPUID_EXT2_LM |
b3fb3a20
EH		 1428 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1429 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1430 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1431 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1432 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1433 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1434 .features[FEAT_8000_0001_ECX] =
27861ecc 1435 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
b3fb3a20
EH		 1436 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1437 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1438 CPUID_EXT3_LAHF_LM,
0bb0b2d2 1439 /* no xsaveopt! */
021941b9
AP		 1440 .xlevel = 0x8000001A,
1441 .model_id = "AMD Opteron 63xx class CPU",
1442 },
c6dc6f63
AP		 1443};
1444
5114e842
EH		 1445typedef struct PropValue {
1446 const char *prop, *value;
1447} PropValue;
1448
1449/* KVM-specific features that are automatically added/removed
1450 * from all CPU models when KVM is enabled.
1451 */
1452static PropValue kvm_default_props[] = {
1453 { "kvmclock", "on" },
1454 { "kvm-nopiodelay", "on" },
1455 { "kvm-asyncpf", "on" },
1456 { "kvm-steal-time", "on" },
1457 { "kvm-pv-eoi", "on" },
1458 { "kvmclock-stable-bit", "on" },
1459 { "x2apic", "on" },
1460 { "acpi", "off" },
1461 { "monitor", "off" },
1462 { "svm", "off" },
1463 { NULL, NULL },
1464};
1465
1466void x86_cpu_change_kvm_default(const char *prop, const char *value)
1467{
1468 PropValue *pv;
1469 for (pv = kvm_default_props; pv->prop; pv++) {
1470 if (!strcmp(pv->prop, prop)) {
1471 pv->value = value;
1472 break;
1473 }
1474 }
1475
1476 /* It is valid to call this function only for properties that
1477 * are already present in the kvm_default_props table.
1478 */
1479 assert(pv->prop);
1480}
1481
4d1b279b
EH		 1482static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
1483 bool migratable_only);
1484
d940ee9b
EH		 1485#ifdef CONFIG_KVM
1486
c6dc6f63
AP		 1487static int cpu_x86_fill_model_id(char *str)
1488{
1489 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1490 int i;
1491
1492 for (i = 0; i < 3; i++) {
1493 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
1494 memcpy(str + i * 16 + 0, &eax, 4);
1495 memcpy(str + i * 16 + 4, &ebx, 4);
1496 memcpy(str + i * 16 + 8, &ecx, 4);
1497 memcpy(str + i * 16 + 12, &edx, 4);
1498 }
1499 return 0;
1500}
1501
d940ee9b
EH		 1502static X86CPUDefinition host_cpudef;
1503
84f1b92f 1504static Property host_x86_cpu_properties[] = {
120eee7d 1505 DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true),
e265e3e4 1506 DEFINE_PROP_BOOL("host-cache-info", X86CPU, cache_info_passthrough, false),
84f1b92f
EH		 1507 DEFINE_PROP_END_OF_LIST()
1508};
1509
d940ee9b 1510/* class_init for the "host" CPU model
6e746f30 1511 *
d940ee9b 1512 * This function may be called before KVM is initialized.
6e746f30 1513 */
d940ee9b 1514static void host_x86_cpu_class_init(ObjectClass *oc, void *data)
c6dc6f63 1515{
84f1b92f 1516 DeviceClass *dc = DEVICE_CLASS(oc);
d940ee9b 1517 X86CPUClass *xcc = X86_CPU_CLASS(oc);
c6dc6f63
AP		 1518 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1519
d940ee9b 1520 xcc->kvm_required = true;
6e746f30 1521
c6dc6f63 1522 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
d940ee9b 1523 x86_cpu_vendor_words2str(host_cpudef.vendor, ebx, edx, ecx);
c6dc6f63
AP		 1524
1525 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
d940ee9b
EH		 1526 host_cpudef.family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
1527 host_cpudef.model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
1528 host_cpudef.stepping = eax & 0x0F;
c6dc6f63 1529
d940ee9b 1530 cpu_x86_fill_model_id(host_cpudef.model_id);
2a573259 1531
d940ee9b 1532 xcc->cpu_def = &host_cpudef;
d940ee9b
EH		 1533
1534 /* level, xlevel, xlevel2, and the feature words are initialized on
1535 * instance_init, because they require KVM to be initialized.
1536 */
84f1b92f
EH		 1537
1538 dc->props = host_x86_cpu_properties;
4c315c27
MA		 1539 /* Reason: host_x86_cpu_initfn() dies when !kvm_enabled() */
1540 dc->cannot_destroy_with_object_finalize_yet = true;
d940ee9b
EH		 1541}
1542
1543static void host_x86_cpu_initfn(Object *obj)
1544{
1545 X86CPU *cpu = X86_CPU(obj);
1546 CPUX86State *env = &cpu->env;
1547 KVMState *s = kvm_state;
d940ee9b
EH		 1548
1549 assert(kvm_enabled());
1550
4d1b279b
EH		 1551 /* We can't fill the features array here because we don't know yet if
1552 * "migratable" is true or false.
1553 */
1554 cpu->host_features = true;
1555
d940ee9b
EH		 1556 env->cpuid_level = kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
1557 env->cpuid_xlevel = kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
1558 env->cpuid_xlevel2 = kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
2a573259 1559
d940ee9b 1560 object_property_set_bool(OBJECT(cpu), true, "pmu", &error_abort);
c6dc6f63
AP		 1561}
1562
d940ee9b
EH		 1563static const TypeInfo host_x86_cpu_type_info = {
1564 .name = X86_CPU_TYPE_NAME("host"),
1565 .parent = TYPE_X86_CPU,
1566 .instance_init = host_x86_cpu_initfn,
1567 .class_init = host_x86_cpu_class_init,
1568};
1569
1570#endif
1571
8459e396 1572static void report_unavailable_features(FeatureWord w, uint32_t mask)
c6dc6f63 1573{
8459e396 1574 FeatureWordInfo *f = &feature_word_info[w];
c6dc6f63
AP		 1575 int i;
1576
857aee33 1577 for (i = 0; i < 32; ++i) {
72370dc1 1578 if ((1UL << i) & mask) {
bffd67b0 1579 const char *reg = get_register_name_32(f->cpuid_reg);
8b4beddc 1580 assert(reg);
fefb41bf 1581 fprintf(stderr, "warning: %s doesn't support requested feature: "
8b4beddc 1582 "CPUID.%02XH:%s%s%s [bit %d]\n",
fefb41bf 1583 kvm_enabled() ? "host" : "TCG",
bffd67b0
EH		 1584 f->cpuid_eax, reg,
1585 f->feat_names[i] ? "." : "",
1586 f->feat_names[i] ? f->feat_names[i] : "", i);
c6dc6f63 1587 }
857aee33 1588 }
c6dc6f63
AP		 1589}
1590
d7bce999
EB		 1591static void x86_cpuid_version_get_family(Object *obj, Visitor *v,
1592 const char *name, void *opaque,
1593 Error **errp)
95b8519d
AF		 1594{
1595 X86CPU *cpu = X86_CPU(obj);
1596 CPUX86State *env = &cpu->env;
1597 int64_t value;
1598
1599 value = (env->cpuid_version >> 8) & 0xf;
1600 if (value == 0xf) {
1601 value += (env->cpuid_version >> 20) & 0xff;
1602 }
51e72bc1 1603 visit_type_int(v, name, &value, errp);
95b8519d
AF		 1604}
1605
d7bce999
EB		 1606static void x86_cpuid_version_set_family(Object *obj, Visitor *v,
1607 const char *name, void *opaque,
1608 Error **errp)
ed5e1ec3 1609{
71ad61d3
AF		 1610 X86CPU *cpu = X86_CPU(obj);
1611 CPUX86State *env = &cpu->env;
1612 const int64_t min = 0;
1613 const int64_t max = 0xff + 0xf;
65cd9064 1614 Error *local_err = NULL;
71ad61d3
AF		 1615 int64_t value;
1616
51e72bc1 1617 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 1618 if (local_err) {
1619 error_propagate(errp, local_err);
71ad61d3
AF		 1620 return;
1621 }
1622 if (value < min || value > max) {
c6bd8c70
MA		 1623 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1624 name ? name : "null", value, min, max);
71ad61d3
AF		 1625 return;
1626 }
1627
ed5e1ec3 1628 env->cpuid_version &= ~0xff00f00;
71ad61d3
AF		 1629 if (value > 0x0f) {
1630 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
ed5e1ec3 1631 } else {
71ad61d3 1632 env->cpuid_version |= value << 8;
ed5e1ec3
AF		 1633 }
1634}
1635
d7bce999
EB		 1636static void x86_cpuid_version_get_model(Object *obj, Visitor *v,
1637 const char *name, void *opaque,
1638 Error **errp)
67e30c83
AF		 1639{
1640 X86CPU *cpu = X86_CPU(obj);
1641 CPUX86State *env = &cpu->env;
1642 int64_t value;
1643
1644 value = (env->cpuid_version >> 4) & 0xf;
1645 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
51e72bc1 1646 visit_type_int(v, name, &value, errp);
67e30c83
AF		 1647}
1648
d7bce999
EB		 1649static void x86_cpuid_version_set_model(Object *obj, Visitor *v,
1650 const char *name, void *opaque,
1651 Error **errp)
b0704cbd 1652{
c5291a4f
AF		 1653 X86CPU *cpu = X86_CPU(obj);
1654 CPUX86State *env = &cpu->env;
1655 const int64_t min = 0;
1656 const int64_t max = 0xff;
65cd9064 1657 Error *local_err = NULL;
c5291a4f
AF		 1658 int64_t value;
1659
51e72bc1 1660 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 1661 if (local_err) {
1662 error_propagate(errp, local_err);
c5291a4f
AF		 1663 return;
1664 }
1665 if (value < min || value > max) {
c6bd8c70
MA		 1666 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1667 name ? name : "null", value, min, max);
c5291a4f
AF		 1668 return;
1669 }
1670
b0704cbd 1671 env->cpuid_version &= ~0xf00f0;
c5291a4f 1672 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
b0704cbd
AF		 1673}
1674
35112e41 1675static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
d7bce999 1676 const char *name, void *opaque,
35112e41
AF		 1677 Error **errp)
1678{
1679 X86CPU *cpu = X86_CPU(obj);
1680 CPUX86State *env = &cpu->env;
1681 int64_t value;
1682
1683 value = env->cpuid_version & 0xf;
51e72bc1 1684 visit_type_int(v, name, &value, errp);
35112e41
AF		 1685}
1686
036e2222 1687static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
d7bce999 1688 const char *name, void *opaque,
036e2222 1689 Error **errp)
38c3dc46 1690{
036e2222
AF		 1691 X86CPU *cpu = X86_CPU(obj);
1692 CPUX86State *env = &cpu->env;
1693 const int64_t min = 0;
1694 const int64_t max = 0xf;
65cd9064 1695 Error *local_err = NULL;
036e2222
AF		 1696 int64_t value;
1697
51e72bc1 1698 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 1699 if (local_err) {
1700 error_propagate(errp, local_err);
036e2222
AF		 1701 return;
1702 }
1703 if (value < min || value > max) {
c6bd8c70
MA		 1704 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1705 name ? name : "null", value, min, max);
036e2222
AF		 1706 return;
1707 }
1708
38c3dc46 1709 env->cpuid_version &= ~0xf;
036e2222 1710 env->cpuid_version |= value & 0xf;
38c3dc46
AF		 1711}
1712
d480e1af
AF		 1713static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
1714{
1715 X86CPU *cpu = X86_CPU(obj);
1716 CPUX86State *env = &cpu->env;
1717 char *value;
d480e1af 1718
e42a92ae 1719 value = g_malloc(CPUID_VENDOR_SZ + 1);
99b88a17
IM		 1720 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2,
1721 env->cpuid_vendor3);
d480e1af
AF		 1722 return value;
1723}
1724
1725static void x86_cpuid_set_vendor(Object *obj, const char *value,
1726 Error **errp)
1727{
1728 X86CPU *cpu = X86_CPU(obj);
1729 CPUX86State *env = &cpu->env;
1730 int i;
1731
9df694ee 1732 if (strlen(value) != CPUID_VENDOR_SZ) {
c6bd8c70 1733 error_setg(errp, QERR_PROPERTY_VALUE_BAD, "", "vendor", value);
d480e1af
AF		 1734 return;
1735 }
1736
1737 env->cpuid_vendor1 = 0;
1738 env->cpuid_vendor2 = 0;
1739 env->cpuid_vendor3 = 0;
1740 for (i = 0; i < 4; i++) {
1741 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
1742 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
1743 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
1744 }
d480e1af
AF		 1745}
1746
63e886eb
AF		 1747static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
1748{
1749 X86CPU *cpu = X86_CPU(obj);
1750 CPUX86State *env = &cpu->env;
1751 char *value;
1752 int i;
1753
1754 value = g_malloc(48 + 1);
1755 for (i = 0; i < 48; i++) {
1756 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
1757 }
1758 value[48] = '\0';
1759 return value;
1760}
1761
938d4c25
AF		 1762static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
1763 Error **errp)
dcce6675 1764{
938d4c25
AF		 1765 X86CPU *cpu = X86_CPU(obj);
1766 CPUX86State *env = &cpu->env;
dcce6675
AF		 1767 int c, len, i;
1768
1769 if (model_id == NULL) {
1770 model_id = "";
1771 }
1772 len = strlen(model_id);
d0a6acf4 1773 memset(env->cpuid_model, 0, 48);
dcce6675
AF		 1774 for (i = 0; i < 48; i++) {
1775 if (i >= len) {
1776 c = '\0';
1777 } else {
1778 c = (uint8_t)model_id[i];
1779 }
1780 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
1781 }
1782}
1783
d7bce999
EB		 1784static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, const char *name,
1785 void *opaque, Error **errp)
89e48965
AF		 1786{
1787 X86CPU *cpu = X86_CPU(obj);
1788 int64_t value;
1789
1790 value = cpu->env.tsc_khz * 1000;
51e72bc1 1791 visit_type_int(v, name, &value, errp);
89e48965
AF		 1792}
1793
d7bce999
EB		 1794static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, const char *name,
1795 void *opaque, Error **errp)
89e48965
AF		 1796{
1797 X86CPU *cpu = X86_CPU(obj);
1798 const int64_t min = 0;
2e84849a 1799 const int64_t max = INT64_MAX;
65cd9064 1800 Error *local_err = NULL;
89e48965
AF		 1801 int64_t value;
1802
51e72bc1 1803 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 1804 if (local_err) {
1805 error_propagate(errp, local_err);
89e48965
AF		 1806 return;
1807 }
1808 if (value < min || value > max) {
c6bd8c70
MA		 1809 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1810 name ? name : "null", value, min, max);
89e48965
AF		 1811 return;
1812 }
1813
36f96c4b 1814 cpu->env.tsc_khz = cpu->env.user_tsc_khz = value / 1000;
89e48965
AF		 1815}
1816
d7bce999
EB		 1817static void x86_cpuid_get_apic_id(Object *obj, Visitor *v, const char *name,
1818 void *opaque, Error **errp)
31050930
IM		 1819{
1820 X86CPU *cpu = X86_CPU(obj);
7e72a45c 1821 int64_t value = cpu->apic_id;
31050930 1822
51e72bc1 1823 visit_type_int(v, name, &value, errp);
31050930
IM		 1824}
1825
d7bce999
EB		 1826static void x86_cpuid_set_apic_id(Object *obj, Visitor *v, const char *name,
1827 void *opaque, Error **errp)
31050930
IM		 1828{
1829 X86CPU *cpu = X86_CPU(obj);
8d6d4980 1830 DeviceState *dev = DEVICE(obj);
31050930
IM		 1831 const int64_t min = 0;
1832 const int64_t max = UINT32_MAX;
1833 Error *error = NULL;
1834 int64_t value;
1835
8d6d4980
IM		 1836 if (dev->realized) {
1837 error_setg(errp, "Attempt to set property '%s' on '%s' after "
1838 "it was realized", name, object_get_typename(obj));
1839 return;
1840 }
1841
51e72bc1 1842 visit_type_int(v, name, &value, &error);
31050930
IM		 1843 if (error) {
1844 error_propagate(errp, error);
1845 return;
1846 }
1847 if (value < min || value > max) {
1848 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
1849 " (minimum: %" PRId64 ", maximum: %" PRId64 ")" ,
1850 object_get_typename(obj), name, value, min, max);
1851 return;
1852 }
1853
7e72a45c 1854 if ((value != cpu->apic_id) && cpu_exists(value)) {
31050930
IM		 1855 error_setg(errp, "CPU with APIC ID %" PRIi64 " exists", value);
1856 return;
1857 }
7e72a45c 1858 cpu->apic_id = value;
31050930
IM		 1859}
1860
7e5292b5 1861/* Generic getter for "feature-words" and "filtered-features" properties */
d7bce999
EB		 1862static void x86_cpu_get_feature_words(Object *obj, Visitor *v,
1863 const char *name, void *opaque,
1864 Error **errp)
8e8aba50 1865{
7e5292b5 1866 uint32_t *array = (uint32_t *)opaque;
8e8aba50
EH		 1867 FeatureWord w;
1868 Error *err = NULL;
1869 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { };
1870 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { };
1871 X86CPUFeatureWordInfoList *list = NULL;
1872
1873 for (w = 0; w < FEATURE_WORDS; w++) {
1874 FeatureWordInfo *wi = &feature_word_info[w];
1875 X86CPUFeatureWordInfo *qwi = &word_infos[w];
1876 qwi->cpuid_input_eax = wi->cpuid_eax;
1877 qwi->has_cpuid_input_ecx = wi->cpuid_needs_ecx;
1878 qwi->cpuid_input_ecx = wi->cpuid_ecx;
1879 qwi->cpuid_register = x86_reg_info_32[wi->cpuid_reg].qapi_enum;
7e5292b5 1880 qwi->features = array[w];
8e8aba50
EH		 1881
1882 /* List will be in reverse order, but order shouldn't matter */
1883 list_entries[w].next = list;
1884 list_entries[w].value = &word_infos[w];
1885 list = &list_entries[w];
1886 }
1887
51e72bc1 1888 visit_type_X86CPUFeatureWordInfoList(v, "feature-words", &list, &err);
8e8aba50
EH		 1889 error_propagate(errp, err);
1890}
1891
d7bce999
EB		 1892static void x86_get_hv_spinlocks(Object *obj, Visitor *v, const char *name,
1893 void *opaque, Error **errp)
c8f0f88e
IM		 1894{
1895 X86CPU *cpu = X86_CPU(obj);
1896 int64_t value = cpu->hyperv_spinlock_attempts;
1897
51e72bc1 1898 visit_type_int(v, name, &value, errp);
c8f0f88e
IM		 1899}
1900
d7bce999
EB		 1901static void x86_set_hv_spinlocks(Object *obj, Visitor *v, const char *name,
1902 void *opaque, Error **errp)
c8f0f88e
IM		 1903{
1904 const int64_t min = 0xFFF;
1905 const int64_t max = UINT_MAX;
1906 X86CPU *cpu = X86_CPU(obj);
1907 Error *err = NULL;
1908 int64_t value;
1909
51e72bc1 1910 visit_type_int(v, name, &value, &err);
c8f0f88e
IM		 1911 if (err) {
1912 error_propagate(errp, err);
1913 return;
1914 }
1915
1916 if (value < min || value > max) {
1917 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
5bb4c35d 1918 " (minimum: %" PRId64 ", maximum: %" PRId64 ")",
1919 object_get_typename(obj), name ? name : "null",
1920 value, min, max);
c8f0f88e
IM		 1921 return;
1922 }
1923 cpu->hyperv_spinlock_attempts = value;
1924}
1925
1926static PropertyInfo qdev_prop_spinlocks = {
1927 .name = "int",
1928 .get = x86_get_hv_spinlocks,
1929 .set = x86_set_hv_spinlocks,
1930};
1931
72ac2e87
IM		 1932/* Convert all '_' in a feature string option name to '-', to make feature
1933 * name conform to QOM property naming rule, which uses '-' instead of '_'.
1934 */
1935static inline void feat2prop(char *s)
1936{
1937 while ((s = strchr(s, '_'))) {
1938 *s = '-';
1939 }
1940}
1941
8f961357
EH		 1942/* Parse "+feature,-feature,feature=foo" CPU feature string
1943 */
94a444b2
AF		 1944static void x86_cpu_parse_featurestr(CPUState *cs, char *features,
1945 Error **errp)
8f961357 1946{
94a444b2 1947 X86CPU *cpu = X86_CPU(cs);
8f961357 1948 char *featurestr; /* Single 'key=value" string being parsed */
e1c224b4 1949 FeatureWord w;
8f961357 1950 /* Features to be added */
077c68c3 1951 FeatureWordArray plus_features = { 0 };
8f961357 1952 /* Features to be removed */
5ef57876 1953 FeatureWordArray minus_features = { 0 };
8f961357 1954 uint32_t numvalue;
a91987c2 1955 CPUX86State *env = &cpu->env;
94a444b2 1956 Error *local_err = NULL;
8f961357 1957
8f961357 1958 featurestr = features ? strtok(features, ",") : NULL;
c6dc6f63
AP		 1959
1960 while (featurestr) {
1961 char *val;
1962 if (featurestr[0] == '+') {
c00c94ab 1963 add_flagname_to_bitmaps(featurestr + 1, plus_features, &local_err);
c6dc6f63 1964 } else if (featurestr[0] == '-') {
c00c94ab 1965 add_flagname_to_bitmaps(featurestr + 1, minus_features, &local_err);
c6dc6f63
AP		 1966 } else if ((val = strchr(featurestr, '='))) {
1967 *val = 0; val++;
72ac2e87 1968 feat2prop(featurestr);
d024d209 1969 if (!strcmp(featurestr, "xlevel")) {
c6dc6f63 1970 char *err;
a91987c2
IM		 1971 char num[32];
1972
c6dc6f63
AP		 1973 numvalue = strtoul(val, &err, 0);
1974 if (!*val || *err) {
6b1dd54b
PB		 1975 error_setg(errp, "bad numerical value %s", val);
1976 return;
c6dc6f63
AP		 1977 }
1978 if (numvalue < 0x80000000) {
94a444b2
AF		 1979 error_report("xlevel value shall always be >= 0x80000000"
1980 ", fixup will be removed in future versions");
2f7a21c4 1981 numvalue += 0x80000000;
c6dc6f63 1982 }
a91987c2 1983 snprintf(num, sizeof(num), "%" PRIu32, numvalue);
94a444b2 1984 object_property_parse(OBJECT(cpu), num, featurestr, &local_err);
72ac2e87 1985 } else if (!strcmp(featurestr, "tsc-freq")) {
b862d1fe
JR		 1986 int64_t tsc_freq;
1987 char *err;
a91987c2 1988 char num[32];
b862d1fe 1989
4677bb40
MAL		 1990 tsc_freq = qemu_strtosz_suffix_unit(val, &err,
1991 QEMU_STRTOSZ_DEFSUFFIX_B, 1000);
45009a30 1992 if (tsc_freq < 0 || *err) {
6b1dd54b
PB		 1993 error_setg(errp, "bad numerical value %s", val);
1994 return;
b862d1fe 1995 }
a91987c2 1996 snprintf(num, sizeof(num), "%" PRId64, tsc_freq);
94a444b2
AF		 1997 object_property_parse(OBJECT(cpu), num, "tsc-frequency",
1998 &local_err);
72ac2e87 1999 } else if (!strcmp(featurestr, "hv-spinlocks")) {
28f52cc0 2000 char *err;
92067bf4 2001 const int min = 0xFFF;
c8f0f88e 2002 char num[32];
28f52cc0
VR		 2003 numvalue = strtoul(val, &err, 0);
2004 if (!*val || *err) {
6b1dd54b
PB		 2005 error_setg(errp, "bad numerical value %s", val);
2006 return;
28f52cc0 2007 }
92067bf4 2008 if (numvalue < min) {
94a444b2 2009 error_report("hv-spinlocks value shall always be >= 0x%x"
5bb4c35d 2010 ", fixup will be removed in future versions",
2011 min);
92067bf4
IM		 2012 numvalue = min;
2013 }
c8f0f88e 2014 snprintf(num, sizeof(num), "%" PRId32, numvalue);
94a444b2 2015 object_property_parse(OBJECT(cpu), num, featurestr, &local_err);
c6dc6f63 2016 } else {
94a444b2 2017 object_property_parse(OBJECT(cpu), val, featurestr, &local_err);
c6dc6f63 2018 }
c6dc6f63 2019 } else {
258f5abe 2020 feat2prop(featurestr);
94a444b2 2021 object_property_parse(OBJECT(cpu), "on", featurestr, &local_err);
a91987c2 2022 }
94a444b2
AF		 2023 if (local_err) {
2024 error_propagate(errp, local_err);
6b1dd54b 2025 return;
c6dc6f63
AP		 2026 }
2027 featurestr = strtok(NULL, ",");
2028 }
e1c224b4 2029
4d1b279b
EH		 2030 if (cpu->host_features) {
2031 for (w = 0; w < FEATURE_WORDS; w++) {
2032 env->features[w] =
2033 x86_cpu_get_supported_feature_word(w, cpu->migratable);
2034 }
2035 }
2036
e1c224b4
EH		 2037 for (w = 0; w < FEATURE_WORDS; w++) {
2038 env->features[w] |= plus_features[w];
2039 env->features[w] &= ~minus_features[w];
2040 }
c6dc6f63
AP		 2041}
2042
8c3329e5 2043/* Print all cpuid feature names in featureset
c6dc6f63 2044 */
8c3329e5 2045static void listflags(FILE *f, fprintf_function print, const char **featureset)
0856579c 2046{
8c3329e5
EH		 2047 int bit;
2048 bool first = true;
2049
2050 for (bit = 0; bit < 32; bit++) {
2051 if (featureset[bit]) {
2052 print(f, "%s%s", first ? "" : " ", featureset[bit]);
2053 first = false;
c6dc6f63 2054 }
8c3329e5 2055 }
c6dc6f63
AP		 2056}
2057
e916cbf8
PM		 2058/* generate CPU information. */
2059void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
c6dc6f63 2060{
9576de75 2061 X86CPUDefinition *def;
c6dc6f63 2062 char buf[256];
7fc9b714 2063 int i;
c6dc6f63 2064
7fc9b714
AF		 2065 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
2066 def = &builtin_x86_defs[i];
c04321b3 2067 snprintf(buf, sizeof(buf), "%s", def->name);
6cdf8854 2068 (*cpu_fprintf)(f, "x86 %16s %-48s\n", buf, def->model_id);
c6dc6f63 2069 }
21ad7789
JK		 2070#ifdef CONFIG_KVM
2071 (*cpu_fprintf)(f, "x86 %16s %-48s\n", "host",
2072 "KVM processor with all supported host features "
2073 "(only available in KVM mode)");
2074#endif
2075
6cdf8854 2076 (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
3af60be2
JK		 2077 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) {
2078 FeatureWordInfo *fw = &feature_word_info[i];
2079
8c3329e5
EH		 2080 (*cpu_fprintf)(f, " ");
2081 listflags(f, cpu_fprintf, fw->feat_names);
2082 (*cpu_fprintf)(f, "\n");
3af60be2 2083 }
c6dc6f63
AP		 2084}
2085
76b64a7a 2086CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
e3966126
AL		 2087{
2088 CpuDefinitionInfoList *cpu_list = NULL;
9576de75 2089 X86CPUDefinition *def;
7fc9b714 2090 int i;
e3966126 2091
7fc9b714 2092 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
e3966126
AL		 2093 CpuDefinitionInfoList *entry;
2094 CpuDefinitionInfo *info;
2095
7fc9b714 2096 def = &builtin_x86_defs[i];
e3966126
AL		 2097 info = g_malloc0(sizeof(*info));
2098 info->name = g_strdup(def->name);
2099
2100 entry = g_malloc0(sizeof(*entry));
2101 entry->value = info;
2102 entry->next = cpu_list;
2103 cpu_list = entry;
2104 }
2105
2106 return cpu_list;
2107}
2108
84f1b92f
EH		 2109static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
2110 bool migratable_only)
27418adf
EH		 2111{
2112 FeatureWordInfo *wi = &feature_word_info[w];
84f1b92f 2113 uint32_t r;
27418adf 2114
fefb41bf 2115 if (kvm_enabled()) {
84f1b92f
EH		 2116 r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid_eax,
2117 wi->cpuid_ecx,
2118 wi->cpuid_reg);
fefb41bf 2119 } else if (tcg_enabled()) {
84f1b92f 2120 r = wi->tcg_features;
fefb41bf
EH		 2121 } else {
2122 return ~0;
2123 }
84f1b92f
EH		 2124 if (migratable_only) {
2125 r &= x86_cpu_get_migratable_flags(w);
2126 }
2127 return r;
27418adf
EH		 2128}
2129
51f63aed
EH		 2130/*
2131 * Filters CPU feature words based on host availability of each feature.
2132 *
51f63aed
EH		 2133 * Returns: 0 if all flags are supported by the host, non-zero otherwise.
2134 */
27418adf 2135static int x86_cpu_filter_features(X86CPU *cpu)
bc74b7db
EH		 2136{
2137 CPUX86State *env = &cpu->env;
bd87d2a2 2138 FeatureWord w;
51f63aed
EH		 2139 int rv = 0;
2140
bd87d2a2 2141 for (w = 0; w < FEATURE_WORDS; w++) {
84f1b92f
EH		 2142 uint32_t host_feat =
2143 x86_cpu_get_supported_feature_word(w, cpu->migratable);
034acf4a
EH		 2144 uint32_t requested_features = env->features[w];
2145 env->features[w] &= host_feat;
2146 cpu->filtered_features[w] = requested_features & ~env->features[w];
51f63aed
EH		 2147 if (cpu->filtered_features[w]) {
2148 if (cpu->check_cpuid || cpu->enforce_cpuid) {
8459e396 2149 report_unavailable_features(w, cpu->filtered_features[w]);
51f63aed
EH		 2150 }
2151 rv = 1;
2152 }
bd87d2a2 2153 }
51f63aed
EH		 2154
2155 return rv;
bc74b7db 2156}
bc74b7db 2157
5114e842
EH		 2158static void x86_cpu_apply_props(X86CPU *cpu, PropValue *props)
2159{
2160 PropValue *pv;
2161 for (pv = props; pv->prop; pv++) {
2162 if (!pv->value) {
2163 continue;
2164 }
2165 object_property_parse(OBJECT(cpu), pv->value, pv->prop,
2166 &error_abort);
2167 }
2168}
2169
d940ee9b 2170/* Load data from X86CPUDefinition
c080e30e 2171 */
d940ee9b 2172static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp)
c6dc6f63 2173{
61dcd775 2174 CPUX86State *env = &cpu->env;
74f54bc4
EH		 2175 const char *vendor;
2176 char host_vendor[CPUID_VENDOR_SZ + 1];
e1c224b4 2177 FeatureWord w;
c6dc6f63 2178
2d64255b
AF		 2179 object_property_set_int(OBJECT(cpu), def->level, "level", errp);
2180 object_property_set_int(OBJECT(cpu), def->family, "family", errp);
2181 object_property_set_int(OBJECT(cpu), def->model, "model", errp);
2182 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", errp);
2d64255b 2183 object_property_set_int(OBJECT(cpu), def->xlevel, "xlevel", errp);
01431f3c 2184 object_property_set_int(OBJECT(cpu), def->xlevel2, "xlevel2", errp);
2d64255b 2185 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", errp);
e1c224b4
EH		 2186 for (w = 0; w < FEATURE_WORDS; w++) {
2187 env->features[w] = def->features[w];
2188 }
82beb536 2189
9576de75 2190 /* Special cases not set in the X86CPUDefinition structs: */
82beb536 2191 if (kvm_enabled()) {
492a4c94
LT		 2192 if (!kvm_irqchip_in_kernel()) {
2193 x86_cpu_change_kvm_default("x2apic", "off");
2194 }
2195
5114e842 2196 x86_cpu_apply_props(cpu, kvm_default_props);
82beb536 2197 }
5fcca9ff 2198
82beb536 2199 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR;
7c08db30
EH		 2200
2201 /* sysenter isn't supported in compatibility mode on AMD,
2202 * syscall isn't supported in compatibility mode on Intel.
2203 * Normally we advertise the actual CPU vendor, but you can
2204 * override this using the 'vendor' property if you want to use
2205 * KVM's sysenter/syscall emulation in compatibility mode and
2206 * when doing cross vendor migration
2207 */
74f54bc4 2208 vendor = def->vendor;
7c08db30
EH		 2209 if (kvm_enabled()) {
2210 uint32_t ebx = 0, ecx = 0, edx = 0;
2211 host_cpuid(0, 0, NULL, &ebx, &ecx, &edx);
2212 x86_cpu_vendor_words2str(host_vendor, ebx, edx, ecx);
2213 vendor = host_vendor;
2214 }
2215
2216 object_property_set_str(OBJECT(cpu), vendor, "vendor", errp);
2217
c6dc6f63
AP		 2218}
2219
e1570d00 2220X86CPU *cpu_x86_create(const char *cpu_model, Error **errp)
5c3c6a68 2221{
2d64255b 2222 X86CPU *cpu = NULL;
d940ee9b 2223 X86CPUClass *xcc;
500050d1 2224 ObjectClass *oc;
2d64255b
AF		 2225 gchar **model_pieces;
2226 char *name, *features;
5c3c6a68
AF		 2227 Error *error = NULL;
2228
2d64255b
AF		 2229 model_pieces = g_strsplit(cpu_model, ",", 2);
2230 if (!model_pieces[0]) {
2231 error_setg(&error, "Invalid/empty CPU model name");
2232 goto out;
2233 }
2234 name = model_pieces[0];
2235 features = model_pieces[1];
2236
500050d1
AF		 2237 oc = x86_cpu_class_by_name(name);
2238 if (oc == NULL) {
2239 error_setg(&error, "Unable to find CPU definition: %s", name);
2240 goto out;
2241 }
d940ee9b
EH		 2242 xcc = X86_CPU_CLASS(oc);
2243
2244 if (xcc->kvm_required && !kvm_enabled()) {
2245 error_setg(&error, "CPU model '%s' requires KVM", name);
285f025d
EH		 2246 goto out;
2247 }
2248
d940ee9b
EH		 2249 cpu = X86_CPU(object_new(object_class_get_name(oc)));
2250
94a444b2 2251 x86_cpu_parse_featurestr(CPU(cpu), features, &error);
2d64255b
AF		 2252 if (error) {
2253 goto out;
5c3c6a68
AF		 2254 }
2255
7f833247 2256out:
cd7b87ff
AF		 2257 if (error != NULL) {
2258 error_propagate(errp, error);
500050d1
AF		 2259 if (cpu) {
2260 object_unref(OBJECT(cpu));
2261 cpu = NULL;
2262 }
cd7b87ff 2263 }
7f833247
IM		 2264 g_strfreev(model_pieces);
2265 return cpu;
2266}
2267
0856579c 2268X86CPU *cpu_x86_init(const char *cpu_model)
7f833247
IM		 2269{
2270 Error *error = NULL;
2271 X86CPU *cpu;
2272
e1570d00 2273 cpu = cpu_x86_create(cpu_model, &error);
5c3c6a68 2274 if (error) {
0856579c 2275 goto out;
9c235e83 2276 }
7f833247 2277
7f833247 2278 object_property_set_bool(OBJECT(cpu), true, "realized", &error);
18b0e4e7 2279
0856579c
PM		 2280out:
2281 if (error) {
2282 error_report_err(error);
2283 if (cpu != NULL) {
2284 object_unref(OBJECT(cpu));
2285 cpu = NULL;
2286 }
18b0e4e7 2287 }
0856579c 2288 return cpu;
5c3c6a68
AF		 2289}
2290
d940ee9b
EH		 2291static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data)
2292{
2293 X86CPUDefinition *cpudef = data;
2294 X86CPUClass *xcc = X86_CPU_CLASS(oc);
2295
2296 xcc->cpu_def = cpudef;
2297}
2298
2299static void x86_register_cpudef_type(X86CPUDefinition *def)
2300{
2301 char *typename = x86_cpu_type_name(def->name);
2302 TypeInfo ti = {
2303 .name = typename,
2304 .parent = TYPE_X86_CPU,
2305 .class_init = x86_cpu_cpudef_class_init,
2306 .class_data = def,
2307 };
2308
2309 type_register(&ti);
2310 g_free(typename);
2311}
2312
c6dc6f63 2313#if !defined(CONFIG_USER_ONLY)
c6dc6f63 2314
0e26b7b8
BS		 2315void cpu_clear_apic_feature(CPUX86State *env)
2316{
0514ef2f 2317 env->features[FEAT_1_EDX] &= ~CPUID_APIC;
0e26b7b8
BS		 2318}
2319
c6dc6f63
AP		 2320#endif /* !CONFIG_USER_ONLY */
2321
c6dc6f63
AP		 2322void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
2323 uint32_t *eax, uint32_t *ebx,
2324 uint32_t *ecx, uint32_t *edx)
2325{
a60f24b5
AF		 2326 X86CPU *cpu = x86_env_get_cpu(env);
2327 CPUState *cs = CPU(cpu);
2328
c6dc6f63
AP		 2329 /* test if maximum index reached */
2330 if (index & 0x80000000) {
b3baa152
BW		 2331 if (index > env->cpuid_xlevel) {
2332 if (env->cpuid_xlevel2 > 0) {
2333 /* Handle the Centaur's CPUID instruction. */
2334 if (index > env->cpuid_xlevel2) {
2335 index = env->cpuid_xlevel2;
2336 } else if (index < 0xC0000000) {
2337 index = env->cpuid_xlevel;
2338 }
2339 } else {
57f26ae7
EH		 2340 /* Intel documentation states that invalid EAX input will
2341 * return the same information as EAX=cpuid_level
2342 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
2343 */
2344 index = env->cpuid_level;
b3baa152
BW		 2345 }
2346 }
c6dc6f63
AP		 2347 } else {
2348 if (index > env->cpuid_level)
2349 index = env->cpuid_level;
2350 }
2351
2352 switch(index) {
2353 case 0:
2354 *eax = env->cpuid_level;
5eb2f7a4
EH		 2355 *ebx = env->cpuid_vendor1;
2356 *edx = env->cpuid_vendor2;
2357 *ecx = env->cpuid_vendor3;
c6dc6f63
AP		 2358 break;
2359 case 1:
2360 *eax = env->cpuid_version;
7e72a45c
EH		 2361 *ebx = (cpu->apic_id << 24) |
2362 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
0514ef2f 2363 *ecx = env->features[FEAT_1_ECX];
19dc85db
RH		 2364 if ((*ecx & CPUID_EXT_XSAVE) && (env->cr[4] & CR4_OSXSAVE_MASK)) {
2365 *ecx |= CPUID_EXT_OSXSAVE;
2366 }
0514ef2f 2367 *edx = env->features[FEAT_1_EDX];
ce3960eb
AF		 2368 if (cs->nr_cores * cs->nr_threads > 1) {
2369 *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
19dc85db 2370 *edx |= CPUID_HT;
c6dc6f63
AP		 2371 }
2372 break;
2373 case 2:
2374 /* cache info: needed for Pentium Pro compatibility */
787aaf57
BC		 2375 if (cpu->cache_info_passthrough) {
2376 host_cpuid(index, 0, eax, ebx, ecx, edx);
2377 break;
2378 }
5e891bf8 2379 *eax = 1; /* Number of CPUID[EAX=2] calls required */
c6dc6f63
AP		 2380 *ebx = 0;
2381 *ecx = 0;
5e891bf8
EH		 2382 *edx = (L1D_DESCRIPTOR << 16) | \
2383 (L1I_DESCRIPTOR << 8) | \
2384 (L2_DESCRIPTOR);
c6dc6f63
AP		 2385 break;
2386 case 4:
2387 /* cache info: needed for Core compatibility */
787aaf57
BC		 2388 if (cpu->cache_info_passthrough) {
2389 host_cpuid(index, count, eax, ebx, ecx, edx);
76c2975a 2390 *eax &= ~0xFC000000;
c6dc6f63 2391 } else {
2f7a21c4 2392 *eax = 0;
76c2975a 2393 switch (count) {
c6dc6f63 2394 case 0: /* L1 dcache info */
5e891bf8
EH		 2395 *eax |= CPUID_4_TYPE_DCACHE | \
2396 CPUID_4_LEVEL(1) | \
2397 CPUID_4_SELF_INIT_LEVEL;
2398 *ebx = (L1D_LINE_SIZE - 1) | \
2399 ((L1D_PARTITIONS - 1) << 12) | \
2400 ((L1D_ASSOCIATIVITY - 1) << 22);
2401 *ecx = L1D_SETS - 1;
2402 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP		 2403 break;
2404 case 1: /* L1 icache info */
5e891bf8
EH		 2405 *eax |= CPUID_4_TYPE_ICACHE | \
2406 CPUID_4_LEVEL(1) | \
2407 CPUID_4_SELF_INIT_LEVEL;
2408 *ebx = (L1I_LINE_SIZE - 1) | \
2409 ((L1I_PARTITIONS - 1) << 12) | \
2410 ((L1I_ASSOCIATIVITY - 1) << 22);
2411 *ecx = L1I_SETS - 1;
2412 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP		 2413 break;
2414 case 2: /* L2 cache info */
5e891bf8
EH		 2415 *eax |= CPUID_4_TYPE_UNIFIED | \
2416 CPUID_4_LEVEL(2) | \
2417 CPUID_4_SELF_INIT_LEVEL;
ce3960eb
AF		 2418 if (cs->nr_threads > 1) {
2419 *eax |= (cs->nr_threads - 1) << 14;
c6dc6f63 2420 }
5e891bf8
EH		 2421 *ebx = (L2_LINE_SIZE - 1) | \
2422 ((L2_PARTITIONS - 1) << 12) | \
2423 ((L2_ASSOCIATIVITY - 1) << 22);
2424 *ecx = L2_SETS - 1;
2425 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP		 2426 break;
2427 default: /* end of info */
2428 *eax = 0;
2429 *ebx = 0;
2430 *ecx = 0;
2431 *edx = 0;
2432 break;
76c2975a
PB		 2433 }
2434 }
2435
2436 /* QEMU gives out its own APIC IDs, never pass down bits 31..26. */
2437 if ((*eax & 31) && cs->nr_cores > 1) {
2438 *eax |= (cs->nr_cores - 1) << 26;
c6dc6f63
AP		 2439 }
2440 break;
2441 case 5:
2442 /* mwait info: needed for Core compatibility */
2443 *eax = 0; /* Smallest monitor-line size in bytes */
2444 *ebx = 0; /* Largest monitor-line size in bytes */
2445 *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
2446 *edx = 0;
2447 break;
2448 case 6:
2449 /* Thermal and Power Leaf */
28b8e4d0 2450 *eax = env->features[FEAT_6_EAX];
c6dc6f63
AP		 2451 *ebx = 0;
2452 *ecx = 0;
2453 *edx = 0;
2454 break;
f7911686 2455 case 7:
13526728
EH		 2456 /* Structured Extended Feature Flags Enumeration Leaf */
2457 if (count == 0) {
2458 *eax = 0; /* Maximum ECX value for sub-leaves */
0514ef2f 2459 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */
f74eefe0 2460 *ecx = env->features[FEAT_7_0_ECX]; /* Feature flags */
0f70ed47
PB		 2461 if ((*ecx & CPUID_7_0_ECX_PKU) && env->cr[4] & CR4_PKE_MASK) {
2462 *ecx |= CPUID_7_0_ECX_OSPKE;
2463 }
13526728 2464 *edx = 0; /* Reserved */
f7911686
YW		 2465 } else {
2466 *eax = 0;
2467 *ebx = 0;
2468 *ecx = 0;
2469 *edx = 0;
2470 }
2471 break;
c6dc6f63
AP		 2472 case 9:
2473 /* Direct Cache Access Information Leaf */
2474 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
2475 *ebx = 0;
2476 *ecx = 0;
2477 *edx = 0;
2478 break;
2479 case 0xA:
2480 /* Architectural Performance Monitoring Leaf */
9337e3b6 2481 if (kvm_enabled() && cpu->enable_pmu) {
a60f24b5 2482 KVMState *s = cs->kvm_state;
a0fa8208
GN		 2483
2484 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
2485 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
2486 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
2487 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
2488 } else {
2489 *eax = 0;
2490 *ebx = 0;
2491 *ecx = 0;
2492 *edx = 0;
2493 }
c6dc6f63 2494 break;
2560f19f
PB		 2495 case 0xD: {
2496 KVMState *s = cs->kvm_state;
19dc85db 2497 uint64_t ena_mask;
2560f19f
PB		 2498 int i;
2499
51e49430 2500 /* Processor Extended State */
2560f19f
PB		 2501 *eax = 0;
2502 *ebx = 0;
2503 *ecx = 0;
2504 *edx = 0;
19dc85db 2505 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
51e49430
SY		 2506 break;
2507 }
19dc85db
RH		 2508 if (kvm_enabled()) {
2509 ena_mask = kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EDX);
2510 ena_mask <<= 32;
2511 ena_mask |= kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EAX);
2512 } else {
2513 ena_mask = -1;
2514 }
ba9bc59e 2515
2560f19f
PB		 2516 if (count == 0) {
2517 *ecx = 0x240;
f4f1110e
RH		 2518 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
2519 const ExtSaveArea *esa = &x86_ext_save_areas[i];
19dc85db
RH		 2520 if ((env->features[esa->feature] & esa->bits) == esa->bits
2521 && ((ena_mask >> i) & 1) != 0) {
2560f19f 2522 if (i < 32) {
19dc85db 2523 *eax |= 1u << i;
2560f19f 2524 } else {
19dc85db 2525 *edx |= 1u << (i - 32);
2560f19f
PB		 2526 }
2527 *ecx = MAX(*ecx, esa->offset + esa->size);
2528 }
2529 }
cfc3b074 2530 *eax |= ena_mask & (XSTATE_FP_MASK | XSTATE_SSE_MASK);
2560f19f
PB		 2531 *ebx = *ecx;
2532 } else if (count == 1) {
0bb0b2d2 2533 *eax = env->features[FEAT_XSAVE];
f4f1110e
RH		 2534 } else if (count < ARRAY_SIZE(x86_ext_save_areas)) {
2535 const ExtSaveArea *esa = &x86_ext_save_areas[count];
19dc85db
RH		 2536 if ((env->features[esa->feature] & esa->bits) == esa->bits
2537 && ((ena_mask >> count) & 1) != 0) {
33f373d7
LJ		 2538 *eax = esa->size;
2539 *ebx = esa->offset;
2560f19f 2540 }
51e49430
SY		 2541 }
2542 break;
2560f19f 2543 }
c6dc6f63
AP		 2544 case 0x80000000:
2545 *eax = env->cpuid_xlevel;
2546 *ebx = env->cpuid_vendor1;
2547 *edx = env->cpuid_vendor2;
2548 *ecx = env->cpuid_vendor3;
2549 break;
2550 case 0x80000001:
2551 *eax = env->cpuid_version;
2552 *ebx = 0;
0514ef2f
EH		 2553 *ecx = env->features[FEAT_8000_0001_ECX];
2554 *edx = env->features[FEAT_8000_0001_EDX];
c6dc6f63
AP		 2555
2556 /* The Linux kernel checks for the CMPLegacy bit and
2557 * discards multiple thread information if it is set.
cb8d4c8f 2558 * So don't set it here for Intel to make Linux guests happy.
c6dc6f63 2559 */
ce3960eb 2560 if (cs->nr_cores * cs->nr_threads > 1) {
5eb2f7a4
EH		 2561 if (env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1 ||
2562 env->cpuid_vendor2 != CPUID_VENDOR_INTEL_2 ||
2563 env->cpuid_vendor3 != CPUID_VENDOR_INTEL_3) {
c6dc6f63
AP		 2564 *ecx |= 1 << 1; /* CmpLegacy bit */
2565 }
2566 }
c6dc6f63
AP		 2567 break;
2568 case 0x80000002:
2569 case 0x80000003:
2570 case 0x80000004:
2571 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
2572 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
2573 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
2574 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
2575 break;
2576 case 0x80000005:
2577 /* cache info (L1 cache) */
787aaf57
BC		 2578 if (cpu->cache_info_passthrough) {
2579 host_cpuid(index, 0, eax, ebx, ecx, edx);
2580 break;
2581 }
5e891bf8
EH		 2582 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | \
2583 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES);
2584 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | \
2585 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES);
2586 *ecx = (L1D_SIZE_KB_AMD << 24) | (L1D_ASSOCIATIVITY_AMD << 16) | \
2587 (L1D_LINES_PER_TAG << 8) | (L1D_LINE_SIZE);
2588 *edx = (L1I_SIZE_KB_AMD << 24) | (L1I_ASSOCIATIVITY_AMD << 16) | \
2589 (L1I_LINES_PER_TAG << 8) | (L1I_LINE_SIZE);
c6dc6f63
AP		 2590 break;
2591 case 0x80000006:
2592 /* cache info (L2 cache) */
787aaf57
BC		 2593 if (cpu->cache_info_passthrough) {
2594 host_cpuid(index, 0, eax, ebx, ecx, edx);
2595 break;
2596 }
5e891bf8
EH		 2597 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | \
2598 (L2_DTLB_2M_ENTRIES << 16) | \
2599 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | \
2600 (L2_ITLB_2M_ENTRIES);
2601 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | \
2602 (L2_DTLB_4K_ENTRIES << 16) | \
2603 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | \
2604 (L2_ITLB_4K_ENTRIES);
2605 *ecx = (L2_SIZE_KB_AMD << 16) | \
2606 (AMD_ENC_ASSOC(L2_ASSOCIATIVITY) << 12) | \
2607 (L2_LINES_PER_TAG << 8) | (L2_LINE_SIZE);
2608 *edx = ((L3_SIZE_KB/512) << 18) | \
2609 (AMD_ENC_ASSOC(L3_ASSOCIATIVITY) << 12) | \
2610 (L3_LINES_PER_TAG << 8) | (L3_LINE_SIZE);
c6dc6f63 2611 break;
303752a9
MT		 2612 case 0x80000007:
2613 *eax = 0;
2614 *ebx = 0;
2615 *ecx = 0;
2616 *edx = env->features[FEAT_8000_0007_EDX];
2617 break;
c6dc6f63
AP		 2618 case 0x80000008:
2619 /* virtual & phys address size in low 2 bytes. */
2620/* XXX: This value must match the one used in the MMU code. */
0514ef2f 2621 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
c6dc6f63
AP		 2622 /* 64 bit processor */
2623/* XXX: The physical address space is limited to 42 bits in exec.c. */
dd13e088 2624 *eax = 0x00003028; /* 48 bits virtual, 40 bits physical */
c6dc6f63 2625 } else {
0514ef2f 2626 if (env->features[FEAT_1_EDX] & CPUID_PSE36) {
c6dc6f63 2627 *eax = 0x00000024; /* 36 bits physical */
dd13e088 2628 } else {
c6dc6f63 2629 *eax = 0x00000020; /* 32 bits physical */
dd13e088 2630 }
c6dc6f63
AP		 2631 }
2632 *ebx = 0;
2633 *ecx = 0;
2634 *edx = 0;
ce3960eb
AF		 2635 if (cs->nr_cores * cs->nr_threads > 1) {
2636 *ecx |= (cs->nr_cores * cs->nr_threads) - 1;
c6dc6f63
AP		 2637 }
2638 break;
2639 case 0x8000000A:
0514ef2f 2640 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
9f3fb565
EH		 2641 *eax = 0x00000001; /* SVM Revision */
2642 *ebx = 0x00000010; /* nr of ASIDs */
2643 *ecx = 0;
0514ef2f 2644 *edx = env->features[FEAT_SVM]; /* optional features */
9f3fb565
EH		 2645 } else {
2646 *eax = 0;
2647 *ebx = 0;
2648 *ecx = 0;
2649 *edx = 0;
2650 }
c6dc6f63 2651 break;
b3baa152
BW		 2652 case 0xC0000000:
2653 *eax = env->cpuid_xlevel2;
2654 *ebx = 0;
2655 *ecx = 0;
2656 *edx = 0;
2657 break;
2658 case 0xC0000001:
2659 /* Support for VIA CPU's CPUID instruction */
2660 *eax = env->cpuid_version;
2661 *ebx = 0;
2662 *ecx = 0;
0514ef2f 2663 *edx = env->features[FEAT_C000_0001_EDX];
b3baa152
BW		 2664 break;
2665 case 0xC0000002:
2666 case 0xC0000003:
2667 case 0xC0000004:
2668 /* Reserved for the future, and now filled with zero */
2669 *eax = 0;
2670 *ebx = 0;
2671 *ecx = 0;
2672 *edx = 0;
2673 break;
c6dc6f63
AP		 2674 default:
2675 /* reserved values: zero */
2676 *eax = 0;
2677 *ebx = 0;
2678 *ecx = 0;
2679 *edx = 0;
2680 break;
2681 }
2682}
5fd2087a
AF		 2683
2684/* CPUClass::reset() */
2685static void x86_cpu_reset(CPUState *s)
2686{
2687 X86CPU *cpu = X86_CPU(s);
2688 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
2689 CPUX86State *env = &cpu->env;
a114d25d
RH		 2690 target_ulong cr4;
2691 uint64_t xcr0;
c1958aea
AF		 2692 int i;
2693
5fd2087a
AF		 2694 xcc->parent_reset(s);
2695
43175fa9 2696 memset(env, 0, offsetof(CPUX86State, cpuid_level));
c1958aea 2697
00c8cb0a 2698 tlb_flush(s, 1);
c1958aea
AF		 2699
2700 env->old_exception = -1;
2701
2702 /* init to reset state */
2703
2704#ifdef CONFIG_SOFTMMU
2705 env->hflags |= HF_SOFTMMU_MASK;
2706#endif
2707 env->hflags2 |= HF2_GIF_MASK;
2708
2709 cpu_x86_update_cr0(env, 0x60000010);
2710 env->a20_mask = ~0x0;
2711 env->smbase = 0x30000;
2712
2713 env->idt.limit = 0xffff;
2714 env->gdt.limit = 0xffff;
2715 env->ldt.limit = 0xffff;
2716 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
2717 env->tr.limit = 0xffff;
2718 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
2719
2720 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
2721 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
2722 DESC_R_MASK | DESC_A_MASK);
2723 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
2724 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2725 DESC_A_MASK);
2726 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
2727 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2728 DESC_A_MASK);
2729 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
2730 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2731 DESC_A_MASK);
2732 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
2733 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2734 DESC_A_MASK);
2735 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
2736 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2737 DESC_A_MASK);
2738
2739 env->eip = 0xfff0;
2740 env->regs[R_EDX] = env->cpuid_version;
2741
2742 env->eflags = 0x2;
2743
2744 /* FPU init */
2745 for (i = 0; i < 8; i++) {
2746 env->fptags[i] = 1;
2747 }
5bde1407 2748 cpu_set_fpuc(env, 0x37f);
c1958aea
AF		 2749
2750 env->mxcsr = 0x1f80;
a114d25d
RH		 2751 /* All units are in INIT state. */
2752 env->xstate_bv = 0;
c1958aea
AF		 2753
2754 env->pat = 0x0007040600070406ULL;
2755 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
2756
2757 memset(env->dr, 0, sizeof(env->dr));
2758 env->dr[6] = DR6_FIXED_1;
2759 env->dr[7] = DR7_FIXED_1;
b3310ab3 2760 cpu_breakpoint_remove_all(s, BP_CPU);
75a34036 2761 cpu_watchpoint_remove_all(s, BP_CPU);
dd673288 2762
a114d25d 2763 cr4 = 0;
cfc3b074 2764 xcr0 = XSTATE_FP_MASK;
a114d25d
RH		 2765
2766#ifdef CONFIG_USER_ONLY
2767 /* Enable all the features for user-mode. */
2768 if (env->features[FEAT_1_EDX] & CPUID_SSE) {
cfc3b074 2769 xcr0 |= XSTATE_SSE_MASK;
a114d25d 2770 }
0f70ed47
PB		 2771 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
2772 const ExtSaveArea *esa = &x86_ext_save_areas[i];
2773 if ((env->features[esa->feature] & esa->bits) == esa->bits) {
2774 xcr0 |= 1ull << i;
2775 }
a114d25d 2776 }
0f70ed47 2777
a114d25d
RH		 2778 if (env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) {
2779 cr4 |= CR4_OSFXSR_MASK | CR4_OSXSAVE_MASK;
2780 }
07929f2a
RH		 2781 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE) {
2782 cr4 |= CR4_FSGSBASE_MASK;
2783 }
a114d25d
RH		 2784#endif
2785
2786 env->xcr0 = xcr0;
2787 cpu_x86_update_cr4(env, cr4);
0522604b 2788
9db2efd9
AW		 2789 /*
2790 * SDM 11.11.5 requires:
2791 * - IA32_MTRR_DEF_TYPE MSR.E = 0
2792 * - IA32_MTRR_PHYSMASKn.V = 0
2793 * All other bits are undefined. For simplification, zero it all.
2794 */
2795 env->mtrr_deftype = 0;
2796 memset(env->mtrr_var, 0, sizeof(env->mtrr_var));
2797 memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed));
2798
dd673288
IM		 2799#if !defined(CONFIG_USER_ONLY)
2800 /* We hard-wire the BSP to the first CPU. */
9cb11fd7 2801 apic_designate_bsp(cpu->apic_state, s->cpu_index == 0);
dd673288 2802
259186a7 2803 s->halted = !cpu_is_bsp(cpu);
50a2c6e5
PB		 2804
2805 if (kvm_enabled()) {
2806 kvm_arch_reset_vcpu(cpu);
2807 }
dd673288 2808#endif
5fd2087a
AF		 2809}
2810
dd673288
IM		 2811#ifndef CONFIG_USER_ONLY
2812bool cpu_is_bsp(X86CPU *cpu)
2813{
02e51483 2814 return cpu_get_apic_base(cpu->apic_state) & MSR_IA32_APICBASE_BSP;
dd673288 2815}
65dee380
IM		 2816
2817/* TODO: remove me, when reset over QOM tree is implemented */
2818static void x86_cpu_machine_reset_cb(void *opaque)
2819{
2820 X86CPU *cpu = opaque;
2821 cpu_reset(CPU(cpu));
2822}
dd673288
IM		 2823#endif
2824
de024815
AF		 2825static void mce_init(X86CPU *cpu)
2826{
2827 CPUX86State *cenv = &cpu->env;
2828 unsigned int bank;
2829
2830 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
0514ef2f 2831 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
de024815
AF		 2832 (CPUID_MCE | CPUID_MCA)) {
2833 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF;
2834 cenv->mcg_ctl = ~(uint64_t)0;
2835 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
2836 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
2837 }
2838 }
2839}
2840
bdeec802 2841#ifndef CONFIG_USER_ONLY
d3c64d6a 2842static void x86_cpu_apic_create(X86CPU *cpu, Error **errp)
bdeec802 2843{
449994eb 2844 APICCommonState *apic;
bdeec802
IM		 2845 const char *apic_type = "apic";
2846
15eafc2e 2847 if (kvm_apic_in_kernel()) {
bdeec802
IM		 2848 apic_type = "kvm-apic";
2849 } else if (xen_enabled()) {
2850 apic_type = "xen-apic";
2851 }
2852
46232aaa 2853 cpu->apic_state = DEVICE(object_new(apic_type));
bdeec802
IM		 2854
2855 object_property_add_child(OBJECT(cpu), "apic",
02e51483 2856 OBJECT(cpu->apic_state), NULL);
7e72a45c 2857 qdev_prop_set_uint8(cpu->apic_state, "id", cpu->apic_id);
bdeec802 2858 /* TODO: convert to link<> */
02e51483 2859 apic = APIC_COMMON(cpu->apic_state);
60671e58 2860 apic->cpu = cpu;
8d42d2d3 2861 apic->apicbase = APIC_DEFAULT_ADDRESS | MSR_IA32_APICBASE_ENABLE;
d3c64d6a
IM		 2862}
2863
2864static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2865{
8d42d2d3
CF		 2866 APICCommonState *apic;
2867 static bool apic_mmio_map_once;
2868
02e51483 2869 if (cpu->apic_state == NULL) {
d3c64d6a
IM		 2870 return;
2871 }
6e8e2651
MA		 2872 object_property_set_bool(OBJECT(cpu->apic_state), true, "realized",
2873 errp);
8d42d2d3
CF		 2874
2875 /* Map APIC MMIO area */
2876 apic = APIC_COMMON(cpu->apic_state);
2877 if (!apic_mmio_map_once) {
2878 memory_region_add_subregion_overlap(get_system_memory(),
2879 apic->apicbase &
2880 MSR_IA32_APICBASE_BASE,
2881 &apic->io_memory,
2882 0x1000);
2883 apic_mmio_map_once = true;
2884 }
bdeec802 2885}
f809c605
PB		 2886
2887static void x86_cpu_machine_done(Notifier *n, void *unused)
2888{
2889 X86CPU *cpu = container_of(n, X86CPU, machine_done);
2890 MemoryRegion *smram =
2891 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
2892
2893 if (smram) {
2894 cpu->smram = g_new(MemoryRegion, 1);
2895 memory_region_init_alias(cpu->smram, OBJECT(cpu), "smram",
2896 smram, 0, 1ull << 32);
2897 memory_region_set_enabled(cpu->smram, false);
2898 memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->smram, 1);
2899 }
2900}
d3c64d6a
IM		 2901#else
2902static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2903{
2904}
bdeec802
IM		 2905#endif
2906
e48638fd
WH		 2907
2908#define IS_INTEL_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && \
2909 (env)->cpuid_vendor2 == CPUID_VENDOR_INTEL_2 && \
2910 (env)->cpuid_vendor3 == CPUID_VENDOR_INTEL_3)
2911#define IS_AMD_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_AMD_1 && \
2912 (env)->cpuid_vendor2 == CPUID_VENDOR_AMD_2 && \
2913 (env)->cpuid_vendor3 == CPUID_VENDOR_AMD_3)
2b6f294c 2914static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
7a059953 2915{
14a10fc3 2916 CPUState *cs = CPU(dev);
2b6f294c
AF		 2917 X86CPU *cpu = X86_CPU(dev);
2918 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
b34d12d1 2919 CPUX86State *env = &cpu->env;
2b6f294c 2920 Error *local_err = NULL;
e48638fd 2921 static bool ht_warned;
b34d12d1 2922
9886e834
EH		 2923 if (cpu->apic_id < 0) {
2924 error_setg(errp, "apic-id property was not initialized properly");
2925 return;
2926 }
2927
0514ef2f 2928 if (env->features[FEAT_7_0_EBX] && env->cpuid_level < 7) {
b34d12d1
IM		 2929 env->cpuid_level = 7;
2930 }
7a059953 2931
9997cf7b
EH		 2932 if (x86_cpu_filter_features(cpu) && cpu->enforce_cpuid) {
2933 error_setg(&local_err,
2934 kvm_enabled() ?
2935 "Host doesn't support requested features" :
2936 "TCG doesn't support requested features");
2937 goto out;
2938 }
2939
9b15cd9e
IM		 2940 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
2941 * CPUID[1].EDX.
2942 */
e48638fd 2943 if (IS_AMD_CPU(env)) {
0514ef2f
EH		 2944 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES;
2945 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX]
9b15cd9e
IM		 2946 & CPUID_EXT2_AMD_ALIASES);
2947 }
2948
fefb41bf 2949
42ecabaa
EH		 2950 cpu_exec_init(cs, &error_abort);
2951
57f2453a
EH		 2952 if (tcg_enabled()) {
2953 tcg_x86_init();
2954 }
2955
65dee380
IM		 2956#ifndef CONFIG_USER_ONLY
2957 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
bdeec802 2958
0514ef2f 2959 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || smp_cpus > 1) {
d3c64d6a 2960 x86_cpu_apic_create(cpu, &local_err);
2b6f294c 2961 if (local_err != NULL) {
4dc1f449 2962 goto out;
bdeec802
IM		 2963 }
2964 }
65dee380
IM		 2965#endif
2966
7a059953 2967 mce_init(cpu);
2001d0cd
PB		 2968
2969#ifndef CONFIG_USER_ONLY
2970 if (tcg_enabled()) {
56943e8c
PM		 2971 AddressSpace *newas = g_new(AddressSpace, 1);
2972
f809c605 2973 cpu->cpu_as_mem = g_new(MemoryRegion, 1);
2001d0cd 2974 cpu->cpu_as_root = g_new(MemoryRegion, 1);
f809c605
PB		 2975
2976 /* Outer container... */
2977 memory_region_init(cpu->cpu_as_root, OBJECT(cpu), "memory", ~0ull);
2001d0cd 2978 memory_region_set_enabled(cpu->cpu_as_root, true);
f809c605
PB		 2979
2980 /* ... with two regions inside: normal system memory with low
2981 * priority, and...
2982 */
2983 memory_region_init_alias(cpu->cpu_as_mem, OBJECT(cpu), "memory",
2984 get_system_memory(), 0, ~0ull);
2985 memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->cpu_as_mem, 0);
2986 memory_region_set_enabled(cpu->cpu_as_mem, true);
56943e8c 2987 address_space_init(newas, cpu->cpu_as_root, "CPU");
12ebc9a7 2988 cs->num_ases = 1;
56943e8c 2989 cpu_address_space_init(cs, newas, 0);
f809c605
PB		 2990
2991 /* ... SMRAM with higher priority, linked from /machine/smram. */
2992 cpu->machine_done.notify = x86_cpu_machine_done;
2993 qemu_add_machine_init_done_notifier(&cpu->machine_done);
2001d0cd
PB		 2994 }
2995#endif
2996
14a10fc3 2997 qemu_init_vcpu(cs);
d3c64d6a 2998
e48638fd
WH		 2999 /* Only Intel CPUs support hyperthreading. Even though QEMU fixes this
3000 * issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX
3001 * based on inputs (sockets,cores,threads), it is still better to gives
3002 * users a warning.
3003 *
3004 * NOTE: the following code has to follow qemu_init_vcpu(). Otherwise
3005 * cs->nr_threads hasn't be populated yet and the checking is incorrect.
3006 */
3007 if (!IS_INTEL_CPU(env) && cs->nr_threads > 1 && !ht_warned) {
3008 error_report("AMD CPU doesn't support hyperthreading. Please configure"
3009 " -smp options properly.");
3010 ht_warned = true;
3011 }
3012
d3c64d6a
IM		 3013 x86_cpu_apic_realize(cpu, &local_err);
3014 if (local_err != NULL) {
3015 goto out;
3016 }
14a10fc3 3017 cpu_reset(cs);
2b6f294c 3018
4dc1f449 3019 xcc->parent_realize(dev, &local_err);
2001d0cd 3020
4dc1f449
IM		 3021out:
3022 if (local_err != NULL) {
3023 error_propagate(errp, local_err);
3024 return;
3025 }
7a059953
AF		 3026}
3027
38e5c119
EH		 3028typedef struct BitProperty {
3029 uint32_t *ptr;
3030 uint32_t mask;
3031} BitProperty;
3032
d7bce999
EB		 3033static void x86_cpu_get_bit_prop(Object *obj, Visitor *v, const char *name,
3034 void *opaque, Error **errp)
38e5c119
EH		 3035{
3036 BitProperty *fp = opaque;
3037 bool value = (*fp->ptr & fp->mask) == fp->mask;
51e72bc1 3038 visit_type_bool(v, name, &value, errp);
38e5c119
EH		 3039}
3040
d7bce999
EB		 3041static void x86_cpu_set_bit_prop(Object *obj, Visitor *v, const char *name,
3042 void *opaque, Error **errp)
38e5c119
EH		 3043{
3044 DeviceState *dev = DEVICE(obj);
3045 BitProperty *fp = opaque;
3046 Error *local_err = NULL;
3047 bool value;
3048
3049 if (dev->realized) {
3050 qdev_prop_set_after_realize(dev, name, errp);
3051 return;
3052 }
3053
51e72bc1 3054 visit_type_bool(v, name, &value, &local_err);
38e5c119
EH		 3055 if (local_err) {
3056 error_propagate(errp, local_err);
3057 return;
3058 }
3059
3060 if (value) {
3061 *fp->ptr |= fp->mask;
3062 } else {
3063 *fp->ptr &= ~fp->mask;
3064 }
3065}
3066
3067static void x86_cpu_release_bit_prop(Object *obj, const char *name,
3068 void *opaque)
3069{
3070 BitProperty *prop = opaque;
3071 g_free(prop);
3072}
3073
3074/* Register a boolean property to get/set a single bit in a uint32_t field.
3075 *
3076 * The same property name can be registered multiple times to make it affect
3077 * multiple bits in the same FeatureWord. In that case, the getter will return
3078 * true only if all bits are set.
3079 */
3080static void x86_cpu_register_bit_prop(X86CPU *cpu,
3081 const char *prop_name,
3082 uint32_t *field,
3083 int bitnr)
3084{
3085 BitProperty *fp;
3086 ObjectProperty *op;
3087 uint32_t mask = (1UL << bitnr);
3088
3089 op = object_property_find(OBJECT(cpu), prop_name, NULL);
3090 if (op) {
3091 fp = op->opaque;
3092 assert(fp->ptr == field);
3093 fp->mask |= mask;
3094 } else {
3095 fp = g_new0(BitProperty, 1);
3096 fp->ptr = field;
3097 fp->mask = mask;
3098 object_property_add(OBJECT(cpu), prop_name, "bool",
3099 x86_cpu_get_bit_prop,
3100 x86_cpu_set_bit_prop,
3101 x86_cpu_release_bit_prop, fp, &error_abort);
3102 }
3103}
3104
3105static void x86_cpu_register_feature_bit_props(X86CPU *cpu,
3106 FeatureWord w,
3107 int bitnr)
3108{
3109 Object *obj = OBJECT(cpu);
3110 int i;
3111 char **names;
3112 FeatureWordInfo *fi = &feature_word_info[w];
3113
3114 if (!fi->feat_names) {
3115 return;
3116 }
3117 if (!fi->feat_names[bitnr]) {
3118 return;
3119 }
3120
3121 names = g_strsplit(fi->feat_names[bitnr], "|", 0);
3122
3123 feat2prop(names[0]);
3124 x86_cpu_register_bit_prop(cpu, names[0], &cpu->env.features[w], bitnr);
3125
3126 for (i = 1; names[i]; i++) {
3127 feat2prop(names[i]);
d461a44c 3128 object_property_add_alias(obj, names[i], obj, names[0],
38e5c119
EH		 3129 &error_abort);
3130 }
3131
3132 g_strfreev(names);
3133}
3134
de024815
AF		 3135static void x86_cpu_initfn(Object *obj)
3136{
55e5c285 3137 CPUState *cs = CPU(obj);
de024815 3138 X86CPU *cpu = X86_CPU(obj);
d940ee9b 3139 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj);
de024815 3140 CPUX86State *env = &cpu->env;
38e5c119 3141 FeatureWord w;
de024815 3142
c05efcb1 3143 cs->env_ptr = env;
71ad61d3
AF		 3144
3145 object_property_add(obj, "family", "int",
95b8519d 3146 x86_cpuid_version_get_family,
71ad61d3 3147 x86_cpuid_version_set_family, NULL, NULL, NULL);
c5291a4f 3148 object_property_add(obj, "model", "int",
67e30c83 3149 x86_cpuid_version_get_model,
c5291a4f 3150 x86_cpuid_version_set_model, NULL, NULL, NULL);
036e2222 3151 object_property_add(obj, "stepping", "int",
35112e41 3152 x86_cpuid_version_get_stepping,
036e2222 3153 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
d480e1af
AF		 3154 object_property_add_str(obj, "vendor",
3155 x86_cpuid_get_vendor,
3156 x86_cpuid_set_vendor, NULL);
938d4c25 3157 object_property_add_str(obj, "model-id",
63e886eb 3158 x86_cpuid_get_model_id,
938d4c25 3159 x86_cpuid_set_model_id, NULL);
89e48965
AF		 3160 object_property_add(obj, "tsc-frequency", "int",
3161 x86_cpuid_get_tsc_freq,
3162 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
31050930
IM		 3163 object_property_add(obj, "apic-id", "int",
3164 x86_cpuid_get_apic_id,
3165 x86_cpuid_set_apic_id, NULL, NULL, NULL);
8e8aba50
EH		 3166 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo",
3167 x86_cpu_get_feature_words,
7e5292b5
EH		 3168 NULL, NULL, (void *)env->features, NULL);
3169 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo",
3170 x86_cpu_get_feature_words,
3171 NULL, NULL, (void *)cpu->filtered_features, NULL);
71ad61d3 3172
92067bf4 3173 cpu->hyperv_spinlock_attempts = HYPERV_SPINLOCK_NEVER_RETRY;
d65e9815 3174
9886e834
EH		 3175#ifndef CONFIG_USER_ONLY
3176 /* Any code creating new X86CPU objects have to set apic-id explicitly */
3177 cpu->apic_id = -1;
3178#endif
3179
38e5c119
EH		 3180 for (w = 0; w < FEATURE_WORDS; w++) {
3181 int bitnr;
3182
3183 for (bitnr = 0; bitnr < 32; bitnr++) {
3184 x86_cpu_register_feature_bit_props(cpu, w, bitnr);
3185 }
3186 }
3187
d940ee9b 3188 x86_cpu_load_def(cpu, xcc->cpu_def, &error_abort);
de024815
AF		 3189}
3190
997395d3
IM		 3191static int64_t x86_cpu_get_arch_id(CPUState *cs)
3192{
3193 X86CPU *cpu = X86_CPU(cs);
997395d3 3194
7e72a45c 3195 return cpu->apic_id;
997395d3
IM		 3196}
3197
444d5590
AF		 3198static bool x86_cpu_get_paging_enabled(const CPUState *cs)
3199{
3200 X86CPU *cpu = X86_CPU(cs);
3201
3202 return cpu->env.cr[0] & CR0_PG_MASK;
3203}
3204
f45748f1
AF		 3205static void x86_cpu_set_pc(CPUState *cs, vaddr value)
3206{
3207 X86CPU *cpu = X86_CPU(cs);
3208
3209 cpu->env.eip = value;
3210}
3211
bdf7ae5b
AF		 3212static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
3213{
3214 X86CPU *cpu = X86_CPU(cs);
3215
3216 cpu->env.eip = tb->pc - tb->cs_base;
3217}
3218
8c2e1b00
AF		 3219static bool x86_cpu_has_work(CPUState *cs)
3220{
3221 X86CPU *cpu = X86_CPU(cs);
3222 CPUX86State *env = &cpu->env;
3223
6220e900
PD		 3224 return ((cs->interrupt_request & (CPU_INTERRUPT_HARD |
3225 CPU_INTERRUPT_POLL)) &&
8c2e1b00
AF		 3226 (env->eflags & IF_MASK)) ||
3227 (cs->interrupt_request & (CPU_INTERRUPT_NMI |
3228 CPU_INTERRUPT_INIT |
3229 CPU_INTERRUPT_SIPI |
a9bad65d
PB		 3230 CPU_INTERRUPT_MCE)) ||
3231 ((cs->interrupt_request & CPU_INTERRUPT_SMI) &&
3232 !(env->hflags & HF_SMM_MASK));
8c2e1b00
AF		 3233}
3234
9337e3b6
EH		 3235static Property x86_cpu_properties[] = {
3236 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false),
c8f0f88e 3237 { .name = "hv-spinlocks", .info = &qdev_prop_spinlocks },
89314504 3238 DEFINE_PROP_BOOL("hv-relaxed", X86CPU, hyperv_relaxed_timing, false),
0f46685d 3239 DEFINE_PROP_BOOL("hv-vapic", X86CPU, hyperv_vapic, false),
48a5f3bc 3240 DEFINE_PROP_BOOL("hv-time", X86CPU, hyperv_time, false),
f2a53c9e 3241 DEFINE_PROP_BOOL("hv-crash", X86CPU, hyperv_crash, false),
744b8a94 3242 DEFINE_PROP_BOOL("hv-reset", X86CPU, hyperv_reset, false),
8c145d7c 3243 DEFINE_PROP_BOOL("hv-vpindex", X86CPU, hyperv_vpindex, false),
46eb8f98 3244 DEFINE_PROP_BOOL("hv-runtime", X86CPU, hyperv_runtime, false),
866eea9a 3245 DEFINE_PROP_BOOL("hv-synic", X86CPU, hyperv_synic, false),
ff99aa64 3246 DEFINE_PROP_BOOL("hv-stimer", X86CPU, hyperv_stimer, false),
15e41345 3247 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, true),
912ffc47 3248 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false),
f522d2ac 3249 DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true),
b9472b76
EH		 3250 DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, 0),
3251 DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, 0),
01431f3c 3252 DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, 0),
1c4a55db 3253 DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor_id),
9337e3b6
EH		 3254 DEFINE_PROP_END_OF_LIST()
3255};
3256
5fd2087a
AF		 3257static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
3258{
3259 X86CPUClass *xcc = X86_CPU_CLASS(oc);
3260 CPUClass *cc = CPU_CLASS(oc);
2b6f294c
AF		 3261 DeviceClass *dc = DEVICE_CLASS(oc);
3262
3263 xcc->parent_realize = dc->realize;
3264 dc->realize = x86_cpu_realizefn;
9337e3b6 3265 dc->props = x86_cpu_properties;
5fd2087a
AF		 3266
3267 xcc->parent_reset = cc->reset;
3268 cc->reset = x86_cpu_reset;
91b1df8c 3269 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP;
f56e3a14 3270
500050d1 3271 cc->class_by_name = x86_cpu_class_by_name;
94a444b2 3272 cc->parse_features = x86_cpu_parse_featurestr;
8c2e1b00 3273 cc->has_work = x86_cpu_has_work;
97a8ea5a 3274 cc->do_interrupt = x86_cpu_do_interrupt;
42f53fea 3275 cc->cpu_exec_interrupt = x86_cpu_exec_interrupt;
878096ee 3276 cc->dump_state = x86_cpu_dump_state;
f45748f1 3277 cc->set_pc = x86_cpu_set_pc;
bdf7ae5b 3278 cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
5b50e790
AF		 3279 cc->gdb_read_register = x86_cpu_gdb_read_register;
3280 cc->gdb_write_register = x86_cpu_gdb_write_register;
444d5590
AF		 3281 cc->get_arch_id = x86_cpu_get_arch_id;
3282 cc->get_paging_enabled = x86_cpu_get_paging_enabled;
7510454e
AF		 3283#ifdef CONFIG_USER_ONLY
3284 cc->handle_mmu_fault = x86_cpu_handle_mmu_fault;
3285#else
a23bbfda 3286 cc->get_memory_mapping = x86_cpu_get_memory_mapping;
00b941e5 3287 cc->get_phys_page_debug = x86_cpu_get_phys_page_debug;
c72bf468
JF		 3288 cc->write_elf64_note = x86_cpu_write_elf64_note;
3289 cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
3290 cc->write_elf32_note = x86_cpu_write_elf32_note;
3291 cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
00b941e5 3292 cc->vmsd = &vmstate_x86_cpu;
c72bf468 3293#endif
a0e372f0 3294 cc->gdb_num_core_regs = CPU_NB_REGS * 2 + 25;
86025ee4
PM		 3295#ifndef CONFIG_USER_ONLY
3296 cc->debug_excp_handler = breakpoint_handler;
3297#endif
374e0cd4
RH		 3298 cc->cpu_exec_enter = x86_cpu_exec_enter;
3299 cc->cpu_exec_exit = x86_cpu_exec_exit;
4c315c27
MA		 3300
3301 /*
3302 * Reason: x86_cpu_initfn() calls cpu_exec_init(), which saves the
3303 * object in cpus -> dangling pointer after final object_unref().
3304 */
3305 dc->cannot_destroy_with_object_finalize_yet = true;
5fd2087a
AF		 3306}
3307
3308static const TypeInfo x86_cpu_type_info = {
3309 .name = TYPE_X86_CPU,
3310 .parent = TYPE_CPU,
3311 .instance_size = sizeof(X86CPU),
de024815 3312 .instance_init = x86_cpu_initfn,
d940ee9b 3313 .abstract = true,
5fd2087a
AF		 3314 .class_size = sizeof(X86CPUClass),
3315 .class_init = x86_cpu_common_class_init,
3316};
3317
3318static void x86_cpu_register_types(void)
3319{
d940ee9b
EH		 3320 int i;
3321
5fd2087a 3322 type_register_static(&x86_cpu_type_info);
d940ee9b
EH		 3323 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
3324 x86_register_cpudef_type(&builtin_x86_defs[i]);
3325 }
3326#ifdef CONFIG_KVM
3327 type_register_static(&host_x86_cpu_type_info);
3328#endif
5fd2087a
AF		 3329}
3330
3331type_init(x86_cpu_register_types)
Empty description
This page took 1.217655 seconds and 4 git commands to generate.