]> Git Repo - qemu.git/blame - target/i386/cpu.c
projects / qemu.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
i386: Document when features can be added to kvm_default_props
[qemu.git] / target / i386 / cpu.c
CommitLineData
c6dc6f63 1/*
79f1a68a 2 * i386 CPUID, CPU class, definitions, models
c6dc6f63
AP		 3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
d9ff33ad 9 * version 2.1 of the License, or (at your option) any later version.
c6dc6f63
AP		 10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
e688df6b 19
1ef26b1f 20#include "qemu/osdep.h"
6a4e0614 21#include "qemu/units.h"
f348b6d1 22#include "qemu/cutils.h"
0442428a 23#include "qemu/qemu-print.h"
c6dc6f63 24#include "cpu.h"
ed69e831 25#include "tcg/helper-tcg.h"
71e8a915 26#include "sysemu/reset.h"
d6dcc558 27#include "sysemu/hvf.h"
a9dc68d9 28#include "kvm/kvm_i386.h"
6cb8f2a6 29#include "sev_i386.h"
8ac25c84 30#include "qapi/qapi-visit-machine.h"
7b1b5d19 31#include "qapi/qmp/qerror.h"
7f7b4e7a 32#include "qapi/qapi-commands-machine-target.h"
1814eab6 33#include "standard-headers/asm-x86/kvm_para.h"
53a89e26 34#include "hw/qdev-properties.h"
5232d00a 35#include "hw/i386/topology.h"
bdeec802 36#ifndef CONFIG_USER_ONLY
2001d0cd 37#include "exec/address-spaces.h"
0e11fc69 38#include "hw/boards.h"
bdeec802
IM		 39#endif
40
b666d2a4 41#include "disas/capstone.h"
79f1a68a 42#include "cpu-internal.h"
b666d2a4 43
7e3482f8
EH		 44/* Helpers for building CPUID[2] descriptors: */
45
46struct CPUID2CacheDescriptorInfo {
47 enum CacheType type;
48 int level;
49 int size;
50 int line_size;
51 int associativity;
52};
5e891bf8 53
7e3482f8
EH		 54/*
55 * Known CPUID 2 cache descriptors.
56 * From Intel SDM Volume 2A, CPUID instruction
57 */
58struct CPUID2CacheDescriptorInfo cpuid2_cache_descriptors[] = {
5f00335a 59 [0x06] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 8 * KiB,
7e3482f8 60 .associativity = 4, .line_size = 32, },
5f00335a 61 [0x08] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 16 * KiB,
7e3482f8 62 .associativity = 4, .line_size = 32, },
5f00335a 63 [0x09] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB,
7e3482f8 64 .associativity = 4, .line_size = 64, },
5f00335a 65 [0x0A] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB,
7e3482f8 66 .associativity = 2, .line_size = 32, },
5f00335a 67 [0x0C] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
7e3482f8 68 .associativity = 4, .line_size = 32, },
5f00335a 69 [0x0D] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
7e3482f8 70 .associativity = 4, .line_size = 64, },
5f00335a 71 [0x0E] = { .level = 1, .type = DATA_CACHE, .size = 24 * KiB,
7e3482f8 72 .associativity = 6, .line_size = 64, },
5f00335a 73 [0x1D] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB,
7e3482f8 74 .associativity = 2, .line_size = 64, },
5f00335a 75 [0x21] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
7e3482f8
EH		 76 .associativity = 8, .line_size = 64, },
77 /* lines per sector is not supported cpuid2_cache_descriptor(),
78 * so descriptors 0x22, 0x23 are not included
79 */
5f00335a 80 [0x24] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8
EH		 81 .associativity = 16, .line_size = 64, },
82 /* lines per sector is not supported cpuid2_cache_descriptor(),
83 * so descriptors 0x25, 0x20 are not included
84 */
5f00335a 85 [0x2C] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB,
7e3482f8 86 .associativity = 8, .line_size = 64, },
5f00335a 87 [0x30] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB,
7e3482f8 88 .associativity = 8, .line_size = 64, },
5f00335a 89 [0x41] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB,
7e3482f8 90 .associativity = 4, .line_size = 32, },
5f00335a 91 [0x42] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
7e3482f8 92 .associativity = 4, .line_size = 32, },
5f00335a 93 [0x43] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
7e3482f8 94 .associativity = 4, .line_size = 32, },
5f00335a 95 [0x44] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8 96 .associativity = 4, .line_size = 32, },
5f00335a 97 [0x45] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
7e3482f8 98 .associativity = 4, .line_size = 32, },
5f00335a 99 [0x46] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
7e3482f8 100 .associativity = 4, .line_size = 64, },
5f00335a 101 [0x47] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
7e3482f8 102 .associativity = 8, .line_size = 64, },
5f00335a 103 [0x48] = { .level = 2, .type = UNIFIED_CACHE, .size = 3 * MiB,
7e3482f8
EH		 104 .associativity = 12, .line_size = 64, },
105 /* Descriptor 0x49 depends on CPU family/model, so it is not included */
5f00335a 106 [0x4A] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB,
7e3482f8 107 .associativity = 12, .line_size = 64, },
5f00335a 108 [0x4B] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
7e3482f8 109 .associativity = 16, .line_size = 64, },
5f00335a 110 [0x4C] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB,
7e3482f8 111 .associativity = 12, .line_size = 64, },
5f00335a 112 [0x4D] = { .level = 3, .type = UNIFIED_CACHE, .size = 16 * MiB,
7e3482f8 113 .associativity = 16, .line_size = 64, },
5f00335a 114 [0x4E] = { .level = 2, .type = UNIFIED_CACHE, .size = 6 * MiB,
7e3482f8 115 .associativity = 24, .line_size = 64, },
5f00335a 116 [0x60] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
7e3482f8 117 .associativity = 8, .line_size = 64, },
5f00335a 118 [0x66] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB,
7e3482f8 119 .associativity = 4, .line_size = 64, },
5f00335a 120 [0x67] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
7e3482f8 121 .associativity = 4, .line_size = 64, },
5f00335a 122 [0x68] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB,
7e3482f8 123 .associativity = 4, .line_size = 64, },
5f00335a 124 [0x78] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8
EH		 125 .associativity = 4, .line_size = 64, },
126 /* lines per sector is not supported cpuid2_cache_descriptor(),
127 * so descriptors 0x79, 0x7A, 0x7B, 0x7C are not included.
128 */
5f00335a 129 [0x7D] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
7e3482f8 130 .associativity = 8, .line_size = 64, },
5f00335a 131 [0x7F] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
7e3482f8 132 .associativity = 2, .line_size = 64, },
5f00335a 133 [0x80] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
7e3482f8 134 .associativity = 8, .line_size = 64, },
5f00335a 135 [0x82] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
7e3482f8 136 .associativity = 8, .line_size = 32, },
5f00335a 137 [0x83] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
7e3482f8 138 .associativity = 8, .line_size = 32, },
5f00335a 139 [0x84] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8 140 .associativity = 8, .line_size = 32, },
5f00335a 141 [0x85] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
7e3482f8 142 .associativity = 8, .line_size = 32, },
5f00335a 143 [0x86] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
7e3482f8 144 .associativity = 4, .line_size = 64, },
5f00335a 145 [0x87] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8 146 .associativity = 8, .line_size = 64, },
5f00335a 147 [0xD0] = { .level = 3, .type = UNIFIED_CACHE, .size = 512 * KiB,
7e3482f8 148 .associativity = 4, .line_size = 64, },
5f00335a 149 [0xD1] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8 150 .associativity = 4, .line_size = 64, },
5f00335a 151 [0xD2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
7e3482f8 152 .associativity = 4, .line_size = 64, },
5f00335a 153 [0xD6] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8 154 .associativity = 8, .line_size = 64, },
5f00335a 155 [0xD7] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
7e3482f8 156 .associativity = 8, .line_size = 64, },
5f00335a 157 [0xD8] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
7e3482f8 158 .associativity = 8, .line_size = 64, },
5f00335a 159 [0xDC] = { .level = 3, .type = UNIFIED_CACHE, .size = 1.5 * MiB,
7e3482f8 160 .associativity = 12, .line_size = 64, },
5f00335a 161 [0xDD] = { .level = 3, .type = UNIFIED_CACHE, .size = 3 * MiB,
7e3482f8 162 .associativity = 12, .line_size = 64, },
5f00335a 163 [0xDE] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB,
7e3482f8 164 .associativity = 12, .line_size = 64, },
5f00335a 165 [0xE2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
7e3482f8 166 .associativity = 16, .line_size = 64, },
5f00335a 167 [0xE3] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
7e3482f8 168 .associativity = 16, .line_size = 64, },
5f00335a 169 [0xE4] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
7e3482f8 170 .associativity = 16, .line_size = 64, },
5f00335a 171 [0xEA] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB,
7e3482f8 172 .associativity = 24, .line_size = 64, },
5f00335a 173 [0xEB] = { .level = 3, .type = UNIFIED_CACHE, .size = 18 * MiB,
7e3482f8 174 .associativity = 24, .line_size = 64, },
5f00335a 175 [0xEC] = { .level = 3, .type = UNIFIED_CACHE, .size = 24 * MiB,
7e3482f8
EH		 176 .associativity = 24, .line_size = 64, },
177};
178
179/*
180 * "CPUID leaf 2 does not report cache descriptor information,
181 * use CPUID leaf 4 to query cache parameters"
182 */
183#define CACHE_DESCRIPTOR_UNAVAILABLE 0xFF
5e891bf8 184
7e3482f8
EH		 185/*
186 * Return a CPUID 2 cache descriptor for a given cache.
187 * If no known descriptor is found, return CACHE_DESCRIPTOR_UNAVAILABLE
188 */
189static uint8_t cpuid2_cache_descriptor(CPUCacheInfo *cache)
190{
191 int i;
192
193 assert(cache->size > 0);
194 assert(cache->level > 0);
195 assert(cache->line_size > 0);
196 assert(cache->associativity > 0);
197 for (i = 0; i < ARRAY_SIZE(cpuid2_cache_descriptors); i++) {
198 struct CPUID2CacheDescriptorInfo *d = &cpuid2_cache_descriptors[i];
199 if (d->level == cache->level && d->type == cache->type &&
200 d->size == cache->size && d->line_size == cache->line_size &&
201 d->associativity == cache->associativity) {
202 return i;
203 }
204 }
5e891bf8 205
7e3482f8
EH		 206 return CACHE_DESCRIPTOR_UNAVAILABLE;
207}
5e891bf8
EH		 208
209/* CPUID Leaf 4 constants: */
210
211/* EAX: */
7e3482f8
EH		 212#define CACHE_TYPE_D 1
213#define CACHE_TYPE_I 2
214#define CACHE_TYPE_UNIFIED 3
5e891bf8 215
7e3482f8 216#define CACHE_LEVEL(l) (l << 5)
5e891bf8 217
7e3482f8 218#define CACHE_SELF_INIT_LEVEL (1 << 8)
5e891bf8
EH		 219
220/* EDX: */
7e3482f8
EH		 221#define CACHE_NO_INVD_SHARING (1 << 0)
222#define CACHE_INCLUSIVE (1 << 1)
223#define CACHE_COMPLEX_IDX (1 << 2)
224
225/* Encode CacheType for CPUID[4].EAX */
5f00335a
EH		 226#define CACHE_TYPE(t) (((t) == DATA_CACHE) ? CACHE_TYPE_D : \
227 ((t) == INSTRUCTION_CACHE) ? CACHE_TYPE_I : \
228 ((t) == UNIFIED_CACHE) ? CACHE_TYPE_UNIFIED : \
229 0 /* Invalid value */)
7e3482f8
EH		 230
231
232/* Encode cache info for CPUID[4] */
233static void encode_cache_cpuid4(CPUCacheInfo *cache,
234 int num_apic_ids, int num_cores,
235 uint32_t *eax, uint32_t *ebx,
236 uint32_t *ecx, uint32_t *edx)
237{
238 assert(cache->size == cache->line_size * cache->associativity *
239 cache->partitions * cache->sets);
240
241 assert(num_apic_ids > 0);
242 *eax = CACHE_TYPE(cache->type) |
243 CACHE_LEVEL(cache->level) |
244 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0) |
245 ((num_cores - 1) << 26) |
246 ((num_apic_ids - 1) << 14);
247
248 assert(cache->line_size > 0);
249 assert(cache->partitions > 0);
250 assert(cache->associativity > 0);
251 /* We don't implement fully-associative caches */
252 assert(cache->associativity < cache->sets);
253 *ebx = (cache->line_size - 1) |
254 ((cache->partitions - 1) << 12) |
255 ((cache->associativity - 1) << 22);
256
257 assert(cache->sets > 0);
258 *ecx = cache->sets - 1;
259
260 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) |
261 (cache->inclusive ? CACHE_INCLUSIVE : 0) |
262 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0);
263}
264
265/* Encode cache info for CPUID[0x80000005].ECX or CPUID[0x80000005].EDX */
266static uint32_t encode_cache_cpuid80000005(CPUCacheInfo *cache)
267{
268 assert(cache->size % 1024 == 0);
269 assert(cache->lines_per_tag > 0);
270 assert(cache->associativity > 0);
271 assert(cache->line_size > 0);
272 return ((cache->size / 1024) << 24) | (cache->associativity << 16) |
273 (cache->lines_per_tag << 8) | (cache->line_size);
274}
5e891bf8
EH		 275
276#define ASSOC_FULL 0xFF
277
278/* AMD associativity encoding used on CPUID Leaf 0x80000006: */
279#define AMD_ENC_ASSOC(a) (a <= 1 ? a : \
280 a == 2 ? 0x2 : \
281 a == 4 ? 0x4 : \
282 a == 8 ? 0x6 : \
283 a == 16 ? 0x8 : \
284 a == 32 ? 0xA : \
285 a == 48 ? 0xB : \
286 a == 64 ? 0xC : \
287 a == 96 ? 0xD : \
288 a == 128 ? 0xE : \
289 a == ASSOC_FULL ? 0xF : \
290 0 /* invalid value */)
291
7e3482f8
EH		 292/*
293 * Encode cache info for CPUID[0x80000006].ECX and CPUID[0x80000006].EDX
294 * @l3 can be NULL.
295 */
296static void encode_cache_cpuid80000006(CPUCacheInfo *l2,
297 CPUCacheInfo *l3,
298 uint32_t *ecx, uint32_t *edx)
299{
300 assert(l2->size % 1024 == 0);
301 assert(l2->associativity > 0);
302 assert(l2->lines_per_tag > 0);
303 assert(l2->line_size > 0);
304 *ecx = ((l2->size / 1024) << 16) |
305 (AMD_ENC_ASSOC(l2->associativity) << 12) |
306 (l2->lines_per_tag << 8) | (l2->line_size);
307
308 if (l3) {
309 assert(l3->size % (512 * 1024) == 0);
310 assert(l3->associativity > 0);
311 assert(l3->lines_per_tag > 0);
312 assert(l3->line_size > 0);
313 *edx = ((l3->size / (512 * 1024)) << 18) |
314 (AMD_ENC_ASSOC(l3->associativity) << 12) |
315 (l3->lines_per_tag << 8) | (l3->line_size);
316 } else {
317 *edx = 0;
318 }
319}
5e891bf8 320
8f4202fb 321/* Encode cache info for CPUID[8000001D] */
2f084d1e
BM		 322static void encode_cache_cpuid8000001d(CPUCacheInfo *cache,
323 X86CPUTopoInfo *topo_info,
324 uint32_t *eax, uint32_t *ebx,
325 uint32_t *ecx, uint32_t *edx)
8f4202fb 326{
2f084d1e 327 uint32_t l3_threads;
8f4202fb
BM		 328 assert(cache->size == cache->line_size * cache->associativity *
329 cache->partitions * cache->sets);
330
331 *eax = CACHE_TYPE(cache->type) | CACHE_LEVEL(cache->level) |
332 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0);
333
334 /* L3 is shared among multiple cores */
335 if (cache->level == 3) {
2f084d1e
BM		 336 l3_threads = topo_info->cores_per_die * topo_info->threads_per_core;
337 *eax |= (l3_threads - 1) << 14;
8f4202fb 338 } else {
2f084d1e 339 *eax |= ((topo_info->threads_per_core - 1) << 14);
8f4202fb
BM		 340 }
341
342 assert(cache->line_size > 0);
343 assert(cache->partitions > 0);
344 assert(cache->associativity > 0);
345 /* We don't implement fully-associative caches */
346 assert(cache->associativity < cache->sets);
347 *ebx = (cache->line_size - 1) |
348 ((cache->partitions - 1) << 12) |
349 ((cache->associativity - 1) << 22);
350
351 assert(cache->sets > 0);
352 *ecx = cache->sets - 1;
353
354 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) |
355 (cache->inclusive ? CACHE_INCLUSIVE : 0) |
356 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0);
357}
358
ed78467a 359/* Encode cache info for CPUID[8000001E] */
31ada106
BM		 360static void encode_topo_cpuid8000001e(X86CPU *cpu, X86CPUTopoInfo *topo_info,
361 uint32_t *eax, uint32_t *ebx,
362 uint32_t *ecx, uint32_t *edx)
ed78467a 363{
31ada106
BM		 364 X86CPUTopoIDs topo_ids;
365
366 x86_topo_ids_from_apicid(cpu->apic_id, topo_info, &topo_ids);
ed78467a 367
ed78467a 368 *eax = cpu->apic_id;
31ada106 369
ed78467a 370 /*
31ada106
BM		 371 * CPUID_Fn8000001E_EBX [Core Identifiers] (CoreId)
372 * Read-only. Reset: 0000_XXXXh.
373 * See Core::X86::Cpuid::ExtApicId.
374 * Core::X86::Cpuid::CoreId_lthree[1:0]_core[3:0]_thread[1:0];
375 * Bits Description
376 * 31:16 Reserved.
377 * 15:8 ThreadsPerCore: threads per core. Read-only. Reset: XXh.
378 * The number of threads per core is ThreadsPerCore+1.
379 * 7:0 CoreId: core ID. Read-only. Reset: XXh.
380 *
381 * NOTE: CoreId is already part of apic_id. Just use it. We can
382 * use all the 8 bits to represent the core_id here.
ed78467a 383 */
31ada106
BM		 384 *ebx = ((topo_info->threads_per_core - 1) << 8) | (topo_ids.core_id & 0xFF);
385
ed78467a 386 /*
31ada106
BM		 387 * CPUID_Fn8000001E_ECX [Node Identifiers] (NodeId)
388 * Read-only. Reset: 0000_0XXXh.
389 * Core::X86::Cpuid::NodeId_lthree[1:0]_core[3:0]_thread[1:0];
390 * Bits Description
391 * 31:11 Reserved.
392 * 10:8 NodesPerProcessor: Node per processor. Read-only. Reset: XXXb.
393 * ValidValues:
394 * Value Description
395 * 000b 1 node per processor.
396 * 001b 2 nodes per processor.
397 * 010b Reserved.
398 * 011b 4 nodes per processor.
399 * 111b-100b Reserved.
400 * 7:0 NodeId: Node ID. Read-only. Reset: XXh.
401 *
402 * NOTE: Hardware reserves 3 bits for number of nodes per processor.
403 * But users can create more nodes than the actual hardware can
404 * support. To genaralize we can use all the upper 8 bits for nodes.
405 * NodeId is combination of node and socket_id which is already decoded
406 * in apic_id. Just use it by shifting.
ed78467a 407 */
31ada106
BM		 408 *ecx = ((topo_info->dies_per_pkg - 1) << 8) |
409 ((cpu->apic_id >> apicid_die_offset(topo_info)) & 0xFF);
410
ed78467a
BM		 411 *edx = 0;
412}
413
ab8f992e
BM		 414/*
415 * Definitions of the hardcoded cache entries we expose:
416 * These are legacy cache values. If there is a need to change any
417 * of these values please use builtin_x86_defs
418 */
5e891bf8
EH		 419
420/* L1 data cache: */
ab8f992e 421static CPUCacheInfo legacy_l1d_cache = {
5f00335a 422 .type = DATA_CACHE,
7e3482f8
EH		 423 .level = 1,
424 .size = 32 * KiB,
425 .self_init = 1,
426 .line_size = 64,
427 .associativity = 8,
428 .sets = 64,
429 .partitions = 1,
430 .no_invd_sharing = true,
431};
432
5e891bf8 433/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
ab8f992e 434static CPUCacheInfo legacy_l1d_cache_amd = {
5f00335a 435 .type = DATA_CACHE,
7e3482f8
EH		 436 .level = 1,
437 .size = 64 * KiB,
438 .self_init = 1,
439 .line_size = 64,
440 .associativity = 2,
441 .sets = 512,
442 .partitions = 1,
443 .lines_per_tag = 1,
444 .no_invd_sharing = true,
445};
5e891bf8
EH		 446
447/* L1 instruction cache: */
ab8f992e 448static CPUCacheInfo legacy_l1i_cache = {
5f00335a 449 .type = INSTRUCTION_CACHE,
7e3482f8
EH		 450 .level = 1,
451 .size = 32 * KiB,
452 .self_init = 1,
453 .line_size = 64,
454 .associativity = 8,
455 .sets = 64,
456 .partitions = 1,
457 .no_invd_sharing = true,
458};
459
5e891bf8 460/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
ab8f992e 461static CPUCacheInfo legacy_l1i_cache_amd = {
5f00335a 462 .type = INSTRUCTION_CACHE,
7e3482f8
EH		 463 .level = 1,
464 .size = 64 * KiB,
465 .self_init = 1,
466 .line_size = 64,
467 .associativity = 2,
468 .sets = 512,
469 .partitions = 1,
470 .lines_per_tag = 1,
471 .no_invd_sharing = true,
472};
5e891bf8
EH		 473
474/* Level 2 unified cache: */
ab8f992e 475static CPUCacheInfo legacy_l2_cache = {
7e3482f8
EH		 476 .type = UNIFIED_CACHE,
477 .level = 2,
478 .size = 4 * MiB,
479 .self_init = 1,
480 .line_size = 64,
481 .associativity = 16,
482 .sets = 4096,
483 .partitions = 1,
484 .no_invd_sharing = true,
485};
486
5e891bf8 487/*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
ab8f992e 488static CPUCacheInfo legacy_l2_cache_cpuid2 = {
7e3482f8
EH		 489 .type = UNIFIED_CACHE,
490 .level = 2,
491 .size = 2 * MiB,
492 .line_size = 64,
493 .associativity = 8,
494};
495
496
5e891bf8 497/*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
ab8f992e 498static CPUCacheInfo legacy_l2_cache_amd = {
7e3482f8
EH		 499 .type = UNIFIED_CACHE,
500 .level = 2,
501 .size = 512 * KiB,
502 .line_size = 64,
503 .lines_per_tag = 1,
504 .associativity = 16,
505 .sets = 512,
506 .partitions = 1,
507};
5e891bf8 508
14c985cf 509/* Level 3 unified cache: */
ab8f992e 510static CPUCacheInfo legacy_l3_cache = {
7e3482f8
EH		 511 .type = UNIFIED_CACHE,
512 .level = 3,
513 .size = 16 * MiB,
514 .line_size = 64,
515 .associativity = 16,
516 .sets = 16384,
517 .partitions = 1,
518 .lines_per_tag = 1,
519 .self_init = true,
520 .inclusive = true,
521 .complex_indexing = true,
522};
5e891bf8
EH		 523
524/* TLB definitions: */
525
526#define L1_DTLB_2M_ASSOC 1
527#define L1_DTLB_2M_ENTRIES 255
528#define L1_DTLB_4K_ASSOC 1
529#define L1_DTLB_4K_ENTRIES 255
530
531#define L1_ITLB_2M_ASSOC 1
532#define L1_ITLB_2M_ENTRIES 255
533#define L1_ITLB_4K_ASSOC 1
534#define L1_ITLB_4K_ENTRIES 255
535
536#define L2_DTLB_2M_ASSOC 0 /* disabled */
537#define L2_DTLB_2M_ENTRIES 0 /* disabled */
538#define L2_DTLB_4K_ASSOC 4
539#define L2_DTLB_4K_ENTRIES 512
540
541#define L2_ITLB_2M_ASSOC 0 /* disabled */
542#define L2_ITLB_2M_ENTRIES 0 /* disabled */
543#define L2_ITLB_4K_ASSOC 4
544#define L2_ITLB_4K_ENTRIES 512
545
e37a5c7f
CP		 546/* CPUID Leaf 0x14 constants: */
547#define INTEL_PT_MAX_SUBLEAF 0x1
548/*
549 * bit[00]: IA32_RTIT_CTL.CR3 filter can be set to 1 and IA32_RTIT_CR3_MATCH
550 * MSR can be accessed;
551 * bit[01]: Support Configurable PSB and Cycle-Accurate Mode;
552 * bit[02]: Support IP Filtering, TraceStop filtering, and preservation
553 * of Intel PT MSRs across warm reset;
554 * bit[03]: Support MTC timing packet and suppression of COFI-based packets;
555 */
556#define INTEL_PT_MINIMAL_EBX 0xf
557/*
558 * bit[00]: Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1 and
559 * IA32_RTIT_OUTPUT_BASE and IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be
560 * accessed;
561 * bit[01]: ToPA tables can hold any number of output entries, up to the
562 * maximum allowed by the MaskOrTableOffset field of
563 * IA32_RTIT_OUTPUT_MASK_PTRS;
564 * bit[02]: Support Single-Range Output scheme;
565 */
566#define INTEL_PT_MINIMAL_ECX 0x7
c078ca96
LK		 567/* generated packets which contain IP payloads have LIP values */
568#define INTEL_PT_IP_LIP (1 << 31)
e37a5c7f
CP		 569#define INTEL_PT_ADDR_RANGES_NUM 0x2 /* Number of configurable address ranges */
570#define INTEL_PT_ADDR_RANGES_NUM_MASK 0x3
571#define INTEL_PT_MTC_BITMAP (0x0249 << 16) /* Support ART(0,3,6,9) */
572#define INTEL_PT_CYCLE_BITMAP 0x1fff /* Support 0,2^(0~11) */
573#define INTEL_PT_PSB_BITMAP (0x003f << 16) /* Support 2K,4K,8K,16K,32K,64K */
5e891bf8 574
f5cc5a5c
CF		 575void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
576 uint32_t vendor2, uint32_t vendor3)
99b88a17
IM		 577{
578 int i;
579 for (i = 0; i < 4; i++) {
580 dst[i] = vendor1 >> (8 * i);
581 dst[i + 4] = vendor2 >> (8 * i);
582 dst[i + 8] = vendor3 >> (8 * i);
583 }
584 dst[CPUID_VENDOR_SZ] = '\0';
585}
586
621626ce
EH		 587#define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
588#define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
589 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
590#define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
591 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
592 CPUID_PSE36 | CPUID_FXSR)
593#define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
594#define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
595 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
596 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
597 CPUID_PAE | CPUID_SEP | CPUID_APIC)
598
599#define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
600 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
601 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
602 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
b6c5a6f0 603 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE)
621626ce
EH		 604 /* partly implemented:
605 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */
606 /* missing:
607 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
608#define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
609 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
610 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
19dc85db 611 CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \
369fd5ca
RH		 612 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR | \
613 CPUID_EXT_RDRAND)
621626ce
EH		 614 /* missing:
615 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
616 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
617 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
19dc85db 618 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_AVX,
369fd5ca 619 CPUID_EXT_F16C */
621626ce
EH		 620
621#ifdef TARGET_X86_64
622#define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM)
623#else
624#define TCG_EXT2_X86_64_FEATURES 0
625#endif
626
627#define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
628 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
629 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \
630 TCG_EXT2_X86_64_FEATURES)
631#define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
632 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
633#define TCG_EXT4_FEATURES 0
fe441054 634#define TCG_SVM_FEATURES CPUID_SVM_NPT
621626ce
EH		 635#define TCG_KVM_FEATURES 0
636#define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \
0c47242b
XG		 637 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \
638 CPUID_7_0_EBX_PCOMMIT | CPUID_7_0_EBX_CLFLUSHOPT | \
7eb24386
PB		 639 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \
640 CPUID_7_0_EBX_ERMS)
621626ce 641 /* missing:
07929f2a 642 CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
7eb24386 643 CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
621626ce 644 CPUID_7_0_EBX_RDSEED */
9ccb9784
EH		 645#define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_PKU | \
646 /* CPUID_7_0_ECX_OSPKE is dynamic */ \
e7e7bdab 647 CPUID_7_0_ECX_LA57 | CPUID_7_0_ECX_PKS)
95ea69fb 648#define TCG_7_0_EDX_FEATURES 0
80db491d 649#define TCG_7_1_EAX_FEATURES 0
303752a9 650#define TCG_APM_FEATURES 0
28b8e4d0 651#define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT
c9cfe8f9
RH		 652#define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1)
653 /* missing:
654 CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */
d1615ea5 655#define TCG_14_0_ECX_FEATURES 0
621626ce 656
79f1a68a 657FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
bffd67b0 658 [FEAT_1_EDX] = {
07585923 659 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 660 .feat_names = {
661 "fpu", "vme", "de", "pse",
662 "tsc", "msr", "pae", "mce",
663 "cx8", "apic", NULL, "sep",
664 "mtrr", "pge", "mca", "cmov",
665 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
666 NULL, "ds" /* Intel dts */, "acpi", "mmx",
667 "fxsr", "sse", "sse2", "ss",
668 "ht" /* Intel htt */, "tm", "ia64", "pbe",
669 },
07585923 670 .cpuid = {.eax = 1, .reg = R_EDX, },
37ce3522 671 .tcg_features = TCG_FEATURES,
bffd67b0
EH		 672 },
673 [FEAT_1_ECX] = {
07585923 674 .type = CPUID_FEATURE_WORD,
2d5312da 675 .feat_names = {
16d2fcaa 676 "pni" /* Intel,AMD sse3 */, "pclmulqdq", "dtes64", "monitor",
fc7dfd20 677 "ds-cpl", "vmx", "smx", "est",
2d5312da
EH		 678 "tm2", "ssse3", "cid", NULL,
679 "fma", "cx16", "xtpr", "pdcm",
16d2fcaa
EH		 680 NULL, "pcid", "dca", "sse4.1",
681 "sse4.2", "x2apic", "movbe", "popcnt",
f1a23522 682 "tsc-deadline", "aes", "xsave", NULL /* osxsave */,
2d5312da
EH		 683 "avx", "f16c", "rdrand", "hypervisor",
684 },
07585923 685 .cpuid = { .eax = 1, .reg = R_ECX, },
37ce3522 686 .tcg_features = TCG_EXT_FEATURES,
bffd67b0 687 },
2d5312da
EH		 688 /* Feature names that are already defined on feature_name[] but
689 * are set on CPUID[8000_0001].EDX on AMD CPUs don't have their
690 * names on feat_names below. They are copied automatically
691 * to features[FEAT_8000_0001_EDX] if and only if CPU vendor is AMD.
692 */
bffd67b0 693 [FEAT_8000_0001_EDX] = {
07585923 694 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 695 .feat_names = {
696 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
697 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
698 NULL /* cx8 */, NULL /* apic */, NULL, "syscall",
699 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
700 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
16d2fcaa
EH		 701 "nx", NULL, "mmxext", NULL /* mmx */,
702 NULL /* fxsr */, "fxsr-opt", "pdpe1gb", "rdtscp",
703 NULL, "lm", "3dnowext", "3dnow",
2d5312da 704 },
07585923 705 .cpuid = { .eax = 0x80000001, .reg = R_EDX, },
37ce3522 706 .tcg_features = TCG_EXT2_FEATURES,
bffd67b0
EH		 707 },
708 [FEAT_8000_0001_ECX] = {
07585923 709 .type = CPUID_FEATURE_WORD,
2d5312da 710 .feat_names = {
fc7dfd20 711 "lahf-lm", "cmp-legacy", "svm", "extapic",
2d5312da
EH		 712 "cr8legacy", "abm", "sse4a", "misalignsse",
713 "3dnowprefetch", "osvw", "ibs", "xop",
714 "skinit", "wdt", NULL, "lwp",
fc7dfd20
EH		 715 "fma4", "tce", NULL, "nodeid-msr",
716 NULL, "tbm", "topoext", "perfctr-core",
717 "perfctr-nb", NULL, NULL, NULL,
2d5312da
EH		 718 NULL, NULL, NULL, NULL,
719 },
07585923 720 .cpuid = { .eax = 0x80000001, .reg = R_ECX, },
37ce3522 721 .tcg_features = TCG_EXT3_FEATURES,
7210a02c
EH		 722 /*
723 * TOPOEXT is always allowed but can't be enabled blindly by
724 * "-cpu host", as it requires consistent cache topology info
725 * to be provided so it doesn't confuse guests.
726 */
727 .no_autoenable_flags = CPUID_EXT3_TOPOEXT,
bffd67b0 728 },
89e49c8b 729 [FEAT_C000_0001_EDX] = {
07585923 730 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 731 .feat_names = {
732 NULL, NULL, "xstore", "xstore-en",
733 NULL, NULL, "xcrypt", "xcrypt-en",
734 "ace2", "ace2-en", "phe", "phe-en",
735 "pmm", "pmm-en", NULL, NULL,
736 NULL, NULL, NULL, NULL,
737 NULL, NULL, NULL, NULL,
738 NULL, NULL, NULL, NULL,
739 NULL, NULL, NULL, NULL,
740 },
07585923 741 .cpuid = { .eax = 0xC0000001, .reg = R_EDX, },
37ce3522 742 .tcg_features = TCG_EXT4_FEATURES,
89e49c8b 743 },
bffd67b0 744 [FEAT_KVM] = {
07585923 745 .type = CPUID_FEATURE_WORD,
2d5312da 746 .feat_names = {
fc7dfd20
EH		 747 "kvmclock", "kvm-nopiodelay", "kvm-mmu", "kvmclock",
748 "kvm-asyncpf", "kvm-steal-time", "kvm-pv-eoi", "kvm-pv-unhalt",
7f710c32 749 NULL, "kvm-pv-tlb-flush", NULL, "kvm-pv-ipi",
c1bb5418 750 "kvm-poll-control", "kvm-pv-sched-yield", "kvm-asyncpf-int", "kvm-msi-ext-dest-id",
2d5312da
EH		 751 NULL, NULL, NULL, NULL,
752 NULL, NULL, NULL, NULL,
753 "kvmclock-stable-bit", NULL, NULL, NULL,
754 NULL, NULL, NULL, NULL,
755 },
07585923 756 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EAX, },
37ce3522 757 .tcg_features = TCG_KVM_FEATURES,
bffd67b0 758 },
be777326 759 [FEAT_KVM_HINTS] = {
07585923 760 .type = CPUID_FEATURE_WORD,
be777326
WL		 761 .feat_names = {
762 "kvm-hint-dedicated", NULL, NULL, NULL,
763 NULL, NULL, NULL, NULL,
764 NULL, NULL, NULL, NULL,
765 NULL, NULL, NULL, NULL,
766 NULL, NULL, NULL, NULL,
767 NULL, NULL, NULL, NULL,
768 NULL, NULL, NULL, NULL,
769 NULL, NULL, NULL, NULL,
770 },
07585923 771 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EDX, },
be777326 772 .tcg_features = TCG_KVM_FEATURES,
0d914f39
EH		 773 /*
774 * KVM hints aren't auto-enabled by -cpu host, they need to be
775 * explicitly enabled in the command-line.
776 */
777 .no_autoenable_flags = ~0U,
be777326 778 },
abd5fc4c
VK		 779 /*
780 * .feat_names are commented out for Hyper-V enlightenments because we
781 * don't want to have two different ways for enabling them on QEMU command
782 * line. Some features (e.g. "hyperv_time", "hyperv_vapic", ...) require
783 * enabling several feature bits simultaneously, exposing these bits
784 * individually may just confuse guests.
785 */
c35bd19a 786 [FEAT_HYPERV_EAX] = {
07585923 787 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 788 .feat_names = {
789 NULL /* hv_msr_vp_runtime_access */, NULL /* hv_msr_time_refcount_access */,
790 NULL /* hv_msr_synic_access */, NULL /* hv_msr_stimer_access */,
791 NULL /* hv_msr_apic_access */, NULL /* hv_msr_hypercall_access */,
792 NULL /* hv_vpindex_access */, NULL /* hv_msr_reset_access */,
793 NULL /* hv_msr_stats_access */, NULL /* hv_reftsc_access */,
794 NULL /* hv_msr_idle_access */, NULL /* hv_msr_frequency_access */,
ba6a4fd9
VK		 795 NULL /* hv_msr_debug_access */, NULL /* hv_msr_reenlightenment_access */,
796 NULL, NULL,
2d5312da
EH		 797 NULL, NULL, NULL, NULL,
798 NULL, NULL, NULL, NULL,
799 NULL, NULL, NULL, NULL,
800 NULL, NULL, NULL, NULL,
801 },
07585923 802 .cpuid = { .eax = 0x40000003, .reg = R_EAX, },
c35bd19a
EY		 803 },
804 [FEAT_HYPERV_EBX] = {
07585923 805 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 806 .feat_names = {
807 NULL /* hv_create_partitions */, NULL /* hv_access_partition_id */,
808 NULL /* hv_access_memory_pool */, NULL /* hv_adjust_message_buffers */,
809 NULL /* hv_post_messages */, NULL /* hv_signal_events */,
810 NULL /* hv_create_port */, NULL /* hv_connect_port */,
811 NULL /* hv_access_stats */, NULL, NULL, NULL /* hv_debugging */,
812 NULL /* hv_cpu_power_management */, NULL /* hv_configure_profiler */,
813 NULL, NULL,
814 NULL, NULL, NULL, NULL,
815 NULL, NULL, NULL, NULL,
816 NULL, NULL, NULL, NULL,
817 NULL, NULL, NULL, NULL,
818 },
07585923 819 .cpuid = { .eax = 0x40000003, .reg = R_EBX, },
c35bd19a
EY		 820 },
821 [FEAT_HYPERV_EDX] = {
07585923 822 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 823 .feat_names = {
824 NULL /* hv_mwait */, NULL /* hv_guest_debugging */,
825 NULL /* hv_perf_monitor */, NULL /* hv_cpu_dynamic_part */,
826 NULL /* hv_hypercall_params_xmm */, NULL /* hv_guest_idle_state */,
827 NULL, NULL,
828 NULL, NULL, NULL /* hv_guest_crash_msr */, NULL,
829 NULL, NULL, NULL, NULL,
830 NULL, NULL, NULL, NULL,
831 NULL, NULL, NULL, NULL,
832 NULL, NULL, NULL, NULL,
833 NULL, NULL, NULL, NULL,
834 },
07585923 835 .cpuid = { .eax = 0x40000003, .reg = R_EDX, },
c35bd19a 836 },
a2b107db
VK		 837 [FEAT_HV_RECOMM_EAX] = {
838 .type = CPUID_FEATURE_WORD,
839 .feat_names = {
840 NULL /* hv_recommend_pv_as_switch */,
841 NULL /* hv_recommend_pv_tlbflush_local */,
842 NULL /* hv_recommend_pv_tlbflush_remote */,
843 NULL /* hv_recommend_msr_apic_access */,
844 NULL /* hv_recommend_msr_reset */,
845 NULL /* hv_recommend_relaxed_timing */,
846 NULL /* hv_recommend_dma_remapping */,
847 NULL /* hv_recommend_int_remapping */,
848 NULL /* hv_recommend_x2apic_msrs */,
849 NULL /* hv_recommend_autoeoi_deprecation */,
850 NULL /* hv_recommend_pv_ipi */,
851 NULL /* hv_recommend_ex_hypercalls */,
852 NULL /* hv_hypervisor_is_nested */,
853 NULL /* hv_recommend_int_mbec */,
854 NULL /* hv_recommend_evmcs */,
855 NULL,
856 NULL, NULL, NULL, NULL,
857 NULL, NULL, NULL, NULL,
858 NULL, NULL, NULL, NULL,
859 NULL, NULL, NULL, NULL,
860 },
861 .cpuid = { .eax = 0x40000004, .reg = R_EAX, },
862 },
863 [FEAT_HV_NESTED_EAX] = {
864 .type = CPUID_FEATURE_WORD,
865 .cpuid = { .eax = 0x4000000A, .reg = R_EAX, },
866 },
bffd67b0 867 [FEAT_SVM] = {
07585923 868 .type = CPUID_FEATURE_WORD,
2d5312da 869 .feat_names = {
fc7dfd20
EH		 870 "npt", "lbrv", "svm-lock", "nrip-save",
871 "tsc-scale", "vmcb-clean", "flushbyasid", "decodeassists",
872 NULL, NULL, "pause-filter", NULL,
5447089c
WH		 873 "pfthreshold", "avic", NULL, "v-vmsave-vmload",
874 "vgif", NULL, NULL, NULL,
2d5312da
EH		 875 NULL, NULL, NULL, NULL,
876 NULL, NULL, NULL, NULL,
5447089c 877 "svme-addr-chk", NULL, NULL, NULL,
2d5312da 878 },
07585923 879 .cpuid = { .eax = 0x8000000A, .reg = R_EDX, },
37ce3522 880 .tcg_features = TCG_SVM_FEATURES,
bffd67b0
EH		 881 },
882 [FEAT_7_0_EBX] = {
07585923 883 .type = CPUID_FEATURE_WORD,
2d5312da 884 .feat_names = {
fc7dfd20 885 "fsgsbase", "tsc-adjust", NULL, "bmi1",
2d5312da
EH		 886 "hle", "avx2", NULL, "smep",
887 "bmi2", "erms", "invpcid", "rtm",
888 NULL, NULL, "mpx", NULL,
889 "avx512f", "avx512dq", "rdseed", "adx",
890 "smap", "avx512ifma", "pcommit", "clflushopt",
e37a5c7f 891 "clwb", "intel-pt", "avx512pf", "avx512er",
638cbd45 892 "avx512cd", "sha-ni", "avx512bw", "avx512vl",
2d5312da 893 },
07585923
RH		 894 .cpuid = {
895 .eax = 7,
896 .needs_ecx = true, .ecx = 0,
897 .reg = R_EBX,
898 },
37ce3522 899 .tcg_features = TCG_7_0_EBX_FEATURES,
bffd67b0 900 },
f74eefe0 901 [FEAT_7_0_ECX] = {
07585923 902 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 903 .feat_names = {
904 NULL, "avx512vbmi", "umip", "pku",
67192a29 905 NULL /* ospke */, "waitpkg", "avx512vbmi2", NULL,
aff9e6e4
YZ		 906 "gfni", "vaes", "vpclmulqdq", "avx512vnni",
907 "avx512bitalg", NULL, "avx512-vpopcntdq", NULL,
6c7c3c21 908 "la57", NULL, NULL, NULL,
2d5312da 909 NULL, NULL, "rdpid", NULL,
06e878b4 910 "bus-lock-detect", "cldemote", NULL, "movdiri",
e7e7bdab 911 "movdir64b", NULL, NULL, "pks",
2d5312da 912 },
07585923
RH		 913 .cpuid = {
914 .eax = 7,
915 .needs_ecx = true, .ecx = 0,
916 .reg = R_ECX,
917 },
f74eefe0
HH		 918 .tcg_features = TCG_7_0_ECX_FEATURES,
919 },
95ea69fb 920 [FEAT_7_0_EDX] = {
07585923 921 .type = CPUID_FEATURE_WORD,
95ea69fb
LK		 922 .feat_names = {
923 NULL, NULL, "avx512-4vnniw", "avx512-4fmaps",
5cb287d2 924 "fsrm", NULL, NULL, NULL,
353f98c9 925 "avx512-vp2intersect", NULL, "md-clear", NULL,
5dd13f2a 926 NULL, NULL, "serialize", NULL,
b3c7344e 927 "tsx-ldtrk", NULL, NULL /* pconfig */, NULL,
40399ecb 928 NULL, NULL, NULL, "avx512-fp16",
0e891658 929 NULL, NULL, "spec-ctrl", "stibp",
597360c0 930 NULL, "arch-capabilities", "core-capability", "ssbd",
95ea69fb 931 },
07585923
RH		 932 .cpuid = {
933 .eax = 7,
934 .needs_ecx = true, .ecx = 0,
935 .reg = R_EDX,
936 },
95ea69fb
LK		 937 .tcg_features = TCG_7_0_EDX_FEATURES,
938 },
80db491d
JL		 939 [FEAT_7_1_EAX] = {
940 .type = CPUID_FEATURE_WORD,
941 .feat_names = {
942 NULL, NULL, NULL, NULL,
c1826ea6 943 "avx-vnni", "avx512-bf16", NULL, NULL,
80db491d
JL		 944 NULL, NULL, NULL, NULL,
945 NULL, NULL, NULL, NULL,
946 NULL, NULL, NULL, NULL,
947 NULL, NULL, NULL, NULL,
948 NULL, NULL, NULL, NULL,
949 NULL, NULL, NULL, NULL,
950 },
951 .cpuid = {
952 .eax = 7,
953 .needs_ecx = true, .ecx = 1,
954 .reg = R_EAX,
955 },
956 .tcg_features = TCG_7_1_EAX_FEATURES,
957 },
303752a9 958 [FEAT_8000_0007_EDX] = {
07585923 959 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 960 .feat_names = {
961 NULL, NULL, NULL, NULL,
962 NULL, NULL, NULL, NULL,
963 "invtsc", NULL, NULL, NULL,
964 NULL, NULL, NULL, NULL,
965 NULL, NULL, NULL, NULL,
966 NULL, NULL, NULL, NULL,
967 NULL, NULL, NULL, NULL,
968 NULL, NULL, NULL, NULL,
969 },
07585923 970 .cpuid = { .eax = 0x80000007, .reg = R_EDX, },
303752a9
MT		 971 .tcg_features = TCG_APM_FEATURES,
972 .unmigratable_flags = CPUID_APM_INVTSC,
973 },
1b3420e1 974 [FEAT_8000_0008_EBX] = {
07585923 975 .type = CPUID_FEATURE_WORD,
1b3420e1 976 .feat_names = {
e900135d 977 "clzero", NULL, "xsaveerptr", NULL,
1b3420e1 978 NULL, NULL, NULL, NULL,
59a80a19 979 NULL, "wbnoinvd", NULL, NULL,
623972ce 980 "ibpb", NULL, "ibrs", "amd-stibp",
1b3420e1
EH		 981 NULL, NULL, NULL, NULL,
982 NULL, NULL, NULL, NULL,
254790a9 983 "amd-ssbd", "virt-ssbd", "amd-no-ssb", NULL,
1b3420e1
EH		 984 NULL, NULL, NULL, NULL,
985 },
07585923 986 .cpuid = { .eax = 0x80000008, .reg = R_EBX, },
1b3420e1
EH		 987 .tcg_features = 0,
988 .unmigratable_flags = 0,
989 },
0bb0b2d2 990 [FEAT_XSAVE] = {
07585923 991 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 992 .feat_names = {
993 "xsaveopt", "xsavec", "xgetbv1", "xsaves",
994 NULL, NULL, NULL, NULL,
995 NULL, NULL, NULL, NULL,
996 NULL, NULL, NULL, NULL,
997 NULL, NULL, NULL, NULL,
998 NULL, NULL, NULL, NULL,
999 NULL, NULL, NULL, NULL,
1000 NULL, NULL, NULL, NULL,
1001 },
07585923
RH		 1002 .cpuid = {
1003 .eax = 0xd,
1004 .needs_ecx = true, .ecx = 1,
1005 .reg = R_EAX,
1006 },
c9cfe8f9 1007 .tcg_features = TCG_XSAVE_FEATURES,
0bb0b2d2 1008 },
28b8e4d0 1009 [FEAT_6_EAX] = {
07585923 1010 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 1011 .feat_names = {
1012 NULL, NULL, "arat", NULL,
1013 NULL, NULL, NULL, NULL,
1014 NULL, NULL, NULL, NULL,
1015 NULL, NULL, NULL, NULL,
1016 NULL, NULL, NULL, NULL,
1017 NULL, NULL, NULL, NULL,
1018 NULL, NULL, NULL, NULL,
1019 NULL, NULL, NULL, NULL,
1020 },
07585923 1021 .cpuid = { .eax = 6, .reg = R_EAX, },
28b8e4d0
JK		 1022 .tcg_features = TCG_6_EAX_FEATURES,
1023 },
96193c22 1024 [FEAT_XSAVE_COMP_LO] = {
07585923
RH		 1025 .type = CPUID_FEATURE_WORD,
1026 .cpuid = {
1027 .eax = 0xD,
1028 .needs_ecx = true, .ecx = 0,
1029 .reg = R_EAX,
1030 },
96193c22 1031 .tcg_features = ~0U,
6fb2fff7
EH		 1032 .migratable_flags = XSTATE_FP_MASK | XSTATE_SSE_MASK |
1033 XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK |
1034 XSTATE_OPMASK_MASK | XSTATE_ZMM_Hi256_MASK | XSTATE_Hi16_ZMM_MASK |
1035 XSTATE_PKRU_MASK,
96193c22
EH		 1036 },
1037 [FEAT_XSAVE_COMP_HI] = {
07585923
RH		 1038 .type = CPUID_FEATURE_WORD,
1039 .cpuid = {
1040 .eax = 0xD,
1041 .needs_ecx = true, .ecx = 0,
1042 .reg = R_EDX,
1043 },
96193c22
EH		 1044 .tcg_features = ~0U,
1045 },
d86f9636
RH		 1046 /*Below are MSR exposed features*/
1047 [FEAT_ARCH_CAPABILITIES] = {
1048 .type = MSR_FEATURE_WORD,
1049 .feat_names = {
1050 "rdctl-no", "ibrs-all", "rsba", "skip-l1dfl-vmentry",
2a9758c5 1051 "ssb-no", "mds-no", "pschange-mc-no", "tsx-ctrl",
7fac3863 1052 "taa-no", NULL, NULL, NULL,
d86f9636
RH		 1053 NULL, NULL, NULL, NULL,
1054 NULL, NULL, NULL, NULL,
1055 NULL, NULL, NULL, NULL,
1056 NULL, NULL, NULL, NULL,
1057 NULL, NULL, NULL, NULL,
1058 },
1059 .msr = {
1060 .index = MSR_IA32_ARCH_CAPABILITIES,
d86f9636
RH		 1061 },
1062 },
597360c0
XL		 1063 [FEAT_CORE_CAPABILITY] = {
1064 .type = MSR_FEATURE_WORD,
1065 .feat_names = {
1066 NULL, NULL, NULL, NULL,
1067 NULL, "split-lock-detect", NULL, NULL,
1068 NULL, NULL, NULL, NULL,
1069 NULL, NULL, NULL, NULL,
1070 NULL, NULL, NULL, NULL,
1071 NULL, NULL, NULL, NULL,
1072 NULL, NULL, NULL, NULL,
1073 NULL, NULL, NULL, NULL,
1074 },
1075 .msr = {
1076 .index = MSR_IA32_CORE_CAPABILITY,
597360c0
XL		 1077 },
1078 },
ea39f9b6
LX		 1079 [FEAT_PERF_CAPABILITIES] = {
1080 .type = MSR_FEATURE_WORD,
1081 .feat_names = {
1082 NULL, NULL, NULL, NULL,
1083 NULL, NULL, NULL, NULL,
1084 NULL, NULL, NULL, NULL,
1085 NULL, "full-width-write", NULL, NULL,
1086 NULL, NULL, NULL, NULL,
1087 NULL, NULL, NULL, NULL,
1088 NULL, NULL, NULL, NULL,
1089 NULL, NULL, NULL, NULL,
1090 },
1091 .msr = {
1092 .index = MSR_IA32_PERF_CAPABILITIES,
1093 },
1094 },
20a78b02
PB		 1095
1096 [FEAT_VMX_PROCBASED_CTLS] = {
1097 .type = MSR_FEATURE_WORD,
1098 .feat_names = {
1099 NULL, NULL, "vmx-vintr-pending", "vmx-tsc-offset",
1100 NULL, NULL, NULL, "vmx-hlt-exit",
1101 NULL, "vmx-invlpg-exit", "vmx-mwait-exit", "vmx-rdpmc-exit",
1102 "vmx-rdtsc-exit", NULL, NULL, "vmx-cr3-load-noexit",
1103 "vmx-cr3-store-noexit", NULL, NULL, "vmx-cr8-load-exit",
1104 "vmx-cr8-store-exit", "vmx-flexpriority", "vmx-vnmi-pending", "vmx-movdr-exit",
1105 "vmx-io-exit", "vmx-io-bitmap", NULL, "vmx-mtf",
1106 "vmx-msr-bitmap", "vmx-monitor-exit", "vmx-pause-exit", "vmx-secondary-ctls",
1107 },
1108 .msr = {
1109 .index = MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1110 }
1111 },
1112
1113 [FEAT_VMX_SECONDARY_CTLS] = {
1114 .type = MSR_FEATURE_WORD,
1115 .feat_names = {
1116 "vmx-apicv-xapic", "vmx-ept", "vmx-desc-exit", "vmx-rdtscp-exit",
1117 "vmx-apicv-x2apic", "vmx-vpid", "vmx-wbinvd-exit", "vmx-unrestricted-guest",
1118 "vmx-apicv-register", "vmx-apicv-vid", "vmx-ple", "vmx-rdrand-exit",
1119 "vmx-invpcid-exit", "vmx-vmfunc", "vmx-shadow-vmcs", "vmx-encls-exit",
1120 "vmx-rdseed-exit", "vmx-pml", NULL, NULL,
1121 "vmx-xsaves", NULL, NULL, NULL,
1122 NULL, NULL, NULL, NULL,
1123 NULL, NULL, NULL, NULL,
1124 },
1125 .msr = {
1126 .index = MSR_IA32_VMX_PROCBASED_CTLS2,
1127 }
1128 },
1129
1130 [FEAT_VMX_PINBASED_CTLS] = {
1131 .type = MSR_FEATURE_WORD,
1132 .feat_names = {
1133 "vmx-intr-exit", NULL, NULL, "vmx-nmi-exit",
1134 NULL, "vmx-vnmi", "vmx-preemption-timer", "vmx-posted-intr",
1135 NULL, NULL, NULL, NULL,
1136 NULL, NULL, NULL, NULL,
1137 NULL, NULL, NULL, NULL,
1138 NULL, NULL, NULL, NULL,
1139 NULL, NULL, NULL, NULL,
1140 NULL, NULL, NULL, NULL,
1141 },
1142 .msr = {
1143 .index = MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1144 }
1145 },
1146
1147 [FEAT_VMX_EXIT_CTLS] = {
1148 .type = MSR_FEATURE_WORD,
1149 /*
1150 * VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE is copied from
1151 * the LM CPUID bit.
1152 */
1153 .feat_names = {
1154 NULL, NULL, "vmx-exit-nosave-debugctl", NULL,
1155 NULL, NULL, NULL, NULL,
1156 NULL, NULL /* vmx-exit-host-addr-space-size */, NULL, NULL,
1157 "vmx-exit-load-perf-global-ctrl", NULL, NULL, "vmx-exit-ack-intr",
1158 NULL, NULL, "vmx-exit-save-pat", "vmx-exit-load-pat",
1159 "vmx-exit-save-efer", "vmx-exit-load-efer",
1160 "vmx-exit-save-preemption-timer", "vmx-exit-clear-bndcfgs",
1161 NULL, "vmx-exit-clear-rtit-ctl", NULL, NULL,
52a44ad2 1162 NULL, "vmx-exit-load-pkrs", NULL, NULL,
20a78b02
PB		 1163 },
1164 .msr = {
1165 .index = MSR_IA32_VMX_TRUE_EXIT_CTLS,
1166 }
1167 },
1168
1169 [FEAT_VMX_ENTRY_CTLS] = {
1170 .type = MSR_FEATURE_WORD,
1171 .feat_names = {
1172 NULL, NULL, "vmx-entry-noload-debugctl", NULL,
1173 NULL, NULL, NULL, NULL,
1174 NULL, "vmx-entry-ia32e-mode", NULL, NULL,
1175 NULL, "vmx-entry-load-perf-global-ctrl", "vmx-entry-load-pat", "vmx-entry-load-efer",
1176 "vmx-entry-load-bndcfgs", NULL, "vmx-entry-load-rtit-ctl", NULL,
52a44ad2 1177 NULL, NULL, "vmx-entry-load-pkrs", NULL,
20a78b02
PB		 1178 NULL, NULL, NULL, NULL,
1179 NULL, NULL, NULL, NULL,
1180 },
1181 .msr = {
1182 .index = MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1183 }
1184 },
1185
1186 [FEAT_VMX_MISC] = {
1187 .type = MSR_FEATURE_WORD,
1188 .feat_names = {
1189 NULL, NULL, NULL, NULL,
1190 NULL, "vmx-store-lma", "vmx-activity-hlt", "vmx-activity-shutdown",
1191 "vmx-activity-wait-sipi", NULL, NULL, NULL,
1192 NULL, NULL, NULL, NULL,
1193 NULL, NULL, NULL, NULL,
1194 NULL, NULL, NULL, NULL,
1195 NULL, NULL, NULL, NULL,
1196 NULL, "vmx-vmwrite-vmexit-fields", "vmx-zero-len-inject", NULL,
1197 },
1198 .msr = {
1199 .index = MSR_IA32_VMX_MISC,
1200 }
1201 },
1202
1203 [FEAT_VMX_EPT_VPID_CAPS] = {
1204 .type = MSR_FEATURE_WORD,
1205 .feat_names = {
1206 "vmx-ept-execonly", NULL, NULL, NULL,
1207 NULL, NULL, "vmx-page-walk-4", "vmx-page-walk-5",
1208 NULL, NULL, NULL, NULL,
1209 NULL, NULL, NULL, NULL,
1210 "vmx-ept-2mb", "vmx-ept-1gb", NULL, NULL,
1211 "vmx-invept", "vmx-eptad", "vmx-ept-advanced-exitinfo", NULL,
1212 NULL, "vmx-invept-single-context", "vmx-invept-all-context", NULL,
1213 NULL, NULL, NULL, NULL,
1214 "vmx-invvpid", NULL, NULL, NULL,
1215 NULL, NULL, NULL, NULL,
1216 "vmx-invvpid-single-addr", "vmx-invept-single-context",
1217 "vmx-invvpid-all-context", "vmx-invept-single-context-noglobals",
1218 NULL, NULL, NULL, NULL,
1219 NULL, NULL, NULL, NULL,
1220 NULL, NULL, NULL, NULL,
1221 NULL, NULL, NULL, NULL,
1222 NULL, NULL, NULL, NULL,
1223 },
1224 .msr = {
1225 .index = MSR_IA32_VMX_EPT_VPID_CAP,
1226 }
1227 },
1228
1229 [FEAT_VMX_BASIC] = {
1230 .type = MSR_FEATURE_WORD,
1231 .feat_names = {
1232 [54] = "vmx-ins-outs",
1233 [55] = "vmx-true-ctls",
1234 },
1235 .msr = {
1236 .index = MSR_IA32_VMX_BASIC,
1237 },
1238 /* Just to be safe - we don't support setting the MSEG version field. */
1239 .no_autoenable_flags = MSR_VMX_BASIC_DUAL_MONITOR,
1240 },
1241
1242 [FEAT_VMX_VMFUNC] = {
1243 .type = MSR_FEATURE_WORD,
1244 .feat_names = {
1245 [0] = "vmx-eptp-switching",
1246 },
1247 .msr = {
1248 .index = MSR_IA32_VMX_VMFUNC,
1249 }
1250 },
1251
d1615ea5
LK		 1252 [FEAT_14_0_ECX] = {
1253 .type = CPUID_FEATURE_WORD,
1254 .feat_names = {
1255 NULL, NULL, NULL, NULL,
1256 NULL, NULL, NULL, NULL,
1257 NULL, NULL, NULL, NULL,
1258 NULL, NULL, NULL, NULL,
1259 NULL, NULL, NULL, NULL,
1260 NULL, NULL, NULL, NULL,
1261 NULL, NULL, NULL, NULL,
1262 NULL, NULL, NULL, "intel-pt-lip",
1263 },
1264 .cpuid = {
1265 .eax = 0x14,
1266 .needs_ecx = true, .ecx = 0,
1267 .reg = R_ECX,
1268 },
1269 .tcg_features = TCG_14_0_ECX_FEATURES,
1270 },
1271
5ef57876
EH		 1272};
1273
99e24dbd
PB		 1274typedef struct FeatureMask {
1275 FeatureWord index;
ede146c2 1276 uint64_t mask;
99e24dbd
PB		 1277} FeatureMask;
1278
1279typedef struct FeatureDep {
1280 FeatureMask from, to;
1281} FeatureDep;
1282
1283static FeatureDep feature_dependencies[] = {
1284 {
1285 .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_ARCH_CAPABILITIES },
ede146c2 1286 .to = { FEAT_ARCH_CAPABILITIES, ~0ull },
99e24dbd
PB		 1287 },
1288 {
1289 .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_CORE_CAPABILITY },
ede146c2 1290 .to = { FEAT_CORE_CAPABILITY, ~0ull },
99e24dbd 1291 },
ea39f9b6
LX		 1292 {
1293 .from = { FEAT_1_ECX, CPUID_EXT_PDCM },
1294 .to = { FEAT_PERF_CAPABILITIES, ~0ull },
1295 },
20a78b02
PB		 1296 {
1297 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1298 .to = { FEAT_VMX_PROCBASED_CTLS, ~0ull },
1299 },
1300 {
1301 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1302 .to = { FEAT_VMX_PINBASED_CTLS, ~0ull },
1303 },
1304 {
1305 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1306 .to = { FEAT_VMX_EXIT_CTLS, ~0ull },
1307 },
1308 {
1309 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1310 .to = { FEAT_VMX_ENTRY_CTLS, ~0ull },
1311 },
1312 {
1313 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1314 .to = { FEAT_VMX_MISC, ~0ull },
1315 },
1316 {
1317 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1318 .to = { FEAT_VMX_BASIC, ~0ull },
1319 },
1320 {
1321 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_LM },
1322 .to = { FEAT_VMX_ENTRY_CTLS, VMX_VM_ENTRY_IA32E_MODE },
1323 },
1324 {
1325 .from = { FEAT_VMX_PROCBASED_CTLS, VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS },
1326 .to = { FEAT_VMX_SECONDARY_CTLS, ~0ull },
1327 },
1328 {
1329 .from = { FEAT_XSAVE, CPUID_XSAVE_XSAVES },
1330 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_XSAVES },
1331 },
1332 {
1333 .from = { FEAT_1_ECX, CPUID_EXT_RDRAND },
1334 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDRAND_EXITING },
1335 },
1336 {
1337 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_INVPCID },
1338 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_INVPCID },
1339 },
1340 {
1341 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_RDSEED },
1342 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDSEED_EXITING },
1343 },
d1615ea5
LK		 1344 {
1345 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT },
1346 .to = { FEAT_14_0_ECX, ~0ull },
1347 },
20a78b02
PB		 1348 {
1349 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_RDTSCP },
1350 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDTSCP },
1351 },
1352 {
1353 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_EPT },
1354 .to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull },
1355 },
1356 {
1357 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_EPT },
1358 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST },
1359 },
1360 {
1361 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_VPID },
1362 .to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull << 32 },
1363 },
1364 {
1365 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_VMFUNC },
1366 .to = { FEAT_VMX_VMFUNC, ~0ull },
1367 },
730319ae
EH		 1368 {
1369 .from = { FEAT_8000_0001_ECX, CPUID_EXT3_SVM },
1370 .to = { FEAT_SVM, ~0ull },
1371 },
99e24dbd
PB		 1372};
1373
8e8aba50
EH		 1374typedef struct X86RegisterInfo32 {
1375 /* Name of register */
1376 const char *name;
1377 /* QAPI enum value register */
1378 X86CPURegister32 qapi_enum;
1379} X86RegisterInfo32;
1380
1381#define REGISTER(reg) \
5d371f41 1382 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
a443bc34 1383static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
8e8aba50
EH		 1384 REGISTER(EAX),
1385 REGISTER(ECX),
1386 REGISTER(EDX),
1387 REGISTER(EBX),
1388 REGISTER(ESP),
1389 REGISTER(EBP),
1390 REGISTER(ESI),
1391 REGISTER(EDI),
1392};
1393#undef REGISTER
1394
3f32bd21
RH		 1395typedef struct ExtSaveArea {
1396 uint32_t feature, bits;
1397 uint32_t offset, size;
1398} ExtSaveArea;
1399
1400static const ExtSaveArea x86_ext_save_areas[] = {
e3c9022b
EH		 1401 [XSTATE_FP_BIT] = {
1402 /* x87 FP state component is always enabled if XSAVE is supported */
1403 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE,
1404 /* x87 state is in the legacy region of the XSAVE area */
1405 .offset = 0,
1406 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader),
1407 },
1408 [XSTATE_SSE_BIT] = {
1409 /* SSE state component is always enabled if XSAVE is supported */
1410 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE,
1411 /* SSE state is in the legacy region of the XSAVE area */
1412 .offset = 0,
1413 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader),
1414 },
cfc3b074
PB		 1415 [XSTATE_YMM_BIT] =
1416 { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
ee1b09f6
EH		 1417 .offset = offsetof(X86XSaveArea, avx_state),
1418 .size = sizeof(XSaveAVX) },
cfc3b074
PB		 1419 [XSTATE_BNDREGS_BIT] =
1420 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
ee1b09f6
EH		 1421 .offset = offsetof(X86XSaveArea, bndreg_state),
1422 .size = sizeof(XSaveBNDREG) },
cfc3b074
PB		 1423 [XSTATE_BNDCSR_BIT] =
1424 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
ee1b09f6
EH		 1425 .offset = offsetof(X86XSaveArea, bndcsr_state),
1426 .size = sizeof(XSaveBNDCSR) },
cfc3b074
PB		 1427 [XSTATE_OPMASK_BIT] =
1428 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6
EH		 1429 .offset = offsetof(X86XSaveArea, opmask_state),
1430 .size = sizeof(XSaveOpmask) },
cfc3b074
PB		 1431 [XSTATE_ZMM_Hi256_BIT] =
1432 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6
EH		 1433 .offset = offsetof(X86XSaveArea, zmm_hi256_state),
1434 .size = sizeof(XSaveZMM_Hi256) },
cfc3b074
PB		 1435 [XSTATE_Hi16_ZMM_BIT] =
1436 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6
EH		 1437 .offset = offsetof(X86XSaveArea, hi16_zmm_state),
1438 .size = sizeof(XSaveHi16_ZMM) },
cfc3b074
PB		 1439 [XSTATE_PKRU_BIT] =
1440 { .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU,
ee1b09f6
EH		 1441 .offset = offsetof(X86XSaveArea, pkru_state),
1442 .size = sizeof(XSavePKRU) },
2560f19f 1443};
8e8aba50 1444
1fda6198
EH		 1445static uint32_t xsave_area_size(uint64_t mask)
1446{
1447 int i;
e3c9022b 1448 uint64_t ret = 0;
1fda6198 1449
e3c9022b 1450 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
1fda6198
EH		 1451 const ExtSaveArea *esa = &x86_ext_save_areas[i];
1452 if ((mask >> i) & 1) {
1453 ret = MAX(ret, esa->offset + esa->size);
1454 }
1455 }
1456 return ret;
1457}
1458
d6dcc558
SAGDR		 1459static inline bool accel_uses_host_cpuid(void)
1460{
1461 return kvm_enabled() || hvf_enabled();
1462}
1463
96193c22
EH		 1464static inline uint64_t x86_cpu_xsave_components(X86CPU *cpu)
1465{
1466 return ((uint64_t)cpu->env.features[FEAT_XSAVE_COMP_HI]) << 32 |
1467 cpu->env.features[FEAT_XSAVE_COMP_LO];
1468}
1469
ed69e831
CF		 1470/* Return name of 32-bit register, from a R_* constant */
1471static const char *get_register_name_32(unsigned int reg)
8b4beddc 1472{
31ccdde2 1473 if (reg >= CPU_NB_REGS32) {
8b4beddc
EH		 1474 return NULL;
1475 }
8e8aba50 1476 return x86_reg_info_32[reg].name;
8b4beddc
EH		 1477}
1478
84f1b92f
EH		 1479/*
1480 * Returns the set of feature flags that are supported and migratable by
1481 * QEMU, for a given FeatureWord.
1482 */
ede146c2 1483static uint64_t x86_cpu_get_migratable_flags(FeatureWord w)
84f1b92f
EH		 1484{
1485 FeatureWordInfo *wi = &feature_word_info[w];
ede146c2 1486 uint64_t r = 0;
84f1b92f
EH		 1487 int i;
1488
ede146c2
PB		 1489 for (i = 0; i < 64; i++) {
1490 uint64_t f = 1ULL << i;
6fb2fff7
EH		 1491
1492 /* If the feature name is known, it is implicitly considered migratable,
1493 * unless it is explicitly set in unmigratable_flags */
1494 if ((wi->migratable_flags & f) ||
1495 (wi->feat_names[i] && !(wi->unmigratable_flags & f))) {
1496 r |= f;
84f1b92f 1497 }
84f1b92f
EH		 1498 }
1499 return r;
1500}
1501
bb44e0d1
JK		 1502void host_cpuid(uint32_t function, uint32_t count,
1503 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
bdde476a 1504{
a1fd24af
AL		 1505 uint32_t vec[4];
1506
1507#ifdef __x86_64__
1508 asm volatile("cpuid"
1509 : "=a"(vec[0]), "=b"(vec[1]),
1510 "=c"(vec[2]), "=d"(vec[3])
1511 : "0"(function), "c"(count) : "cc");
c1f41226 1512#elif defined(__i386__)
a1fd24af
AL		 1513 asm volatile("pusha \n\t"
1514 "cpuid \n\t"
1515 "mov %%eax, 0(%2) \n\t"
1516 "mov %%ebx, 4(%2) \n\t"
1517 "mov %%ecx, 8(%2) \n\t"
1518 "mov %%edx, 12(%2) \n\t"
1519 "popa"
1520 : : "a"(function), "c"(count), "S"(vec)
1521 : "memory", "cc");
c1f41226
EH		 1522#else
1523 abort();
a1fd24af
AL		 1524#endif
1525
bdde476a 1526 if (eax)
a1fd24af 1527 *eax = vec[0];
bdde476a 1528 if (ebx)
a1fd24af 1529 *ebx = vec[1];
bdde476a 1530 if (ecx)
a1fd24af 1531 *ecx = vec[2];
bdde476a 1532 if (edx)
a1fd24af 1533 *edx = vec[3];
bdde476a 1534}
c6dc6f63 1535
d940ee9b
EH		 1536/* CPU class name definitions: */
1537
d940ee9b
EH		 1538/* Return type name for a given CPU model name
1539 * Caller is responsible for freeing the returned string.
1540 */
1541static char *x86_cpu_type_name(const char *model_name)
1542{
1543 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name);
1544}
1545
500050d1
AF		 1546static ObjectClass *x86_cpu_class_by_name(const char *cpu_model)
1547{
88703ce2
EH		 1548 g_autofree char *typename = x86_cpu_type_name(cpu_model);
1549 return object_class_by_name(typename);
500050d1
AF		 1550}
1551
104494ea
IM		 1552static char *x86_cpu_class_get_model_name(X86CPUClass *cc)
1553{
1554 const char *class_name = object_class_get_name(OBJECT_CLASS(cc));
1555 assert(g_str_has_suffix(class_name, X86_CPU_TYPE_SUFFIX));
1556 return g_strndup(class_name,
1557 strlen(class_name) - strlen(X86_CPU_TYPE_SUFFIX));
1558}
1559
dcafd1ef
EH		 1560typedef struct X86CPUVersionDefinition {
1561 X86CPUVersion version;
53db89d9 1562 const char *alias;
c63938df 1563 const char *note;
dcafd1ef
EH		 1564 PropValue *props;
1565} X86CPUVersionDefinition;
1566
1567/* Base definition for a CPU model */
1568typedef struct X86CPUDefinition {
c6dc6f63
AP		 1569 const char *name;
1570 uint32_t level;
90e4b0c3 1571 uint32_t xlevel;
99b88a17
IM		 1572 /* vendor is zero-terminated, 12 character ASCII string */
1573 char vendor[CPUID_VENDOR_SZ + 1];
c6dc6f63
AP		 1574 int family;
1575 int model;
1576 int stepping;
0514ef2f 1577 FeatureWordArray features;
807e9869 1578 const char *model_id;
6aaeb054 1579 CPUCaches *cache_info;
dcafd1ef
EH		 1580 /*
1581 * Definitions for alternative versions of CPU model.
1582 * List is terminated by item with version == 0.
1583 * If NULL, version 1 will be registered automatically.
1584 */
1585 const X86CPUVersionDefinition *versions;
61ad65d0 1586 const char *deprecation_note;
dcafd1ef
EH		 1587} X86CPUDefinition;
1588
1589/* Reference to a specific CPU model version */
1590struct X86CPUModel {
1591 /* Base CPU definition */
1592 X86CPUDefinition *cpudef;
1593 /* CPU model version */
1594 X86CPUVersion version;
c63938df 1595 const char *note;
0788a56b
EH		 1596 /*
1597 * If true, this is an alias CPU model.
1598 * This matters only for "-cpu help" and query-cpu-definitions
1599 */
1600 bool is_alias;
d940ee9b 1601};
c6dc6f63 1602
dcafd1ef
EH		 1603/* Get full model name for CPU version */
1604static char *x86_cpu_versioned_model_name(X86CPUDefinition *cpudef,
1605 X86CPUVersion version)
1606{
1607 assert(version > 0);
1608 return g_strdup_printf("%s-v%d", cpudef->name, (int)version);
1609}
1610
1611static const X86CPUVersionDefinition *x86_cpu_def_get_versions(X86CPUDefinition *def)
1612{
1613 /* When X86CPUDefinition::versions is NULL, we register only v1 */
1614 static const X86CPUVersionDefinition default_version_list[] = {
1615 { 1 },
1616 { /* end of list */ }
1617 };
1618
1619 return def->versions ?: default_version_list;
1620}
1621
fe52acd2 1622static CPUCaches epyc_cache_info = {
a9f27ea9 1623 .l1d_cache = &(CPUCacheInfo) {
5f00335a 1624 .type = DATA_CACHE,
fe52acd2
BM		 1625 .level = 1,
1626 .size = 32 * KiB,
1627 .line_size = 64,
1628 .associativity = 8,
1629 .partitions = 1,
1630 .sets = 64,
1631 .lines_per_tag = 1,
1632 .self_init = 1,
1633 .no_invd_sharing = true,
1634 },
a9f27ea9 1635 .l1i_cache = &(CPUCacheInfo) {
5f00335a 1636 .type = INSTRUCTION_CACHE,
fe52acd2
BM		 1637 .level = 1,
1638 .size = 64 * KiB,
1639 .line_size = 64,
1640 .associativity = 4,
1641 .partitions = 1,
1642 .sets = 256,
1643 .lines_per_tag = 1,
1644 .self_init = 1,
1645 .no_invd_sharing = true,
1646 },
a9f27ea9 1647 .l2_cache = &(CPUCacheInfo) {
fe52acd2
BM		 1648 .type = UNIFIED_CACHE,
1649 .level = 2,
1650 .size = 512 * KiB,
1651 .line_size = 64,
1652 .associativity = 8,
1653 .partitions = 1,
1654 .sets = 1024,
1655 .lines_per_tag = 1,
1656 },
a9f27ea9 1657 .l3_cache = &(CPUCacheInfo) {
fe52acd2
BM		 1658 .type = UNIFIED_CACHE,
1659 .level = 3,
1660 .size = 8 * MiB,
1661 .line_size = 64,
1662 .associativity = 16,
1663 .partitions = 1,
1664 .sets = 8192,
1665 .lines_per_tag = 1,
1666 .self_init = true,
1667 .inclusive = true,
1668 .complex_indexing = true,
1669 },
1670};
1671
143c30d4
MB		 1672static CPUCaches epyc_rome_cache_info = {
1673 .l1d_cache = &(CPUCacheInfo) {
1674 .type = DATA_CACHE,
1675 .level = 1,
1676 .size = 32 * KiB,
1677 .line_size = 64,
1678 .associativity = 8,
1679 .partitions = 1,
1680 .sets = 64,
1681 .lines_per_tag = 1,
1682 .self_init = 1,
1683 .no_invd_sharing = true,
1684 },
1685 .l1i_cache = &(CPUCacheInfo) {
1686 .type = INSTRUCTION_CACHE,
1687 .level = 1,
1688 .size = 32 * KiB,
1689 .line_size = 64,
1690 .associativity = 8,
1691 .partitions = 1,
1692 .sets = 64,
1693 .lines_per_tag = 1,
1694 .self_init = 1,
1695 .no_invd_sharing = true,
1696 },
1697 .l2_cache = &(CPUCacheInfo) {
1698 .type = UNIFIED_CACHE,
1699 .level = 2,
1700 .size = 512 * KiB,
1701 .line_size = 64,
1702 .associativity = 8,
1703 .partitions = 1,
1704 .sets = 1024,
1705 .lines_per_tag = 1,
1706 },
1707 .l3_cache = &(CPUCacheInfo) {
1708 .type = UNIFIED_CACHE,
1709 .level = 3,
1710 .size = 16 * MiB,
1711 .line_size = 64,
1712 .associativity = 16,
1713 .partitions = 1,
1714 .sets = 16384,
1715 .lines_per_tag = 1,
1716 .self_init = true,
1717 .inclusive = true,
1718 .complex_indexing = true,
1719 },
1720};
1721
623972ce
BM		 1722static CPUCaches epyc_milan_cache_info = {
1723 .l1d_cache = &(CPUCacheInfo) {
1724 .type = DATA_CACHE,
1725 .level = 1,
1726 .size = 32 * KiB,
1727 .line_size = 64,
1728 .associativity = 8,
1729 .partitions = 1,
1730 .sets = 64,
1731 .lines_per_tag = 1,
1732 .self_init = 1,
1733 .no_invd_sharing = true,
1734 },
1735 .l1i_cache = &(CPUCacheInfo) {
1736 .type = INSTRUCTION_CACHE,
1737 .level = 1,
1738 .size = 32 * KiB,
1739 .line_size = 64,
1740 .associativity = 8,
1741 .partitions = 1,
1742 .sets = 64,
1743 .lines_per_tag = 1,
1744 .self_init = 1,
1745 .no_invd_sharing = true,
1746 },
1747 .l2_cache = &(CPUCacheInfo) {
1748 .type = UNIFIED_CACHE,
1749 .level = 2,
1750 .size = 512 * KiB,
1751 .line_size = 64,
1752 .associativity = 8,
1753 .partitions = 1,
1754 .sets = 1024,
1755 .lines_per_tag = 1,
1756 },
1757 .l3_cache = &(CPUCacheInfo) {
1758 .type = UNIFIED_CACHE,
1759 .level = 3,
1760 .size = 32 * MiB,
1761 .line_size = 64,
1762 .associativity = 16,
1763 .partitions = 1,
1764 .sets = 32768,
1765 .lines_per_tag = 1,
1766 .self_init = true,
1767 .inclusive = true,
1768 .complex_indexing = true,
1769 },
1770};
1771
0723cc8a
PB		 1772/* The following VMX features are not supported by KVM and are left out in the
1773 * CPU definitions:
1774 *
1775 * Dual-monitor support (all processors)
1776 * Entry to SMM
1777 * Deactivate dual-monitor treatment
1778 * Number of CR3-target values
1779 * Shutdown activity state
1780 * Wait-for-SIPI activity state
1781 * PAUSE-loop exiting (Westmere and newer)
1782 * EPT-violation #VE (Broadwell and newer)
1783 * Inject event with insn length=0 (Skylake and newer)
1784 * Conceal non-root operation from PT
1785 * Conceal VM exits from PT
1786 * Conceal VM entries from PT
1787 * Enable ENCLS exiting
1788 * Mode-based execute control (XS/XU)
1789 s TSC scaling (Skylake Server and newer)
1790 * GPA translation for PT (IceLake and newer)
1791 * User wait and pause
1792 * ENCLV exiting
1793 * Load IA32_RTIT_CTL
1794 * Clear IA32_RTIT_CTL
1795 * Advanced VM-exit information for EPT violations
1796 * Sub-page write permissions
1797 * PT in VMX operation
1798 */
1799
9576de75 1800static X86CPUDefinition builtin_x86_defs[] = {
c6dc6f63
AP		 1801 {
1802 .name = "qemu64",
3046bb5d 1803 .level = 0xd,
99b88a17 1804 .vendor = CPUID_VENDOR_AMD,
c6dc6f63 1805 .family = 6,
f8e6a11a 1806 .model = 6,
c6dc6f63 1807 .stepping = 3,
0514ef2f 1808 .features[FEAT_1_EDX] =
27861ecc 1809 PPRO_FEATURES |
c6dc6f63 1810 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
c6dc6f63 1811 CPUID_PSE36,
0514ef2f 1812 .features[FEAT_1_ECX] =
6aa91e4a 1813 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
0514ef2f 1814 .features[FEAT_8000_0001_EDX] =
c6dc6f63 1815 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 1816 .features[FEAT_8000_0001_ECX] =
71195672 1817 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM,
c6dc6f63 1818 .xlevel = 0x8000000A,
9cf2cc3d 1819 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63
AP		 1820 },
1821 {
1822 .name = "phenom",
1823 .level = 5,
99b88a17 1824 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 1825 .family = 16,
1826 .model = 2,
1827 .stepping = 3,
b9fc20bc 1828 /* Missing: CPUID_HT */
0514ef2f 1829 .features[FEAT_1_EDX] =
27861ecc 1830 PPRO_FEATURES |
c6dc6f63 1831 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
b9fc20bc 1832 CPUID_PSE36 | CPUID_VME,
0514ef2f 1833 .features[FEAT_1_ECX] =
27861ecc 1834 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
c6dc6f63 1835 CPUID_EXT_POPCNT,
0514ef2f 1836 .features[FEAT_8000_0001_EDX] =
c6dc6f63
AP		 1837 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
1838 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
8560efed 1839 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
c6dc6f63
AP		 1840 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
1841 CPUID_EXT3_CR8LEG,
1842 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
1843 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
0514ef2f 1844 .features[FEAT_8000_0001_ECX] =
27861ecc 1845 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
c6dc6f63 1846 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
b9fc20bc 1847 /* Missing: CPUID_SVM_LBRV */
0514ef2f 1848 .features[FEAT_SVM] =
b9fc20bc 1849 CPUID_SVM_NPT,
c6dc6f63
AP		 1850 .xlevel = 0x8000001A,
1851 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
1852 },
1853 {
1854 .name = "core2duo",
1855 .level = 10,
99b88a17 1856 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 1857 .family = 6,
1858 .model = 15,
1859 .stepping = 11,
b9fc20bc 1860 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 1861 .features[FEAT_1_EDX] =
27861ecc 1862 PPRO_FEATURES |
c6dc6f63 1863 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
b9fc20bc
EH		 1864 CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS,
1865 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST,
e93abc14 1866 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */
0514ef2f 1867 .features[FEAT_1_ECX] =
27861ecc 1868 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
e93abc14 1869 CPUID_EXT_CX16,
0514ef2f 1870 .features[FEAT_8000_0001_EDX] =
27861ecc 1871 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 1872 .features[FEAT_8000_0001_ECX] =
27861ecc 1873 CPUID_EXT3_LAHF_LM,
0723cc8a
PB		 1874 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS,
1875 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
1876 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
1877 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
1878 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
1879 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS,
1880 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
1881 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
1882 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
1883 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
1884 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
1885 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
1886 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
1887 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
1888 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
1889 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
1890 .features[FEAT_VMX_SECONDARY_CTLS] =
1891 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES,
c6dc6f63
AP		 1892 .xlevel = 0x80000008,
1893 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
1894 },
1895 {
1896 .name = "kvm64",
3046bb5d 1897 .level = 0xd,
99b88a17 1898 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 1899 .family = 15,
1900 .model = 6,
1901 .stepping = 1,
b3a4f0b1 1902 /* Missing: CPUID_HT */
0514ef2f 1903 .features[FEAT_1_EDX] =
b3a4f0b1 1904 PPRO_FEATURES | CPUID_VME |
c6dc6f63
AP		 1905 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
1906 CPUID_PSE36,
1907 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
0514ef2f 1908 .features[FEAT_1_ECX] =
27861ecc 1909 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
c6dc6f63 1910 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
0514ef2f 1911 .features[FEAT_8000_0001_EDX] =
c6dc6f63
AP		 1912 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1913 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
1914 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
1915 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
1916 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
0514ef2f 1917 .features[FEAT_8000_0001_ECX] =
27861ecc 1918 0,
0723cc8a
PB		 1919 /* VMX features from Cedar Mill/Prescott */
1920 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
1921 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
1922 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
1923 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
1924 VMX_PIN_BASED_NMI_EXITING,
1925 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
1926 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
1927 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
1928 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
1929 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
1930 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
1931 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
1932 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING,
c6dc6f63
AP		 1933 .xlevel = 0x80000008,
1934 .model_id = "Common KVM processor"
1935 },
c6dc6f63
AP		 1936 {
1937 .name = "qemu32",
1938 .level = 4,
99b88a17 1939 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 1940 .family = 6,
f8e6a11a 1941 .model = 6,
c6dc6f63 1942 .stepping = 3,
0514ef2f 1943 .features[FEAT_1_EDX] =
27861ecc 1944 PPRO_FEATURES,
0514ef2f 1945 .features[FEAT_1_ECX] =
6aa91e4a 1946 CPUID_EXT_SSE3,
58012d66 1947 .xlevel = 0x80000004,
9cf2cc3d 1948 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63 1949 },
eafaf1e5
AP		 1950 {
1951 .name = "kvm32",
1952 .level = 5,
99b88a17 1953 .vendor = CPUID_VENDOR_INTEL,
eafaf1e5
AP		 1954 .family = 15,
1955 .model = 6,
1956 .stepping = 1,
0514ef2f 1957 .features[FEAT_1_EDX] =
b3a4f0b1 1958 PPRO_FEATURES | CPUID_VME |
eafaf1e5 1959 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
0514ef2f 1960 .features[FEAT_1_ECX] =
27861ecc 1961 CPUID_EXT_SSE3,
0514ef2f 1962 .features[FEAT_8000_0001_ECX] =
27861ecc 1963 0,
0723cc8a
PB		 1964 /* VMX features from Yonah */
1965 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
1966 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
1967 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
1968 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
1969 VMX_PIN_BASED_NMI_EXITING,
1970 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
1971 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
1972 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
1973 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
1974 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING |
1975 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING |
1976 VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS,
eafaf1e5
AP		 1977 .xlevel = 0x80000008,
1978 .model_id = "Common 32-bit KVM processor"
1979 },
c6dc6f63
AP		 1980 {
1981 .name = "coreduo",
1982 .level = 10,
99b88a17 1983 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 1984 .family = 6,
1985 .model = 14,
1986 .stepping = 8,
b9fc20bc 1987 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 1988 .features[FEAT_1_EDX] =
27861ecc 1989 PPRO_FEATURES | CPUID_VME |
b9fc20bc
EH		 1990 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI |
1991 CPUID_SS,
1992 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR,
e93abc14 1993 * CPUID_EXT_PDCM, CPUID_EXT_VMX */
0514ef2f 1994 .features[FEAT_1_ECX] =
e93abc14 1995 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR,
0514ef2f 1996 .features[FEAT_8000_0001_EDX] =
27861ecc 1997 CPUID_EXT2_NX,
0723cc8a
PB		 1998 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
1999 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
2000 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
2001 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2002 VMX_PIN_BASED_NMI_EXITING,
2003 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2004 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2005 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2006 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2007 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING |
2008 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING |
2009 VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS,
c6dc6f63
AP		 2010 .xlevel = 0x80000008,
2011 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
2012 },
2013 {
2014 .name = "486",
58012d66 2015 .level = 1,
99b88a17 2016 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 2017 .family = 4,
b2a856d9 2018 .model = 8,
c6dc6f63 2019 .stepping = 0,
0514ef2f 2020 .features[FEAT_1_EDX] =
27861ecc 2021 I486_FEATURES,
c6dc6f63 2022 .xlevel = 0,
807e9869 2023 .model_id = "",
c6dc6f63
AP		 2024 },
2025 {
2026 .name = "pentium",
2027 .level = 1,
99b88a17 2028 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 2029 .family = 5,
2030 .model = 4,
2031 .stepping = 3,
0514ef2f 2032 .features[FEAT_1_EDX] =
27861ecc 2033 PENTIUM_FEATURES,
c6dc6f63 2034 .xlevel = 0,
807e9869 2035 .model_id = "",
c6dc6f63
AP		 2036 },
2037 {
2038 .name = "pentium2",
2039 .level = 2,
99b88a17 2040 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 2041 .family = 6,
2042 .model = 5,
2043 .stepping = 2,
0514ef2f 2044 .features[FEAT_1_EDX] =
27861ecc 2045 PENTIUM2_FEATURES,
c6dc6f63 2046 .xlevel = 0,
807e9869 2047 .model_id = "",
c6dc6f63
AP		 2048 },
2049 {
2050 .name = "pentium3",
3046bb5d 2051 .level = 3,
99b88a17 2052 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 2053 .family = 6,
2054 .model = 7,
2055 .stepping = 3,
0514ef2f 2056 .features[FEAT_1_EDX] =
27861ecc 2057 PENTIUM3_FEATURES,
c6dc6f63 2058 .xlevel = 0,
807e9869 2059 .model_id = "",
c6dc6f63
AP		 2060 },
2061 {
2062 .name = "athlon",
2063 .level = 2,
99b88a17 2064 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 2065 .family = 6,
2066 .model = 2,
2067 .stepping = 3,
0514ef2f 2068 .features[FEAT_1_EDX] =
27861ecc 2069 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
60032ac0 2070 CPUID_MCA,
0514ef2f 2071 .features[FEAT_8000_0001_EDX] =
60032ac0 2072 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
c6dc6f63 2073 .xlevel = 0x80000008,
9cf2cc3d 2074 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63
AP		 2075 },
2076 {
2077 .name = "n270",
3046bb5d 2078 .level = 10,
99b88a17 2079 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 2080 .family = 6,
2081 .model = 28,
2082 .stepping = 2,
b9fc20bc 2083 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 2084 .features[FEAT_1_EDX] =
27861ecc 2085 PPRO_FEATURES |
b9fc20bc
EH		 2086 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME |
2087 CPUID_ACPI | CPUID_SS,
c6dc6f63 2088 /* Some CPUs got no CPUID_SEP */
b9fc20bc
EH		 2089 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2,
2090 * CPUID_EXT_XTPR */
0514ef2f 2091 .features[FEAT_1_ECX] =
27861ecc 2092 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
4458c236 2093 CPUID_EXT_MOVBE,
0514ef2f 2094 .features[FEAT_8000_0001_EDX] =
60032ac0 2095 CPUID_EXT2_NX,
0514ef2f 2096 .features[FEAT_8000_0001_ECX] =
27861ecc 2097 CPUID_EXT3_LAHF_LM,
3046bb5d 2098 .xlevel = 0x80000008,
c6dc6f63
AP		 2099 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
2100 },
3eca4642
EH		 2101 {
2102 .name = "Conroe",
3046bb5d 2103 .level = 10,
99b88a17 2104 .vendor = CPUID_VENDOR_INTEL,
3eca4642 2105 .family = 6,
ffce9ebb 2106 .model = 15,
3eca4642 2107 .stepping = 3,
0514ef2f 2108 .features[FEAT_1_EDX] =
b3a4f0b1 2109 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2110 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2111 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2112 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2113 CPUID_DE | CPUID_FP87,
0514ef2f 2114 .features[FEAT_1_ECX] =
27861ecc 2115 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 2116 .features[FEAT_8000_0001_EDX] =
27861ecc 2117 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 2118 .features[FEAT_8000_0001_ECX] =
27861ecc 2119 CPUID_EXT3_LAHF_LM,
0723cc8a
PB		 2120 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS,
2121 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
2122 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
2123 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
2124 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2125 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS,
2126 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2127 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2128 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2129 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2130 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2131 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2132 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2133 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2134 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2135 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2136 .features[FEAT_VMX_SECONDARY_CTLS] =
2137 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES,
3046bb5d 2138 .xlevel = 0x80000008,
3eca4642
EH		 2139 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
2140 },
2141 {
2142 .name = "Penryn",
3046bb5d 2143 .level = 10,
99b88a17 2144 .vendor = CPUID_VENDOR_INTEL,
3eca4642 2145 .family = 6,
ffce9ebb 2146 .model = 23,
3eca4642 2147 .stepping = 3,
0514ef2f 2148 .features[FEAT_1_EDX] =
b3a4f0b1 2149 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2150 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2151 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2152 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2153 CPUID_DE | CPUID_FP87,
0514ef2f 2154 .features[FEAT_1_ECX] =
27861ecc 2155 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
b3fb3a20 2156 CPUID_EXT_SSE3,
0514ef2f 2157 .features[FEAT_8000_0001_EDX] =
27861ecc 2158 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 2159 .features[FEAT_8000_0001_ECX] =
27861ecc 2160 CPUID_EXT3_LAHF_LM,
0723cc8a
PB		 2161 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS,
2162 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2163 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
2164 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT |
2165 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
2166 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
2167 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2168 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS,
2169 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2170 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2171 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2172 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2173 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2174 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2175 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2176 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2177 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2178 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2179 .features[FEAT_VMX_SECONDARY_CTLS] =
2180 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2181 VMX_SECONDARY_EXEC_WBINVD_EXITING,
3046bb5d 2182 .xlevel = 0x80000008,
3eca4642
EH		 2183 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
2184 },
2185 {
2186 .name = "Nehalem",
3046bb5d 2187 .level = 11,
99b88a17 2188 .vendor = CPUID_VENDOR_INTEL,
3eca4642 2189 .family = 6,
ffce9ebb 2190 .model = 26,
3eca4642 2191 .stepping = 3,
0514ef2f 2192 .features[FEAT_1_EDX] =
b3a4f0b1 2193 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2194 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2195 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2196 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2197 CPUID_DE | CPUID_FP87,
0514ef2f 2198 .features[FEAT_1_ECX] =
27861ecc 2199 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
b3fb3a20 2200 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 2201 .features[FEAT_8000_0001_EDX] =
27861ecc 2202 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 2203 .features[FEAT_8000_0001_ECX] =
27861ecc 2204 CPUID_EXT3_LAHF_LM,
0723cc8a
PB		 2205 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2206 MSR_VMX_BASIC_TRUE_CTLS,
2207 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2208 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2209 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2210 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2211 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2212 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2213 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2214 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2215 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2216 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
2217 .features[FEAT_VMX_EXIT_CTLS] =
2218 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2219 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2220 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2221 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2222 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2223 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
2224 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2225 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2226 VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
2227 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2228 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2229 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2230 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2231 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2232 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2233 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2234 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2235 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2236 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2237 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2238 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2239 .features[FEAT_VMX_SECONDARY_CTLS] =
2240 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2241 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2242 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2243 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2244 VMX_SECONDARY_EXEC_ENABLE_VPID,
3046bb5d 2245 .xlevel = 0x80000008,
3eca4642 2246 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
d86a7088
EH		 2247 .versions = (X86CPUVersionDefinition[]) {
2248 { .version = 1 },
2249 {
2250 .version = 2,
53db89d9 2251 .alias = "Nehalem-IBRS",
d86a7088
EH		 2252 .props = (PropValue[]) {
2253 { "spec-ctrl", "on" },
2254 { "model-id",
2255 "Intel Core i7 9xx (Nehalem Core i7, IBRS update)" },
2256 { /* end of list */ }
2257 }
2258 },
2259 { /* end of list */ }
2260 }
3eca4642
EH		 2261 },
2262 {
2263 .name = "Westmere",
2264 .level = 11,
99b88a17 2265 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 2266 .family = 6,
2267 .model = 44,
2268 .stepping = 1,
0514ef2f 2269 .features[FEAT_1_EDX] =
b3a4f0b1 2270 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2271 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2272 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2273 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2274 CPUID_DE | CPUID_FP87,
0514ef2f 2275 .features[FEAT_1_ECX] =
27861ecc 2276 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
b3fb3a20
EH		 2277 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2278 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
0514ef2f 2279 .features[FEAT_8000_0001_EDX] =
27861ecc 2280 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 2281 .features[FEAT_8000_0001_ECX] =
27861ecc 2282 CPUID_EXT3_LAHF_LM,
28b8e4d0
JK		 2283 .features[FEAT_6_EAX] =
2284 CPUID_6_EAX_ARAT,
0723cc8a
PB		 2285 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2286 MSR_VMX_BASIC_TRUE_CTLS,
2287 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2288 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2289 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2290 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2291 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2292 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2293 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2294 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2295 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2296 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
2297 .features[FEAT_VMX_EXIT_CTLS] =
2298 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2299 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2300 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2301 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2302 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2303 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2304 MSR_VMX_MISC_STORE_LMA,
2305 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2306 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2307 VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
2308 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2309 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2310 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2311 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2312 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2313 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2314 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2315 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2316 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2317 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2318 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2319 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2320 .features[FEAT_VMX_SECONDARY_CTLS] =
2321 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2322 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2323 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2324 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2325 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST,
3046bb5d 2326 .xlevel = 0x80000008,
3eca4642 2327 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
d86a7088
EH		 2328 .versions = (X86CPUVersionDefinition[]) {
2329 { .version = 1 },
2330 {
2331 .version = 2,
53db89d9 2332 .alias = "Westmere-IBRS",
d86a7088
EH		 2333 .props = (PropValue[]) {
2334 { "spec-ctrl", "on" },
2335 { "model-id",
2336 "Westmere E56xx/L56xx/X56xx (IBRS update)" },
2337 { /* end of list */ }
2338 }
2339 },
2340 { /* end of list */ }
2341 }
3eca4642
EH		 2342 },
2343 {
2344 .name = "SandyBridge",
2345 .level = 0xd,
99b88a17 2346 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 2347 .family = 6,
2348 .model = 42,
2349 .stepping = 1,
0514ef2f 2350 .features[FEAT_1_EDX] =
b3a4f0b1 2351 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2352 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2353 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2354 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2355 CPUID_DE | CPUID_FP87,
0514ef2f 2356 .features[FEAT_1_ECX] =
27861ecc 2357 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 2358 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
2359 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
2360 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
2361 CPUID_EXT_SSE3,
0514ef2f 2362 .features[FEAT_8000_0001_EDX] =
27861ecc 2363 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
b3fb3a20 2364 CPUID_EXT2_SYSCALL,
0514ef2f 2365 .features[FEAT_8000_0001_ECX] =
27861ecc 2366 CPUID_EXT3_LAHF_LM,
0bb0b2d2
PB		 2367 .features[FEAT_XSAVE] =
2368 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 2369 .features[FEAT_6_EAX] =
2370 CPUID_6_EAX_ARAT,
0723cc8a
PB		 2371 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2372 MSR_VMX_BASIC_TRUE_CTLS,
2373 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2374 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2375 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2376 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2377 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2378 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2379 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2380 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2381 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2382 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
2383 .features[FEAT_VMX_EXIT_CTLS] =
2384 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2385 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2386 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2387 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2388 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2389 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2390 MSR_VMX_MISC_STORE_LMA,
2391 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2392 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2393 VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
2394 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2395 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2396 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2397 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2398 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2399 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2400 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2401 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2402 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2403 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2404 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2405 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2406 .features[FEAT_VMX_SECONDARY_CTLS] =
2407 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2408 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2409 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2410 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2411 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST,
3046bb5d 2412 .xlevel = 0x80000008,
3eca4642 2413 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
d86a7088
EH		 2414 .versions = (X86CPUVersionDefinition[]) {
2415 { .version = 1 },
2416 {
2417 .version = 2,
53db89d9 2418 .alias = "SandyBridge-IBRS",
d86a7088
EH		 2419 .props = (PropValue[]) {
2420 { "spec-ctrl", "on" },
2421 { "model-id",
2422 "Intel Xeon E312xx (Sandy Bridge, IBRS update)" },
2423 { /* end of list */ }
2424 }
2425 },
2426 { /* end of list */ }
2427 }
3eca4642 2428 },
2f9ac42a
PB		 2429 {
2430 .name = "IvyBridge",
2431 .level = 0xd,
2432 .vendor = CPUID_VENDOR_INTEL,
2433 .family = 6,
2434 .model = 58,
2435 .stepping = 9,
2436 .features[FEAT_1_EDX] =
2437 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2438 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2439 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2440 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2441 CPUID_DE | CPUID_FP87,
2442 .features[FEAT_1_ECX] =
2443 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2444 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
2445 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
2446 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
2447 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2448 .features[FEAT_7_0_EBX] =
2449 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP |
2450 CPUID_7_0_EBX_ERMS,
2451 .features[FEAT_8000_0001_EDX] =
2452 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2453 CPUID_EXT2_SYSCALL,
2454 .features[FEAT_8000_0001_ECX] =
2455 CPUID_EXT3_LAHF_LM,
2456 .features[FEAT_XSAVE] =
2457 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 2458 .features[FEAT_6_EAX] =
2459 CPUID_6_EAX_ARAT,
0723cc8a
PB		 2460 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2461 MSR_VMX_BASIC_TRUE_CTLS,
2462 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2463 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2464 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2465 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2466 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2467 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2468 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2469 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2470 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2471 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
2472 .features[FEAT_VMX_EXIT_CTLS] =
2473 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2474 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2475 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2476 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2477 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2478 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2479 MSR_VMX_MISC_STORE_LMA,
2480 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2481 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2482 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
2483 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2484 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2485 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2486 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2487 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2488 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2489 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2490 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2491 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2492 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2493 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2494 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2495 .features[FEAT_VMX_SECONDARY_CTLS] =
2496 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2497 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2498 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2499 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2500 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
2501 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
2502 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2503 VMX_SECONDARY_EXEC_RDRAND_EXITING,
3046bb5d 2504 .xlevel = 0x80000008,
2f9ac42a 2505 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)",
d86a7088
EH		 2506 .versions = (X86CPUVersionDefinition[]) {
2507 { .version = 1 },
2508 {
2509 .version = 2,
53db89d9 2510 .alias = "IvyBridge-IBRS",
d86a7088
EH		 2511 .props = (PropValue[]) {
2512 { "spec-ctrl", "on" },
2513 { "model-id",
2514 "Intel Xeon E3-12xx v2 (Ivy Bridge, IBRS)" },
2515 { /* end of list */ }
2516 }
2517 },
2518 { /* end of list */ }
2519 }
2f9ac42a 2520 },
ac96c413 2521 {
37507094
EH		 2522 .name = "Haswell",
2523 .level = 0xd,
99b88a17 2524 .vendor = CPUID_VENDOR_INTEL,
37507094
EH		 2525 .family = 6,
2526 .model = 60,
ec56a4a7 2527 .stepping = 4,
0514ef2f 2528 .features[FEAT_1_EDX] =
b3a4f0b1 2529 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2530 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2531 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2532 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2533 CPUID_DE | CPUID_FP87,
0514ef2f 2534 .features[FEAT_1_ECX] =
27861ecc 2535 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 2536 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2537 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2538 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2539 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
78a611f1 2540 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
0514ef2f 2541 .features[FEAT_8000_0001_EDX] =
27861ecc 2542 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
b3fb3a20 2543 CPUID_EXT2_SYSCALL,
0514ef2f 2544 .features[FEAT_8000_0001_ECX] =
becb6667 2545 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
0514ef2f 2546 .features[FEAT_7_0_EBX] =
27861ecc 2547 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1ee91598
EH		 2548 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2549 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2550 CPUID_7_0_EBX_RTM,
0bb0b2d2
PB		 2551 .features[FEAT_XSAVE] =
2552 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 2553 .features[FEAT_6_EAX] =
2554 CPUID_6_EAX_ARAT,
0723cc8a
PB		 2555 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2556 MSR_VMX_BASIC_TRUE_CTLS,
2557 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2558 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2559 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2560 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2561 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2562 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2563 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2564 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2565 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2566 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
2567 .features[FEAT_VMX_EXIT_CTLS] =
2568 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2569 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2570 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2571 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2572 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2573 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2574 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
2575 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2576 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2577 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
2578 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2579 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2580 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2581 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2582 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2583 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2584 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2585 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2586 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2587 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2588 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2589 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2590 .features[FEAT_VMX_SECONDARY_CTLS] =
2591 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2592 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2593 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2594 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2595 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
2596 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
2597 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2598 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
2599 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS,
2600 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
3046bb5d 2601 .xlevel = 0x80000008,
37507094 2602 .model_id = "Intel Core Processor (Haswell)",
d86a7088
EH		 2603 .versions = (X86CPUVersionDefinition[]) {
2604 { .version = 1 },
2605 {
2606 .version = 2,
53db89d9 2607 .alias = "Haswell-noTSX",
d86a7088
EH		 2608 .props = (PropValue[]) {
2609 { "hle", "off" },
2610 { "rtm", "off" },
2611 { "stepping", "1" },
2612 { "model-id", "Intel Core Processor (Haswell, no TSX)", },
2613 { /* end of list */ }
2614 },
2615 },
2616 {
2617 .version = 3,
53db89d9 2618 .alias = "Haswell-IBRS",
d86a7088
EH		 2619 .props = (PropValue[]) {
2620 /* Restore TSX features removed by -v2 above */
2621 { "hle", "on" },
2622 { "rtm", "on" },
2623 /*
2624 * Haswell and Haswell-IBRS had stepping=4 in
2625 * QEMU 4.0 and older
2626 */
2627 { "stepping", "4" },
2628 { "spec-ctrl", "on" },
2629 { "model-id",
2630 "Intel Core Processor (Haswell, IBRS)" },
2631 { /* end of list */ }
2632 }
2633 },
2634 {
2635 .version = 4,
53db89d9 2636 .alias = "Haswell-noTSX-IBRS",
d86a7088
EH		 2637 .props = (PropValue[]) {
2638 { "hle", "off" },
2639 { "rtm", "off" },
2640 /* spec-ctrl was already enabled by -v3 above */
2641 { "stepping", "1" },
2642 { "model-id",
2643 "Intel Core Processor (Haswell, no TSX, IBRS)" },
2644 { /* end of list */ }
2645 }
2646 },
2647 { /* end of list */ }
2648 }
37507094 2649 },
ece01354
EH		 2650 {
2651 .name = "Broadwell",
2652 .level = 0xd,
2653 .vendor = CPUID_VENDOR_INTEL,
2654 .family = 6,
2655 .model = 61,
2656 .stepping = 2,
2657 .features[FEAT_1_EDX] =
b3a4f0b1 2658 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
ece01354
EH		 2659 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2660 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2661 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2662 CPUID_DE | CPUID_FP87,
2663 .features[FEAT_1_ECX] =
2664 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2665 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2666 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2667 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2668 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
78a611f1 2669 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
ece01354
EH		 2670 .features[FEAT_8000_0001_EDX] =
2671 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2672 CPUID_EXT2_SYSCALL,
2673 .features[FEAT_8000_0001_ECX] =
becb6667 2674 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
ece01354
EH		 2675 .features[FEAT_7_0_EBX] =
2676 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1ee91598 2677 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
ece01354 2678 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1ee91598 2679 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
ece01354 2680 CPUID_7_0_EBX_SMAP,
0bb0b2d2
PB		 2681 .features[FEAT_XSAVE] =
2682 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 2683 .features[FEAT_6_EAX] =
2684 CPUID_6_EAX_ARAT,
0723cc8a
PB		 2685 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2686 MSR_VMX_BASIC_TRUE_CTLS,
2687 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2688 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2689 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2690 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2691 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2692 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2693 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2694 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2695 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2696 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
2697 .features[FEAT_VMX_EXIT_CTLS] =
2698 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2699 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2700 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2701 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2702 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2703 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2704 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
2705 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2706 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2707 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
2708 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2709 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2710 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2711 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2712 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2713 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2714 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2715 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2716 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2717 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2718 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2719 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2720 .features[FEAT_VMX_SECONDARY_CTLS] =
2721 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2722 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2723 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2724 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2725 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
2726 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
2727 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2728 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
2729 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
2730 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
2731 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
3046bb5d 2732 .xlevel = 0x80000008,
ece01354 2733 .model_id = "Intel Core Processor (Broadwell)",
d86a7088
EH		 2734 .versions = (X86CPUVersionDefinition[]) {
2735 { .version = 1 },
2736 {
2737 .version = 2,
53db89d9 2738 .alias = "Broadwell-noTSX",
d86a7088
EH		 2739 .props = (PropValue[]) {
2740 { "hle", "off" },
2741 { "rtm", "off" },
2742 { "model-id", "Intel Core Processor (Broadwell, no TSX)", },
2743 { /* end of list */ }
2744 },
2745 },
2746 {
2747 .version = 3,
53db89d9 2748 .alias = "Broadwell-IBRS",
d86a7088
EH		 2749 .props = (PropValue[]) {
2750 /* Restore TSX features removed by -v2 above */
2751 { "hle", "on" },
2752 { "rtm", "on" },
2753 { "spec-ctrl", "on" },
2754 { "model-id",
2755 "Intel Core Processor (Broadwell, IBRS)" },
2756 { /* end of list */ }
2757 }
2758 },
2759 {
2760 .version = 4,
53db89d9 2761 .alias = "Broadwell-noTSX-IBRS",
d86a7088
EH		 2762 .props = (PropValue[]) {
2763 { "hle", "off" },
2764 { "rtm", "off" },
2765 /* spec-ctrl was already enabled by -v3 above */
2766 { "model-id",
2767 "Intel Core Processor (Broadwell, no TSX, IBRS)" },
2768 { /* end of list */ }
2769 }
2770 },
2771 { /* end of list */ }
2772 }
ece01354 2773 },
f6f949e9
EH		 2774 {
2775 .name = "Skylake-Client",
2776 .level = 0xd,
2777 .vendor = CPUID_VENDOR_INTEL,
2778 .family = 6,
2779 .model = 94,
2780 .stepping = 3,
2781 .features[FEAT_1_EDX] =
2782 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2783 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2784 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2785 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2786 CPUID_DE | CPUID_FP87,
2787 .features[FEAT_1_ECX] =
2788 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2789 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2790 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2791 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2792 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2793 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2794 .features[FEAT_8000_0001_EDX] =
2795 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2796 CPUID_EXT2_SYSCALL,
2797 .features[FEAT_8000_0001_ECX] =
2798 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2799 .features[FEAT_7_0_EBX] =
2800 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2801 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2802 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2803 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
ecb85fe4 2804 CPUID_7_0_EBX_SMAP,
7bde6b18 2805 /* XSAVES is added in version 4 */
f6f949e9
EH		 2806 .features[FEAT_XSAVE] =
2807 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2808 CPUID_XSAVE_XGETBV1,
2809 .features[FEAT_6_EAX] =
2810 CPUID_6_EAX_ARAT,
0723cc8a
PB		 2811 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
2812 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2813 MSR_VMX_BASIC_TRUE_CTLS,
2814 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2815 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2816 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2817 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2818 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2819 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2820 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2821 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2822 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2823 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
2824 .features[FEAT_VMX_EXIT_CTLS] =
2825 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2826 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2827 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2828 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2829 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2830 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2831 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
2832 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2833 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2834 VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
2835 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2836 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2837 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2838 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2839 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2840 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2841 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2842 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2843 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2844 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2845 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2846 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2847 .features[FEAT_VMX_SECONDARY_CTLS] =
2848 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2849 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2850 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2851 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
2852 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
2853 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
2854 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
2855 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
f6f949e9
EH		 2856 .xlevel = 0x80000008,
2857 .model_id = "Intel Core Processor (Skylake)",
d86a7088
EH		 2858 .versions = (X86CPUVersionDefinition[]) {
2859 { .version = 1 },
2860 {
2861 .version = 2,
53db89d9 2862 .alias = "Skylake-Client-IBRS",
d86a7088
EH		 2863 .props = (PropValue[]) {
2864 { "spec-ctrl", "on" },
2865 { "model-id",
2866 "Intel Core Processor (Skylake, IBRS)" },
2867 { /* end of list */ }
2868 }
2869 },
9ab2237f
EH		 2870 {
2871 .version = 3,
02fa60d1 2872 .alias = "Skylake-Client-noTSX-IBRS",
9ab2237f
EH		 2873 .props = (PropValue[]) {
2874 { "hle", "off" },
2875 { "rtm", "off" },
673b0add
KC		 2876 { "model-id",
2877 "Intel Core Processor (Skylake, IBRS, no TSX)" },
9ab2237f
EH		 2878 { /* end of list */ }
2879 }
2880 },
7bde6b18
VK		 2881 {
2882 .version = 4,
2883 .note = "IBRS, XSAVES, no TSX",
2884 .props = (PropValue[]) {
2885 { "xsaves", "on" },
2886 { "vmx-xsaves", "on" },
2887 { /* end of list */ }
2888 }
2889 },
d86a7088
EH		 2890 { /* end of list */ }
2891 }
f6f949e9 2892 },
53f9a6f4
BF		 2893 {
2894 .name = "Skylake-Server",
2895 .level = 0xd,
2896 .vendor = CPUID_VENDOR_INTEL,
2897 .family = 6,
2898 .model = 85,
2899 .stepping = 4,
2900 .features[FEAT_1_EDX] =
2901 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2902 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2903 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2904 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2905 CPUID_DE | CPUID_FP87,
2906 .features[FEAT_1_ECX] =
2907 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2908 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2909 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2910 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2911 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2912 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2913 .features[FEAT_8000_0001_EDX] =
2914 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
2915 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2916 .features[FEAT_8000_0001_ECX] =
2917 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2918 .features[FEAT_7_0_EBX] =
2919 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2920 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2921 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2922 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
ecb85fe4 2923 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
53f9a6f4
BF		 2924 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
2925 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
c68bcb3a 2926 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
09b9ee64
TX		 2927 .features[FEAT_7_0_ECX] =
2928 CPUID_7_0_ECX_PKU,
7bde6b18 2929 /* XSAVES is added in version 5 */
53f9a6f4
BF		 2930 .features[FEAT_XSAVE] =
2931 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2932 CPUID_XSAVE_XGETBV1,
2933 .features[FEAT_6_EAX] =
2934 CPUID_6_EAX_ARAT,
0723cc8a
PB		 2935 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
2936 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2937 MSR_VMX_BASIC_TRUE_CTLS,
2938 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2939 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2940 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2941 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2942 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2943 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2944 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2945 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2946 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2947 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
2948 .features[FEAT_VMX_EXIT_CTLS] =
2949 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2950 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2951 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2952 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2953 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2954 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2955 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
2956 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2957 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2958 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
2959 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2960 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2961 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2962 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2963 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2964 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2965 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2966 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2967 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2968 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2969 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2970 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2971 .features[FEAT_VMX_SECONDARY_CTLS] =
2972 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2973 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2974 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2975 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2976 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
2977 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
2978 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2979 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
c6f3215f
PB		 2980 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
2981 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
53f9a6f4
BF		 2982 .xlevel = 0x80000008,
2983 .model_id = "Intel Xeon Processor (Skylake)",
d86a7088
EH		 2984 .versions = (X86CPUVersionDefinition[]) {
2985 { .version = 1 },
2986 {
2987 .version = 2,
53db89d9 2988 .alias = "Skylake-Server-IBRS",
d86a7088
EH		 2989 .props = (PropValue[]) {
2990 /* clflushopt was not added to Skylake-Server-IBRS */
2991 /* TODO: add -v3 including clflushopt */
2992 { "clflushopt", "off" },
2993 { "spec-ctrl", "on" },
2994 { "model-id",
2995 "Intel Xeon Processor (Skylake, IBRS)" },
2996 { /* end of list */ }
2997 }
2998 },
9ab2237f
EH		 2999 {
3000 .version = 3,
02fa60d1 3001 .alias = "Skylake-Server-noTSX-IBRS",
9ab2237f
EH		 3002 .props = (PropValue[]) {
3003 { "hle", "off" },
3004 { "rtm", "off" },
673b0add
KC		 3005 { "model-id",
3006 "Intel Xeon Processor (Skylake, IBRS, no TSX)" },
9ab2237f
EH		 3007 { /* end of list */ }
3008 }
3009 },
644e3c5d
CQ		 3010 {
3011 .version = 4,
3012 .props = (PropValue[]) {
3013 { "vmx-eptp-switching", "on" },
3014 { /* end of list */ }
3015 }
3016 },
7bde6b18
VK		 3017 {
3018 .version = 5,
3019 .note = "IBRS, XSAVES, EPT switching, no TSX",
3020 .props = (PropValue[]) {
3021 { "xsaves", "on" },
3022 { "vmx-xsaves", "on" },
3023 { /* end of list */ }
3024 }
3025 },
d86a7088
EH		 3026 { /* end of list */ }
3027 }
53f9a6f4 3028 },
c7a88b52
TX		 3029 {
3030 .name = "Cascadelake-Server",
3031 .level = 0xd,
3032 .vendor = CPUID_VENDOR_INTEL,
3033 .family = 6,
3034 .model = 85,
b0a19803 3035 .stepping = 6,
c7a88b52
TX		 3036 .features[FEAT_1_EDX] =
3037 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3038 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3039 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3040 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3041 CPUID_DE | CPUID_FP87,
3042 .features[FEAT_1_ECX] =
3043 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3044 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
3045 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
3046 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
3047 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
3048 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
3049 .features[FEAT_8000_0001_EDX] =
3050 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
3051 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3052 .features[FEAT_8000_0001_ECX] =
3053 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
3054 .features[FEAT_7_0_EBX] =
3055 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
3056 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
3057 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
3058 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
ecb85fe4 3059 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
c7a88b52
TX		 3060 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
3061 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
4c257911 3062 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
c7a88b52 3063 .features[FEAT_7_0_ECX] =
bb4928c7 3064 CPUID_7_0_ECX_PKU |
c7a88b52
TX		 3065 CPUID_7_0_ECX_AVX512VNNI,
3066 .features[FEAT_7_0_EDX] =
3067 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
7bde6b18 3068 /* XSAVES is added in version 5 */
c7a88b52
TX		 3069 .features[FEAT_XSAVE] =
3070 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
3071 CPUID_XSAVE_XGETBV1,
3072 .features[FEAT_6_EAX] =
3073 CPUID_6_EAX_ARAT,
0723cc8a
PB		 3074 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
3075 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
3076 MSR_VMX_BASIC_TRUE_CTLS,
3077 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
3078 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
3079 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
3080 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
3081 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
3082 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
3083 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3084 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3085 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3086 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
3087 .features[FEAT_VMX_EXIT_CTLS] =
3088 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3089 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3090 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
3091 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3092 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3093 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
3094 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
3095 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
3096 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
3097 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
3098 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3099 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3100 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3101 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3102 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3103 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
3104 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
3105 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
3106 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
3107 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3108 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3109 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3110 .features[FEAT_VMX_SECONDARY_CTLS] =
3111 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3112 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3113 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3114 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3115 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3116 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
3117 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3118 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
c6f3215f
PB		 3119 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
3120 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
c7a88b52
TX		 3121 .xlevel = 0x80000008,
3122 .model_id = "Intel Xeon Processor (Cascadelake)",
fd63c6d1
EH		 3123 .versions = (X86CPUVersionDefinition[]) {
3124 { .version = 1 },
3125 { .version = 2,
47f0d11d 3126 .note = "ARCH_CAPABILITIES",
fd63c6d1
EH		 3127 .props = (PropValue[]) {
3128 { "arch-capabilities", "on" },
3129 { "rdctl-no", "on" },
3130 { "ibrs-all", "on" },
3131 { "skip-l1dfl-vmentry", "on" },
3132 { "mds-no", "on" },
3133 { /* end of list */ }
3134 },
3135 },
9ab2237f 3136 { .version = 3,
02fa60d1 3137 .alias = "Cascadelake-Server-noTSX",
47f0d11d 3138 .note = "ARCH_CAPABILITIES, no TSX",
9ab2237f
EH		 3139 .props = (PropValue[]) {
3140 { "hle", "off" },
3141 { "rtm", "off" },
3142 { /* end of list */ }
3143 },
3144 },
644e3c5d
CQ		 3145 { .version = 4,
3146 .note = "ARCH_CAPABILITIES, no TSX",
3147 .props = (PropValue[]) {
3148 { "vmx-eptp-switching", "on" },
3149 { /* end of list */ }
3150 },
3151 },
7bde6b18
VK		 3152 { .version = 5,
3153 .note = "ARCH_CAPABILITIES, EPT switching, XSAVES, no TSX",
3154 .props = (PropValue[]) {
3155 { "xsaves", "on" },
3156 { "vmx-xsaves", "on" },
3157 { /* end of list */ }
3158 },
3159 },
fd63c6d1
EH		 3160 { /* end of list */ }
3161 }
c7a88b52 3162 },
22a866b6
CZ		 3163 {
3164 .name = "Cooperlake",
3165 .level = 0xd,
3166 .vendor = CPUID_VENDOR_INTEL,
3167 .family = 6,
3168 .model = 85,
3169 .stepping = 10,
3170 .features[FEAT_1_EDX] =
3171 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3172 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3173 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3174 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3175 CPUID_DE | CPUID_FP87,
3176 .features[FEAT_1_ECX] =
3177 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3178 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
3179 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
3180 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
3181 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
3182 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
3183 .features[FEAT_8000_0001_EDX] =
3184 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
3185 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3186 .features[FEAT_8000_0001_ECX] =
3187 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
3188 .features[FEAT_7_0_EBX] =
3189 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
3190 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
3191 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
3192 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
3193 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
3194 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
3195 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
3196 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
3197 .features[FEAT_7_0_ECX] =
3198 CPUID_7_0_ECX_PKU |
3199 CPUID_7_0_ECX_AVX512VNNI,
3200 .features[FEAT_7_0_EDX] =
3201 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_STIBP |
3202 CPUID_7_0_EDX_SPEC_CTRL_SSBD | CPUID_7_0_EDX_ARCH_CAPABILITIES,
3203 .features[FEAT_ARCH_CAPABILITIES] =
3204 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL |
2dea9d9c
XL		 3205 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO |
3206 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO,
22a866b6 3207 .features[FEAT_7_1_EAX] =
c1826ea6 3208 CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_AVX512_BF16,
7bde6b18 3209 /* XSAVES is added in version 2 */
22a866b6
CZ		 3210 .features[FEAT_XSAVE] =
3211 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
3212 CPUID_XSAVE_XGETBV1,
3213 .features[FEAT_6_EAX] =
3214 CPUID_6_EAX_ARAT,
2dea9d9c
XL		 3215 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
3216 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
3217 MSR_VMX_BASIC_TRUE_CTLS,
3218 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
3219 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
3220 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
3221 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
3222 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
3223 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
3224 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3225 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3226 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3227 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
3228 .features[FEAT_VMX_EXIT_CTLS] =
3229 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3230 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3231 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
3232 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3233 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3234 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
3235 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
3236 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
3237 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
3238 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
3239 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3240 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3241 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3242 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3243 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3244 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
3245 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
3246 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
3247 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
3248 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3249 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3250 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3251 .features[FEAT_VMX_SECONDARY_CTLS] =
3252 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3253 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3254 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3255 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3256 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3257 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
3258 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3259 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
3260 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
3261 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
3262 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
22a866b6
CZ		 3263 .xlevel = 0x80000008,
3264 .model_id = "Intel Xeon Processor (Cooperlake)",
7bde6b18
VK		 3265 .versions = (X86CPUVersionDefinition[]) {
3266 { .version = 1 },
3267 { .version = 2,
3268 .note = "XSAVES",
3269 .props = (PropValue[]) {
3270 { "xsaves", "on" },
3271 { "vmx-xsaves", "on" },
3272 { /* end of list */ }
3273 },
3274 },
3275 { /* end of list */ }
3276 }
22a866b6 3277 },
8a11c62d
RH		 3278 {
3279 .name = "Icelake-Client",
3280 .level = 0xd,
3281 .vendor = CPUID_VENDOR_INTEL,
3282 .family = 6,
3283 .model = 126,
3284 .stepping = 0,
3285 .features[FEAT_1_EDX] =
3286 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3287 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3288 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3289 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3290 CPUID_DE | CPUID_FP87,
3291 .features[FEAT_1_ECX] =
3292 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3293 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
3294 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
3295 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
3296 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
3297 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
3298 .features[FEAT_8000_0001_EDX] =
3299 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
3300 CPUID_EXT2_SYSCALL,
3301 .features[FEAT_8000_0001_ECX] =
3302 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
3303 .features[FEAT_8000_0008_EBX] =
3304 CPUID_8000_0008_EBX_WBNOINVD,
3305 .features[FEAT_7_0_EBX] =
3306 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
3307 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
3308 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
3309 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
4c257911 3310 CPUID_7_0_EBX_SMAP,
8a11c62d 3311 .features[FEAT_7_0_ECX] =
e7694a5e
TX		 3312 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU |
3313 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI |
8a11c62d
RH		 3314 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ |
3315 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG |
3316 CPUID_7_0_ECX_AVX512_VPOPCNTDQ,
3317 .features[FEAT_7_0_EDX] =
3318 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
7bde6b18 3319 /* XSAVES is added in version 3 */
8a11c62d
RH		 3320 .features[FEAT_XSAVE] =
3321 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
3322 CPUID_XSAVE_XGETBV1,
3323 .features[FEAT_6_EAX] =
3324 CPUID_6_EAX_ARAT,
0723cc8a
PB		 3325 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
3326 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
3327 MSR_VMX_BASIC_TRUE_CTLS,
3328 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
3329 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
3330 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
3331 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
3332 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
3333 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
3334 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3335 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3336 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3337 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
3338 .features[FEAT_VMX_EXIT_CTLS] =
3339 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3340 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3341 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
3342 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3343 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3344 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
3345 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
3346 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
3347 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
3348 VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
3349 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3350 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3351 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3352 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3353 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3354 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
3355 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
3356 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
3357 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
3358 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3359 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3360 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3361 .features[FEAT_VMX_SECONDARY_CTLS] =
3362 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3363 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3364 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3365 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3366 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
3367 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
3368 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
3369 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
8a11c62d
RH		 3370 .xlevel = 0x80000008,
3371 .model_id = "Intel Core Processor (Icelake)",
9ab2237f 3372 .versions = (X86CPUVersionDefinition[]) {
3e6a015c
RH		 3373 {
3374 .version = 1,
3375 .note = "deprecated"
3376 },
9ab2237f
EH		 3377 {
3378 .version = 2,
3e6a015c 3379 .note = "no TSX, deprecated",
02fa60d1 3380 .alias = "Icelake-Client-noTSX",
9ab2237f
EH		 3381 .props = (PropValue[]) {
3382 { "hle", "off" },
3383 { "rtm", "off" },
3384 { /* end of list */ }
3385 },
3386 },
7bde6b18
VK		 3387 {
3388 .version = 3,
3389 .note = "no TSX, XSAVES, deprecated",
3390 .props = (PropValue[]) {
3391 { "xsaves", "on" },
3392 { "vmx-xsaves", "on" },
3393 { /* end of list */ }
3394 },
3395 },
9ab2237f 3396 { /* end of list */ }
3e6a015c
RH		 3397 },
3398 .deprecation_note = "use Icelake-Server instead"
8a11c62d
RH		 3399 },
3400 {
3401 .name = "Icelake-Server",
3402 .level = 0xd,
3403 .vendor = CPUID_VENDOR_INTEL,
3404 .family = 6,
3405 .model = 134,
3406 .stepping = 0,
3407 .features[FEAT_1_EDX] =
3408 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3409 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3410 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3411 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3412 CPUID_DE | CPUID_FP87,
3413 .features[FEAT_1_ECX] =
3414 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3415 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
3416 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
3417 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
3418 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
3419 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
3420 .features[FEAT_8000_0001_EDX] =
3421 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
3422 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3423 .features[FEAT_8000_0001_ECX] =
3424 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
3425 .features[FEAT_8000_0008_EBX] =
3426 CPUID_8000_0008_EBX_WBNOINVD,
3427 .features[FEAT_7_0_EBX] =
3428 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
3429 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
3430 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
3431 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
ecb85fe4 3432 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
8a11c62d
RH		 3433 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
3434 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
4c257911 3435 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
8a11c62d 3436 .features[FEAT_7_0_ECX] =
e7694a5e
TX		 3437 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU |
3438 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI |
8a11c62d
RH		 3439 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ |
3440 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG |
3441 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57,
3442 .features[FEAT_7_0_EDX] =
76e5a4d5 3443 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
7bde6b18 3444 /* XSAVES is added in version 5 */
8a11c62d
RH		 3445 .features[FEAT_XSAVE] =
3446 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
3447 CPUID_XSAVE_XGETBV1,
3448 .features[FEAT_6_EAX] =
3449 CPUID_6_EAX_ARAT,
0723cc8a
PB		 3450 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
3451 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
3452 MSR_VMX_BASIC_TRUE_CTLS,
3453 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
3454 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
3455 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
3456 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
3457 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
3458 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
3459 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3460 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3461 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3462 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
3463 .features[FEAT_VMX_EXIT_CTLS] =
3464 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3465 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3466 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
3467 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3468 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3469 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
3470 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
3471 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
3472 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
3473 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
3474 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3475 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3476 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3477 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3478 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3479 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
3480 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
3481 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
3482 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
3483 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3484 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3485 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3486 .features[FEAT_VMX_SECONDARY_CTLS] =
3487 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3488 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3489 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3490 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3491 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3492 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
3493 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3494 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
3495 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS,
8a11c62d
RH		 3496 .xlevel = 0x80000008,
3497 .model_id = "Intel Xeon Processor (Icelake)",
9ab2237f
EH		 3498 .versions = (X86CPUVersionDefinition[]) {
3499 { .version = 1 },
3500 {
3501 .version = 2,
47f0d11d 3502 .note = "no TSX",
02fa60d1 3503 .alias = "Icelake-Server-noTSX",
9ab2237f
EH		 3504 .props = (PropValue[]) {
3505 { "hle", "off" },
3506 { "rtm", "off" },
3507 { /* end of list */ }
3508 },
3509 },
d965dc35
XL		 3510 {
3511 .version = 3,
3512 .props = (PropValue[]) {
3513 { "arch-capabilities", "on" },
3514 { "rdctl-no", "on" },
3515 { "ibrs-all", "on" },
3516 { "skip-l1dfl-vmentry", "on" },
3517 { "mds-no", "on" },
3518 { "pschange-mc-no", "on" },
3519 { "taa-no", "on" },
3520 { /* end of list */ }
3521 },
3522 },
e0013791
CQ		 3523 {
3524 .version = 4,
3525 .props = (PropValue[]) {
3526 { "sha-ni", "on" },
3527 { "avx512ifma", "on" },
3528 { "rdpid", "on" },
3529 { "fsrm", "on" },
3530 { "vmx-rdseed-exit", "on" },
3531 { "vmx-pml", "on" },
3532 { "vmx-eptp-switching", "on" },
3533 { "model", "106" },
3534 { /* end of list */ }
3535 },
3536 },
7bde6b18
VK		 3537 {
3538 .version = 5,
3539 .note = "XSAVES",
3540 .props = (PropValue[]) {
3541 { "xsaves", "on" },
3542 { "vmx-xsaves", "on" },
3543 { /* end of list */ }
3544 },
3545 },
9ab2237f
EH		 3546 { /* end of list */ }
3547 }
8a11c62d 3548 },
8b44d860
TX		 3549 {
3550 .name = "Denverton",
3551 .level = 21,
3552 .vendor = CPUID_VENDOR_INTEL,
3553 .family = 6,
3554 .model = 95,
3555 .stepping = 1,
3556 .features[FEAT_1_EDX] =
3557 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC |
3558 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC |
3559 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV |
3560 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR |
3561 CPUID_SSE | CPUID_SSE2,
3562 .features[FEAT_1_ECX] =
3563 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR |
3564 CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | CPUID_EXT_SSE41 |
3565 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE |
3566 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER |
3567 CPUID_EXT_AES | CPUID_EXT_XSAVE | CPUID_EXT_RDRAND,
3568 .features[FEAT_8000_0001_EDX] =
3569 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB |
3570 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM,
3571 .features[FEAT_8000_0001_ECX] =
3572 CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
3573 .features[FEAT_7_0_EBX] =
3574 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_ERMS |
3575 CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_SMAP |
3576 CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_SHA_NI,
3577 .features[FEAT_7_0_EDX] =
3578 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_ARCH_CAPABILITIES |
3579 CPUID_7_0_EDX_SPEC_CTRL_SSBD,
7bde6b18 3580 /* XSAVES is added in version 3 */
8b44d860
TX		 3581 .features[FEAT_XSAVE] =
3582 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | CPUID_XSAVE_XGETBV1,
3583 .features[FEAT_6_EAX] =
3584 CPUID_6_EAX_ARAT,
3585 .features[FEAT_ARCH_CAPABILITIES] =
3586 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY,
0723cc8a
PB		 3587 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
3588 MSR_VMX_BASIC_TRUE_CTLS,
3589 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
3590 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
3591 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
3592 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
3593 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
3594 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
3595 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3596 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3597 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3598 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
3599 .features[FEAT_VMX_EXIT_CTLS] =
3600 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3601 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3602 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
3603 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3604 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3605 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
3606 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
3607 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
3608 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
3609 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
3610 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3611 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3612 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3613 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3614 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3615 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
3616 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
3617 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
3618 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
3619 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3620 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3621 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3622 .features[FEAT_VMX_SECONDARY_CTLS] =
3623 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3624 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3625 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3626 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3627 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3628 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
3629 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3630 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
3631 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
3632 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
3633 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
8b44d860
TX		 3634 .xlevel = 0x80000008,
3635 .model_id = "Intel Atom Processor (Denverton)",
ab0c942c
TX		 3636 .versions = (X86CPUVersionDefinition[]) {
3637 { .version = 1 },
3638 {
3639 .version = 2,
47f0d11d 3640 .note = "no MPX, no MONITOR",
ab0c942c
TX		 3641 .props = (PropValue[]) {
3642 { "monitor", "off" },
3643 { "mpx", "off" },
3644 { /* end of list */ },
3645 },
3646 },
7bde6b18
VK		 3647 {
3648 .version = 3,
3649 .note = "XSAVES, no MPX, no MONITOR",
3650 .props = (PropValue[]) {
3651 { "xsaves", "on" },
3652 { "vmx-xsaves", "on" },
3653 { /* end of list */ },
3654 },
3655 },
ab0c942c
TX		 3656 { /* end of list */ },
3657 },
8b44d860 3658 },
0b18874b 3659 {
ff656fcd 3660 .name = "Snowridge",
0b18874b
PL		 3661 .level = 27,
3662 .vendor = CPUID_VENDOR_INTEL,
3663 .family = 6,
3664 .model = 134,
3665 .stepping = 1,
3666 .features[FEAT_1_EDX] =
3667 /* missing: CPUID_PN CPUID_IA64 */
3668 /* missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
3669 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE |
3670 CPUID_TSC | CPUID_MSR | CPUID_PAE | CPUID_MCE |
3671 CPUID_CX8 | CPUID_APIC | CPUID_SEP |
3672 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV |
3673 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH |
3674 CPUID_MMX |
3675 CPUID_FXSR | CPUID_SSE | CPUID_SSE2,
3676 .features[FEAT_1_ECX] =
3677 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR |
0b18874b
PL		 3678 CPUID_EXT_SSSE3 |
3679 CPUID_EXT_CX16 |
3680 CPUID_EXT_SSE41 |
3681 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE |
3682 CPUID_EXT_POPCNT |
3683 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | CPUID_EXT_XSAVE |
3684 CPUID_EXT_RDRAND,
3685 .features[FEAT_8000_0001_EDX] =
3686 CPUID_EXT2_SYSCALL |
3687 CPUID_EXT2_NX |
3688 CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
3689 CPUID_EXT2_LM,
3690 .features[FEAT_8000_0001_ECX] =
3691 CPUID_EXT3_LAHF_LM |
3692 CPUID_EXT3_3DNOWPREFETCH,
3693 .features[FEAT_7_0_EBX] =
3694 CPUID_7_0_EBX_FSGSBASE |
3695 CPUID_7_0_EBX_SMEP |
3696 CPUID_7_0_EBX_ERMS |
3697 CPUID_7_0_EBX_MPX | /* missing bits 13, 15 */
3698 CPUID_7_0_EBX_RDSEED |
3699 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
3700 CPUID_7_0_EBX_CLWB |
3701 CPUID_7_0_EBX_SHA_NI,
3702 .features[FEAT_7_0_ECX] =
3703 CPUID_7_0_ECX_UMIP |
3704 /* missing bit 5 */
3705 CPUID_7_0_ECX_GFNI |
3706 CPUID_7_0_ECX_MOVDIRI | CPUID_7_0_ECX_CLDEMOTE |
3707 CPUID_7_0_ECX_MOVDIR64B,
3708 .features[FEAT_7_0_EDX] =
3709 CPUID_7_0_EDX_SPEC_CTRL |
3710 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD |
3711 CPUID_7_0_EDX_CORE_CAPABILITY,
3712 .features[FEAT_CORE_CAPABILITY] =
3713 MSR_CORE_CAP_SPLIT_LOCK_DETECT,
7bde6b18 3714 /* XSAVES is is added in version 3 */
0b18874b
PL		 3715 .features[FEAT_XSAVE] =
3716 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
3717 CPUID_XSAVE_XGETBV1,
3718 .features[FEAT_6_EAX] =
3719 CPUID_6_EAX_ARAT,
0723cc8a
PB		 3720 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
3721 MSR_VMX_BASIC_TRUE_CTLS,
3722 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
3723 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
3724 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
3725 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
3726 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
3727 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
3728 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3729 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3730 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3731 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
3732 .features[FEAT_VMX_EXIT_CTLS] =
3733 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3734 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3735 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
3736 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3737 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3738 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
3739 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
3740 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
3741 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
3742 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
3743 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3744 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3745 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3746 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3747 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3748 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
3749 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
3750 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
3751 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
3752 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3753 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3754 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3755 .features[FEAT_VMX_SECONDARY_CTLS] =
3756 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3757 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3758 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3759 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3760 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3761 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
3762 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3763 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
3764 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
3765 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
3766 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
0b18874b
PL		 3767 .xlevel = 0x80000008,
3768 .model_id = "Intel Atom Processor (SnowRidge)",
69edb0f3
XL		 3769 .versions = (X86CPUVersionDefinition[]) {
3770 { .version = 1 },
3771 {
3772 .version = 2,
3773 .props = (PropValue[]) {
3774 { "mpx", "off" },
3775 { "model-id", "Intel Atom Processor (Snowridge, no MPX)" },
3776 { /* end of list */ },
3777 },
3778 },
7bde6b18
VK		 3779 {
3780 .version = 3,
3781 .note = "XSAVES, no MPX",
3782 .props = (PropValue[]) {
3783 { "xsaves", "on" },
3784 { "vmx-xsaves", "on" },
3785 { /* end of list */ },
3786 },
3787 },
69edb0f3
XL		 3788 { /* end of list */ },
3789 },
0b18874b 3790 },
a1849515
BF		 3791 {
3792 .name = "KnightsMill",
3793 .level = 0xd,
3794 .vendor = CPUID_VENDOR_INTEL,
3795 .family = 6,
3796 .model = 133,
3797 .stepping = 0,
3798 .features[FEAT_1_EDX] =
3799 CPUID_VME | CPUID_SS | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR |
3800 CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV |
3801 CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC |
3802 CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC |
3803 CPUID_PSE | CPUID_DE | CPUID_FP87,
3804 .features[FEAT_1_ECX] =
3805 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3806 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
3807 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
3808 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
3809 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
3810 CPUID_EXT_F16C | CPUID_EXT_RDRAND,
3811 .features[FEAT_8000_0001_EDX] =
3812 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
3813 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3814 .features[FEAT_8000_0001_ECX] =
3815 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
3816 .features[FEAT_7_0_EBX] =
3817 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
3818 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS |
3819 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_AVX512F |
3820 CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_AVX512PF |
3821 CPUID_7_0_EBX_AVX512ER,
3822 .features[FEAT_7_0_ECX] =
3823 CPUID_7_0_ECX_AVX512_VPOPCNTDQ,
3824 .features[FEAT_7_0_EDX] =
3825 CPUID_7_0_EDX_AVX512_4VNNIW | CPUID_7_0_EDX_AVX512_4FMAPS,
3826 .features[FEAT_XSAVE] =
3827 CPUID_XSAVE_XSAVEOPT,
3828 .features[FEAT_6_EAX] =
3829 CPUID_6_EAX_ARAT,
3830 .xlevel = 0x80000008,
3831 .model_id = "Intel Xeon Phi Processor (Knights Mill)",
3832 },
3eca4642
EH		 3833 {
3834 .name = "Opteron_G1",
3835 .level = 5,
99b88a17 3836 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 3837 .family = 15,
3838 .model = 6,
3839 .stepping = 1,
0514ef2f 3840 .features[FEAT_1_EDX] =
b3a4f0b1 3841 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 3842 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3843 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3844 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3845 CPUID_DE | CPUID_FP87,
0514ef2f 3846 .features[FEAT_1_ECX] =
27861ecc 3847 CPUID_EXT_SSE3,
0514ef2f 3848 .features[FEAT_8000_0001_EDX] =
2a923a29 3849 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3eca4642
EH		 3850 .xlevel = 0x80000008,
3851 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
3852 },
3853 {
3854 .name = "Opteron_G2",
3855 .level = 5,
99b88a17 3856 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 3857 .family = 15,
3858 .model = 6,
3859 .stepping = 1,
0514ef2f 3860 .features[FEAT_1_EDX] =
b3a4f0b1 3861 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 3862 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3863 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3864 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3865 CPUID_DE | CPUID_FP87,
0514ef2f 3866 .features[FEAT_1_ECX] =
27861ecc 3867 CPUID_EXT_CX16 | CPUID_EXT_SSE3,
0514ef2f 3868 .features[FEAT_8000_0001_EDX] =
2a923a29 3869 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 3870 .features[FEAT_8000_0001_ECX] =
27861ecc 3871 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH		 3872 .xlevel = 0x80000008,
3873 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
3874 },
3875 {
3876 .name = "Opteron_G3",
3877 .level = 5,
99b88a17 3878 .vendor = CPUID_VENDOR_AMD,
339892d7
EY		 3879 .family = 16,
3880 .model = 2,
3881 .stepping = 3,
0514ef2f 3882 .features[FEAT_1_EDX] =
b3a4f0b1 3883 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 3884 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3885 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3886 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3887 CPUID_DE | CPUID_FP87,
0514ef2f 3888 .features[FEAT_1_ECX] =
27861ecc 3889 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
b3fb3a20 3890 CPUID_EXT_SSE3,
0514ef2f 3891 .features[FEAT_8000_0001_EDX] =
483c6ad4
BP		 3892 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL |
3893 CPUID_EXT2_RDTSCP,
0514ef2f 3894 .features[FEAT_8000_0001_ECX] =
27861ecc 3895 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
b3fb3a20 3896 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH		 3897 .xlevel = 0x80000008,
3898 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
3899 },
3900 {
3901 .name = "Opteron_G4",
3902 .level = 0xd,
99b88a17 3903 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 3904 .family = 21,
3905 .model = 1,
3906 .stepping = 2,
0514ef2f 3907 .features[FEAT_1_EDX] =
b3a4f0b1 3908 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 3909 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3910 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3911 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3912 CPUID_DE | CPUID_FP87,
0514ef2f 3913 .features[FEAT_1_ECX] =
27861ecc 3914 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 3915 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
3916 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
3917 CPUID_EXT_SSE3,
0514ef2f 3918 .features[FEAT_8000_0001_EDX] =
2a923a29 3919 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX |
483c6ad4 3920 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP,
0514ef2f 3921 .features[FEAT_8000_0001_ECX] =
27861ecc 3922 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
b3fb3a20
EH		 3923 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
3924 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
3925 CPUID_EXT3_LAHF_LM,
9fe8b7be
VK		 3926 .features[FEAT_SVM] =
3927 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
0bb0b2d2 3928 /* no xsaveopt! */
3eca4642
EH		 3929 .xlevel = 0x8000001A,
3930 .model_id = "AMD Opteron 62xx class CPU",
3931 },
021941b9
AP		 3932 {
3933 .name = "Opteron_G5",
3934 .level = 0xd,
99b88a17 3935 .vendor = CPUID_VENDOR_AMD,
021941b9
AP		 3936 .family = 21,
3937 .model = 2,
3938 .stepping = 0,
0514ef2f 3939 .features[FEAT_1_EDX] =
b3a4f0b1 3940 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 3941 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3942 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3943 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3944 CPUID_DE | CPUID_FP87,
0514ef2f 3945 .features[FEAT_1_ECX] =
27861ecc 3946 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
b3fb3a20
EH		 3947 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
3948 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
3949 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
0514ef2f 3950 .features[FEAT_8000_0001_EDX] =
2a923a29 3951 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX |
483c6ad4 3952 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP,
0514ef2f 3953 .features[FEAT_8000_0001_ECX] =
27861ecc 3954 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
b3fb3a20
EH		 3955 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
3956 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
3957 CPUID_EXT3_LAHF_LM,
9fe8b7be
VK		 3958 .features[FEAT_SVM] =
3959 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
0bb0b2d2 3960 /* no xsaveopt! */
021941b9
AP		 3961 .xlevel = 0x8000001A,
3962 .model_id = "AMD Opteron 63xx class CPU",
3963 },
2e2efc7d
BS		 3964 {
3965 .name = "EPYC",
3966 .level = 0xd,
3967 .vendor = CPUID_VENDOR_AMD,
3968 .family = 23,
3969 .model = 1,
3970 .stepping = 2,
3971 .features[FEAT_1_EDX] =
3972 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
3973 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
3974 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
3975 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
3976 CPUID_VME | CPUID_FP87,
3977 .features[FEAT_1_ECX] =
3978 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
3979 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT |
3980 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
3981 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
3982 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
3983 .features[FEAT_8000_0001_EDX] =
3984 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
3985 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
3986 CPUID_EXT2_SYSCALL,
3987 .features[FEAT_8000_0001_ECX] =
3988 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
3989 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
e0051647
BM		 3990 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |
3991 CPUID_EXT3_TOPOEXT,
2e2efc7d
BS		 3992 .features[FEAT_7_0_EBX] =
3993 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
3994 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
3995 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
3996 CPUID_7_0_EBX_SHA_NI,
2e2efc7d
BS		 3997 .features[FEAT_XSAVE] =
3998 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
3999 CPUID_XSAVE_XGETBV1,
4000 .features[FEAT_6_EAX] =
4001 CPUID_6_EAX_ARAT,
9fe8b7be
VK		 4002 .features[FEAT_SVM] =
4003 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
e0051647 4004 .xlevel = 0x8000001E,
2e2efc7d 4005 .model_id = "AMD EPYC Processor",
fe52acd2 4006 .cache_info = &epyc_cache_info,
d86a7088
EH		 4007 .versions = (X86CPUVersionDefinition[]) {
4008 { .version = 1 },
4009 {
4010 .version = 2,
53db89d9 4011 .alias = "EPYC-IBPB",
d86a7088
EH		 4012 .props = (PropValue[]) {
4013 { "ibpb", "on" },
4014 { "model-id",
4015 "AMD EPYC Processor (with IBPB)" },
4016 { /* end of list */ }
4017 }
4018 },
a16e8dbc
MB		 4019 {
4020 .version = 3,
4021 .props = (PropValue[]) {
4022 { "ibpb", "on" },
4023 { "perfctr-core", "on" },
4024 { "clzero", "on" },
4025 { "xsaveerptr", "on" },
4026 { "xsaves", "on" },
4027 { "model-id",
4028 "AMD EPYC Processor" },
4029 { /* end of list */ }
4030 }
4031 },
d86a7088
EH		 4032 { /* end of list */ }
4033 }
2e2efc7d 4034 },
8d031cec
PW		 4035 {
4036 .name = "Dhyana",
4037 .level = 0xd,
4038 .vendor = CPUID_VENDOR_HYGON,
4039 .family = 24,
4040 .model = 0,
4041 .stepping = 1,
4042 .features[FEAT_1_EDX] =
4043 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
4044 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
4045 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
4046 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
4047 CPUID_VME | CPUID_FP87,
4048 .features[FEAT_1_ECX] =
4049 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
4050 CPUID_EXT_XSAVE | CPUID_EXT_POPCNT |
4051 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
4052 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
4053 CPUID_EXT_MONITOR | CPUID_EXT_SSE3,
4054 .features[FEAT_8000_0001_EDX] =
4055 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
4056 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
4057 CPUID_EXT2_SYSCALL,
4058 .features[FEAT_8000_0001_ECX] =
4059 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
4060 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
4061 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |
4062 CPUID_EXT3_TOPOEXT,
4063 .features[FEAT_8000_0008_EBX] =
4064 CPUID_8000_0008_EBX_IBPB,
4065 .features[FEAT_7_0_EBX] =
4066 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
4067 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
4068 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT,
7bde6b18 4069 /* XSAVES is added in version 2 */
8d031cec
PW		 4070 .features[FEAT_XSAVE] =
4071 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
4072 CPUID_XSAVE_XGETBV1,
4073 .features[FEAT_6_EAX] =
4074 CPUID_6_EAX_ARAT,
4075 .features[FEAT_SVM] =
4076 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
4077 .xlevel = 0x8000001E,
4078 .model_id = "Hygon Dhyana Processor",
4079 .cache_info = &epyc_cache_info,
7bde6b18
VK		 4080 .versions = (X86CPUVersionDefinition[]) {
4081 { .version = 1 },
4082 { .version = 2,
4083 .note = "XSAVES",
4084 .props = (PropValue[]) {
4085 { "xsaves", "on" },
4086 { /* end of list */ }
4087 },
4088 },
4089 { /* end of list */ }
4090 }
8d031cec 4091 },
143c30d4
MB		 4092 {
4093 .name = "EPYC-Rome",
4094 .level = 0xd,
4095 .vendor = CPUID_VENDOR_AMD,
4096 .family = 23,
4097 .model = 49,
4098 .stepping = 0,
4099 .features[FEAT_1_EDX] =
4100 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
4101 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
4102 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
4103 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
4104 CPUID_VME | CPUID_FP87,
4105 .features[FEAT_1_ECX] =
4106 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
4107 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT |
4108 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
4109 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
4110 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
4111 .features[FEAT_8000_0001_EDX] =
4112 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
4113 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
4114 CPUID_EXT2_SYSCALL,
4115 .features[FEAT_8000_0001_ECX] =
4116 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
4117 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
4118 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |
4119 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE,
4120 .features[FEAT_8000_0008_EBX] =
4121 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR |
4122 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB |
4123 CPUID_8000_0008_EBX_STIBP,
4124 .features[FEAT_7_0_EBX] =
4125 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
4126 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
4127 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
4128 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_CLWB,
4129 .features[FEAT_7_0_ECX] =
4130 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_RDPID,
4131 .features[FEAT_XSAVE] =
4132 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
4133 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES,
4134 .features[FEAT_6_EAX] =
4135 CPUID_6_EAX_ARAT,
4136 .features[FEAT_SVM] =
4137 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
4138 .xlevel = 0x8000001E,
4139 .model_id = "AMD EPYC-Rome Processor",
4140 .cache_info = &epyc_rome_cache_info,
cdeaed27
BM		 4141 .versions = (X86CPUVersionDefinition[]) {
4142 { .version = 1 },
4143 {
4144 .version = 2,
4145 .props = (PropValue[]) {
4146 { "ibrs", "on" },
4147 { "amd-ssbd", "on" },
4148 { /* end of list */ }
4149 }
4150 },
4151 { /* end of list */ }
4152 }
143c30d4 4153 },
623972ce
BM		 4154 {
4155 .name = "EPYC-Milan",
4156 .level = 0xd,
4157 .vendor = CPUID_VENDOR_AMD,
4158 .family = 25,
4159 .model = 1,
4160 .stepping = 1,
4161 .features[FEAT_1_EDX] =
4162 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
4163 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
4164 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
4165 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
4166 CPUID_VME | CPUID_FP87,
4167 .features[FEAT_1_ECX] =
4168 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
4169 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT |
4170 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
4171 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
4172 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
4173 CPUID_EXT_PCID,
4174 .features[FEAT_8000_0001_EDX] =
4175 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
4176 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
4177 CPUID_EXT2_SYSCALL,
4178 .features[FEAT_8000_0001_ECX] =
4179 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
4180 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
4181 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |
4182 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE,
4183 .features[FEAT_8000_0008_EBX] =
4184 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR |
4185 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB |
4186 CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP |
4187 CPUID_8000_0008_EBX_AMD_SSBD,
4188 .features[FEAT_7_0_EBX] =
4189 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
4190 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
4191 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
4192 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_ERMS |
4193 CPUID_7_0_EBX_INVPCID,
4194 .features[FEAT_7_0_ECX] =
4195 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_PKU,
4196 .features[FEAT_7_0_EDX] =
4197 CPUID_7_0_EDX_FSRM,
4198 .features[FEAT_XSAVE] =
4199 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
4200 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES,
4201 .features[FEAT_6_EAX] =
4202 CPUID_6_EAX_ARAT,
4203 .features[FEAT_SVM] =
4204 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE | CPUID_SVM_SVME_ADDR_CHK,
4205 .xlevel = 0x8000001E,
4206 .model_id = "AMD EPYC-Milan Processor",
4207 .cache_info = &epyc_milan_cache_info,
4208 },
c6dc6f63
AP		 4209};
4210
ad183928
EH		 4211/*
4212 * We resolve CPU model aliases using -v1 when using "-machine
4213 * none", but this is just for compatibility while libvirt isn't
4214 * adapted to resolve CPU model versions before creating VMs.
32048d72
MA		 4215 * See "Runnability guarantee of CPU models" at
4216 * docs/system/deprecated.rst.
ad183928
EH		 4217 */
4218X86CPUVersion default_cpu_version = 1;
0788a56b
EH		 4219
4220void x86_cpu_set_default_version(X86CPUVersion version)
4221{
4222 /* Translating CPU_VERSION_AUTO to CPU_VERSION_AUTO doesn't make sense */
4223 assert(version != CPU_VERSION_AUTO);
4224 default_cpu_version = version;
4225}
4226
dcafd1ef
EH		 4227static X86CPUVersion x86_cpu_model_last_version(const X86CPUModel *model)
4228{
4229 int v = 0;
4230 const X86CPUVersionDefinition *vdef =
4231 x86_cpu_def_get_versions(model->cpudef);
4232 while (vdef->version) {
4233 v = vdef->version;
4234 vdef++;
4235 }
4236 return v;
4237}
4238
4239/* Return the actual version being used for a specific CPU model */
4240static X86CPUVersion x86_cpu_model_resolve_version(const X86CPUModel *model)
4241{
4242 X86CPUVersion v = model->version;
0788a56b
EH		 4243 if (v == CPU_VERSION_AUTO) {
4244 v = default_cpu_version;
4245 }
dcafd1ef
EH		 4246 if (v == CPU_VERSION_LATEST) {
4247 return x86_cpu_model_last_version(model);
4248 }
4249 return v;
4250}
4251
c62f2630 4252static Property max_x86_cpu_properties[] = {
120eee7d 4253 DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true),
e265e3e4 4254 DEFINE_PROP_BOOL("host-cache-info", X86CPU, cache_info_passthrough, false),
84f1b92f
EH		 4255 DEFINE_PROP_END_OF_LIST()
4256};
4257
c62f2630 4258static void max_x86_cpu_class_init(ObjectClass *oc, void *data)
c6dc6f63 4259{
84f1b92f 4260 DeviceClass *dc = DEVICE_CLASS(oc);
d940ee9b 4261 X86CPUClass *xcc = X86_CPU_CLASS(oc);
c6dc6f63 4262
f48c8837 4263 xcc->ordering = 9;
6e746f30 4264
ee465a3e 4265 xcc->model_description =
c62f2630 4266 "Enables all features supported by the accelerator in the current host";
d940ee9b 4267
4f67d30b 4268 device_class_set_props(dc, max_x86_cpu_properties);
d940ee9b
EH		 4269}
4270
c62f2630 4271static void max_x86_cpu_initfn(Object *obj)
d940ee9b
EH		 4272{
4273 X86CPU *cpu = X86_CPU(obj);
d940ee9b 4274
4d1b279b
EH		 4275 /* We can't fill the features array here because we don't know yet if
4276 * "migratable" is true or false.
4277 */
44bd8e53 4278 cpu->max_features = true;
5325cc34 4279 object_property_set_bool(OBJECT(cpu), "pmu", true, &error_abort);
f5cc5a5c
CF		 4280
4281 /*
4282 * these defaults are used for TCG and all other accelerators
4283 * besides KVM and HVF, which overwrite these values
4284 */
4285 object_property_set_str(OBJECT(cpu), "vendor", CPUID_VENDOR_AMD,
4286 &error_abort);
4287 object_property_set_int(OBJECT(cpu), "family", 6, &error_abort);
4288 object_property_set_int(OBJECT(cpu), "model", 6, &error_abort);
4289 object_property_set_int(OBJECT(cpu), "stepping", 3, &error_abort);
4290 object_property_set_str(OBJECT(cpu), "model-id",
4291 "QEMU TCG CPU version " QEMU_HW_VERSION,
4292 &error_abort);
c6dc6f63
AP		 4293}
4294
c62f2630
EH		 4295static const TypeInfo max_x86_cpu_type_info = {
4296 .name = X86_CPU_TYPE_NAME("max"),
4297 .parent = TYPE_X86_CPU,
4298 .instance_init = max_x86_cpu_initfn,
4299 .class_init = max_x86_cpu_class_init,
4300};
4301
07585923
RH		 4302static char *feature_word_description(FeatureWordInfo *f, uint32_t bit)
4303{
4304 assert(f->type == CPUID_FEATURE_WORD || f->type == MSR_FEATURE_WORD);
4305
4306 switch (f->type) {
4307 case CPUID_FEATURE_WORD:
4308 {
4309 const char *reg = get_register_name_32(f->cpuid.reg);
4310 assert(reg);
4311 return g_strdup_printf("CPUID.%02XH:%s",
4312 f->cpuid.eax, reg);
4313 }
4314 case MSR_FEATURE_WORD:
4315 return g_strdup_printf("MSR(%02XH)",
4316 f->msr.index);
4317 }
4318
4319 return NULL;
4320}
4321
245edd0c 4322static bool x86_cpu_have_filtered_features(X86CPU *cpu)
c6dc6f63 4323{
245edd0c
PB		 4324 FeatureWord w;
4325
4326 for (w = 0; w < FEATURE_WORDS; w++) {
4327 if (cpu->filtered_features[w]) {
4328 return true;
4329 }
4330 }
4331
4332 return false;
4333}
4334
ede146c2 4335static void mark_unavailable_features(X86CPU *cpu, FeatureWord w, uint64_t mask,
245edd0c
PB		 4336 const char *verbose_prefix)
4337{
4338 CPUX86State *env = &cpu->env;
8459e396 4339 FeatureWordInfo *f = &feature_word_info[w];
c6dc6f63
AP		 4340 int i;
4341
245edd0c
PB		 4342 if (!cpu->force_features) {
4343 env->features[w] &= ~mask;
4344 }
4345 cpu->filtered_features[w] |= mask;
4346
4347 if (!verbose_prefix) {
4348 return;
4349 }
4350
ede146c2
PB		 4351 for (i = 0; i < 64; ++i) {
4352 if ((1ULL << i) & mask) {
88703ce2 4353 g_autofree char *feat_word_str = feature_word_description(f, i);
245edd0c
PB		 4354 warn_report("%s: %s%s%s [bit %d]",
4355 verbose_prefix,
07585923 4356 feat_word_str,
8297be80
AF		 4357 f->feat_names[i] ? "." : "",
4358 f->feat_names[i] ? f->feat_names[i] : "", i);
c6dc6f63 4359 }
857aee33 4360 }
c6dc6f63
AP		 4361}
4362
d7bce999
EB		 4363static void x86_cpuid_version_get_family(Object *obj, Visitor *v,
4364 const char *name, void *opaque,
4365 Error **errp)
95b8519d
AF		 4366{
4367 X86CPU *cpu = X86_CPU(obj);
4368 CPUX86State *env = &cpu->env;
4369 int64_t value;
4370
4371 value = (env->cpuid_version >> 8) & 0xf;
4372 if (value == 0xf) {
4373 value += (env->cpuid_version >> 20) & 0xff;
4374 }
51e72bc1 4375 visit_type_int(v, name, &value, errp);
95b8519d
AF		 4376}
4377
d7bce999
EB		 4378static void x86_cpuid_version_set_family(Object *obj, Visitor *v,
4379 const char *name, void *opaque,
4380 Error **errp)
ed5e1ec3 4381{
71ad61d3
AF		 4382 X86CPU *cpu = X86_CPU(obj);
4383 CPUX86State *env = &cpu->env;
4384 const int64_t min = 0;
4385 const int64_t max = 0xff + 0xf;
4386 int64_t value;
4387
668f62ec 4388 if (!visit_type_int(v, name, &value, errp)) {
71ad61d3
AF		 4389 return;
4390 }
4391 if (value < min || value > max) {
c6bd8c70
MA		 4392 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
4393 name ? name : "null", value, min, max);
71ad61d3
AF		 4394 return;
4395 }
4396
ed5e1ec3 4397 env->cpuid_version &= ~0xff00f00;
71ad61d3
AF		 4398 if (value > 0x0f) {
4399 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
ed5e1ec3 4400 } else {
71ad61d3 4401 env->cpuid_version |= value << 8;
ed5e1ec3
AF		 4402 }
4403}
4404
d7bce999
EB		 4405static void x86_cpuid_version_get_model(Object *obj, Visitor *v,
4406 const char *name, void *opaque,
4407 Error **errp)
67e30c83
AF		 4408{
4409 X86CPU *cpu = X86_CPU(obj);
4410 CPUX86State *env = &cpu->env;
4411 int64_t value;
4412
4413 value = (env->cpuid_version >> 4) & 0xf;
4414 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
51e72bc1 4415 visit_type_int(v, name, &value, errp);
67e30c83
AF		 4416}
4417
d7bce999
EB		 4418static void x86_cpuid_version_set_model(Object *obj, Visitor *v,
4419 const char *name, void *opaque,
4420 Error **errp)
b0704cbd 4421{
c5291a4f
AF		 4422 X86CPU *cpu = X86_CPU(obj);
4423 CPUX86State *env = &cpu->env;
4424 const int64_t min = 0;
4425 const int64_t max = 0xff;
4426 int64_t value;
4427
668f62ec 4428 if (!visit_type_int(v, name, &value, errp)) {
c5291a4f
AF		 4429 return;
4430 }
4431 if (value < min || value > max) {
c6bd8c70
MA		 4432 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
4433 name ? name : "null", value, min, max);
c5291a4f
AF		 4434 return;
4435 }
4436
b0704cbd 4437 env->cpuid_version &= ~0xf00f0;
c5291a4f 4438 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
b0704cbd
AF		 4439}
4440
35112e41 4441static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
d7bce999 4442 const char *name, void *opaque,
35112e41
AF		 4443 Error **errp)
4444{
4445 X86CPU *cpu = X86_CPU(obj);
4446 CPUX86State *env = &cpu->env;
4447 int64_t value;
4448
4449 value = env->cpuid_version & 0xf;
51e72bc1 4450 visit_type_int(v, name, &value, errp);
35112e41
AF		 4451}
4452
036e2222 4453static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
d7bce999 4454 const char *name, void *opaque,
036e2222 4455 Error **errp)
38c3dc46 4456{
036e2222
AF		 4457 X86CPU *cpu = X86_CPU(obj);
4458 CPUX86State *env = &cpu->env;
4459 const int64_t min = 0;
4460 const int64_t max = 0xf;
4461 int64_t value;
4462
668f62ec 4463 if (!visit_type_int(v, name, &value, errp)) {
036e2222
AF		 4464 return;
4465 }
4466 if (value < min || value > max) {
c6bd8c70
MA		 4467 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
4468 name ? name : "null", value, min, max);
036e2222
AF		 4469 return;
4470 }
4471
38c3dc46 4472 env->cpuid_version &= ~0xf;
036e2222 4473 env->cpuid_version |= value & 0xf;
38c3dc46
AF		 4474}
4475
d480e1af
AF		 4476static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
4477{
4478 X86CPU *cpu = X86_CPU(obj);
4479 CPUX86State *env = &cpu->env;
4480 char *value;
d480e1af 4481
e42a92ae 4482 value = g_malloc(CPUID_VENDOR_SZ + 1);
99b88a17
IM		 4483 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2,
4484 env->cpuid_vendor3);
d480e1af
AF		 4485 return value;
4486}
4487
4488static void x86_cpuid_set_vendor(Object *obj, const char *value,
4489 Error **errp)
4490{
4491 X86CPU *cpu = X86_CPU(obj);
4492 CPUX86State *env = &cpu->env;
4493 int i;
4494
9df694ee 4495 if (strlen(value) != CPUID_VENDOR_SZ) {
c6bd8c70 4496 error_setg(errp, QERR_PROPERTY_VALUE_BAD, "", "vendor", value);
d480e1af
AF		 4497 return;
4498 }
4499
4500 env->cpuid_vendor1 = 0;
4501 env->cpuid_vendor2 = 0;
4502 env->cpuid_vendor3 = 0;
4503 for (i = 0; i < 4; i++) {
4504 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
4505 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
4506 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
4507 }
d480e1af
AF		 4508}
4509
63e886eb
AF		 4510static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
4511{
4512 X86CPU *cpu = X86_CPU(obj);
4513 CPUX86State *env = &cpu->env;
4514 char *value;
4515 int i;
4516
4517 value = g_malloc(48 + 1);
4518 for (i = 0; i < 48; i++) {
4519 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
4520 }
4521 value[48] = '\0';
4522 return value;
4523}
4524
938d4c25
AF		 4525static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
4526 Error **errp)
dcce6675 4527{
938d4c25
AF		 4528 X86CPU *cpu = X86_CPU(obj);
4529 CPUX86State *env = &cpu->env;
dcce6675
AF		 4530 int c, len, i;
4531
4532 if (model_id == NULL) {
4533 model_id = "";
4534 }
4535 len = strlen(model_id);
d0a6acf4 4536 memset(env->cpuid_model, 0, 48);
dcce6675
AF		 4537 for (i = 0; i < 48; i++) {
4538 if (i >= len) {
4539 c = '\0';
4540 } else {
4541 c = (uint8_t)model_id[i];
4542 }
4543 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
4544 }
4545}
4546
d7bce999
EB		 4547static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, const char *name,
4548 void *opaque, Error **errp)
89e48965
AF		 4549{
4550 X86CPU *cpu = X86_CPU(obj);
4551 int64_t value;
4552
4553 value = cpu->env.tsc_khz * 1000;
51e72bc1 4554 visit_type_int(v, name, &value, errp);
89e48965
AF		 4555}
4556
d7bce999
EB		 4557static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, const char *name,
4558 void *opaque, Error **errp)
89e48965
AF		 4559{
4560 X86CPU *cpu = X86_CPU(obj);
4561 const int64_t min = 0;
2e84849a 4562 const int64_t max = INT64_MAX;
89e48965
AF		 4563 int64_t value;
4564
668f62ec 4565 if (!visit_type_int(v, name, &value, errp)) {
89e48965
AF		 4566 return;
4567 }
4568 if (value < min || value > max) {
c6bd8c70
MA		 4569 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
4570 name ? name : "null", value, min, max);
89e48965
AF		 4571 return;
4572 }
4573
36f96c4b 4574 cpu->env.tsc_khz = cpu->env.user_tsc_khz = value / 1000;
89e48965
AF		 4575}
4576
7e5292b5 4577/* Generic getter for "feature-words" and "filtered-features" properties */
d7bce999
EB		 4578static void x86_cpu_get_feature_words(Object *obj, Visitor *v,
4579 const char *name, void *opaque,
4580 Error **errp)
8e8aba50 4581{
ede146c2 4582 uint64_t *array = (uint64_t *)opaque;
8e8aba50 4583 FeatureWord w;
8e8aba50
EH		 4584 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { };
4585 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { };
4586 X86CPUFeatureWordInfoList *list = NULL;
4587
4588 for (w = 0; w < FEATURE_WORDS; w++) {
4589 FeatureWordInfo *wi = &feature_word_info[w];
07585923
RH		 4590 /*
4591 * We didn't have MSR features when "feature-words" was
4592 * introduced. Therefore skipped other type entries.
4593 */
4594 if (wi->type != CPUID_FEATURE_WORD) {
4595 continue;
4596 }
8e8aba50 4597 X86CPUFeatureWordInfo *qwi = &word_infos[w];
07585923
RH		 4598 qwi->cpuid_input_eax = wi->cpuid.eax;
4599 qwi->has_cpuid_input_ecx = wi->cpuid.needs_ecx;
4600 qwi->cpuid_input_ecx = wi->cpuid.ecx;
4601 qwi->cpuid_register = x86_reg_info_32[wi->cpuid.reg].qapi_enum;
7e5292b5 4602 qwi->features = array[w];
8e8aba50
EH		 4603
4604 /* List will be in reverse order, but order shouldn't matter */
4605 list_entries[w].next = list;
4606 list_entries[w].value = &word_infos[w];
4607 list = &list_entries[w];
4608 }
4609
6b62d961 4610 visit_type_X86CPUFeatureWordInfoList(v, "feature-words", &list, errp);
8e8aba50
EH		 4611}
4612
72ac2e87
IM		 4613/* Convert all '_' in a feature string option name to '-', to make feature
4614 * name conform to QOM property naming rule, which uses '-' instead of '_'.
4615 */
4616static inline void feat2prop(char *s)
4617{
4618 while ((s = strchr(s, '_'))) {
4619 *s = '-';
4620 }
4621}
4622
b54c9377
EH		 4623/* Return the feature property name for a feature flag bit */
4624static const char *x86_cpu_feature_name(FeatureWord w, int bitnr)
4625{
ede146c2 4626 const char *name;
b54c9377
EH		 4627 /* XSAVE components are automatically enabled by other features,
4628 * so return the original feature name instead
4629 */
4630 if (w == FEAT_XSAVE_COMP_LO || w == FEAT_XSAVE_COMP_HI) {
4631 int comp = (w == FEAT_XSAVE_COMP_HI) ? bitnr + 32 : bitnr;
4632
4633 if (comp < ARRAY_SIZE(x86_ext_save_areas) &&
4634 x86_ext_save_areas[comp].bits) {
4635 w = x86_ext_save_areas[comp].feature;
4636 bitnr = ctz32(x86_ext_save_areas[comp].bits);
4637 }
4638 }
4639
ede146c2 4640 assert(bitnr < 64);
b54c9377 4641 assert(w < FEATURE_WORDS);
ede146c2
PB		 4642 name = feature_word_info[w].feat_names[bitnr];
4643 assert(bitnr < 32 || !(name && feature_word_info[w].type == CPUID_FEATURE_WORD));
4644 return name;
b54c9377
EH		 4645}
4646
dc15c051
IM		 4647/* Compatibily hack to maintain legacy +-feat semantic,
4648 * where +-feat overwrites any feature set by
4649 * feat=on|feat even if the later is parsed after +-feat
4650 * (i.e. "-x2apic,x2apic=on" will result in x2apic disabled)
4651 */
2fae0d96 4652static GList *plus_features, *minus_features;
dc15c051 4653
83a00f60
EH		 4654static gint compare_string(gconstpointer a, gconstpointer b)
4655{
4656 return g_strcmp0(a, b);
4657}
4658
8f961357
EH		 4659/* Parse "+feature,-feature,feature=foo" CPU feature string
4660 */
62a48a2a 4661static void x86_cpu_parse_featurestr(const char *typename, char *features,
94a444b2 4662 Error **errp)
8f961357 4663{
8f961357 4664 char *featurestr; /* Single 'key=value" string being parsed */
62a48a2a 4665 static bool cpu_globals_initialized;
83a00f60 4666 bool ambiguous = false;
62a48a2a
IM		 4667
4668 if (cpu_globals_initialized) {
4669 return;
4670 }
4671 cpu_globals_initialized = true;
8f961357 4672
f6750e95
EH		 4673 if (!features) {
4674 return;
4675 }
4676
4677 for (featurestr = strtok(features, ",");
685479bd 4678 featurestr;
f6750e95
EH		 4679 featurestr = strtok(NULL, ",")) {
4680 const char *name;
4681 const char *val = NULL;
4682 char *eq = NULL;
cf2887c9 4683 char num[32];
62a48a2a 4684 GlobalProperty *prop;
c6dc6f63 4685
f6750e95 4686 /* Compatibility syntax: */
c6dc6f63 4687 if (featurestr[0] == '+') {
2fae0d96
EH		 4688 plus_features = g_list_append(plus_features,
4689 g_strdup(featurestr + 1));
f6750e95 4690 continue;
c6dc6f63 4691 } else if (featurestr[0] == '-') {
2fae0d96
EH		 4692 minus_features = g_list_append(minus_features,
4693 g_strdup(featurestr + 1));
f6750e95
EH		 4694 continue;
4695 }
4696
4697 eq = strchr(featurestr, '=');
4698 if (eq) {
4699 *eq++ = 0;
4700 val = eq;
c6dc6f63 4701 } else {
f6750e95 4702 val = "on";
a91987c2 4703 }
f6750e95
EH		 4704
4705 feat2prop(featurestr);
4706 name = featurestr;
4707
83a00f60 4708 if (g_list_find_custom(plus_features, name, compare_string)) {
3dc6f869
AF		 4709 warn_report("Ambiguous CPU model string. "
4710 "Don't mix both \"+%s\" and \"%s=%s\"",
4711 name, name, val);
83a00f60
EH		 4712 ambiguous = true;
4713 }
4714 if (g_list_find_custom(minus_features, name, compare_string)) {
3dc6f869
AF		 4715 warn_report("Ambiguous CPU model string. "
4716 "Don't mix both \"-%s\" and \"%s=%s\"",
4717 name, name, val);
83a00f60
EH		 4718 ambiguous = true;
4719 }
4720
f6750e95
EH		 4721 /* Special case: */
4722 if (!strcmp(name, "tsc-freq")) {
f17fd4fd 4723 int ret;
f46bfdbf 4724 uint64_t tsc_freq;
f6750e95 4725
f17fd4fd 4726 ret = qemu_strtosz_metric(val, NULL, &tsc_freq);
f46bfdbf 4727 if (ret < 0 || tsc_freq > INT64_MAX) {
f6750e95
EH		 4728 error_setg(errp, "bad numerical value %s", val);
4729 return;
4730 }
4731 snprintf(num, sizeof(num), "%" PRId64, tsc_freq);
4732 val = num;
4733 name = "tsc-frequency";
c6dc6f63 4734 }
f6750e95 4735
62a48a2a
IM		 4736 prop = g_new0(typeof(*prop), 1);
4737 prop->driver = typename;
4738 prop->property = g_strdup(name);
4739 prop->value = g_strdup(val);
62a48a2a 4740 qdev_prop_register_global(prop);
f6750e95
EH		 4741 }
4742
83a00f60 4743 if (ambiguous) {
3dc6f869
AF		 4744 warn_report("Compatibility of ambiguous CPU model "
4745 "strings won't be kept on future QEMU versions");
83a00f60 4746 }
c6dc6f63
AP		 4747}
4748
245edd0c 4749static void x86_cpu_filter_features(X86CPU *cpu, bool verbose);
b54c9377 4750
5a853fc5
EH		 4751/* Build a list with the name of all features on a feature word array */
4752static void x86_cpu_list_feature_names(FeatureWordArray features,
c3033fd3 4753 strList **list)
5a853fc5 4754{
c3033fd3 4755 strList **tail = list;
5a853fc5 4756 FeatureWord w;
5a853fc5
EH		 4757
4758 for (w = 0; w < FEATURE_WORDS; w++) {
ede146c2 4759 uint64_t filtered = features[w];
5a853fc5 4760 int i;
ede146c2
PB		 4761 for (i = 0; i < 64; i++) {
4762 if (filtered & (1ULL << i)) {
c3033fd3 4763 QAPI_LIST_APPEND(tail, g_strdup(x86_cpu_feature_name(w, i)));
5a853fc5
EH		 4764 }
4765 }
4766 }
4767}
4768
506174bf
EH		 4769static void x86_cpu_get_unavailable_features(Object *obj, Visitor *v,
4770 const char *name, void *opaque,
4771 Error **errp)
4772{
4773 X86CPU *xc = X86_CPU(obj);
4774 strList *result = NULL;
4775
4776 x86_cpu_list_feature_names(xc->filtered_features, &result);
4777 visit_type_strList(v, "unavailable-features", &result, errp);
4778}
4779
b54c9377
EH		 4780/* Check for missing features that may prevent the CPU class from
4781 * running using the current machine and accelerator.
4782 */
4783static void x86_cpu_class_check_missing_features(X86CPUClass *xcc,
c3033fd3 4784 strList **list)
b54c9377 4785{
c3033fd3 4786 strList **tail = list;
b54c9377 4787 X86CPU *xc;
b54c9377 4788 Error *err = NULL;
b54c9377 4789
d6dcc558 4790 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) {
c3033fd3 4791 QAPI_LIST_APPEND(tail, g_strdup("kvm"));
b54c9377
EH		 4792 return;
4793 }
4794
3c75e12e 4795 xc = X86_CPU(object_new_with_class(OBJECT_CLASS(xcc)));
b54c9377 4796
b8d834a0 4797 x86_cpu_expand_features(xc, &err);
b54c9377 4798 if (err) {
b8d834a0 4799 /* Errors at x86_cpu_expand_features should never happen,
b54c9377
EH		 4800 * but in case it does, just report the model as not
4801 * runnable at all using the "type" property.
4802 */
c3033fd3 4803 QAPI_LIST_APPEND(tail, g_strdup("type"));
3aa8203e 4804 error_free(err);
b54c9377
EH		 4805 }
4806
245edd0c 4807 x86_cpu_filter_features(xc, false);
b54c9377 4808
c3033fd3 4809 x86_cpu_list_feature_names(xc->filtered_features, tail);
b54c9377
EH		 4810
4811 object_unref(OBJECT(xc));
4812}
4813
8c3329e5 4814/* Print all cpuid feature names in featureset
c6dc6f63 4815 */
0442428a 4816static void listflags(GList *features)
0856579c 4817{
cc643b1e
DB		 4818 size_t len = 0;
4819 GList *tmp;
4820
4821 for (tmp = features; tmp; tmp = tmp->next) {
4822 const char *name = tmp->data;
4823 if ((len + strlen(name) + 1) >= 75) {
0442428a 4824 qemu_printf("\n");
cc643b1e 4825 len = 0;
c6dc6f63 4826 }
0442428a 4827 qemu_printf("%s%s", len == 0 ? " " : " ", name);
cc643b1e 4828 len += strlen(name) + 1;
8c3329e5 4829 }
0442428a 4830 qemu_printf("\n");
c6dc6f63
AP		 4831}
4832
f48c8837 4833/* Sort alphabetically by type name, respecting X86CPUClass::ordering. */
ee465a3e
EH		 4834static gint x86_cpu_list_compare(gconstpointer a, gconstpointer b)
4835{
4836 ObjectClass *class_a = (ObjectClass *)a;
4837 ObjectClass *class_b = (ObjectClass *)b;
4838 X86CPUClass *cc_a = X86_CPU_CLASS(class_a);
4839 X86CPUClass *cc_b = X86_CPU_CLASS(class_b);
c7dbff4b 4840 int ret;
ee465a3e 4841
f48c8837 4842 if (cc_a->ordering != cc_b->ordering) {
c7dbff4b 4843 ret = cc_a->ordering - cc_b->ordering;
ee465a3e 4844 } else {
88703ce2
EH		 4845 g_autofree char *name_a = x86_cpu_class_get_model_name(cc_a);
4846 g_autofree char *name_b = x86_cpu_class_get_model_name(cc_b);
c7dbff4b 4847 ret = strcmp(name_a, name_b);
ee465a3e 4848 }
c7dbff4b 4849 return ret;
ee465a3e
EH		 4850}
4851
4852static GSList *get_sorted_cpu_model_list(void)
4853{
4854 GSList *list = object_class_get_list(TYPE_X86_CPU, false);
4855 list = g_slist_sort(list, x86_cpu_list_compare);
4856 return list;
4857}
4858
164e779c
EH		 4859static char *x86_cpu_class_get_model_id(X86CPUClass *xc)
4860{
3c75e12e 4861 Object *obj = object_new_with_class(OBJECT_CLASS(xc));
164e779c
EH		 4862 char *r = object_property_get_str(obj, "model-id", &error_abort);
4863 object_unref(obj);
4864 return r;
4865}
4866
0788a56b
EH		 4867static char *x86_cpu_class_get_alias_of(X86CPUClass *cc)
4868{
4869 X86CPUVersion version;
4870
4871 if (!cc->model || !cc->model->is_alias) {
4872 return NULL;
4873 }
4874 version = x86_cpu_model_resolve_version(cc->model);
4875 if (version <= 0) {
4876 return NULL;
4877 }
4878 return x86_cpu_versioned_model_name(cc->model->cpudef, version);
4879}
4880
ee465a3e
EH		 4881static void x86_cpu_list_entry(gpointer data, gpointer user_data)
4882{
4883 ObjectClass *oc = data;
4884 X86CPUClass *cc = X86_CPU_CLASS(oc);
88703ce2
EH		 4885 g_autofree char *name = x86_cpu_class_get_model_name(cc);
4886 g_autofree char *desc = g_strdup(cc->model_description);
4887 g_autofree char *alias_of = x86_cpu_class_get_alias_of(cc);
c63938df 4888 g_autofree char *model_id = x86_cpu_class_get_model_id(cc);
164e779c 4889
0788a56b
EH		 4890 if (!desc && alias_of) {
4891 if (cc->model && cc->model->version == CPU_VERSION_AUTO) {
4892 desc = g_strdup("(alias configured by machine type)");
4893 } else {
4894 desc = g_strdup_printf("(alias of %s)", alias_of);
4895 }
4896 }
c63938df
TX		 4897 if (!desc && cc->model && cc->model->note) {
4898 desc = g_strdup_printf("%s [%s]", model_id, cc->model->note);
4899 }
164e779c 4900 if (!desc) {
c63938df 4901 desc = g_strdup_printf("%s", model_id);
ee465a3e
EH		 4902 }
4903
c63938df 4904 qemu_printf("x86 %-20s %-58s\n", name, desc);
ee465a3e
EH		 4905}
4906
4907/* list available CPU models and flags */
0442428a 4908void x86_cpu_list(void)
c6dc6f63 4909{
cc643b1e 4910 int i, j;
ee465a3e 4911 GSList *list;
cc643b1e 4912 GList *names = NULL;
c6dc6f63 4913
0442428a 4914 qemu_printf("Available CPUs:\n");
ee465a3e 4915 list = get_sorted_cpu_model_list();
0442428a 4916 g_slist_foreach(list, x86_cpu_list_entry, NULL);
ee465a3e 4917 g_slist_free(list);
21ad7789 4918
cc643b1e 4919 names = NULL;
3af60be2
JK		 4920 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) {
4921 FeatureWordInfo *fw = &feature_word_info[i];
ede146c2 4922 for (j = 0; j < 64; j++) {
cc643b1e
DB		 4923 if (fw->feat_names[j]) {
4924 names = g_list_append(names, (gpointer)fw->feat_names[j]);
4925 }
4926 }
3af60be2 4927 }
cc643b1e
DB		 4928
4929 names = g_list_sort(names, (GCompareFunc)strcmp);
4930
0442428a
MA		 4931 qemu_printf("\nRecognized CPUID flags:\n");
4932 listflags(names);
4933 qemu_printf("\n");
cc643b1e 4934 g_list_free(names);
c6dc6f63
AP		 4935}
4936
ee465a3e
EH		 4937static void x86_cpu_definition_entry(gpointer data, gpointer user_data)
4938{
4939 ObjectClass *oc = data;
4940 X86CPUClass *cc = X86_CPU_CLASS(oc);
4941 CpuDefinitionInfoList **cpu_list = user_data;
ee465a3e
EH		 4942 CpuDefinitionInfo *info;
4943
4944 info = g_malloc0(sizeof(*info));
4945 info->name = x86_cpu_class_get_model_name(cc);
b54c9377
EH		 4946 x86_cpu_class_check_missing_features(cc, &info->unavailable_features);
4947 info->has_unavailable_features = true;
8ed877b7 4948 info->q_typename = g_strdup(object_class_get_name(oc));
bd72159d
EH		 4949 info->migration_safe = cc->migration_safe;
4950 info->has_migration_safe = true;
5adbed30 4951 info->q_static = cc->static_model;
61ad65d0
RH		 4952 if (cc->model && cc->model->cpudef->deprecation_note) {
4953 info->deprecated = true;
4954 } else {
4955 info->deprecated = false;
4956 }
0788a56b
EH		 4957 /*
4958 * Old machine types won't report aliases, so that alias translation
4959 * doesn't break compatibility with previous QEMU versions.
4960 */
4961 if (default_cpu_version != CPU_VERSION_LEGACY) {
4962 info->alias_of = x86_cpu_class_get_alias_of(cc);
4963 info->has_alias_of = !!info->alias_of;
4964 }
ee465a3e 4965
54aa3de7 4966 QAPI_LIST_PREPEND(*cpu_list, info);
ee465a3e
EH		 4967}
4968
25a9d6ca 4969CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
e3966126
AL		 4970{
4971 CpuDefinitionInfoList *cpu_list = NULL;
ee465a3e
EH		 4972 GSList *list = get_sorted_cpu_model_list();
4973 g_slist_foreach(list, x86_cpu_definition_entry, &cpu_list);
4974 g_slist_free(list);
e3966126
AL		 4975 return cpu_list;
4976}
4977
ede146c2 4978static uint64_t x86_cpu_get_supported_feature_word(FeatureWord w,
84f1b92f 4979 bool migratable_only)
27418adf
EH		 4980{
4981 FeatureWordInfo *wi = &feature_word_info[w];
ede146c2 4982 uint64_t r = 0;
27418adf 4983
fefb41bf 4984 if (kvm_enabled()) {
07585923
RH		 4985 switch (wi->type) {
4986 case CPUID_FEATURE_WORD:
4987 r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid.eax,
4988 wi->cpuid.ecx,
4989 wi->cpuid.reg);
4990 break;
4991 case MSR_FEATURE_WORD:
d86f9636
RH		 4992 r = kvm_arch_get_supported_msr_feature(kvm_state,
4993 wi->msr.index);
07585923
RH		 4994 break;
4995 }
d6dcc558 4996 } else if (hvf_enabled()) {
07585923
RH		 4997 if (wi->type != CPUID_FEATURE_WORD) {
4998 return 0;
4999 }
5000 r = hvf_get_supported_cpuid(wi->cpuid.eax,
5001 wi->cpuid.ecx,
5002 wi->cpuid.reg);
fefb41bf 5003 } else if (tcg_enabled()) {
84f1b92f 5004 r = wi->tcg_features;
fefb41bf
EH		 5005 } else {
5006 return ~0;
5007 }
5ea9e9e2
PB		 5008#ifndef TARGET_X86_64
5009 if (w == FEAT_8000_0001_EDX) {
5010 r &= ~CPUID_EXT2_LM;
5011 }
5012#endif
84f1b92f
EH		 5013 if (migratable_only) {
5014 r &= x86_cpu_get_migratable_flags(w);
5015 }
5016 return r;
27418adf
EH		 5017}
5018
f5cc5a5c 5019void x86_cpu_apply_props(X86CPU *cpu, PropValue *props)
5114e842
EH		 5020{
5021 PropValue *pv;
5022 for (pv = props; pv->prop; pv++) {
5023 if (!pv->value) {
5024 continue;
5025 }
5325cc34 5026 object_property_parse(OBJECT(cpu), pv->prop, pv->value,
5114e842
EH		 5027 &error_abort);
5028 }
5029}
5030
dcafd1ef
EH		 5031/* Apply properties for the CPU model version specified in model */
5032static void x86_cpu_apply_version_props(X86CPU *cpu, X86CPUModel *model)
5033{
5034 const X86CPUVersionDefinition *vdef;
5035 X86CPUVersion version = x86_cpu_model_resolve_version(model);
5036
5037 if (version == CPU_VERSION_LEGACY) {
5038 return;
5039 }
5040
5041 for (vdef = x86_cpu_def_get_versions(model->cpudef); vdef->version; vdef++) {
5042 PropValue *p;
5043
5044 for (p = vdef->props; p && p->prop; p++) {
5325cc34 5045 object_property_parse(OBJECT(cpu), p->prop, p->value,
dcafd1ef
EH		 5046 &error_abort);
5047 }
5048
5049 if (vdef->version == version) {
5050 break;
5051 }
5052 }
5053
5054 /*
5055 * If we reached the end of the list, version number was invalid
5056 */
5057 assert(vdef->version == version);
5058}
5059
f99fd7ca 5060/* Load data from X86CPUDefinition into a X86CPU object
c080e30e 5061 */
49e2fa85 5062static void x86_cpu_load_model(X86CPU *cpu, X86CPUModel *model)
c6dc6f63 5063{
dcafd1ef 5064 X86CPUDefinition *def = model->cpudef;
61dcd775 5065 CPUX86State *env = &cpu->env;
e1c224b4 5066 FeatureWord w;
c6dc6f63 5067
f99fd7ca
EH		 5068 /*NOTE: any property set by this function should be returned by
5069 * x86_cpu_static_props(), so static expansion of
5070 * query-cpu-model-expansion is always complete.
5071 */
5072
c39c0edf 5073 /* CPU models only set _minimum_ values for level/xlevel: */
5325cc34 5074 object_property_set_uint(OBJECT(cpu), "min-level", def->level,
49e2fa85 5075 &error_abort);
5325cc34 5076 object_property_set_uint(OBJECT(cpu), "min-xlevel", def->xlevel,
49e2fa85
MA		 5077 &error_abort);
5078
5325cc34
MA		 5079 object_property_set_int(OBJECT(cpu), "family", def->family, &error_abort);
5080 object_property_set_int(OBJECT(cpu), "model", def->model, &error_abort);
5081 object_property_set_int(OBJECT(cpu), "stepping", def->stepping,
49e2fa85 5082 &error_abort);
5325cc34 5083 object_property_set_str(OBJECT(cpu), "model-id", def->model_id,
49e2fa85 5084 &error_abort);
e1c224b4
EH		 5085 for (w = 0; w < FEATURE_WORDS; w++) {
5086 env->features[w] = def->features[w];
5087 }
82beb536 5088
a9f27ea9
EH		 5089 /* legacy-cache defaults to 'off' if CPU model provides cache info */
5090 cpu->legacy_cache = !def->cache_info;
ab8f992e 5091
82beb536 5092 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR;
7c08db30
EH		 5093
5094 /* sysenter isn't supported in compatibility mode on AMD,
5095 * syscall isn't supported in compatibility mode on Intel.
5096 * Normally we advertise the actual CPU vendor, but you can
5097 * override this using the 'vendor' property if you want to use
5098 * KVM's sysenter/syscall emulation in compatibility mode and
5099 * when doing cross vendor migration
5100 */
7c08db30 5101
f5cc5a5c
CF		 5102 /*
5103 * vendor property is set here but then overloaded with the
5104 * host cpu vendor for KVM and HVF.
5105 */
5106 object_property_set_str(OBJECT(cpu), "vendor", def->vendor, &error_abort);
7c08db30 5107
dcafd1ef 5108 x86_cpu_apply_version_props(cpu, model);
1f43671a
XL		 5109
5110 /*
5111 * Properties in versioned CPU model are not user specified features.
5112 * We can simply clear env->user_features here since it will be filled later
5113 * in x86_cpu_expand_features() based on plus_features and minus_features.
5114 */
5115 memset(&env->user_features, 0, sizeof(env->user_features));
c6dc6f63
AP		 5116}
5117
00fcd100
AB		 5118static gchar *x86_gdb_arch_name(CPUState *cs)
5119{
5120#ifdef TARGET_X86_64
5121 return g_strdup("i386:x86-64");
5122#else
5123 return g_strdup("i386");
5124#endif
5125}
5126
d940ee9b
EH		 5127static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data)
5128{
dcafd1ef 5129 X86CPUModel *model = data;
d940ee9b 5130 X86CPUClass *xcc = X86_CPU_CLASS(oc);
61ad65d0 5131 CPUClass *cc = CPU_CLASS(oc);
d940ee9b 5132
dcafd1ef 5133 xcc->model = model;
bd72159d 5134 xcc->migration_safe = true;
61ad65d0 5135 cc->deprecation_note = model->cpudef->deprecation_note;
d940ee9b
EH		 5136}
5137
dcafd1ef 5138static void x86_register_cpu_model_type(const char *name, X86CPUModel *model)
d940ee9b 5139{
88703ce2 5140 g_autofree char *typename = x86_cpu_type_name(name);
d940ee9b
EH		 5141 TypeInfo ti = {
5142 .name = typename,
5143 .parent = TYPE_X86_CPU,
5144 .class_init = x86_cpu_cpudef_class_init,
dcafd1ef 5145 .class_data = model,
d940ee9b
EH		 5146 };
5147
dcafd1ef 5148 type_register(&ti);
dcafd1ef
EH		 5149}
5150
5151static void x86_register_cpudef_types(X86CPUDefinition *def)
5152{
5153 X86CPUModel *m;
5154 const X86CPUVersionDefinition *vdef;
dcafd1ef 5155
2a923a29
EH		 5156 /* AMD aliases are handled at runtime based on CPUID vendor, so
5157 * they shouldn't be set on the CPU model table.
5158 */
5159 assert(!(def->features[FEAT_8000_0001_EDX] & CPUID_EXT2_AMD_ALIASES));
807e9869
EH		 5160 /* catch mistakes instead of silently truncating model_id when too long */
5161 assert(def->model_id && strlen(def->model_id) <= 48);
5162
dcafd1ef
EH		 5163 /* Unversioned model: */
5164 m = g_new0(X86CPUModel, 1);
5165 m->cpudef = def;
0788a56b
EH		 5166 m->version = CPU_VERSION_AUTO;
5167 m->is_alias = true;
dcafd1ef
EH		 5168 x86_register_cpu_model_type(def->name, m);
5169
5170 /* Versioned models: */
5171
5172 for (vdef = x86_cpu_def_get_versions(def); vdef->version; vdef++) {
5173 X86CPUModel *m = g_new0(X86CPUModel, 1);
88703ce2
EH		 5174 g_autofree char *name =
5175 x86_cpu_versioned_model_name(def, vdef->version);
dcafd1ef
EH		 5176 m->cpudef = def;
5177 m->version = vdef->version;
c63938df 5178 m->note = vdef->note;
dcafd1ef 5179 x86_register_cpu_model_type(name, m);
53db89d9
EH		 5180
5181 if (vdef->alias) {
5182 X86CPUModel *am = g_new0(X86CPUModel, 1);
5183 am->cpudef = def;
5184 am->version = vdef->version;
0788a56b 5185 am->is_alias = true;
53db89d9
EH		 5186 x86_register_cpu_model_type(vdef->alias, am);
5187 }
dcafd1ef 5188 }
2a923a29 5189
d940ee9b
EH		 5190}
5191
c6dc6f63
AP		 5192void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
5193 uint32_t *eax, uint32_t *ebx,
5194 uint32_t *ecx, uint32_t *edx)
5195{
6aa9e42f
RH		 5196 X86CPU *cpu = env_archcpu(env);
5197 CPUState *cs = env_cpu(env);
d65af288 5198 uint32_t die_offset;
4ed3d478 5199 uint32_t limit;
1ce36bfe 5200 uint32_t signature[3];
f20dec0b
BM		 5201 X86CPUTopoInfo topo_info;
5202
5203 topo_info.dies_per_pkg = env->nr_dies;
5204 topo_info.cores_per_die = cs->nr_cores;
5205 topo_info.threads_per_core = cs->nr_threads;
a60f24b5 5206
4ed3d478
DB		 5207 /* Calculate & apply limits for different index ranges */
5208 if (index >= 0xC0000000) {
5209 limit = env->cpuid_xlevel2;
5210 } else if (index >= 0x80000000) {
5211 limit = env->cpuid_xlevel;
1ce36bfe
DB		 5212 } else if (index >= 0x40000000) {
5213 limit = 0x40000001;
c6dc6f63 5214 } else {
4ed3d478
DB		 5215 limit = env->cpuid_level;
5216 }
5217
5218 if (index > limit) {
5219 /* Intel documentation states that invalid EAX input will
5220 * return the same information as EAX=cpuid_level
5221 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
5222 */
5223 index = env->cpuid_level;
c6dc6f63
AP		 5224 }
5225
5226 switch(index) {
5227 case 0:
5228 *eax = env->cpuid_level;
5eb2f7a4
EH		 5229 *ebx = env->cpuid_vendor1;
5230 *edx = env->cpuid_vendor2;
5231 *ecx = env->cpuid_vendor3;
c6dc6f63
AP		 5232 break;
5233 case 1:
5234 *eax = env->cpuid_version;
7e72a45c
EH		 5235 *ebx = (cpu->apic_id << 24) |
5236 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
0514ef2f 5237 *ecx = env->features[FEAT_1_ECX];
19dc85db
RH		 5238 if ((*ecx & CPUID_EXT_XSAVE) && (env->cr[4] & CR4_OSXSAVE_MASK)) {
5239 *ecx |= CPUID_EXT_OSXSAVE;
5240 }
0514ef2f 5241 *edx = env->features[FEAT_1_EDX];
ce3960eb
AF		 5242 if (cs->nr_cores * cs->nr_threads > 1) {
5243 *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
19dc85db 5244 *edx |= CPUID_HT;
c6dc6f63 5245 }
ea39f9b6
LX		 5246 if (!cpu->enable_pmu) {
5247 *ecx &= ~CPUID_EXT_PDCM;
5248 }
c6dc6f63
AP		 5249 break;
5250 case 2:
5251 /* cache info: needed for Pentium Pro compatibility */
787aaf57
BC		 5252 if (cpu->cache_info_passthrough) {
5253 host_cpuid(index, 0, eax, ebx, ecx, edx);
5254 break;
5255 }
5e891bf8 5256 *eax = 1; /* Number of CPUID[EAX=2] calls required */
c6dc6f63 5257 *ebx = 0;
14c985cf
LM		 5258 if (!cpu->enable_l3_cache) {
5259 *ecx = 0;
5260 } else {
a9f27ea9 5261 *ecx = cpuid2_cache_descriptor(env->cache_info_cpuid2.l3_cache);
14c985cf 5262 }
a9f27ea9
EH		 5263 *edx = (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1d_cache) << 16) |
5264 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1i_cache) << 8) |
5265 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l2_cache));
c6dc6f63
AP		 5266 break;
5267 case 4:
5268 /* cache info: needed for Core compatibility */
787aaf57
BC		 5269 if (cpu->cache_info_passthrough) {
5270 host_cpuid(index, count, eax, ebx, ecx, edx);
7e3482f8 5271 /* QEMU gives out its own APIC IDs, never pass down bits 31..26. */
76c2975a 5272 *eax &= ~0xFC000000;
7e3482f8
EH		 5273 if ((*eax & 31) && cs->nr_cores > 1) {
5274 *eax |= (cs->nr_cores - 1) << 26;
5275 }
c6dc6f63 5276 } else {
2f7a21c4 5277 *eax = 0;
76c2975a 5278 switch (count) {
c6dc6f63 5279 case 0: /* L1 dcache info */
a9f27ea9
EH		 5280 encode_cache_cpuid4(env->cache_info_cpuid4.l1d_cache,
5281 1, cs->nr_cores,
7e3482f8 5282 eax, ebx, ecx, edx);
c6dc6f63
AP		 5283 break;
5284 case 1: /* L1 icache info */
a9f27ea9
EH		 5285 encode_cache_cpuid4(env->cache_info_cpuid4.l1i_cache,
5286 1, cs->nr_cores,
7e3482f8 5287 eax, ebx, ecx, edx);
c6dc6f63
AP		 5288 break;
5289 case 2: /* L2 cache info */
a9f27ea9
EH		 5290 encode_cache_cpuid4(env->cache_info_cpuid4.l2_cache,
5291 cs->nr_threads, cs->nr_cores,
7e3482f8 5292 eax, ebx, ecx, edx);
c6dc6f63 5293 break;
14c985cf 5294 case 3: /* L3 cache info */
f20dec0b 5295 die_offset = apicid_die_offset(&topo_info);
7e3482f8 5296 if (cpu->enable_l3_cache) {
a9f27ea9 5297 encode_cache_cpuid4(env->cache_info_cpuid4.l3_cache,
d65af288 5298 (1 << die_offset), cs->nr_cores,
7e3482f8 5299 eax, ebx, ecx, edx);
14c985cf
LM		 5300 break;
5301 }
7e3482f8 5302 /* fall through */
c6dc6f63 5303 default: /* end of info */
7e3482f8 5304 *eax = *ebx = *ecx = *edx = 0;
c6dc6f63 5305 break;
76c2975a
PB		 5306 }
5307 }
c6dc6f63
AP		 5308 break;
5309 case 5:
2266d443
MT		 5310 /* MONITOR/MWAIT Leaf */
5311 *eax = cpu->mwait.eax; /* Smallest monitor-line size in bytes */
5312 *ebx = cpu->mwait.ebx; /* Largest monitor-line size in bytes */
5313 *ecx = cpu->mwait.ecx; /* flags */
5314 *edx = cpu->mwait.edx; /* mwait substates */
c6dc6f63
AP		 5315 break;
5316 case 6:
5317 /* Thermal and Power Leaf */
28b8e4d0 5318 *eax = env->features[FEAT_6_EAX];
c6dc6f63
AP		 5319 *ebx = 0;
5320 *ecx = 0;
5321 *edx = 0;
5322 break;
f7911686 5323 case 7:
13526728
EH		 5324 /* Structured Extended Feature Flags Enumeration Leaf */
5325 if (count == 0) {
80db491d
JL		 5326 /* Maximum ECX value for sub-leaves */
5327 *eax = env->cpuid_level_func7;
0514ef2f 5328 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */
f74eefe0 5329 *ecx = env->features[FEAT_7_0_ECX]; /* Feature flags */
0f70ed47
PB		 5330 if ((*ecx & CPUID_7_0_ECX_PKU) && env->cr[4] & CR4_PKE_MASK) {
5331 *ecx |= CPUID_7_0_ECX_OSPKE;
5332 }
95ea69fb 5333 *edx = env->features[FEAT_7_0_EDX]; /* Feature flags */
80db491d
JL		 5334 } else if (count == 1) {
5335 *eax = env->features[FEAT_7_1_EAX];
5336 *ebx = 0;
5337 *ecx = 0;
5338 *edx = 0;
f7911686
YW		 5339 } else {
5340 *eax = 0;
5341 *ebx = 0;
5342 *ecx = 0;
5343 *edx = 0;
5344 }
5345 break;
c6dc6f63
AP		 5346 case 9:
5347 /* Direct Cache Access Information Leaf */
5348 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
5349 *ebx = 0;
5350 *ecx = 0;
5351 *edx = 0;
5352 break;
5353 case 0xA:
5354 /* Architectural Performance Monitoring Leaf */
9337e3b6 5355 if (kvm_enabled() && cpu->enable_pmu) {
a60f24b5 5356 KVMState *s = cs->kvm_state;
a0fa8208
GN		 5357
5358 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
5359 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
5360 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
5361 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
d6dcc558
SAGDR		 5362 } else if (hvf_enabled() && cpu->enable_pmu) {
5363 *eax = hvf_get_supported_cpuid(0xA, count, R_EAX);
5364 *ebx = hvf_get_supported_cpuid(0xA, count, R_EBX);
5365 *ecx = hvf_get_supported_cpuid(0xA, count, R_ECX);
5366 *edx = hvf_get_supported_cpuid(0xA, count, R_EDX);
a0fa8208
GN		 5367 } else {
5368 *eax = 0;
5369 *ebx = 0;
5370 *ecx = 0;
5371 *edx = 0;
5372 }
c6dc6f63 5373 break;
5232d00a
RK		 5374 case 0xB:
5375 /* Extended Topology Enumeration Leaf */
5376 if (!cpu->enable_cpuid_0xb) {
5377 *eax = *ebx = *ecx = *edx = 0;
5378 break;
5379 }
5380
5381 *ecx = count & 0xff;
5382 *edx = cpu->apic_id;
5383
5384 switch (count) {
5385 case 0:
f20dec0b 5386 *eax = apicid_core_offset(&topo_info);
eab60fb9 5387 *ebx = cs->nr_threads;
5232d00a
RK		 5388 *ecx |= CPUID_TOPOLOGY_LEVEL_SMT;
5389 break;
5390 case 1:
fb49865d 5391 *eax = apicid_pkg_offset(&topo_info);
eab60fb9 5392 *ebx = cs->nr_cores * cs->nr_threads;
5232d00a
RK		 5393 *ecx |= CPUID_TOPOLOGY_LEVEL_CORE;
5394 break;
5395 default:
5396 *eax = 0;
5397 *ebx = 0;
5398 *ecx |= CPUID_TOPOLOGY_LEVEL_INVALID;
5399 }
5400
a94e1428
LX		 5401 assert(!(*eax & ~0x1f));
5402 *ebx &= 0xffff; /* The count doesn't need to be reliable. */
5403 break;
5404 case 0x1F:
5405 /* V2 Extended Topology Enumeration Leaf */
5406 if (env->nr_dies < 2) {
5407 *eax = *ebx = *ecx = *edx = 0;
5408 break;
5409 }
5410
5411 *ecx = count & 0xff;
5412 *edx = cpu->apic_id;
5413 switch (count) {
5414 case 0:
f20dec0b 5415 *eax = apicid_core_offset(&topo_info);
a94e1428
LX		 5416 *ebx = cs->nr_threads;
5417 *ecx |= CPUID_TOPOLOGY_LEVEL_SMT;
5418 break;
5419 case 1:
f20dec0b 5420 *eax = apicid_die_offset(&topo_info);
a94e1428
LX		 5421 *ebx = cs->nr_cores * cs->nr_threads;
5422 *ecx |= CPUID_TOPOLOGY_LEVEL_CORE;
5423 break;
5424 case 2:
fb49865d 5425 *eax = apicid_pkg_offset(&topo_info);
a94e1428
LX		 5426 *ebx = env->nr_dies * cs->nr_cores * cs->nr_threads;
5427 *ecx |= CPUID_TOPOLOGY_LEVEL_DIE;
5428 break;
5429 default:
5430 *eax = 0;
5431 *ebx = 0;
5432 *ecx |= CPUID_TOPOLOGY_LEVEL_INVALID;
5433 }
5232d00a
RK		 5434 assert(!(*eax & ~0x1f));
5435 *ebx &= 0xffff; /* The count doesn't need to be reliable. */
5436 break;
2560f19f 5437 case 0xD: {
51e49430 5438 /* Processor Extended State */
2560f19f
PB		 5439 *eax = 0;
5440 *ebx = 0;
5441 *ecx = 0;
5442 *edx = 0;
19dc85db 5443 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
51e49430
SY		 5444 break;
5445 }
4928cd6d 5446
2560f19f 5447 if (count == 0) {
96193c22
EH		 5448 *ecx = xsave_area_size(x86_cpu_xsave_components(cpu));
5449 *eax = env->features[FEAT_XSAVE_COMP_LO];
5450 *edx = env->features[FEAT_XSAVE_COMP_HI];
76ecd7a5
BS		 5451 /*
5452 * The initial value of xcr0 and ebx == 0, On host without kvm
5453 * commit 412a3c41(e.g., CentOS 6), the ebx's value always == 0
5454 * even through guest update xcr0, this will crash some legacy guest
5455 * (e.g., CentOS 6), So set ebx == ecx to workaroud it.
5456 */
5457 *ebx = kvm_enabled() ? *ecx : xsave_area_size(env->xcr0);
2560f19f 5458 } else if (count == 1) {
0bb0b2d2 5459 *eax = env->features[FEAT_XSAVE];
f4f1110e 5460 } else if (count < ARRAY_SIZE(x86_ext_save_areas)) {
96193c22
EH		 5461 if ((x86_cpu_xsave_components(cpu) >> count) & 1) {
5462 const ExtSaveArea *esa = &x86_ext_save_areas[count];
33f373d7
LJ		 5463 *eax = esa->size;
5464 *ebx = esa->offset;
2560f19f 5465 }
51e49430
SY		 5466 }
5467 break;
2560f19f 5468 }
e37a5c7f
CP		 5469 case 0x14: {
5470 /* Intel Processor Trace Enumeration */
5471 *eax = 0;
5472 *ebx = 0;
5473 *ecx = 0;
5474 *edx = 0;
5475 if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) ||
5476 !kvm_enabled()) {
5477 break;
5478 }
5479
5480 if (count == 0) {
5481 *eax = INTEL_PT_MAX_SUBLEAF;
5482 *ebx = INTEL_PT_MINIMAL_EBX;
5483 *ecx = INTEL_PT_MINIMAL_ECX;
d1615ea5
LK		 5484 if (env->features[FEAT_14_0_ECX] & CPUID_14_0_ECX_LIP) {
5485 *ecx |= CPUID_14_0_ECX_LIP;
5486 }
e37a5c7f
CP		 5487 } else if (count == 1) {
5488 *eax = INTEL_PT_MTC_BITMAP | INTEL_PT_ADDR_RANGES_NUM;
5489 *ebx = INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP;
5490 }
5491 break;
5492 }
1ce36bfe
DB		 5493 case 0x40000000:
5494 /*
5495 * CPUID code in kvm_arch_init_vcpu() ignores stuff
5496 * set here, but we restrict to TCG none the less.
5497 */
5498 if (tcg_enabled() && cpu->expose_tcg) {
5499 memcpy(signature, "TCGTCGTCGTCG", 12);
5500 *eax = 0x40000001;
5501 *ebx = signature[0];
5502 *ecx = signature[1];
5503 *edx = signature[2];
5504 } else {
5505 *eax = 0;
5506 *ebx = 0;
5507 *ecx = 0;
5508 *edx = 0;
5509 }
5510 break;
5511 case 0x40000001:
5512 *eax = 0;
5513 *ebx = 0;
5514 *ecx = 0;
5515 *edx = 0;
5516 break;
c6dc6f63
AP		 5517 case 0x80000000:
5518 *eax = env->cpuid_xlevel;
5519 *ebx = env->cpuid_vendor1;
5520 *edx = env->cpuid_vendor2;
5521 *ecx = env->cpuid_vendor3;
5522 break;
5523 case 0x80000001:
5524 *eax = env->cpuid_version;
5525 *ebx = 0;
0514ef2f
EH		 5526 *ecx = env->features[FEAT_8000_0001_ECX];
5527 *edx = env->features[FEAT_8000_0001_EDX];
c6dc6f63
AP		 5528
5529 /* The Linux kernel checks for the CMPLegacy bit and
5530 * discards multiple thread information if it is set.
cb8d4c8f 5531 * So don't set it here for Intel to make Linux guests happy.
c6dc6f63 5532 */
ce3960eb 5533 if (cs->nr_cores * cs->nr_threads > 1) {
5eb2f7a4
EH		 5534 if (env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1 ||
5535 env->cpuid_vendor2 != CPUID_VENDOR_INTEL_2 ||
5536 env->cpuid_vendor3 != CPUID_VENDOR_INTEL_3) {
c6dc6f63
AP		 5537 *ecx |= 1 << 1; /* CmpLegacy bit */
5538 }
5539 }
c6dc6f63
AP		 5540 break;
5541 case 0x80000002:
5542 case 0x80000003:
5543 case 0x80000004:
5544 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
5545 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
5546 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
5547 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
5548 break;
5549 case 0x80000005:
5550 /* cache info (L1 cache) */
787aaf57
BC		 5551 if (cpu->cache_info_passthrough) {
5552 host_cpuid(index, 0, eax, ebx, ecx, edx);
5553 break;
5554 }
78ee6bd0 5555 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) |
5e891bf8 5556 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES);
78ee6bd0 5557 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) |
5e891bf8 5558 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES);
a9f27ea9
EH		 5559 *ecx = encode_cache_cpuid80000005(env->cache_info_amd.l1d_cache);
5560 *edx = encode_cache_cpuid80000005(env->cache_info_amd.l1i_cache);
c6dc6f63
AP		 5561 break;
5562 case 0x80000006:
5563 /* cache info (L2 cache) */
787aaf57
BC		 5564 if (cpu->cache_info_passthrough) {
5565 host_cpuid(index, 0, eax, ebx, ecx, edx);
5566 break;
5567 }
78ee6bd0
PMD		 5568 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) |
5569 (L2_DTLB_2M_ENTRIES << 16) |
5570 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) |
5e891bf8 5571 (L2_ITLB_2M_ENTRIES);
78ee6bd0
PMD		 5572 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) |
5573 (L2_DTLB_4K_ENTRIES << 16) |
5574 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) |
5e891bf8 5575 (L2_ITLB_4K_ENTRIES);
a9f27ea9
EH		 5576 encode_cache_cpuid80000006(env->cache_info_amd.l2_cache,
5577 cpu->enable_l3_cache ?
5578 env->cache_info_amd.l3_cache : NULL,
5579 ecx, edx);
c6dc6f63 5580 break;
303752a9
MT		 5581 case 0x80000007:
5582 *eax = 0;
5583 *ebx = 0;
5584 *ecx = 0;
5585 *edx = env->features[FEAT_8000_0007_EDX];
5586 break;
c6dc6f63
AP		 5587 case 0x80000008:
5588 /* virtual & phys address size in low 2 bytes. */
0514ef2f 5589 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
6c7c3c21
KS		 5590 /* 64 bit processor */
5591 *eax = cpu->phys_bits; /* configurable physical bits */
5592 if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_LA57) {
5593 *eax |= 0x00003900; /* 57 bits virtual */
5594 } else {
5595 *eax |= 0x00003000; /* 48 bits virtual */
5596 }
c6dc6f63 5597 } else {
af45907a 5598 *eax = cpu->phys_bits;
c6dc6f63 5599 }
1b3420e1 5600 *ebx = env->features[FEAT_8000_0008_EBX];
ce3960eb 5601 if (cs->nr_cores * cs->nr_threads > 1) {
cac9edfc
BM		 5602 /*
5603 * Bits 15:12 is "The number of bits in the initial
5604 * Core::X86::Apic::ApicId[ApicId] value that indicate
fb49865d 5605 * thread ID within a package".
cac9edfc
BM		 5606 * Bits 7:0 is "The number of threads in the package is NC+1"
5607 */
fb49865d 5608 *ecx = (apicid_pkg_offset(&topo_info) << 12) |
cac9edfc
BM		 5609 ((cs->nr_cores * cs->nr_threads) - 1);
5610 } else {
5611 *ecx = 0;
c6dc6f63 5612 }
cac9edfc 5613 *edx = 0;
c6dc6f63
AP		 5614 break;
5615 case 0x8000000A:
0514ef2f 5616 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
9f3fb565
EH		 5617 *eax = 0x00000001; /* SVM Revision */
5618 *ebx = 0x00000010; /* nr of ASIDs */
5619 *ecx = 0;
0514ef2f 5620 *edx = env->features[FEAT_SVM]; /* optional features */
9f3fb565
EH		 5621 } else {
5622 *eax = 0;
5623 *ebx = 0;
5624 *ecx = 0;
5625 *edx = 0;
5626 }
c6dc6f63 5627 break;
8f4202fb
BM		 5628 case 0x8000001D:
5629 *eax = 0;
a4e0b436
SL		 5630 if (cpu->cache_info_passthrough) {
5631 host_cpuid(index, count, eax, ebx, ecx, edx);
5632 break;
5633 }
8f4202fb
BM		 5634 switch (count) {
5635 case 0: /* L1 dcache info */
2f084d1e
BM		 5636 encode_cache_cpuid8000001d(env->cache_info_amd.l1d_cache,
5637 &topo_info, eax, ebx, ecx, edx);
8f4202fb
BM		 5638 break;
5639 case 1: /* L1 icache info */
2f084d1e
BM		 5640 encode_cache_cpuid8000001d(env->cache_info_amd.l1i_cache,
5641 &topo_info, eax, ebx, ecx, edx);
8f4202fb
BM		 5642 break;
5643 case 2: /* L2 cache info */
2f084d1e
BM		 5644 encode_cache_cpuid8000001d(env->cache_info_amd.l2_cache,
5645 &topo_info, eax, ebx, ecx, edx);
8f4202fb
BM		 5646 break;
5647 case 3: /* L3 cache info */
2f084d1e
BM		 5648 encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache,
5649 &topo_info, eax, ebx, ecx, edx);
8f4202fb
BM		 5650 break;
5651 default: /* end of info */
5652 *eax = *ebx = *ecx = *edx = 0;
5653 break;
5654 }
5655 break;
ed78467a 5656 case 0x8000001E:
35ac5dfb
BM		 5657 if (cpu->core_id <= 255) {
5658 encode_topo_cpuid8000001e(cpu, &topo_info, eax, ebx, ecx, edx);
5659 } else {
5660 *eax = 0;
5661 *ebx = 0;
5662 *ecx = 0;
5663 *edx = 0;
5664 }
ed78467a 5665 break;
b3baa152
BW		 5666 case 0xC0000000:
5667 *eax = env->cpuid_xlevel2;
5668 *ebx = 0;
5669 *ecx = 0;
5670 *edx = 0;
5671 break;
5672 case 0xC0000001:
5673 /* Support for VIA CPU's CPUID instruction */
5674 *eax = env->cpuid_version;
5675 *ebx = 0;
5676 *ecx = 0;
0514ef2f 5677 *edx = env->features[FEAT_C000_0001_EDX];
b3baa152
BW		 5678 break;
5679 case 0xC0000002:
5680 case 0xC0000003:
5681 case 0xC0000004:
5682 /* Reserved for the future, and now filled with zero */
5683 *eax = 0;
5684 *ebx = 0;
5685 *ecx = 0;
5686 *edx = 0;
5687 break;
6cb8f2a6
BS		 5688 case 0x8000001F:
5689 *eax = sev_enabled() ? 0x2 : 0;
6b98e96f 5690 *eax |= sev_es_enabled() ? 0x8 : 0;
6cb8f2a6
BS		 5691 *ebx = sev_get_cbit_position();
5692 *ebx |= sev_get_reduced_phys_bits() << 6;
5693 *ecx = 0;
5694 *edx = 0;
5695 break;
c6dc6f63
AP		 5696 default:
5697 /* reserved values: zero */
5698 *eax = 0;
5699 *ebx = 0;
5700 *ecx = 0;
5701 *edx = 0;
5702 break;
5703 }
5704}
5fd2087a 5705
781c67ca 5706static void x86_cpu_reset(DeviceState *dev)
5fd2087a 5707{
781c67ca 5708 CPUState *s = CPU(dev);
5fd2087a
AF		 5709 X86CPU *cpu = X86_CPU(s);
5710 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
5711 CPUX86State *env = &cpu->env;
a114d25d
RH		 5712 target_ulong cr4;
5713 uint64_t xcr0;
c1958aea
AF		 5714 int i;
5715
781c67ca 5716 xcc->parent_reset(dev);
5fd2087a 5717
5e992a8e 5718 memset(env, 0, offsetof(CPUX86State, end_reset_fields));
c1958aea 5719
c1958aea
AF		 5720 env->old_exception = -1;
5721
5722 /* init to reset state */
5723
c1958aea 5724 env->hflags2 |= HF2_GIF_MASK;
b16c0e20 5725 env->hflags &= ~HF_GUEST_MASK;
c1958aea
AF		 5726
5727 cpu_x86_update_cr0(env, 0x60000010);
5728 env->a20_mask = ~0x0;
5729 env->smbase = 0x30000;
e13713db 5730 env->msr_smi_count = 0;
c1958aea
AF		 5731
5732 env->idt.limit = 0xffff;
5733 env->gdt.limit = 0xffff;
5734 env->ldt.limit = 0xffff;
5735 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
5736 env->tr.limit = 0xffff;
5737 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
5738
5739 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
5740 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
5741 DESC_R_MASK | DESC_A_MASK);
5742 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
5743 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
5744 DESC_A_MASK);
5745 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
5746 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
5747 DESC_A_MASK);
5748 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
5749 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
5750 DESC_A_MASK);
5751 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
5752 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
5753 DESC_A_MASK);
5754 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
5755 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
5756 DESC_A_MASK);
5757
5758 env->eip = 0xfff0;
5759 env->regs[R_EDX] = env->cpuid_version;
5760
5761 env->eflags = 0x2;
5762
5763 /* FPU init */
5764 for (i = 0; i < 8; i++) {
5765 env->fptags[i] = 1;
5766 }
5bde1407 5767 cpu_set_fpuc(env, 0x37f);
c1958aea
AF		 5768
5769 env->mxcsr = 0x1f80;
a114d25d
RH		 5770 /* All units are in INIT state. */
5771 env->xstate_bv = 0;
c1958aea
AF		 5772
5773 env->pat = 0x0007040600070406ULL;
5774 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
4cfd7bab
WL		 5775 if (env->features[FEAT_1_ECX] & CPUID_EXT_MONITOR) {
5776 env->msr_ia32_misc_enable |= MSR_IA32_MISC_ENABLE_MWAIT;
5777 }
c1958aea
AF		 5778
5779 memset(env->dr, 0, sizeof(env->dr));
5780 env->dr[6] = DR6_FIXED_1;
5781 env->dr[7] = DR7_FIXED_1;
b3310ab3 5782 cpu_breakpoint_remove_all(s, BP_CPU);
75a34036 5783 cpu_watchpoint_remove_all(s, BP_CPU);
dd673288 5784
a114d25d 5785 cr4 = 0;
cfc3b074 5786 xcr0 = XSTATE_FP_MASK;
a114d25d
RH		 5787
5788#ifdef CONFIG_USER_ONLY
5789 /* Enable all the features for user-mode. */
5790 if (env->features[FEAT_1_EDX] & CPUID_SSE) {
cfc3b074 5791 xcr0 |= XSTATE_SSE_MASK;
a114d25d 5792 }
0f70ed47
PB		 5793 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
5794 const ExtSaveArea *esa = &x86_ext_save_areas[i];
9646f492 5795 if (env->features[esa->feature] & esa->bits) {
0f70ed47
PB		 5796 xcr0 |= 1ull << i;
5797 }
a114d25d 5798 }
0f70ed47 5799
a114d25d
RH		 5800 if (env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) {
5801 cr4 |= CR4_OSFXSR_MASK | CR4_OSXSAVE_MASK;
5802 }
07929f2a
RH		 5803 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE) {
5804 cr4 |= CR4_FSGSBASE_MASK;
5805 }
a114d25d
RH		 5806#endif
5807
5808 env->xcr0 = xcr0;
5809 cpu_x86_update_cr4(env, cr4);
0522604b 5810
9db2efd9
AW		 5811 /*
5812 * SDM 11.11.5 requires:
5813 * - IA32_MTRR_DEF_TYPE MSR.E = 0
5814 * - IA32_MTRR_PHYSMASKn.V = 0
5815 * All other bits are undefined. For simplification, zero it all.
5816 */
5817 env->mtrr_deftype = 0;
5818 memset(env->mtrr_var, 0, sizeof(env->mtrr_var));
5819 memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed));
5820
b7394c83 5821 env->interrupt_injected = -1;
fd13f23b
LA		 5822 env->exception_nr = -1;
5823 env->exception_pending = 0;
5824 env->exception_injected = 0;
5825 env->exception_has_payload = false;
5826 env->exception_payload = 0;
b7394c83 5827 env->nmi_injected = false;
dd673288
IM		 5828#if !defined(CONFIG_USER_ONLY)
5829 /* We hard-wire the BSP to the first CPU. */
9cb11fd7 5830 apic_designate_bsp(cpu->apic_state, s->cpu_index == 0);
dd673288 5831
259186a7 5832 s->halted = !cpu_is_bsp(cpu);
50a2c6e5
PB		 5833
5834 if (kvm_enabled()) {
5835 kvm_arch_reset_vcpu(cpu);
5836 }
dd673288 5837#endif
5fd2087a
AF		 5838}
5839
de024815
AF		 5840static void mce_init(X86CPU *cpu)
5841{
5842 CPUX86State *cenv = &cpu->env;
5843 unsigned int bank;
5844
5845 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
0514ef2f 5846 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
de024815 5847 (CPUID_MCE | CPUID_MCA)) {
87f8b626
AR		 5848 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF |
5849 (cpu->enable_lmce ? MCG_LMCE_P : 0);
de024815
AF		 5850 cenv->mcg_ctl = ~(uint64_t)0;
5851 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
5852 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
5853 }
5854 }
5855}
5856
c39c0edf
EH		 5857static void x86_cpu_adjust_level(X86CPU *cpu, uint32_t *min, uint32_t value)
5858{
5859 if (*min < value) {
5860 *min = value;
5861 }
5862}
5863
5864/* Increase cpuid_min_{level,xlevel,xlevel2} automatically, if appropriate */
5865static void x86_cpu_adjust_feat_level(X86CPU *cpu, FeatureWord w)
5866{
5867 CPUX86State *env = &cpu->env;
5868 FeatureWordInfo *fi = &feature_word_info[w];
07585923 5869 uint32_t eax = fi->cpuid.eax;
c39c0edf
EH		 5870 uint32_t region = eax & 0xF0000000;
5871
07585923 5872 assert(feature_word_info[w].type == CPUID_FEATURE_WORD);
c39c0edf
EH		 5873 if (!env->features[w]) {
5874 return;
5875 }
5876
5877 switch (region) {
5878 case 0x00000000:
5879 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, eax);
5880 break;
5881 case 0x80000000:
5882 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, eax);
5883 break;
5884 case 0xC0000000:
5885 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel2, eax);
5886 break;
5887 }
80db491d
JL		 5888
5889 if (eax == 7) {
5890 x86_cpu_adjust_level(cpu, &env->cpuid_min_level_func7,
5891 fi->cpuid.ecx);
5892 }
c39c0edf
EH		 5893}
5894
2ca8a8be
EH		 5895/* Calculate XSAVE components based on the configured CPU feature flags */
5896static void x86_cpu_enable_xsave_components(X86CPU *cpu)
5897{
5898 CPUX86State *env = &cpu->env;
5899 int i;
96193c22 5900 uint64_t mask;
2ca8a8be
EH		 5901
5902 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
19ca8285
XL		 5903 env->features[FEAT_XSAVE_COMP_LO] = 0;
5904 env->features[FEAT_XSAVE_COMP_HI] = 0;
2ca8a8be
EH		 5905 return;
5906 }
5907
e3c9022b
EH		 5908 mask = 0;
5909 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
2ca8a8be
EH		 5910 const ExtSaveArea *esa = &x86_ext_save_areas[i];
5911 if (env->features[esa->feature] & esa->bits) {
96193c22 5912 mask |= (1ULL << i);
2ca8a8be
EH		 5913 }
5914 }
5915
96193c22
EH		 5916 env->features[FEAT_XSAVE_COMP_LO] = mask;
5917 env->features[FEAT_XSAVE_COMP_HI] = mask >> 32;
2ca8a8be
EH		 5918}
5919
b8d834a0
EH		 5920/***** Steps involved on loading and filtering CPUID data
5921 *
5922 * When initializing and realizing a CPU object, the steps
5923 * involved in setting up CPUID data are:
5924 *
5925 * 1) Loading CPU model definition (X86CPUDefinition). This is
dcafd1ef 5926 * implemented by x86_cpu_load_model() and should be completely
b8d834a0
EH		 5927 * transparent, as it is done automatically by instance_init.
5928 * No code should need to look at X86CPUDefinition structs
5929 * outside instance_init.
5930 *
5931 * 2) CPU expansion. This is done by realize before CPUID
5932 * filtering, and will make sure host/accelerator data is
5933 * loaded for CPU models that depend on host capabilities
5934 * (e.g. "host"). Done by x86_cpu_expand_features().
5935 *
5936 * 3) CPUID filtering. This initializes extra data related to
5937 * CPUID, and checks if the host supports all capabilities
5938 * required by the CPU. Runnability of a CPU model is
5939 * determined at this step. Done by x86_cpu_filter_features().
5940 *
5941 * Some operations don't require all steps to be performed.
5942 * More precisely:
5943 *
5944 * - CPU instance creation (instance_init) will run only CPU
5945 * model loading. CPU expansion can't run at instance_init-time
5946 * because host/accelerator data may be not available yet.
5947 * - CPU realization will perform both CPU model expansion and CPUID
5948 * filtering, and return an error in case one of them fails.
5949 * - query-cpu-definitions needs to run all 3 steps. It needs
5950 * to run CPUID filtering, as the 'unavailable-features'
5951 * field is set based on the filtering results.
5952 * - The query-cpu-model-expansion QMP command only needs to run
5953 * CPU model loading and CPU expansion. It should not filter
5954 * any CPUID data based on host capabilities.
5955 */
5956
5957/* Expand CPU configuration data, based on configured features
5958 * and host/accelerator capabilities when appropriate.
5959 */
79f1a68a 5960void x86_cpu_expand_features(X86CPU *cpu, Error **errp)
7a059953 5961{
b34d12d1 5962 CPUX86State *env = &cpu->env;
dc15c051 5963 FeatureWord w;
99e24dbd 5964 int i;
2fae0d96 5965 GList *l;
9886e834 5966
99e24dbd
PB		 5967 for (l = plus_features; l; l = l->next) {
5968 const char *prop = l->data;
992861fb
MA		 5969 if (!object_property_set_bool(OBJECT(cpu), prop, true, errp)) {
5970 return;
99e24dbd
PB		 5971 }
5972 }
5973
5974 for (l = minus_features; l; l = l->next) {
5975 const char *prop = l->data;
992861fb
MA		 5976 if (!object_property_set_bool(OBJECT(cpu), prop, false, errp)) {
5977 return;
99e24dbd
PB		 5978 }
5979 }
5980
d4a606b3
EH		 5981 /*TODO: Now cpu->max_features doesn't overwrite features
5982 * set using QOM properties, and we can convert
dc15c051
IM		 5983 * plus_features & minus_features to global properties
5984 * inside x86_cpu_parse_featurestr() too.
5985 */
44bd8e53 5986 if (cpu->max_features) {
dc15c051 5987 for (w = 0; w < FEATURE_WORDS; w++) {
d4a606b3
EH		 5988 /* Override only features that weren't set explicitly
5989 * by the user.
5990 */
5991 env->features[w] |=
5992 x86_cpu_get_supported_feature_word(w, cpu->migratable) &
78ee6bd0 5993 ~env->user_features[w] &
0d914f39 5994 ~feature_word_info[w].no_autoenable_flags;
dc15c051
IM		 5995 }
5996 }
5997
99e24dbd
PB		 5998 for (i = 0; i < ARRAY_SIZE(feature_dependencies); i++) {
5999 FeatureDep *d = &feature_dependencies[i];
6000 if (!(env->features[d->from.index] & d->from.mask)) {
ede146c2 6001 uint64_t unavailable_features = env->features[d->to.index] & d->to.mask;
2fae0d96 6002
99e24dbd
PB		 6003 /* Not an error unless the dependent feature was added explicitly. */
6004 mark_unavailable_features(cpu, d->to.index,
6005 unavailable_features & env->user_features[d->to.index],
6006 "This feature depends on other features that were not requested");
6007
99e24dbd 6008 env->features[d->to.index] &= ~unavailable_features;
2fae0d96 6009 }
dc15c051
IM		 6010 }
6011
aec661de
EH		 6012 if (!kvm_enabled() || !cpu->expose_kvm) {
6013 env->features[FEAT_KVM] = 0;
6014 }
6015
2ca8a8be 6016 x86_cpu_enable_xsave_components(cpu);
c39c0edf
EH		 6017
6018 /* CPUID[EAX=7,ECX=0].EBX always increased level automatically: */
6019 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_EBX);
6020 if (cpu->full_cpuid_auto_level) {
6021 x86_cpu_adjust_feat_level(cpu, FEAT_1_EDX);
6022 x86_cpu_adjust_feat_level(cpu, FEAT_1_ECX);
6023 x86_cpu_adjust_feat_level(cpu, FEAT_6_EAX);
6024 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_ECX);
80db491d 6025 x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EAX);
c39c0edf
EH		 6026 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_EDX);
6027 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_ECX);
6028 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0007_EDX);
1b3420e1 6029 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0008_EBX);
c39c0edf
EH		 6030 x86_cpu_adjust_feat_level(cpu, FEAT_C000_0001_EDX);
6031 x86_cpu_adjust_feat_level(cpu, FEAT_SVM);
6032 x86_cpu_adjust_feat_level(cpu, FEAT_XSAVE);
f24c3a79
LK		 6033
6034 /* Intel Processor Trace requires CPUID[0x14] */
ddc2fc9e
LK		 6035 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT)) {
6036 if (cpu->intel_pt_auto_level) {
6037 x86_cpu_adjust_level(cpu, &cpu->env.cpuid_min_level, 0x14);
6038 } else if (cpu->env.cpuid_min_level < 0x14) {
6039 mark_unavailable_features(cpu, FEAT_7_0_EBX,
6040 CPUID_7_0_EBX_INTEL_PT,
b7d77f5a 6041 "Intel PT need CPUID leaf 0x14, please set by \"-cpu ...,intel-pt=on,min-level=0x14\"");
ddc2fc9e 6042 }
f24c3a79
LK		 6043 }
6044
a94e1428
LX		 6045 /* CPU topology with multi-dies support requires CPUID[0x1F] */
6046 if (env->nr_dies > 1) {
6047 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x1F);
6048 }
6049
0c3d7c00
EH		 6050 /* SVM requires CPUID[0x8000000A] */
6051 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
6052 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A);
6053 }
6cb8f2a6
BS		 6054
6055 /* SEV requires CPUID[0x8000001F] */
6056 if (sev_enabled()) {
6057 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000001F);
6058 }
c39c0edf
EH		 6059 }
6060
6061 /* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set */
80db491d
JL		 6062 if (env->cpuid_level_func7 == UINT32_MAX) {
6063 env->cpuid_level_func7 = env->cpuid_min_level_func7;
6064 }
c39c0edf
EH		 6065 if (env->cpuid_level == UINT32_MAX) {
6066 env->cpuid_level = env->cpuid_min_level;
6067 }
6068 if (env->cpuid_xlevel == UINT32_MAX) {
6069 env->cpuid_xlevel = env->cpuid_min_xlevel;
6070 }
6071 if (env->cpuid_xlevel2 == UINT32_MAX) {
6072 env->cpuid_xlevel2 = env->cpuid_min_xlevel2;
b34d12d1 6073 }
41f3d4d6
EH		 6074}
6075
b8d834a0
EH		 6076/*
6077 * Finishes initialization of CPUID data, filters CPU feature
6078 * words based on host availability of each feature.
6079 *
6080 * Returns: 0 if all flags are supported by the host, non-zero otherwise.
6081 */
245edd0c 6082static void x86_cpu_filter_features(X86CPU *cpu, bool verbose)
b8d834a0
EH		 6083{
6084 CPUX86State *env = &cpu->env;
6085 FeatureWord w;
245edd0c
PB		 6086 const char *prefix = NULL;
6087
6088 if (verbose) {
6089 prefix = accel_uses_host_cpuid()
6090 ? "host doesn't support requested feature"
6091 : "TCG doesn't support requested feature";
6092 }
b8d834a0
EH		 6093
6094 for (w = 0; w < FEATURE_WORDS; w++) {
ede146c2 6095 uint64_t host_feat =
b8d834a0 6096 x86_cpu_get_supported_feature_word(w, false);
ede146c2
PB		 6097 uint64_t requested_features = env->features[w];
6098 uint64_t unavailable_features = requested_features & ~host_feat;
245edd0c 6099 mark_unavailable_features(cpu, w, unavailable_features, prefix);
b8d834a0
EH		 6100 }
6101
e37a5c7f
CP		 6102 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) &&
6103 kvm_enabled()) {
6104 KVMState *s = CPU(cpu)->kvm_state;
6105 uint32_t eax_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_EAX);
6106 uint32_t ebx_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_EBX);
6107 uint32_t ecx_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_ECX);
6108 uint32_t eax_1 = kvm_arch_get_supported_cpuid(s, 0x14, 1, R_EAX);
6109 uint32_t ebx_1 = kvm_arch_get_supported_cpuid(s, 0x14, 1, R_EBX);
6110
6111 if (!eax_0 ||
6112 ((ebx_0 & INTEL_PT_MINIMAL_EBX) != INTEL_PT_MINIMAL_EBX) ||
6113 ((ecx_0 & INTEL_PT_MINIMAL_ECX) != INTEL_PT_MINIMAL_ECX) ||
6114 ((eax_1 & INTEL_PT_MTC_BITMAP) != INTEL_PT_MTC_BITMAP) ||
6115 ((eax_1 & INTEL_PT_ADDR_RANGES_NUM_MASK) <
6116 INTEL_PT_ADDR_RANGES_NUM) ||
6117 ((ebx_1 & (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) !=
c078ca96 6118 (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) ||
d1615ea5
LK		 6119 ((ecx_0 & CPUID_14_0_ECX_LIP) !=
6120 (env->features[FEAT_14_0_ECX] & CPUID_14_0_ECX_LIP))) {
e37a5c7f
CP		 6121 /*
6122 * Processor Trace capabilities aren't configurable, so if the
6123 * host can't emulate the capabilities we report on
6124 * cpu_x86_cpuid(), intel-pt can't be enabled on the current host.
6125 */
245edd0c 6126 mark_unavailable_features(cpu, FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT, prefix);
e37a5c7f
CP		 6127 }
6128 }
b8d834a0
EH		 6129}
6130
08856771
VK		 6131static void x86_cpu_hyperv_realize(X86CPU *cpu)
6132{
6133 size_t len;
6134
6135 /* Hyper-V vendor id */
6136 if (!cpu->hyperv_vendor) {
6137 memcpy(cpu->hyperv_vendor_id, "Microsoft Hv", 12);
6138 } else {
6139 len = strlen(cpu->hyperv_vendor);
6140
6141 if (len > 12) {
6142 warn_report("hv-vendor-id truncated to 12 characters");
6143 len = 12;
6144 }
6145 memset(cpu->hyperv_vendor_id, 0, 12);
6146 memcpy(cpu->hyperv_vendor_id, cpu->hyperv_vendor, len);
6147 }
735db465
VK		 6148
6149 /* 'Hv#1' interface identification*/
6150 cpu->hyperv_interface_id[0] = 0x31237648;
6151 cpu->hyperv_interface_id[1] = 0;
6152 cpu->hyperv_interface_id[2] = 0;
6153 cpu->hyperv_interface_id[3] = 0;
fb7e31aa
VK		 6154
6155 /* Hypervisor system identity */
6156 cpu->hyperv_version_id[0] = 0x00001bbc;
6157 cpu->hyperv_version_id[1] = 0x00060001;
23eb5d03
VK		 6158
6159 /* Hypervisor implementation limits */
6160 cpu->hyperv_limits[0] = 64;
6161 cpu->hyperv_limits[1] = 0;
6162 cpu->hyperv_limits[2] = 0;
08856771
VK		 6163}
6164
41f3d4d6
EH		 6165static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
6166{
6167 CPUState *cs = CPU(dev);
6168 X86CPU *cpu = X86_CPU(dev);
6169 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
6170 CPUX86State *env = &cpu->env;
6171 Error *local_err = NULL;
6172 static bool ht_warned;
6173
30565f10
CF		 6174 /* Process Hyper-V enlightenments */
6175 x86_cpu_hyperv_realize(cpu);
6176
6177 cpu_exec_realizefn(cs, &local_err);
6178 if (local_err != NULL) {
6179 error_propagate(errp, local_err);
6180 return;
be02cda3 6181 }
2266d443 6182
f5cc5a5c
CF		 6183 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) {
6184 g_autofree char *name = x86_cpu_class_get_model_name(xcc);
6185 error_setg(&local_err, "CPU model '%s' requires KVM or HVF", name);
6186 goto out;
41f3d4d6
EH		 6187 }
6188
4e45aff3
PB		 6189 if (cpu->ucode_rev == 0) {
6190 /* The default is the same as KVM's. */
6191 if (IS_AMD_CPU(env)) {
6192 cpu->ucode_rev = 0x01000065;
6193 } else {
6194 cpu->ucode_rev = 0x100000000ULL;
6195 }
6196 }
6197
2266d443
MT		 6198 /* mwait extended info: needed for Core compatibility */
6199 /* We always wake on interrupt even if host does not have the capability */
6200 cpu->mwait.ecx |= CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
6201
41f3d4d6
EH		 6202 if (cpu->apic_id == UNASSIGNED_APIC_ID) {
6203 error_setg(errp, "apic-id property was not initialized properly");
6204 return;
6205 }
6206
b8d834a0 6207 x86_cpu_expand_features(cpu, &local_err);
41f3d4d6
EH		 6208 if (local_err) {
6209 goto out;
6210 }
6211
245edd0c
PB		 6212 x86_cpu_filter_features(cpu, cpu->check_cpuid || cpu->enforce_cpuid);
6213
6214 if (cpu->enforce_cpuid && x86_cpu_have_filtered_features(cpu)) {
6215 error_setg(&local_err,
6216 accel_uses_host_cpuid() ?
6217 "Host doesn't support requested features" :
6218 "TCG doesn't support requested features");
6219 goto out;
9997cf7b
EH		 6220 }
6221
9b15cd9e
IM		 6222 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
6223 * CPUID[1].EDX.
6224 */
e48638fd 6225 if (IS_AMD_CPU(env)) {
0514ef2f
EH		 6226 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES;
6227 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX]
9b15cd9e
IM		 6228 & CPUID_EXT2_AMD_ALIASES);
6229 }
6230
11f6fee5
DDAG		 6231 /* For 64bit systems think about the number of physical bits to present.
6232 * ideally this should be the same as the host; anything other than matching
6233 * the host can cause incorrect guest behaviour.
6234 * QEMU used to pick the magic value of 40 bits that corresponds to
6235 * consumer AMD devices but nothing else.
6236 */
af45907a 6237 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
b8184135
PB		 6238 if (cpu->phys_bits &&
6239 (cpu->phys_bits > TARGET_PHYS_ADDR_SPACE_BITS ||
6240 cpu->phys_bits < 32)) {
6241 error_setg(errp, "phys-bits should be between 32 and %u "
6242 " (but is %u)",
6243 TARGET_PHYS_ADDR_SPACE_BITS, cpu->phys_bits);
6244 return;
af45907a 6245 }
f5cc5a5c
CF		 6246 /*
6247 * 0 means it was not explicitly set by the user (or by machine
6248 * compat_props or by the host code in host-cpu.c).
6249 * In this case, the default is the value used by TCG (40).
11f6fee5
DDAG		 6250 */
6251 if (cpu->phys_bits == 0) {
6252 cpu->phys_bits = TCG_PHYS_ADDR_BITS;
6253 }
af45907a
DDAG		 6254 } else {
6255 /* For 32 bit systems don't use the user set value, but keep
6256 * phys_bits consistent with what we tell the guest.
6257 */
6258 if (cpu->phys_bits != 0) {
6259 error_setg(errp, "phys-bits is not user-configurable in 32 bit");
6260 return;
6261 }
fefb41bf 6262
af45907a
DDAG		 6263 if (env->features[FEAT_1_EDX] & CPUID_PSE36) {
6264 cpu->phys_bits = 36;
6265 } else {
6266 cpu->phys_bits = 32;
6267 }
6268 }
a9f27ea9
EH		 6269
6270 /* Cache information initialization */
6271 if (!cpu->legacy_cache) {
dcafd1ef 6272 if (!xcc->model || !xcc->model->cpudef->cache_info) {
88703ce2 6273 g_autofree char *name = x86_cpu_class_get_model_name(xcc);
a9f27ea9
EH		 6274 error_setg(errp,
6275 "CPU model '%s' doesn't support legacy-cache=off", name);
a9f27ea9
EH		 6276 return;
6277 }
6278 env->cache_info_cpuid2 = env->cache_info_cpuid4 = env->cache_info_amd =
dcafd1ef 6279 *xcc->model->cpudef->cache_info;
a9f27ea9
EH		 6280 } else {
6281 /* Build legacy cache information */
6282 env->cache_info_cpuid2.l1d_cache = &legacy_l1d_cache;
6283 env->cache_info_cpuid2.l1i_cache = &legacy_l1i_cache;
6284 env->cache_info_cpuid2.l2_cache = &legacy_l2_cache_cpuid2;
6285 env->cache_info_cpuid2.l3_cache = &legacy_l3_cache;
6286
6287 env->cache_info_cpuid4.l1d_cache = &legacy_l1d_cache;
6288 env->cache_info_cpuid4.l1i_cache = &legacy_l1i_cache;
6289 env->cache_info_cpuid4.l2_cache = &legacy_l2_cache;
6290 env->cache_info_cpuid4.l3_cache = &legacy_l3_cache;
6291
6292 env->cache_info_amd.l1d_cache = &legacy_l1d_cache_amd;
6293 env->cache_info_amd.l1i_cache = &legacy_l1i_cache_amd;
6294 env->cache_info_amd.l2_cache = &legacy_l2_cache_amd;
6295 env->cache_info_amd.l3_cache = &legacy_l3_cache;
6296 }
6297
65dee380 6298#ifndef CONFIG_USER_ONLY
0e11fc69 6299 MachineState *ms = MACHINE(qdev_get_machine());
65dee380 6300 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
bdeec802 6301
0e11fc69 6302 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || ms->smp.cpus > 1) {
d3c64d6a 6303 x86_cpu_apic_create(cpu, &local_err);
2b6f294c 6304 if (local_err != NULL) {
4dc1f449 6305 goto out;
bdeec802
IM		 6306 }
6307 }
65dee380
IM		 6308#endif
6309
7a059953 6310 mce_init(cpu);
2001d0cd 6311
14a10fc3 6312 qemu_init_vcpu(cs);
d3c64d6a 6313
6b2942f9
BM		 6314 /*
6315 * Most Intel and certain AMD CPUs support hyperthreading. Even though QEMU
6316 * fixes this issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX
6317 * based on inputs (sockets,cores,threads), it is still better to give
e48638fd
WH		 6318 * users a warning.
6319 *
6320 * NOTE: the following code has to follow qemu_init_vcpu(). Otherwise
6321 * cs->nr_threads hasn't be populated yet and the checking is incorrect.
6322 */
0765691e
MA		 6323 if (IS_AMD_CPU(env) &&
6324 !(env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_TOPOEXT) &&
6325 cs->nr_threads > 1 && !ht_warned) {
6326 warn_report("This family of AMD CPU doesn't support "
6327 "hyperthreading(%d)",
6328 cs->nr_threads);
6329 error_printf("Please configure -smp options properly"
6330 " or try enabling topoext feature.\n");
6331 ht_warned = true;
e48638fd
WH		 6332 }
6333
79f1a68a 6334#ifndef CONFIG_USER_ONLY
d3c64d6a
IM		 6335 x86_cpu_apic_realize(cpu, &local_err);
6336 if (local_err != NULL) {
6337 goto out;
6338 }
79f1a68a 6339#endif /* !CONFIG_USER_ONLY */
14a10fc3 6340 cpu_reset(cs);
2b6f294c 6341
4dc1f449 6342 xcc->parent_realize(dev, &local_err);
2001d0cd 6343
4dc1f449
IM		 6344out:
6345 if (local_err != NULL) {
6346 error_propagate(errp, local_err);
6347 return;
6348 }
7a059953
AF		 6349}
6350
b69c3c21 6351static void x86_cpu_unrealizefn(DeviceState *dev)
c884776e
IM		 6352{
6353 X86CPU *cpu = X86_CPU(dev);
7bbc124e 6354 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
c884776e
IM		 6355
6356#ifndef CONFIG_USER_ONLY
6357 cpu_remove_sync(CPU(dev));
6358 qemu_unregister_reset(x86_cpu_machine_reset_cb, dev);
6359#endif
6360
6361 if (cpu->apic_state) {
6362 object_unparent(OBJECT(cpu->apic_state));
6363 cpu->apic_state = NULL;
6364 }
7bbc124e 6365
b69c3c21 6366 xcc->parent_unrealize(dev);
c884776e
IM		 6367}
6368
38e5c119 6369typedef struct BitProperty {
a7b0ffac 6370 FeatureWord w;
ede146c2 6371 uint64_t mask;
38e5c119
EH		 6372} BitProperty;
6373
d7bce999
EB		 6374static void x86_cpu_get_bit_prop(Object *obj, Visitor *v, const char *name,
6375 void *opaque, Error **errp)
38e5c119 6376{
a7b0ffac 6377 X86CPU *cpu = X86_CPU(obj);
38e5c119 6378 BitProperty *fp = opaque;
ede146c2 6379 uint64_t f = cpu->env.features[fp->w];
a7b0ffac 6380 bool value = (f & fp->mask) == fp->mask;
51e72bc1 6381 visit_type_bool(v, name, &value, errp);
38e5c119
EH		 6382}
6383
d7bce999
EB		 6384static void x86_cpu_set_bit_prop(Object *obj, Visitor *v, const char *name,
6385 void *opaque, Error **errp)
38e5c119
EH		 6386{
6387 DeviceState *dev = DEVICE(obj);
a7b0ffac 6388 X86CPU *cpu = X86_CPU(obj);
38e5c119 6389 BitProperty *fp = opaque;
38e5c119
EH		 6390 bool value;
6391
6392 if (dev->realized) {
6393 qdev_prop_set_after_realize(dev, name, errp);
6394 return;
6395 }
6396
668f62ec 6397 if (!visit_type_bool(v, name, &value, errp)) {
38e5c119
EH		 6398 return;
6399 }
6400
6401 if (value) {
a7b0ffac 6402 cpu->env.features[fp->w] |= fp->mask;
38e5c119 6403 } else {
a7b0ffac 6404 cpu->env.features[fp->w] &= ~fp->mask;
38e5c119 6405 }
d4a606b3 6406 cpu->env.user_features[fp->w] |= fp->mask;
38e5c119
EH		 6407}
6408
38e5c119
EH		 6409/* Register a boolean property to get/set a single bit in a uint32_t field.
6410 *
6411 * The same property name can be registered multiple times to make it affect
6412 * multiple bits in the same FeatureWord. In that case, the getter will return
6413 * true only if all bits are set.
6414 */
f5730c69 6415static void x86_cpu_register_bit_prop(X86CPUClass *xcc,
38e5c119 6416 const char *prop_name,
a7b0ffac 6417 FeatureWord w,
38e5c119
EH		 6418 int bitnr)
6419{
f5730c69 6420 ObjectClass *oc = OBJECT_CLASS(xcc);
38e5c119
EH		 6421 BitProperty *fp;
6422 ObjectProperty *op;
ede146c2 6423 uint64_t mask = (1ULL << bitnr);
38e5c119 6424
f5730c69 6425 op = object_class_property_find(oc, prop_name);
38e5c119
EH		 6426 if (op) {
6427 fp = op->opaque;
a7b0ffac 6428 assert(fp->w == w);
38e5c119
EH		 6429 fp->mask |= mask;
6430 } else {
6431 fp = g_new0(BitProperty, 1);
a7b0ffac 6432 fp->w = w;
38e5c119 6433 fp->mask = mask;
f5730c69
EH		 6434 object_class_property_add(oc, prop_name, "bool",
6435 x86_cpu_get_bit_prop,
6436 x86_cpu_set_bit_prop,
6437 NULL, fp);
38e5c119
EH		 6438 }
6439}
6440
f5730c69 6441static void x86_cpu_register_feature_bit_props(X86CPUClass *xcc,
38e5c119
EH		 6442 FeatureWord w,
6443 int bitnr)
6444{
38e5c119 6445 FeatureWordInfo *fi = &feature_word_info[w];
16d2fcaa 6446 const char *name = fi->feat_names[bitnr];
38e5c119 6447
16d2fcaa 6448 if (!name) {
38e5c119
EH		 6449 return;
6450 }
6451
fc7dfd20
EH		 6452 /* Property names should use "-" instead of "_".
6453 * Old names containing underscores are registered as aliases
6454 * using object_property_add_alias()
6455 */
16d2fcaa
EH		 6456 assert(!strchr(name, '_'));
6457 /* aliases don't use "|" delimiters anymore, they are registered
6458 * manually using object_property_add_alias() */
6459 assert(!strchr(name, '|'));
f5730c69 6460 x86_cpu_register_bit_prop(xcc, name, w, bitnr);
38e5c119
EH		 6461}
6462
de024815
AF		 6463static void x86_cpu_initfn(Object *obj)
6464{
6465 X86CPU *cpu = X86_CPU(obj);
d940ee9b 6466 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj);
de024815
AF		 6467 CPUX86State *env = &cpu->env;
6468
c26ae610 6469 env->nr_dies = 1;
7506ed90 6470 cpu_set_cpustate_pointers(cpu);
71ad61d3 6471
8e8aba50
EH		 6472 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo",
6473 x86_cpu_get_feature_words,
d2623129 6474 NULL, NULL, (void *)env->features);
7e5292b5
EH		 6475 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo",
6476 x86_cpu_get_feature_words,
d2623129 6477 NULL, NULL, (void *)cpu->filtered_features);
d187e08d 6478
d2623129
MA		 6479 object_property_add_alias(obj, "sse3", obj, "pni");
6480 object_property_add_alias(obj, "pclmuldq", obj, "pclmulqdq");
6481 object_property_add_alias(obj, "sse4-1", obj, "sse4.1");
6482 object_property_add_alias(obj, "sse4-2", obj, "sse4.2");
6483 object_property_add_alias(obj, "xd", obj, "nx");
6484 object_property_add_alias(obj, "ffxsr", obj, "fxsr-opt");
6485 object_property_add_alias(obj, "i64", obj, "lm");
6486
6487 object_property_add_alias(obj, "ds_cpl", obj, "ds-cpl");
6488 object_property_add_alias(obj, "tsc_adjust", obj, "tsc-adjust");
6489 object_property_add_alias(obj, "fxsr_opt", obj, "fxsr-opt");
6490 object_property_add_alias(obj, "lahf_lm", obj, "lahf-lm");
6491 object_property_add_alias(obj, "cmp_legacy", obj, "cmp-legacy");
6492 object_property_add_alias(obj, "nodeid_msr", obj, "nodeid-msr");
6493 object_property_add_alias(obj, "perfctr_core", obj, "perfctr-core");
6494 object_property_add_alias(obj, "perfctr_nb", obj, "perfctr-nb");
6495 object_property_add_alias(obj, "kvm_nopiodelay", obj, "kvm-nopiodelay");
6496 object_property_add_alias(obj, "kvm_mmu", obj, "kvm-mmu");
6497 object_property_add_alias(obj, "kvm_asyncpf", obj, "kvm-asyncpf");
db5daafa 6498 object_property_add_alias(obj, "kvm_asyncpf_int", obj, "kvm-asyncpf-int");
d2623129
MA		 6499 object_property_add_alias(obj, "kvm_steal_time", obj, "kvm-steal-time");
6500 object_property_add_alias(obj, "kvm_pv_eoi", obj, "kvm-pv-eoi");
6501 object_property_add_alias(obj, "kvm_pv_unhalt", obj, "kvm-pv-unhalt");
6502 object_property_add_alias(obj, "kvm_poll_control", obj, "kvm-poll-control");
6503 object_property_add_alias(obj, "svm_lock", obj, "svm-lock");
6504 object_property_add_alias(obj, "nrip_save", obj, "nrip-save");
6505 object_property_add_alias(obj, "tsc_scale", obj, "tsc-scale");
6506 object_property_add_alias(obj, "vmcb_clean", obj, "vmcb-clean");
6507 object_property_add_alias(obj, "pause_filter", obj, "pause-filter");
6508 object_property_add_alias(obj, "sse4_1", obj, "sse4.1");
6509 object_property_add_alias(obj, "sse4_2", obj, "sse4.2");
54b8dc7c 6510
dcafd1ef 6511 if (xcc->model) {
49e2fa85 6512 x86_cpu_load_model(cpu, xcc->model);
0bacd8b3 6513 }
f5cc5a5c 6514
bb883fd6
CF		 6515 /* if required, do accelerator-specific cpu initializations */
6516 accel_cpu_instance_init(CPU(obj));
de024815
AF		 6517}
6518
997395d3
IM		 6519static int64_t x86_cpu_get_arch_id(CPUState *cs)
6520{
6521 X86CPU *cpu = X86_CPU(cs);
997395d3 6522
7e72a45c 6523 return cpu->apic_id;
997395d3
IM		 6524}
6525
6bc0d6a0 6526#if !defined(CONFIG_USER_ONLY)
444d5590
AF		 6527static bool x86_cpu_get_paging_enabled(const CPUState *cs)
6528{
6529 X86CPU *cpu = X86_CPU(cs);
6530
6531 return cpu->env.cr[0] & CR0_PG_MASK;
6532}
6bc0d6a0 6533#endif /* !CONFIG_USER_ONLY */
444d5590 6534
f45748f1
AF		 6535static void x86_cpu_set_pc(CPUState *cs, vaddr value)
6536{
6537 X86CPU *cpu = X86_CPU(cs);
6538
6539 cpu->env.eip = value;
6540}
6541
92d5f1a4 6542int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request)
8c2e1b00
AF		 6543{
6544 X86CPU *cpu = X86_CPU(cs);
6545 CPUX86State *env = &cpu->env;
6546
92d5f1a4
PB		 6547#if !defined(CONFIG_USER_ONLY)
6548 if (interrupt_request & CPU_INTERRUPT_POLL) {
6549 return CPU_INTERRUPT_POLL;
6550 }
6551#endif
6552 if (interrupt_request & CPU_INTERRUPT_SIPI) {
6553 return CPU_INTERRUPT_SIPI;
6554 }
6555
6556 if (env->hflags2 & HF2_GIF_MASK) {
6557 if ((interrupt_request & CPU_INTERRUPT_SMI) &&
6558 !(env->hflags & HF_SMM_MASK)) {
6559 return CPU_INTERRUPT_SMI;
6560 } else if ((interrupt_request & CPU_INTERRUPT_NMI) &&
6561 !(env->hflags2 & HF2_NMI_MASK)) {
6562 return CPU_INTERRUPT_NMI;
6563 } else if (interrupt_request & CPU_INTERRUPT_MCE) {
6564 return CPU_INTERRUPT_MCE;
6565 } else if ((interrupt_request & CPU_INTERRUPT_HARD) &&
6566 (((env->hflags2 & HF2_VINTR_MASK) &&
6567 (env->hflags2 & HF2_HIF_MASK)) ||
6568 (!(env->hflags2 & HF2_VINTR_MASK) &&
6569 (env->eflags & IF_MASK &&
6570 !(env->hflags & HF_INHIBIT_IRQ_MASK))))) {
6571 return CPU_INTERRUPT_HARD;
6572#if !defined(CONFIG_USER_ONLY)
6573 } else if ((interrupt_request & CPU_INTERRUPT_VIRQ) &&
6574 (env->eflags & IF_MASK) &&
6575 !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
6576 return CPU_INTERRUPT_VIRQ;
6577#endif
6578 }
6579 }
6580
6581 return 0;
6582}
6583
6584static bool x86_cpu_has_work(CPUState *cs)
6585{
6586 return x86_cpu_pending_interrupt(cs, cs->interrupt_request) != 0;
8c2e1b00
AF		 6587}
6588
f50f3dd5
RH		 6589static void x86_disas_set_info(CPUState *cs, disassemble_info *info)
6590{
6591 X86CPU *cpu = X86_CPU(cs);
6592 CPUX86State *env = &cpu->env;
6593
6594 info->mach = (env->hflags & HF_CS64_MASK ? bfd_mach_x86_64
6595 : env->hflags & HF_CS32_MASK ? bfd_mach_i386_i386
6596 : bfd_mach_i386_i8086);
6597 info->print_insn = print_insn_i386;
b666d2a4
RH		 6598
6599 info->cap_arch = CS_ARCH_X86;
6600 info->cap_mode = (env->hflags & HF_CS64_MASK ? CS_MODE_64
6601 : env->hflags & HF_CS32_MASK ? CS_MODE_32
6602 : CS_MODE_16);
15fa1a0a
RH		 6603 info->cap_insn_unit = 1;
6604 info->cap_insn_split = 8;
f50f3dd5
RH		 6605}
6606
35b1b927
TW		 6607void x86_update_hflags(CPUX86State *env)
6608{
6609 uint32_t hflags;
6610#define HFLAG_COPY_MASK \
6611 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
6612 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
6613 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
6614 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
6615
6616 hflags = env->hflags & HFLAG_COPY_MASK;
6617 hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
6618 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
6619 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
6620 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
6621 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
6622
6623 if (env->cr[4] & CR4_OSFXSR_MASK) {
6624 hflags |= HF_OSFXSR_MASK;
6625 }
6626
6627 if (env->efer & MSR_EFER_LMA) {
6628 hflags |= HF_LMA_MASK;
6629 }
6630
6631 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
6632 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
6633 } else {
6634 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
6635 (DESC_B_SHIFT - HF_CS32_SHIFT);
6636 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
6637 (DESC_B_SHIFT - HF_SS32_SHIFT);
6638 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
6639 !(hflags & HF_CS32_MASK)) {
6640 hflags |= HF_ADDSEG_MASK;
6641 } else {
6642 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
6643 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
6644 }
6645 }
6646 env->hflags = hflags;
6647}
6648
9337e3b6 6649static Property x86_cpu_properties[] = {
2da00e31
IM		 6650#ifdef CONFIG_USER_ONLY
6651 /* apic_id = 0 by default for *-user, see commit 9886e834 */
6652 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, 0),
d89c2b8b
IM		 6653 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, 0),
6654 DEFINE_PROP_INT32("core-id", X86CPU, core_id, 0),
176d2cda 6655 DEFINE_PROP_INT32("die-id", X86CPU, die_id, 0),
d89c2b8b 6656 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, 0),
2da00e31
IM		 6657#else
6658 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, UNASSIGNED_APIC_ID),
d89c2b8b
IM		 6659 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, -1),
6660 DEFINE_PROP_INT32("core-id", X86CPU, core_id, -1),
176d2cda 6661 DEFINE_PROP_INT32("die-id", X86CPU, die_id, -1),
d89c2b8b 6662 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, -1),
2da00e31 6663#endif
15f8b142 6664 DEFINE_PROP_INT32("node-id", X86CPU, node_id, CPU_UNSET_NUMA_NODE_ID),
9337e3b6 6665 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false),
2d384d7c 6666
915aee93 6667 DEFINE_PROP_UINT32("hv-spinlocks", X86CPU, hyperv_spinlock_attempts,
f701c082 6668 HYPERV_SPINLOCK_NEVER_NOTIFY),
2d384d7c
VK		 6669 DEFINE_PROP_BIT64("hv-relaxed", X86CPU, hyperv_features,
6670 HYPERV_FEAT_RELAXED, 0),
6671 DEFINE_PROP_BIT64("hv-vapic", X86CPU, hyperv_features,
6672 HYPERV_FEAT_VAPIC, 0),
6673 DEFINE_PROP_BIT64("hv-time", X86CPU, hyperv_features,
6674 HYPERV_FEAT_TIME, 0),
6675 DEFINE_PROP_BIT64("hv-crash", X86CPU, hyperv_features,
6676 HYPERV_FEAT_CRASH, 0),
6677 DEFINE_PROP_BIT64("hv-reset", X86CPU, hyperv_features,
6678 HYPERV_FEAT_RESET, 0),
6679 DEFINE_PROP_BIT64("hv-vpindex", X86CPU, hyperv_features,
6680 HYPERV_FEAT_VPINDEX, 0),
6681 DEFINE_PROP_BIT64("hv-runtime", X86CPU, hyperv_features,
6682 HYPERV_FEAT_RUNTIME, 0),
6683 DEFINE_PROP_BIT64("hv-synic", X86CPU, hyperv_features,
6684 HYPERV_FEAT_SYNIC, 0),
6685 DEFINE_PROP_BIT64("hv-stimer", X86CPU, hyperv_features,
6686 HYPERV_FEAT_STIMER, 0),
6687 DEFINE_PROP_BIT64("hv-frequencies", X86CPU, hyperv_features,
6688 HYPERV_FEAT_FREQUENCIES, 0),
6689 DEFINE_PROP_BIT64("hv-reenlightenment", X86CPU, hyperv_features,
6690 HYPERV_FEAT_REENLIGHTENMENT, 0),
6691 DEFINE_PROP_BIT64("hv-tlbflush", X86CPU, hyperv_features,
6692 HYPERV_FEAT_TLBFLUSH, 0),
6693 DEFINE_PROP_BIT64("hv-evmcs", X86CPU, hyperv_features,
6694 HYPERV_FEAT_EVMCS, 0),
6695 DEFINE_PROP_BIT64("hv-ipi", X86CPU, hyperv_features,
6696 HYPERV_FEAT_IPI, 0),
128531d9
VK		 6697 DEFINE_PROP_BIT64("hv-stimer-direct", X86CPU, hyperv_features,
6698 HYPERV_FEAT_STIMER_DIRECT, 0),
30d6ff66
VK		 6699 DEFINE_PROP_ON_OFF_AUTO("hv-no-nonarch-coresharing", X86CPU,
6700 hyperv_no_nonarch_cs, ON_OFF_AUTO_OFF),
e48ddcc6 6701 DEFINE_PROP_BOOL("hv-passthrough", X86CPU, hyperv_passthrough, false),
2d384d7c 6702
15e41345 6703 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, true),
912ffc47 6704 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false),
dac1deae 6705 DEFINE_PROP_BOOL("x-force-features", X86CPU, force_features, false),
f522d2ac 6706 DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true),
af45907a 6707 DEFINE_PROP_UINT32("phys-bits", X86CPU, phys_bits, 0),
11f6fee5 6708 DEFINE_PROP_BOOL("host-phys-bits", X86CPU, host_phys_bits, false),
258fe08b 6709 DEFINE_PROP_UINT8("host-phys-bits-limit", X86CPU, host_phys_bits_limit, 0),
fcc35e7c 6710 DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU, fill_mtrr_mask, true),
80db491d
JL		 6711 DEFINE_PROP_UINT32("level-func7", X86CPU, env.cpuid_level_func7,
6712 UINT32_MAX),
c39c0edf
EH		 6713 DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, UINT32_MAX),
6714 DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, UINT32_MAX),
6715 DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, UINT32_MAX),
6716 DEFINE_PROP_UINT32("min-level", X86CPU, env.cpuid_min_level, 0),
6717 DEFINE_PROP_UINT32("min-xlevel", X86CPU, env.cpuid_min_xlevel, 0),
6718 DEFINE_PROP_UINT32("min-xlevel2", X86CPU, env.cpuid_min_xlevel2, 0),
4e45aff3 6719 DEFINE_PROP_UINT64("ucode-rev", X86CPU, ucode_rev, 0),
c39c0edf 6720 DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_level, true),
08856771 6721 DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor),
5232d00a 6722 DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true),
87f8b626 6723 DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false),
14c985cf 6724 DEFINE_PROP_BOOL("l3-cache", X86CPU, enable_l3_cache, true),
fc3a1fd7
DDAG		 6725 DEFINE_PROP_BOOL("kvm-no-smi-migration", X86CPU, kvm_no_smi_migration,
6726 false),
0b564e6f 6727 DEFINE_PROP_BOOL("vmware-cpuid-freq", X86CPU, vmware_cpuid_freq, true),
1ce36bfe 6728 DEFINE_PROP_BOOL("tcg-cpuid", X86CPU, expose_tcg, true),
990e0be2
PB		 6729 DEFINE_PROP_BOOL("x-migrate-smi-count", X86CPU, migrate_smi_count,
6730 true),
ab8f992e 6731 /*
a9f27ea9
EH		 6732 * lecacy_cache defaults to true unless the CPU model provides its
6733 * own cache information (see x86_cpu_load_def()).
ab8f992e 6734 */
a9f27ea9 6735 DEFINE_PROP_BOOL("legacy-cache", X86CPU, legacy_cache, true),
6c69dfb6
GA		 6736
6737 /*
6738 * From "Requirements for Implementing the Microsoft
6739 * Hypervisor Interface":
6740 * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs
6741 *
6742 * "Starting with Windows Server 2012 and Windows 8, if
6743 * CPUID.40000005.EAX contains a value of -1, Windows assumes that
6744 * the hypervisor imposes no specific limit to the number of VPs.
6745 * In this case, Windows Server 2012 guest VMs may use more than
6746 * 64 VPs, up to the maximum supported number of processors applicable
6747 * to the specific Windows version being used."
6748 */
6749 DEFINE_PROP_INT32("x-hv-max-vps", X86CPU, hv_max_vps, -1),
9b4cf107
RK		 6750 DEFINE_PROP_BOOL("x-hv-synic-kvm-only", X86CPU, hyperv_synic_kvm_only,
6751 false),
f24c3a79
LK		 6752 DEFINE_PROP_BOOL("x-intel-pt-auto-level", X86CPU, intel_pt_auto_level,
6753 true),
9337e3b6
EH		 6754 DEFINE_PROP_END_OF_LIST()
6755};
6756
8b80bd28
PMD		 6757#ifndef CONFIG_USER_ONLY
6758#include "hw/core/sysemu-cpu-ops.h"
6759
6760static const struct SysemuCPUOps i386_sysemu_ops = {
2b60b62e 6761 .get_memory_mapping = x86_cpu_get_memory_mapping,
6bc0d6a0 6762 .get_paging_enabled = x86_cpu_get_paging_enabled,
08928c6d 6763 .get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug,
faf39e82 6764 .asidx_from_attrs = x86_asidx_from_attrs,
83ec01b6 6765 .get_crash_info = x86_cpu_get_crash_info,
715e3c1a
PMD		 6766 .write_elf32_note = x86_cpu_write_elf32_note,
6767 .write_elf64_note = x86_cpu_write_elf64_note,
6768 .write_elf32_qemunote = x86_cpu_write_elf32_qemunote,
6769 .write_elf64_qemunote = x86_cpu_write_elf64_qemunote,
feece4d0 6770 .legacy_vmsd = &vmstate_x86_cpu,
8b80bd28
PMD		 6771};
6772#endif
6773
5fd2087a
AF		 6774static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
6775{
6776 X86CPUClass *xcc = X86_CPU_CLASS(oc);
6777 CPUClass *cc = CPU_CLASS(oc);
2b6f294c 6778 DeviceClass *dc = DEVICE_CLASS(oc);
f5730c69 6779 FeatureWord w;
2b6f294c 6780
bf853881
PMD		 6781 device_class_set_parent_realize(dc, x86_cpu_realizefn,
6782 &xcc->parent_realize);
6783 device_class_set_parent_unrealize(dc, x86_cpu_unrealizefn,
6784 &xcc->parent_unrealize);
4f67d30b 6785 device_class_set_props(dc, x86_cpu_properties);
5fd2087a 6786
781c67ca 6787 device_class_set_parent_reset(dc, x86_cpu_reset, &xcc->parent_reset);
91b1df8c 6788 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP;
f56e3a14 6789
500050d1 6790 cc->class_by_name = x86_cpu_class_by_name;
94a444b2 6791 cc->parse_features = x86_cpu_parse_featurestr;
8c2e1b00 6792 cc->has_work = x86_cpu_has_work;
878096ee 6793 cc->dump_state = x86_cpu_dump_state;
f45748f1 6794 cc->set_pc = x86_cpu_set_pc;
5b50e790
AF		 6795 cc->gdb_read_register = x86_cpu_gdb_read_register;
6796 cc->gdb_write_register = x86_cpu_gdb_write_register;
444d5590 6797 cc->get_arch_id = x86_cpu_get_arch_id;
ed69e831 6798
5d004421 6799#ifndef CONFIG_USER_ONLY
8b80bd28 6800 cc->sysemu_ops = &i386_sysemu_ops;
ed69e831
CF		 6801#endif /* !CONFIG_USER_ONLY */
6802
00fcd100
AB		 6803 cc->gdb_arch_name = x86_gdb_arch_name;
6804#ifdef TARGET_X86_64
b8158192 6805 cc->gdb_core_xml_file = "i386-64bit.xml";
7b0f97ba 6806 cc->gdb_num_core_regs = 66;
00fcd100 6807#else
b8158192 6808 cc->gdb_core_xml_file = "i386-32bit.xml";
7b0f97ba 6809 cc->gdb_num_core_regs = 50;
74d7fc7f 6810#endif
f50f3dd5 6811 cc->disas_set_info = x86_disas_set_info;
4c315c27 6812
e90f2a8c 6813 dc->user_creatable = true;
3e0dceaf
EH		 6814
6815 object_class_property_add(oc, "family", "int",
6816 x86_cpuid_version_get_family,
6817 x86_cpuid_version_set_family, NULL, NULL);
6818 object_class_property_add(oc, "model", "int",
6819 x86_cpuid_version_get_model,
6820 x86_cpuid_version_set_model, NULL, NULL);
6821 object_class_property_add(oc, "stepping", "int",
6822 x86_cpuid_version_get_stepping,
6823 x86_cpuid_version_set_stepping, NULL, NULL);
6824 object_class_property_add_str(oc, "vendor",
6825 x86_cpuid_get_vendor,
6826 x86_cpuid_set_vendor);
6827 object_class_property_add_str(oc, "model-id",
6828 x86_cpuid_get_model_id,
6829 x86_cpuid_set_model_id);
6830 object_class_property_add(oc, "tsc-frequency", "int",
6831 x86_cpuid_get_tsc_freq,
6832 x86_cpuid_set_tsc_freq, NULL, NULL);
6833 /*
6834 * The "unavailable-features" property has the same semantics as
6835 * CpuDefinitionInfo.unavailable-features on the "query-cpu-definitions"
6836 * QMP command: they list the features that would have prevented the
6837 * CPU from running if the "enforce" flag was set.
6838 */
6839 object_class_property_add(oc, "unavailable-features", "strList",
6840 x86_cpu_get_unavailable_features,
6841 NULL, NULL, NULL);
6842
6843#if !defined(CONFIG_USER_ONLY)
6844 object_class_property_add(oc, "crash-information", "GuestPanicInformation",
6845 x86_cpu_get_crash_info_qom, NULL, NULL, NULL);
6846#endif
6847
f5730c69
EH		 6848 for (w = 0; w < FEATURE_WORDS; w++) {
6849 int bitnr;
6850 for (bitnr = 0; bitnr < 64; bitnr++) {
6851 x86_cpu_register_feature_bit_props(xcc, w, bitnr);
6852 }
6853 }
5fd2087a
AF		 6854}
6855
6856static const TypeInfo x86_cpu_type_info = {
6857 .name = TYPE_X86_CPU,
6858 .parent = TYPE_CPU,
6859 .instance_size = sizeof(X86CPU),
de024815 6860 .instance_init = x86_cpu_initfn,
d940ee9b 6861 .abstract = true,
5fd2087a
AF		 6862 .class_size = sizeof(X86CPUClass),
6863 .class_init = x86_cpu_common_class_init,
6864};
6865
5adbed30
EH		 6866
6867/* "base" CPU model, used by query-cpu-model-expansion */
6868static void x86_cpu_base_class_init(ObjectClass *oc, void *data)
6869{
6870 X86CPUClass *xcc = X86_CPU_CLASS(oc);
6871
6872 xcc->static_model = true;
6873 xcc->migration_safe = true;
6874 xcc->model_description = "base CPU model type with no features enabled";
6875 xcc->ordering = 8;
6876}
6877
6878static const TypeInfo x86_base_cpu_type_info = {
6879 .name = X86_CPU_TYPE_NAME("base"),
6880 .parent = TYPE_X86_CPU,
6881 .class_init = x86_cpu_base_class_init,
6882};
6883
5fd2087a
AF		 6884static void x86_cpu_register_types(void)
6885{
d940ee9b
EH		 6886 int i;
6887
5fd2087a 6888 type_register_static(&x86_cpu_type_info);
d940ee9b 6889 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
dcafd1ef 6890 x86_register_cpudef_types(&builtin_x86_defs[i]);
d940ee9b 6891 }
c62f2630 6892 type_register_static(&max_x86_cpu_type_info);
5adbed30 6893 type_register_static(&x86_base_cpu_type_info);
5fd2087a
AF		 6894}
6895
6896type_init(x86_cpu_register_types)
Empty description
This page took 2.268798 seconds and 4 git commands to generate.