[qemu.git] / hw / net / pcnet-pci.c

/*
 * QEMU AMD PC-Net II (Am79C970A) PCI emulation
 *
 * Copyright (c) 2004 Antony T Curtis
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

/* This software was written to be compatible with the specification:
 * AMD Am79C970A PCnet-PCI II Ethernet Controller Data-Sheet
 * AMD Publication# 19436  Rev:E  Amendment/0  Issue Date: June 2000
 */

#include "qemu/osdep.h"
#include "hw/pci/pci.h"
#include "net/net.h"
#include "hw/loader.h"
#include "qemu/timer.h"
#include "sysemu/dma.h"
#include "sysemu/sysemu.h"
#include "trace.h"

#include "pcnet.h"

//#define PCNET_DEBUG
//#define PCNET_DEBUG_IO
//#define PCNET_DEBUG_BCR
//#define PCNET_DEBUG_CSR
//#define PCNET_DEBUG_RMD
//#define PCNET_DEBUG_TMD
//#define PCNET_DEBUG_MATCH

#define TYPE_PCI_PCNET "pcnet"

#define PCI_PCNET(obj) \
     OBJECT_CHECK(PCIPCNetState, (obj), TYPE_PCI_PCNET)

typedef struct {
    /*< private >*/
    PCIDevice parent_obj;
    /*< public >*/

    PCNetState state;
    MemoryRegion io_bar;
} PCIPCNetState;

static void pcnet_aprom_writeb(void *opaque, uint32_t addr, uint32_t val)
{
    PCNetState *s = opaque;

    trace_pcnet_aprom_writeb(opaque, addr, val);
    if (BCR_APROMWE(s)) {
        s->prom[addr & 15] = val;
    }
}

static uint32_t pcnet_aprom_readb(void *opaque, uint32_t addr)
{
    PCNetState *s = opaque;
    uint32_t val = s->prom[addr & 15];

    trace_pcnet_aprom_readb(opaque, addr, val);
    return val;
}

static uint64_t pcnet_ioport_read(void *opaque, hwaddr addr,
                                  unsigned size)
{
    PCNetState *d = opaque;

    trace_pcnet_ioport_read(opaque, addr, size);
    if (addr < 0x10) {
        if (!BCR_DWIO(d) && size == 1) {
            return pcnet_aprom_readb(d, addr);
        } else if (!BCR_DWIO(d) && (addr & 1) == 0 && size == 2) {
            return pcnet_aprom_readb(d, addr) |
                   (pcnet_aprom_readb(d, addr + 1) << 8);
        } else if (BCR_DWIO(d) && (addr & 3) == 0 && size == 4) {
            return pcnet_aprom_readb(d, addr) |
                   (pcnet_aprom_readb(d, addr + 1) << 8) |
                   (pcnet_aprom_readb(d, addr + 2) << 16) |
                   (pcnet_aprom_readb(d, addr + 3) << 24);
        }
    } else {
        if (size == 2) {
            return pcnet_ioport_readw(d, addr);
        } else if (size == 4) {
            return pcnet_ioport_readl(d, addr);
        }
    }
    return ((uint64_t)1 << (size * 8)) - 1;
}

static void pcnet_ioport_write(void *opaque, hwaddr addr,
                               uint64_t data, unsigned size)
{
    PCNetState *d = opaque;

    trace_pcnet_ioport_write(opaque, addr, data, size);
    if (addr < 0x10) {
        if (!BCR_DWIO(d) && size == 1) {
            pcnet_aprom_writeb(d, addr, data);
        } else if (!BCR_DWIO(d) && (addr & 1) == 0 && size == 2) {
            pcnet_aprom_writeb(d, addr, data & 0xff);
            pcnet_aprom_writeb(d, addr + 1, data >> 8);
        } else if (BCR_DWIO(d) && (addr & 3) == 0 && size == 4) {
            pcnet_aprom_writeb(d, addr, data & 0xff);
            pcnet_aprom_writeb(d, addr + 1, (data >> 8) & 0xff);
            pcnet_aprom_writeb(d, addr + 2, (data >> 16) & 0xff);
            pcnet_aprom_writeb(d, addr + 3, data >> 24);
        }
    } else {
        if (size == 2) {
            pcnet_ioport_writew(d, addr, data);
        } else if (size == 4) {
            pcnet_ioport_writel(d, addr, data);
        }
    }
}

static const MemoryRegionOps pcnet_io_ops = {
    .read = pcnet_ioport_read,
    .write = pcnet_ioport_write,
    .endianness = DEVICE_LITTLE_ENDIAN,
};

static void pcnet_mmio_writeb(void *opaque, hwaddr addr, uint32_t val)
{
    PCNetState *d = opaque;

    trace_pcnet_mmio_writeb(opaque, addr, val);
    if (!(addr & 0x10))
        pcnet_aprom_writeb(d, addr & 0x0f, val);
}

static uint32_t pcnet_mmio_readb(void *opaque, hwaddr addr)
{
    PCNetState *d = opaque;
    uint32_t val = -1;

    if (!(addr & 0x10))
        val = pcnet_aprom_readb(d, addr & 0x0f);
    trace_pcnet_mmio_readb(opaque, addr, val);
    return val;
}

static void pcnet_mmio_writew(void *opaque, hwaddr addr, uint32_t val)
{
    PCNetState *d = opaque;

    trace_pcnet_mmio_writew(opaque, addr, val);
    if (addr & 0x10)
        pcnet_ioport_writew(d, addr & 0x0f, val);
    else {
        addr &= 0x0f;
        pcnet_aprom_writeb(d, addr, val & 0xff);
        pcnet_aprom_writeb(d, addr+1, (val & 0xff00) >> 8);
    }
}

static uint32_t pcnet_mmio_readw(void *opaque, hwaddr addr)
{
    PCNetState *d = opaque;
    uint32_t val = -1;

    if (addr & 0x10)
        val = pcnet_ioport_readw(d, addr & 0x0f);
    else {
        addr &= 0x0f;
        val = pcnet_aprom_readb(d, addr+1);
        val <<= 8;
        val |= pcnet_aprom_readb(d, addr);
    }
    trace_pcnet_mmio_readw(opaque, addr, val);
    return val;
}

static void pcnet_mmio_writel(void *opaque, hwaddr addr, uint32_t val)
{
    PCNetState *d = opaque;

    trace_pcnet_mmio_writel(opaque, addr, val);
    if (addr & 0x10)
        pcnet_ioport_writel(d, addr & 0x0f, val);
    else {
        addr &= 0x0f;
        pcnet_aprom_writeb(d, addr, val & 0xff);
        pcnet_aprom_writeb(d, addr+1, (val & 0xff00) >> 8);
        pcnet_aprom_writeb(d, addr+2, (val & 0xff0000) >> 16);
        pcnet_aprom_writeb(d, addr+3, (val & 0xff000000) >> 24);
    }
}

static uint32_t pcnet_mmio_readl(void *opaque, hwaddr addr)
{
    PCNetState *d = opaque;
    uint32_t val;

    if (addr & 0x10)
        val = pcnet_ioport_readl(d, addr & 0x0f);
    else {
        addr &= 0x0f;
        val = pcnet_aprom_readb(d, addr+3);
        val <<= 8;
        val |= pcnet_aprom_readb(d, addr+2);
        val <<= 8;
        val |= pcnet_aprom_readb(d, addr+1);
        val <<= 8;
        val |= pcnet_aprom_readb(d, addr);
    }
    trace_pcnet_mmio_readl(opaque, addr, val);
    return val;
}

static const VMStateDescription vmstate_pci_pcnet = {
    .name = "pcnet",
    .version_id = 3,
    .minimum_version_id = 2,
    .fields = (VMStateField[]) {
        VMSTATE_PCI_DEVICE(parent_obj, PCIPCNetState),
        VMSTATE_STRUCT(state, PCIPCNetState, 0, vmstate_pcnet, PCNetState),
        VMSTATE_END_OF_LIST()
    }
};

/* PCI interface */

static const MemoryRegionOps pcnet_mmio_ops = {
    .old_mmio = {
        .read = { pcnet_mmio_readb, pcnet_mmio_readw, pcnet_mmio_readl },
        .write = { pcnet_mmio_writeb, pcnet_mmio_writew, pcnet_mmio_writel },
    },
    .endianness = DEVICE_LITTLE_ENDIAN,
};

static void pci_physical_memory_write(void *dma_opaque, hwaddr addr,
                                      uint8_t *buf, int len, int do_bswap)
{
    pci_dma_write(dma_opaque, addr, buf, len);
}

static void pci_physical_memory_read(void *dma_opaque, hwaddr addr,
                                     uint8_t *buf, int len, int do_bswap)
{
    pci_dma_read(dma_opaque, addr, buf, len);
}

static void pci_pcnet_uninit(PCIDevice *dev)
{
    PCIPCNetState *d = PCI_PCNET(dev);

    qemu_free_irq(d->state.irq);
    timer_del(d->state.poll_timer);
    timer_free(d->state.poll_timer);
    qemu_del_nic(d->state.nic);
}

static NetClientInfo net_pci_pcnet_info = {
    .type = NET_CLIENT_DRIVER_NIC,
    .size = sizeof(NICState),
    .receive = pcnet_receive,
    .link_status_changed = pcnet_set_link_status,
};

static void pci_pcnet_realize(PCIDevice *pci_dev, Error **errp)
{
    PCIPCNetState *d = PCI_PCNET(pci_dev);
    PCNetState *s = &d->state;
    uint8_t *pci_conf;

#if 0
    printf("sizeof(RMD)=%d, sizeof(TMD)=%d\n",
        sizeof(struct pcnet_RMD), sizeof(struct pcnet_TMD));
#endif

    pci_conf = pci_dev->config;

    pci_set_word(pci_conf + PCI_STATUS,
                 PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MEDIUM);

    pci_set_word(pci_conf + PCI_SUBSYSTEM_VENDOR_ID, 0x0);
    pci_set_word(pci_conf + PCI_SUBSYSTEM_ID, 0x0);

    pci_conf[PCI_INTERRUPT_PIN] = 1; /* interrupt pin A */
    pci_conf[PCI_MIN_GNT] = 0x06;
    pci_conf[PCI_MAX_LAT] = 0xff;

    /* Handler for memory-mapped I/O */
    memory_region_init_io(&d->state.mmio, OBJECT(d), &pcnet_mmio_ops, s,
                          "pcnet-mmio", PCNET_PNPMMIO_SIZE);

    memory_region_init_io(&d->io_bar, OBJECT(d), &pcnet_io_ops, s, "pcnet-io",
                          PCNET_IOPORT_SIZE);
    pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &d->io_bar);

    pci_register_bar(pci_dev, 1, 0, &s->mmio);

    s->irq = pci_allocate_irq(pci_dev);
    s->phys_mem_read = pci_physical_memory_read;
    s->phys_mem_write = pci_physical_memory_write;
    s->dma_opaque = pci_dev;

    pcnet_common_init(DEVICE(pci_dev), s, &net_pci_pcnet_info);
}

static void pci_reset(DeviceState *dev)
{
    PCIPCNetState *d = PCI_PCNET(dev);

    pcnet_h_reset(&d->state);
}

static void pcnet_instance_init(Object *obj)
{
    PCIPCNetState *d = PCI_PCNET(obj);
    PCNetState *s = &d->state;

    device_add_bootindex_property(obj, &s->conf.bootindex,
                                  "bootindex", "/ethernet-phy@0",
                                  DEVICE(obj), NULL);
}

static Property pcnet_properties[] = {
    DEFINE_NIC_PROPERTIES(PCIPCNetState, state.conf),
    DEFINE_PROP_END_OF_LIST(),
};

static void pcnet_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);

    k->realize = pci_pcnet_realize;
    k->exit = pci_pcnet_uninit;
    k->romfile = "efi-pcnet.rom",
    k->vendor_id = PCI_VENDOR_ID_AMD;
    k->device_id = PCI_DEVICE_ID_AMD_LANCE;
    k->revision = 0x10;
    k->class_id = PCI_CLASS_NETWORK_ETHERNET;
    dc->reset = pci_reset;
    dc->vmsd = &vmstate_pci_pcnet;
    dc->props = pcnet_properties;
    set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
}

static const TypeInfo pcnet_info = {
    .name          = TYPE_PCI_PCNET,
    .parent        = TYPE_PCI_DEVICE,
    .instance_size = sizeof(PCIPCNetState),
    .class_init    = pcnet_class_init,
    .instance_init = pcnet_instance_init,
};

static void pci_pcnet_register_types(void)
{
    type_register_static(&pcnet_info);
}

type_init(pci_pcnet_register_types)
Commit	Line	Data
661a1799 PB	1	/*
	2	* QEMU AMD PC-Net II (Am79C970A) PCI emulation
	3	*
	4	* Copyright (c) 2004 Antony T Curtis
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
	24
	25	/* This software was written to be compatible with the specification:
	26	* AMD Am79C970A PCnet-PCI II Ethernet Controller Data-Sheet
	27	* AMD Publication# 19436 Rev:E Amendment/0 Issue Date: June 2000
	28	*/
	29
e8d40465	30	#include "qemu/osdep.h"
83c9f4ca	31	#include "hw/pci/pci.h"
1422e32d	32	#include "net/net.h"
83c9f4ca	33	#include "hw/loader.h"
1de7afc9	34	#include "qemu/timer.h"
9c17d615	35	#include "sysemu/dma.h"
ea3b3511	36	#include "sysemu/sysemu.h"
32c95249	37	#include "trace.h"
661a1799	38
47b43a1f	39	#include "pcnet.h"
661a1799 PB	40
	41	//#define PCNET_DEBUG
	42	//#define PCNET_DEBUG_IO
	43	//#define PCNET_DEBUG_BCR
	44	//#define PCNET_DEBUG_CSR
	45	//#define PCNET_DEBUG_RMD
	46	//#define PCNET_DEBUG_TMD
	47	//#define PCNET_DEBUG_MATCH
	48
1f8c7946 PC	49	#define TYPE_PCI_PCNET "pcnet"
	50
	51	#define PCI_PCNET(obj) \
	52	OBJECT_CHECK(PCIPCNetState, (obj), TYPE_PCI_PCNET)
661a1799 PB	53
661a1799 PB	54	typedef struct {
1f8c7946 PC	55	/< private >/
	56	PCIDevice parent_obj;
	57	/< public >/
	58
661a1799	59	PCNetState state;
bd8d6f7c	60	MemoryRegion io_bar;
661a1799 PB	61	} PCIPCNetState;
	62
	63	static void pcnet_aprom_writeb(void *opaque, uint32_t addr, uint32_t val)
	64	{
	65	PCNetState *s = opaque;
32c95249 DK	66
32c95249 DK	67	trace_pcnet_aprom_writeb(opaque, addr, val);
488a1a5d	68	if (BCR_APROMWE(s)) {
661a1799	69	s->prom[addr & 15] = val;
488a1a5d	70	}
661a1799 PB	71	}
	72
	73	static uint32_t pcnet_aprom_readb(void *opaque, uint32_t addr)
	74	{
	75	PCNetState *s = opaque;
	76	uint32_t val = s->prom[addr & 15];
32c95249 DK	77
32c95249 DK	78	trace_pcnet_aprom_readb(opaque, addr, val);
661a1799 PB	79	return val;
	80	}
	81
a8170e5e	82	static uint64_t pcnet_ioport_read(void *opaque, hwaddr addr,
bd8d6f7c	83	unsigned size)
661a1799	84	{
bd8d6f7c	85	PCNetState *d = opaque;
661a1799	86
32c95249	87	trace_pcnet_ioport_read(opaque, addr, size);
7ba79741 JK	88	if (addr < 0x10) {
	89	if (!BCR_DWIO(d) && size == 1) {
	90	return pcnet_aprom_readb(d, addr);
	91	} else if (!BCR_DWIO(d) && (addr & 1) == 0 && size == 2) {
	92	return pcnet_aprom_readb(d, addr) \|
	93	(pcnet_aprom_readb(d, addr + 1) << 8);
	94	} else if (BCR_DWIO(d) && (addr & 3) == 0 && size == 4) {
	95	return pcnet_aprom_readb(d, addr) \|
	96	(pcnet_aprom_readb(d, addr + 1) << 8) \|
	97	(pcnet_aprom_readb(d, addr + 2) << 16) \|
	98	(pcnet_aprom_readb(d, addr + 3) << 24);
	99	}
	100	} else {
	101	if (size == 2) {
	102	return pcnet_ioport_readw(d, addr);
	103	} else if (size == 4) {
	104	return pcnet_ioport_readl(d, addr);
	105	}
bd8d6f7c AK	106	}
	107	return ((uint64_t)1 << (size * 8)) - 1;
	108	}
661a1799	109
a8170e5e	110	static void pcnet_ioport_write(void *opaque, hwaddr addr,
bd8d6f7c AK	111	uint64_t data, unsigned size)
	112	{
	113	PCNetState *d = opaque;
661a1799	114
32c95249	115	trace_pcnet_ioport_write(opaque, addr, data, size);
7ba79741 JK	116	if (addr < 0x10) {
	117	if (!BCR_DWIO(d) && size == 1) {
	118	pcnet_aprom_writeb(d, addr, data);
	119	} else if (!BCR_DWIO(d) && (addr & 1) == 0 && size == 2) {
	120	pcnet_aprom_writeb(d, addr, data & 0xff);
	121	pcnet_aprom_writeb(d, addr + 1, data >> 8);
	122	} else if (BCR_DWIO(d) && (addr & 3) == 0 && size == 4) {
	123	pcnet_aprom_writeb(d, addr, data & 0xff);
	124	pcnet_aprom_writeb(d, addr + 1, (data >> 8) & 0xff);
	125	pcnet_aprom_writeb(d, addr + 2, (data >> 16) & 0xff);
	126	pcnet_aprom_writeb(d, addr + 3, data >> 24);
	127	}
	128	} else {
	129	if (size == 2) {
	130	pcnet_ioport_writew(d, addr, data);
	131	} else if (size == 4) {
	132	pcnet_ioport_writel(d, addr, data);
	133	}
bd8d6f7c	134	}
661a1799 PB	135	}
661a1799 PB	136
bd8d6f7c AK	137	static const MemoryRegionOps pcnet_io_ops = {
	138	.read = pcnet_ioport_read,
	139	.write = pcnet_ioport_write,
a26405b3	140	.endianness = DEVICE_LITTLE_ENDIAN,
bd8d6f7c AK	141	};
bd8d6f7c AK	142
a8170e5e	143	static void pcnet_mmio_writeb(void *opaque, hwaddr addr, uint32_t val)
661a1799 PB	144	{
661a1799 PB	145	PCNetState *d = opaque;
32c95249 DK	146
32c95249 DK	147	trace_pcnet_mmio_writeb(opaque, addr, val);
661a1799 PB	148	if (!(addr & 0x10))
	149	pcnet_aprom_writeb(d, addr & 0x0f, val);
	150	}
	151
a8170e5e	152	static uint32_t pcnet_mmio_readb(void *opaque, hwaddr addr)
661a1799 PB	153	{
	154	PCNetState *d = opaque;
	155	uint32_t val = -1;
32c95249	156
661a1799 PB	157	if (!(addr & 0x10))
661a1799 PB	158	val = pcnet_aprom_readb(d, addr & 0x0f);
32c95249	159	trace_pcnet_mmio_readb(opaque, addr, val);
661a1799 PB	160	return val;
	161	}
	162
a8170e5e	163	static void pcnet_mmio_writew(void *opaque, hwaddr addr, uint32_t val)
661a1799 PB	164	{
661a1799 PB	165	PCNetState *d = opaque;
32c95249 DK	166
32c95249 DK	167	trace_pcnet_mmio_writew(opaque, addr, val);
661a1799 PB	168	if (addr & 0x10)
	169	pcnet_ioport_writew(d, addr & 0x0f, val);
	170	else {
	171	addr &= 0x0f;
	172	pcnet_aprom_writeb(d, addr, val & 0xff);
	173	pcnet_aprom_writeb(d, addr+1, (val & 0xff00) >> 8);
	174	}
	175	}
	176
a8170e5e	177	static uint32_t pcnet_mmio_readw(void *opaque, hwaddr addr)
661a1799 PB	178	{
	179	PCNetState *d = opaque;
	180	uint32_t val = -1;
32c95249	181
661a1799 PB	182	if (addr & 0x10)
	183	val = pcnet_ioport_readw(d, addr & 0x0f);
	184	else {
	185	addr &= 0x0f;
	186	val = pcnet_aprom_readb(d, addr+1);
	187	val <<= 8;
	188	val \|= pcnet_aprom_readb(d, addr);
	189	}
32c95249	190	trace_pcnet_mmio_readw(opaque, addr, val);
661a1799 PB	191	return val;
	192	}
	193
a8170e5e	194	static void pcnet_mmio_writel(void *opaque, hwaddr addr, uint32_t val)
661a1799 PB	195	{
661a1799 PB	196	PCNetState *d = opaque;
32c95249 DK	197
32c95249 DK	198	trace_pcnet_mmio_writel(opaque, addr, val);
661a1799 PB	199	if (addr & 0x10)
	200	pcnet_ioport_writel(d, addr & 0x0f, val);
	201	else {
	202	addr &= 0x0f;
	203	pcnet_aprom_writeb(d, addr, val & 0xff);
	204	pcnet_aprom_writeb(d, addr+1, (val & 0xff00) >> 8);
	205	pcnet_aprom_writeb(d, addr+2, (val & 0xff0000) >> 16);
	206	pcnet_aprom_writeb(d, addr+3, (val & 0xff000000) >> 24);
	207	}
	208	}
	209
a8170e5e	210	static uint32_t pcnet_mmio_readl(void *opaque, hwaddr addr)
661a1799 PB	211	{
	212	PCNetState *d = opaque;
	213	uint32_t val;
32c95249	214
661a1799 PB	215	if (addr & 0x10)
	216	val = pcnet_ioport_readl(d, addr & 0x0f);
	217	else {
	218	addr &= 0x0f;
	219	val = pcnet_aprom_readb(d, addr+3);
	220	val <<= 8;
	221	val \|= pcnet_aprom_readb(d, addr+2);
	222	val <<= 8;
	223	val \|= pcnet_aprom_readb(d, addr+1);
	224	val <<= 8;
	225	val \|= pcnet_aprom_readb(d, addr);
	226	}
32c95249	227	trace_pcnet_mmio_readl(opaque, addr, val);
661a1799 PB	228	return val;
	229	}
	230
	231	static const VMStateDescription vmstate_pci_pcnet = {
	232	.name = "pcnet",
	233	.version_id = 3,
	234	.minimum_version_id = 2,
d49805ae	235	.fields = (VMStateField[]) {
1f8c7946	236	VMSTATE_PCI_DEVICE(parent_obj, PCIPCNetState),
661a1799 PB	237	VMSTATE_STRUCT(state, PCIPCNetState, 0, vmstate_pcnet, PCNetState),
	238	VMSTATE_END_OF_LIST()
	239	}
	240	};
	241
	242	/* PCI interface */
	243
bd8d6f7c AK	244	static const MemoryRegionOps pcnet_mmio_ops = {
	245	.old_mmio = {
	246	.read = { pcnet_mmio_readb, pcnet_mmio_readw, pcnet_mmio_readl },
	247	.write = { pcnet_mmio_writeb, pcnet_mmio_writew, pcnet_mmio_writel },
	248	},
a26405b3	249	.endianness = DEVICE_LITTLE_ENDIAN,
661a1799 PB	250	};
661a1799 PB	251
a8170e5e	252	static void pci_physical_memory_write(void *dma_opaque, hwaddr addr,
661a1799 PB	253	uint8_t *buf, int len, int do_bswap)
661a1799 PB	254	{
14fecf26	255	pci_dma_write(dma_opaque, addr, buf, len);
661a1799 PB	256	}
661a1799 PB	257
a8170e5e	258	static void pci_physical_memory_read(void *dma_opaque, hwaddr addr,
661a1799 PB	259	uint8_t *buf, int len, int do_bswap)
661a1799 PB	260	{
14fecf26	261	pci_dma_read(dma_opaque, addr, buf, len);
661a1799 PB	262	}
661a1799 PB	263
f90c2bcd	264	static void pci_pcnet_uninit(PCIDevice *dev)
661a1799	265	{
1f8c7946	266	PCIPCNetState *d = PCI_PCNET(dev);
661a1799	267
9e64f8a3	268	qemu_free_irq(d->state.irq);
bc72ad67 AB	269	timer_del(d->state.poll_timer);
bc72ad67 AB	270	timer_free(d->state.poll_timer);
948ecf21	271	qemu_del_nic(d->state.nic);
661a1799 PB	272	}
	273
	274	static NetClientInfo net_pci_pcnet_info = {
f394b2e2	275	.type = NET_CLIENT_DRIVER_NIC,
661a1799	276	.size = sizeof(NICState),
661a1799	277	.receive = pcnet_receive,
e1c2008a	278	.link_status_changed = pcnet_set_link_status,
661a1799 PB	279	};
661a1799 PB	280
eb1bef94	281	static void pci_pcnet_realize(PCIDevice pci_dev, Error *errp)
661a1799	282	{
1f8c7946	283	PCIPCNetState *d = PCI_PCNET(pci_dev);
661a1799 PB	284	PCNetState *s = &d->state;
	285	uint8_t *pci_conf;
	286
	287	#if 0
	288	printf("sizeof(RMD)=%d, sizeof(TMD)=%d\n",
	289	sizeof(struct pcnet_RMD), sizeof(struct pcnet_TMD));
	290	#endif
	291
	292	pci_conf = pci_dev->config;
	293
661a1799 PB	294	pci_set_word(pci_conf + PCI_STATUS,
661a1799 PB	295	PCI_STATUS_FAST_BACK \| PCI_STATUS_DEVSEL_MEDIUM);
661a1799 PB	296
	297	pci_set_word(pci_conf + PCI_SUBSYSTEM_VENDOR_ID, 0x0);
	298	pci_set_word(pci_conf + PCI_SUBSYSTEM_ID, 0x0);
	299
817e0b6f	300	pci_conf[PCI_INTERRUPT_PIN] = 1; /* interrupt pin A */
661a1799 PB	301	pci_conf[PCI_MIN_GNT] = 0x06;
	302	pci_conf[PCI_MAX_LAT] = 0xff;
	303
	304	/* Handler for memory-mapped I/O */
eedfac6f PB	305	memory_region_init_io(&d->state.mmio, OBJECT(d), &pcnet_mmio_ops, s,
eedfac6f PB	306	"pcnet-mmio", PCNET_PNPMMIO_SIZE);
661a1799	307
eedfac6f	308	memory_region_init_io(&d->io_bar, OBJECT(d), &pcnet_io_ops, s, "pcnet-io",
bd8d6f7c	309	PCNET_IOPORT_SIZE);
e824b2cc	310	pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &d->io_bar);
661a1799	311
e824b2cc	312	pci_register_bar(pci_dev, 1, 0, &s->mmio);
661a1799	313
9e64f8a3	314	s->irq = pci_allocate_irq(pci_dev);
661a1799 PB	315	s->phys_mem_read = pci_physical_memory_read;
661a1799 PB	316	s->phys_mem_write = pci_physical_memory_write;
14fecf26	317	s->dma_opaque = pci_dev;
661a1799	318
4c3b2245	319	pcnet_common_init(DEVICE(pci_dev), s, &net_pci_pcnet_info);
661a1799 PB	320	}
	321
	322	static void pci_reset(DeviceState *dev)
	323	{
1f8c7946	324	PCIPCNetState *d = PCI_PCNET(dev);
661a1799 PB	325
	326	pcnet_h_reset(&d->state);
	327	}
	328
ea3b3511 GA	329	static void pcnet_instance_init(Object *obj)
	330	{
	331	PCIPCNetState *d = PCI_PCNET(obj);
	332	PCNetState *s = &d->state;
	333
	334	device_add_bootindex_property(obj, &s->conf.bootindex,
	335	"bootindex", "/ethernet-phy@0",
	336	DEVICE(obj), NULL);
	337	}
	338
40021f08 AL	339	static Property pcnet_properties[] = {
	340	DEFINE_NIC_PROPERTIES(PCIPCNetState, state.conf),
	341	DEFINE_PROP_END_OF_LIST(),
	342	};
	343
	344	static void pcnet_class_init(ObjectClass klass, void data)
	345	{
39bffca2	346	DeviceClass *dc = DEVICE_CLASS(klass);
40021f08 AL	347	PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
40021f08 AL	348
eb1bef94	349	k->realize = pci_pcnet_realize;
40021f08	350	k->exit = pci_pcnet_uninit;
c45e5b5b	351	k->romfile = "efi-pcnet.rom",
40021f08 AL	352	k->vendor_id = PCI_VENDOR_ID_AMD;
	353	k->device_id = PCI_DEVICE_ID_AMD_LANCE;
	354	k->revision = 0x10;
	355	k->class_id = PCI_CLASS_NETWORK_ETHERNET;
39bffca2 AL	356	dc->reset = pci_reset;
	357	dc->vmsd = &vmstate_pci_pcnet;
	358	dc->props = pcnet_properties;
125ee0ed	359	set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
40021f08 AL	360	}
40021f08 AL	361
8c43a6f0	362	static const TypeInfo pcnet_info = {
1f8c7946	363	.name = TYPE_PCI_PCNET,
39bffca2 AL	364	.parent = TYPE_PCI_DEVICE,
	365	.instance_size = sizeof(PCIPCNetState),
	366	.class_init = pcnet_class_init,
ea3b3511	367	.instance_init = pcnet_instance_init,
661a1799 PB	368	};
661a1799 PB	369
83f7d43a	370	static void pci_pcnet_register_types(void)
661a1799	371	{
39bffca2	372	type_register_static(&pcnet_info);
661a1799 PB	373	}
661a1799 PB	374
83f7d43a	375	type_init(pci_pcnet_register_types)