[qemu.git] / hw / pcnet-pci.c

/*
 * QEMU AMD PC-Net II (Am79C970A) PCI emulation
 *
 * Copyright (c) 2004 Antony T Curtis
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

/* This software was written to be compatible with the specification:
 * AMD Am79C970A PCnet-PCI II Ethernet Controller Data-Sheet
 * AMD Publication# 19436  Rev:E  Amendment/0  Issue Date: June 2000
 */

#include "pci.h"
#include "net.h"
#include "loader.h"
#include "qemu-timer.h"
#include "dma.h"

#include "pcnet.h"

//#define PCNET_DEBUG
//#define PCNET_DEBUG_IO
//#define PCNET_DEBUG_BCR
//#define PCNET_DEBUG_CSR
//#define PCNET_DEBUG_RMD
//#define PCNET_DEBUG_TMD
//#define PCNET_DEBUG_MATCH


typedef struct {
    PCIDevice pci_dev;
    PCNetState state;
    MemoryRegion io_bar;
} PCIPCNetState;

static void pcnet_aprom_writeb(void *opaque, uint32_t addr, uint32_t val)
{
    PCNetState *s = opaque;
#ifdef PCNET_DEBUG
    printf("pcnet_aprom_writeb addr=0x%08x val=0x%02x\n", addr, val);
#endif
    /* Check APROMWE bit to enable write access */
    if (pcnet_bcr_readw(s,2) & 0x100)
        s->prom[addr & 15] = val;
}

static uint32_t pcnet_aprom_readb(void *opaque, uint32_t addr)
{
    PCNetState *s = opaque;
    uint32_t val = s->prom[addr & 15];
#ifdef PCNET_DEBUG
    printf("pcnet_aprom_readb addr=0x%08x val=0x%02x\n", addr, val);
#endif
    return val;
}

static uint64_t pcnet_ioport_read(void *opaque, target_phys_addr_t addr,
                                  unsigned size)
{
    PCNetState *d = opaque;

    if (addr < 16 && size == 1) {
        return pcnet_aprom_readb(d, addr);
    } else if (addr >= 0x10 && addr < 0x20 && size == 2) {
        return pcnet_ioport_readw(d, addr);
    } else if (addr >= 0x10 && addr < 0x20 && size == 4) {
        return pcnet_ioport_readl(d, addr);
    }
    return ((uint64_t)1 << (size * 8)) - 1;
}

static void pcnet_ioport_write(void *opaque, target_phys_addr_t addr,
                               uint64_t data, unsigned size)
{
    PCNetState *d = opaque;

    if (addr < 16 && size == 1) {
        return pcnet_aprom_writeb(d, addr, data);
    } else if (addr >= 0x10 && addr < 0x20 && size == 2) {
        return pcnet_ioport_writew(d, addr, data);
    } else if (addr >= 0x10 && addr < 0x20 && size == 4) {
        return pcnet_ioport_writel(d, addr, data);
    }
}

static const MemoryRegionOps pcnet_io_ops = {
    .read = pcnet_ioport_read,
    .write = pcnet_ioport_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

static void pcnet_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
{
    PCNetState *d = opaque;
#ifdef PCNET_DEBUG_IO
    printf("pcnet_mmio_writeb addr=0x" TARGET_FMT_plx" val=0x%02x\n", addr,
           val);
#endif
    if (!(addr & 0x10))
        pcnet_aprom_writeb(d, addr & 0x0f, val);
}

static uint32_t pcnet_mmio_readb(void *opaque, target_phys_addr_t addr)
{
    PCNetState *d = opaque;
    uint32_t val = -1;
    if (!(addr & 0x10))
        val = pcnet_aprom_readb(d, addr & 0x0f);
#ifdef PCNET_DEBUG_IO
    printf("pcnet_mmio_readb addr=0x" TARGET_FMT_plx " val=0x%02x\n", addr,
           val & 0xff);
#endif
    return val;
}

static void pcnet_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
{
    PCNetState *d = opaque;
#ifdef PCNET_DEBUG_IO
    printf("pcnet_mmio_writew addr=0x" TARGET_FMT_plx " val=0x%04x\n", addr,
           val);
#endif
    if (addr & 0x10)
        pcnet_ioport_writew(d, addr & 0x0f, val);
    else {
        addr &= 0x0f;
        pcnet_aprom_writeb(d, addr, val & 0xff);
        pcnet_aprom_writeb(d, addr+1, (val & 0xff00) >> 8);
    }
}

static uint32_t pcnet_mmio_readw(void *opaque, target_phys_addr_t addr)
{
    PCNetState *d = opaque;
    uint32_t val = -1;
    if (addr & 0x10)
        val = pcnet_ioport_readw(d, addr & 0x0f);
    else {
        addr &= 0x0f;
        val = pcnet_aprom_readb(d, addr+1);
        val <<= 8;
        val |= pcnet_aprom_readb(d, addr);
    }
#ifdef PCNET_DEBUG_IO
    printf("pcnet_mmio_readw addr=0x" TARGET_FMT_plx" val = 0x%04x\n", addr,
           val & 0xffff);
#endif
    return val;
}

static void pcnet_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
{
    PCNetState *d = opaque;
#ifdef PCNET_DEBUG_IO
    printf("pcnet_mmio_writel addr=0x" TARGET_FMT_plx" val=0x%08x\n", addr,
           val);
#endif
    if (addr & 0x10)
        pcnet_ioport_writel(d, addr & 0x0f, val);
    else {
        addr &= 0x0f;
        pcnet_aprom_writeb(d, addr, val & 0xff);
        pcnet_aprom_writeb(d, addr+1, (val & 0xff00) >> 8);
        pcnet_aprom_writeb(d, addr+2, (val & 0xff0000) >> 16);
        pcnet_aprom_writeb(d, addr+3, (val & 0xff000000) >> 24);
    }
}

static uint32_t pcnet_mmio_readl(void *opaque, target_phys_addr_t addr)
{
    PCNetState *d = opaque;
    uint32_t val;
    if (addr & 0x10)
        val = pcnet_ioport_readl(d, addr & 0x0f);
    else {
        addr &= 0x0f;
        val = pcnet_aprom_readb(d, addr+3);
        val <<= 8;
        val |= pcnet_aprom_readb(d, addr+2);
        val <<= 8;
        val |= pcnet_aprom_readb(d, addr+1);
        val <<= 8;
        val |= pcnet_aprom_readb(d, addr);
    }
#ifdef PCNET_DEBUG_IO
    printf("pcnet_mmio_readl addr=0x" TARGET_FMT_plx " val=0x%08x\n", addr,
           val);
#endif
    return val;
}

static const VMStateDescription vmstate_pci_pcnet = {
    .name = "pcnet",
    .version_id = 3,
    .minimum_version_id = 2,
    .minimum_version_id_old = 2,
    .fields      = (VMStateField []) {
        VMSTATE_PCI_DEVICE(pci_dev, PCIPCNetState),
        VMSTATE_STRUCT(state, PCIPCNetState, 0, vmstate_pcnet, PCNetState),
        VMSTATE_END_OF_LIST()
    }
};

/* PCI interface */

static const MemoryRegionOps pcnet_mmio_ops = {
    .old_mmio = {
        .read = { pcnet_mmio_readb, pcnet_mmio_readw, pcnet_mmio_readl },
        .write = { pcnet_mmio_writeb, pcnet_mmio_writew, pcnet_mmio_writel },
    },
    .endianness = DEVICE_NATIVE_ENDIAN,
};

static void pci_physical_memory_write(void *dma_opaque, target_phys_addr_t addr,
                                      uint8_t *buf, int len, int do_bswap)
{
    pci_dma_write(dma_opaque, addr, buf, len);
}

static void pci_physical_memory_read(void *dma_opaque, target_phys_addr_t addr,
                                     uint8_t *buf, int len, int do_bswap)
{
    pci_dma_read(dma_opaque, addr, buf, len);
}

static void pci_pcnet_cleanup(VLANClientState *nc)
{
    PCNetState *d = DO_UPCAST(NICState, nc, nc)->opaque;

    pcnet_common_cleanup(d);
}

static int pci_pcnet_uninit(PCIDevice *dev)
{
    PCIPCNetState *d = DO_UPCAST(PCIPCNetState, pci_dev, dev);

    memory_region_destroy(&d->state.mmio);
    memory_region_destroy(&d->io_bar);
    qemu_del_timer(d->state.poll_timer);
    qemu_free_timer(d->state.poll_timer);
    qemu_del_vlan_client(&d->state.nic->nc);
    return 0;
}

static NetClientInfo net_pci_pcnet_info = {
    .type = NET_CLIENT_TYPE_NIC,
    .size = sizeof(NICState),
    .can_receive = pcnet_can_receive,
    .receive = pcnet_receive,
    .cleanup = pci_pcnet_cleanup,
};

static int pci_pcnet_init(PCIDevice *pci_dev)
{
    PCIPCNetState *d = DO_UPCAST(PCIPCNetState, pci_dev, pci_dev);
    PCNetState *s = &d->state;
    uint8_t *pci_conf;

#if 0
    printf("sizeof(RMD)=%d, sizeof(TMD)=%d\n",
        sizeof(struct pcnet_RMD), sizeof(struct pcnet_TMD));
#endif

    pci_conf = pci_dev->config;

    pci_set_word(pci_conf + PCI_STATUS,
                 PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MEDIUM);

    pci_set_word(pci_conf + PCI_SUBSYSTEM_VENDOR_ID, 0x0);
    pci_set_word(pci_conf + PCI_SUBSYSTEM_ID, 0x0);

    pci_conf[PCI_INTERRUPT_PIN] = 1; /* interrupt pin A */
    pci_conf[PCI_MIN_GNT] = 0x06;
    pci_conf[PCI_MAX_LAT] = 0xff;

    /* Handler for memory-mapped I/O */
    memory_region_init_io(&d->state.mmio, &pcnet_mmio_ops, s, "pcnet-mmio",
                          PCNET_PNPMMIO_SIZE);

    memory_region_init_io(&d->io_bar, &pcnet_io_ops, s, "pcnet-io",
                          PCNET_IOPORT_SIZE);
    pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &d->io_bar);

    pci_register_bar(pci_dev, 1, 0, &s->mmio);

    s->irq = pci_dev->irq[0];
    s->phys_mem_read = pci_physical_memory_read;
    s->phys_mem_write = pci_physical_memory_write;
    s->dma_opaque = pci_dev;

    if (!pci_dev->qdev.hotplugged) {
        static int loaded = 0;
        if (!loaded) {
            rom_add_option("pxe-pcnet.rom", -1);
            loaded = 1;
        }
    }

    return pcnet_common_init(&pci_dev->qdev, s, &net_pci_pcnet_info);
}

static void pci_reset(DeviceState *dev)
{
    PCIPCNetState *d = DO_UPCAST(PCIPCNetState, pci_dev.qdev, dev);

    pcnet_h_reset(&d->state);
}

static PCIDeviceInfo pcnet_info = {
    .qdev.name  = "pcnet",
    .qdev.size  = sizeof(PCIPCNetState),
    .qdev.reset = pci_reset,
    .qdev.vmsd  = &vmstate_pci_pcnet,
    .init       = pci_pcnet_init,
    .exit       = pci_pcnet_uninit,
    .vendor_id  = PCI_VENDOR_ID_AMD,
    .device_id  = PCI_DEVICE_ID_AMD_LANCE,
    .revision   = 0x10,
    .class_id   = PCI_CLASS_NETWORK_ETHERNET,
    .qdev.props = (Property[]) {
        DEFINE_NIC_PROPERTIES(PCIPCNetState, state.conf),
        DEFINE_PROP_END_OF_LIST(),
    }
};

static void pci_pcnet_register_devices(void)
{
    pci_qdev_register(&pcnet_info);
}

device_init(pci_pcnet_register_devices)
Commit	Line	Data
661a1799 PB	1	/*
	2	* QEMU AMD PC-Net II (Am79C970A) PCI emulation
	3	*
	4	* Copyright (c) 2004 Antony T Curtis
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
	24
	25	/* This software was written to be compatible with the specification:
	26	* AMD Am79C970A PCnet-PCI II Ethernet Controller Data-Sheet
	27	* AMD Publication# 19436 Rev:E Amendment/0 Issue Date: June 2000
	28	*/
	29
	30	#include "pci.h"
	31	#include "net.h"
	32	#include "loader.h"
	33	#include "qemu-timer.h"
14fecf26	34	#include "dma.h"
661a1799 PB	35
	36	#include "pcnet.h"
	37
	38	//#define PCNET_DEBUG
	39	//#define PCNET_DEBUG_IO
	40	//#define PCNET_DEBUG_BCR
	41	//#define PCNET_DEBUG_CSR
	42	//#define PCNET_DEBUG_RMD
	43	//#define PCNET_DEBUG_TMD
	44	//#define PCNET_DEBUG_MATCH
	45
	46
	47	typedef struct {
	48	PCIDevice pci_dev;
	49	PCNetState state;
bd8d6f7c	50	MemoryRegion io_bar;
661a1799 PB	51	} PCIPCNetState;
	52
	53	static void pcnet_aprom_writeb(void *opaque, uint32_t addr, uint32_t val)
	54	{
	55	PCNetState *s = opaque;
	56	#ifdef PCNET_DEBUG
	57	printf("pcnet_aprom_writeb addr=0x%08x val=0x%02x\n", addr, val);
	58	#endif
	59	/* Check APROMWE bit to enable write access */
	60	if (pcnet_bcr_readw(s,2) & 0x100)
	61	s->prom[addr & 15] = val;
	62	}
	63
	64	static uint32_t pcnet_aprom_readb(void *opaque, uint32_t addr)
	65	{
	66	PCNetState *s = opaque;
	67	uint32_t val = s->prom[addr & 15];
	68	#ifdef PCNET_DEBUG
	69	printf("pcnet_aprom_readb addr=0x%08x val=0x%02x\n", addr, val);
	70	#endif
	71	return val;
	72	}
	73
bd8d6f7c AK	74	static uint64_t pcnet_ioport_read(void *opaque, target_phys_addr_t addr,
bd8d6f7c AK	75	unsigned size)
661a1799	76	{
bd8d6f7c	77	PCNetState *d = opaque;
661a1799	78
bd8d6f7c AK	79	if (addr < 16 && size == 1) {
	80	return pcnet_aprom_readb(d, addr);
	81	} else if (addr >= 0x10 && addr < 0x20 && size == 2) {
	82	return pcnet_ioport_readw(d, addr);
	83	} else if (addr >= 0x10 && addr < 0x20 && size == 4) {
	84	return pcnet_ioport_readl(d, addr);
	85	}
	86	return ((uint64_t)1 << (size * 8)) - 1;
	87	}
661a1799	88
bd8d6f7c AK	89	static void pcnet_ioport_write(void *opaque, target_phys_addr_t addr,
	90	uint64_t data, unsigned size)
	91	{
	92	PCNetState *d = opaque;
661a1799	93
bd8d6f7c AK	94	if (addr < 16 && size == 1) {
	95	return pcnet_aprom_writeb(d, addr, data);
	96	} else if (addr >= 0x10 && addr < 0x20 && size == 2) {
	97	return pcnet_ioport_writew(d, addr, data);
	98	} else if (addr >= 0x10 && addr < 0x20 && size == 4) {
	99	return pcnet_ioport_writel(d, addr, data);
	100	}
661a1799 PB	101	}
661a1799 PB	102
bd8d6f7c AK	103	static const MemoryRegionOps pcnet_io_ops = {
	104	.read = pcnet_ioport_read,
	105	.write = pcnet_ioport_write,
	106	.endianness = DEVICE_NATIVE_ENDIAN,
	107	};
	108
661a1799 PB	109	static void pcnet_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
	110	{
	111	PCNetState *d = opaque;
	112	#ifdef PCNET_DEBUG_IO
	113	printf("pcnet_mmio_writeb addr=0x" TARGET_FMT_plx" val=0x%02x\n", addr,
	114	val);
	115	#endif
	116	if (!(addr & 0x10))
	117	pcnet_aprom_writeb(d, addr & 0x0f, val);
	118	}
	119
	120	static uint32_t pcnet_mmio_readb(void *opaque, target_phys_addr_t addr)
	121	{
	122	PCNetState *d = opaque;
	123	uint32_t val = -1;
	124	if (!(addr & 0x10))
	125	val = pcnet_aprom_readb(d, addr & 0x0f);
	126	#ifdef PCNET_DEBUG_IO
	127	printf("pcnet_mmio_readb addr=0x" TARGET_FMT_plx " val=0x%02x\n", addr,
	128	val & 0xff);
	129	#endif
	130	return val;
	131	}
	132
	133	static void pcnet_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
	134	{
	135	PCNetState *d = opaque;
	136	#ifdef PCNET_DEBUG_IO
	137	printf("pcnet_mmio_writew addr=0x" TARGET_FMT_plx " val=0x%04x\n", addr,
	138	val);
	139	#endif
	140	if (addr & 0x10)
	141	pcnet_ioport_writew(d, addr & 0x0f, val);
	142	else {
	143	addr &= 0x0f;
	144	pcnet_aprom_writeb(d, addr, val & 0xff);
	145	pcnet_aprom_writeb(d, addr+1, (val & 0xff00) >> 8);
	146	}
	147	}
	148
	149	static uint32_t pcnet_mmio_readw(void *opaque, target_phys_addr_t addr)
	150	{
	151	PCNetState *d = opaque;
	152	uint32_t val = -1;
	153	if (addr & 0x10)
	154	val = pcnet_ioport_readw(d, addr & 0x0f);
	155	else {
	156	addr &= 0x0f;
	157	val = pcnet_aprom_readb(d, addr+1);
	158	val <<= 8;
	159	val \|= pcnet_aprom_readb(d, addr);
	160	}
	161	#ifdef PCNET_DEBUG_IO
	162	printf("pcnet_mmio_readw addr=0x" TARGET_FMT_plx" val = 0x%04x\n", addr,
	163	val & 0xffff);
	164	#endif
	165	return val;
	166	}
	167
	168	static void pcnet_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
	169	{
	170	PCNetState *d = opaque;
	171	#ifdef PCNET_DEBUG_IO
	172	printf("pcnet_mmio_writel addr=0x" TARGET_FMT_plx" val=0x%08x\n", addr,
173	val);
174	#endif
175	if (addr & 0x10)
176	pcnet_ioport_writel(d, addr & 0x0f, val);
177	else {
178	addr &= 0x0f;
179	pcnet_aprom_writeb(d, addr, val & 0xff);
180	pcnet_aprom_writeb(d, addr+1, (val & 0xff00) >> 8);
181	pcnet_aprom_writeb(d, addr+2, (val & 0xff0000) >> 16);
182	pcnet_aprom_writeb(d, addr+3, (val & 0xff000000) >> 24);
183	}
184	}
185
186	static uint32_t pcnet_mmio_readl(void *opaque, target_phys_addr_t addr)
187	{
188	PCNetState *d = opaque;
189	uint32_t val;
190	if (addr & 0x10)
191	val = pcnet_ioport_readl(d, addr & 0x0f);
192	else {
193	addr &= 0x0f;
194	val = pcnet_aprom_readb(d, addr+3);
195	val <<= 8;
196	val \|= pcnet_aprom_readb(d, addr+2);
197	val <<= 8;
198	val \|= pcnet_aprom_readb(d, addr+1);
199	val <<= 8;
200	val \|= pcnet_aprom_readb(d, addr);
201	}
202	#ifdef PCNET_DEBUG_IO
203	printf("pcnet_mmio_readl addr=0x" TARGET_FMT_plx " val=0x%08x\n", addr,
204	val);
205	#endif
206	return val;
207	}
208
209	static const VMStateDescription vmstate_pci_pcnet = {
210	.name = "pcnet",
211	.version_id = 3,
212	.minimum_version_id = 2,
213	.minimum_version_id_old = 2,
214	.fields = (VMStateField []) {
215	VMSTATE_PCI_DEVICE(pci_dev, PCIPCNetState),
216	VMSTATE_STRUCT(state, PCIPCNetState, 0, vmstate_pcnet, PCNetState),
217	VMSTATE_END_OF_LIST()
218	}
219	};
220
221	/* PCI interface */
222
bd8d6f7c AK	223	static const MemoryRegionOps pcnet_mmio_ops = {
	224	.old_mmio = {
	225	.read = { pcnet_mmio_readb, pcnet_mmio_readw, pcnet_mmio_readl },
	226	.write = { pcnet_mmio_writeb, pcnet_mmio_writew, pcnet_mmio_writel },
	227	},
	228	.endianness = DEVICE_NATIVE_ENDIAN,
661a1799 PB	229	};
661a1799 PB	230
661a1799 PB	231	static void pci_physical_memory_write(void *dma_opaque, target_phys_addr_t addr,
	232	uint8_t *buf, int len, int do_bswap)
	233	{
14fecf26	234	pci_dma_write(dma_opaque, addr, buf, len);
661a1799 PB	235	}
	236
	237	static void pci_physical_memory_read(void *dma_opaque, target_phys_addr_t addr,
	238	uint8_t *buf, int len, int do_bswap)
	239	{
14fecf26	240	pci_dma_read(dma_opaque, addr, buf, len);
661a1799 PB	241	}
	242
	243	static void pci_pcnet_cleanup(VLANClientState *nc)
	244	{
	245	PCNetState *d = DO_UPCAST(NICState, nc, nc)->opaque;
	246
	247	pcnet_common_cleanup(d);
	248	}
	249
	250	static int pci_pcnet_uninit(PCIDevice *dev)
	251	{
	252	PCIPCNetState *d = DO_UPCAST(PCIPCNetState, pci_dev, dev);
	253
bd8d6f7c AK	254	memory_region_destroy(&d->state.mmio);
bd8d6f7c AK	255	memory_region_destroy(&d->io_bar);
661a1799 PB	256	qemu_del_timer(d->state.poll_timer);
	257	qemu_free_timer(d->state.poll_timer);
	258	qemu_del_vlan_client(&d->state.nic->nc);
	259	return 0;
	260	}
	261
	262	static NetClientInfo net_pci_pcnet_info = {
	263	.type = NET_CLIENT_TYPE_NIC,
	264	.size = sizeof(NICState),
	265	.can_receive = pcnet_can_receive,
	266	.receive = pcnet_receive,
	267	.cleanup = pci_pcnet_cleanup,
	268	};
	269
	270	static int pci_pcnet_init(PCIDevice *pci_dev)
	271	{
	272	PCIPCNetState *d = DO_UPCAST(PCIPCNetState, pci_dev, pci_dev);
	273	PCNetState *s = &d->state;
	274	uint8_t *pci_conf;
	275
	276	#if 0
	277	printf("sizeof(RMD)=%d, sizeof(TMD)=%d\n",
	278	sizeof(struct pcnet_RMD), sizeof(struct pcnet_TMD));
	279	#endif
	280
	281	pci_conf = pci_dev->config;
	282
661a1799 PB	283	pci_set_word(pci_conf + PCI_STATUS,
661a1799 PB	284	PCI_STATUS_FAST_BACK \| PCI_STATUS_DEVSEL_MEDIUM);
661a1799 PB	285
	286	pci_set_word(pci_conf + PCI_SUBSYSTEM_VENDOR_ID, 0x0);
	287	pci_set_word(pci_conf + PCI_SUBSYSTEM_ID, 0x0);
	288
817e0b6f	289	pci_conf[PCI_INTERRUPT_PIN] = 1; /* interrupt pin A */
661a1799 PB	290	pci_conf[PCI_MIN_GNT] = 0x06;
	291	pci_conf[PCI_MAX_LAT] = 0xff;
	292
	293	/* Handler for memory-mapped I/O */
145aebec	294	memory_region_init_io(&d->state.mmio, &pcnet_mmio_ops, s, "pcnet-mmio",
bd8d6f7c	295	PCNET_PNPMMIO_SIZE);
661a1799	296
145aebec	297	memory_region_init_io(&d->io_bar, &pcnet_io_ops, s, "pcnet-io",
bd8d6f7c	298	PCNET_IOPORT_SIZE);
e824b2cc	299	pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &d->io_bar);
661a1799	300
e824b2cc	301	pci_register_bar(pci_dev, 1, 0, &s->mmio);
661a1799 PB	302
	303	s->irq = pci_dev->irq[0];
	304	s->phys_mem_read = pci_physical_memory_read;
	305	s->phys_mem_write = pci_physical_memory_write;
14fecf26	306	s->dma_opaque = pci_dev;
661a1799 PB	307
	308	if (!pci_dev->qdev.hotplugged) {
	309	static int loaded = 0;
	310	if (!loaded) {
5ee8ad71	311	rom_add_option("pxe-pcnet.rom", -1);
661a1799 PB	312	loaded = 1;
	313	}
	314	}
	315
	316	return pcnet_common_init(&pci_dev->qdev, s, &net_pci_pcnet_info);
	317	}
	318
	319	static void pci_reset(DeviceState *dev)
	320	{
	321	PCIPCNetState *d = DO_UPCAST(PCIPCNetState, pci_dev.qdev, dev);
	322
	323	pcnet_h_reset(&d->state);
	324	}
	325
	326	static PCIDeviceInfo pcnet_info = {
	327	.qdev.name = "pcnet",
	328	.qdev.size = sizeof(PCIPCNetState),
	329	.qdev.reset = pci_reset,
	330	.qdev.vmsd = &vmstate_pci_pcnet,
	331	.init = pci_pcnet_init,
	332	.exit = pci_pcnet_uninit,
d7dccd11 IY	333	.vendor_id = PCI_VENDOR_ID_AMD,
	334	.device_id = PCI_DEVICE_ID_AMD_LANCE,
	335	.revision = 0x10,
	336	.class_id = PCI_CLASS_NETWORK_ETHERNET,
661a1799 PB	337	.qdev.props = (Property[]) {
	338	DEFINE_NIC_PROPERTIES(PCIPCNetState, state.conf),
	339	DEFINE_PROP_END_OF_LIST(),
	340	}
	341	};
	342
	343	static void pci_pcnet_register_devices(void)
	344	{
	345	pci_qdev_register(&pcnet_info);
	346	}
	347
	348	device_init(pci_pcnet_register_devices)