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661a1799 PB |
1 | /* |
2 | * QEMU AMD PC-Net II (Am79C970A) PCI emulation | |
3 | * | |
4 | * Copyright (c) 2004 Antony T Curtis | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
24 | ||
25 | /* This software was written to be compatible with the specification: | |
26 | * AMD Am79C970A PCnet-PCI II Ethernet Controller Data-Sheet | |
27 | * AMD Publication# 19436 Rev:E Amendment/0 Issue Date: June 2000 | |
28 | */ | |
29 | ||
a2cb15b0 | 30 | #include "pci/pci.h" |
661a1799 PB |
31 | #include "net.h" |
32 | #include "loader.h" | |
33 | #include "qemu-timer.h" | |
14fecf26 | 34 | #include "dma.h" |
661a1799 PB |
35 | |
36 | #include "pcnet.h" | |
37 | ||
38 | //#define PCNET_DEBUG | |
39 | //#define PCNET_DEBUG_IO | |
40 | //#define PCNET_DEBUG_BCR | |
41 | //#define PCNET_DEBUG_CSR | |
42 | //#define PCNET_DEBUG_RMD | |
43 | //#define PCNET_DEBUG_TMD | |
44 | //#define PCNET_DEBUG_MATCH | |
45 | ||
46 | ||
47 | typedef struct { | |
48 | PCIDevice pci_dev; | |
49 | PCNetState state; | |
bd8d6f7c | 50 | MemoryRegion io_bar; |
661a1799 PB |
51 | } PCIPCNetState; |
52 | ||
53 | static void pcnet_aprom_writeb(void *opaque, uint32_t addr, uint32_t val) | |
54 | { | |
55 | PCNetState *s = opaque; | |
56 | #ifdef PCNET_DEBUG | |
57 | printf("pcnet_aprom_writeb addr=0x%08x val=0x%02x\n", addr, val); | |
58 | #endif | |
488a1a5d | 59 | if (BCR_APROMWE(s)) { |
661a1799 | 60 | s->prom[addr & 15] = val; |
488a1a5d | 61 | } |
661a1799 PB |
62 | } |
63 | ||
64 | static uint32_t pcnet_aprom_readb(void *opaque, uint32_t addr) | |
65 | { | |
66 | PCNetState *s = opaque; | |
67 | uint32_t val = s->prom[addr & 15]; | |
68 | #ifdef PCNET_DEBUG | |
69 | printf("pcnet_aprom_readb addr=0x%08x val=0x%02x\n", addr, val); | |
70 | #endif | |
71 | return val; | |
72 | } | |
73 | ||
a8170e5e | 74 | static uint64_t pcnet_ioport_read(void *opaque, hwaddr addr, |
bd8d6f7c | 75 | unsigned size) |
661a1799 | 76 | { |
bd8d6f7c | 77 | PCNetState *d = opaque; |
661a1799 | 78 | |
7ba79741 JK |
79 | if (addr < 0x10) { |
80 | if (!BCR_DWIO(d) && size == 1) { | |
81 | return pcnet_aprom_readb(d, addr); | |
82 | } else if (!BCR_DWIO(d) && (addr & 1) == 0 && size == 2) { | |
83 | return pcnet_aprom_readb(d, addr) | | |
84 | (pcnet_aprom_readb(d, addr + 1) << 8); | |
85 | } else if (BCR_DWIO(d) && (addr & 3) == 0 && size == 4) { | |
86 | return pcnet_aprom_readb(d, addr) | | |
87 | (pcnet_aprom_readb(d, addr + 1) << 8) | | |
88 | (pcnet_aprom_readb(d, addr + 2) << 16) | | |
89 | (pcnet_aprom_readb(d, addr + 3) << 24); | |
90 | } | |
91 | } else { | |
92 | if (size == 2) { | |
93 | return pcnet_ioport_readw(d, addr); | |
94 | } else if (size == 4) { | |
95 | return pcnet_ioport_readl(d, addr); | |
96 | } | |
bd8d6f7c AK |
97 | } |
98 | return ((uint64_t)1 << (size * 8)) - 1; | |
99 | } | |
661a1799 | 100 | |
a8170e5e | 101 | static void pcnet_ioport_write(void *opaque, hwaddr addr, |
bd8d6f7c AK |
102 | uint64_t data, unsigned size) |
103 | { | |
104 | PCNetState *d = opaque; | |
661a1799 | 105 | |
7ba79741 JK |
106 | if (addr < 0x10) { |
107 | if (!BCR_DWIO(d) && size == 1) { | |
108 | pcnet_aprom_writeb(d, addr, data); | |
109 | } else if (!BCR_DWIO(d) && (addr & 1) == 0 && size == 2) { | |
110 | pcnet_aprom_writeb(d, addr, data & 0xff); | |
111 | pcnet_aprom_writeb(d, addr + 1, data >> 8); | |
112 | } else if (BCR_DWIO(d) && (addr & 3) == 0 && size == 4) { | |
113 | pcnet_aprom_writeb(d, addr, data & 0xff); | |
114 | pcnet_aprom_writeb(d, addr + 1, (data >> 8) & 0xff); | |
115 | pcnet_aprom_writeb(d, addr + 2, (data >> 16) & 0xff); | |
116 | pcnet_aprom_writeb(d, addr + 3, data >> 24); | |
117 | } | |
118 | } else { | |
119 | if (size == 2) { | |
120 | pcnet_ioport_writew(d, addr, data); | |
121 | } else if (size == 4) { | |
122 | pcnet_ioport_writel(d, addr, data); | |
123 | } | |
bd8d6f7c | 124 | } |
661a1799 PB |
125 | } |
126 | ||
bd8d6f7c AK |
127 | static const MemoryRegionOps pcnet_io_ops = { |
128 | .read = pcnet_ioport_read, | |
129 | .write = pcnet_ioport_write, | |
130 | .endianness = DEVICE_NATIVE_ENDIAN, | |
131 | }; | |
132 | ||
a8170e5e | 133 | static void pcnet_mmio_writeb(void *opaque, hwaddr addr, uint32_t val) |
661a1799 PB |
134 | { |
135 | PCNetState *d = opaque; | |
136 | #ifdef PCNET_DEBUG_IO | |
137 | printf("pcnet_mmio_writeb addr=0x" TARGET_FMT_plx" val=0x%02x\n", addr, | |
138 | val); | |
139 | #endif | |
140 | if (!(addr & 0x10)) | |
141 | pcnet_aprom_writeb(d, addr & 0x0f, val); | |
142 | } | |
143 | ||
a8170e5e | 144 | static uint32_t pcnet_mmio_readb(void *opaque, hwaddr addr) |
661a1799 PB |
145 | { |
146 | PCNetState *d = opaque; | |
147 | uint32_t val = -1; | |
148 | if (!(addr & 0x10)) | |
149 | val = pcnet_aprom_readb(d, addr & 0x0f); | |
150 | #ifdef PCNET_DEBUG_IO | |
151 | printf("pcnet_mmio_readb addr=0x" TARGET_FMT_plx " val=0x%02x\n", addr, | |
152 | val & 0xff); | |
153 | #endif | |
154 | return val; | |
155 | } | |
156 | ||
a8170e5e | 157 | static void pcnet_mmio_writew(void *opaque, hwaddr addr, uint32_t val) |
661a1799 PB |
158 | { |
159 | PCNetState *d = opaque; | |
160 | #ifdef PCNET_DEBUG_IO | |
161 | printf("pcnet_mmio_writew addr=0x" TARGET_FMT_plx " val=0x%04x\n", addr, | |
162 | val); | |
163 | #endif | |
164 | if (addr & 0x10) | |
165 | pcnet_ioport_writew(d, addr & 0x0f, val); | |
166 | else { | |
167 | addr &= 0x0f; | |
168 | pcnet_aprom_writeb(d, addr, val & 0xff); | |
169 | pcnet_aprom_writeb(d, addr+1, (val & 0xff00) >> 8); | |
170 | } | |
171 | } | |
172 | ||
a8170e5e | 173 | static uint32_t pcnet_mmio_readw(void *opaque, hwaddr addr) |
661a1799 PB |
174 | { |
175 | PCNetState *d = opaque; | |
176 | uint32_t val = -1; | |
177 | if (addr & 0x10) | |
178 | val = pcnet_ioport_readw(d, addr & 0x0f); | |
179 | else { | |
180 | addr &= 0x0f; | |
181 | val = pcnet_aprom_readb(d, addr+1); | |
182 | val <<= 8; | |
183 | val |= pcnet_aprom_readb(d, addr); | |
184 | } | |
185 | #ifdef PCNET_DEBUG_IO | |
186 | printf("pcnet_mmio_readw addr=0x" TARGET_FMT_plx" val = 0x%04x\n", addr, | |
187 | val & 0xffff); | |
188 | #endif | |
189 | return val; | |
190 | } | |
191 | ||
a8170e5e | 192 | static void pcnet_mmio_writel(void *opaque, hwaddr addr, uint32_t val) |
661a1799 PB |
193 | { |
194 | PCNetState *d = opaque; | |
195 | #ifdef PCNET_DEBUG_IO | |
196 | printf("pcnet_mmio_writel addr=0x" TARGET_FMT_plx" val=0x%08x\n", addr, | |
197 | val); | |
198 | #endif | |
199 | if (addr & 0x10) | |
200 | pcnet_ioport_writel(d, addr & 0x0f, val); | |
201 | else { | |
202 | addr &= 0x0f; | |
203 | pcnet_aprom_writeb(d, addr, val & 0xff); | |
204 | pcnet_aprom_writeb(d, addr+1, (val & 0xff00) >> 8); | |
205 | pcnet_aprom_writeb(d, addr+2, (val & 0xff0000) >> 16); | |
206 | pcnet_aprom_writeb(d, addr+3, (val & 0xff000000) >> 24); | |
207 | } | |
208 | } | |
209 | ||
a8170e5e | 210 | static uint32_t pcnet_mmio_readl(void *opaque, hwaddr addr) |
661a1799 PB |
211 | { |
212 | PCNetState *d = opaque; | |
213 | uint32_t val; | |
214 | if (addr & 0x10) | |
215 | val = pcnet_ioport_readl(d, addr & 0x0f); | |
216 | else { | |
217 | addr &= 0x0f; | |
218 | val = pcnet_aprom_readb(d, addr+3); | |
219 | val <<= 8; | |
220 | val |= pcnet_aprom_readb(d, addr+2); | |
221 | val <<= 8; | |
222 | val |= pcnet_aprom_readb(d, addr+1); | |
223 | val <<= 8; | |
224 | val |= pcnet_aprom_readb(d, addr); | |
225 | } | |
226 | #ifdef PCNET_DEBUG_IO | |
227 | printf("pcnet_mmio_readl addr=0x" TARGET_FMT_plx " val=0x%08x\n", addr, | |
228 | val); | |
229 | #endif | |
230 | return val; | |
231 | } | |
232 | ||
233 | static const VMStateDescription vmstate_pci_pcnet = { | |
234 | .name = "pcnet", | |
235 | .version_id = 3, | |
236 | .minimum_version_id = 2, | |
237 | .minimum_version_id_old = 2, | |
238 | .fields = (VMStateField []) { | |
239 | VMSTATE_PCI_DEVICE(pci_dev, PCIPCNetState), | |
240 | VMSTATE_STRUCT(state, PCIPCNetState, 0, vmstate_pcnet, PCNetState), | |
241 | VMSTATE_END_OF_LIST() | |
242 | } | |
243 | }; | |
244 | ||
245 | /* PCI interface */ | |
246 | ||
bd8d6f7c AK |
247 | static const MemoryRegionOps pcnet_mmio_ops = { |
248 | .old_mmio = { | |
249 | .read = { pcnet_mmio_readb, pcnet_mmio_readw, pcnet_mmio_readl }, | |
250 | .write = { pcnet_mmio_writeb, pcnet_mmio_writew, pcnet_mmio_writel }, | |
251 | }, | |
252 | .endianness = DEVICE_NATIVE_ENDIAN, | |
661a1799 PB |
253 | }; |
254 | ||
a8170e5e | 255 | static void pci_physical_memory_write(void *dma_opaque, hwaddr addr, |
661a1799 PB |
256 | uint8_t *buf, int len, int do_bswap) |
257 | { | |
14fecf26 | 258 | pci_dma_write(dma_opaque, addr, buf, len); |
661a1799 PB |
259 | } |
260 | ||
a8170e5e | 261 | static void pci_physical_memory_read(void *dma_opaque, hwaddr addr, |
661a1799 PB |
262 | uint8_t *buf, int len, int do_bswap) |
263 | { | |
14fecf26 | 264 | pci_dma_read(dma_opaque, addr, buf, len); |
661a1799 PB |
265 | } |
266 | ||
4e68f7a0 | 267 | static void pci_pcnet_cleanup(NetClientState *nc) |
661a1799 PB |
268 | { |
269 | PCNetState *d = DO_UPCAST(NICState, nc, nc)->opaque; | |
270 | ||
271 | pcnet_common_cleanup(d); | |
272 | } | |
273 | ||
f90c2bcd | 274 | static void pci_pcnet_uninit(PCIDevice *dev) |
661a1799 PB |
275 | { |
276 | PCIPCNetState *d = DO_UPCAST(PCIPCNetState, pci_dev, dev); | |
277 | ||
bd8d6f7c AK |
278 | memory_region_destroy(&d->state.mmio); |
279 | memory_region_destroy(&d->io_bar); | |
661a1799 PB |
280 | qemu_del_timer(d->state.poll_timer); |
281 | qemu_free_timer(d->state.poll_timer); | |
b20c6b9e | 282 | qemu_del_net_client(&d->state.nic->nc); |
661a1799 PB |
283 | } |
284 | ||
285 | static NetClientInfo net_pci_pcnet_info = { | |
2be64a68 | 286 | .type = NET_CLIENT_OPTIONS_KIND_NIC, |
661a1799 PB |
287 | .size = sizeof(NICState), |
288 | .can_receive = pcnet_can_receive, | |
289 | .receive = pcnet_receive, | |
e1c2008a | 290 | .link_status_changed = pcnet_set_link_status, |
661a1799 PB |
291 | .cleanup = pci_pcnet_cleanup, |
292 | }; | |
293 | ||
294 | static int pci_pcnet_init(PCIDevice *pci_dev) | |
295 | { | |
296 | PCIPCNetState *d = DO_UPCAST(PCIPCNetState, pci_dev, pci_dev); | |
297 | PCNetState *s = &d->state; | |
298 | uint8_t *pci_conf; | |
299 | ||
300 | #if 0 | |
301 | printf("sizeof(RMD)=%d, sizeof(TMD)=%d\n", | |
302 | sizeof(struct pcnet_RMD), sizeof(struct pcnet_TMD)); | |
303 | #endif | |
304 | ||
305 | pci_conf = pci_dev->config; | |
306 | ||
661a1799 PB |
307 | pci_set_word(pci_conf + PCI_STATUS, |
308 | PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MEDIUM); | |
661a1799 PB |
309 | |
310 | pci_set_word(pci_conf + PCI_SUBSYSTEM_VENDOR_ID, 0x0); | |
311 | pci_set_word(pci_conf + PCI_SUBSYSTEM_ID, 0x0); | |
312 | ||
817e0b6f | 313 | pci_conf[PCI_INTERRUPT_PIN] = 1; /* interrupt pin A */ |
661a1799 PB |
314 | pci_conf[PCI_MIN_GNT] = 0x06; |
315 | pci_conf[PCI_MAX_LAT] = 0xff; | |
316 | ||
317 | /* Handler for memory-mapped I/O */ | |
145aebec | 318 | memory_region_init_io(&d->state.mmio, &pcnet_mmio_ops, s, "pcnet-mmio", |
bd8d6f7c | 319 | PCNET_PNPMMIO_SIZE); |
661a1799 | 320 | |
145aebec | 321 | memory_region_init_io(&d->io_bar, &pcnet_io_ops, s, "pcnet-io", |
bd8d6f7c | 322 | PCNET_IOPORT_SIZE); |
e824b2cc | 323 | pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &d->io_bar); |
661a1799 | 324 | |
e824b2cc | 325 | pci_register_bar(pci_dev, 1, 0, &s->mmio); |
661a1799 PB |
326 | |
327 | s->irq = pci_dev->irq[0]; | |
328 | s->phys_mem_read = pci_physical_memory_read; | |
329 | s->phys_mem_write = pci_physical_memory_write; | |
14fecf26 | 330 | s->dma_opaque = pci_dev; |
661a1799 | 331 | |
661a1799 PB |
332 | return pcnet_common_init(&pci_dev->qdev, s, &net_pci_pcnet_info); |
333 | } | |
334 | ||
335 | static void pci_reset(DeviceState *dev) | |
336 | { | |
337 | PCIPCNetState *d = DO_UPCAST(PCIPCNetState, pci_dev.qdev, dev); | |
338 | ||
339 | pcnet_h_reset(&d->state); | |
340 | } | |
341 | ||
40021f08 AL |
342 | static Property pcnet_properties[] = { |
343 | DEFINE_NIC_PROPERTIES(PCIPCNetState, state.conf), | |
344 | DEFINE_PROP_END_OF_LIST(), | |
345 | }; | |
346 | ||
347 | static void pcnet_class_init(ObjectClass *klass, void *data) | |
348 | { | |
39bffca2 | 349 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
350 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
351 | ||
352 | k->init = pci_pcnet_init; | |
353 | k->exit = pci_pcnet_uninit; | |
9ebe95fb | 354 | k->romfile = "pxe-pcnet.rom", |
40021f08 AL |
355 | k->vendor_id = PCI_VENDOR_ID_AMD; |
356 | k->device_id = PCI_DEVICE_ID_AMD_LANCE; | |
357 | k->revision = 0x10; | |
358 | k->class_id = PCI_CLASS_NETWORK_ETHERNET; | |
39bffca2 AL |
359 | dc->reset = pci_reset; |
360 | dc->vmsd = &vmstate_pci_pcnet; | |
361 | dc->props = pcnet_properties; | |
40021f08 AL |
362 | } |
363 | ||
39bffca2 AL |
364 | static TypeInfo pcnet_info = { |
365 | .name = "pcnet", | |
366 | .parent = TYPE_PCI_DEVICE, | |
367 | .instance_size = sizeof(PCIPCNetState), | |
368 | .class_init = pcnet_class_init, | |
661a1799 PB |
369 | }; |
370 | ||
83f7d43a | 371 | static void pci_pcnet_register_types(void) |
661a1799 | 372 | { |
39bffca2 | 373 | type_register_static(&pcnet_info); |
661a1799 PB |
374 | } |
375 | ||
83f7d43a | 376 | type_init(pci_pcnet_register_types) |