[qemu.git] / hw / net / pcnet-pci.c

/*
 * QEMU AMD PC-Net II (Am79C970A) PCI emulation
 *
 * Copyright (c) 2004 Antony T Curtis
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

/* This software was written to be compatible with the specification:
 * AMD Am79C970A PCnet-PCI II Ethernet Controller Data-Sheet
 * AMD Publication# 19436  Rev:E  Amendment/0  Issue Date: June 2000
 */

#include "hw/pci/pci.h"
#include "net/net.h"
#include "hw/loader.h"
#include "qemu/timer.h"
#include "sysemu/dma.h"
#include "sysemu/sysemu.h"
#include "trace.h"

#include "pcnet.h"

//#define PCNET_DEBUG
//#define PCNET_DEBUG_IO
//#define PCNET_DEBUG_BCR
//#define PCNET_DEBUG_CSR
//#define PCNET_DEBUG_RMD
//#define PCNET_DEBUG_TMD
//#define PCNET_DEBUG_MATCH

#define TYPE_PCI_PCNET "pcnet"

#define PCI_PCNET(obj) \
     OBJECT_CHECK(PCIPCNetState, (obj), TYPE_PCI_PCNET)

typedef struct {
    /*< private >*/
    PCIDevice parent_obj;
    /*< public >*/

    PCNetState state;
    MemoryRegion io_bar;
} PCIPCNetState;

static void pcnet_aprom_writeb(void *opaque, uint32_t addr, uint32_t val)
{
    PCNetState *s = opaque;

    trace_pcnet_aprom_writeb(opaque, addr, val);
    if (BCR_APROMWE(s)) {
        s->prom[addr & 15] = val;
    }
}

static uint32_t pcnet_aprom_readb(void *opaque, uint32_t addr)
{
    PCNetState *s = opaque;
    uint32_t val = s->prom[addr & 15];

    trace_pcnet_aprom_readb(opaque, addr, val);
    return val;
}

static uint64_t pcnet_ioport_read(void *opaque, hwaddr addr,
                                  unsigned size)
{
    PCNetState *d = opaque;

    trace_pcnet_ioport_read(opaque, addr, size);
    if (addr < 0x10) {
        if (!BCR_DWIO(d) && size == 1) {
            return pcnet_aprom_readb(d, addr);
        } else if (!BCR_DWIO(d) && (addr & 1) == 0 && size == 2) {
            return pcnet_aprom_readb(d, addr) |
                   (pcnet_aprom_readb(d, addr + 1) << 8);
        } else if (BCR_DWIO(d) && (addr & 3) == 0 && size == 4) {
            return pcnet_aprom_readb(d, addr) |
                   (pcnet_aprom_readb(d, addr + 1) << 8) |
                   (pcnet_aprom_readb(d, addr + 2) << 16) |
                   (pcnet_aprom_readb(d, addr + 3) << 24);
        }
    } else {
        if (size == 2) {
            return pcnet_ioport_readw(d, addr);
        } else if (size == 4) {
            return pcnet_ioport_readl(d, addr);
        }
    }
    return ((uint64_t)1 << (size * 8)) - 1;
}

static void pcnet_ioport_write(void *opaque, hwaddr addr,
                               uint64_t data, unsigned size)
{
    PCNetState *d = opaque;

    trace_pcnet_ioport_write(opaque, addr, data, size);
    if (addr < 0x10) {
        if (!BCR_DWIO(d) && size == 1) {
            pcnet_aprom_writeb(d, addr, data);
        } else if (!BCR_DWIO(d) && (addr & 1) == 0 && size == 2) {
            pcnet_aprom_writeb(d, addr, data & 0xff);
            pcnet_aprom_writeb(d, addr + 1, data >> 8);
        } else if (BCR_DWIO(d) && (addr & 3) == 0 && size == 4) {
            pcnet_aprom_writeb(d, addr, data & 0xff);
            pcnet_aprom_writeb(d, addr + 1, (data >> 8) & 0xff);
            pcnet_aprom_writeb(d, addr + 2, (data >> 16) & 0xff);
            pcnet_aprom_writeb(d, addr + 3, data >> 24);
        }
    } else {
        if (size == 2) {
            pcnet_ioport_writew(d, addr, data);
        } else if (size == 4) {
            pcnet_ioport_writel(d, addr, data);
        }
    }
}

static const MemoryRegionOps pcnet_io_ops = {
    .read = pcnet_ioport_read,
    .write = pcnet_ioport_write,
    .endianness = DEVICE_LITTLE_ENDIAN,
};

static void pcnet_mmio_writeb(void *opaque, hwaddr addr, uint32_t val)
{
    PCNetState *d = opaque;

    trace_pcnet_mmio_writeb(opaque, addr, val);
    if (!(addr & 0x10))
        pcnet_aprom_writeb(d, addr & 0x0f, val);
}

static uint32_t pcnet_mmio_readb(void *opaque, hwaddr addr)
{
    PCNetState *d = opaque;
    uint32_t val = -1;

    if (!(addr & 0x10))
        val = pcnet_aprom_readb(d, addr & 0x0f);
    trace_pcnet_mmio_readb(opaque, addr, val);
    return val;
}

static void pcnet_mmio_writew(void *opaque, hwaddr addr, uint32_t val)
{
    PCNetState *d = opaque;

    trace_pcnet_mmio_writew(opaque, addr, val);
    if (addr & 0x10)
        pcnet_ioport_writew(d, addr & 0x0f, val);
    else {
        addr &= 0x0f;
        pcnet_aprom_writeb(d, addr, val & 0xff);
        pcnet_aprom_writeb(d, addr+1, (val & 0xff00) >> 8);
    }
}

static uint32_t pcnet_mmio_readw(void *opaque, hwaddr addr)
{
    PCNetState *d = opaque;
    uint32_t val = -1;

    if (addr & 0x10)
        val = pcnet_ioport_readw(d, addr & 0x0f);
    else {
        addr &= 0x0f;
        val = pcnet_aprom_readb(d, addr+1);
        val <<= 8;
        val |= pcnet_aprom_readb(d, addr);
    }
    trace_pcnet_mmio_readw(opaque, addr, val);
    return val;
}

static void pcnet_mmio_writel(void *opaque, hwaddr addr, uint32_t val)
{
    PCNetState *d = opaque;

    trace_pcnet_mmio_writel(opaque, addr, val);
    if (addr & 0x10)
        pcnet_ioport_writel(d, addr & 0x0f, val);
    else {
        addr &= 0x0f;
        pcnet_aprom_writeb(d, addr, val & 0xff);
        pcnet_aprom_writeb(d, addr+1, (val & 0xff00) >> 8);
        pcnet_aprom_writeb(d, addr+2, (val & 0xff0000) >> 16);
        pcnet_aprom_writeb(d, addr+3, (val & 0xff000000) >> 24);
    }
}

static uint32_t pcnet_mmio_readl(void *opaque, hwaddr addr)
{
    PCNetState *d = opaque;
    uint32_t val;

    if (addr & 0x10)
        val = pcnet_ioport_readl(d, addr & 0x0f);
    else {
        addr &= 0x0f;
        val = pcnet_aprom_readb(d, addr+3);
        val <<= 8;
        val |= pcnet_aprom_readb(d, addr+2);
        val <<= 8;
        val |= pcnet_aprom_readb(d, addr+1);
        val <<= 8;
        val |= pcnet_aprom_readb(d, addr);
    }
    trace_pcnet_mmio_readl(opaque, addr, val);
    return val;
}

static const VMStateDescription vmstate_pci_pcnet = {
    .name = "pcnet",
    .version_id = 3,
    .minimum_version_id = 2,
    .fields = (VMStateField[]) {
        VMSTATE_PCI_DEVICE(parent_obj, PCIPCNetState),
        VMSTATE_STRUCT(state, PCIPCNetState, 0, vmstate_pcnet, PCNetState),
        VMSTATE_END_OF_LIST()
    }
};

/* PCI interface */

static const MemoryRegionOps pcnet_mmio_ops = {
    .old_mmio = {
        .read = { pcnet_mmio_readb, pcnet_mmio_readw, pcnet_mmio_readl },
        .write = { pcnet_mmio_writeb, pcnet_mmio_writew, pcnet_mmio_writel },
    },
    .endianness = DEVICE_LITTLE_ENDIAN,
};

static void pci_physical_memory_write(void *dma_opaque, hwaddr addr,
                                      uint8_t *buf, int len, int do_bswap)
{
    pci_dma_write(dma_opaque, addr, buf, len);
}

static void pci_physical_memory_read(void *dma_opaque, hwaddr addr,
                                     uint8_t *buf, int len, int do_bswap)
{
    pci_dma_read(dma_opaque, addr, buf, len);
}

static void pci_pcnet_uninit(PCIDevice *dev)
{
    PCIPCNetState *d = PCI_PCNET(dev);

    qemu_free_irq(d->state.irq);
    timer_del(d->state.poll_timer);
    timer_free(d->state.poll_timer);
    qemu_del_nic(d->state.nic);
}

static NetClientInfo net_pci_pcnet_info = {
    .type = NET_CLIENT_OPTIONS_KIND_NIC,
    .size = sizeof(NICState),
    .receive = pcnet_receive,
    .link_status_changed = pcnet_set_link_status,
};

static void pci_pcnet_realize(PCIDevice *pci_dev, Error **errp)
{
    PCIPCNetState *d = PCI_PCNET(pci_dev);
    PCNetState *s = &d->state;
    uint8_t *pci_conf;

#if 0
    printf("sizeof(RMD)=%d, sizeof(TMD)=%d\n",
        sizeof(struct pcnet_RMD), sizeof(struct pcnet_TMD));
#endif

    pci_conf = pci_dev->config;

    pci_set_word(pci_conf + PCI_STATUS,
                 PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MEDIUM);

    pci_set_word(pci_conf + PCI_SUBSYSTEM_VENDOR_ID, 0x0);
    pci_set_word(pci_conf + PCI_SUBSYSTEM_ID, 0x0);

    pci_conf[PCI_INTERRUPT_PIN] = 1; /* interrupt pin A */
    pci_conf[PCI_MIN_GNT] = 0x06;
    pci_conf[PCI_MAX_LAT] = 0xff;

    /* Handler for memory-mapped I/O */
    memory_region_init_io(&d->state.mmio, OBJECT(d), &pcnet_mmio_ops, s,
                          "pcnet-mmio", PCNET_PNPMMIO_SIZE);

    memory_region_init_io(&d->io_bar, OBJECT(d), &pcnet_io_ops, s, "pcnet-io",
                          PCNET_IOPORT_SIZE);
    pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &d->io_bar);

    pci_register_bar(pci_dev, 1, 0, &s->mmio);

    s->irq = pci_allocate_irq(pci_dev);
    s->phys_mem_read = pci_physical_memory_read;
    s->phys_mem_write = pci_physical_memory_write;
    s->dma_opaque = pci_dev;

    pcnet_common_init(DEVICE(pci_dev), s, &net_pci_pcnet_info);
}

static void pci_reset(DeviceState *dev)
{
    PCIPCNetState *d = PCI_PCNET(dev);

    pcnet_h_reset(&d->state);
}

static void pcnet_instance_init(Object *obj)
{
    PCIPCNetState *d = PCI_PCNET(obj);
    PCNetState *s = &d->state;

    device_add_bootindex_property(obj, &s->conf.bootindex,
                                  "bootindex", "/ethernet-phy@0",
                                  DEVICE(obj), NULL);
}

static Property pcnet_properties[] = {
    DEFINE_NIC_PROPERTIES(PCIPCNetState, state.conf),
    DEFINE_PROP_END_OF_LIST(),
};

static void pcnet_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);

    k->realize = pci_pcnet_realize;
    k->exit = pci_pcnet_uninit;
    k->romfile = "efi-pcnet.rom",
    k->vendor_id = PCI_VENDOR_ID_AMD;
    k->device_id = PCI_DEVICE_ID_AMD_LANCE;
    k->revision = 0x10;
    k->class_id = PCI_CLASS_NETWORK_ETHERNET;
    dc->reset = pci_reset;
    dc->vmsd = &vmstate_pci_pcnet;
    dc->props = pcnet_properties;
    set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
}

static const TypeInfo pcnet_info = {
    .name          = TYPE_PCI_PCNET,
    .parent        = TYPE_PCI_DEVICE,
    .instance_size = sizeof(PCIPCNetState),
    .class_init    = pcnet_class_init,
    .instance_init = pcnet_instance_init,
};

static void pci_pcnet_register_types(void)
{
    type_register_static(&pcnet_info);
}

type_init(pci_pcnet_register_types)
Commit	Line	Data
661a1799 PB	1	/*
	2	* QEMU AMD PC-Net II (Am79C970A) PCI emulation
	3	*
	4	* Copyright (c) 2004 Antony T Curtis
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
	24
	25	/* This software was written to be compatible with the specification:
	26	* AMD Am79C970A PCnet-PCI II Ethernet Controller Data-Sheet
	27	* AMD Publication# 19436 Rev:E Amendment/0 Issue Date: June 2000
	28	*/
	29
83c9f4ca	30	#include "hw/pci/pci.h"
1422e32d	31	#include "net/net.h"
83c9f4ca	32	#include "hw/loader.h"
1de7afc9	33	#include "qemu/timer.h"
9c17d615	34	#include "sysemu/dma.h"
ea3b3511	35	#include "sysemu/sysemu.h"
32c95249	36	#include "trace.h"
661a1799	37
47b43a1f	38	#include "pcnet.h"
661a1799 PB	39
	40	//#define PCNET_DEBUG
	41	//#define PCNET_DEBUG_IO
	42	//#define PCNET_DEBUG_BCR
	43	//#define PCNET_DEBUG_CSR
	44	//#define PCNET_DEBUG_RMD
	45	//#define PCNET_DEBUG_TMD
	46	//#define PCNET_DEBUG_MATCH
	47
1f8c7946 PC	48	#define TYPE_PCI_PCNET "pcnet"
	49
	50	#define PCI_PCNET(obj) \
	51	OBJECT_CHECK(PCIPCNetState, (obj), TYPE_PCI_PCNET)
661a1799 PB	52
661a1799 PB	53	typedef struct {
1f8c7946 PC	54	/< private >/
	55	PCIDevice parent_obj;
	56	/< public >/
	57
661a1799	58	PCNetState state;
bd8d6f7c	59	MemoryRegion io_bar;
661a1799 PB	60	} PCIPCNetState;
	61
	62	static void pcnet_aprom_writeb(void *opaque, uint32_t addr, uint32_t val)
	63	{
	64	PCNetState *s = opaque;
32c95249 DK	65
32c95249 DK	66	trace_pcnet_aprom_writeb(opaque, addr, val);
488a1a5d	67	if (BCR_APROMWE(s)) {
661a1799	68	s->prom[addr & 15] = val;
488a1a5d	69	}
661a1799 PB	70	}
	71
	72	static uint32_t pcnet_aprom_readb(void *opaque, uint32_t addr)
	73	{
	74	PCNetState *s = opaque;
	75	uint32_t val = s->prom[addr & 15];
32c95249 DK	76
32c95249 DK	77	trace_pcnet_aprom_readb(opaque, addr, val);
661a1799 PB	78	return val;
	79	}
	80
a8170e5e	81	static uint64_t pcnet_ioport_read(void *opaque, hwaddr addr,
bd8d6f7c	82	unsigned size)
661a1799	83	{
bd8d6f7c	84	PCNetState *d = opaque;
661a1799	85
32c95249	86	trace_pcnet_ioport_read(opaque, addr, size);
7ba79741 JK	87	if (addr < 0x10) {
	88	if (!BCR_DWIO(d) && size == 1) {
	89	return pcnet_aprom_readb(d, addr);
	90	} else if (!BCR_DWIO(d) && (addr & 1) == 0 && size == 2) {
	91	return pcnet_aprom_readb(d, addr) \|
	92	(pcnet_aprom_readb(d, addr + 1) << 8);
	93	} else if (BCR_DWIO(d) && (addr & 3) == 0 && size == 4) {
	94	return pcnet_aprom_readb(d, addr) \|
	95	(pcnet_aprom_readb(d, addr + 1) << 8) \|
	96	(pcnet_aprom_readb(d, addr + 2) << 16) \|
	97	(pcnet_aprom_readb(d, addr + 3) << 24);
	98	}
	99	} else {
	100	if (size == 2) {
	101	return pcnet_ioport_readw(d, addr);
	102	} else if (size == 4) {
	103	return pcnet_ioport_readl(d, addr);
	104	}
bd8d6f7c AK	105	}
	106	return ((uint64_t)1 << (size * 8)) - 1;
	107	}
661a1799	108
a8170e5e	109	static void pcnet_ioport_write(void *opaque, hwaddr addr,
bd8d6f7c AK	110	uint64_t data, unsigned size)
	111	{
	112	PCNetState *d = opaque;
661a1799	113
32c95249	114	trace_pcnet_ioport_write(opaque, addr, data, size);
7ba79741 JK	115	if (addr < 0x10) {
	116	if (!BCR_DWIO(d) && size == 1) {
	117	pcnet_aprom_writeb(d, addr, data);
	118	} else if (!BCR_DWIO(d) && (addr & 1) == 0 && size == 2) {
	119	pcnet_aprom_writeb(d, addr, data & 0xff);
	120	pcnet_aprom_writeb(d, addr + 1, data >> 8);
	121	} else if (BCR_DWIO(d) && (addr & 3) == 0 && size == 4) {
	122	pcnet_aprom_writeb(d, addr, data & 0xff);
	123	pcnet_aprom_writeb(d, addr + 1, (data >> 8) & 0xff);
	124	pcnet_aprom_writeb(d, addr + 2, (data >> 16) & 0xff);
	125	pcnet_aprom_writeb(d, addr + 3, data >> 24);
	126	}
	127	} else {
	128	if (size == 2) {
	129	pcnet_ioport_writew(d, addr, data);
	130	} else if (size == 4) {
	131	pcnet_ioport_writel(d, addr, data);
	132	}
bd8d6f7c	133	}
661a1799 PB	134	}
661a1799 PB	135
bd8d6f7c AK	136	static const MemoryRegionOps pcnet_io_ops = {
	137	.read = pcnet_ioport_read,
	138	.write = pcnet_ioport_write,
a26405b3	139	.endianness = DEVICE_LITTLE_ENDIAN,
bd8d6f7c AK	140	};
bd8d6f7c AK	141
a8170e5e	142	static void pcnet_mmio_writeb(void *opaque, hwaddr addr, uint32_t val)
661a1799 PB	143	{
661a1799 PB	144	PCNetState *d = opaque;
32c95249 DK	145
32c95249 DK	146	trace_pcnet_mmio_writeb(opaque, addr, val);
661a1799 PB	147	if (!(addr & 0x10))
	148	pcnet_aprom_writeb(d, addr & 0x0f, val);
	149	}
	150
a8170e5e	151	static uint32_t pcnet_mmio_readb(void *opaque, hwaddr addr)
661a1799 PB	152	{
	153	PCNetState *d = opaque;
	154	uint32_t val = -1;
32c95249	155
661a1799 PB	156	if (!(addr & 0x10))
661a1799 PB	157	val = pcnet_aprom_readb(d, addr & 0x0f);
32c95249	158	trace_pcnet_mmio_readb(opaque, addr, val);
661a1799 PB	159	return val;
	160	}
	161
a8170e5e	162	static void pcnet_mmio_writew(void *opaque, hwaddr addr, uint32_t val)
661a1799 PB	163	{
661a1799 PB	164	PCNetState *d = opaque;
32c95249 DK	165
32c95249 DK	166	trace_pcnet_mmio_writew(opaque, addr, val);
661a1799 PB	167	if (addr & 0x10)
	168	pcnet_ioport_writew(d, addr & 0x0f, val);
	169	else {
	170	addr &= 0x0f;
	171	pcnet_aprom_writeb(d, addr, val & 0xff);
	172	pcnet_aprom_writeb(d, addr+1, (val & 0xff00) >> 8);
	173	}
	174	}
	175
a8170e5e	176	static uint32_t pcnet_mmio_readw(void *opaque, hwaddr addr)
661a1799 PB	177	{
	178	PCNetState *d = opaque;
	179	uint32_t val = -1;
32c95249	180
661a1799 PB	181	if (addr & 0x10)
	182	val = pcnet_ioport_readw(d, addr & 0x0f);
	183	else {
	184	addr &= 0x0f;
	185	val = pcnet_aprom_readb(d, addr+1);
	186	val <<= 8;
	187	val \|= pcnet_aprom_readb(d, addr);
	188	}
32c95249	189	trace_pcnet_mmio_readw(opaque, addr, val);
661a1799 PB	190	return val;
	191	}
	192
a8170e5e	193	static void pcnet_mmio_writel(void *opaque, hwaddr addr, uint32_t val)
661a1799 PB	194	{
661a1799 PB	195	PCNetState *d = opaque;
32c95249 DK	196
32c95249 DK	197	trace_pcnet_mmio_writel(opaque, addr, val);
661a1799 PB	198	if (addr & 0x10)
	199	pcnet_ioport_writel(d, addr & 0x0f, val);
	200	else {
	201	addr &= 0x0f;
	202	pcnet_aprom_writeb(d, addr, val & 0xff);
	203	pcnet_aprom_writeb(d, addr+1, (val & 0xff00) >> 8);
	204	pcnet_aprom_writeb(d, addr+2, (val & 0xff0000) >> 16);
	205	pcnet_aprom_writeb(d, addr+3, (val & 0xff000000) >> 24);
	206	}
	207	}
	208
a8170e5e	209	static uint32_t pcnet_mmio_readl(void *opaque, hwaddr addr)
661a1799 PB	210	{
	211	PCNetState *d = opaque;
	212	uint32_t val;
32c95249	213
661a1799 PB	214	if (addr & 0x10)
	215	val = pcnet_ioport_readl(d, addr & 0x0f);
	216	else {
	217	addr &= 0x0f;
	218	val = pcnet_aprom_readb(d, addr+3);
	219	val <<= 8;
	220	val \|= pcnet_aprom_readb(d, addr+2);
	221	val <<= 8;
	222	val \|= pcnet_aprom_readb(d, addr+1);
	223	val <<= 8;
	224	val \|= pcnet_aprom_readb(d, addr);
	225	}
32c95249	226	trace_pcnet_mmio_readl(opaque, addr, val);
661a1799 PB	227	return val;
	228	}
	229
	230	static const VMStateDescription vmstate_pci_pcnet = {
	231	.name = "pcnet",
	232	.version_id = 3,
	233	.minimum_version_id = 2,
d49805ae	234	.fields = (VMStateField[]) {
1f8c7946	235	VMSTATE_PCI_DEVICE(parent_obj, PCIPCNetState),
661a1799 PB	236	VMSTATE_STRUCT(state, PCIPCNetState, 0, vmstate_pcnet, PCNetState),
	237	VMSTATE_END_OF_LIST()
	238	}
	239	};
	240
	241	/* PCI interface */
	242
bd8d6f7c AK	243	static const MemoryRegionOps pcnet_mmio_ops = {
	244	.old_mmio = {
	245	.read = { pcnet_mmio_readb, pcnet_mmio_readw, pcnet_mmio_readl },
	246	.write = { pcnet_mmio_writeb, pcnet_mmio_writew, pcnet_mmio_writel },
	247	},
a26405b3	248	.endianness = DEVICE_LITTLE_ENDIAN,
661a1799 PB	249	};
661a1799 PB	250
a8170e5e	251	static void pci_physical_memory_write(void *dma_opaque, hwaddr addr,
661a1799 PB	252	uint8_t *buf, int len, int do_bswap)
661a1799 PB	253	{
14fecf26	254	pci_dma_write(dma_opaque, addr, buf, len);
661a1799 PB	255	}
661a1799 PB	256
a8170e5e	257	static void pci_physical_memory_read(void *dma_opaque, hwaddr addr,
661a1799 PB	258	uint8_t *buf, int len, int do_bswap)
661a1799 PB	259	{
14fecf26	260	pci_dma_read(dma_opaque, addr, buf, len);
661a1799 PB	261	}
661a1799 PB	262
f90c2bcd	263	static void pci_pcnet_uninit(PCIDevice *dev)
661a1799	264	{
1f8c7946	265	PCIPCNetState *d = PCI_PCNET(dev);
661a1799	266
9e64f8a3	267	qemu_free_irq(d->state.irq);
bc72ad67 AB	268	timer_del(d->state.poll_timer);
bc72ad67 AB	269	timer_free(d->state.poll_timer);
948ecf21	270	qemu_del_nic(d->state.nic);
661a1799 PB	271	}
	272
	273	static NetClientInfo net_pci_pcnet_info = {
2be64a68	274	.type = NET_CLIENT_OPTIONS_KIND_NIC,
661a1799	275	.size = sizeof(NICState),
661a1799	276	.receive = pcnet_receive,
e1c2008a	277	.link_status_changed = pcnet_set_link_status,
661a1799 PB	278	};
661a1799 PB	279
eb1bef94	280	static void pci_pcnet_realize(PCIDevice pci_dev, Error *errp)
661a1799	281	{
1f8c7946	282	PCIPCNetState *d = PCI_PCNET(pci_dev);
661a1799 PB	283	PCNetState *s = &d->state;
	284	uint8_t *pci_conf;
	285
	286	#if 0
	287	printf("sizeof(RMD)=%d, sizeof(TMD)=%d\n",
	288	sizeof(struct pcnet_RMD), sizeof(struct pcnet_TMD));
	289	#endif
	290
	291	pci_conf = pci_dev->config;
	292
661a1799 PB	293	pci_set_word(pci_conf + PCI_STATUS,
661a1799 PB	294	PCI_STATUS_FAST_BACK \| PCI_STATUS_DEVSEL_MEDIUM);
661a1799 PB	295
	296	pci_set_word(pci_conf + PCI_SUBSYSTEM_VENDOR_ID, 0x0);
	297	pci_set_word(pci_conf + PCI_SUBSYSTEM_ID, 0x0);
	298
817e0b6f	299	pci_conf[PCI_INTERRUPT_PIN] = 1; /* interrupt pin A */
661a1799 PB	300	pci_conf[PCI_MIN_GNT] = 0x06;
	301	pci_conf[PCI_MAX_LAT] = 0xff;
	302
	303	/* Handler for memory-mapped I/O */
eedfac6f PB	304	memory_region_init_io(&d->state.mmio, OBJECT(d), &pcnet_mmio_ops, s,
eedfac6f PB	305	"pcnet-mmio", PCNET_PNPMMIO_SIZE);
661a1799	306
eedfac6f	307	memory_region_init_io(&d->io_bar, OBJECT(d), &pcnet_io_ops, s, "pcnet-io",
bd8d6f7c	308	PCNET_IOPORT_SIZE);
e824b2cc	309	pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &d->io_bar);
661a1799	310
e824b2cc	311	pci_register_bar(pci_dev, 1, 0, &s->mmio);
661a1799	312
9e64f8a3	313	s->irq = pci_allocate_irq(pci_dev);
661a1799 PB	314	s->phys_mem_read = pci_physical_memory_read;
661a1799 PB	315	s->phys_mem_write = pci_physical_memory_write;
14fecf26	316	s->dma_opaque = pci_dev;
661a1799	317
4c3b2245	318	pcnet_common_init(DEVICE(pci_dev), s, &net_pci_pcnet_info);
661a1799 PB	319	}
	320
	321	static void pci_reset(DeviceState *dev)
	322	{
1f8c7946	323	PCIPCNetState *d = PCI_PCNET(dev);
661a1799 PB	324
	325	pcnet_h_reset(&d->state);
	326	}
	327
ea3b3511 GA	328	static void pcnet_instance_init(Object *obj)
	329	{
	330	PCIPCNetState *d = PCI_PCNET(obj);
	331	PCNetState *s = &d->state;
	332
	333	device_add_bootindex_property(obj, &s->conf.bootindex,
	334	"bootindex", "/ethernet-phy@0",
	335	DEVICE(obj), NULL);
	336	}
	337
40021f08 AL	338	static Property pcnet_properties[] = {
	339	DEFINE_NIC_PROPERTIES(PCIPCNetState, state.conf),
	340	DEFINE_PROP_END_OF_LIST(),
	341	};
	342
	343	static void pcnet_class_init(ObjectClass klass, void data)
	344	{
39bffca2	345	DeviceClass *dc = DEVICE_CLASS(klass);
40021f08 AL	346	PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
40021f08 AL	347
eb1bef94	348	k->realize = pci_pcnet_realize;
40021f08	349	k->exit = pci_pcnet_uninit;
c45e5b5b	350	k->romfile = "efi-pcnet.rom",
40021f08 AL	351	k->vendor_id = PCI_VENDOR_ID_AMD;
	352	k->device_id = PCI_DEVICE_ID_AMD_LANCE;
	353	k->revision = 0x10;
	354	k->class_id = PCI_CLASS_NETWORK_ETHERNET;
39bffca2 AL	355	dc->reset = pci_reset;
	356	dc->vmsd = &vmstate_pci_pcnet;
	357	dc->props = pcnet_properties;
125ee0ed	358	set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
40021f08 AL	359	}
40021f08 AL	360
8c43a6f0	361	static const TypeInfo pcnet_info = {
1f8c7946	362	.name = TYPE_PCI_PCNET,
39bffca2 AL	363	.parent = TYPE_PCI_DEVICE,
	364	.instance_size = sizeof(PCIPCNetState),
	365	.class_init = pcnet_class_init,
ea3b3511	366	.instance_init = pcnet_instance_init,
661a1799 PB	367	};
661a1799 PB	368
83f7d43a	369	static void pci_pcnet_register_types(void)
661a1799	370	{
39bffca2	371	type_register_static(&pcnet_info);
661a1799 PB	372	}
661a1799 PB	373
83f7d43a	374	type_init(pci_pcnet_register_types)