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Fix TLB access (Jakub Jermar)
[qemu.git] / target-ppc / translate.c
CommitLineData
79aceca5 1/*
3fc6c082 2 * PowerPC emulation for qemu: main translation routines.
5fafdf24 3 *
76a66253 4 * Copyright (c) 2003-2007 Jocelyn Mayer
79aceca5
FB		 5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
fad6cb1a 18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
79aceca5 19 */
c6a1c22b
FB		 20#include <stdarg.h>
21#include <stdlib.h>
22#include <stdio.h>
23#include <string.h>
24#include <inttypes.h>
25
79aceca5 26#include "cpu.h"
c6a1c22b 27#include "exec-all.h"
79aceca5 28#include "disas.h"
57fec1fe 29#include "tcg-op.h"
ca10f867 30#include "qemu-common.h"
79aceca5 31
a7812ae4
PB		 32#include "helper.h"
33#define GEN_HELPER 1
34#include "helper.h"
35
8cbcb4fa
AJ		 36#define CPU_SINGLE_STEP 0x1
37#define CPU_BRANCH_STEP 0x2
38#define GDBSTUB_SINGLE_STEP 0x4
39
a750fc0b 40/* Include definitions for instructions classes and implementations flags */
e8fc4fa7 41//#define DO_SINGLE_STEP
9fddaa0c 42//#define PPC_DEBUG_DISAS
76a66253 43//#define DO_PPC_STATISTICS
79aceca5 44
a750fc0b
JM		 45/*****************************************************************************/
46/* Code translation helpers */
c53be334 47
f78fb44e 48/* global register indexes */
a7812ae4 49static TCGv_ptr cpu_env;
1d542695 50static char cpu_reg_names[10*3 + 22*4 /* GPR */
f78fb44e 51#if !defined(TARGET_PPC64)
1d542695 52 + 10*4 + 22*5 /* SPE GPRh */
f78fb44e 53#endif
a5e26afa 54 + 10*4 + 22*5 /* FPR */
47e4661c
AJ		 55 + 2*(10*6 + 22*7) /* AVRh, AVRl */
56 + 8*5 /* CRF */];
f78fb44e
AJ		 57static TCGv cpu_gpr[32];
58#if !defined(TARGET_PPC64)
59static TCGv cpu_gprh[32];
60#endif
a7812ae4
PB		 61static TCGv_i64 cpu_fpr[32];
62static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
63static TCGv_i32 cpu_crf[8];
bd568f18 64static TCGv cpu_nip;
6527f6ea 65static TCGv cpu_msr;
cfdcd37a
AJ		 66static TCGv cpu_ctr;
67static TCGv cpu_lr;
3d7b417e 68static TCGv cpu_xer;
cf360a32 69static TCGv cpu_reserve;
a7812ae4 70static TCGv_i32 cpu_fpscr;
a7859e89 71static TCGv_i32 cpu_access_type;
f78fb44e 72
2e70f6ef
PB		 73#include "gen-icount.h"
74
75void ppc_translate_init(void)
76{
f78fb44e
AJ		 77 int i;
78 char* p;
b2437bf2 79 static int done_init = 0;
f78fb44e 80
2e70f6ef
PB		 81 if (done_init)
82 return;
f78fb44e 83
a7812ae4 84 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
a7812ae4 85
f78fb44e 86 p = cpu_reg_names;
47e4661c
AJ		 87
88 for (i = 0; i < 8; i++) {
89 sprintf(p, "crf%d", i);
a7812ae4
PB		 90 cpu_crf[i] = tcg_global_mem_new_i32(TCG_AREG0,
91 offsetof(CPUState, crf[i]), p);
47e4661c
AJ		 92 p += 5;
93 }
94
f78fb44e
AJ		 95 for (i = 0; i < 32; i++) {
96 sprintf(p, "r%d", i);
a7812ae4 97 cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0,
f78fb44e
AJ		 98 offsetof(CPUState, gpr[i]), p);
99 p += (i < 10) ? 3 : 4;
100#if !defined(TARGET_PPC64)
101 sprintf(p, "r%dH", i);
a7812ae4
PB		 102 cpu_gprh[i] = tcg_global_mem_new_i32(TCG_AREG0,
103 offsetof(CPUState, gprh[i]), p);
f78fb44e
AJ		 104 p += (i < 10) ? 4 : 5;
105#endif
1d542695 106
a5e26afa 107 sprintf(p, "fp%d", i);
a7812ae4
PB		 108 cpu_fpr[i] = tcg_global_mem_new_i64(TCG_AREG0,
109 offsetof(CPUState, fpr[i]), p);
ec1ac72d 110 p += (i < 10) ? 4 : 5;
a5e26afa 111
1d542695 112 sprintf(p, "avr%dH", i);
fe1e5c53
AJ		 113#ifdef WORDS_BIGENDIAN
114 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
115 offsetof(CPUState, avr[i].u64[0]), p);
116#else
a7812ae4 117 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
fe1e5c53
AJ		 118 offsetof(CPUState, avr[i].u64[1]), p);
119#endif
1d542695 120 p += (i < 10) ? 6 : 7;
ec1ac72d 121
1d542695 122 sprintf(p, "avr%dL", i);
fe1e5c53
AJ		 123#ifdef WORDS_BIGENDIAN
124 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
125 offsetof(CPUState, avr[i].u64[1]), p);
126#else
a7812ae4 127 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
fe1e5c53
AJ		 128 offsetof(CPUState, avr[i].u64[0]), p);
129#endif
1d542695 130 p += (i < 10) ? 6 : 7;
f78fb44e 131 }
f10dc08e 132
a7812ae4 133 cpu_nip = tcg_global_mem_new(TCG_AREG0,
bd568f18
AJ		 134 offsetof(CPUState, nip), "nip");
135
6527f6ea
AJ		 136 cpu_msr = tcg_global_mem_new(TCG_AREG0,
137 offsetof(CPUState, msr), "msr");
138
a7812ae4 139 cpu_ctr = tcg_global_mem_new(TCG_AREG0,
cfdcd37a
AJ		 140 offsetof(CPUState, ctr), "ctr");
141
a7812ae4 142 cpu_lr = tcg_global_mem_new(TCG_AREG0,
cfdcd37a
AJ		 143 offsetof(CPUState, lr), "lr");
144
a7812ae4 145 cpu_xer = tcg_global_mem_new(TCG_AREG0,
3d7b417e
AJ		 146 offsetof(CPUState, xer), "xer");
147
cf360a32
AJ		 148 cpu_reserve = tcg_global_mem_new(TCG_AREG0,
149 offsetof(CPUState, reserve), "reserve");
150
a7812ae4
PB		 151 cpu_fpscr = tcg_global_mem_new_i32(TCG_AREG0,
152 offsetof(CPUState, fpscr), "fpscr");
e1571908 153
a7859e89
AJ		 154 cpu_access_type = tcg_global_mem_new_i32(TCG_AREG0,
155 offsetof(CPUState, access_type), "access_type");
156
f10dc08e 157 /* register helpers */
a7812ae4 158#define GEN_HELPER 2
f10dc08e
AJ		 159#include "helper.h"
160
2e70f6ef
PB		 161 done_init = 1;
162}
163
79aceca5
FB		 164/* internal defines */
165typedef struct DisasContext {
166 struct TranslationBlock *tb;
0fa85d43 167 target_ulong nip;
79aceca5 168 uint32_t opcode;
9a64fbe4 169 uint32_t exception;
3cc62370
FB		 170 /* Routine used to access memory */
171 int mem_idx;
76db3ba4 172 int access_type;
3cc62370 173 /* Translation flags */
76db3ba4 174 int le_mode;
d9bce9d9
JM		 175#if defined(TARGET_PPC64)
176 int sf_mode;
9a64fbe4 177#endif
3cc62370 178 int fpu_enabled;
a9d9eb8f 179 int altivec_enabled;
0487d6a8 180 int spe_enabled;
3fc6c082 181 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
ea4e754f 182 int singlestep_enabled;
79aceca5
FB		 183} DisasContext;
184
3fc6c082 185struct opc_handler_t {
79aceca5
FB		 186 /* invalid bits */
187 uint32_t inval;
9a64fbe4 188 /* instruction type */
0487d6a8 189 uint64_t type;
79aceca5
FB		 190 /* handler */
191 void (*handler)(DisasContext *ctx);
a750fc0b 192#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
b55266b5 193 const char *oname;
a750fc0b
JM		 194#endif
195#if defined(DO_PPC_STATISTICS)
76a66253
JM		 196 uint64_t count;
197#endif
3fc6c082 198};
79aceca5 199
7c58044c
JM		 200static always_inline void gen_reset_fpstatus (void)
201{
202#ifdef CONFIG_SOFTFLOAT
a44d2ce1 203 gen_helper_reset_fpstatus();
7c58044c
JM		 204#endif
205}
206
0f2f39c2 207static always_inline void gen_compute_fprf (TCGv_i64 arg, int set_fprf, int set_rc)
7c58044c 208{
0f2f39c2 209 TCGv_i32 t0 = tcg_temp_new_i32();
af12906f 210
7c58044c
JM		 211 if (set_fprf != 0) {
212 /* This case might be optimized later */
0f2f39c2 213 tcg_gen_movi_i32(t0, 1);
af12906f 214 gen_helper_compute_fprf(t0, arg, t0);
a7812ae4 215 if (unlikely(set_rc)) {
0f2f39c2 216 tcg_gen_mov_i32(cpu_crf[1], t0);
a7812ae4 217 }
af12906f 218 gen_helper_float_check_status();
7c58044c
JM		 219 } else if (unlikely(set_rc)) {
220 /* We always need to compute fpcc */
0f2f39c2 221 tcg_gen_movi_i32(t0, 0);
af12906f 222 gen_helper_compute_fprf(t0, arg, t0);
0f2f39c2 223 tcg_gen_mov_i32(cpu_crf[1], t0);
7c58044c 224 }
af12906f 225
0f2f39c2 226 tcg_temp_free_i32(t0);
7c58044c
JM		 227}
228
76db3ba4 229static always_inline void gen_set_access_type (DisasContext *ctx, int access_type)
a7859e89 230{
76db3ba4
AJ		 231 if (ctx->access_type != access_type) {
232 tcg_gen_movi_i32(cpu_access_type, access_type);
233 ctx->access_type = access_type;
234 }
a7859e89
AJ		 235}
236
b068d6a7 237static always_inline void gen_update_nip (DisasContext *ctx, target_ulong nip)
d9bce9d9
JM		 238{
239#if defined(TARGET_PPC64)
240 if (ctx->sf_mode)
bd568f18 241 tcg_gen_movi_tl(cpu_nip, nip);
d9bce9d9
JM		 242 else
243#endif
bd568f18 244 tcg_gen_movi_tl(cpu_nip, (uint32_t)nip);
d9bce9d9
JM		 245}
246
e06fcd75
AJ		 247static always_inline void gen_exception_err (DisasContext *ctx, uint32_t excp, uint32_t error)
248{
249 TCGv_i32 t0, t1;
250 if (ctx->exception == POWERPC_EXCP_NONE) {
251 gen_update_nip(ctx, ctx->nip);
252 }
253 t0 = tcg_const_i32(excp);
254 t1 = tcg_const_i32(error);
255 gen_helper_raise_exception_err(t0, t1);
256 tcg_temp_free_i32(t0);
257 tcg_temp_free_i32(t1);
258 ctx->exception = (excp);
259}
e1833e1f 260
e06fcd75
AJ		 261static always_inline void gen_exception (DisasContext *ctx, uint32_t excp)
262{
263 TCGv_i32 t0;
264 if (ctx->exception == POWERPC_EXCP_NONE) {
265 gen_update_nip(ctx, ctx->nip);
266 }
267 t0 = tcg_const_i32(excp);
268 gen_helper_raise_exception(t0);
269 tcg_temp_free_i32(t0);
270 ctx->exception = (excp);
271}
e1833e1f 272
e06fcd75
AJ		 273static always_inline void gen_debug_exception (DisasContext *ctx)
274{
275 TCGv_i32 t0;
276 gen_update_nip(ctx, ctx->nip);
277 t0 = tcg_const_i32(EXCP_DEBUG);
278 gen_helper_raise_exception(t0);
279 tcg_temp_free_i32(t0);
280}
9a64fbe4 281
e06fcd75
AJ		 282static always_inline void gen_inval_exception (DisasContext *ctx, uint32_t error)
283{
284 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | error);
285}
a9d9eb8f 286
f24e5695 287/* Stop translation */
e06fcd75 288static always_inline void gen_stop_exception (DisasContext *ctx)
3fc6c082 289{
d9bce9d9 290 gen_update_nip(ctx, ctx->nip);
e1833e1f 291 ctx->exception = POWERPC_EXCP_STOP;
3fc6c082
FB		 292}
293
f24e5695 294/* No need to update nip here, as execution flow will change */
e06fcd75 295static always_inline void gen_sync_exception (DisasContext *ctx)
2be0071f 296{
e1833e1f 297 ctx->exception = POWERPC_EXCP_SYNC;
2be0071f
FB		 298}
299
79aceca5
FB		 300#define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
301static void gen_##name (DisasContext *ctx); \
302GEN_OPCODE(name, opc1, opc2, opc3, inval, type); \
303static void gen_##name (DisasContext *ctx)
304
c7697e1f
JM		 305#define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
306static void gen_##name (DisasContext *ctx); \
307GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type); \
308static void gen_##name (DisasContext *ctx)
309
79aceca5
FB		 310typedef struct opcode_t {
311 unsigned char opc1, opc2, opc3;
1235fc06 312#if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
18fba28c
FB		 313 unsigned char pad[5];
314#else
315 unsigned char pad[1];
316#endif
79aceca5 317 opc_handler_t handler;
b55266b5 318 const char *oname;
79aceca5
FB		 319} opcode_t;
320
a750fc0b 321/*****************************************************************************/
79aceca5
FB		 322/*** Instruction decoding ***/
323#define EXTRACT_HELPER(name, shift, nb) \
b068d6a7 324static always_inline uint32_t name (uint32_t opcode) \
79aceca5
FB		 325{ \
326 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
327}
328
329#define EXTRACT_SHELPER(name, shift, nb) \
b068d6a7 330static always_inline int32_t name (uint32_t opcode) \
79aceca5 331{ \
18fba28c 332 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
79aceca5
FB		 333}
334
335/* Opcode part 1 */
336EXTRACT_HELPER(opc1, 26, 6);
337/* Opcode part 2 */
338EXTRACT_HELPER(opc2, 1, 5);
339/* Opcode part 3 */
340EXTRACT_HELPER(opc3, 6, 5);
341/* Update Cr0 flags */
342EXTRACT_HELPER(Rc, 0, 1);
343/* Destination */
344EXTRACT_HELPER(rD, 21, 5);
345/* Source */
346EXTRACT_HELPER(rS, 21, 5);
347/* First operand */
348EXTRACT_HELPER(rA, 16, 5);
349/* Second operand */
350EXTRACT_HELPER(rB, 11, 5);
351/* Third operand */
352EXTRACT_HELPER(rC, 6, 5);
353/*** Get CRn ***/
354EXTRACT_HELPER(crfD, 23, 3);
355EXTRACT_HELPER(crfS, 18, 3);
356EXTRACT_HELPER(crbD, 21, 5);
357EXTRACT_HELPER(crbA, 16, 5);
358EXTRACT_HELPER(crbB, 11, 5);
359/* SPR / TBL */
3fc6c082 360EXTRACT_HELPER(_SPR, 11, 10);
b068d6a7 361static always_inline uint32_t SPR (uint32_t opcode)
3fc6c082
FB		 362{
363 uint32_t sprn = _SPR(opcode);
364
365 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
366}
79aceca5
FB		 367/*** Get constants ***/
368EXTRACT_HELPER(IMM, 12, 8);
369/* 16 bits signed immediate value */
370EXTRACT_SHELPER(SIMM, 0, 16);
371/* 16 bits unsigned immediate value */
372EXTRACT_HELPER(UIMM, 0, 16);
21d21583
AJ		 373/* 5 bits signed immediate value */
374EXTRACT_HELPER(SIMM5, 16, 5);
27a4edb3
AJ		 375/* 5 bits signed immediate value */
376EXTRACT_HELPER(UIMM5, 16, 5);
79aceca5
FB		 377/* Bit count */
378EXTRACT_HELPER(NB, 11, 5);
379/* Shift count */
380EXTRACT_HELPER(SH, 11, 5);
cd633b10
AJ		 381/* Vector shift count */
382EXTRACT_HELPER(VSH, 6, 4);
79aceca5
FB		 383/* Mask start */
384EXTRACT_HELPER(MB, 6, 5);
385/* Mask end */
386EXTRACT_HELPER(ME, 1, 5);
fb0eaffc
FB		 387/* Trap operand */
388EXTRACT_HELPER(TO, 21, 5);
79aceca5
FB		 389
390EXTRACT_HELPER(CRM, 12, 8);
391EXTRACT_HELPER(FM, 17, 8);
392EXTRACT_HELPER(SR, 16, 4);
e4bb997e 393EXTRACT_HELPER(FPIMM, 12, 4);
fb0eaffc 394
79aceca5
FB		 395/*** Jump target decoding ***/
396/* Displacement */
397EXTRACT_SHELPER(d, 0, 16);
398/* Immediate address */
b068d6a7 399static always_inline target_ulong LI (uint32_t opcode)
79aceca5
FB		 400{
401 return (opcode >> 0) & 0x03FFFFFC;
402}
403
b068d6a7 404static always_inline uint32_t BD (uint32_t opcode)
79aceca5
FB		 405{
406 return (opcode >> 0) & 0xFFFC;
407}
408
409EXTRACT_HELPER(BO, 21, 5);
410EXTRACT_HELPER(BI, 16, 5);
411/* Absolute/relative address */
412EXTRACT_HELPER(AA, 1, 1);
413/* Link */
414EXTRACT_HELPER(LK, 0, 1);
415
416/* Create a mask between <start> and <end> bits */
b068d6a7 417static always_inline target_ulong MASK (uint32_t start, uint32_t end)
79aceca5 418{
76a66253 419 target_ulong ret;
79aceca5 420
76a66253
JM		 421#if defined(TARGET_PPC64)
422 if (likely(start == 0)) {
6f2d8978 423 ret = UINT64_MAX << (63 - end);
76a66253 424 } else if (likely(end == 63)) {
6f2d8978 425 ret = UINT64_MAX >> start;
76a66253
JM		 426 }
427#else
428 if (likely(start == 0)) {
6f2d8978 429 ret = UINT32_MAX << (31 - end);
76a66253 430 } else if (likely(end == 31)) {
6f2d8978 431 ret = UINT32_MAX >> start;
76a66253
JM		 432 }
433#endif
434 else {
435 ret = (((target_ulong)(-1ULL)) >> (start)) ^
436 (((target_ulong)(-1ULL) >> (end)) >> 1);
437 if (unlikely(start > end))
438 return ~ret;
439 }
79aceca5
FB		 440
441 return ret;
442}
443
a750fc0b
JM		 444/*****************************************************************************/
445/* PowerPC Instructions types definitions */
446enum {
1b413d55 447 PPC_NONE = 0x0000000000000000ULL,
12de9a39 448 /* PowerPC base instructions set */
1b413d55
JM		 449 PPC_INSNS_BASE = 0x0000000000000001ULL,
450 /* integer operations instructions */
a750fc0b 451#define PPC_INTEGER PPC_INSNS_BASE
1b413d55 452 /* flow control instructions */
a750fc0b 453#define PPC_FLOW PPC_INSNS_BASE
1b413d55 454 /* virtual memory instructions */
a750fc0b 455#define PPC_MEM PPC_INSNS_BASE
1b413d55 456 /* ld/st with reservation instructions */
a750fc0b 457#define PPC_RES PPC_INSNS_BASE
1b413d55 458 /* spr/msr access instructions */
a750fc0b 459#define PPC_MISC PPC_INSNS_BASE
1b413d55
JM		 460 /* Deprecated instruction sets */
461 /* Original POWER instruction set */
f610349f 462 PPC_POWER = 0x0000000000000002ULL,
1b413d55 463 /* POWER2 instruction set extension */
f610349f 464 PPC_POWER2 = 0x0000000000000004ULL,
1b413d55 465 /* Power RTC support */
f610349f 466 PPC_POWER_RTC = 0x0000000000000008ULL,
1b413d55 467 /* Power-to-PowerPC bridge (601) */
f610349f 468 PPC_POWER_BR = 0x0000000000000010ULL,
1b413d55 469 /* 64 bits PowerPC instruction set */
f610349f 470 PPC_64B = 0x0000000000000020ULL,
1b413d55 471 /* New 64 bits extensions (PowerPC 2.0x) */
f610349f 472 PPC_64BX = 0x0000000000000040ULL,
1b413d55 473 /* 64 bits hypervisor extensions */
f610349f 474 PPC_64H = 0x0000000000000080ULL,
1b413d55 475 /* New wait instruction (PowerPC 2.0x) */
f610349f 476 PPC_WAIT = 0x0000000000000100ULL,
1b413d55 477 /* Time base mftb instruction */
f610349f 478 PPC_MFTB = 0x0000000000000200ULL,
1b413d55
JM		 479
480 /* Fixed-point unit extensions */
481 /* PowerPC 602 specific */
f610349f 482 PPC_602_SPEC = 0x0000000000000400ULL,
05332d70
JM		 483 /* isel instruction */
484 PPC_ISEL = 0x0000000000000800ULL,
485 /* popcntb instruction */
486 PPC_POPCNTB = 0x0000000000001000ULL,
487 /* string load / store */
488 PPC_STRING = 0x0000000000002000ULL,
1b413d55
JM		 489
490 /* Floating-point unit extensions */
491 /* Optional floating point instructions */
492 PPC_FLOAT = 0x0000000000010000ULL,
493 /* New floating-point extensions (PowerPC 2.0x) */
494 PPC_FLOAT_EXT = 0x0000000000020000ULL,
495 PPC_FLOAT_FSQRT = 0x0000000000040000ULL,
496 PPC_FLOAT_FRES = 0x0000000000080000ULL,
497 PPC_FLOAT_FRSQRTE = 0x0000000000100000ULL,
498 PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
499 PPC_FLOAT_FSEL = 0x0000000000400000ULL,
500 PPC_FLOAT_STFIWX = 0x0000000000800000ULL,
501
502 /* Vector/SIMD extensions */
503 /* Altivec support */
504 PPC_ALTIVEC = 0x0000000001000000ULL,
1b413d55 505 /* PowerPC 2.03 SPE extension */
05332d70 506 PPC_SPE = 0x0000000002000000ULL,
1b413d55 507 /* PowerPC 2.03 SPE floating-point extension */
05332d70 508 PPC_SPEFPU = 0x0000000004000000ULL,
1b413d55 509
12de9a39 510 /* Optional memory control instructions */
1b413d55
JM		 511 PPC_MEM_TLBIA = 0x0000000010000000ULL,
512 PPC_MEM_TLBIE = 0x0000000020000000ULL,
513 PPC_MEM_TLBSYNC = 0x0000000040000000ULL,
514 /* sync instruction */
515 PPC_MEM_SYNC = 0x0000000080000000ULL,
516 /* eieio instruction */
517 PPC_MEM_EIEIO = 0x0000000100000000ULL,
518
519 /* Cache control instructions */
c8623f2e 520 PPC_CACHE = 0x0000000200000000ULL,
1b413d55 521 /* icbi instruction */
05332d70 522 PPC_CACHE_ICBI = 0x0000000400000000ULL,
1b413d55 523 /* dcbz instruction with fixed cache line size */
05332d70 524 PPC_CACHE_DCBZ = 0x0000000800000000ULL,
1b413d55 525 /* dcbz instruction with tunable cache line size */
05332d70 526 PPC_CACHE_DCBZT = 0x0000001000000000ULL,
1b413d55 527 /* dcba instruction */
05332d70
JM		 528 PPC_CACHE_DCBA = 0x0000002000000000ULL,
529 /* Freescale cache locking instructions */
530 PPC_CACHE_LOCK = 0x0000004000000000ULL,
1b413d55
JM		 531
532 /* MMU related extensions */
533 /* external control instructions */
05332d70 534 PPC_EXTERN = 0x0000010000000000ULL,
1b413d55 535 /* segment register access instructions */
05332d70 536 PPC_SEGMENT = 0x0000020000000000ULL,
1b413d55 537 /* PowerPC 6xx TLB management instructions */
05332d70 538 PPC_6xx_TLB = 0x0000040000000000ULL,
1b413d55 539 /* PowerPC 74xx TLB management instructions */
05332d70 540 PPC_74xx_TLB = 0x0000080000000000ULL,
1b413d55 541 /* PowerPC 40x TLB management instructions */
05332d70 542 PPC_40x_TLB = 0x0000100000000000ULL,
1b413d55 543 /* segment register access instructions for PowerPC 64 "bridge" */
05332d70 544 PPC_SEGMENT_64B = 0x0000200000000000ULL,
1b413d55 545 /* SLB management */
05332d70 546 PPC_SLBI = 0x0000400000000000ULL,
1b413d55 547
12de9a39 548 /* Embedded PowerPC dedicated instructions */
05332d70 549 PPC_WRTEE = 0x0001000000000000ULL,
12de9a39 550 /* PowerPC 40x exception model */
05332d70 551 PPC_40x_EXCP = 0x0002000000000000ULL,
12de9a39 552 /* PowerPC 405 Mac instructions */
05332d70 553 PPC_405_MAC = 0x0004000000000000ULL,
12de9a39 554 /* PowerPC 440 specific instructions */
05332d70 555 PPC_440_SPEC = 0x0008000000000000ULL,
12de9a39 556 /* BookE (embedded) PowerPC specification */
05332d70
JM		 557 PPC_BOOKE = 0x0010000000000000ULL,
558 /* mfapidi instruction */
559 PPC_MFAPIDI = 0x0020000000000000ULL,
560 /* tlbiva instruction */
561 PPC_TLBIVA = 0x0040000000000000ULL,
562 /* tlbivax instruction */
563 PPC_TLBIVAX = 0x0080000000000000ULL,
12de9a39 564 /* PowerPC 4xx dedicated instructions */
05332d70 565 PPC_4xx_COMMON = 0x0100000000000000ULL,
12de9a39 566 /* PowerPC 40x ibct instructions */
05332d70 567 PPC_40x_ICBT = 0x0200000000000000ULL,
12de9a39 568 /* rfmci is not implemented in all BookE PowerPC */
05332d70
JM		 569 PPC_RFMCI = 0x0400000000000000ULL,
570 /* rfdi instruction */
571 PPC_RFDI = 0x0800000000000000ULL,
572 /* DCR accesses */
573 PPC_DCR = 0x1000000000000000ULL,
574 /* DCR extended accesse */
575 PPC_DCRX = 0x2000000000000000ULL,
12de9a39 576 /* user-mode DCR access, implemented in PowerPC 460 */
05332d70 577 PPC_DCRUX = 0x4000000000000000ULL,
a750fc0b
JM		 578};
579
580/*****************************************************************************/
581/* PowerPC instructions table */
3fc6c082
FB		 582#if HOST_LONG_BITS == 64
583#define OPC_ALIGN 8
584#else
585#define OPC_ALIGN 4
586#endif
1b039c09 587#if defined(__APPLE__)
d9bce9d9 588#define OPCODES_SECTION \
3fc6c082 589 __attribute__ ((section("__TEXT,__opcodes"), unused, aligned (OPC_ALIGN) ))
933dc6eb 590#else
d9bce9d9 591#define OPCODES_SECTION \
3fc6c082 592 __attribute__ ((section(".opcodes"), unused, aligned (OPC_ALIGN) ))
933dc6eb
FB		 593#endif
594
76a66253 595#if defined(DO_PPC_STATISTICS)
79aceca5 596#define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
18fba28c 597OPCODES_SECTION opcode_t opc_##name = { \
79aceca5
FB		 598 .opc1 = op1, \
599 .opc2 = op2, \
600 .opc3 = op3, \
18fba28c 601 .pad = { 0, }, \
79aceca5
FB		 602 .handler = { \
603 .inval = invl, \
9a64fbe4 604 .type = _typ, \
79aceca5 605 .handler = &gen_##name, \
76a66253 606 .oname = stringify(name), \
79aceca5 607 }, \
3fc6c082 608 .oname = stringify(name), \
79aceca5 609}
c7697e1f
JM		 610#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
611OPCODES_SECTION opcode_t opc_##name = { \
612 .opc1 = op1, \
613 .opc2 = op2, \
614 .opc3 = op3, \
615 .pad = { 0, }, \
616 .handler = { \
617 .inval = invl, \
618 .type = _typ, \
619 .handler = &gen_##name, \
620 .oname = onam, \
621 }, \
622 .oname = onam, \
623}
76a66253
JM		 624#else
625#define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
626OPCODES_SECTION opcode_t opc_##name = { \
627 .opc1 = op1, \
628 .opc2 = op2, \
629 .opc3 = op3, \
630 .pad = { 0, }, \
631 .handler = { \
632 .inval = invl, \
633 .type = _typ, \
634 .handler = &gen_##name, \
635 }, \
636 .oname = stringify(name), \
637}
c7697e1f
JM		 638#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
639OPCODES_SECTION opcode_t opc_##name = { \
640 .opc1 = op1, \
641 .opc2 = op2, \
642 .opc3 = op3, \
643 .pad = { 0, }, \
644 .handler = { \
645 .inval = invl, \
646 .type = _typ, \
647 .handler = &gen_##name, \
648 }, \
649 .oname = onam, \
650}
76a66253 651#endif
79aceca5
FB		 652
653#define GEN_OPCODE_MARK(name) \
18fba28c 654OPCODES_SECTION opcode_t opc_##name = { \
79aceca5
FB		 655 .opc1 = 0xFF, \
656 .opc2 = 0xFF, \
657 .opc3 = 0xFF, \
18fba28c 658 .pad = { 0, }, \
79aceca5
FB		 659 .handler = { \
660 .inval = 0x00000000, \
9a64fbe4 661 .type = 0x00, \
79aceca5
FB		 662 .handler = NULL, \
663 }, \
3fc6c082 664 .oname = stringify(name), \
79aceca5
FB		 665}
666
54cdcae6
AJ		 667/* SPR load/store helpers */
668static always_inline void gen_load_spr(TCGv t, int reg)
669{
670 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUState, spr[reg]));
671}
672
673static always_inline void gen_store_spr(int reg, TCGv t)
674{
675 tcg_gen_st_tl(t, cpu_env, offsetof(CPUState, spr[reg]));
676}
677
79aceca5
FB		 678/* Start opcode list */
679GEN_OPCODE_MARK(start);
680
681/* Invalid instruction */
9a64fbe4
FB		 682GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE)
683{
e06fcd75 684 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
9a64fbe4
FB		 685}
686
79aceca5
FB		 687static opc_handler_t invalid_handler = {
688 .inval = 0xFFFFFFFF,
9a64fbe4 689 .type = PPC_NONE,
79aceca5
FB		 690 .handler = gen_invalid,
691};
692
e1571908
AJ		 693/*** Integer comparison ***/
694
ea363694 695static always_inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
e1571908
AJ		 696{
697 int l1, l2, l3;
698
269f3e95
AJ		 699 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_xer);
700 tcg_gen_shri_i32(cpu_crf[crf], cpu_crf[crf], XER_SO);
e1571908
AJ		 701 tcg_gen_andi_i32(cpu_crf[crf], cpu_crf[crf], 1);
702
703 l1 = gen_new_label();
704 l2 = gen_new_label();
705 l3 = gen_new_label();
706 if (s) {
ea363694
AJ		 707 tcg_gen_brcond_tl(TCG_COND_LT, arg0, arg1, l1);
708 tcg_gen_brcond_tl(TCG_COND_GT, arg0, arg1, l2);
e1571908 709 } else {
ea363694
AJ		 710 tcg_gen_brcond_tl(TCG_COND_LTU, arg0, arg1, l1);
711 tcg_gen_brcond_tl(TCG_COND_GTU, arg0, arg1, l2);
e1571908
AJ		 712 }
713 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_EQ);
714 tcg_gen_br(l3);
715 gen_set_label(l1);
716 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_LT);
717 tcg_gen_br(l3);
718 gen_set_label(l2);
719 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_GT);
720 gen_set_label(l3);
721}
722
ea363694 723static always_inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
e1571908 724{
ea363694
AJ		 725 TCGv t0 = tcg_const_local_tl(arg1);
726 gen_op_cmp(arg0, t0, s, crf);
727 tcg_temp_free(t0);
e1571908
AJ		 728}
729
730#if defined(TARGET_PPC64)
ea363694 731static always_inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
e1571908 732{
ea363694 733 TCGv t0, t1;
a7812ae4
PB		 734 t0 = tcg_temp_local_new();
735 t1 = tcg_temp_local_new();
e1571908 736 if (s) {
ea363694
AJ		 737 tcg_gen_ext32s_tl(t0, arg0);
738 tcg_gen_ext32s_tl(t1, arg1);
e1571908 739 } else {
ea363694
AJ		 740 tcg_gen_ext32u_tl(t0, arg0);
741 tcg_gen_ext32u_tl(t1, arg1);
e1571908 742 }
ea363694
AJ		 743 gen_op_cmp(t0, t1, s, crf);
744 tcg_temp_free(t1);
745 tcg_temp_free(t0);
e1571908
AJ		 746}
747
ea363694 748static always_inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
e1571908 749{
ea363694
AJ		 750 TCGv t0 = tcg_const_local_tl(arg1);
751 gen_op_cmp32(arg0, t0, s, crf);
752 tcg_temp_free(t0);
e1571908
AJ		 753}
754#endif
755
756static always_inline void gen_set_Rc0 (DisasContext *ctx, TCGv reg)
757{
758#if defined(TARGET_PPC64)
759 if (!(ctx->sf_mode))
760 gen_op_cmpi32(reg, 0, 1, 0);
761 else
762#endif
763 gen_op_cmpi(reg, 0, 1, 0);
764}
765
766/* cmp */
767GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER)
768{
769#if defined(TARGET_PPC64)
770 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
771 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
772 1, crfD(ctx->opcode));
773 else
774#endif
775 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
776 1, crfD(ctx->opcode));
777}
778
779/* cmpi */
780GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
781{
782#if defined(TARGET_PPC64)
783 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
784 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
785 1, crfD(ctx->opcode));
786 else
787#endif
788 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
789 1, crfD(ctx->opcode));
790}
791
792/* cmpl */
793GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER)
794{
795#if defined(TARGET_PPC64)
796 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
797 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
798 0, crfD(ctx->opcode));
799 else
800#endif
801 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
802 0, crfD(ctx->opcode));
803}
804
805/* cmpli */
806GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
807{
808#if defined(TARGET_PPC64)
809 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
810 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
811 0, crfD(ctx->opcode));
812 else
813#endif
814 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
815 0, crfD(ctx->opcode));
816}
817
818/* isel (PowerPC 2.03 specification) */
819GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL)
820{
821 int l1, l2;
822 uint32_t bi = rC(ctx->opcode);
823 uint32_t mask;
a7812ae4 824 TCGv_i32 t0;
e1571908
AJ		 825
826 l1 = gen_new_label();
827 l2 = gen_new_label();
828
829 mask = 1 << (3 - (bi & 0x03));
a7812ae4 830 t0 = tcg_temp_new_i32();
fea0c503
AJ		 831 tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask);
832 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
e1571908
AJ		 833 if (rA(ctx->opcode) == 0)
834 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
835 else
836 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
837 tcg_gen_br(l2);
838 gen_set_label(l1);
839 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
840 gen_set_label(l2);
a7812ae4 841 tcg_temp_free_i32(t0);
e1571908
AJ		 842}
843
79aceca5 844/*** Integer arithmetic ***/
79aceca5 845
74637406
AJ		 846static always_inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, TCGv arg1, TCGv arg2, int sub)
847{
848 int l1;
849 TCGv t0;
79aceca5 850
74637406
AJ		 851 l1 = gen_new_label();
852 /* Start with XER OV disabled, the most likely case */
853 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
a7812ae4 854 t0 = tcg_temp_local_new();
74637406
AJ		 855 tcg_gen_xor_tl(t0, arg0, arg1);
856#if defined(TARGET_PPC64)
857 if (!ctx->sf_mode)
858 tcg_gen_ext32s_tl(t0, t0);
859#endif
860 if (sub)
861 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1);
862 else
863 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
864 tcg_gen_xor_tl(t0, arg1, arg2);
865#if defined(TARGET_PPC64)
866 if (!ctx->sf_mode)
867 tcg_gen_ext32s_tl(t0, t0);
868#endif
869 if (sub)
870 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
871 else
872 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1);
873 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
874 gen_set_label(l1);
875 tcg_temp_free(t0);
79aceca5
FB		 876}
877
74637406
AJ		 878static always_inline void gen_op_arith_compute_ca(DisasContext *ctx, TCGv arg1, TCGv arg2, int sub)
879{
880 int l1 = gen_new_label();
d9bce9d9
JM		 881
882#if defined(TARGET_PPC64)
74637406
AJ		 883 if (!(ctx->sf_mode)) {
884 TCGv t0, t1;
a7812ae4
PB		 885 t0 = tcg_temp_new();
886 t1 = tcg_temp_new();
d9bce9d9 887
74637406
AJ		 888 tcg_gen_ext32u_tl(t0, arg1);
889 tcg_gen_ext32u_tl(t1, arg2);
890 if (sub) {
891 tcg_gen_brcond_tl(TCG_COND_GTU, t0, t1, l1);
bdc4e053 892 } else {
74637406
AJ		 893 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
894 }
a9730017
AJ		 895 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
896 gen_set_label(l1);
897 tcg_temp_free(t0);
898 tcg_temp_free(t1);
74637406
AJ		 899 } else
900#endif
a9730017
AJ		 901 {
902 if (sub) {
903 tcg_gen_brcond_tl(TCG_COND_GTU, arg1, arg2, l1);
904 } else {
905 tcg_gen_brcond_tl(TCG_COND_GEU, arg1, arg2, l1);
906 }
907 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
908 gen_set_label(l1);
74637406 909 }
d9bce9d9
JM		 910}
911
74637406
AJ		 912/* Common add function */
913static always_inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
914 int add_ca, int compute_ca, int compute_ov)
915{
916 TCGv t0, t1;
d9bce9d9 917
74637406 918 if ((!compute_ca && !compute_ov) ||
a7812ae4 919 (!TCGV_EQUAL(ret,arg1) && !TCGV_EQUAL(ret, arg2))) {
74637406
AJ		 920 t0 = ret;
921 } else {
a7812ae4 922 t0 = tcg_temp_local_new();
74637406 923 }
79aceca5 924
74637406 925 if (add_ca) {
a7812ae4 926 t1 = tcg_temp_local_new();
74637406
AJ		 927 tcg_gen_andi_tl(t1, cpu_xer, (1 << XER_CA));
928 tcg_gen_shri_tl(t1, t1, XER_CA);
929 }
79aceca5 930
74637406
AJ		 931 if (compute_ca && compute_ov) {
932 /* Start with XER CA and OV disabled, the most likely case */
933 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~((1 << XER_CA) | (1 << XER_OV)));
934 } else if (compute_ca) {
935 /* Start with XER CA disabled, the most likely case */
936 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
937 } else if (compute_ov) {
938 /* Start with XER OV disabled, the most likely case */
939 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
940 }
79aceca5 941
74637406
AJ		 942 tcg_gen_add_tl(t0, arg1, arg2);
943
944 if (compute_ca) {
945 gen_op_arith_compute_ca(ctx, t0, arg1, 0);
946 }
947 if (add_ca) {
948 tcg_gen_add_tl(t0, t0, t1);
949 gen_op_arith_compute_ca(ctx, t0, t1, 0);
950 tcg_temp_free(t1);
951 }
952 if (compute_ov) {
953 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
954 }
955
956 if (unlikely(Rc(ctx->opcode) != 0))
957 gen_set_Rc0(ctx, t0);
958
a7812ae4 959 if (!TCGV_EQUAL(t0, ret)) {
74637406
AJ		 960 tcg_gen_mov_tl(ret, t0);
961 tcg_temp_free(t0);
962 }
39dd32ee 963}
74637406
AJ		 964/* Add functions with two operands */
965#define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
966GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER) \
967{ \
968 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
969 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
970 add_ca, compute_ca, compute_ov); \
971}
972/* Add functions with one operand and one immediate */
973#define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
974 add_ca, compute_ca, compute_ov) \
975GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER) \
976{ \
977 TCGv t0 = tcg_const_local_tl(const_val); \
978 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
979 cpu_gpr[rA(ctx->opcode)], t0, \
980 add_ca, compute_ca, compute_ov); \
981 tcg_temp_free(t0); \
982}
983
984/* add add. addo addo. */
985GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
986GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
987/* addc addc. addco addco. */
988GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
989GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
990/* adde adde. addeo addeo. */
991GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
992GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
993/* addme addme. addmeo addmeo. */
994GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
995GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
996/* addze addze. addzeo addzeo.*/
997GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
998GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
999/* addi */
1000GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
d9bce9d9 1001{
74637406
AJ		 1002 target_long simm = SIMM(ctx->opcode);
1003
1004 if (rA(ctx->opcode) == 0) {
1005 /* li case */
1006 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
1007 } else {
1008 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm);
1009 }
d9bce9d9 1010}
74637406
AJ		 1011/* addic addic.*/
1012static always_inline void gen_op_addic (DisasContext *ctx, TCGv ret, TCGv arg1,
1013 int compute_Rc0)
d9bce9d9 1014{
74637406
AJ		 1015 target_long simm = SIMM(ctx->opcode);
1016
1017 /* Start with XER CA and OV disabled, the most likely case */
1018 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1019
1020 if (likely(simm != 0)) {
a7812ae4 1021 TCGv t0 = tcg_temp_local_new();
74637406
AJ		 1022 tcg_gen_addi_tl(t0, arg1, simm);
1023 gen_op_arith_compute_ca(ctx, t0, arg1, 0);
1024 tcg_gen_mov_tl(ret, t0);
1025 tcg_temp_free(t0);
1026 } else {
1027 tcg_gen_mov_tl(ret, arg1);
1028 }
1029 if (compute_Rc0) {
1030 gen_set_Rc0(ctx, ret);
1031 }
d9bce9d9 1032}
74637406 1033GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
d9bce9d9 1034{
74637406 1035 gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0);
d9bce9d9 1036}
74637406 1037GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
d9bce9d9 1038{
74637406 1039 gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1);
d9bce9d9 1040}
74637406
AJ		 1041/* addis */
1042GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
d9bce9d9 1043{
74637406
AJ		 1044 target_long simm = SIMM(ctx->opcode);
1045
1046 if (rA(ctx->opcode) == 0) {
1047 /* lis case */
1048 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
1049 } else {
1050 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm << 16);
1051 }
d9bce9d9 1052}
74637406
AJ		 1053
1054static always_inline void gen_op_arith_divw (DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
1055 int sign, int compute_ov)
d9bce9d9 1056{
2ef1b120
AJ		 1057 int l1 = gen_new_label();
1058 int l2 = gen_new_label();
a7812ae4
PB		 1059 TCGv_i32 t0 = tcg_temp_local_new_i32();
1060 TCGv_i32 t1 = tcg_temp_local_new_i32();
74637406 1061
2ef1b120
AJ		 1062 tcg_gen_trunc_tl_i32(t0, arg1);
1063 tcg_gen_trunc_tl_i32(t1, arg2);
1064 tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
74637406 1065 if (sign) {
2ef1b120
AJ		 1066 int l3 = gen_new_label();
1067 tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
1068 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
74637406 1069 gen_set_label(l3);
2ef1b120 1070 tcg_gen_div_i32(t0, t0, t1);
74637406 1071 } else {
2ef1b120 1072 tcg_gen_divu_i32(t0, t0, t1);
74637406
AJ		 1073 }
1074 if (compute_ov) {
1075 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1076 }
1077 tcg_gen_br(l2);
1078 gen_set_label(l1);
1079 if (sign) {
2ef1b120 1080 tcg_gen_sari_i32(t0, t0, 31);
74637406
AJ		 1081 } else {
1082 tcg_gen_movi_i32(t0, 0);
1083 }
1084 if (compute_ov) {
1085 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1086 }
1087 gen_set_label(l2);
2ef1b120 1088 tcg_gen_extu_i32_tl(ret, t0);
a7812ae4
PB		 1089 tcg_temp_free_i32(t0);
1090 tcg_temp_free_i32(t1);
74637406
AJ		 1091 if (unlikely(Rc(ctx->opcode) != 0))
1092 gen_set_Rc0(ctx, ret);
d9bce9d9 1093}
74637406
AJ		 1094/* Div functions */
1095#define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
1096GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER) \
1097{ \
1098 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
1099 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1100 sign, compute_ov); \
1101}
1102/* divwu divwu. divwuo divwuo. */
1103GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
1104GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
1105/* divw divw. divwo divwo. */
1106GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
1107GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
d9bce9d9 1108#if defined(TARGET_PPC64)
2ef1b120
AJ		 1109static always_inline void gen_op_arith_divd (DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
1110 int sign, int compute_ov)
d9bce9d9 1111{
2ef1b120
AJ		 1112 int l1 = gen_new_label();
1113 int l2 = gen_new_label();
74637406
AJ		 1114
1115 tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
1116 if (sign) {
2ef1b120 1117 int l3 = gen_new_label();
74637406
AJ		 1118 tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
1119 tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);
1120 gen_set_label(l3);
74637406
AJ		 1121 tcg_gen_div_i64(ret, arg1, arg2);
1122 } else {
1123 tcg_gen_divu_i64(ret, arg1, arg2);
1124 }
1125 if (compute_ov) {
1126 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1127 }
1128 tcg_gen_br(l2);
1129 gen_set_label(l1);
1130 if (sign) {
1131 tcg_gen_sari_i64(ret, arg1, 63);
1132 } else {
1133 tcg_gen_movi_i64(ret, 0);
1134 }
1135 if (compute_ov) {
1136 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1137 }
1138 gen_set_label(l2);
1139 if (unlikely(Rc(ctx->opcode) != 0))
1140 gen_set_Rc0(ctx, ret);
d9bce9d9 1141}
74637406
AJ		 1142#define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1143GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) \
1144{ \
2ef1b120
AJ		 1145 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1146 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1147 sign, compute_ov); \
74637406
AJ		 1148}
1149/* divwu divwu. divwuo divwuo. */
1150GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1151GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1152/* divw divw. divwo divwo. */
1153GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1154GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
d9bce9d9 1155#endif
74637406
AJ		 1156
1157/* mulhw mulhw. */
1158GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER)
d9bce9d9 1159{
a7812ae4 1160 TCGv_i64 t0, t1;
74637406 1161
a7812ae4
PB		 1162 t0 = tcg_temp_new_i64();
1163 t1 = tcg_temp_new_i64();
74637406
AJ		 1164#if defined(TARGET_PPC64)
1165 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
1166 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
1167 tcg_gen_mul_i64(t0, t0, t1);
1168 tcg_gen_shri_i64(cpu_gpr[rD(ctx->opcode)], t0, 32);
1169#else
1170 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1171 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1172 tcg_gen_mul_i64(t0, t0, t1);
1173 tcg_gen_shri_i64(t0, t0, 32);
1174 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1175#endif
a7812ae4
PB		 1176 tcg_temp_free_i64(t0);
1177 tcg_temp_free_i64(t1);
74637406
AJ		 1178 if (unlikely(Rc(ctx->opcode) != 0))
1179 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1180}
74637406
AJ		 1181/* mulhwu mulhwu. */
1182GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER)
d9bce9d9 1183{
a7812ae4 1184 TCGv_i64 t0, t1;
74637406 1185
a7812ae4
PB		 1186 t0 = tcg_temp_new_i64();
1187 t1 = tcg_temp_new_i64();
d9bce9d9 1188#if defined(TARGET_PPC64)
74637406
AJ		 1189 tcg_gen_ext32u_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1190 tcg_gen_ext32u_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1191 tcg_gen_mul_i64(t0, t0, t1);
1192 tcg_gen_shri_i64(cpu_gpr[rD(ctx->opcode)], t0, 32);
1193#else
1194 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1195 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1196 tcg_gen_mul_i64(t0, t0, t1);
1197 tcg_gen_shri_i64(t0, t0, 32);
1198 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1199#endif
a7812ae4
PB		 1200 tcg_temp_free_i64(t0);
1201 tcg_temp_free_i64(t1);
74637406
AJ		 1202 if (unlikely(Rc(ctx->opcode) != 0))
1203 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1204}
74637406
AJ		 1205/* mullw mullw. */
1206GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER)
d9bce9d9 1207{
74637406
AJ		 1208 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1209 cpu_gpr[rB(ctx->opcode)]);
1e4c090f 1210 tcg_gen_ext32s_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)]);
74637406
AJ		 1211 if (unlikely(Rc(ctx->opcode) != 0))
1212 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1213}
74637406
AJ		 1214/* mullwo mullwo. */
1215GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER)
d9bce9d9 1216{
74637406 1217 int l1;
a7812ae4 1218 TCGv_i64 t0, t1;
74637406 1219
a7812ae4
PB		 1220 t0 = tcg_temp_new_i64();
1221 t1 = tcg_temp_new_i64();
74637406
AJ		 1222 l1 = gen_new_label();
1223 /* Start with XER OV disabled, the most likely case */
1224 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1225#if defined(TARGET_PPC64)
1226 tcg_gen_ext32s_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1227 tcg_gen_ext32s_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1228#else
1229 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1230 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
d9bce9d9 1231#endif
74637406
AJ		 1232 tcg_gen_mul_i64(t0, t0, t1);
1233#if defined(TARGET_PPC64)
1234 tcg_gen_ext32s_i64(cpu_gpr[rD(ctx->opcode)], t0);
1235 tcg_gen_brcond_i64(TCG_COND_EQ, t0, cpu_gpr[rD(ctx->opcode)], l1);
1236#else
1237 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1238 tcg_gen_ext32s_i64(t1, t0);
1239 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
1240#endif
1241 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1242 gen_set_label(l1);
a7812ae4
PB		 1243 tcg_temp_free_i64(t0);
1244 tcg_temp_free_i64(t1);
74637406
AJ		 1245 if (unlikely(Rc(ctx->opcode) != 0))
1246 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1247}
74637406
AJ		 1248/* mulli */
1249GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
d9bce9d9 1250{
74637406
AJ		 1251 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1252 SIMM(ctx->opcode));
d9bce9d9
JM		 1253}
1254#if defined(TARGET_PPC64)
74637406
AJ		 1255#define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
1256GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) \
1257{ \
a7812ae4 1258 gen_helper_##name (cpu_gpr[rD(ctx->opcode)], \
74637406
AJ		 1259 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
1260 if (unlikely(Rc(ctx->opcode) != 0)) \
1261 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
d9bce9d9 1262}
74637406
AJ		 1263/* mulhd mulhd. */
1264GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00);
1265/* mulhdu mulhdu. */
1266GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02);
1267/* mulld mulld. */
1268GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B)
d9bce9d9 1269{
74637406
AJ		 1270 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1271 cpu_gpr[rB(ctx->opcode)]);
1272 if (unlikely(Rc(ctx->opcode) != 0))
1273 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1274}
74637406
AJ		 1275/* mulldo mulldo. */
1276GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17);
d9bce9d9 1277#endif
74637406
AJ		 1278
1279/* neg neg. nego nego. */
ec6469a3 1280static always_inline void gen_op_arith_neg (DisasContext *ctx, TCGv ret, TCGv arg1, int ov_check)
d9bce9d9 1281{
ec6469a3
AJ		 1282 int l1 = gen_new_label();
1283 int l2 = gen_new_label();
a7812ae4 1284 TCGv t0 = tcg_temp_local_new();
d9bce9d9 1285#if defined(TARGET_PPC64)
74637406 1286 if (ctx->sf_mode) {
741a7444 1287 tcg_gen_mov_tl(t0, arg1);
ec6469a3
AJ		 1288 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT64_MIN, l1);
1289 } else
1290#endif
1291 {
1292 tcg_gen_ext32s_tl(t0, arg1);
74637406
AJ		 1293 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT32_MIN, l1);
1294 }
74637406
AJ		 1295 tcg_gen_neg_tl(ret, arg1);
1296 if (ov_check) {
1297 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1298 }
1299 tcg_gen_br(l2);
1300 gen_set_label(l1);
ec6469a3 1301 tcg_gen_mov_tl(ret, t0);
74637406
AJ		 1302 if (ov_check) {
1303 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1304 }
1305 gen_set_label(l2);
ec6469a3 1306 tcg_temp_free(t0);
74637406
AJ		 1307 if (unlikely(Rc(ctx->opcode) != 0))
1308 gen_set_Rc0(ctx, ret);
1309}
1310GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER)
d9bce9d9 1311{
ec6469a3 1312 gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0);
d9bce9d9 1313}
74637406 1314GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER)
79aceca5 1315{
ec6469a3 1316 gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1);
79aceca5 1317}
74637406
AJ		 1318
1319/* Common subf function */
1320static always_inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
1321 int add_ca, int compute_ca, int compute_ov)
79aceca5 1322{
74637406 1323 TCGv t0, t1;
76a66253 1324
74637406 1325 if ((!compute_ca && !compute_ov) ||
a7812ae4 1326 (!TCGV_EQUAL(ret, arg1) && !TCGV_EQUAL(ret, arg2))) {
74637406 1327 t0 = ret;
e864cabd 1328 } else {
a7812ae4 1329 t0 = tcg_temp_local_new();
d9bce9d9 1330 }
76a66253 1331
74637406 1332 if (add_ca) {
a7812ae4 1333 t1 = tcg_temp_local_new();
74637406
AJ		 1334 tcg_gen_andi_tl(t1, cpu_xer, (1 << XER_CA));
1335 tcg_gen_shri_tl(t1, t1, XER_CA);
d9bce9d9 1336 }
79aceca5 1337
74637406
AJ		 1338 if (compute_ca && compute_ov) {
1339 /* Start with XER CA and OV disabled, the most likely case */
1340 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~((1 << XER_CA) | (1 << XER_OV)));
1341 } else if (compute_ca) {
1342 /* Start with XER CA disabled, the most likely case */
1343 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1344 } else if (compute_ov) {
1345 /* Start with XER OV disabled, the most likely case */
1346 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1347 }
1348
1349 if (add_ca) {
1350 tcg_gen_not_tl(t0, arg1);
1351 tcg_gen_add_tl(t0, t0, arg2);
1352 gen_op_arith_compute_ca(ctx, t0, arg2, 0);
1353 tcg_gen_add_tl(t0, t0, t1);
1354 gen_op_arith_compute_ca(ctx, t0, t1, 0);
1355 tcg_temp_free(t1);
79aceca5 1356 } else {
74637406
AJ		 1357 tcg_gen_sub_tl(t0, arg2, arg1);
1358 if (compute_ca) {
1359 gen_op_arith_compute_ca(ctx, t0, arg2, 1);
1360 }
1361 }
1362 if (compute_ov) {
1363 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1364 }
1365
1366 if (unlikely(Rc(ctx->opcode) != 0))
1367 gen_set_Rc0(ctx, t0);
1368
a7812ae4 1369 if (!TCGV_EQUAL(t0, ret)) {
74637406
AJ		 1370 tcg_gen_mov_tl(ret, t0);
1371 tcg_temp_free(t0);
79aceca5 1372 }
79aceca5 1373}
74637406
AJ		 1374/* Sub functions with Two operands functions */
1375#define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1376GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER) \
1377{ \
1378 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1379 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1380 add_ca, compute_ca, compute_ov); \
1381}
1382/* Sub functions with one operand and one immediate */
1383#define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1384 add_ca, compute_ca, compute_ov) \
1385GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER) \
1386{ \
1387 TCGv t0 = tcg_const_local_tl(const_val); \
1388 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1389 cpu_gpr[rA(ctx->opcode)], t0, \
1390 add_ca, compute_ca, compute_ov); \
1391 tcg_temp_free(t0); \
1392}
1393/* subf subf. subfo subfo. */
1394GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1395GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1396/* subfc subfc. subfco subfco. */
1397GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1398GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1399/* subfe subfe. subfeo subfo. */
1400GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1401GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1402/* subfme subfme. subfmeo subfmeo. */
1403GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1404GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1405/* subfze subfze. subfzeo subfzeo.*/
1406GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1407GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
79aceca5
FB		 1408/* subfic */
1409GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1410{
74637406
AJ		 1411 /* Start with XER CA and OV disabled, the most likely case */
1412 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
a7812ae4 1413 TCGv t0 = tcg_temp_local_new();
74637406
AJ		 1414 TCGv t1 = tcg_const_local_tl(SIMM(ctx->opcode));
1415 tcg_gen_sub_tl(t0, t1, cpu_gpr[rA(ctx->opcode)]);
1416 gen_op_arith_compute_ca(ctx, t0, t1, 1);
1417 tcg_temp_free(t1);
1418 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
1419 tcg_temp_free(t0);
79aceca5
FB		 1420}
1421
79aceca5 1422/*** Integer logical ***/
26d67362
AJ		 1423#define GEN_LOGICAL2(name, tcg_op, opc, type) \
1424GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) \
79aceca5 1425{ \
26d67362
AJ		 1426 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1427 cpu_gpr[rB(ctx->opcode)]); \
76a66253 1428 if (unlikely(Rc(ctx->opcode) != 0)) \
26d67362 1429 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
79aceca5 1430}
79aceca5 1431
26d67362 1432#define GEN_LOGICAL1(name, tcg_op, opc, type) \
d9bce9d9 1433GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) \
79aceca5 1434{ \
26d67362 1435 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
76a66253 1436 if (unlikely(Rc(ctx->opcode) != 0)) \
26d67362 1437 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
79aceca5
FB		 1438}
1439
1440/* and & and. */
26d67362 1441GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
79aceca5 1442/* andc & andc. */
26d67362 1443GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
79aceca5 1444/* andi. */
c7697e1f 1445GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
79aceca5 1446{
26d67362
AJ		 1447 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1448 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5
FB		 1449}
1450/* andis. */
c7697e1f 1451GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
79aceca5 1452{
26d67362
AJ		 1453 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1454 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5 1455}
79aceca5 1456/* cntlzw */
26d67362
AJ		 1457GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER)
1458{
a7812ae4 1459 gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
26d67362 1460 if (unlikely(Rc(ctx->opcode) != 0))
2e31f5d3 1461 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
26d67362 1462}
79aceca5 1463/* eqv & eqv. */
26d67362 1464GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
79aceca5 1465/* extsb & extsb. */
26d67362 1466GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
79aceca5 1467/* extsh & extsh. */
26d67362 1468GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
79aceca5 1469/* nand & nand. */
26d67362 1470GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
79aceca5 1471/* nor & nor. */
26d67362 1472GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
79aceca5 1473/* or & or. */
9a64fbe4
FB		 1474GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER)
1475{
76a66253
JM		 1476 int rs, ra, rb;
1477
1478 rs = rS(ctx->opcode);
1479 ra = rA(ctx->opcode);
1480 rb = rB(ctx->opcode);
1481 /* Optimisation for mr. ri case */
1482 if (rs != ra || rs != rb) {
26d67362
AJ		 1483 if (rs != rb)
1484 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1485 else
1486 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
76a66253 1487 if (unlikely(Rc(ctx->opcode) != 0))
26d67362 1488 gen_set_Rc0(ctx, cpu_gpr[ra]);
76a66253 1489 } else if (unlikely(Rc(ctx->opcode) != 0)) {
26d67362 1490 gen_set_Rc0(ctx, cpu_gpr[rs]);
c80f84e3
JM		 1491#if defined(TARGET_PPC64)
1492 } else {
26d67362
AJ		 1493 int prio = 0;
1494
c80f84e3
JM		 1495 switch (rs) {
1496 case 1:
1497 /* Set process priority to low */
26d67362 1498 prio = 2;
c80f84e3
JM		 1499 break;
1500 case 6:
1501 /* Set process priority to medium-low */
26d67362 1502 prio = 3;
c80f84e3
JM		 1503 break;
1504 case 2:
1505 /* Set process priority to normal */
26d67362 1506 prio = 4;
c80f84e3 1507 break;
be147d08
JM		 1508#if !defined(CONFIG_USER_ONLY)
1509 case 31:
76db3ba4 1510 if (ctx->mem_idx > 0) {
be147d08 1511 /* Set process priority to very low */
26d67362 1512 prio = 1;
be147d08
JM		 1513 }
1514 break;
1515 case 5:
76db3ba4 1516 if (ctx->mem_idx > 0) {
be147d08 1517 /* Set process priority to medium-hight */
26d67362 1518 prio = 5;
be147d08
JM		 1519 }
1520 break;
1521 case 3:
76db3ba4 1522 if (ctx->mem_idx > 0) {
be147d08 1523 /* Set process priority to high */
26d67362 1524 prio = 6;
be147d08
JM		 1525 }
1526 break;
be147d08 1527 case 7:
76db3ba4 1528 if (ctx->mem_idx > 1) {
be147d08 1529 /* Set process priority to very high */
26d67362 1530 prio = 7;
be147d08
JM		 1531 }
1532 break;
be147d08 1533#endif
c80f84e3
JM		 1534 default:
1535 /* nop */
1536 break;
1537 }
26d67362 1538 if (prio) {
a7812ae4 1539 TCGv t0 = tcg_temp_new();
54cdcae6 1540 gen_load_spr(t0, SPR_PPR);
ea363694
AJ		 1541 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1542 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
54cdcae6 1543 gen_store_spr(SPR_PPR, t0);
ea363694 1544 tcg_temp_free(t0);
26d67362 1545 }
c80f84e3 1546#endif
9a64fbe4 1547 }
9a64fbe4 1548}
79aceca5 1549/* orc & orc. */
26d67362 1550GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
79aceca5 1551/* xor & xor. */
9a64fbe4
FB		 1552GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER)
1553{
9a64fbe4 1554 /* Optimisation for "set to zero" case */
26d67362 1555 if (rS(ctx->opcode) != rB(ctx->opcode))
312179c4 1556 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
26d67362
AJ		 1557 else
1558 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
76a66253 1559 if (unlikely(Rc(ctx->opcode) != 0))
26d67362 1560 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
9a64fbe4 1561}
79aceca5
FB		 1562/* ori */
1563GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1564{
76a66253 1565 target_ulong uimm = UIMM(ctx->opcode);
79aceca5 1566
9a64fbe4
FB		 1567 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1568 /* NOP */
76a66253 1569 /* XXX: should handle special NOPs for POWER series */
9a64fbe4 1570 return;
76a66253 1571 }
26d67362 1572 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
79aceca5
FB		 1573}
1574/* oris */
1575GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1576{
76a66253 1577 target_ulong uimm = UIMM(ctx->opcode);
79aceca5 1578
9a64fbe4
FB		 1579 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1580 /* NOP */
1581 return;
76a66253 1582 }
26d67362 1583 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
79aceca5
FB		 1584}
1585/* xori */
1586GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1587{
76a66253 1588 target_ulong uimm = UIMM(ctx->opcode);
9a64fbe4
FB		 1589
1590 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1591 /* NOP */
1592 return;
1593 }
26d67362 1594 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
79aceca5 1595}
79aceca5
FB		 1596/* xoris */
1597GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1598{
76a66253 1599 target_ulong uimm = UIMM(ctx->opcode);
9a64fbe4
FB		 1600
1601 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1602 /* NOP */
1603 return;
1604 }
26d67362 1605 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
79aceca5 1606}
d9bce9d9 1607/* popcntb : PowerPC 2.03 specification */
05332d70 1608GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB)
d9bce9d9 1609{
d9bce9d9
JM		 1610#if defined(TARGET_PPC64)
1611 if (ctx->sf_mode)
a7812ae4 1612 gen_helper_popcntb_64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
d9bce9d9
JM		 1613 else
1614#endif
a7812ae4 1615 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
d9bce9d9
JM		 1616}
1617
1618#if defined(TARGET_PPC64)
1619/* extsw & extsw. */
26d67362 1620GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
d9bce9d9 1621/* cntlzd */
26d67362
AJ		 1622GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B)
1623{
a7812ae4 1624 gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
26d67362
AJ		 1625 if (unlikely(Rc(ctx->opcode) != 0))
1626 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1627}
d9bce9d9
JM		 1628#endif
1629
79aceca5
FB		 1630/*** Integer rotate ***/
1631/* rlwimi & rlwimi. */
1632GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1633{
76a66253 1634 uint32_t mb, me, sh;
79aceca5
FB		 1635
1636 mb = MB(ctx->opcode);
1637 me = ME(ctx->opcode);
76a66253 1638 sh = SH(ctx->opcode);
d03ef511
AJ		 1639 if (likely(sh == 0 && mb == 0 && me == 31)) {
1640 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1641 } else {
d03ef511 1642 target_ulong mask;
a7812ae4
PB		 1643 TCGv t1;
1644 TCGv t0 = tcg_temp_new();
54843a58 1645#if defined(TARGET_PPC64)
a7812ae4
PB		 1646 TCGv_i32 t2 = tcg_temp_new_i32();
1647 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rS(ctx->opcode)]);
1648 tcg_gen_rotli_i32(t2, t2, sh);
1649 tcg_gen_extu_i32_i64(t0, t2);
1650 tcg_temp_free_i32(t2);
54843a58
AJ		 1651#else
1652 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1653#endif
76a66253 1654#if defined(TARGET_PPC64)
d03ef511
AJ		 1655 mb += 32;
1656 me += 32;
76a66253 1657#endif
d03ef511 1658 mask = MASK(mb, me);
a7812ae4 1659 t1 = tcg_temp_new();
d03ef511
AJ		 1660 tcg_gen_andi_tl(t0, t0, mask);
1661 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1662 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1663 tcg_temp_free(t0);
1664 tcg_temp_free(t1);
1665 }
76a66253 1666 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1667 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5
FB		 1668}
1669/* rlwinm & rlwinm. */
1670GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1671{
1672 uint32_t mb, me, sh;
3b46e624 1673
79aceca5
FB		 1674 sh = SH(ctx->opcode);
1675 mb = MB(ctx->opcode);
1676 me = ME(ctx->opcode);
d03ef511
AJ		 1677
1678 if (likely(mb == 0 && me == (31 - sh))) {
1679 if (likely(sh == 0)) {
1680 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1681 } else {
a7812ae4 1682 TCGv t0 = tcg_temp_new();
d03ef511
AJ		 1683 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1684 tcg_gen_shli_tl(t0, t0, sh);
1685 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1686 tcg_temp_free(t0);
79aceca5 1687 }
d03ef511 1688 } else if (likely(sh != 0 && me == 31 && sh == (32 - mb))) {
a7812ae4 1689 TCGv t0 = tcg_temp_new();
d03ef511
AJ		 1690 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1691 tcg_gen_shri_tl(t0, t0, mb);
1692 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1693 tcg_temp_free(t0);
1694 } else {
a7812ae4 1695 TCGv t0 = tcg_temp_new();
54843a58 1696#if defined(TARGET_PPC64)
a7812ae4 1697 TCGv_i32 t1 = tcg_temp_new_i32();
54843a58
AJ		 1698 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1699 tcg_gen_rotli_i32(t1, t1, sh);
1700 tcg_gen_extu_i32_i64(t0, t1);
a7812ae4 1701 tcg_temp_free_i32(t1);
54843a58
AJ		 1702#else
1703 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1704#endif
76a66253 1705#if defined(TARGET_PPC64)
d03ef511
AJ		 1706 mb += 32;
1707 me += 32;
76a66253 1708#endif
d03ef511
AJ		 1709 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1710 tcg_temp_free(t0);
1711 }
76a66253 1712 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1713 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5
FB		 1714}
1715/* rlwnm & rlwnm. */
1716GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1717{
1718 uint32_t mb, me;
54843a58
AJ		 1719 TCGv t0;
1720#if defined(TARGET_PPC64)
a7812ae4 1721 TCGv_i32 t1, t2;
54843a58 1722#endif
79aceca5
FB		 1723
1724 mb = MB(ctx->opcode);
1725 me = ME(ctx->opcode);
a7812ae4 1726 t0 = tcg_temp_new();
d03ef511 1727 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f);
54843a58 1728#if defined(TARGET_PPC64)
a7812ae4
PB		 1729 t1 = tcg_temp_new_i32();
1730 t2 = tcg_temp_new_i32();
54843a58
AJ		 1731 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1732 tcg_gen_trunc_i64_i32(t2, t0);
1733 tcg_gen_rotl_i32(t1, t1, t2);
1734 tcg_gen_extu_i32_i64(t0, t1);
a7812ae4
PB		 1735 tcg_temp_free_i32(t1);
1736 tcg_temp_free_i32(t2);
54843a58
AJ		 1737#else
1738 tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0);
1739#endif
76a66253
JM		 1740 if (unlikely(mb != 0 || me != 31)) {
1741#if defined(TARGET_PPC64)
1742 mb += 32;
1743 me += 32;
1744#endif
54843a58 1745 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
d03ef511 1746 } else {
54843a58 1747 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
79aceca5 1748 }
54843a58 1749 tcg_temp_free(t0);
76a66253 1750 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1751 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5
FB		 1752}
1753
d9bce9d9
JM		 1754#if defined(TARGET_PPC64)
1755#define GEN_PPC64_R2(name, opc1, opc2) \
c7697e1f 1756GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
d9bce9d9
JM		 1757{ \
1758 gen_##name(ctx, 0); \
1759} \
c7697e1f
JM		 1760GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
1761 PPC_64B) \
d9bce9d9
JM		 1762{ \
1763 gen_##name(ctx, 1); \
1764}
1765#define GEN_PPC64_R4(name, opc1, opc2) \
c7697e1f 1766GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
d9bce9d9
JM		 1767{ \
1768 gen_##name(ctx, 0, 0); \
1769} \
c7697e1f
JM		 1770GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
1771 PPC_64B) \
d9bce9d9
JM		 1772{ \
1773 gen_##name(ctx, 0, 1); \
1774} \
c7697e1f
JM		 1775GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
1776 PPC_64B) \
d9bce9d9
JM		 1777{ \
1778 gen_##name(ctx, 1, 0); \
1779} \
c7697e1f
JM		 1780GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
1781 PPC_64B) \
d9bce9d9
JM		 1782{ \
1783 gen_##name(ctx, 1, 1); \
1784}
51789c41 1785
b068d6a7
JM		 1786static always_inline void gen_rldinm (DisasContext *ctx, uint32_t mb,
1787 uint32_t me, uint32_t sh)
51789c41 1788{
d03ef511
AJ		 1789 if (likely(sh != 0 && mb == 0 && me == (63 - sh))) {
1790 tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1791 } else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) {
1792 tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb);
1793 } else {
a7812ae4 1794 TCGv t0 = tcg_temp_new();
54843a58 1795 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
d03ef511 1796 if (likely(mb == 0 && me == 63)) {
54843a58 1797 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
d03ef511
AJ		 1798 } else {
1799 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
51789c41 1800 }
d03ef511 1801 tcg_temp_free(t0);
51789c41 1802 }
51789c41 1803 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1804 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
51789c41 1805}
d9bce9d9 1806/* rldicl - rldicl. */
b068d6a7 1807static always_inline void gen_rldicl (DisasContext *ctx, int mbn, int shn)
d9bce9d9 1808{
51789c41 1809 uint32_t sh, mb;
d9bce9d9 1810
9d53c753
JM		 1811 sh = SH(ctx->opcode) | (shn << 5);
1812 mb = MB(ctx->opcode) | (mbn << 5);
51789c41 1813 gen_rldinm(ctx, mb, 63, sh);
d9bce9d9 1814}
51789c41 1815GEN_PPC64_R4(rldicl, 0x1E, 0x00);
d9bce9d9 1816/* rldicr - rldicr. */
b068d6a7 1817static always_inline void gen_rldicr (DisasContext *ctx, int men, int shn)
d9bce9d9 1818{
51789c41 1819 uint32_t sh, me;
d9bce9d9 1820
9d53c753
JM		 1821 sh = SH(ctx->opcode) | (shn << 5);
1822 me = MB(ctx->opcode) | (men << 5);
51789c41 1823 gen_rldinm(ctx, 0, me, sh);
d9bce9d9 1824}
51789c41 1825GEN_PPC64_R4(rldicr, 0x1E, 0x02);
d9bce9d9 1826/* rldic - rldic. */
b068d6a7 1827static always_inline void gen_rldic (DisasContext *ctx, int mbn, int shn)
d9bce9d9 1828{
51789c41 1829 uint32_t sh, mb;
d9bce9d9 1830
9d53c753
JM		 1831 sh = SH(ctx->opcode) | (shn << 5);
1832 mb = MB(ctx->opcode) | (mbn << 5);
51789c41
JM		 1833 gen_rldinm(ctx, mb, 63 - sh, sh);
1834}
1835GEN_PPC64_R4(rldic, 0x1E, 0x04);
1836
b068d6a7
JM		 1837static always_inline void gen_rldnm (DisasContext *ctx, uint32_t mb,
1838 uint32_t me)
51789c41 1839{
54843a58 1840 TCGv t0;
d03ef511
AJ		 1841
1842 mb = MB(ctx->opcode);
1843 me = ME(ctx->opcode);
a7812ae4 1844 t0 = tcg_temp_new();
d03ef511 1845 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
54843a58 1846 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
51789c41 1847 if (unlikely(mb != 0 || me != 63)) {
54843a58
AJ		 1848 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1849 } else {
1850 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1851 }
1852 tcg_temp_free(t0);
51789c41 1853 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1854 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
d9bce9d9 1855}
51789c41 1856
d9bce9d9 1857/* rldcl - rldcl. */
b068d6a7 1858static always_inline void gen_rldcl (DisasContext *ctx, int mbn)
d9bce9d9 1859{
51789c41 1860 uint32_t mb;
d9bce9d9 1861
9d53c753 1862 mb = MB(ctx->opcode) | (mbn << 5);
51789c41 1863 gen_rldnm(ctx, mb, 63);
d9bce9d9 1864}
36081602 1865GEN_PPC64_R2(rldcl, 0x1E, 0x08);
d9bce9d9 1866/* rldcr - rldcr. */
b068d6a7 1867static always_inline void gen_rldcr (DisasContext *ctx, int men)
d9bce9d9 1868{
51789c41 1869 uint32_t me;
d9bce9d9 1870
9d53c753 1871 me = MB(ctx->opcode) | (men << 5);
51789c41 1872 gen_rldnm(ctx, 0, me);
d9bce9d9 1873}
36081602 1874GEN_PPC64_R2(rldcr, 0x1E, 0x09);
d9bce9d9 1875/* rldimi - rldimi. */
b068d6a7 1876static always_inline void gen_rldimi (DisasContext *ctx, int mbn, int shn)
d9bce9d9 1877{
271a916e 1878 uint32_t sh, mb, me;
d9bce9d9 1879
9d53c753
JM		 1880 sh = SH(ctx->opcode) | (shn << 5);
1881 mb = MB(ctx->opcode) | (mbn << 5);
271a916e 1882 me = 63 - sh;
d03ef511
AJ		 1883 if (unlikely(sh == 0 && mb == 0)) {
1884 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1885 } else {
1886 TCGv t0, t1;
1887 target_ulong mask;
1888
a7812ae4 1889 t0 = tcg_temp_new();
54843a58 1890 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
a7812ae4 1891 t1 = tcg_temp_new();
d03ef511
AJ		 1892 mask = MASK(mb, me);
1893 tcg_gen_andi_tl(t0, t0, mask);
1894 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1895 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1896 tcg_temp_free(t0);
1897 tcg_temp_free(t1);
51789c41 1898 }
51789c41 1899 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1900 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
d9bce9d9 1901}
36081602 1902GEN_PPC64_R4(rldimi, 0x1E, 0x06);
d9bce9d9
JM		 1903#endif
1904
79aceca5
FB		 1905/*** Integer shift ***/
1906/* slw & slw. */
26d67362
AJ		 1907GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER)
1908{
fea0c503 1909 TCGv t0;
26d67362
AJ		 1910 int l1, l2;
1911 l1 = gen_new_label();
1912 l2 = gen_new_label();
1913
a7812ae4 1914 t0 = tcg_temp_local_new();
0cfe58cd
AJ		 1915 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1916 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x20, l1);
26d67362
AJ		 1917 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1918 tcg_gen_br(l2);
1919 gen_set_label(l1);
fea0c503 1920 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
26d67362
AJ		 1921 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
1922 gen_set_label(l2);
fea0c503 1923 tcg_temp_free(t0);
26d67362
AJ		 1924 if (unlikely(Rc(ctx->opcode) != 0))
1925 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1926}
79aceca5 1927/* sraw & sraw. */
26d67362
AJ		 1928GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER)
1929{
a7812ae4
PB		 1930 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)],
1931 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
26d67362
AJ		 1932 if (unlikely(Rc(ctx->opcode) != 0))
1933 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1934}
79aceca5
FB		 1935/* srawi & srawi. */
1936GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER)
1937{
26d67362
AJ		 1938 int sh = SH(ctx->opcode);
1939 if (sh != 0) {
1940 int l1, l2;
fea0c503 1941 TCGv t0;
26d67362
AJ		 1942 l1 = gen_new_label();
1943 l2 = gen_new_label();
a7812ae4 1944 t0 = tcg_temp_local_new();
fea0c503
AJ		 1945 tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1946 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
1947 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
1948 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
269f3e95 1949 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
26d67362
AJ		 1950 tcg_gen_br(l2);
1951 gen_set_label(l1);
269f3e95 1952 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
26d67362 1953 gen_set_label(l2);
fea0c503
AJ		 1954 tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1955 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], t0, sh);
1956 tcg_temp_free(t0);
26d67362
AJ		 1957 } else {
1958 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
269f3e95 1959 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
d9bce9d9 1960 }
76a66253 1961 if (unlikely(Rc(ctx->opcode) != 0))
26d67362 1962 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5
FB		 1963}
1964/* srw & srw. */
26d67362
AJ		 1965GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER)
1966{
fea0c503 1967 TCGv t0, t1;
26d67362
AJ		 1968 int l1, l2;
1969 l1 = gen_new_label();
1970 l2 = gen_new_label();
d9bce9d9 1971
a7812ae4 1972 t0 = tcg_temp_local_new();
0cfe58cd
AJ		 1973 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1974 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x20, l1);
26d67362
AJ		 1975 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1976 tcg_gen_br(l2);
1977 gen_set_label(l1);
a7812ae4 1978 t1 = tcg_temp_new();
fea0c503
AJ		 1979 tcg_gen_ext32u_tl(t1, cpu_gpr[rS(ctx->opcode)]);
1980 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t1, t0);
1981 tcg_temp_free(t1);
26d67362 1982 gen_set_label(l2);
fea0c503 1983 tcg_temp_free(t0);
26d67362
AJ		 1984 if (unlikely(Rc(ctx->opcode) != 0))
1985 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1986}
d9bce9d9
JM		 1987#if defined(TARGET_PPC64)
1988/* sld & sld. */
26d67362
AJ		 1989GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B)
1990{
fea0c503 1991 TCGv t0;
26d67362
AJ		 1992 int l1, l2;
1993 l1 = gen_new_label();
1994 l2 = gen_new_label();
1995
a7812ae4 1996 t0 = tcg_temp_local_new();
0cfe58cd
AJ		 1997 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x7f);
1998 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x40, l1);
26d67362
AJ		 1999 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
2000 tcg_gen_br(l2);
2001 gen_set_label(l1);
fea0c503 2002 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
26d67362 2003 gen_set_label(l2);
fea0c503 2004 tcg_temp_free(t0);
26d67362
AJ		 2005 if (unlikely(Rc(ctx->opcode) != 0))
2006 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2007}
d9bce9d9 2008/* srad & srad. */
26d67362
AJ		 2009GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B)
2010{
a7812ae4
PB		 2011 gen_helper_srad(cpu_gpr[rA(ctx->opcode)],
2012 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
26d67362
AJ		 2013 if (unlikely(Rc(ctx->opcode) != 0))
2014 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2015}
d9bce9d9 2016/* sradi & sradi. */
b068d6a7 2017static always_inline void gen_sradi (DisasContext *ctx, int n)
d9bce9d9 2018{
26d67362 2019 int sh = SH(ctx->opcode) + (n << 5);
d9bce9d9 2020 if (sh != 0) {
26d67362 2021 int l1, l2;
fea0c503 2022 TCGv t0;
26d67362
AJ		 2023 l1 = gen_new_label();
2024 l2 = gen_new_label();
a7812ae4 2025 t0 = tcg_temp_local_new();
26d67362 2026 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
fea0c503
AJ		 2027 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
2028 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
269f3e95 2029 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
26d67362
AJ		 2030 tcg_gen_br(l2);
2031 gen_set_label(l1);
269f3e95 2032 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
26d67362 2033 gen_set_label(l2);
a9730017 2034 tcg_temp_free(t0);
26d67362
AJ		 2035 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
2036 } else {
2037 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
269f3e95 2038 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
d9bce9d9 2039 }
d9bce9d9 2040 if (unlikely(Rc(ctx->opcode) != 0))
26d67362 2041 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
d9bce9d9 2042}
c7697e1f 2043GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B)
d9bce9d9
JM		 2044{
2045 gen_sradi(ctx, 0);
2046}
c7697e1f 2047GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B)
d9bce9d9
JM		 2048{
2049 gen_sradi(ctx, 1);
2050}
2051/* srd & srd. */
26d67362
AJ		 2052GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B)
2053{
fea0c503 2054 TCGv t0;
26d67362
AJ		 2055 int l1, l2;
2056 l1 = gen_new_label();
2057 l2 = gen_new_label();
2058
a7812ae4 2059 t0 = tcg_temp_local_new();
0cfe58cd
AJ		 2060 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x7f);
2061 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x40, l1);
26d67362
AJ		 2062 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
2063 tcg_gen_br(l2);
2064 gen_set_label(l1);
fea0c503 2065 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
26d67362 2066 gen_set_label(l2);
fea0c503 2067 tcg_temp_free(t0);
26d67362
AJ		 2068 if (unlikely(Rc(ctx->opcode) != 0))
2069 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2070}
d9bce9d9 2071#endif
79aceca5
FB		 2072
2073/*** Floating-Point arithmetic ***/
7c58044c 2074#define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
a750fc0b 2075GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type) \
9a64fbe4 2076{ \
76a66253 2077 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 2078 gen_exception(ctx, POWERPC_EXCP_FPU); \
3cc62370
FB		 2079 return; \
2080 } \
eb44b959
AJ		 2081 /* NIP cannot be restored if the memory exception comes from an helper */ \
2082 gen_update_nip(ctx, ctx->nip - 4); \
7c58044c 2083 gen_reset_fpstatus(); \
af12906f
AJ		 2084 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
2085 cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
4ecc3190 2086 if (isfloat) { \
af12906f 2087 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
4ecc3190 2088 } \
af12906f
AJ		 2089 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf, \
2090 Rc(ctx->opcode) != 0); \
9a64fbe4
FB		 2091}
2092
7c58044c
JM		 2093#define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
2094_GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
2095_GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
9a64fbe4 2096
7c58044c
JM		 2097#define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2098GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \
9a64fbe4 2099{ \
76a66253 2100 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 2101 gen_exception(ctx, POWERPC_EXCP_FPU); \
3cc62370
FB		 2102 return; \
2103 } \
eb44b959
AJ		 2104 /* NIP cannot be restored if the memory exception comes from an helper */ \
2105 gen_update_nip(ctx, ctx->nip - 4); \
7c58044c 2106 gen_reset_fpstatus(); \
af12906f
AJ		 2107 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
2108 cpu_fpr[rB(ctx->opcode)]); \
4ecc3190 2109 if (isfloat) { \
af12906f 2110 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
4ecc3190 2111 } \
af12906f
AJ		 2112 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2113 set_fprf, Rc(ctx->opcode) != 0); \
9a64fbe4 2114}
7c58044c
JM		 2115#define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
2116_GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2117_GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
9a64fbe4 2118
7c58044c
JM		 2119#define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2120GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \
9a64fbe4 2121{ \
76a66253 2122 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 2123 gen_exception(ctx, POWERPC_EXCP_FPU); \
3cc62370
FB		 2124 return; \
2125 } \
eb44b959
AJ		 2126 /* NIP cannot be restored if the memory exception comes from an helper */ \
2127 gen_update_nip(ctx, ctx->nip - 4); \
7c58044c 2128 gen_reset_fpstatus(); \
af12906f
AJ		 2129 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
2130 cpu_fpr[rC(ctx->opcode)]); \
4ecc3190 2131 if (isfloat) { \
af12906f 2132 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
4ecc3190 2133 } \
af12906f
AJ		 2134 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2135 set_fprf, Rc(ctx->opcode) != 0); \
9a64fbe4 2136}
7c58044c
JM		 2137#define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
2138_GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2139_GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
9a64fbe4 2140
7c58044c 2141#define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
a750fc0b 2142GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type) \
9a64fbe4 2143{ \
76a66253 2144 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 2145 gen_exception(ctx, POWERPC_EXCP_FPU); \
3cc62370
FB		 2146 return; \
2147 } \
eb44b959
AJ		 2148 /* NIP cannot be restored if the memory exception comes from an helper */ \
2149 gen_update_nip(ctx, ctx->nip - 4); \
7c58044c 2150 gen_reset_fpstatus(); \
af12906f
AJ		 2151 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2152 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2153 set_fprf, Rc(ctx->opcode) != 0); \
79aceca5
FB		 2154}
2155
7c58044c 2156#define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
a750fc0b 2157GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type) \
9a64fbe4 2158{ \
76a66253 2159 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 2160 gen_exception(ctx, POWERPC_EXCP_FPU); \
3cc62370
FB		 2161 return; \
2162 } \
eb44b959
AJ		 2163 /* NIP cannot be restored if the memory exception comes from an helper */ \
2164 gen_update_nip(ctx, ctx->nip - 4); \
7c58044c 2165 gen_reset_fpstatus(); \
af12906f
AJ		 2166 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2167 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2168 set_fprf, Rc(ctx->opcode) != 0); \
79aceca5
FB		 2169}
2170
9a64fbe4 2171/* fadd - fadds */
7c58044c 2172GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
4ecc3190 2173/* fdiv - fdivs */
7c58044c 2174GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
4ecc3190 2175/* fmul - fmuls */
7c58044c 2176GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
79aceca5 2177
d7e4b87e 2178/* fre */
7c58044c 2179GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
d7e4b87e 2180
a750fc0b 2181/* fres */
7c58044c 2182GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
79aceca5 2183
a750fc0b 2184/* frsqrte */
7c58044c
JM		 2185GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
2186
2187/* frsqrtes */
af12906f 2188GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES)
7c58044c 2189{
af12906f 2190 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2191 gen_exception(ctx, POWERPC_EXCP_FPU);
af12906f
AJ		 2192 return;
2193 }
eb44b959
AJ		 2194 /* NIP cannot be restored if the memory exception comes from an helper */
2195 gen_update_nip(ctx, ctx->nip - 4);
af12906f
AJ		 2196 gen_reset_fpstatus();
2197 gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2198 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]);
2199 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
7c58044c 2200}
79aceca5 2201
a750fc0b 2202/* fsel */
7c58044c 2203_GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
4ecc3190 2204/* fsub - fsubs */
7c58044c 2205GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
79aceca5
FB		 2206/* Optional: */
2207/* fsqrt */
a750fc0b 2208GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
c7d344af 2209{
76a66253 2210 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2211 gen_exception(ctx, POWERPC_EXCP_FPU);
c7d344af
FB		 2212 return;
2213 }
eb44b959
AJ		 2214 /* NIP cannot be restored if the memory exception comes from an helper */
2215 gen_update_nip(ctx, ctx->nip - 4);
7c58044c 2216 gen_reset_fpstatus();
af12906f
AJ		 2217 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2218 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
c7d344af 2219}
79aceca5 2220
a750fc0b 2221GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
79aceca5 2222{
76a66253 2223 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2224 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2225 return;
2226 }
eb44b959
AJ		 2227 /* NIP cannot be restored if the memory exception comes from an helper */
2228 gen_update_nip(ctx, ctx->nip - 4);
7c58044c 2229 gen_reset_fpstatus();
af12906f
AJ		 2230 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2231 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]);
2232 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
79aceca5
FB		 2233}
2234
2235/*** Floating-Point multiply-and-add ***/
4ecc3190 2236/* fmadd - fmadds */
7c58044c 2237GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
4ecc3190 2238/* fmsub - fmsubs */
7c58044c 2239GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
4ecc3190 2240/* fnmadd - fnmadds */
7c58044c 2241GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
4ecc3190 2242/* fnmsub - fnmsubs */
7c58044c 2243GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
79aceca5
FB		 2244
2245/*** Floating-Point round & convert ***/
2246/* fctiw */
7c58044c 2247GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
79aceca5 2248/* fctiwz */
7c58044c 2249GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
79aceca5 2250/* frsp */
7c58044c 2251GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
426613db
JM		 2252#if defined(TARGET_PPC64)
2253/* fcfid */
7c58044c 2254GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B);
426613db 2255/* fctid */
7c58044c 2256GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B);
426613db 2257/* fctidz */
7c58044c 2258GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B);
426613db 2259#endif
79aceca5 2260
d7e4b87e 2261/* frin */
7c58044c 2262GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
d7e4b87e 2263/* friz */
7c58044c 2264GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
d7e4b87e 2265/* frip */
7c58044c 2266GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
d7e4b87e 2267/* frim */
7c58044c 2268GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
d7e4b87e 2269
79aceca5
FB		 2270/*** Floating-Point compare ***/
2271/* fcmpo */
76a66253 2272GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT)
79aceca5 2273{
330c483b 2274 TCGv_i32 crf;
76a66253 2275 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2276 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2277 return;
2278 }
eb44b959
AJ		 2279 /* NIP cannot be restored if the memory exception comes from an helper */
2280 gen_update_nip(ctx, ctx->nip - 4);
7c58044c 2281 gen_reset_fpstatus();
9a819377
AJ		 2282 crf = tcg_const_i32(crfD(ctx->opcode));
2283 gen_helper_fcmpo(cpu_fpr[rA(ctx->opcode)], cpu_fpr[rB(ctx->opcode)], crf);
330c483b 2284 tcg_temp_free_i32(crf);
af12906f 2285 gen_helper_float_check_status();
79aceca5
FB		 2286}
2287
2288/* fcmpu */
76a66253 2289GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT)
79aceca5 2290{
330c483b 2291 TCGv_i32 crf;
76a66253 2292 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2293 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2294 return;
2295 }
eb44b959
AJ		 2296 /* NIP cannot be restored if the memory exception comes from an helper */
2297 gen_update_nip(ctx, ctx->nip - 4);
7c58044c 2298 gen_reset_fpstatus();
9a819377
AJ		 2299 crf = tcg_const_i32(crfD(ctx->opcode));
2300 gen_helper_fcmpu(cpu_fpr[rA(ctx->opcode)], cpu_fpr[rB(ctx->opcode)], crf);
330c483b 2301 tcg_temp_free_i32(crf);
af12906f 2302 gen_helper_float_check_status();
79aceca5
FB		 2303}
2304
9a64fbe4
FB		 2305/*** Floating-point move ***/
2306/* fabs */
7c58044c
JM		 2307/* XXX: beware that fabs never checks for NaNs nor update FPSCR */
2308GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT);
9a64fbe4
FB		 2309
2310/* fmr - fmr. */
7c58044c 2311/* XXX: beware that fmr never checks for NaNs nor update FPSCR */
9a64fbe4
FB		 2312GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT)
2313{
76a66253 2314 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2315 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2316 return;
2317 }
af12906f
AJ		 2318 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2319 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
9a64fbe4
FB		 2320}
2321
2322/* fnabs */
7c58044c
JM		 2323/* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
2324GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT);
9a64fbe4 2325/* fneg */
7c58044c
JM		 2326/* XXX: beware that fneg never checks for NaNs nor update FPSCR */
2327GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT);
9a64fbe4 2328
79aceca5
FB		 2329/*** Floating-Point status & ctrl register ***/
2330/* mcrfs */
2331GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT)
2332{
7c58044c
JM		 2333 int bfa;
2334
76a66253 2335 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2336 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2337 return;
2338 }
7c58044c 2339 bfa = 4 * (7 - crfS(ctx->opcode));
e1571908
AJ		 2340 tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_fpscr, bfa);
2341 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
af12906f 2342 tcg_gen_andi_i32(cpu_fpscr, cpu_fpscr, ~(0xF << bfa));
79aceca5
FB		 2343}
2344
2345/* mffs */
2346GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT)
2347{
76a66253 2348 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2349 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2350 return;
2351 }
7c58044c 2352 gen_reset_fpstatus();
af12906f
AJ		 2353 tcg_gen_extu_i32_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr);
2354 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
79aceca5
FB		 2355}
2356
2357/* mtfsb0 */
2358GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT)
2359{
fb0eaffc 2360 uint8_t crb;
3b46e624 2361
76a66253 2362 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2363 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2364 return;
2365 }
6e35d524 2366 crb = 31 - crbD(ctx->opcode);
7c58044c 2367 gen_reset_fpstatus();
6e35d524 2368 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) {
eb44b959
AJ		 2369 TCGv_i32 t0;
2370 /* NIP cannot be restored if the memory exception comes from an helper */
2371 gen_update_nip(ctx, ctx->nip - 4);
2372 t0 = tcg_const_i32(crb);
6e35d524
AJ		 2373 gen_helper_fpscr_clrbit(t0);
2374 tcg_temp_free_i32(t0);
2375 }
7c58044c 2376 if (unlikely(Rc(ctx->opcode) != 0)) {
e1571908 2377 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
7c58044c 2378 }
79aceca5
FB		 2379}
2380
2381/* mtfsb1 */
2382GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT)
2383{
fb0eaffc 2384 uint8_t crb;
3b46e624 2385
76a66253 2386 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2387 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2388 return;
2389 }
6e35d524 2390 crb = 31 - crbD(ctx->opcode);
7c58044c
JM		 2391 gen_reset_fpstatus();
2392 /* XXX: we pretend we can only do IEEE floating-point computations */
af12906f 2393 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
eb44b959
AJ		 2394 TCGv_i32 t0;
2395 /* NIP cannot be restored if the memory exception comes from an helper */
2396 gen_update_nip(ctx, ctx->nip - 4);
2397 t0 = tcg_const_i32(crb);
af12906f 2398 gen_helper_fpscr_setbit(t0);
0f2f39c2 2399 tcg_temp_free_i32(t0);
af12906f 2400 }
7c58044c 2401 if (unlikely(Rc(ctx->opcode) != 0)) {
e1571908 2402 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
7c58044c
JM		 2403 }
2404 /* We can raise a differed exception */
af12906f 2405 gen_helper_float_check_status();
79aceca5
FB		 2406}
2407
2408/* mtfsf */
2409GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x02010000, PPC_FLOAT)
2410{
0f2f39c2 2411 TCGv_i32 t0;
af12906f 2412
76a66253 2413 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2414 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2415 return;
2416 }
eb44b959
AJ		 2417 /* NIP cannot be restored if the memory exception comes from an helper */
2418 gen_update_nip(ctx, ctx->nip - 4);
7c58044c 2419 gen_reset_fpstatus();
af12906f
AJ		 2420 t0 = tcg_const_i32(FM(ctx->opcode));
2421 gen_helper_store_fpscr(cpu_fpr[rB(ctx->opcode)], t0);
0f2f39c2 2422 tcg_temp_free_i32(t0);
7c58044c 2423 if (unlikely(Rc(ctx->opcode) != 0)) {
e1571908 2424 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
7c58044c
JM		 2425 }
2426 /* We can raise a differed exception */
af12906f 2427 gen_helper_float_check_status();
79aceca5
FB		 2428}
2429
2430/* mtfsfi */
2431GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT)
2432{
7c58044c 2433 int bf, sh;
0f2f39c2
AJ		 2434 TCGv_i64 t0;
2435 TCGv_i32 t1;
7c58044c 2436
76a66253 2437 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2438 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2439 return;
2440 }
7c58044c
JM		 2441 bf = crbD(ctx->opcode) >> 2;
2442 sh = 7 - bf;
eb44b959
AJ		 2443 /* NIP cannot be restored if the memory exception comes from an helper */
2444 gen_update_nip(ctx, ctx->nip - 4);
7c58044c 2445 gen_reset_fpstatus();
0f2f39c2 2446 t0 = tcg_const_i64(FPIMM(ctx->opcode) << (4 * sh));
af12906f
AJ		 2447 t1 = tcg_const_i32(1 << sh);
2448 gen_helper_store_fpscr(t0, t1);
0f2f39c2
AJ		 2449 tcg_temp_free_i64(t0);
2450 tcg_temp_free_i32(t1);
7c58044c 2451 if (unlikely(Rc(ctx->opcode) != 0)) {
e1571908 2452 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
7c58044c
JM		 2453 }
2454 /* We can raise a differed exception */
af12906f 2455 gen_helper_float_check_status();
79aceca5
FB		 2456}
2457
76a66253
JM		 2458/*** Addressing modes ***/
2459/* Register indirect with immediate index : EA = (rA|0) + SIMM */
76db3ba4 2460static always_inline void gen_addr_imm_index (DisasContext *ctx, TCGv EA, target_long maskl)
76a66253
JM		 2461{
2462 target_long simm = SIMM(ctx->opcode);
2463
be147d08 2464 simm &= ~maskl;
76db3ba4
AJ		 2465 if (rA(ctx->opcode) == 0) {
2466#if defined(TARGET_PPC64)
2467 if (!ctx->sf_mode) {
2468 tcg_gen_movi_tl(EA, (uint32_t)simm);
2469 } else
2470#endif
e2be8d8d 2471 tcg_gen_movi_tl(EA, simm);
76db3ba4 2472 } else if (likely(simm != 0)) {
e2be8d8d 2473 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
76db3ba4
AJ		 2474#if defined(TARGET_PPC64)
2475 if (!ctx->sf_mode) {
2476 tcg_gen_ext32u_tl(EA, EA);
2477 }
2478#endif
2479 } else {
2480#if defined(TARGET_PPC64)
2481 if (!ctx->sf_mode) {
2482 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2483 } else
2484#endif
e2be8d8d 2485 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
76db3ba4 2486 }
76a66253
JM		 2487}
2488
76db3ba4 2489static always_inline void gen_addr_reg_index (DisasContext *ctx, TCGv EA)
76a66253 2490{
76db3ba4
AJ		 2491 if (rA(ctx->opcode) == 0) {
2492#if defined(TARGET_PPC64)
2493 if (!ctx->sf_mode) {
2494 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2495 } else
2496#endif
e2be8d8d 2497 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
76db3ba4 2498 } else {
e2be8d8d 2499 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
76db3ba4
AJ		 2500#if defined(TARGET_PPC64)
2501 if (!ctx->sf_mode) {
2502 tcg_gen_ext32u_tl(EA, EA);
2503 }
2504#endif
2505 }
76a66253
JM		 2506}
2507
76db3ba4 2508static always_inline void gen_addr_register (DisasContext *ctx, TCGv EA)
76a66253 2509{
76db3ba4 2510 if (rA(ctx->opcode) == 0) {
e2be8d8d 2511 tcg_gen_movi_tl(EA, 0);
76db3ba4
AJ		 2512 } else {
2513#if defined(TARGET_PPC64)
2514 if (!ctx->sf_mode) {
2515 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2516 } else
2517#endif
2518 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2519 }
2520}
2521
2522static always_inline void gen_addr_add (DisasContext *ctx, TCGv ret, TCGv arg1, target_long val)
2523{
2524 tcg_gen_addi_tl(ret, arg1, val);
2525#if defined(TARGET_PPC64)
2526 if (!ctx->sf_mode) {
2527 tcg_gen_ext32u_tl(ret, ret);
2528 }
2529#endif
76a66253
JM		 2530}
2531
cf360a32
AJ		 2532static always_inline void gen_check_align (DisasContext *ctx, TCGv EA, int mask)
2533{
2534 int l1 = gen_new_label();
2535 TCGv t0 = tcg_temp_new();
2536 TCGv_i32 t1, t2;
2537 /* NIP cannot be restored if the memory exception comes from an helper */
2538 gen_update_nip(ctx, ctx->nip - 4);
2539 tcg_gen_andi_tl(t0, EA, mask);
2540 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2541 t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
2542 t2 = tcg_const_i32(0);
2543 gen_helper_raise_exception_err(t1, t2);
2544 tcg_temp_free_i32(t1);
2545 tcg_temp_free_i32(t2);
2546 gen_set_label(l1);
2547 tcg_temp_free(t0);
2548}
2549
7863667f 2550/*** Integer load ***/
76db3ba4
AJ		 2551static always_inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2552{
2553 tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx);
2554}
2555
2556static always_inline void gen_qemu_ld8s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2557{
2558 tcg_gen_qemu_ld8s(arg1, arg2, ctx->mem_idx);
2559}
2560
2561static always_inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2562{
2563 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2564 if (unlikely(ctx->le_mode)) {
b61f2753 2565#if defined(TARGET_PPC64)
76db3ba4
AJ		 2566 TCGv_i32 t0 = tcg_temp_new_i32();
2567 tcg_gen_trunc_tl_i32(t0, arg1);
ea363694 2568 tcg_gen_bswap16_i32(t0, t0);
76db3ba4 2569 tcg_gen_extu_i32_tl(arg1, t0);
a7812ae4 2570 tcg_temp_free_i32(t0);
76db3ba4
AJ		 2571#else
2572 tcg_gen_bswap16_i32(arg1, arg1);
2573#endif
2574 }
b61f2753
AJ		 2575}
2576
76db3ba4 2577static always_inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2578{
76db3ba4
AJ		 2579 if (unlikely(ctx->le_mode)) {
2580#if defined(TARGET_PPC64)
a7812ae4 2581 TCGv_i32 t0;
76db3ba4 2582 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
a7812ae4 2583 t0 = tcg_temp_new_i32();
76db3ba4 2584 tcg_gen_trunc_tl_i32(t0, arg1);
ea363694 2585 tcg_gen_bswap16_i32(t0, t0);
76db3ba4
AJ		 2586 tcg_gen_extu_i32_tl(arg1, t0);
2587 tcg_gen_ext16s_tl(arg1, arg1);
a7812ae4 2588 tcg_temp_free_i32(t0);
76db3ba4
AJ		 2589#else
2590 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2591 tcg_gen_bswap16_i32(arg1, arg1);
2592 tcg_gen_ext16s_i32(arg1, arg1);
2593#endif
2594 } else {
2595 tcg_gen_qemu_ld16s(arg1, arg2, ctx->mem_idx);
2596 }
b61f2753
AJ		 2597}
2598
76db3ba4 2599static always_inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2600{
76db3ba4
AJ		 2601 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2602 if (unlikely(ctx->le_mode)) {
2603#if defined(TARGET_PPC64)
2604 TCGv_i32 t0 = tcg_temp_new_i32();
2605 tcg_gen_trunc_tl_i32(t0, arg1);
ea363694 2606 tcg_gen_bswap_i32(t0, t0);
76db3ba4 2607 tcg_gen_extu_i32_tl(arg1, t0);
a7812ae4 2608 tcg_temp_free_i32(t0);
76db3ba4
AJ		 2609#else
2610 tcg_gen_bswap_i32(arg1, arg1);
2611#endif
2612 }
b61f2753
AJ		 2613}
2614
76db3ba4
AJ		 2615#if defined(TARGET_PPC64)
2616static always_inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2617{
76db3ba4 2618 if (unlikely(ctx->mem_idx)) {
a7812ae4 2619 TCGv_i32 t0;
76db3ba4 2620 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
a7812ae4 2621 t0 = tcg_temp_new_i32();
76db3ba4 2622 tcg_gen_trunc_tl_i32(t0, arg1);
ea363694 2623 tcg_gen_bswap_i32(t0, t0);
76db3ba4 2624 tcg_gen_ext_i32_tl(arg1, t0);
a7812ae4 2625 tcg_temp_free_i32(t0);
b61f2753 2626 } else
76db3ba4 2627 tcg_gen_qemu_ld32s(arg1, arg2, ctx->mem_idx);
b61f2753 2628}
76db3ba4 2629#endif
b61f2753 2630
76db3ba4 2631static always_inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
b61f2753 2632{
76db3ba4
AJ		 2633 tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx);
2634 if (unlikely(ctx->le_mode)) {
2635 tcg_gen_bswap_i64(arg1, arg1);
2636 }
b61f2753
AJ		 2637}
2638
76db3ba4 2639static always_inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2640{
76db3ba4 2641 tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx);
b61f2753
AJ		 2642}
2643
76db3ba4 2644static always_inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2645{
76db3ba4
AJ		 2646 if (unlikely(ctx->le_mode)) {
2647#if defined(TARGET_PPC64)
a7812ae4 2648 TCGv_i32 t0;
76db3ba4 2649 TCGv t1;
a7812ae4 2650 t0 = tcg_temp_new_i32();
76db3ba4 2651 tcg_gen_trunc_tl_i32(t0, arg1);
ea363694
AJ		 2652 tcg_gen_ext16u_i32(t0, t0);
2653 tcg_gen_bswap16_i32(t0, t0);
76db3ba4 2654 t1 = tcg_temp_new();
ea363694 2655 tcg_gen_extu_i32_tl(t1, t0);
a7812ae4 2656 tcg_temp_free_i32(t0);
76db3ba4
AJ		 2657 tcg_gen_qemu_st16(t1, arg2, ctx->mem_idx);
2658 tcg_temp_free(t1);
2659#else
2660 TCGv t0 = tcg_temp_new();
2661 tcg_gen_ext16u_tl(t0, arg1);
2662 tcg_gen_bswap16_i32(t0, t0);
2663 tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
2664 tcg_temp_free(t0);
2665#endif
2666 } else {
2667 tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
2668 }
b61f2753
AJ		 2669}
2670
76db3ba4 2671static always_inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2672{
76db3ba4
AJ		 2673 if (unlikely(ctx->le_mode)) {
2674#if defined(TARGET_PPC64)
a7812ae4 2675 TCGv_i32 t0;
76db3ba4 2676 TCGv t1;
a7812ae4 2677 t0 = tcg_temp_new_i32();
76db3ba4 2678 tcg_gen_trunc_tl_i32(t0, arg1);
ea363694 2679 tcg_gen_bswap_i32(t0, t0);
76db3ba4 2680 t1 = tcg_temp_new();
ea363694 2681 tcg_gen_extu_i32_tl(t1, t0);
a7812ae4 2682 tcg_temp_free_i32(t0);
76db3ba4
AJ		 2683 tcg_gen_qemu_st32(t1, arg2, ctx->mem_idx);
2684 tcg_temp_free(t1);
2685#else
2686 TCGv t0 = tcg_temp_new_i32();
2687 tcg_gen_bswap_i32(t0, arg1);
2688 tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
2689 tcg_temp_free(t0);
2690#endif
2691 } else {
2692 tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
2693 }
b61f2753
AJ		 2694}
2695
76db3ba4 2696static always_inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
b61f2753 2697{
76db3ba4 2698 if (unlikely(ctx->le_mode)) {
a7812ae4 2699 TCGv_i64 t0 = tcg_temp_new_i64();
76db3ba4
AJ		 2700 tcg_gen_bswap_i64(t0, arg1);
2701 tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx);
a7812ae4 2702 tcg_temp_free_i64(t0);
b61f2753 2703 } else
76db3ba4 2704 tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx);
b61f2753
AJ		 2705}
2706
0c8aacd4
AJ		 2707#define GEN_LD(name, ldop, opc, type) \
2708GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2709{ \
76db3ba4
AJ		 2710 TCGv EA; \
2711 gen_set_access_type(ctx, ACCESS_INT); \
2712 EA = tcg_temp_new(); \
2713 gen_addr_imm_index(ctx, EA, 0); \
2714 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
b61f2753 2715 tcg_temp_free(EA); \
79aceca5
FB		 2716}
2717
0c8aacd4
AJ		 2718#define GEN_LDU(name, ldop, opc, type) \
2719GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2720{ \
b61f2753 2721 TCGv EA; \
76a66253
JM		 2722 if (unlikely(rA(ctx->opcode) == 0 || \
2723 rA(ctx->opcode) == rD(ctx->opcode))) { \
e06fcd75 2724 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 2725 return; \
9a64fbe4 2726 } \
76db3ba4 2727 gen_set_access_type(ctx, ACCESS_INT); \
0c8aacd4 2728 EA = tcg_temp_new(); \
9d53c753 2729 if (type == PPC_64B) \
76db3ba4 2730 gen_addr_imm_index(ctx, EA, 0x03); \
9d53c753 2731 else \
76db3ba4
AJ		 2732 gen_addr_imm_index(ctx, EA, 0); \
2733 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
b61f2753
AJ		 2734 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2735 tcg_temp_free(EA); \
79aceca5
FB		 2736}
2737
0c8aacd4
AJ		 2738#define GEN_LDUX(name, ldop, opc2, opc3, type) \
2739GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2740{ \
b61f2753 2741 TCGv EA; \
76a66253
JM		 2742 if (unlikely(rA(ctx->opcode) == 0 || \
2743 rA(ctx->opcode) == rD(ctx->opcode))) { \
e06fcd75 2744 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 2745 return; \
9a64fbe4 2746 } \
76db3ba4 2747 gen_set_access_type(ctx, ACCESS_INT); \
0c8aacd4 2748 EA = tcg_temp_new(); \
76db3ba4
AJ		 2749 gen_addr_reg_index(ctx, EA); \
2750 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
b61f2753
AJ		 2751 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2752 tcg_temp_free(EA); \
79aceca5
FB		 2753}
2754
0c8aacd4
AJ		 2755#define GEN_LDX(name, ldop, opc2, opc3, type) \
2756GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2757{ \
76db3ba4
AJ		 2758 TCGv EA; \
2759 gen_set_access_type(ctx, ACCESS_INT); \
2760 EA = tcg_temp_new(); \
2761 gen_addr_reg_index(ctx, EA); \
2762 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
b61f2753 2763 tcg_temp_free(EA); \
79aceca5
FB		 2764}
2765
0c8aacd4
AJ		 2766#define GEN_LDS(name, ldop, op, type) \
2767GEN_LD(name, ldop, op | 0x20, type); \
2768GEN_LDU(name, ldop, op | 0x21, type); \
2769GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2770GEN_LDX(name, ldop, 0x17, op | 0x00, type)
79aceca5
FB		 2771
2772/* lbz lbzu lbzux lbzx */
0c8aacd4 2773GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
79aceca5 2774/* lha lhau lhaux lhax */
0c8aacd4 2775GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
79aceca5 2776/* lhz lhzu lhzux lhzx */
0c8aacd4 2777GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
79aceca5 2778/* lwz lwzu lwzux lwzx */
0c8aacd4 2779GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
d9bce9d9 2780#if defined(TARGET_PPC64)
d9bce9d9 2781/* lwaux */
0c8aacd4 2782GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
d9bce9d9 2783/* lwax */
0c8aacd4 2784GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
d9bce9d9 2785/* ldux */
0c8aacd4 2786GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B);
d9bce9d9 2787/* ldx */
0c8aacd4 2788GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B);
d9bce9d9
JM		 2789GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B)
2790{
b61f2753 2791 TCGv EA;
d9bce9d9
JM		 2792 if (Rc(ctx->opcode)) {
2793 if (unlikely(rA(ctx->opcode) == 0 ||
2794 rA(ctx->opcode) == rD(ctx->opcode))) {
e06fcd75 2795 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
d9bce9d9
JM		 2796 return;
2797 }
2798 }
76db3ba4 2799 gen_set_access_type(ctx, ACCESS_INT);
a7812ae4 2800 EA = tcg_temp_new();
76db3ba4 2801 gen_addr_imm_index(ctx, EA, 0x03);
d9bce9d9
JM		 2802 if (ctx->opcode & 0x02) {
2803 /* lwa (lwau is undefined) */
76db3ba4 2804 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
d9bce9d9
JM		 2805 } else {
2806 /* ld - ldu */
76db3ba4 2807 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
d9bce9d9 2808 }
d9bce9d9 2809 if (Rc(ctx->opcode))
b61f2753
AJ		 2810 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2811 tcg_temp_free(EA);
d9bce9d9 2812}
be147d08
JM		 2813/* lq */
2814GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX)
2815{
2816#if defined(CONFIG_USER_ONLY)
e06fcd75 2817 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
be147d08
JM		 2818#else
2819 int ra, rd;
b61f2753 2820 TCGv EA;
be147d08
JM		 2821
2822 /* Restore CPU state */
76db3ba4 2823 if (unlikely(ctx->mem_idx == 0)) {
e06fcd75 2824 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
be147d08
JM		 2825 return;
2826 }
2827 ra = rA(ctx->opcode);
2828 rd = rD(ctx->opcode);
2829 if (unlikely((rd & 1) || rd == ra)) {
e06fcd75 2830 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
be147d08
JM		 2831 return;
2832 }
76db3ba4 2833 if (unlikely(ctx->le_mode)) {
be147d08 2834 /* Little-endian mode is not handled */
e06fcd75 2835 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
be147d08
JM		 2836 return;
2837 }
76db3ba4 2838 gen_set_access_type(ctx, ACCESS_INT);
a7812ae4 2839 EA = tcg_temp_new();
76db3ba4
AJ		 2840 gen_addr_imm_index(ctx, EA, 0x0F);
2841 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2842 gen_addr_add(ctx, EA, EA, 8);
2843 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
b61f2753 2844 tcg_temp_free(EA);
be147d08
JM		 2845#endif
2846}
d9bce9d9 2847#endif
79aceca5
FB		 2848
2849/*** Integer store ***/
0c8aacd4
AJ		 2850#define GEN_ST(name, stop, opc, type) \
2851GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2852{ \
76db3ba4
AJ		 2853 TCGv EA; \
2854 gen_set_access_type(ctx, ACCESS_INT); \
2855 EA = tcg_temp_new(); \
2856 gen_addr_imm_index(ctx, EA, 0); \
2857 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
b61f2753 2858 tcg_temp_free(EA); \
79aceca5
FB		 2859}
2860
0c8aacd4
AJ		 2861#define GEN_STU(name, stop, opc, type) \
2862GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2863{ \
b61f2753 2864 TCGv EA; \
76a66253 2865 if (unlikely(rA(ctx->opcode) == 0)) { \
e06fcd75 2866 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 2867 return; \
9a64fbe4 2868 } \
76db3ba4 2869 gen_set_access_type(ctx, ACCESS_INT); \
0c8aacd4 2870 EA = tcg_temp_new(); \
9d53c753 2871 if (type == PPC_64B) \
76db3ba4 2872 gen_addr_imm_index(ctx, EA, 0x03); \
9d53c753 2873 else \
76db3ba4
AJ		 2874 gen_addr_imm_index(ctx, EA, 0); \
2875 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
b61f2753
AJ		 2876 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2877 tcg_temp_free(EA); \
79aceca5
FB		 2878}
2879
0c8aacd4
AJ		 2880#define GEN_STUX(name, stop, opc2, opc3, type) \
2881GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2882{ \
b61f2753 2883 TCGv EA; \
76a66253 2884 if (unlikely(rA(ctx->opcode) == 0)) { \
e06fcd75 2885 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 2886 return; \
9a64fbe4 2887 } \
76db3ba4 2888 gen_set_access_type(ctx, ACCESS_INT); \
0c8aacd4 2889 EA = tcg_temp_new(); \
76db3ba4
AJ		 2890 gen_addr_reg_index(ctx, EA); \
2891 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
b61f2753
AJ		 2892 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2893 tcg_temp_free(EA); \
79aceca5
FB		 2894}
2895
0c8aacd4
AJ		 2896#define GEN_STX(name, stop, opc2, opc3, type) \
2897GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2898{ \
76db3ba4
AJ		 2899 TCGv EA; \
2900 gen_set_access_type(ctx, ACCESS_INT); \
2901 EA = tcg_temp_new(); \
2902 gen_addr_reg_index(ctx, EA); \
2903 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
b61f2753 2904 tcg_temp_free(EA); \
79aceca5
FB		 2905}
2906
0c8aacd4
AJ		 2907#define GEN_STS(name, stop, op, type) \
2908GEN_ST(name, stop, op | 0x20, type); \
2909GEN_STU(name, stop, op | 0x21, type); \
2910GEN_STUX(name, stop, 0x17, op | 0x01, type); \
2911GEN_STX(name, stop, 0x17, op | 0x00, type)
79aceca5
FB		 2912
2913/* stb stbu stbux stbx */
0c8aacd4 2914GEN_STS(stb, st8, 0x06, PPC_INTEGER);
79aceca5 2915/* sth sthu sthux sthx */
0c8aacd4 2916GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
79aceca5 2917/* stw stwu stwux stwx */
0c8aacd4 2918GEN_STS(stw, st32, 0x04, PPC_INTEGER);
d9bce9d9 2919#if defined(TARGET_PPC64)
0c8aacd4
AJ		 2920GEN_STUX(std, st64, 0x15, 0x05, PPC_64B);
2921GEN_STX(std, st64, 0x15, 0x04, PPC_64B);
be147d08 2922GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B)
d9bce9d9 2923{
be147d08 2924 int rs;
b61f2753 2925 TCGv EA;
be147d08
JM		 2926
2927 rs = rS(ctx->opcode);
2928 if ((ctx->opcode & 0x3) == 0x2) {
2929#if defined(CONFIG_USER_ONLY)
e06fcd75 2930 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
be147d08
JM		 2931#else
2932 /* stq */
76db3ba4 2933 if (unlikely(ctx->mem_idx == 0)) {
e06fcd75 2934 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
be147d08
JM		 2935 return;
2936 }
2937 if (unlikely(rs & 1)) {
e06fcd75 2938 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
d9bce9d9
JM		 2939 return;
2940 }
76db3ba4 2941 if (unlikely(ctx->le_mode)) {
be147d08 2942 /* Little-endian mode is not handled */
e06fcd75 2943 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
be147d08
JM		 2944 return;
2945 }
76db3ba4 2946 gen_set_access_type(ctx, ACCESS_INT);
a7812ae4 2947 EA = tcg_temp_new();
76db3ba4
AJ		 2948 gen_addr_imm_index(ctx, EA, 0x03);
2949 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2950 gen_addr_add(ctx, EA, EA, 8);
2951 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
b61f2753 2952 tcg_temp_free(EA);
be147d08
JM		 2953#endif
2954 } else {
2955 /* std / stdu */
2956 if (Rc(ctx->opcode)) {
2957 if (unlikely(rA(ctx->opcode) == 0)) {
e06fcd75 2958 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
be147d08
JM		 2959 return;
2960 }
2961 }
76db3ba4 2962 gen_set_access_type(ctx, ACCESS_INT);
a7812ae4 2963 EA = tcg_temp_new();
76db3ba4
AJ		 2964 gen_addr_imm_index(ctx, EA, 0x03);
2965 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
be147d08 2966 if (Rc(ctx->opcode))
b61f2753
AJ		 2967 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2968 tcg_temp_free(EA);
d9bce9d9 2969 }
d9bce9d9
JM		 2970}
2971#endif
79aceca5
FB		 2972/*** Integer load and store with byte reverse ***/
2973/* lhbrx */
76db3ba4 2974static void always_inline gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2975{
76db3ba4
AJ		 2976 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2977 if (likely(!ctx->le_mode)) {
2978#if defined(TARGET_PPC64)
2979 TCGv_i32 t0 = tcg_temp_new_i32();
2980 tcg_gen_trunc_tl_i32(t0, arg1);
2981 tcg_gen_bswap16_i32(t0, t0);
2982 tcg_gen_extu_i32_tl(arg1, t0);
2983 tcg_temp_free_i32(t0);
2984#else
2985 tcg_gen_bswap16_i32(arg1, arg1);
2986#endif
2987 }
b61f2753 2988}
0c8aacd4 2989GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
b61f2753 2990
79aceca5 2991/* lwbrx */
76db3ba4 2992static void always_inline gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2993{
76db3ba4
AJ		 2994 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2995 if (likely(!ctx->le_mode)) {
2996#if defined(TARGET_PPC64)
2997 TCGv_i32 t0 = tcg_temp_new_i32();
2998 tcg_gen_trunc_tl_i32(t0, arg1);
2999 tcg_gen_bswap_i32(t0, t0);
3000 tcg_gen_extu_i32_tl(arg1, t0);
3001 tcg_temp_free_i32(t0);
3002#else
3003 tcg_gen_bswap_i32(arg1, arg1);
3004#endif
3005 }
b61f2753 3006}
0c8aacd4 3007GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
b61f2753 3008
79aceca5 3009/* sthbrx */
76db3ba4 3010static void always_inline gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 3011{
76db3ba4
AJ		 3012 if (likely(!ctx->le_mode)) {
3013#if defined(TARGET_PPC64)
3014 TCGv_i32 t0;
3015 TCGv t1;
3016 t0 = tcg_temp_new_i32();
3017 tcg_gen_trunc_tl_i32(t0, arg1);
3018 tcg_gen_ext16u_i32(t0, t0);
3019 tcg_gen_bswap16_i32(t0, t0);
3020 t1 = tcg_temp_new();
3021 tcg_gen_extu_i32_tl(t1, t0);
3022 tcg_temp_free_i32(t0);
3023 tcg_gen_qemu_st16(t1, arg2, ctx->mem_idx);
3024 tcg_temp_free(t1);
3025#else
3026 TCGv t0 = tcg_temp_new();
3027 tcg_gen_ext16u_tl(t0, arg1);
3028 tcg_gen_bswap16_i32(t0, t0);
3029 tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
3030 tcg_temp_free(t0);
3031#endif
3032 } else {
3033 tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
3034 }
b61f2753 3035}
0c8aacd4 3036GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
b61f2753 3037
79aceca5 3038/* stwbrx */
76db3ba4 3039static void always_inline gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 3040{
76db3ba4
AJ		 3041 if (likely(!ctx->le_mode)) {
3042#if defined(TARGET_PPC64)
3043 TCGv_i32 t0;
3044 TCGv t1;
3045 t0 = tcg_temp_new_i32();
3046 tcg_gen_trunc_tl_i32(t0, arg1);
3047 tcg_gen_bswap_i32(t0, t0);
3048 t1 = tcg_temp_new();
3049 tcg_gen_extu_i32_tl(t1, t0);
3050 tcg_temp_free_i32(t0);
3051 tcg_gen_qemu_st32(t1, arg2, ctx->mem_idx);
3052 tcg_temp_free(t1);
3053#else
3054 TCGv t0 = tcg_temp_new_i32();
3055 tcg_gen_bswap_i32(t0, arg1);
3056 tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
3057 tcg_temp_free(t0);
3058#endif
3059 } else {
3060 tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
3061 }
b61f2753 3062}
0c8aacd4 3063GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
79aceca5
FB		 3064
3065/*** Integer load and store multiple ***/
3066/* lmw */
3067GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
3068{
76db3ba4
AJ		 3069 TCGv t0;
3070 TCGv_i32 t1;
3071 gen_set_access_type(ctx, ACCESS_INT);
76a66253 3072 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3073 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 3074 t0 = tcg_temp_new();
3075 t1 = tcg_const_i32(rD(ctx->opcode));
3076 gen_addr_imm_index(ctx, t0, 0);
ff4a62cd
AJ		 3077 gen_helper_lmw(t0, t1);
3078 tcg_temp_free(t0);
3079 tcg_temp_free_i32(t1);
79aceca5
FB		 3080}
3081
3082/* stmw */
3083GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
3084{
76db3ba4
AJ		 3085 TCGv t0;
3086 TCGv_i32 t1;
3087 gen_set_access_type(ctx, ACCESS_INT);
76a66253 3088 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3089 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 3090 t0 = tcg_temp_new();
3091 t1 = tcg_const_i32(rS(ctx->opcode));
3092 gen_addr_imm_index(ctx, t0, 0);
ff4a62cd
AJ		 3093 gen_helper_stmw(t0, t1);
3094 tcg_temp_free(t0);
3095 tcg_temp_free_i32(t1);
79aceca5
FB		 3096}
3097
3098/*** Integer load and store strings ***/
3099/* lswi */
3fc6c082 3100/* PowerPC32 specification says we must generate an exception if
9a64fbe4
FB		 3101 * rA is in the range of registers to be loaded.
3102 * In an other hand, IBM says this is valid, but rA won't be loaded.
3103 * For now, I'll follow the spec...
3104 */
05332d70 3105GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING)
79aceca5 3106{
dfbc799d
AJ		 3107 TCGv t0;
3108 TCGv_i32 t1, t2;
79aceca5
FB		 3109 int nb = NB(ctx->opcode);
3110 int start = rD(ctx->opcode);
9a64fbe4 3111 int ra = rA(ctx->opcode);
79aceca5
FB		 3112 int nr;
3113
3114 if (nb == 0)
3115 nb = 32;
3116 nr = nb / 4;
76a66253
JM		 3117 if (unlikely(((start + nr) > 32 &&
3118 start <= ra && (start + nr - 32) > ra) ||
3119 ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
e06fcd75 3120 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
9fddaa0c 3121 return;
297d8e62 3122 }
76db3ba4 3123 gen_set_access_type(ctx, ACCESS_INT);
8dd4983c 3124 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3125 gen_update_nip(ctx, ctx->nip - 4);
dfbc799d 3126 t0 = tcg_temp_new();
76db3ba4 3127 gen_addr_register(ctx, t0);
dfbc799d
AJ		 3128 t1 = tcg_const_i32(nb);
3129 t2 = tcg_const_i32(start);
3130 gen_helper_lsw(t0, t1, t2);
3131 tcg_temp_free(t0);
3132 tcg_temp_free_i32(t1);
3133 tcg_temp_free_i32(t2);
79aceca5
FB		 3134}
3135
3136/* lswx */
05332d70 3137GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING)
79aceca5 3138{
76db3ba4
AJ		 3139 TCGv t0;
3140 TCGv_i32 t1, t2, t3;
3141 gen_set_access_type(ctx, ACCESS_INT);
76a66253 3142 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3143 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 3144 t0 = tcg_temp_new();
3145 gen_addr_reg_index(ctx, t0);
3146 t1 = tcg_const_i32(rD(ctx->opcode));
3147 t2 = tcg_const_i32(rA(ctx->opcode));
3148 t3 = tcg_const_i32(rB(ctx->opcode));
dfbc799d
AJ		 3149 gen_helper_lswx(t0, t1, t2, t3);
3150 tcg_temp_free(t0);
3151 tcg_temp_free_i32(t1);
3152 tcg_temp_free_i32(t2);
3153 tcg_temp_free_i32(t3);
79aceca5
FB		 3154}
3155
3156/* stswi */
05332d70 3157GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING)
79aceca5 3158{
76db3ba4
AJ		 3159 TCGv t0;
3160 TCGv_i32 t1, t2;
4b3686fa 3161 int nb = NB(ctx->opcode);
76db3ba4 3162 gen_set_access_type(ctx, ACCESS_INT);
76a66253 3163 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3164 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 3165 t0 = tcg_temp_new();
3166 gen_addr_register(ctx, t0);
4b3686fa
FB		 3167 if (nb == 0)
3168 nb = 32;
dfbc799d 3169 t1 = tcg_const_i32(nb);
76db3ba4 3170 t2 = tcg_const_i32(rS(ctx->opcode));
dfbc799d
AJ		 3171 gen_helper_stsw(t0, t1, t2);
3172 tcg_temp_free(t0);
3173 tcg_temp_free_i32(t1);
3174 tcg_temp_free_i32(t2);
79aceca5
FB		 3175}
3176
3177/* stswx */
05332d70 3178GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING)
79aceca5 3179{
76db3ba4
AJ		 3180 TCGv t0;
3181 TCGv_i32 t1, t2;
3182 gen_set_access_type(ctx, ACCESS_INT);
8dd4983c 3183 /* NIP cannot be restored if the memory exception comes from an helper */
5fafdf24 3184 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 3185 t0 = tcg_temp_new();
3186 gen_addr_reg_index(ctx, t0);
3187 t1 = tcg_temp_new_i32();
dfbc799d
AJ		 3188 tcg_gen_trunc_tl_i32(t1, cpu_xer);
3189 tcg_gen_andi_i32(t1, t1, 0x7F);
76db3ba4 3190 t2 = tcg_const_i32(rS(ctx->opcode));
dfbc799d
AJ		 3191 gen_helper_stsw(t0, t1, t2);
3192 tcg_temp_free(t0);
3193 tcg_temp_free_i32(t1);
3194 tcg_temp_free_i32(t2);
79aceca5
FB		 3195}
3196
3197/*** Memory synchronisation ***/
3198/* eieio */
0db1b20e 3199GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO)
79aceca5 3200{
79aceca5
FB		 3201}
3202
3203/* isync */
0db1b20e 3204GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM)
79aceca5 3205{
e06fcd75 3206 gen_stop_exception(ctx);
79aceca5
FB		 3207}
3208
111bfab3 3209/* lwarx */
76a66253 3210GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000001, PPC_RES)
79aceca5 3211{
76db3ba4
AJ		 3212 TCGv t0;
3213 gen_set_access_type(ctx, ACCESS_RES);
3214 t0 = tcg_temp_local_new();
3215 gen_addr_reg_index(ctx, t0);
cf360a32 3216 gen_check_align(ctx, t0, 0x03);
76db3ba4 3217 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
cf360a32
AJ		 3218 tcg_gen_mov_tl(cpu_reserve, t0);
3219 tcg_temp_free(t0);
79aceca5
FB		 3220}
3221
3222/* stwcx. */
c7697e1f 3223GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES)
79aceca5 3224{
76db3ba4
AJ		 3225 int l1;
3226 TCGv t0;
3227 gen_set_access_type(ctx, ACCESS_RES);
3228 t0 = tcg_temp_local_new();
3229 gen_addr_reg_index(ctx, t0);
cf360a32 3230 gen_check_align(ctx, t0, 0x03);
cf360a32
AJ		 3231 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
3232 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
3233 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
76db3ba4 3234 l1 = gen_new_label();
cf360a32
AJ		 3235 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3236 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
76db3ba4 3237 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], t0);
cf360a32
AJ		 3238 gen_set_label(l1);
3239 tcg_gen_movi_tl(cpu_reserve, -1);
3240 tcg_temp_free(t0);
79aceca5
FB		 3241}
3242
426613db 3243#if defined(TARGET_PPC64)
426613db 3244/* ldarx */
a750fc0b 3245GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000001, PPC_64B)
426613db 3246{
76db3ba4
AJ		 3247 TCGv t0;
3248 gen_set_access_type(ctx, ACCESS_RES);
3249 t0 = tcg_temp_local_new();
3250 gen_addr_reg_index(ctx, t0);
cf360a32 3251 gen_check_align(ctx, t0, 0x07);
76db3ba4 3252 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], t0);
cf360a32
AJ		 3253 tcg_gen_mov_tl(cpu_reserve, t0);
3254 tcg_temp_free(t0);
426613db
JM		 3255}
3256
3257/* stdcx. */
c7697e1f 3258GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B)
426613db 3259{
76db3ba4
AJ		 3260 int l1;
3261 TCGv t0;
3262 gen_set_access_type(ctx, ACCESS_RES);
3263 t0 = tcg_temp_local_new();
3264 gen_addr_reg_index(ctx, t0);
cf360a32 3265 gen_check_align(ctx, t0, 0x07);
cf360a32
AJ		 3266 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
3267 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
3268 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
76db3ba4 3269 l1 = gen_new_label();
cf360a32
AJ		 3270 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3271 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
76db3ba4 3272 gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], t0);
cf360a32
AJ		 3273 gen_set_label(l1);
3274 tcg_gen_movi_tl(cpu_reserve, -1);
3275 tcg_temp_free(t0);
426613db
JM		 3276}
3277#endif /* defined(TARGET_PPC64) */
3278
79aceca5 3279/* sync */
a902d886 3280GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC)
79aceca5 3281{
79aceca5
FB		 3282}
3283
0db1b20e
JM		 3284/* wait */
3285GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT)
3286{
931ff272
AJ		 3287 TCGv_i32 t0 = tcg_temp_new_i32();
3288 tcg_gen_st_i32(t0, cpu_env, offsetof(CPUState, halted));
3289 tcg_temp_free_i32(t0);
0db1b20e 3290 /* Stop translation, as the CPU is supposed to sleep from now */
e06fcd75 3291 gen_exception_err(ctx, EXCP_HLT, 1);
0db1b20e
JM		 3292}
3293
79aceca5 3294/*** Floating-point load ***/
a0d7d5a7
AJ		 3295#define GEN_LDF(name, ldop, opc, type) \
3296GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 3297{ \
a0d7d5a7 3298 TCGv EA; \
76a66253 3299 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3300 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3301 return; \
3302 } \
76db3ba4 3303 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3304 EA = tcg_temp_new(); \
76db3ba4
AJ		 3305 gen_addr_imm_index(ctx, EA, 0); \
3306 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
a0d7d5a7 3307 tcg_temp_free(EA); \
79aceca5
FB		 3308}
3309
a0d7d5a7
AJ		 3310#define GEN_LDUF(name, ldop, opc, type) \
3311GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 3312{ \
a0d7d5a7 3313 TCGv EA; \
76a66253 3314 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3315 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3316 return; \
3317 } \
76a66253 3318 if (unlikely(rA(ctx->opcode) == 0)) { \
e06fcd75 3319 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 3320 return; \
9a64fbe4 3321 } \
76db3ba4 3322 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3323 EA = tcg_temp_new(); \
76db3ba4
AJ		 3324 gen_addr_imm_index(ctx, EA, 0); \
3325 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
a0d7d5a7
AJ		 3326 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3327 tcg_temp_free(EA); \
79aceca5
FB		 3328}
3329
a0d7d5a7
AJ		 3330#define GEN_LDUXF(name, ldop, opc, type) \
3331GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type) \
79aceca5 3332{ \
a0d7d5a7 3333 TCGv EA; \
76a66253 3334 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3335 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3336 return; \
3337 } \
76a66253 3338 if (unlikely(rA(ctx->opcode) == 0)) { \
e06fcd75 3339 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 3340 return; \
9a64fbe4 3341 } \
76db3ba4 3342 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3343 EA = tcg_temp_new(); \
76db3ba4
AJ		 3344 gen_addr_reg_index(ctx, EA); \
3345 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
a0d7d5a7
AJ		 3346 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3347 tcg_temp_free(EA); \
79aceca5
FB		 3348}
3349
a0d7d5a7
AJ		 3350#define GEN_LDXF(name, ldop, opc2, opc3, type) \
3351GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 3352{ \
a0d7d5a7 3353 TCGv EA; \
76a66253 3354 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3355 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3356 return; \
3357 } \
76db3ba4 3358 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3359 EA = tcg_temp_new(); \
76db3ba4
AJ		 3360 gen_addr_reg_index(ctx, EA); \
3361 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
a0d7d5a7 3362 tcg_temp_free(EA); \
79aceca5
FB		 3363}
3364
a0d7d5a7
AJ		 3365#define GEN_LDFS(name, ldop, op, type) \
3366GEN_LDF(name, ldop, op | 0x20, type); \
3367GEN_LDUF(name, ldop, op | 0x21, type); \
3368GEN_LDUXF(name, ldop, op | 0x01, type); \
3369GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
3370
76db3ba4 3371static always_inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
a0d7d5a7
AJ		 3372{
3373 TCGv t0 = tcg_temp_new();
3374 TCGv_i32 t1 = tcg_temp_new_i32();
76db3ba4 3375 gen_qemu_ld32u(ctx, t0, arg2);
a0d7d5a7
AJ		 3376 tcg_gen_trunc_tl_i32(t1, t0);
3377 tcg_temp_free(t0);
3378 gen_helper_float32_to_float64(arg1, t1);
3379 tcg_temp_free_i32(t1);
3380}
79aceca5 3381
a0d7d5a7
AJ		 3382 /* lfd lfdu lfdux lfdx */
3383GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT);
3384 /* lfs lfsu lfsux lfsx */
3385GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
79aceca5
FB		 3386
3387/*** Floating-point store ***/
a0d7d5a7
AJ		 3388#define GEN_STF(name, stop, opc, type) \
3389GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 3390{ \
a0d7d5a7 3391 TCGv EA; \
76a66253 3392 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3393 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3394 return; \
3395 } \
76db3ba4 3396 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3397 EA = tcg_temp_new(); \
76db3ba4
AJ		 3398 gen_addr_imm_index(ctx, EA, 0); \
3399 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
a0d7d5a7 3400 tcg_temp_free(EA); \
79aceca5
FB		 3401}
3402
a0d7d5a7
AJ		 3403#define GEN_STUF(name, stop, opc, type) \
3404GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 3405{ \
a0d7d5a7 3406 TCGv EA; \
76a66253 3407 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3408 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3409 return; \
3410 } \
76a66253 3411 if (unlikely(rA(ctx->opcode) == 0)) { \
e06fcd75 3412 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 3413 return; \
9a64fbe4 3414 } \
76db3ba4 3415 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3416 EA = tcg_temp_new(); \
76db3ba4
AJ		 3417 gen_addr_imm_index(ctx, EA, 0); \
3418 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
a0d7d5a7
AJ		 3419 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3420 tcg_temp_free(EA); \
79aceca5
FB		 3421}
3422
a0d7d5a7
AJ		 3423#define GEN_STUXF(name, stop, opc, type) \
3424GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type) \
79aceca5 3425{ \
a0d7d5a7 3426 TCGv EA; \
76a66253 3427 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3428 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3429 return; \
3430 } \
76a66253 3431 if (unlikely(rA(ctx->opcode) == 0)) { \
e06fcd75 3432 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 3433 return; \
9a64fbe4 3434 } \
76db3ba4 3435 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3436 EA = tcg_temp_new(); \
76db3ba4
AJ		 3437 gen_addr_reg_index(ctx, EA); \
3438 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
a0d7d5a7
AJ		 3439 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3440 tcg_temp_free(EA); \
79aceca5
FB		 3441}
3442
a0d7d5a7
AJ		 3443#define GEN_STXF(name, stop, opc2, opc3, type) \
3444GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 3445{ \
a0d7d5a7 3446 TCGv EA; \
76a66253 3447 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3448 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3449 return; \
3450 } \
76db3ba4 3451 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3452 EA = tcg_temp_new(); \
76db3ba4
AJ		 3453 gen_addr_reg_index(ctx, EA); \
3454 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
a0d7d5a7 3455 tcg_temp_free(EA); \
79aceca5
FB		 3456}
3457
a0d7d5a7
AJ		 3458#define GEN_STFS(name, stop, op, type) \
3459GEN_STF(name, stop, op | 0x20, type); \
3460GEN_STUF(name, stop, op | 0x21, type); \
3461GEN_STUXF(name, stop, op | 0x01, type); \
3462GEN_STXF(name, stop, 0x17, op | 0x00, type)
3463
76db3ba4 3464static always_inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
a0d7d5a7
AJ		 3465{
3466 TCGv_i32 t0 = tcg_temp_new_i32();
3467 TCGv t1 = tcg_temp_new();
3468 gen_helper_float64_to_float32(t0, arg1);
3469 tcg_gen_extu_i32_tl(t1, t0);
3470 tcg_temp_free_i32(t0);
76db3ba4 3471 gen_qemu_st32(ctx, t1, arg2);
a0d7d5a7
AJ		 3472 tcg_temp_free(t1);
3473}
79aceca5
FB		 3474
3475/* stfd stfdu stfdux stfdx */
a0d7d5a7 3476GEN_STFS(stfd, st64, 0x16, PPC_FLOAT);
79aceca5 3477/* stfs stfsu stfsux stfsx */
a0d7d5a7 3478GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
79aceca5
FB		 3479
3480/* Optional: */
76db3ba4 3481static always_inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
a0d7d5a7
AJ		 3482{
3483 TCGv t0 = tcg_temp_new();
3484 tcg_gen_trunc_i64_tl(t0, arg1),
76db3ba4 3485 gen_qemu_st32(ctx, t0, arg2);
a0d7d5a7
AJ		 3486 tcg_temp_free(t0);
3487}
79aceca5 3488/* stfiwx */
a0d7d5a7 3489GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
79aceca5
FB		 3490
3491/*** Branch ***/
b068d6a7
JM		 3492static always_inline void gen_goto_tb (DisasContext *ctx, int n,
3493 target_ulong dest)
c1942362
FB		 3494{
3495 TranslationBlock *tb;
3496 tb = ctx->tb;
a2ffb812
AJ		 3497#if defined(TARGET_PPC64)
3498 if (!ctx->sf_mode)
3499 dest = (uint32_t) dest;
3500#endif
57fec1fe 3501 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
8cbcb4fa 3502 likely(!ctx->singlestep_enabled)) {
57fec1fe 3503 tcg_gen_goto_tb(n);
a2ffb812 3504 tcg_gen_movi_tl(cpu_nip, dest & ~3);
57fec1fe 3505 tcg_gen_exit_tb((long)tb + n);
c1942362 3506 } else {
a2ffb812 3507 tcg_gen_movi_tl(cpu_nip, dest & ~3);
8cbcb4fa
AJ		 3508 if (unlikely(ctx->singlestep_enabled)) {
3509 if ((ctx->singlestep_enabled &
bdc4e053 3510 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
8cbcb4fa
AJ		 3511 ctx->exception == POWERPC_EXCP_BRANCH) {
3512 target_ulong tmp = ctx->nip;
3513 ctx->nip = dest;
e06fcd75 3514 gen_exception(ctx, POWERPC_EXCP_TRACE);
8cbcb4fa
AJ		 3515 ctx->nip = tmp;
3516 }
3517 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
e06fcd75 3518 gen_debug_exception(ctx);
8cbcb4fa
AJ		 3519 }
3520 }
57fec1fe 3521 tcg_gen_exit_tb(0);
c1942362 3522 }
c53be334
FB		 3523}
3524
b068d6a7 3525static always_inline void gen_setlr (DisasContext *ctx, target_ulong nip)
e1833e1f
JM		 3526{
3527#if defined(TARGET_PPC64)
a2ffb812
AJ		 3528 if (ctx->sf_mode == 0)
3529 tcg_gen_movi_tl(cpu_lr, (uint32_t)nip);
e1833e1f
JM		 3530 else
3531#endif
a2ffb812 3532 tcg_gen_movi_tl(cpu_lr, nip);
e1833e1f
JM		 3533}
3534
79aceca5
FB		 3535/* b ba bl bla */
3536GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3537{
76a66253 3538 target_ulong li, target;
38a64f9d 3539
8cbcb4fa 3540 ctx->exception = POWERPC_EXCP_BRANCH;
38a64f9d 3541 /* sign extend LI */
76a66253 3542#if defined(TARGET_PPC64)
d9bce9d9
JM		 3543 if (ctx->sf_mode)
3544 li = ((int64_t)LI(ctx->opcode) << 38) >> 38;
3545 else
76a66253 3546#endif
d9bce9d9 3547 li = ((int32_t)LI(ctx->opcode) << 6) >> 6;
76a66253 3548 if (likely(AA(ctx->opcode) == 0))
046d6672 3549 target = ctx->nip + li - 4;
79aceca5 3550 else
9a64fbe4 3551 target = li;
e1833e1f
JM		 3552 if (LK(ctx->opcode))
3553 gen_setlr(ctx, ctx->nip);
c1942362 3554 gen_goto_tb(ctx, 0, target);
79aceca5
FB		 3555}
3556
e98a6e40
FB		 3557#define BCOND_IM 0
3558#define BCOND_LR 1
3559#define BCOND_CTR 2
3560
b068d6a7 3561static always_inline void gen_bcond (DisasContext *ctx, int type)
d9bce9d9 3562{
d9bce9d9 3563 uint32_t bo = BO(ctx->opcode);
a2ffb812
AJ		 3564 int l1 = gen_new_label();
3565 TCGv target;
e98a6e40 3566
8cbcb4fa 3567 ctx->exception = POWERPC_EXCP_BRANCH;
a2ffb812 3568 if (type == BCOND_LR || type == BCOND_CTR) {
a7812ae4 3569 target = tcg_temp_local_new();
a2ffb812
AJ		 3570 if (type == BCOND_CTR)
3571 tcg_gen_mov_tl(target, cpu_ctr);
3572 else
3573 tcg_gen_mov_tl(target, cpu_lr);
e98a6e40 3574 }
e1833e1f
JM		 3575 if (LK(ctx->opcode))
3576 gen_setlr(ctx, ctx->nip);
a2ffb812
AJ		 3577 l1 = gen_new_label();
3578 if ((bo & 0x4) == 0) {
3579 /* Decrement and test CTR */
a7812ae4 3580 TCGv temp = tcg_temp_new();
a2ffb812 3581 if (unlikely(type == BCOND_CTR)) {
e06fcd75 3582 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
a2ffb812
AJ		 3583 return;
3584 }
3585 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
d9bce9d9 3586#if defined(TARGET_PPC64)
a2ffb812
AJ		 3587 if (!ctx->sf_mode)
3588 tcg_gen_ext32u_tl(temp, cpu_ctr);
3589 else
d9bce9d9 3590#endif
a2ffb812
AJ		 3591 tcg_gen_mov_tl(temp, cpu_ctr);
3592 if (bo & 0x2) {
3593 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3594 } else {
3595 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
e98a6e40 3596 }
a7812ae4 3597 tcg_temp_free(temp);
a2ffb812
AJ		 3598 }
3599 if ((bo & 0x10) == 0) {
3600 /* Test CR */
3601 uint32_t bi = BI(ctx->opcode);
3602 uint32_t mask = 1 << (3 - (bi & 0x03));
a7812ae4 3603 TCGv_i32 temp = tcg_temp_new_i32();
a2ffb812 3604
d9bce9d9 3605 if (bo & 0x8) {
a2ffb812
AJ		 3606 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3607 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
d9bce9d9 3608 } else {
a2ffb812
AJ		 3609 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3610 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
d9bce9d9 3611 }
a7812ae4 3612 tcg_temp_free_i32(temp);
d9bce9d9 3613 }
e98a6e40 3614 if (type == BCOND_IM) {
a2ffb812
AJ		 3615 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3616 if (likely(AA(ctx->opcode) == 0)) {
3617 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3618 } else {
3619 gen_goto_tb(ctx, 0, li);
3620 }
c53be334 3621 gen_set_label(l1);
c1942362 3622 gen_goto_tb(ctx, 1, ctx->nip);
e98a6e40 3623 } else {
d9bce9d9 3624#if defined(TARGET_PPC64)
a2ffb812
AJ		 3625 if (!(ctx->sf_mode))
3626 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3627 else
3628#endif
3629 tcg_gen_andi_tl(cpu_nip, target, ~3);
3630 tcg_gen_exit_tb(0);
3631 gen_set_label(l1);
3632#if defined(TARGET_PPC64)
3633 if (!(ctx->sf_mode))
3634 tcg_gen_movi_tl(cpu_nip, (uint32_t)ctx->nip);
d9bce9d9
JM		 3635 else
3636#endif
a2ffb812 3637 tcg_gen_movi_tl(cpu_nip, ctx->nip);
57fec1fe 3638 tcg_gen_exit_tb(0);
08e46e54 3639 }
e98a6e40
FB		 3640}
3641
3642GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3b46e624 3643{
e98a6e40
FB		 3644 gen_bcond(ctx, BCOND_IM);
3645}
3646
3647GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW)
3b46e624 3648{
e98a6e40
FB		 3649 gen_bcond(ctx, BCOND_CTR);
3650}
3651
3652GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW)
3b46e624 3653{
e98a6e40
FB		 3654 gen_bcond(ctx, BCOND_LR);
3655}
79aceca5
FB		 3656
3657/*** Condition register logical ***/
e1571908
AJ		 3658#define GEN_CRLOGIC(name, tcg_op, opc) \
3659GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) \
79aceca5 3660{ \
fc0d441e
JM		 3661 uint8_t bitmask; \
3662 int sh; \
a7812ae4 3663 TCGv_i32 t0, t1; \
fc0d441e 3664 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
a7812ae4 3665 t0 = tcg_temp_new_i32(); \
fc0d441e 3666 if (sh > 0) \
fea0c503 3667 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
fc0d441e 3668 else if (sh < 0) \
fea0c503 3669 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
e1571908 3670 else \
fea0c503 3671 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
a7812ae4 3672 t1 = tcg_temp_new_i32(); \
fc0d441e
JM		 3673 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3674 if (sh > 0) \
fea0c503 3675 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
fc0d441e 3676 else if (sh < 0) \
fea0c503 3677 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
e1571908 3678 else \
fea0c503
AJ		 3679 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3680 tcg_op(t0, t0, t1); \
fc0d441e 3681 bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \
fea0c503
AJ		 3682 tcg_gen_andi_i32(t0, t0, bitmask); \
3683 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3684 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
a7812ae4
PB		 3685 tcg_temp_free_i32(t0); \
3686 tcg_temp_free_i32(t1); \
79aceca5
FB		 3687}
3688
3689/* crand */
e1571908 3690GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
79aceca5 3691/* crandc */
e1571908 3692GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
79aceca5 3693/* creqv */
e1571908 3694GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
79aceca5 3695/* crnand */
e1571908 3696GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
79aceca5 3697/* crnor */
e1571908 3698GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
79aceca5 3699/* cror */
e1571908 3700GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
79aceca5 3701/* crorc */
e1571908 3702GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
79aceca5 3703/* crxor */
e1571908 3704GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
79aceca5
FB		 3705/* mcrf */
3706GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER)
3707{
47e4661c 3708 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
79aceca5
FB		 3709}
3710
3711/*** System linkage ***/
76db3ba4 3712/* rfi (mem_idx only) */
76a66253 3713GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW)
79aceca5 3714{
9a64fbe4 3715#if defined(CONFIG_USER_ONLY)
e06fcd75 3716 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9a64fbe4
FB		 3717#else
3718 /* Restore CPU state */
76db3ba4 3719 if (unlikely(!ctx->mem_idx)) {
e06fcd75 3720 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9fddaa0c 3721 return;
9a64fbe4 3722 }
d72a19f7 3723 gen_helper_rfi();
e06fcd75 3724 gen_sync_exception(ctx);
9a64fbe4 3725#endif
79aceca5
FB		 3726}
3727
426613db 3728#if defined(TARGET_PPC64)
a750fc0b 3729GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B)
426613db
JM		 3730{
3731#if defined(CONFIG_USER_ONLY)
e06fcd75 3732 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
426613db
JM		 3733#else
3734 /* Restore CPU state */
76db3ba4 3735 if (unlikely(!ctx->mem_idx)) {
e06fcd75 3736 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
426613db
JM		 3737 return;
3738 }
d72a19f7 3739 gen_helper_rfid();
e06fcd75 3740 gen_sync_exception(ctx);
426613db
JM		 3741#endif
3742}
426613db 3743
5b8105fa 3744GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H)
be147d08
JM		 3745{
3746#if defined(CONFIG_USER_ONLY)
e06fcd75 3747 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
be147d08
JM		 3748#else
3749 /* Restore CPU state */
76db3ba4 3750 if (unlikely(ctx->mem_idx <= 1)) {
e06fcd75 3751 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
be147d08
JM		 3752 return;
3753 }
d72a19f7 3754 gen_helper_hrfid();
e06fcd75 3755 gen_sync_exception(ctx);
be147d08
JM		 3756#endif
3757}
3758#endif
3759
79aceca5 3760/* sc */
417bf010
JM		 3761#if defined(CONFIG_USER_ONLY)
3762#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3763#else
3764#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3765#endif
e1833e1f 3766GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW)
79aceca5 3767{
e1833e1f
JM		 3768 uint32_t lev;
3769
3770 lev = (ctx->opcode >> 5) & 0x7F;
e06fcd75 3771 gen_exception_err(ctx, POWERPC_SYSCALL, lev);
79aceca5
FB		 3772}
3773
3774/*** Trap ***/
3775/* tw */
76a66253 3776GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW)
79aceca5 3777{
cab3bee2 3778 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
a0ae05aa 3779 /* Update the nip since this might generate a trap exception */
d9bce9d9 3780 gen_update_nip(ctx, ctx->nip);
cab3bee2
AJ		 3781 gen_helper_tw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
3782 tcg_temp_free_i32(t0);
79aceca5
FB		 3783}
3784
3785/* twi */
3786GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3787{
cab3bee2
AJ		 3788 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3789 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
d9bce9d9
JM		 3790 /* Update the nip since this might generate a trap exception */
3791 gen_update_nip(ctx, ctx->nip);
cab3bee2
AJ		 3792 gen_helper_tw(cpu_gpr[rA(ctx->opcode)], t0, t1);
3793 tcg_temp_free(t0);
3794 tcg_temp_free_i32(t1);
79aceca5
FB		 3795}
3796
d9bce9d9
JM		 3797#if defined(TARGET_PPC64)
3798/* td */
3799GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B)
3800{
cab3bee2 3801 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
d9bce9d9
JM		 3802 /* Update the nip since this might generate a trap exception */
3803 gen_update_nip(ctx, ctx->nip);
cab3bee2
AJ		 3804 gen_helper_td(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
3805 tcg_temp_free_i32(t0);
d9bce9d9
JM		 3806}
3807
3808/* tdi */
3809GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B)
3810{
cab3bee2
AJ		 3811 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3812 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
d9bce9d9
JM		 3813 /* Update the nip since this might generate a trap exception */
3814 gen_update_nip(ctx, ctx->nip);
cab3bee2
AJ		 3815 gen_helper_td(cpu_gpr[rA(ctx->opcode)], t0, t1);
3816 tcg_temp_free(t0);
3817 tcg_temp_free_i32(t1);
d9bce9d9
JM		 3818}
3819#endif
3820
79aceca5 3821/*** Processor control ***/
79aceca5
FB		 3822/* mcrxr */
3823GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC)
3824{
3d7b417e
AJ		 3825 tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], cpu_xer);
3826 tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], XER_CA);
269f3e95 3827 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_SO | 1 << XER_OV | 1 << XER_CA));
79aceca5
FB		 3828}
3829
3830/* mfcr */
76a66253 3831GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC)
79aceca5 3832{
76a66253 3833 uint32_t crm, crn;
3b46e624 3834
76a66253
JM		 3835 if (likely(ctx->opcode & 0x00100000)) {
3836 crm = CRM(ctx->opcode);
3837 if (likely((crm ^ (crm - 1)) == 0)) {
3838 crn = ffs(crm);
e1571908 3839 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
76a66253 3840 }
d9bce9d9 3841 } else {
a7812ae4 3842 gen_helper_load_cr(cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 3843 }
79aceca5
FB		 3844}
3845
3846/* mfmsr */
3847GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC)
3848{
9a64fbe4 3849#if defined(CONFIG_USER_ONLY)
e06fcd75 3850 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9a64fbe4 3851#else
76db3ba4 3852 if (unlikely(!ctx->mem_idx)) {
e06fcd75 3853 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9fddaa0c 3854 return;
9a64fbe4 3855 }
6527f6ea 3856 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
9a64fbe4 3857#endif
79aceca5
FB		 3858}
3859
a11b8151 3860#if 1
6f2d8978 3861#define SPR_NOACCESS ((void *)(-1UL))
3fc6c082
FB		 3862#else
3863static void spr_noaccess (void *opaque, int sprn)
3864{
3865 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
3866 printf("ERROR: try to access SPR %d !\n", sprn);
3867}
3868#define SPR_NOACCESS (&spr_noaccess)
3869#endif
3870
79aceca5 3871/* mfspr */
b068d6a7 3872static always_inline void gen_op_mfspr (DisasContext *ctx)
79aceca5 3873{
45d827d2 3874 void (*read_cb)(void *opaque, int gprn, int sprn);
79aceca5
FB		 3875 uint32_t sprn = SPR(ctx->opcode);
3876
3fc6c082 3877#if !defined(CONFIG_USER_ONLY)
76db3ba4 3878 if (ctx->mem_idx == 2)
be147d08 3879 read_cb = ctx->spr_cb[sprn].hea_read;
76db3ba4 3880 else if (ctx->mem_idx)
3fc6c082
FB		 3881 read_cb = ctx->spr_cb[sprn].oea_read;
3882 else
9a64fbe4 3883#endif
3fc6c082 3884 read_cb = ctx->spr_cb[sprn].uea_read;
76a66253
JM		 3885 if (likely(read_cb != NULL)) {
3886 if (likely(read_cb != SPR_NOACCESS)) {
45d827d2 3887 (*read_cb)(ctx, rD(ctx->opcode), sprn);
3fc6c082
FB		 3888 } else {
3889 /* Privilege exception */
9fceefa7
JM		 3890 /* This is a hack to avoid warnings when running Linux:
3891 * this OS breaks the PowerPC virtualisation model,
3892 * allowing userland application to read the PVR
3893 */
3894 if (sprn != SPR_PVR) {
3895 if (loglevel != 0) {
6b542af7 3896 fprintf(logfile, "Trying to read privileged spr %d %03x at "
077fc206 3897 ADDRX "\n", sprn, sprn, ctx->nip);
9fceefa7 3898 }
077fc206
JM		 3899 printf("Trying to read privileged spr %d %03x at " ADDRX "\n",
3900 sprn, sprn, ctx->nip);
f24e5695 3901 }
e06fcd75 3902 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
79aceca5 3903 }
3fc6c082
FB		 3904 } else {
3905 /* Not defined */
4a057712 3906 if (loglevel != 0) {
077fc206
JM		 3907 fprintf(logfile, "Trying to read invalid spr %d %03x at "
3908 ADDRX "\n", sprn, sprn, ctx->nip);
f24e5695 3909 }
077fc206
JM		 3910 printf("Trying to read invalid spr %d %03x at " ADDRX "\n",
3911 sprn, sprn, ctx->nip);
e06fcd75 3912 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
79aceca5 3913 }
79aceca5
FB		 3914}
3915
3fc6c082 3916GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC)
79aceca5 3917{
3fc6c082 3918 gen_op_mfspr(ctx);
76a66253 3919}
3fc6c082
FB		 3920
3921/* mftb */
a750fc0b 3922GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB)
3fc6c082
FB		 3923{
3924 gen_op_mfspr(ctx);
79aceca5
FB		 3925}
3926
3927/* mtcrf */
8dd4983c 3928GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC)
79aceca5 3929{
76a66253 3930 uint32_t crm, crn;
3b46e624 3931
76a66253
JM		 3932 crm = CRM(ctx->opcode);
3933 if (likely((ctx->opcode & 0x00100000) || (crm ^ (crm - 1)) == 0)) {
a7812ae4 3934 TCGv_i32 temp = tcg_temp_new_i32();
76a66253 3935 crn = ffs(crm);
a7812ae4
PB		 3936 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
3937 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
e1571908 3938 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
a7812ae4 3939 tcg_temp_free_i32(temp);
76a66253 3940 } else {
a7812ae4
PB		 3941 TCGv_i32 temp = tcg_const_i32(crm);
3942 gen_helper_store_cr(cpu_gpr[rS(ctx->opcode)], temp);
3943 tcg_temp_free_i32(temp);
76a66253 3944 }
79aceca5
FB		 3945}
3946
3947/* mtmsr */
426613db 3948#if defined(TARGET_PPC64)
be147d08 3949GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B)
426613db
JM		 3950{
3951#if defined(CONFIG_USER_ONLY)
e06fcd75 3952 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
426613db 3953#else
76db3ba4 3954 if (unlikely(!ctx->mem_idx)) {
e06fcd75 3955 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
426613db
JM		 3956 return;
3957 }
be147d08
JM		 3958 if (ctx->opcode & 0x00010000) {
3959 /* Special form that does not need any synchronisation */
6527f6ea
AJ		 3960 TCGv t0 = tcg_temp_new();
3961 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
3962 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
3963 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
3964 tcg_temp_free(t0);
be147d08 3965 } else {
056b05f8
JM		 3966 /* XXX: we need to update nip before the store
3967 * if we enter power saving mode, we will exit the loop
3968 * directly from ppc_store_msr
3969 */
be147d08 3970 gen_update_nip(ctx, ctx->nip);
6527f6ea 3971 gen_helper_store_msr(cpu_gpr[rS(ctx->opcode)]);
be147d08
JM		 3972 /* Must stop the translation as machine state (may have) changed */
3973 /* Note that mtmsr is not always defined as context-synchronizing */
e06fcd75 3974 gen_stop_exception(ctx);
be147d08 3975 }
426613db
JM		 3976#endif
3977}
3978#endif
3979
79aceca5
FB		 3980GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC)
3981{
9a64fbe4 3982#if defined(CONFIG_USER_ONLY)
e06fcd75 3983 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9a64fbe4 3984#else
76db3ba4 3985 if (unlikely(!ctx->mem_idx)) {
e06fcd75 3986 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9fddaa0c 3987 return;
9a64fbe4 3988 }
be147d08
JM		 3989 if (ctx->opcode & 0x00010000) {
3990 /* Special form that does not need any synchronisation */
6527f6ea
AJ		 3991 TCGv t0 = tcg_temp_new();
3992 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
3993 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
3994 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
3995 tcg_temp_free(t0);
be147d08 3996 } else {
056b05f8
JM		 3997 /* XXX: we need to update nip before the store
3998 * if we enter power saving mode, we will exit the loop
3999 * directly from ppc_store_msr
4000 */
be147d08 4001 gen_update_nip(ctx, ctx->nip);
d9bce9d9 4002#if defined(TARGET_PPC64)
6527f6ea
AJ		 4003 if (!ctx->sf_mode) {
4004 TCGv t0 = tcg_temp_new();
4005 TCGv t1 = tcg_temp_new();
4006 tcg_gen_andi_tl(t0, cpu_msr, 0xFFFFFFFF00000000ULL);
4007 tcg_gen_ext32u_tl(t1, cpu_gpr[rS(ctx->opcode)]);
4008 tcg_gen_or_tl(t0, t0, t1);
4009 tcg_temp_free(t1);
4010 gen_helper_store_msr(t0);
4011 tcg_temp_free(t0);
4012 } else
d9bce9d9 4013#endif
6527f6ea 4014 gen_helper_store_msr(cpu_gpr[rS(ctx->opcode)]);
be147d08 4015 /* Must stop the translation as machine state (may have) changed */
6527f6ea 4016 /* Note that mtmsr is not always defined as context-synchronizing */
e06fcd75 4017 gen_stop_exception(ctx);
be147d08 4018 }
9a64fbe4 4019#endif
79aceca5
FB		 4020}
4021
4022/* mtspr */
4023GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC)
4024{
45d827d2 4025 void (*write_cb)(void *opaque, int sprn, int gprn);
79aceca5
FB		 4026 uint32_t sprn = SPR(ctx->opcode);
4027
3fc6c082 4028#if !defined(CONFIG_USER_ONLY)
76db3ba4 4029 if (ctx->mem_idx == 2)
be147d08 4030 write_cb = ctx->spr_cb[sprn].hea_write;
76db3ba4 4031 else if (ctx->mem_idx)
3fc6c082
FB		 4032 write_cb = ctx->spr_cb[sprn].oea_write;
4033 else
9a64fbe4 4034#endif
3fc6c082 4035 write_cb = ctx->spr_cb[sprn].uea_write;
76a66253
JM		 4036 if (likely(write_cb != NULL)) {
4037 if (likely(write_cb != SPR_NOACCESS)) {
45d827d2 4038 (*write_cb)(ctx, sprn, rS(ctx->opcode));
3fc6c082
FB		 4039 } else {
4040 /* Privilege exception */
4a057712 4041 if (loglevel != 0) {
077fc206
JM		 4042 fprintf(logfile, "Trying to write privileged spr %d %03x at "
4043 ADDRX "\n", sprn, sprn, ctx->nip);
f24e5695 4044 }
077fc206
JM		 4045 printf("Trying to write privileged spr %d %03x at " ADDRX "\n",
4046 sprn, sprn, ctx->nip);
e06fcd75 4047 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
76a66253 4048 }
3fc6c082
FB		 4049 } else {
4050 /* Not defined */
4a057712 4051 if (loglevel != 0) {
077fc206
JM		 4052 fprintf(logfile, "Trying to write invalid spr %d %03x at "
4053 ADDRX "\n", sprn, sprn, ctx->nip);
f24e5695 4054 }
077fc206
JM		 4055 printf("Trying to write invalid spr %d %03x at " ADDRX "\n",
4056 sprn, sprn, ctx->nip);
e06fcd75 4057 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
79aceca5 4058 }
79aceca5
FB		 4059}
4060
4061/*** Cache management ***/
79aceca5 4062/* dcbf */
0db1b20e 4063GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE)
79aceca5 4064{
dac454af 4065 /* XXX: specification says this is treated as a load by the MMU */
76db3ba4
AJ		 4066 TCGv t0;
4067 gen_set_access_type(ctx, ACCESS_CACHE);
4068 t0 = tcg_temp_new();
4069 gen_addr_reg_index(ctx, t0);
4070 gen_qemu_ld8u(ctx, t0, t0);
fea0c503 4071 tcg_temp_free(t0);
79aceca5
FB		 4072}
4073
4074/* dcbi (Supervisor only) */
9a64fbe4 4075GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE)
79aceca5 4076{
a541f297 4077#if defined(CONFIG_USER_ONLY)
e06fcd75 4078 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
a541f297 4079#else
b61f2753 4080 TCGv EA, val;
76db3ba4 4081 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4082 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9fddaa0c 4083 return;
9a64fbe4 4084 }
a7812ae4 4085 EA = tcg_temp_new();
76db3ba4
AJ		 4086 gen_set_access_type(ctx, ACCESS_CACHE);
4087 gen_addr_reg_index(ctx, EA);
a7812ae4 4088 val = tcg_temp_new();
76a66253 4089 /* XXX: specification says this should be treated as a store by the MMU */
76db3ba4
AJ		 4090 gen_qemu_ld8u(ctx, val, EA);
4091 gen_qemu_st8(ctx, val, EA);
b61f2753
AJ		 4092 tcg_temp_free(val);
4093 tcg_temp_free(EA);
a541f297 4094#endif
79aceca5
FB		 4095}
4096
4097/* dcdst */
9a64fbe4 4098GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE)
79aceca5 4099{
76a66253 4100 /* XXX: specification say this is treated as a load by the MMU */
76db3ba4
AJ		 4101 TCGv t0;
4102 gen_set_access_type(ctx, ACCESS_CACHE);
4103 t0 = tcg_temp_new();
4104 gen_addr_reg_index(ctx, t0);
4105 gen_qemu_ld8u(ctx, t0, t0);
fea0c503 4106 tcg_temp_free(t0);
79aceca5
FB		 4107}
4108
4109/* dcbt */
0db1b20e 4110GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE)
79aceca5 4111{
0db1b20e 4112 /* interpreted as no-op */
76a66253
JM		 4113 /* XXX: specification say this is treated as a load by the MMU
4114 * but does not generate any exception
4115 */
79aceca5
FB		 4116}
4117
4118/* dcbtst */
0db1b20e 4119GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE)
79aceca5 4120{
0db1b20e 4121 /* interpreted as no-op */
76a66253
JM		 4122 /* XXX: specification say this is treated as a load by the MMU
4123 * but does not generate any exception
4124 */
79aceca5
FB		 4125}
4126
4127/* dcbz */
d63001d1 4128GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE_DCBZ)
79aceca5 4129{
76db3ba4
AJ		 4130 TCGv t0;
4131 gen_set_access_type(ctx, ACCESS_CACHE);
799a8c8d
AJ		 4132 /* NIP cannot be restored if the memory exception comes from an helper */
4133 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 4134 t0 = tcg_temp_new();
4135 gen_addr_reg_index(ctx, t0);
799a8c8d
AJ		 4136 gen_helper_dcbz(t0);
4137 tcg_temp_free(t0);
d63001d1
JM		 4138}
4139
c7697e1f 4140GEN_HANDLER2(dcbz_970, "dcbz", 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZT)
d63001d1 4141{
76db3ba4
AJ		 4142 TCGv t0;
4143 gen_set_access_type(ctx, ACCESS_CACHE);
799a8c8d
AJ		 4144 /* NIP cannot be restored if the memory exception comes from an helper */
4145 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 4146 t0 = tcg_temp_new();
4147 gen_addr_reg_index(ctx, t0);
d63001d1 4148 if (ctx->opcode & 0x00200000)
799a8c8d 4149 gen_helper_dcbz(t0);
d63001d1 4150 else
799a8c8d
AJ		 4151 gen_helper_dcbz_970(t0);
4152 tcg_temp_free(t0);
79aceca5
FB		 4153}
4154
4155/* icbi */
1b413d55 4156GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI)
79aceca5 4157{
76db3ba4
AJ		 4158 TCGv t0;
4159 gen_set_access_type(ctx, ACCESS_CACHE);
30032c94
JM		 4160 /* NIP cannot be restored if the memory exception comes from an helper */
4161 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 4162 t0 = tcg_temp_new();
4163 gen_addr_reg_index(ctx, t0);
37d269df
AJ		 4164 gen_helper_icbi(t0);
4165 tcg_temp_free(t0);
79aceca5
FB		 4166}
4167
4168/* Optional: */
4169/* dcba */
a750fc0b 4170GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA)
79aceca5 4171{
0db1b20e
JM		 4172 /* interpreted as no-op */
4173 /* XXX: specification say this is treated as a store by the MMU
4174 * but does not generate any exception
4175 */
79aceca5
FB		 4176}
4177
4178/*** Segment register manipulation ***/
4179/* Supervisor only: */
4180/* mfsr */
4181GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT)
4182{
9a64fbe4 4183#if defined(CONFIG_USER_ONLY)
e06fcd75 4184 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9a64fbe4 4185#else
74d37793 4186 TCGv t0;
76db3ba4 4187 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4188 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9fddaa0c 4189 return;
9a64fbe4 4190 }
74d37793
AJ		 4191 t0 = tcg_const_tl(SR(ctx->opcode));
4192 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0);
4193 tcg_temp_free(t0);
9a64fbe4 4194#endif
79aceca5
FB		 4195}
4196
4197/* mfsrin */
9a64fbe4 4198GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT)
79aceca5 4199{
9a64fbe4 4200#if defined(CONFIG_USER_ONLY)
e06fcd75 4201 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9a64fbe4 4202#else
74d37793 4203 TCGv t0;
76db3ba4 4204 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4205 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9fddaa0c 4206 return;
9a64fbe4 4207 }
74d37793
AJ		 4208 t0 = tcg_temp_new();
4209 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4210 tcg_gen_andi_tl(t0, t0, 0xF);
4211 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0);
4212 tcg_temp_free(t0);
9a64fbe4 4213#endif
79aceca5
FB		 4214}
4215
4216/* mtsr */
e63c59cb 4217GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT)
79aceca5 4218{
9a64fbe4 4219#if defined(CONFIG_USER_ONLY)
e06fcd75 4220 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9a64fbe4 4221#else
74d37793 4222 TCGv t0;
76db3ba4 4223 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4224 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9fddaa0c 4225 return;
9a64fbe4 4226 }
74d37793
AJ		 4227 t0 = tcg_const_tl(SR(ctx->opcode));
4228 gen_helper_store_sr(t0, cpu_gpr[rS(ctx->opcode)]);
4229 tcg_temp_free(t0);
9a64fbe4 4230#endif
79aceca5
FB		 4231}
4232
4233/* mtsrin */
9a64fbe4 4234GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT)
79aceca5 4235{
9a64fbe4 4236#if defined(CONFIG_USER_ONLY)
e06fcd75 4237 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9a64fbe4 4238#else
74d37793 4239 TCGv t0;
76db3ba4 4240 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4241 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9fddaa0c 4242 return;
9a64fbe4 4243 }
74d37793
AJ		 4244 t0 = tcg_temp_new();
4245 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4246 tcg_gen_andi_tl(t0, t0, 0xF);
4247 gen_helper_store_sr(t0, cpu_gpr[rD(ctx->opcode)]);
4248 tcg_temp_free(t0);
9a64fbe4 4249#endif
79aceca5
FB		 4250}
4251
12de9a39
JM		 4252#if defined(TARGET_PPC64)
4253/* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4254/* mfsr */
c7697e1f 4255GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B)
12de9a39
JM		 4256{
4257#if defined(CONFIG_USER_ONLY)
e06fcd75 4258 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39 4259#else
74d37793 4260 TCGv t0;
76db3ba4 4261 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4262 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39
JM		 4263 return;
4264 }
74d37793
AJ		 4265 t0 = tcg_const_tl(SR(ctx->opcode));
4266 gen_helper_load_slb(cpu_gpr[rD(ctx->opcode)], t0);
4267 tcg_temp_free(t0);
12de9a39
JM		 4268#endif
4269}
4270
4271/* mfsrin */
c7697e1f
JM		 4272GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
4273 PPC_SEGMENT_64B)
12de9a39
JM		 4274{
4275#if defined(CONFIG_USER_ONLY)
e06fcd75 4276 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39 4277#else
74d37793 4278 TCGv t0;
76db3ba4 4279 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4280 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39
JM		 4281 return;
4282 }
74d37793
AJ		 4283 t0 = tcg_temp_new();
4284 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4285 tcg_gen_andi_tl(t0, t0, 0xF);
4286 gen_helper_load_slb(cpu_gpr[rD(ctx->opcode)], t0);
4287 tcg_temp_free(t0);
12de9a39
JM		 4288#endif
4289}
4290
4291/* mtsr */
c7697e1f 4292GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B)
12de9a39
JM		 4293{
4294#if defined(CONFIG_USER_ONLY)
e06fcd75 4295 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39 4296#else
74d37793 4297 TCGv t0;
76db3ba4 4298 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4299 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39
JM		 4300 return;
4301 }
74d37793
AJ		 4302 t0 = tcg_const_tl(SR(ctx->opcode));
4303 gen_helper_store_slb(t0, cpu_gpr[rS(ctx->opcode)]);
4304 tcg_temp_free(t0);
12de9a39
JM		 4305#endif
4306}
4307
4308/* mtsrin */
c7697e1f
JM		 4309GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
4310 PPC_SEGMENT_64B)
12de9a39
JM		 4311{
4312#if defined(CONFIG_USER_ONLY)
e06fcd75 4313 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39 4314#else
74d37793 4315 TCGv t0;
76db3ba4 4316 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4317 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39
JM		 4318 return;
4319 }
74d37793
AJ		 4320 t0 = tcg_temp_new();
4321 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4322 tcg_gen_andi_tl(t0, t0, 0xF);
4323 gen_helper_store_slb(t0, cpu_gpr[rS(ctx->opcode)]);
4324 tcg_temp_free(t0);
12de9a39
JM		 4325#endif
4326}
4327#endif /* defined(TARGET_PPC64) */
4328
79aceca5 4329/*** Lookaside buffer management ***/
76db3ba4 4330/* Optional & mem_idx only: */
79aceca5 4331/* tlbia */
3fc6c082 4332GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA)
79aceca5 4333{
9a64fbe4 4334#if defined(CONFIG_USER_ONLY)
e06fcd75 4335 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9a64fbe4 4336#else
76db3ba4 4337 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4338 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9fddaa0c 4339 return;
9a64fbe4 4340 }
74d37793 4341 gen_helper_tlbia();
9a64fbe4 4342#endif
79aceca5
FB		 4343}
4344
4345/* tlbie */
76a66253 4346GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE)
79aceca5 4347{
9a64fbe4 4348#if defined(CONFIG_USER_ONLY)
e06fcd75 4349 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9a64fbe4 4350#else
76db3ba4 4351 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4352 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9fddaa0c 4353 return;
9a64fbe4 4354 }
d9bce9d9 4355#if defined(TARGET_PPC64)
74d37793
AJ		 4356 if (!ctx->sf_mode) {
4357 TCGv t0 = tcg_temp_new();
4358 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
4359 gen_helper_tlbie(t0);
4360 tcg_temp_free(t0);
4361 } else
d9bce9d9 4362#endif
74d37793 4363 gen_helper_tlbie(cpu_gpr[rB(ctx->opcode)]);
9a64fbe4 4364#endif
79aceca5
FB		 4365}
4366
4367/* tlbsync */
76a66253 4368GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC)
79aceca5 4369{
9a64fbe4 4370#if defined(CONFIG_USER_ONLY)
e06fcd75 4371 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9a64fbe4 4372#else
76db3ba4 4373 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4374 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9fddaa0c 4375 return;
9a64fbe4
FB		 4376 }
4377 /* This has no effect: it should ensure that all previous
4378 * tlbie have completed
4379 */
e06fcd75 4380 gen_stop_exception(ctx);
9a64fbe4 4381#endif
79aceca5
FB		 4382}
4383
426613db
JM		 4384#if defined(TARGET_PPC64)
4385/* slbia */
4386GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI)
4387{
4388#if defined(CONFIG_USER_ONLY)
e06fcd75 4389 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
426613db 4390#else
76db3ba4 4391 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4392 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
426613db
JM		 4393 return;
4394 }
74d37793 4395 gen_helper_slbia();
426613db
JM		 4396#endif
4397}
4398
4399/* slbie */
4400GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI)
4401{
4402#if defined(CONFIG_USER_ONLY)
e06fcd75 4403 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
426613db 4404#else
76db3ba4 4405 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4406 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
426613db
JM		 4407 return;
4408 }
74d37793 4409 gen_helper_slbie(cpu_gpr[rB(ctx->opcode)]);
426613db
JM		 4410#endif
4411}
4412#endif
4413
79aceca5
FB		 4414/*** External control ***/
4415/* Optional: */
111bfab3 4416/* eciwx */
79aceca5
FB		 4417GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN)
4418{
76db3ba4 4419 TCGv t0;
fa407c03 4420 /* Should check EAR[E] ! */
76db3ba4
AJ		 4421 gen_set_access_type(ctx, ACCESS_EXT);
4422 t0 = tcg_temp_new();
4423 gen_addr_reg_index(ctx, t0);
fa407c03 4424 gen_check_align(ctx, t0, 0x03);
76db3ba4 4425 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
fa407c03 4426 tcg_temp_free(t0);
76a66253
JM		 4427}
4428
4429/* ecowx */
4430GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN)
4431{
76db3ba4 4432 TCGv t0;
fa407c03 4433 /* Should check EAR[E] ! */
76db3ba4
AJ		 4434 gen_set_access_type(ctx, ACCESS_EXT);
4435 t0 = tcg_temp_new();
4436 gen_addr_reg_index(ctx, t0);
fa407c03 4437 gen_check_align(ctx, t0, 0x03);
76db3ba4 4438 gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0);
fa407c03 4439 tcg_temp_free(t0);
76a66253
JM		 4440}
4441
4442/* PowerPC 601 specific instructions */
4443/* abs - abs. */
4444GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR)
4445{
22e0e173
AJ		 4446 int l1 = gen_new_label();
4447 int l2 = gen_new_label();
4448 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
4449 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4450 tcg_gen_br(l2);
4451 gen_set_label(l1);
4452 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4453 gen_set_label(l2);
76a66253 4454 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4455 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4456}
4457
4458/* abso - abso. */
4459GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR)
4460{
22e0e173
AJ		 4461 int l1 = gen_new_label();
4462 int l2 = gen_new_label();
4463 int l3 = gen_new_label();
4464 /* Start with XER OV disabled, the most likely case */
4465 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4466 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
4467 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
4468 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
4469 tcg_gen_br(l2);
4470 gen_set_label(l1);
4471 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4472 tcg_gen_br(l3);
4473 gen_set_label(l2);
4474 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4475 gen_set_label(l3);
76a66253 4476 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4477 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4478}
4479
4480/* clcs */
a750fc0b 4481GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR)
76a66253 4482{
22e0e173
AJ		 4483 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
4484 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], t0);
4485 tcg_temp_free_i32(t0);
c7697e1f 4486 /* Rc=1 sets CR0 to an undefined state */
76a66253
JM		 4487}
4488
4489/* div - div. */
4490GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR)
4491{
22e0e173 4492 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
76a66253 4493 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4494 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4495}
4496
4497/* divo - divo. */
4498GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR)
4499{
22e0e173 4500 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
76a66253 4501 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4502 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4503}
4504
4505/* divs - divs. */
4506GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR)
4507{
22e0e173 4508 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
76a66253 4509 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4510 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4511}
4512
4513/* divso - divso. */
4514GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR)
4515{
22e0e173 4516 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
76a66253 4517 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4518 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4519}
4520
4521/* doz - doz. */
4522GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR)
4523{
22e0e173
AJ		 4524 int l1 = gen_new_label();
4525 int l2 = gen_new_label();
4526 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4527 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4528 tcg_gen_br(l2);
4529 gen_set_label(l1);
4530 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4531 gen_set_label(l2);
76a66253 4532 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4533 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4534}
4535
4536/* dozo - dozo. */
4537GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR)
4538{
22e0e173
AJ		 4539 int l1 = gen_new_label();
4540 int l2 = gen_new_label();
4541 TCGv t0 = tcg_temp_new();
4542 TCGv t1 = tcg_temp_new();
4543 TCGv t2 = tcg_temp_new();
4544 /* Start with XER OV disabled, the most likely case */
4545 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4546 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4547 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4548 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4549 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
4550 tcg_gen_andc_tl(t1, t1, t2);
4551 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
4552 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4553 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
4554 tcg_gen_br(l2);
4555 gen_set_label(l1);
4556 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4557 gen_set_label(l2);
4558 tcg_temp_free(t0);
4559 tcg_temp_free(t1);
4560 tcg_temp_free(t2);
76a66253 4561 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4562 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4563}
4564
4565/* dozi */
4566GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
4567{
22e0e173
AJ		 4568 target_long simm = SIMM(ctx->opcode);
4569 int l1 = gen_new_label();
4570 int l2 = gen_new_label();
4571 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
4572 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
4573 tcg_gen_br(l2);
4574 gen_set_label(l1);
4575 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4576 gen_set_label(l2);
4577 if (unlikely(Rc(ctx->opcode) != 0))
4578 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4579}
4580
76a66253
JM		 4581/* lscbx - lscbx. */
4582GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR)
4583{
bdb4b689
AJ		 4584 TCGv t0 = tcg_temp_new();
4585 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
4586 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
4587 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
76a66253 4588
76db3ba4 4589 gen_addr_reg_index(ctx, t0);
76a66253 4590 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 4591 gen_update_nip(ctx, ctx->nip - 4);
bdb4b689
AJ		 4592 gen_helper_lscbx(t0, t0, t1, t2, t3);
4593 tcg_temp_free_i32(t1);
4594 tcg_temp_free_i32(t2);
4595 tcg_temp_free_i32(t3);
3d7b417e 4596 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
bdb4b689 4597 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
76a66253 4598 if (unlikely(Rc(ctx->opcode) != 0))
bdb4b689
AJ		 4599 gen_set_Rc0(ctx, t0);
4600 tcg_temp_free(t0);
76a66253
JM		 4601}
4602
4603/* maskg - maskg. */
4604GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR)
4605{
22e0e173
AJ		 4606 int l1 = gen_new_label();
4607 TCGv t0 = tcg_temp_new();
4608 TCGv t1 = tcg_temp_new();
4609 TCGv t2 = tcg_temp_new();
4610 TCGv t3 = tcg_temp_new();
4611 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
4612 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4613 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
4614 tcg_gen_addi_tl(t2, t0, 1);
4615 tcg_gen_shr_tl(t2, t3, t2);
4616 tcg_gen_shr_tl(t3, t3, t1);
4617 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
4618 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
4619 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4620 gen_set_label(l1);
4621 tcg_temp_free(t0);
4622 tcg_temp_free(t1);
4623 tcg_temp_free(t2);
4624 tcg_temp_free(t3);
76a66253 4625 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4626 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4627}
4628
4629/* maskir - maskir. */
4630GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR)
4631{
22e0e173
AJ		 4632 TCGv t0 = tcg_temp_new();
4633 TCGv t1 = tcg_temp_new();
4634 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4635 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4636 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4637 tcg_temp_free(t0);
4638 tcg_temp_free(t1);
76a66253 4639 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4640 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4641}
4642
4643/* mul - mul. */
4644GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR)
4645{
22e0e173
AJ		 4646 TCGv_i64 t0 = tcg_temp_new_i64();
4647 TCGv_i64 t1 = tcg_temp_new_i64();
4648 TCGv t2 = tcg_temp_new();
4649 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4650 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4651 tcg_gen_mul_i64(t0, t0, t1);
4652 tcg_gen_trunc_i64_tl(t2, t0);
4653 gen_store_spr(SPR_MQ, t2);
4654 tcg_gen_shri_i64(t1, t0, 32);
4655 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4656 tcg_temp_free_i64(t0);
4657 tcg_temp_free_i64(t1);
4658 tcg_temp_free(t2);
76a66253 4659 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4660 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4661}
4662
4663/* mulo - mulo. */
4664GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR)
4665{
22e0e173
AJ		 4666 int l1 = gen_new_label();
4667 TCGv_i64 t0 = tcg_temp_new_i64();
4668 TCGv_i64 t1 = tcg_temp_new_i64();
4669 TCGv t2 = tcg_temp_new();
4670 /* Start with XER OV disabled, the most likely case */
4671 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4672 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4673 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4674 tcg_gen_mul_i64(t0, t0, t1);
4675 tcg_gen_trunc_i64_tl(t2, t0);
4676 gen_store_spr(SPR_MQ, t2);
4677 tcg_gen_shri_i64(t1, t0, 32);
4678 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4679 tcg_gen_ext32s_i64(t1, t0);
4680 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
4681 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
4682 gen_set_label(l1);
4683 tcg_temp_free_i64(t0);
4684 tcg_temp_free_i64(t1);
4685 tcg_temp_free(t2);
76a66253 4686 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4687 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4688}
4689
4690/* nabs - nabs. */
4691GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR)
4692{
22e0e173
AJ		 4693 int l1 = gen_new_label();
4694 int l2 = gen_new_label();
4695 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4696 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4697 tcg_gen_br(l2);
4698 gen_set_label(l1);
4699 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4700 gen_set_label(l2);
76a66253 4701 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4702 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4703}
4704
4705/* nabso - nabso. */
4706GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR)
4707{
22e0e173
AJ		 4708 int l1 = gen_new_label();
4709 int l2 = gen_new_label();
4710 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4711 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4712 tcg_gen_br(l2);
4713 gen_set_label(l1);
4714 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4715 gen_set_label(l2);
4716 /* nabs never overflows */
4717 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
76a66253 4718 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4719 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4720}
4721
4722/* rlmi - rlmi. */
4723GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
4724{
7487953d
AJ		 4725 uint32_t mb = MB(ctx->opcode);
4726 uint32_t me = ME(ctx->opcode);
4727 TCGv t0 = tcg_temp_new();
4728 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4729 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4730 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
4731 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
4732 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
4733 tcg_temp_free(t0);
76a66253 4734 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4735 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4736}
4737
4738/* rrib - rrib. */
4739GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR)
4740{
7487953d
AJ		 4741 TCGv t0 = tcg_temp_new();
4742 TCGv t1 = tcg_temp_new();
4743 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4744 tcg_gen_movi_tl(t1, 0x80000000);
4745 tcg_gen_shr_tl(t1, t1, t0);
4746 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4747 tcg_gen_and_tl(t0, t0, t1);
4748 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
4749 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4750 tcg_temp_free(t0);
4751 tcg_temp_free(t1);
76a66253 4752 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4753 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4754}
4755
4756/* sle - sle. */
4757GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR)
4758{
7487953d
AJ		 4759 TCGv t0 = tcg_temp_new();
4760 TCGv t1 = tcg_temp_new();
4761 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4762 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4763 tcg_gen_subfi_tl(t1, 32, t1);
4764 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4765 tcg_gen_or_tl(t1, t0, t1);
4766 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4767 gen_store_spr(SPR_MQ, t1);
4768 tcg_temp_free(t0);
4769 tcg_temp_free(t1);
76a66253 4770 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4771 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4772}
4773
4774/* sleq - sleq. */
4775GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR)
4776{
7487953d
AJ		 4777 TCGv t0 = tcg_temp_new();
4778 TCGv t1 = tcg_temp_new();
4779 TCGv t2 = tcg_temp_new();
4780 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4781 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
4782 tcg_gen_shl_tl(t2, t2, t0);
4783 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4784 gen_load_spr(t1, SPR_MQ);
4785 gen_store_spr(SPR_MQ, t0);
4786 tcg_gen_and_tl(t0, t0, t2);
4787 tcg_gen_andc_tl(t1, t1, t2);
4788 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4789 tcg_temp_free(t0);
4790 tcg_temp_free(t1);
4791 tcg_temp_free(t2);
76a66253 4792 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4793 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4794}
4795
4796/* sliq - sliq. */
4797GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR)
4798{
7487953d
AJ		 4799 int sh = SH(ctx->opcode);
4800 TCGv t0 = tcg_temp_new();
4801 TCGv t1 = tcg_temp_new();
4802 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4803 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4804 tcg_gen_or_tl(t1, t0, t1);
4805 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4806 gen_store_spr(SPR_MQ, t1);
4807 tcg_temp_free(t0);
4808 tcg_temp_free(t1);
76a66253 4809 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4810 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4811}
4812
4813/* slliq - slliq. */
4814GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR)
4815{
7487953d
AJ		 4816 int sh = SH(ctx->opcode);
4817 TCGv t0 = tcg_temp_new();
4818 TCGv t1 = tcg_temp_new();
4819 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4820 gen_load_spr(t1, SPR_MQ);
4821 gen_store_spr(SPR_MQ, t0);
4822 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
4823 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
4824 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4825 tcg_temp_free(t0);
4826 tcg_temp_free(t1);
76a66253 4827 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4828 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4829}
4830
4831/* sllq - sllq. */
4832GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR)
4833{
7487953d
AJ		 4834 int l1 = gen_new_label();
4835 int l2 = gen_new_label();
4836 TCGv t0 = tcg_temp_local_new();
4837 TCGv t1 = tcg_temp_local_new();
4838 TCGv t2 = tcg_temp_local_new();
4839 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4840 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
4841 tcg_gen_shl_tl(t1, t1, t2);
4842 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4843 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
4844 gen_load_spr(t0, SPR_MQ);
4845 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4846 tcg_gen_br(l2);
4847 gen_set_label(l1);
4848 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4849 gen_load_spr(t2, SPR_MQ);
4850 tcg_gen_andc_tl(t1, t2, t1);
4851 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4852 gen_set_label(l2);
4853 tcg_temp_free(t0);
4854 tcg_temp_free(t1);
4855 tcg_temp_free(t2);
76a66253 4856 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4857 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4858}
4859
4860/* slq - slq. */
4861GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR)
4862{
7487953d
AJ		 4863 int l1 = gen_new_label();
4864 TCGv t0 = tcg_temp_new();
4865 TCGv t1 = tcg_temp_new();
4866 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4867 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4868 tcg_gen_subfi_tl(t1, 32, t1);
4869 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4870 tcg_gen_or_tl(t1, t0, t1);
4871 gen_store_spr(SPR_MQ, t1);
4872 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
4873 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4874 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4875 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
4876 gen_set_label(l1);
4877 tcg_temp_free(t0);
4878 tcg_temp_free(t1);
76a66253 4879 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4880 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4881}
4882
d9bce9d9 4883/* sraiq - sraiq. */
76a66253
JM		 4884GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR)
4885{
7487953d
AJ		 4886 int sh = SH(ctx->opcode);
4887 int l1 = gen_new_label();
4888 TCGv t0 = tcg_temp_new();
4889 TCGv t1 = tcg_temp_new();
4890 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4891 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4892 tcg_gen_or_tl(t0, t0, t1);
4893 gen_store_spr(SPR_MQ, t0);
4894 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
4895 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4896 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
4897 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_CA));
4898 gen_set_label(l1);
4899 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
4900 tcg_temp_free(t0);
4901 tcg_temp_free(t1);
76a66253 4902 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4903 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4904}
4905
4906/* sraq - sraq. */
4907GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR)
4908{
7487953d
AJ		 4909 int l1 = gen_new_label();
4910 int l2 = gen_new_label();
4911 TCGv t0 = tcg_temp_new();
4912 TCGv t1 = tcg_temp_local_new();
4913 TCGv t2 = tcg_temp_local_new();
4914 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4915 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4916 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
4917 tcg_gen_subfi_tl(t2, 32, t2);
4918 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
4919 tcg_gen_or_tl(t0, t0, t2);
4920 gen_store_spr(SPR_MQ, t0);
4921 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4922 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
4923 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
4924 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
4925 gen_set_label(l1);
4926 tcg_temp_free(t0);
4927 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
4928 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
4929 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4930 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
4931 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_CA));
4932 gen_set_label(l2);
4933 tcg_temp_free(t1);
4934 tcg_temp_free(t2);
76a66253 4935 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4936 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4937}
4938
4939/* sre - sre. */
4940GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR)
4941{
7487953d
AJ		 4942 TCGv t0 = tcg_temp_new();
4943 TCGv t1 = tcg_temp_new();
4944 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4945 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4946 tcg_gen_subfi_tl(t1, 32, t1);
4947 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4948 tcg_gen_or_tl(t1, t0, t1);
4949 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4950 gen_store_spr(SPR_MQ, t1);
4951 tcg_temp_free(t0);
4952 tcg_temp_free(t1);
76a66253 4953 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4954 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4955}
4956
4957/* srea - srea. */
4958GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR)
4959{
7487953d
AJ		 4960 TCGv t0 = tcg_temp_new();
4961 TCGv t1 = tcg_temp_new();
4962 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4963 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4964 gen_store_spr(SPR_MQ, t0);
4965 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
4966 tcg_temp_free(t0);
4967 tcg_temp_free(t1);
76a66253 4968 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4969 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4970}
4971
4972/* sreq */
4973GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR)
4974{
7487953d
AJ		 4975 TCGv t0 = tcg_temp_new();
4976 TCGv t1 = tcg_temp_new();
4977 TCGv t2 = tcg_temp_new();
4978 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4979 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
4980 tcg_gen_shr_tl(t1, t1, t0);
4981 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4982 gen_load_spr(t2, SPR_MQ);
4983 gen_store_spr(SPR_MQ, t0);
4984 tcg_gen_and_tl(t0, t0, t1);
4985 tcg_gen_andc_tl(t2, t2, t1);
4986 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
4987 tcg_temp_free(t0);
4988 tcg_temp_free(t1);
4989 tcg_temp_free(t2);
76a66253 4990 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4991 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4992}
4993
4994/* sriq */
4995GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR)
4996{
7487953d
AJ		 4997 int sh = SH(ctx->opcode);
4998 TCGv t0 = tcg_temp_new();
4999 TCGv t1 = tcg_temp_new();
5000 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5001 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5002 tcg_gen_or_tl(t1, t0, t1);
5003 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5004 gen_store_spr(SPR_MQ, t1);
5005 tcg_temp_free(t0);
5006 tcg_temp_free(t1);
76a66253 5007 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5008 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5009}
5010
5011/* srliq */
5012GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR)
5013{
7487953d
AJ		 5014 int sh = SH(ctx->opcode);
5015 TCGv t0 = tcg_temp_new();
5016 TCGv t1 = tcg_temp_new();
5017 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5018 gen_load_spr(t1, SPR_MQ);
5019 gen_store_spr(SPR_MQ, t0);
5020 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
5021 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
5022 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5023 tcg_temp_free(t0);
5024 tcg_temp_free(t1);
76a66253 5025 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5026 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5027}
5028
5029/* srlq */
5030GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR)
5031{
7487953d
AJ		 5032 int l1 = gen_new_label();
5033 int l2 = gen_new_label();
5034 TCGv t0 = tcg_temp_local_new();
5035 TCGv t1 = tcg_temp_local_new();
5036 TCGv t2 = tcg_temp_local_new();
5037 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5038 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5039 tcg_gen_shr_tl(t2, t1, t2);
5040 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5041 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5042 gen_load_spr(t0, SPR_MQ);
5043 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5044 tcg_gen_br(l2);
5045 gen_set_label(l1);
5046 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5047 tcg_gen_and_tl(t0, t0, t2);
5048 gen_load_spr(t1, SPR_MQ);
5049 tcg_gen_andc_tl(t1, t1, t2);
5050 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5051 gen_set_label(l2);
5052 tcg_temp_free(t0);
5053 tcg_temp_free(t1);
5054 tcg_temp_free(t2);
76a66253 5055 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5056 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5057}
5058
5059/* srq */
5060GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR)
5061{
7487953d
AJ		 5062 int l1 = gen_new_label();
5063 TCGv t0 = tcg_temp_new();
5064 TCGv t1 = tcg_temp_new();
5065 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5066 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5067 tcg_gen_subfi_tl(t1, 32, t1);
5068 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5069 tcg_gen_or_tl(t1, t0, t1);
5070 gen_store_spr(SPR_MQ, t1);
5071 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5072 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5073 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5074 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5075 gen_set_label(l1);
5076 tcg_temp_free(t0);
5077 tcg_temp_free(t1);
76a66253 5078 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5079 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5080}
5081
5082/* PowerPC 602 specific instructions */
5083/* dsa */
5084GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC)
5085{
5086 /* XXX: TODO */
e06fcd75 5087 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
76a66253
JM		 5088}
5089
5090/* esa */
5091GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC)
5092{
5093 /* XXX: TODO */
e06fcd75 5094 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
76a66253
JM		 5095}
5096
5097/* mfrom */
5098GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC)
5099{
5100#if defined(CONFIG_USER_ONLY)
e06fcd75 5101 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5102#else
76db3ba4 5103 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5104 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5105 return;
5106 }
cf02a65c 5107 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5108#endif
5109}
5110
5111/* 602 - 603 - G2 TLB management */
5112/* tlbld */
c7697e1f 5113GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB)
76a66253
JM		 5114{
5115#if defined(CONFIG_USER_ONLY)
e06fcd75 5116 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5117#else
76db3ba4 5118 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5119 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5120 return;
5121 }
74d37793 5122 gen_helper_6xx_tlbd(cpu_gpr[rB(ctx->opcode)]);
76a66253
JM		 5123#endif
5124}
5125
5126/* tlbli */
c7697e1f 5127GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB)
76a66253
JM		 5128{
5129#if defined(CONFIG_USER_ONLY)
e06fcd75 5130 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5131#else
76db3ba4 5132 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5133 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5134 return;
5135 }
74d37793 5136 gen_helper_6xx_tlbi(cpu_gpr[rB(ctx->opcode)]);
76a66253
JM		 5137#endif
5138}
5139
7dbe11ac
JM		 5140/* 74xx TLB management */
5141/* tlbld */
c7697e1f 5142GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB)
7dbe11ac
JM		 5143{
5144#if defined(CONFIG_USER_ONLY)
e06fcd75 5145 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
7dbe11ac 5146#else
76db3ba4 5147 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5148 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
7dbe11ac
JM		 5149 return;
5150 }
74d37793 5151 gen_helper_74xx_tlbd(cpu_gpr[rB(ctx->opcode)]);
7dbe11ac
JM		 5152#endif
5153}
5154
5155/* tlbli */
c7697e1f 5156GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB)
7dbe11ac
JM		 5157{
5158#if defined(CONFIG_USER_ONLY)
e06fcd75 5159 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
7dbe11ac 5160#else
76db3ba4 5161 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5162 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
7dbe11ac
JM		 5163 return;
5164 }
74d37793 5165 gen_helper_74xx_tlbi(cpu_gpr[rB(ctx->opcode)]);
7dbe11ac
JM		 5166#endif
5167}
5168
76a66253
JM		 5169/* POWER instructions not in PowerPC 601 */
5170/* clf */
5171GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER)
5172{
5173 /* Cache line flush: implemented as no-op */
5174}
5175
5176/* cli */
5177GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER)
5178{
7f75ffd3 5179 /* Cache line invalidate: privileged and treated as no-op */
76a66253 5180#if defined(CONFIG_USER_ONLY)
e06fcd75 5181 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5182#else
76db3ba4 5183 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5184 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5185 return;
5186 }
5187#endif
5188}
5189
5190/* dclst */
5191GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER)
5192{
5193 /* Data cache line store: treated as no-op */
5194}
5195
5196GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER)
5197{
5198#if defined(CONFIG_USER_ONLY)
e06fcd75 5199 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5200#else
74d37793
AJ		 5201 int ra = rA(ctx->opcode);
5202 int rd = rD(ctx->opcode);
5203 TCGv t0;
76db3ba4 5204 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5205 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5206 return;
5207 }
74d37793 5208 t0 = tcg_temp_new();
76db3ba4 5209 gen_addr_reg_index(ctx, t0);
74d37793
AJ		 5210 tcg_gen_shri_tl(t0, t0, 28);
5211 tcg_gen_andi_tl(t0, t0, 0xF);
5212 gen_helper_load_sr(cpu_gpr[rd], t0);
5213 tcg_temp_free(t0);
76a66253 5214 if (ra != 0 && ra != rd)
74d37793 5215 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
76a66253
JM		 5216#endif
5217}
5218
5219GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER)
5220{
5221#if defined(CONFIG_USER_ONLY)
e06fcd75 5222 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5223#else
22e0e173 5224 TCGv t0;
76db3ba4 5225 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5226 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5227 return;
5228 }
22e0e173 5229 t0 = tcg_temp_new();
76db3ba4 5230 gen_addr_reg_index(ctx, t0);
22e0e173
AJ		 5231 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], t0);
5232 tcg_temp_free(t0);
76a66253
JM		 5233#endif
5234}
5235
5236GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER)
5237{
5238#if defined(CONFIG_USER_ONLY)
e06fcd75 5239 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5240#else
76db3ba4 5241 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5242 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5243 return;
5244 }
d72a19f7 5245 gen_helper_rfsvc();
e06fcd75 5246 gen_sync_exception(ctx);
76a66253
JM		 5247#endif
5248}
5249
5250/* svc is not implemented for now */
5251
5252/* POWER2 specific instructions */
5253/* Quad manipulation (load/store two floats at a time) */
76a66253
JM		 5254
5255/* lfq */
5256GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5257{
01a4afeb 5258 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5259 TCGv t0;
5260 gen_set_access_type(ctx, ACCESS_FLOAT);
5261 t0 = tcg_temp_new();
5262 gen_addr_imm_index(ctx, t0, 0);
5263 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5264 gen_addr_add(ctx, t0, t0, 8);
5265 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
01a4afeb 5266 tcg_temp_free(t0);
76a66253
JM		 5267}
5268
5269/* lfqu */
5270GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5271{
5272 int ra = rA(ctx->opcode);
01a4afeb 5273 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5274 TCGv t0, t1;
5275 gen_set_access_type(ctx, ACCESS_FLOAT);
5276 t0 = tcg_temp_new();
5277 t1 = tcg_temp_new();
5278 gen_addr_imm_index(ctx, t0, 0);
5279 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5280 gen_addr_add(ctx, t1, t0, 8);
5281 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
76a66253 5282 if (ra != 0)
01a4afeb
AJ		 5283 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5284 tcg_temp_free(t0);
5285 tcg_temp_free(t1);
76a66253
JM		 5286}
5287
5288/* lfqux */
5289GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2)
5290{
5291 int ra = rA(ctx->opcode);
01a4afeb 5292 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5293 gen_set_access_type(ctx, ACCESS_FLOAT);
5294 TCGv t0, t1;
5295 t0 = tcg_temp_new();
5296 gen_addr_reg_index(ctx, t0);
5297 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5298 t1 = tcg_temp_new();
5299 gen_addr_add(ctx, t1, t0, 8);
5300 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5301 tcg_temp_free(t1);
76a66253 5302 if (ra != 0)
01a4afeb
AJ		 5303 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5304 tcg_temp_free(t0);
76a66253
JM		 5305}
5306
5307/* lfqx */
5308GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2)
5309{
01a4afeb 5310 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5311 TCGv t0;
5312 gen_set_access_type(ctx, ACCESS_FLOAT);
5313 t0 = tcg_temp_new();
5314 gen_addr_reg_index(ctx, t0);
5315 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5316 gen_addr_add(ctx, t0, t0, 8);
5317 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
01a4afeb 5318 tcg_temp_free(t0);
76a66253
JM		 5319}
5320
5321/* stfq */
5322GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5323{
01a4afeb 5324 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5325 TCGv t0;
5326 gen_set_access_type(ctx, ACCESS_FLOAT);
5327 t0 = tcg_temp_new();
5328 gen_addr_imm_index(ctx, t0, 0);
5329 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5330 gen_addr_add(ctx, t0, t0, 8);
5331 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
01a4afeb 5332 tcg_temp_free(t0);
76a66253
JM		 5333}
5334
5335/* stfqu */
5336GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5337{
5338 int ra = rA(ctx->opcode);
01a4afeb 5339 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5340 TCGv t0, t1;
5341 gen_set_access_type(ctx, ACCESS_FLOAT);
5342 t0 = tcg_temp_new();
5343 gen_addr_imm_index(ctx, t0, 0);
5344 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5345 t1 = tcg_temp_new();
5346 gen_addr_add(ctx, t1, t0, 8);
5347 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5348 tcg_temp_free(t1);
76a66253 5349 if (ra != 0)
01a4afeb
AJ		 5350 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5351 tcg_temp_free(t0);
76a66253
JM		 5352}
5353
5354/* stfqux */
5355GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2)
5356{
5357 int ra = rA(ctx->opcode);
01a4afeb 5358 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5359 TCGv t0, t1;
5360 gen_set_access_type(ctx, ACCESS_FLOAT);
5361 t0 = tcg_temp_new();
5362 gen_addr_reg_index(ctx, t0);
5363 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5364 t1 = tcg_temp_new();
5365 gen_addr_add(ctx, t1, t0, 8);
5366 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5367 tcg_temp_free(t1);
76a66253 5368 if (ra != 0)
01a4afeb
AJ		 5369 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5370 tcg_temp_free(t0);
76a66253
JM		 5371}
5372
5373/* stfqx */
5374GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2)
5375{
01a4afeb 5376 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5377 TCGv t0;
5378 gen_set_access_type(ctx, ACCESS_FLOAT);
5379 t0 = tcg_temp_new();
5380 gen_addr_reg_index(ctx, t0);
5381 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5382 gen_addr_add(ctx, t0, t0, 8);
5383 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
01a4afeb 5384 tcg_temp_free(t0);
76a66253
JM		 5385}
5386
5387/* BookE specific instructions */
2662a059 5388/* XXX: not implemented on 440 ? */
05332d70 5389GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI)
76a66253
JM		 5390{
5391 /* XXX: TODO */
e06fcd75 5392 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
76a66253
JM		 5393}
5394
2662a059 5395/* XXX: not implemented on 440 ? */
05332d70 5396GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA)
76a66253
JM		 5397{
5398#if defined(CONFIG_USER_ONLY)
e06fcd75 5399 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5400#else
74d37793 5401 TCGv t0;
76db3ba4 5402 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5403 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5404 return;
5405 }
ec72e276 5406 t0 = tcg_temp_new();
76db3ba4 5407 gen_addr_reg_index(ctx, t0);
74d37793
AJ		 5408 gen_helper_tlbie(cpu_gpr[rB(ctx->opcode)]);
5409 tcg_temp_free(t0);
76a66253
JM		 5410#endif
5411}
5412
5413/* All 405 MAC instructions are translated here */
b068d6a7
JM		 5414static always_inline void gen_405_mulladd_insn (DisasContext *ctx,
5415 int opc2, int opc3,
5416 int ra, int rb, int rt, int Rc)
76a66253 5417{
182608d4
AJ		 5418 TCGv t0, t1;
5419
a7812ae4
PB		 5420 t0 = tcg_temp_local_new();
5421 t1 = tcg_temp_local_new();
182608d4 5422
76a66253
JM		 5423 switch (opc3 & 0x0D) {
5424 case 0x05:
5425 /* macchw - macchw. - macchwo - macchwo. */
5426 /* macchws - macchws. - macchwso - macchwso. */
5427 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5428 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5429 /* mulchw - mulchw. */
182608d4
AJ		 5430 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5431 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5432 tcg_gen_ext16s_tl(t1, t1);
76a66253
JM		 5433 break;
5434 case 0x04:
5435 /* macchwu - macchwu. - macchwuo - macchwuo. */
5436 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5437 /* mulchwu - mulchwu. */
182608d4
AJ		 5438 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5439 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5440 tcg_gen_ext16u_tl(t1, t1);
76a66253
JM		 5441 break;
5442 case 0x01:
5443 /* machhw - machhw. - machhwo - machhwo. */
5444 /* machhws - machhws. - machhwso - machhwso. */
5445 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5446 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5447 /* mulhhw - mulhhw. */
182608d4
AJ		 5448 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5449 tcg_gen_ext16s_tl(t0, t0);
5450 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5451 tcg_gen_ext16s_tl(t1, t1);
76a66253
JM		 5452 break;
5453 case 0x00:
5454 /* machhwu - machhwu. - machhwuo - machhwuo. */
5455 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5456 /* mulhhwu - mulhhwu. */
182608d4
AJ		 5457 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5458 tcg_gen_ext16u_tl(t0, t0);
5459 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5460 tcg_gen_ext16u_tl(t1, t1);
76a66253
JM		 5461 break;
5462 case 0x0D:
5463 /* maclhw - maclhw. - maclhwo - maclhwo. */
5464 /* maclhws - maclhws. - maclhwso - maclhwso. */
5465 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5466 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5467 /* mullhw - mullhw. */
182608d4
AJ		 5468 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5469 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
76a66253
JM		 5470 break;
5471 case 0x0C:
5472 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5473 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5474 /* mullhwu - mullhwu. */
182608d4
AJ		 5475 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5476 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
76a66253
JM		 5477 break;
5478 }
76a66253 5479 if (opc2 & 0x04) {
182608d4
AJ		 5480 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5481 tcg_gen_mul_tl(t1, t0, t1);
5482 if (opc2 & 0x02) {
5483 /* nmultiply-and-accumulate (0x0E) */
5484 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
5485 } else {
5486 /* multiply-and-accumulate (0x0C) */
5487 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
5488 }
5489
5490 if (opc3 & 0x12) {
5491 /* Check overflow and/or saturate */
5492 int l1 = gen_new_label();
5493
5494 if (opc3 & 0x10) {
5495 /* Start with XER OV disabled, the most likely case */
5496 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
5497 }
5498 if (opc3 & 0x01) {
5499 /* Signed */
5500 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
5501 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
5502 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
5503 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
bdc4e053 5504 if (opc3 & 0x02) {
182608d4
AJ		 5505 /* Saturate */
5506 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
5507 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
5508 }
5509 } else {
5510 /* Unsigned */
5511 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
bdc4e053 5512 if (opc3 & 0x02) {
182608d4
AJ		 5513 /* Saturate */
5514 tcg_gen_movi_tl(t0, UINT32_MAX);
5515 }
5516 }
5517 if (opc3 & 0x10) {
5518 /* Check overflow */
5519 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
5520 }
5521 gen_set_label(l1);
5522 tcg_gen_mov_tl(cpu_gpr[rt], t0);
5523 }
5524 } else {
5525 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
76a66253 5526 }
182608d4
AJ		 5527 tcg_temp_free(t0);
5528 tcg_temp_free(t1);
76a66253
JM		 5529 if (unlikely(Rc) != 0) {
5530 /* Update Rc0 */
182608d4 5531 gen_set_Rc0(ctx, cpu_gpr[rt]);
76a66253
JM		 5532 }
5533}
5534
a750fc0b
JM		 5535#define GEN_MAC_HANDLER(name, opc2, opc3) \
5536GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) \
76a66253
JM		 5537{ \
5538 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5539 rD(ctx->opcode), Rc(ctx->opcode)); \
5540}
5541
5542/* macchw - macchw. */
a750fc0b 5543GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
76a66253 5544/* macchwo - macchwo. */
a750fc0b 5545GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
76a66253 5546/* macchws - macchws. */
a750fc0b 5547GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
76a66253 5548/* macchwso - macchwso. */
a750fc0b 5549GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
76a66253 5550/* macchwsu - macchwsu. */
a750fc0b 5551GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
76a66253 5552/* macchwsuo - macchwsuo. */
a750fc0b 5553GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
76a66253 5554/* macchwu - macchwu. */
a750fc0b 5555GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
76a66253 5556/* macchwuo - macchwuo. */
a750fc0b 5557GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
76a66253 5558/* machhw - machhw. */
a750fc0b 5559GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
76a66253 5560/* machhwo - machhwo. */
a750fc0b 5561GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
76a66253 5562/* machhws - machhws. */
a750fc0b 5563GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
76a66253 5564/* machhwso - machhwso. */
a750fc0b 5565GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
76a66253 5566/* machhwsu - machhwsu. */
a750fc0b 5567GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
76a66253 5568/* machhwsuo - machhwsuo. */
a750fc0b 5569GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
76a66253 5570/* machhwu - machhwu. */
a750fc0b 5571GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
76a66253 5572/* machhwuo - machhwuo. */
a750fc0b 5573GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
76a66253 5574/* maclhw - maclhw. */
a750fc0b 5575GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
76a66253 5576/* maclhwo - maclhwo. */
a750fc0b 5577GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
76a66253 5578/* maclhws - maclhws. */
a750fc0b 5579GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
76a66253 5580/* maclhwso - maclhwso. */
a750fc0b 5581GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
76a66253 5582/* maclhwu - maclhwu. */
a750fc0b 5583GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
76a66253 5584/* maclhwuo - maclhwuo. */
a750fc0b 5585GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
76a66253 5586/* maclhwsu - maclhwsu. */
a750fc0b 5587GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
76a66253 5588/* maclhwsuo - maclhwsuo. */
a750fc0b 5589GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
76a66253 5590/* nmacchw - nmacchw. */
a750fc0b 5591GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
76a66253 5592/* nmacchwo - nmacchwo. */
a750fc0b 5593GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
76a66253 5594/* nmacchws - nmacchws. */
a750fc0b 5595GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
76a66253 5596/* nmacchwso - nmacchwso. */
a750fc0b 5597GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
76a66253 5598/* nmachhw - nmachhw. */
a750fc0b 5599GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
76a66253 5600/* nmachhwo - nmachhwo. */
a750fc0b 5601GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
76a66253 5602/* nmachhws - nmachhws. */
a750fc0b 5603GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
76a66253 5604/* nmachhwso - nmachhwso. */
a750fc0b 5605GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
76a66253 5606/* nmaclhw - nmaclhw. */
a750fc0b 5607GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
76a66253 5608/* nmaclhwo - nmaclhwo. */
a750fc0b 5609GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
76a66253 5610/* nmaclhws - nmaclhws. */
a750fc0b 5611GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
76a66253 5612/* nmaclhwso - nmaclhwso. */
a750fc0b 5613GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
76a66253
JM		 5614
5615/* mulchw - mulchw. */
a750fc0b 5616GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
76a66253 5617/* mulchwu - mulchwu. */
a750fc0b 5618GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
76a66253 5619/* mulhhw - mulhhw. */
a750fc0b 5620GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
76a66253 5621/* mulhhwu - mulhhwu. */
a750fc0b 5622GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
76a66253 5623/* mullhw - mullhw. */
a750fc0b 5624GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
76a66253 5625/* mullhwu - mullhwu. */
a750fc0b 5626GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
76a66253
JM		 5627
5628/* mfdcr */
05332d70 5629GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR)
76a66253
JM		 5630{
5631#if defined(CONFIG_USER_ONLY)
e06fcd75 5632 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
76a66253 5633#else
06dca6a7 5634 TCGv dcrn;
76db3ba4 5635 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5636 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
76a66253
JM		 5637 return;
5638 }
06dca6a7
AJ		 5639 /* NIP cannot be restored if the memory exception comes from an helper */
5640 gen_update_nip(ctx, ctx->nip - 4);
5641 dcrn = tcg_const_tl(SPR(ctx->opcode));
5642 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], dcrn);
5643 tcg_temp_free(dcrn);
76a66253
JM		 5644#endif
5645}
5646
5647/* mtdcr */
05332d70 5648GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR)
76a66253
JM		 5649{
5650#if defined(CONFIG_USER_ONLY)
e06fcd75 5651 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
76a66253 5652#else
06dca6a7 5653 TCGv dcrn;
76db3ba4 5654 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5655 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
76a66253
JM		 5656 return;
5657 }
06dca6a7
AJ		 5658 /* NIP cannot be restored if the memory exception comes from an helper */
5659 gen_update_nip(ctx, ctx->nip - 4);
5660 dcrn = tcg_const_tl(SPR(ctx->opcode));
5661 gen_helper_store_dcr(dcrn, cpu_gpr[rS(ctx->opcode)]);
5662 tcg_temp_free(dcrn);
a42bd6cc
JM		 5663#endif
5664}
5665
5666/* mfdcrx */
2662a059 5667/* XXX: not implemented on 440 ? */
05332d70 5668GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX)
a42bd6cc
JM		 5669{
5670#if defined(CONFIG_USER_ONLY)
e06fcd75 5671 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
a42bd6cc 5672#else
76db3ba4 5673 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5674 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
a42bd6cc
JM		 5675 return;
5676 }
06dca6a7
AJ		 5677 /* NIP cannot be restored if the memory exception comes from an helper */
5678 gen_update_nip(ctx, ctx->nip - 4);
5679 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
a750fc0b 5680 /* Note: Rc update flag set leads to undefined state of Rc0 */
a42bd6cc
JM		 5681#endif
5682}
5683
5684/* mtdcrx */
2662a059 5685/* XXX: not implemented on 440 ? */
05332d70 5686GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX)
a42bd6cc
JM		 5687{
5688#if defined(CONFIG_USER_ONLY)
e06fcd75 5689 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
a42bd6cc 5690#else
76db3ba4 5691 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5692 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
a42bd6cc
JM		 5693 return;
5694 }
06dca6a7
AJ		 5695 /* NIP cannot be restored if the memory exception comes from an helper */
5696 gen_update_nip(ctx, ctx->nip - 4);
5697 gen_helper_store_dcr(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
a750fc0b 5698 /* Note: Rc update flag set leads to undefined state of Rc0 */
76a66253
JM		 5699#endif
5700}
5701
a750fc0b
JM		 5702/* mfdcrux (PPC 460) : user-mode access to DCR */
5703GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX)
5704{
06dca6a7
AJ		 5705 /* NIP cannot be restored if the memory exception comes from an helper */
5706 gen_update_nip(ctx, ctx->nip - 4);
5707 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
a750fc0b
JM		 5708 /* Note: Rc update flag set leads to undefined state of Rc0 */
5709}
5710
5711/* mtdcrux (PPC 460) : user-mode access to DCR */
5712GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX)
5713{
06dca6a7
AJ		 5714 /* NIP cannot be restored if the memory exception comes from an helper */
5715 gen_update_nip(ctx, ctx->nip - 4);
5716 gen_helper_store_dcr(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
a750fc0b
JM		 5717 /* Note: Rc update flag set leads to undefined state of Rc0 */
5718}
5719
76a66253
JM		 5720/* dccci */
5721GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON)
5722{
5723#if defined(CONFIG_USER_ONLY)
e06fcd75 5724 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5725#else
76db3ba4 5726 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5727 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5728 return;
5729 }
5730 /* interpreted as no-op */
5731#endif
5732}
5733
5734/* dcread */
5735GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON)
5736{
5737#if defined(CONFIG_USER_ONLY)
e06fcd75 5738 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5739#else
b61f2753 5740 TCGv EA, val;
76db3ba4 5741 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5742 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5743 return;
5744 }
76db3ba4 5745 gen_set_access_type(ctx, ACCESS_CACHE);
a7812ae4 5746 EA = tcg_temp_new();
76db3ba4 5747 gen_addr_reg_index(ctx, EA);
a7812ae4 5748 val = tcg_temp_new();
76db3ba4 5749 gen_qemu_ld32u(ctx, val, EA);
b61f2753
AJ		 5750 tcg_temp_free(val);
5751 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
5752 tcg_temp_free(EA);
76a66253
JM		 5753#endif
5754}
5755
5756/* icbt */
c7697e1f 5757GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT)
76a66253
JM		 5758{
5759 /* interpreted as no-op */
5760 /* XXX: specification say this is treated as a load by the MMU
5761 * but does not generate any exception
5762 */
5763}
5764
5765/* iccci */
5766GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON)
5767{
5768#if defined(CONFIG_USER_ONLY)
e06fcd75 5769 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5770#else
76db3ba4 5771 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5772 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5773 return;
5774 }
5775 /* interpreted as no-op */
5776#endif
5777}
5778
5779/* icread */
5780GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON)
5781{
5782#if defined(CONFIG_USER_ONLY)
e06fcd75 5783 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5784#else
76db3ba4 5785 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5786 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5787 return;
5788 }
5789 /* interpreted as no-op */
5790#endif
5791}
5792
76db3ba4 5793/* rfci (mem_idx only) */
c7697e1f 5794GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP)
a42bd6cc
JM		 5795{
5796#if defined(CONFIG_USER_ONLY)
e06fcd75 5797 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
a42bd6cc 5798#else
76db3ba4 5799 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5800 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
a42bd6cc
JM		 5801 return;
5802 }
5803 /* Restore CPU state */
d72a19f7 5804 gen_helper_40x_rfci();
e06fcd75 5805 gen_sync_exception(ctx);
a42bd6cc
JM		 5806#endif
5807}
5808
5809GEN_HANDLER(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE)
5810{
5811#if defined(CONFIG_USER_ONLY)
e06fcd75 5812 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
a42bd6cc 5813#else
76db3ba4 5814 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5815 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
a42bd6cc
JM		 5816 return;
5817 }
5818 /* Restore CPU state */
d72a19f7 5819 gen_helper_rfci();
e06fcd75 5820 gen_sync_exception(ctx);
a42bd6cc
JM		 5821#endif
5822}
5823
5824/* BookE specific */
2662a059 5825/* XXX: not implemented on 440 ? */
05332d70 5826GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI)
76a66253
JM		 5827{
5828#if defined(CONFIG_USER_ONLY)
e06fcd75 5829 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5830#else
76db3ba4 5831 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5832 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5833 return;
5834 }
5835 /* Restore CPU state */
d72a19f7 5836 gen_helper_rfdi();
e06fcd75 5837 gen_sync_exception(ctx);
76a66253
JM		 5838#endif
5839}
5840
2662a059 5841/* XXX: not implemented on 440 ? */
a750fc0b 5842GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI)
a42bd6cc
JM		 5843{
5844#if defined(CONFIG_USER_ONLY)
e06fcd75 5845 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
a42bd6cc 5846#else
76db3ba4 5847 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5848 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
a42bd6cc
JM		 5849 return;
5850 }
5851 /* Restore CPU state */
d72a19f7 5852 gen_helper_rfmci();
e06fcd75 5853 gen_sync_exception(ctx);
a42bd6cc
JM		 5854#endif
5855}
5eb7995e 5856
d9bce9d9 5857/* TLB management - PowerPC 405 implementation */
76a66253 5858/* tlbre */
c7697e1f 5859GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB)
76a66253
JM		 5860{
5861#if defined(CONFIG_USER_ONLY)
e06fcd75 5862 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5863#else
76db3ba4 5864 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5865 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5866 return;
5867 }
5868 switch (rB(ctx->opcode)) {
5869 case 0:
74d37793 5870 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5871 break;
5872 case 1:
74d37793 5873 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5874 break;
5875 default:
e06fcd75 5876 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
76a66253 5877 break;
9a64fbe4 5878 }
76a66253
JM		 5879#endif
5880}
5881
d9bce9d9 5882/* tlbsx - tlbsx. */
c7697e1f 5883GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB)
76a66253
JM		 5884{
5885#if defined(CONFIG_USER_ONLY)
e06fcd75 5886 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5887#else
74d37793 5888 TCGv t0;
76db3ba4 5889 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5890 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5891 return;
5892 }
74d37793 5893 t0 = tcg_temp_new();
76db3ba4 5894 gen_addr_reg_index(ctx, t0);
74d37793
AJ		 5895 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], t0);
5896 tcg_temp_free(t0);
5897 if (Rc(ctx->opcode)) {
5898 int l1 = gen_new_label();
5899 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
5900 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
5901 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
5902 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5903 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5904 gen_set_label(l1);
5905 }
76a66253 5906#endif
79aceca5
FB		 5907}
5908
76a66253 5909/* tlbwe */
c7697e1f 5910GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB)
79aceca5 5911{
76a66253 5912#if defined(CONFIG_USER_ONLY)
e06fcd75 5913 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5914#else
76db3ba4 5915 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5916 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5917 return;
5918 }
5919 switch (rB(ctx->opcode)) {
5920 case 0:
74d37793 5921 gen_helper_4xx_tlbwe_hi(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
76a66253
JM		 5922 break;
5923 case 1:
74d37793 5924 gen_helper_4xx_tlbwe_lo(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
76a66253
JM		 5925 break;
5926 default:
e06fcd75 5927 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
76a66253 5928 break;
9a64fbe4 5929 }
76a66253
JM		 5930#endif
5931}
5932
a4bb6c3e 5933/* TLB management - PowerPC 440 implementation */
5eb7995e 5934/* tlbre */
c7697e1f 5935GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE)
5eb7995e
JM		 5936{
5937#if defined(CONFIG_USER_ONLY)
e06fcd75 5938 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5eb7995e 5939#else
76db3ba4 5940 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5941 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5eb7995e
JM		 5942 return;
5943 }
5944 switch (rB(ctx->opcode)) {
5945 case 0:
5eb7995e 5946 case 1:
5eb7995e 5947 case 2:
74d37793
AJ		 5948 {
5949 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
5950 gen_helper_440_tlbwe(t0, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5951 tcg_temp_free_i32(t0);
5952 }
5eb7995e
JM		 5953 break;
5954 default:
e06fcd75 5955 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5eb7995e
JM		 5956 break;
5957 }
5958#endif
5959}
5960
5961/* tlbsx - tlbsx. */
c7697e1f 5962GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE)
5eb7995e
JM		 5963{
5964#if defined(CONFIG_USER_ONLY)
e06fcd75 5965 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5eb7995e 5966#else
74d37793 5967 TCGv t0;
76db3ba4 5968 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5969 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5eb7995e
JM		 5970 return;
5971 }
74d37793 5972 t0 = tcg_temp_new();
76db3ba4 5973 gen_addr_reg_index(ctx, t0);
74d37793
AJ		 5974 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], t0);
5975 tcg_temp_free(t0);
5976 if (Rc(ctx->opcode)) {
5977 int l1 = gen_new_label();
5978 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
5979 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
5980 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
5981 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5982 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5983 gen_set_label(l1);
5984 }
5eb7995e
JM		 5985#endif
5986}
5987
5988/* tlbwe */
c7697e1f 5989GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE)
5eb7995e
JM		 5990{
5991#if defined(CONFIG_USER_ONLY)
e06fcd75 5992 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5eb7995e 5993#else
76db3ba4 5994 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5995 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5eb7995e
JM		 5996 return;
5997 }
5998 switch (rB(ctx->opcode)) {
5999 case 0:
5eb7995e 6000 case 1:
5eb7995e 6001 case 2:
74d37793
AJ		 6002 {
6003 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6004 gen_helper_440_tlbwe(t0, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
6005 tcg_temp_free_i32(t0);
6006 }
5eb7995e
JM		 6007 break;
6008 default:
e06fcd75 6009 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5eb7995e
JM		 6010 break;
6011 }
6012#endif
6013}
6014
76a66253 6015/* wrtee */
05332d70 6016GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE)
76a66253
JM		 6017{
6018#if defined(CONFIG_USER_ONLY)
e06fcd75 6019 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 6020#else
6527f6ea 6021 TCGv t0;
76db3ba4 6022 if (unlikely(!ctx->mem_idx)) {
e06fcd75 6023 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 6024 return;
6025 }
6527f6ea
AJ		 6026 t0 = tcg_temp_new();
6027 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
6028 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6029 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
6030 tcg_temp_free(t0);
dee96f6c
JM		 6031 /* Stop translation to have a chance to raise an exception
6032 * if we just set msr_ee to 1
6033 */
e06fcd75 6034 gen_stop_exception(ctx);
76a66253
JM		 6035#endif
6036}
6037
6038/* wrteei */
05332d70 6039GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000EFC01, PPC_WRTEE)
76a66253
JM		 6040{
6041#if defined(CONFIG_USER_ONLY)
e06fcd75 6042 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 6043#else
76db3ba4 6044 if (unlikely(!ctx->mem_idx)) {
e06fcd75 6045 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 6046 return;
6047 }
6527f6ea
AJ		 6048 if (ctx->opcode & 0x00010000) {
6049 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
6050 /* Stop translation to have a chance to raise an exception */
e06fcd75 6051 gen_stop_exception(ctx);
6527f6ea
AJ		 6052 } else {
6053 tcg_gen_andi_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
6054 }
76a66253
JM		 6055#endif
6056}
6057
08e46e54 6058/* PowerPC 440 specific instructions */
76a66253
JM		 6059/* dlmzb */
6060GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC)
6061{
ef0d51af
AJ		 6062 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
6063 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
6064 cpu_gpr[rB(ctx->opcode)], t0);
6065 tcg_temp_free_i32(t0);
76a66253
JM		 6066}
6067
6068/* mbar replaces eieio on 440 */
26370046 6069GEN_HANDLER(mbar, 0x1F, 0x16, 0x1a, 0x001FF801, PPC_BOOKE)
76a66253
JM		 6070{
6071 /* interpreted as no-op */
6072}
6073
6074/* msync replaces sync on 440 */
0db1b20e 6075GEN_HANDLER(msync, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE)
76a66253
JM		 6076{
6077 /* interpreted as no-op */
6078}
6079
6080/* icbt */
c7697e1f 6081GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, PPC_BOOKE)
76a66253
JM		 6082{
6083 /* interpreted as no-op */
6084 /* XXX: specification say this is treated as a load by the MMU
6085 * but does not generate any exception
6086 */
79aceca5
FB		 6087}
6088
a9d9eb8f
JM		 6089/*** Altivec vector extension ***/
6090/* Altivec registers moves */
a9d9eb8f 6091
564e571a
AJ		 6092static always_inline TCGv_ptr gen_avr_ptr(int reg)
6093{
e4704b3b 6094 TCGv_ptr r = tcg_temp_new_ptr();
564e571a
AJ		 6095 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, avr[reg]));
6096 return r;
6097}
6098
a9d9eb8f 6099#define GEN_VR_LDX(name, opc2, opc3) \
fe1e5c53 6100GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
a9d9eb8f 6101{ \
fe1e5c53 6102 TCGv EA; \
a9d9eb8f 6103 if (unlikely(!ctx->altivec_enabled)) { \
e06fcd75 6104 gen_exception(ctx, POWERPC_EXCP_VPU); \
a9d9eb8f
JM		 6105 return; \
6106 } \
76db3ba4 6107 gen_set_access_type(ctx, ACCESS_INT); \
fe1e5c53 6108 EA = tcg_temp_new(); \
76db3ba4 6109 gen_addr_reg_index(ctx, EA); \
fe1e5c53 6110 tcg_gen_andi_tl(EA, EA, ~0xf); \
76db3ba4
AJ		 6111 if (ctx->le_mode) { \
6112 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
fe1e5c53 6113 tcg_gen_addi_tl(EA, EA, 8); \
76db3ba4 6114 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
fe1e5c53 6115 } else { \
76db3ba4 6116 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
fe1e5c53 6117 tcg_gen_addi_tl(EA, EA, 8); \
76db3ba4 6118 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
fe1e5c53
AJ		 6119 } \
6120 tcg_temp_free(EA); \
a9d9eb8f
JM		 6121}
6122
6123#define GEN_VR_STX(name, opc2, opc3) \
6124GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
6125{ \
fe1e5c53 6126 TCGv EA; \
a9d9eb8f 6127 if (unlikely(!ctx->altivec_enabled)) { \
e06fcd75 6128 gen_exception(ctx, POWERPC_EXCP_VPU); \
a9d9eb8f
JM		 6129 return; \
6130 } \
76db3ba4 6131 gen_set_access_type(ctx, ACCESS_INT); \
fe1e5c53 6132 EA = tcg_temp_new(); \
76db3ba4 6133 gen_addr_reg_index(ctx, EA); \
fe1e5c53 6134 tcg_gen_andi_tl(EA, EA, ~0xf); \
76db3ba4
AJ		 6135 if (ctx->le_mode) { \
6136 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
fe1e5c53 6137 tcg_gen_addi_tl(EA, EA, 8); \
76db3ba4 6138 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
fe1e5c53 6139 } else { \
76db3ba4 6140 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
fe1e5c53 6141 tcg_gen_addi_tl(EA, EA, 8); \
76db3ba4 6142 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
fe1e5c53
AJ		 6143 } \
6144 tcg_temp_free(EA); \
a9d9eb8f
JM		 6145}
6146
cbfb6ae9
AJ		 6147#define GEN_VR_LVE(name, opc2, opc3) \
6148 GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
6149 { \
6150 TCGv EA; \
6151 TCGv_ptr rs; \
6152 if (unlikely(!ctx->altivec_enabled)) { \
6153 gen_exception(ctx, POWERPC_EXCP_VPU); \
6154 return; \
6155 } \
6156 gen_set_access_type(ctx, ACCESS_INT); \
6157 EA = tcg_temp_new(); \
6158 gen_addr_reg_index(ctx, EA); \
6159 rs = gen_avr_ptr(rS(ctx->opcode)); \
6160 gen_helper_lve##name (rs, EA); \
6161 tcg_temp_free(EA); \
6162 tcg_temp_free_ptr(rs); \
6163 }
6164
6165#define GEN_VR_STVE(name, opc2, opc3) \
6166 GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
6167 { \
6168 TCGv EA; \
6169 TCGv_ptr rs; \
6170 if (unlikely(!ctx->altivec_enabled)) { \
6171 gen_exception(ctx, POWERPC_EXCP_VPU); \
6172 return; \
6173 } \
6174 gen_set_access_type(ctx, ACCESS_INT); \
6175 EA = tcg_temp_new(); \
6176 gen_addr_reg_index(ctx, EA); \
6177 rs = gen_avr_ptr(rS(ctx->opcode)); \
6178 gen_helper_stve##name (rs, EA); \
6179 tcg_temp_free(EA); \
6180 tcg_temp_free_ptr(rs); \
6181 }
6182
fe1e5c53 6183GEN_VR_LDX(lvx, 0x07, 0x03);
a9d9eb8f 6184/* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
fe1e5c53 6185GEN_VR_LDX(lvxl, 0x07, 0x0B);
a9d9eb8f 6186
cbfb6ae9
AJ		 6187GEN_VR_LVE(bx, 0x07, 0x00);
6188GEN_VR_LVE(hx, 0x07, 0x01);
6189GEN_VR_LVE(wx, 0x07, 0x02);
6190
fe1e5c53 6191GEN_VR_STX(svx, 0x07, 0x07);
a9d9eb8f 6192/* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
fe1e5c53 6193GEN_VR_STX(svxl, 0x07, 0x0F);
a9d9eb8f 6194
cbfb6ae9
AJ		 6195GEN_VR_STVE(bx, 0x07, 0x04);
6196GEN_VR_STVE(hx, 0x07, 0x05);
6197GEN_VR_STVE(wx, 0x07, 0x06);
6198
bf8d8ded
AJ		 6199GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC)
6200{
6201 TCGv_ptr rd;
6202 TCGv EA;
6203 if (unlikely(!ctx->altivec_enabled)) {
6204 gen_exception(ctx, POWERPC_EXCP_VPU);
6205 return;
6206 }
6207 EA = tcg_temp_new();
6208 gen_addr_reg_index(ctx, EA);
6209 rd = gen_avr_ptr(rD(ctx->opcode));
6210 gen_helper_lvsl(rd, EA);
6211 tcg_temp_free(EA);
6212 tcg_temp_free_ptr(rd);
6213}
6214
6215GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC)
6216{
6217 TCGv_ptr rd;
6218 TCGv EA;
6219 if (unlikely(!ctx->altivec_enabled)) {
6220 gen_exception(ctx, POWERPC_EXCP_VPU);
6221 return;
6222 }
6223 EA = tcg_temp_new();
6224 gen_addr_reg_index(ctx, EA);
6225 rd = gen_avr_ptr(rD(ctx->opcode));
6226 gen_helper_lvsr(rd, EA);
6227 tcg_temp_free(EA);
6228 tcg_temp_free_ptr(rd);
6229}
6230
785f451b
AJ		 6231GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC)
6232{
6233 TCGv_i32 t;
6234 if (unlikely(!ctx->altivec_enabled)) {
6235 gen_exception(ctx, POWERPC_EXCP_VPU);
6236 return;
6237 }
6238 tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0);
6239 t = tcg_temp_new_i32();
6240 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUState, vscr));
6241 tcg_gen_extu_i32_i64(cpu_avrl[rD(ctx->opcode)], t);
6242 tcg_temp_free(t);
6243}
6244
6245GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC)
6246{
6247 TCGv_i32 t;
6248 if (unlikely(!ctx->altivec_enabled)) {
6249 gen_exception(ctx, POWERPC_EXCP_VPU);
6250 return;
6251 }
6252 t = tcg_temp_new_i32();
6253 tcg_gen_trunc_i64_i32(t, cpu_avrl[rD(ctx->opcode)]);
6254 tcg_gen_st_i32(t, cpu_env, offsetof(CPUState, vscr));
6255 tcg_temp_free_i32(t);
6256}
6257
7a9b96cf
AJ		 6258/* Logical operations */
6259#define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
6260GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
6261{ \
6262 if (unlikely(!ctx->altivec_enabled)) { \
6263 gen_exception(ctx, POWERPC_EXCP_VPU); \
6264 return; \
6265 } \
6266 tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \
6267 tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \
6268}
6269
6270GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16);
6271GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17);
6272GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18);
6273GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19);
6274GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20);
6275
8e27dd6f
AJ		 6276#define GEN_VXFORM(name, opc2, opc3) \
6277GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
6278{ \
6279 TCGv_ptr ra, rb, rd; \
6280 if (unlikely(!ctx->altivec_enabled)) { \
6281 gen_exception(ctx, POWERPC_EXCP_VPU); \
6282 return; \
6283 } \
6284 ra = gen_avr_ptr(rA(ctx->opcode)); \
6285 rb = gen_avr_ptr(rB(ctx->opcode)); \
6286 rd = gen_avr_ptr(rD(ctx->opcode)); \
6287 gen_helper_##name (rd, ra, rb); \
6288 tcg_temp_free_ptr(ra); \
6289 tcg_temp_free_ptr(rb); \
6290 tcg_temp_free_ptr(rd); \
6291}
6292
7872c51c
AJ		 6293GEN_VXFORM(vaddubm, 0, 0);
6294GEN_VXFORM(vadduhm, 0, 1);
6295GEN_VXFORM(vadduwm, 0, 2);
6296GEN_VXFORM(vsububm, 0, 16);
6297GEN_VXFORM(vsubuhm, 0, 17);
6298GEN_VXFORM(vsubuwm, 0, 18);
e4039339
AJ		 6299GEN_VXFORM(vmaxub, 1, 0);
6300GEN_VXFORM(vmaxuh, 1, 1);
6301GEN_VXFORM(vmaxuw, 1, 2);
6302GEN_VXFORM(vmaxsb, 1, 4);
6303GEN_VXFORM(vmaxsh, 1, 5);
6304GEN_VXFORM(vmaxsw, 1, 6);
6305GEN_VXFORM(vminub, 1, 8);
6306GEN_VXFORM(vminuh, 1, 9);
6307GEN_VXFORM(vminuw, 1, 10);
6308GEN_VXFORM(vminsb, 1, 12);
6309GEN_VXFORM(vminsh, 1, 13);
6310GEN_VXFORM(vminsw, 1, 14);
fab3cbe9
AJ		 6311GEN_VXFORM(vavgub, 1, 16);
6312GEN_VXFORM(vavguh, 1, 17);
6313GEN_VXFORM(vavguw, 1, 18);
6314GEN_VXFORM(vavgsb, 1, 20);
6315GEN_VXFORM(vavgsh, 1, 21);
6316GEN_VXFORM(vavgsw, 1, 22);
3b430048
AJ		 6317GEN_VXFORM(vmrghb, 6, 0);
6318GEN_VXFORM(vmrghh, 6, 1);
6319GEN_VXFORM(vmrghw, 6, 2);
6320GEN_VXFORM(vmrglb, 6, 4);
6321GEN_VXFORM(vmrglh, 6, 5);
6322GEN_VXFORM(vmrglw, 6, 6);
2c277908
AJ		 6323GEN_VXFORM(vmuloub, 4, 0);
6324GEN_VXFORM(vmulouh, 4, 1);
6325GEN_VXFORM(vmulosb, 4, 4);
6326GEN_VXFORM(vmulosh, 4, 5);
6327GEN_VXFORM(vmuleub, 4, 8);
6328GEN_VXFORM(vmuleuh, 4, 9);
6329GEN_VXFORM(vmulesb, 4, 12);
6330GEN_VXFORM(vmulesh, 4, 13);
d79f0809
AJ		 6331GEN_VXFORM(vslb, 2, 4);
6332GEN_VXFORM(vslh, 2, 5);
6333GEN_VXFORM(vslw, 2, 6);
07ef34c3
AJ		 6334GEN_VXFORM(vsrb, 2, 8);
6335GEN_VXFORM(vsrh, 2, 9);
6336GEN_VXFORM(vsrw, 2, 10);
6337GEN_VXFORM(vsrab, 2, 12);
6338GEN_VXFORM(vsrah, 2, 13);
6339GEN_VXFORM(vsraw, 2, 14);
7b239bec
AJ		 6340GEN_VXFORM(vslo, 6, 16);
6341GEN_VXFORM(vsro, 6, 17);
e343da72
AJ		 6342GEN_VXFORM(vaddcuw, 0, 6);
6343GEN_VXFORM(vsubcuw, 0, 22);
5ab09f33
AJ		 6344GEN_VXFORM(vaddubs, 0, 8);
6345GEN_VXFORM(vadduhs, 0, 9);
6346GEN_VXFORM(vadduws, 0, 10);
6347GEN_VXFORM(vaddsbs, 0, 12);
6348GEN_VXFORM(vaddshs, 0, 13);
6349GEN_VXFORM(vaddsws, 0, 14);
6350GEN_VXFORM(vsububs, 0, 24);
6351GEN_VXFORM(vsubuhs, 0, 25);
6352GEN_VXFORM(vsubuws, 0, 26);
6353GEN_VXFORM(vsubsbs, 0, 28);
6354GEN_VXFORM(vsubshs, 0, 29);
6355GEN_VXFORM(vsubsws, 0, 30);
5e1d0985
AJ		 6356GEN_VXFORM(vrlb, 2, 0);
6357GEN_VXFORM(vrlh, 2, 1);
6358GEN_VXFORM(vrlw, 2, 2);
d9430add
AJ		 6359GEN_VXFORM(vsl, 2, 7);
6360GEN_VXFORM(vsr, 2, 11);
5335a145
AJ		 6361GEN_VXFORM(vpkuhum, 7, 0);
6362GEN_VXFORM(vpkuwum, 7, 1);
6363GEN_VXFORM(vpkuhus, 7, 2);
6364GEN_VXFORM(vpkuwus, 7, 3);
6365GEN_VXFORM(vpkshus, 7, 4);
6366GEN_VXFORM(vpkswus, 7, 5);
6367GEN_VXFORM(vpkshss, 7, 6);
6368GEN_VXFORM(vpkswss, 7, 7);
1dd9ffb9 6369GEN_VXFORM(vpkpx, 7, 12);
8142cddd
AJ		 6370GEN_VXFORM(vsum4ubs, 4, 24);
6371GEN_VXFORM(vsum4sbs, 4, 28);
6372GEN_VXFORM(vsum4shs, 4, 25);
6373GEN_VXFORM(vsum2sws, 4, 26);
6374GEN_VXFORM(vsumsws, 4, 30);
fab3cbe9 6375
0cbcd906
AJ		 6376#define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
6377 GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
6378 { \
6379 TCGv_ptr ra, rb, rd; \
6380 if (unlikely(!ctx->altivec_enabled)) { \
6381 gen_exception(ctx, POWERPC_EXCP_VPU); \
6382 return; \
6383 } \
6384 ra = gen_avr_ptr(rA(ctx->opcode)); \
6385 rb = gen_avr_ptr(rB(ctx->opcode)); \
6386 rd = gen_avr_ptr(rD(ctx->opcode)); \
6387 gen_helper_##opname (rd, ra, rb); \
6388 tcg_temp_free_ptr(ra); \
6389 tcg_temp_free_ptr(rb); \
6390 tcg_temp_free_ptr(rd); \
6391 }
6392
6393#define GEN_VXRFORM(name, opc2, opc3) \
6394 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
6395 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
6396
1add6e23
AJ		 6397GEN_VXRFORM(vcmpequb, 3, 0)
6398GEN_VXRFORM(vcmpequh, 3, 1)
6399GEN_VXRFORM(vcmpequw, 3, 2)
6400GEN_VXRFORM(vcmpgtsb, 3, 12)
6401GEN_VXRFORM(vcmpgtsh, 3, 13)
6402GEN_VXRFORM(vcmpgtsw, 3, 14)
6403GEN_VXRFORM(vcmpgtub, 3, 8)
6404GEN_VXRFORM(vcmpgtuh, 3, 9)
6405GEN_VXRFORM(vcmpgtuw, 3, 10)
6406
c026766b
AJ		 6407#define GEN_VXFORM_SIMM(name, opc2, opc3) \
6408 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
6409 { \
6410 TCGv_ptr rd; \
6411 TCGv_i32 simm; \
6412 if (unlikely(!ctx->altivec_enabled)) { \
6413 gen_exception(ctx, POWERPC_EXCP_VPU); \
6414 return; \
6415 } \
6416 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
6417 rd = gen_avr_ptr(rD(ctx->opcode)); \
6418 gen_helper_##name (rd, simm); \
6419 tcg_temp_free_i32(simm); \
6420 tcg_temp_free_ptr(rd); \
6421 }
6422
6423GEN_VXFORM_SIMM(vspltisb, 6, 12);
6424GEN_VXFORM_SIMM(vspltish, 6, 13);
6425GEN_VXFORM_SIMM(vspltisw, 6, 14);
6426
de5f2484
AJ		 6427#define GEN_VXFORM_NOA(name, opc2, opc3) \
6428 GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC) \
6429 { \
6430 TCGv_ptr rb, rd; \
6431 if (unlikely(!ctx->altivec_enabled)) { \
6432 gen_exception(ctx, POWERPC_EXCP_VPU); \
6433 return; \
6434 } \
6435 rb = gen_avr_ptr(rB(ctx->opcode)); \
6436 rd = gen_avr_ptr(rD(ctx->opcode)); \
6437 gen_helper_##name (rd, rb); \
6438 tcg_temp_free_ptr(rb); \
6439 tcg_temp_free_ptr(rd); \
6440 }
6441
6cf1c6e5
AJ		 6442GEN_VXFORM_NOA(vupkhsb, 7, 8);
6443GEN_VXFORM_NOA(vupkhsh, 7, 9);
6444GEN_VXFORM_NOA(vupklsb, 7, 10);
6445GEN_VXFORM_NOA(vupklsh, 7, 11);
79f85c3a
AJ		 6446GEN_VXFORM_NOA(vupkhpx, 7, 13);
6447GEN_VXFORM_NOA(vupklpx, 7, 15);
6448
21d21583
AJ		 6449#define GEN_VXFORM_SIMM(name, opc2, opc3) \
6450 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
6451 { \
6452 TCGv_ptr rd; \
6453 TCGv_i32 simm; \
6454 if (unlikely(!ctx->altivec_enabled)) { \
6455 gen_exception(ctx, POWERPC_EXCP_VPU); \
6456 return; \
6457 } \
6458 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
6459 rd = gen_avr_ptr(rD(ctx->opcode)); \
6460 gen_helper_##name (rd, simm); \
6461 tcg_temp_free_i32(simm); \
6462 tcg_temp_free_ptr(rd); \
6463 }
6464
27a4edb3
AJ		 6465#define GEN_VXFORM_UIMM(name, opc2, opc3) \
6466 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
6467 { \
6468 TCGv_ptr rb, rd; \
6469 TCGv_i32 uimm; \
6470 if (unlikely(!ctx->altivec_enabled)) { \
6471 gen_exception(ctx, POWERPC_EXCP_VPU); \
6472 return; \
6473 } \
6474 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
6475 rb = gen_avr_ptr(rB(ctx->opcode)); \
6476 rd = gen_avr_ptr(rD(ctx->opcode)); \
6477 gen_helper_##name (rd, rb, uimm); \
6478 tcg_temp_free_i32(uimm); \
6479 tcg_temp_free_ptr(rb); \
6480 tcg_temp_free_ptr(rd); \
6481 }
6482
e4e6bee7
AJ		 6483GEN_VXFORM_UIMM(vspltb, 6, 8);
6484GEN_VXFORM_UIMM(vsplth, 6, 9);
6485GEN_VXFORM_UIMM(vspltw, 6, 10);
6486
cd633b10
AJ		 6487GEN_HANDLER(vsldoi, 0x04, 0x16, 0xFF, 0x00000400, PPC_ALTIVEC)
6488{
6489 TCGv_ptr ra, rb, rd;
6490 TCGv sh;
6491 if (unlikely(!ctx->altivec_enabled)) {
6492 gen_exception(ctx, POWERPC_EXCP_VPU);
6493 return;
6494 }
6495 ra = gen_avr_ptr(rA(ctx->opcode));
6496 rb = gen_avr_ptr(rB(ctx->opcode));
6497 rd = gen_avr_ptr(rD(ctx->opcode));
6498 sh = tcg_const_i32(VSH(ctx->opcode));
6499 gen_helper_vsldoi (rd, ra, rb, sh);
6500 tcg_temp_free_ptr(ra);
6501 tcg_temp_free_ptr(rb);
6502 tcg_temp_free_ptr(rd);
6503 tcg_temp_free(sh);
6504}
6505
707cec33
AJ		 6506#define GEN_VAFORM_PAIRED(name0, name1, opc2) \
6507 GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC) \
6508 { \
6509 TCGv_ptr ra, rb, rc, rd; \
6510 if (unlikely(!ctx->altivec_enabled)) { \
6511 gen_exception(ctx, POWERPC_EXCP_VPU); \
6512 return; \
6513 } \
6514 ra = gen_avr_ptr(rA(ctx->opcode)); \
6515 rb = gen_avr_ptr(rB(ctx->opcode)); \
6516 rc = gen_avr_ptr(rC(ctx->opcode)); \
6517 rd = gen_avr_ptr(rD(ctx->opcode)); \
6518 if (Rc(ctx->opcode)) { \
6519 gen_helper_##name1 (rd, ra, rb, rc); \
6520 } else { \
6521 gen_helper_##name0 (rd, ra, rb, rc); \
6522 } \
6523 tcg_temp_free_ptr(ra); \
6524 tcg_temp_free_ptr(rb); \
6525 tcg_temp_free_ptr(rc); \
6526 tcg_temp_free_ptr(rd); \
6527 }
6528
b161ae27
AJ		 6529GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16)
6530
bcd2ee23
AJ		 6531GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC)
6532{
6533 TCGv_ptr ra, rb, rc, rd;
6534 if (unlikely(!ctx->altivec_enabled)) {
6535 gen_exception(ctx, POWERPC_EXCP_VPU);
6536 return;
6537 }
6538 ra = gen_avr_ptr(rA(ctx->opcode));
6539 rb = gen_avr_ptr(rB(ctx->opcode));
6540 rc = gen_avr_ptr(rC(ctx->opcode));
6541 rd = gen_avr_ptr(rD(ctx->opcode));
6542 gen_helper_vmladduhm(rd, ra, rb, rc);
6543 tcg_temp_free_ptr(ra);
6544 tcg_temp_free_ptr(rb);
6545 tcg_temp_free_ptr(rc);
6546 tcg_temp_free_ptr(rd);
6547}
6548
b04ae981 6549GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18)
4d9903b6 6550GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19)
eae07261 6551GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20)
d1258698 6552GEN_VAFORM_PAIRED(vsel, vperm, 21)
b04ae981 6553
0487d6a8 6554/*** SPE extension ***/
0487d6a8 6555/* Register moves */
3cd7d1dd 6556
a7812ae4 6557static always_inline void gen_load_gpr64(TCGv_i64 t, int reg) {
f78fb44e
AJ		 6558#if defined(TARGET_PPC64)
6559 tcg_gen_mov_i64(t, cpu_gpr[reg]);
6560#else
36aa55dc 6561 tcg_gen_concat_i32_i64(t, cpu_gpr[reg], cpu_gprh[reg]);
3cd7d1dd 6562#endif
f78fb44e 6563}
3cd7d1dd 6564
a7812ae4 6565static always_inline void gen_store_gpr64(int reg, TCGv_i64 t) {
f78fb44e
AJ		 6566#if defined(TARGET_PPC64)
6567 tcg_gen_mov_i64(cpu_gpr[reg], t);
6568#else
a7812ae4 6569 TCGv_i64 tmp = tcg_temp_new_i64();
f78fb44e 6570 tcg_gen_trunc_i64_i32(cpu_gpr[reg], t);
f78fb44e
AJ		 6571 tcg_gen_shri_i64(tmp, t, 32);
6572 tcg_gen_trunc_i64_i32(cpu_gprh[reg], tmp);
a7812ae4 6573 tcg_temp_free_i64(tmp);
3cd7d1dd 6574#endif
f78fb44e 6575}
3cd7d1dd 6576
0487d6a8
JM		 6577#define GEN_SPE(name0, name1, opc2, opc3, inval, type) \
6578GEN_HANDLER(name0##_##name1, 0x04, opc2, opc3, inval, type) \
6579{ \
6580 if (Rc(ctx->opcode)) \
6581 gen_##name1(ctx); \
6582 else \
6583 gen_##name0(ctx); \
6584}
6585
6586/* Handler for undefined SPE opcodes */
b068d6a7 6587static always_inline void gen_speundef (DisasContext *ctx)
0487d6a8 6588{
e06fcd75 6589 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
0487d6a8
JM		 6590}
6591
57951c27
AJ		 6592/* SPE logic */
6593#if defined(TARGET_PPC64)
6594#define GEN_SPEOP_LOGIC2(name, tcg_op) \
b068d6a7 6595static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 6596{ \
6597 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 6598 gen_exception(ctx, POWERPC_EXCP_APU); \
0487d6a8
JM		 6599 return; \
6600 } \
57951c27
AJ		 6601 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6602 cpu_gpr[rB(ctx->opcode)]); \
6603}
6604#else
6605#define GEN_SPEOP_LOGIC2(name, tcg_op) \
6606static always_inline void gen_##name (DisasContext *ctx) \
6607{ \
6608 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 6609 gen_exception(ctx, POWERPC_EXCP_APU); \
57951c27
AJ		 6610 return; \
6611 } \
6612 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6613 cpu_gpr[rB(ctx->opcode)]); \
6614 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6615 cpu_gprh[rB(ctx->opcode)]); \
0487d6a8 6616}
57951c27
AJ		 6617#endif
6618
6619GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl);
6620GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl);
6621GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl);
6622GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl);
6623GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl);
6624GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl);
6625GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl);
6626GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl);
0487d6a8 6627
57951c27
AJ		 6628/* SPE logic immediate */
6629#if defined(TARGET_PPC64)
6630#define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
3d3a6a0a
AJ		 6631static always_inline void gen_##name (DisasContext *ctx) \
6632{ \
6633 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 6634 gen_exception(ctx, POWERPC_EXCP_APU); \
3d3a6a0a
AJ		 6635 return; \
6636 } \
a7812ae4
PB		 6637 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6638 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6639 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
57951c27
AJ		 6640 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6641 tcg_opi(t0, t0, rB(ctx->opcode)); \
6642 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6643 tcg_gen_trunc_i64_i32(t1, t2); \
a7812ae4 6644 tcg_temp_free_i64(t2); \
57951c27
AJ		 6645 tcg_opi(t1, t1, rB(ctx->opcode)); \
6646 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
a7812ae4
PB		 6647 tcg_temp_free_i32(t0); \
6648 tcg_temp_free_i32(t1); \
3d3a6a0a 6649}
57951c27
AJ		 6650#else
6651#define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
b068d6a7 6652static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 6653{ \
6654 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 6655 gen_exception(ctx, POWERPC_EXCP_APU); \
0487d6a8
JM		 6656 return; \
6657 } \
57951c27
AJ		 6658 tcg_opi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6659 rB(ctx->opcode)); \
6660 tcg_opi(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6661 rB(ctx->opcode)); \
0487d6a8 6662}
57951c27
AJ		 6663#endif
6664GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32);
6665GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32);
6666GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32);
6667GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32);
0487d6a8 6668
57951c27
AJ		 6669/* SPE arithmetic */
6670#if defined(TARGET_PPC64)
6671#define GEN_SPEOP_ARITH1(name, tcg_op) \
b068d6a7 6672static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 6673{ \
6674 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 6675 gen_exception(ctx, POWERPC_EXCP_APU); \
0487d6a8
JM		 6676 return; \
6677 } \
a7812ae4
PB		 6678 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6679 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6680 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
57951c27
AJ		 6681 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6682 tcg_op(t0, t0); \
6683 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6684 tcg_gen_trunc_i64_i32(t1, t2); \
a7812ae4 6685 tcg_temp_free_i64(t2); \
57951c27
AJ		 6686 tcg_op(t1, t1); \
6687 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
a7812ae4
PB		 6688 tcg_temp_free_i32(t0); \
6689 tcg_temp_free_i32(t1); \
0487d6a8 6690}
57951c27 6691#else
a7812ae4 6692#define GEN_SPEOP_ARITH1(name, tcg_op) \
57951c27
AJ		 6693static always_inline void gen_##name (DisasContext *ctx) \
6694{ \
6695 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 6696 gen_exception(ctx, POWERPC_EXCP_APU); \
57951c27
AJ		 6697 return; \
6698 } \
6699 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \
6700 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \
6701}
6702#endif
0487d6a8 6703
a7812ae4 6704static always_inline void gen_op_evabs (TCGv_i32 ret, TCGv_i32 arg1)
57951c27
AJ		 6705{
6706 int l1 = gen_new_label();
6707 int l2 = gen_new_label();
0487d6a8 6708
57951c27
AJ		 6709 tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1);
6710 tcg_gen_neg_i32(ret, arg1);
6711 tcg_gen_br(l2);
6712 gen_set_label(l1);
a7812ae4 6713 tcg_gen_mov_i32(ret, arg1);
57951c27
AJ		 6714 gen_set_label(l2);
6715}
6716GEN_SPEOP_ARITH1(evabs, gen_op_evabs);
6717GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32);
6718GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32);
6719GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32);
a7812ae4 6720static always_inline void gen_op_evrndw (TCGv_i32 ret, TCGv_i32 arg1)
0487d6a8 6721{
57951c27
AJ		 6722 tcg_gen_addi_i32(ret, arg1, 0x8000);
6723 tcg_gen_ext16u_i32(ret, ret);
6724}
6725GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw);
a7812ae4
PB		 6726GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32);
6727GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32);
0487d6a8 6728
57951c27
AJ		 6729#if defined(TARGET_PPC64)
6730#define GEN_SPEOP_ARITH2(name, tcg_op) \
6731static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 6732{ \
6733 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 6734 gen_exception(ctx, POWERPC_EXCP_APU); \
0487d6a8
JM		 6735 return; \
6736 } \
a7812ae4
PB		 6737 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6738 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6739 TCGv_i32 t2 = tcg_temp_local_new_i32(); \
501e23c4 6740 TCGv_i64 t3 = tcg_temp_local_new_i64(); \
57951c27
AJ		 6741 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6742 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rB(ctx->opcode)]); \
6743 tcg_op(t0, t0, t2); \
6744 tcg_gen_shri_i64(t3, cpu_gpr[rA(ctx->opcode)], 32); \
6745 tcg_gen_trunc_i64_i32(t1, t3); \
6746 tcg_gen_shri_i64(t3, cpu_gpr[rB(ctx->opcode)], 32); \
6747 tcg_gen_trunc_i64_i32(t2, t3); \
a7812ae4 6748 tcg_temp_free_i64(t3); \
57951c27 6749 tcg_op(t1, t1, t2); \
a7812ae4 6750 tcg_temp_free_i32(t2); \
57951c27 6751 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
a7812ae4
PB		 6752 tcg_temp_free_i32(t0); \
6753 tcg_temp_free_i32(t1); \
0487d6a8 6754}
57951c27
AJ		 6755#else
6756#define GEN_SPEOP_ARITH2(name, tcg_op) \
6757static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 6758{ \
6759 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 6760 gen_exception(ctx, POWERPC_EXCP_APU); \
0487d6a8
JM		 6761 return; \
6762 } \
57951c27
AJ		 6763 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6764 cpu_gpr[rB(ctx->opcode)]); \
6765 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6766 cpu_gprh[rB(ctx->opcode)]); \
0487d6a8 6767}
57951c27 6768#endif
0487d6a8 6769
a7812ae4 6770static always_inline void gen_op_evsrwu (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
57951c27 6771{
a7812ae4 6772 TCGv_i32 t0;
57951c27 6773 int l1, l2;
0487d6a8 6774
57951c27
AJ		 6775 l1 = gen_new_label();
6776 l2 = gen_new_label();
a7812ae4 6777 t0 = tcg_temp_local_new_i32();
57951c27
AJ		 6778 /* No error here: 6 bits are used */
6779 tcg_gen_andi_i32(t0, arg2, 0x3F);
6780 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
6781 tcg_gen_shr_i32(ret, arg1, t0);
6782 tcg_gen_br(l2);
6783 gen_set_label(l1);
6784 tcg_gen_movi_i32(ret, 0);
6785 tcg_gen_br(l2);
a7812ae4 6786 tcg_temp_free_i32(t0);
57951c27
AJ		 6787}
6788GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu);
a7812ae4 6789static always_inline void gen_op_evsrws (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
57951c27 6790{
a7812ae4 6791 TCGv_i32 t0;
57951c27
AJ		 6792 int l1, l2;
6793
6794 l1 = gen_new_label();
6795 l2 = gen_new_label();
a7812ae4 6796 t0 = tcg_temp_local_new_i32();
57951c27
AJ		 6797 /* No error here: 6 bits are used */
6798 tcg_gen_andi_i32(t0, arg2, 0x3F);
6799 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
6800 tcg_gen_sar_i32(ret, arg1, t0);
6801 tcg_gen_br(l2);
6802 gen_set_label(l1);
6803 tcg_gen_movi_i32(ret, 0);
6804 tcg_gen_br(l2);
a7812ae4 6805 tcg_temp_free_i32(t0);
57951c27
AJ		 6806}
6807GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws);
a7812ae4 6808static always_inline void gen_op_evslw (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
57951c27 6809{
a7812ae4 6810 TCGv_i32 t0;
57951c27
AJ		 6811 int l1, l2;
6812
6813 l1 = gen_new_label();
6814 l2 = gen_new_label();
a7812ae4 6815 t0 = tcg_temp_local_new_i32();
57951c27
AJ		 6816 /* No error here: 6 bits are used */
6817 tcg_gen_andi_i32(t0, arg2, 0x3F);
6818 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
6819 tcg_gen_shl_i32(ret, arg1, t0);
6820 tcg_gen_br(l2);
6821 gen_set_label(l1);
6822 tcg_gen_movi_i32(ret, 0);
6823 tcg_gen_br(l2);
a7812ae4 6824 tcg_temp_free_i32(t0);
57951c27
AJ		 6825}
6826GEN_SPEOP_ARITH2(evslw, gen_op_evslw);
a7812ae4 6827static always_inline void gen_op_evrlw (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
57951c27 6828{
a7812ae4 6829 TCGv_i32 t0 = tcg_temp_new_i32();
57951c27
AJ		 6830 tcg_gen_andi_i32(t0, arg2, 0x1F);
6831 tcg_gen_rotl_i32(ret, arg1, t0);
a7812ae4 6832 tcg_temp_free_i32(t0);
57951c27
AJ		 6833}
6834GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw);
6835static always_inline void gen_evmergehi (DisasContext *ctx)
6836{
6837 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 6838 gen_exception(ctx, POWERPC_EXCP_APU);
57951c27
AJ		 6839 return;
6840 }
6841#if defined(TARGET_PPC64)
a7812ae4
PB		 6842 TCGv t0 = tcg_temp_new();
6843 TCGv t1 = tcg_temp_new();
57951c27
AJ		 6844 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
6845 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
6846 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
6847 tcg_temp_free(t0);
6848 tcg_temp_free(t1);
6849#else
6850 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
6851 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6852#endif
6853}
6854GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32);
a7812ae4 6855static always_inline void gen_op_evsubf (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
0487d6a8 6856{
57951c27
AJ		 6857 tcg_gen_sub_i32(ret, arg2, arg1);
6858}
6859GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf);
0487d6a8 6860
57951c27
AJ		 6861/* SPE arithmetic immediate */
6862#if defined(TARGET_PPC64)
6863#define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
6864static always_inline void gen_##name (DisasContext *ctx) \
6865{ \
6866 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 6867 gen_exception(ctx, POWERPC_EXCP_APU); \
57951c27
AJ		 6868 return; \
6869 } \
a7812ae4
PB		 6870 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6871 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6872 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
57951c27
AJ		 6873 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
6874 tcg_op(t0, t0, rA(ctx->opcode)); \
6875 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
6876 tcg_gen_trunc_i64_i32(t1, t2); \
e06fcd75 6877 tcg_temp_free_i64(t2); \
57951c27
AJ		 6878 tcg_op(t1, t1, rA(ctx->opcode)); \
6879 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
a7812ae4
PB		 6880 tcg_temp_free_i32(t0); \
6881 tcg_temp_free_i32(t1); \
57951c27
AJ		 6882}
6883#else
6884#define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
6885static always_inline void gen_##name (DisasContext *ctx) \
6886{ \
6887 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 6888 gen_exception(ctx, POWERPC_EXCP_APU); \
57951c27
AJ		 6889 return; \
6890 } \
6891 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
6892 rA(ctx->opcode)); \
6893 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)], \
6894 rA(ctx->opcode)); \
6895}
6896#endif
6897GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32);
6898GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32);
6899
6900/* SPE comparison */
6901#if defined(TARGET_PPC64)
6902#define GEN_SPEOP_COMP(name, tcg_cond) \
6903static always_inline void gen_##name (DisasContext *ctx) \
6904{ \
6905 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 6906 gen_exception(ctx, POWERPC_EXCP_APU); \
57951c27
AJ		 6907 return; \
6908 } \
6909 int l1 = gen_new_label(); \
6910 int l2 = gen_new_label(); \
6911 int l3 = gen_new_label(); \
6912 int l4 = gen_new_label(); \
a7812ae4
PB		 6913 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6914 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6915 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
57951c27
AJ		 6916 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6917 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
6918 tcg_gen_brcond_i32(tcg_cond, t0, t1, l1); \
a7812ae4 6919 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \
57951c27
AJ		 6920 tcg_gen_br(l2); \
6921 gen_set_label(l1); \
6922 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
6923 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
6924 gen_set_label(l2); \
6925 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6926 tcg_gen_trunc_i64_i32(t0, t2); \
6927 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
6928 tcg_gen_trunc_i64_i32(t1, t2); \
a7812ae4 6929 tcg_temp_free_i64(t2); \
57951c27
AJ		 6930 tcg_gen_brcond_i32(tcg_cond, t0, t1, l3); \
6931 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
6932 ~(CRF_CH | CRF_CH_AND_CL)); \
6933 tcg_gen_br(l4); \
6934 gen_set_label(l3); \
6935 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
6936 CRF_CH | CRF_CH_OR_CL); \
6937 gen_set_label(l4); \
a7812ae4
PB		 6938 tcg_temp_free_i32(t0); \
6939 tcg_temp_free_i32(t1); \
57951c27
AJ		 6940}
6941#else
6942#define GEN_SPEOP_COMP(name, tcg_cond) \
6943static always_inline void gen_##name (DisasContext *ctx) \
6944{ \
6945 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 6946 gen_exception(ctx, POWERPC_EXCP_APU); \
57951c27
AJ		 6947 return; \
6948 } \
6949 int l1 = gen_new_label(); \
6950 int l2 = gen_new_label(); \
6951 int l3 = gen_new_label(); \
6952 int l4 = gen_new_label(); \
6953 \
6954 tcg_gen_brcond_i32(tcg_cond, cpu_gpr[rA(ctx->opcode)], \
6955 cpu_gpr[rB(ctx->opcode)], l1); \
6956 tcg_gen_movi_tl(cpu_crf[crfD(ctx->opcode)], 0); \
6957 tcg_gen_br(l2); \
6958 gen_set_label(l1); \
6959 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
6960 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
6961 gen_set_label(l2); \
6962 tcg_gen_brcond_i32(tcg_cond, cpu_gprh[rA(ctx->opcode)], \
6963 cpu_gprh[rB(ctx->opcode)], l3); \
6964 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
6965 ~(CRF_CH | CRF_CH_AND_CL)); \
6966 tcg_gen_br(l4); \
6967 gen_set_label(l3); \
6968 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
6969 CRF_CH | CRF_CH_OR_CL); \
6970 gen_set_label(l4); \
6971}
6972#endif
6973GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU);
6974GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT);
6975GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU);
6976GEN_SPEOP_COMP(evcmplts, TCG_COND_LT);
6977GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ);
6978
6979/* SPE misc */
6980static always_inline void gen_brinc (DisasContext *ctx)
6981{
6982 /* Note: brinc is usable even if SPE is disabled */
a7812ae4
PB		 6983 gen_helper_brinc(cpu_gpr[rD(ctx->opcode)],
6984 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
0487d6a8 6985}
57951c27
AJ		 6986static always_inline void gen_evmergelo (DisasContext *ctx)
6987{
6988 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 6989 gen_exception(ctx, POWERPC_EXCP_APU);
57951c27
AJ		 6990 return;
6991 }
6992#if defined(TARGET_PPC64)
a7812ae4
PB		 6993 TCGv t0 = tcg_temp_new();
6994 TCGv t1 = tcg_temp_new();
57951c27
AJ		 6995 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x00000000FFFFFFFFLL);
6996 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
6997 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
6998 tcg_temp_free(t0);
6999 tcg_temp_free(t1);
7000#else
7001 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7002 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7003#endif
7004}
7005static always_inline void gen_evmergehilo (DisasContext *ctx)
7006{
7007 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 7008 gen_exception(ctx, POWERPC_EXCP_APU);
57951c27
AJ		 7009 return;
7010 }
7011#if defined(TARGET_PPC64)
a7812ae4
PB		 7012 TCGv t0 = tcg_temp_new();
7013 TCGv t1 = tcg_temp_new();
57951c27
AJ		 7014 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x00000000FFFFFFFFLL);
7015 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
7016 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7017 tcg_temp_free(t0);
7018 tcg_temp_free(t1);
7019#else
7020 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7021 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7022#endif
7023}
7024static always_inline void gen_evmergelohi (DisasContext *ctx)
7025{
7026 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 7027 gen_exception(ctx, POWERPC_EXCP_APU);
57951c27
AJ		 7028 return;
7029 }
7030#if defined(TARGET_PPC64)
a7812ae4
PB		 7031 TCGv t0 = tcg_temp_new();
7032 TCGv t1 = tcg_temp_new();
57951c27
AJ		 7033 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
7034 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
7035 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7036 tcg_temp_free(t0);
7037 tcg_temp_free(t1);
7038#else
7039 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7040 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7041#endif
7042}
7043static always_inline void gen_evsplati (DisasContext *ctx)
7044{
38d14952 7045 uint64_t imm = ((int32_t)(rA(ctx->opcode) << 11)) >> 27;
0487d6a8 7046
57951c27 7047#if defined(TARGET_PPC64)
38d14952 7048 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
57951c27
AJ		 7049#else
7050 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
7051 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
7052#endif
7053}
b068d6a7 7054static always_inline void gen_evsplatfi (DisasContext *ctx)
0487d6a8 7055{
38d14952 7056 uint64_t imm = rA(ctx->opcode) << 11;
0487d6a8 7057
57951c27 7058#if defined(TARGET_PPC64)
38d14952 7059 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
57951c27
AJ		 7060#else
7061 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
7062 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
7063#endif
0487d6a8
JM		 7064}
7065
57951c27
AJ		 7066static always_inline void gen_evsel (DisasContext *ctx)
7067{
7068 int l1 = gen_new_label();
7069 int l2 = gen_new_label();
7070 int l3 = gen_new_label();
7071 int l4 = gen_new_label();
a7812ae4 7072 TCGv_i32 t0 = tcg_temp_local_new_i32();
57951c27 7073#if defined(TARGET_PPC64)
a7812ae4
PB		 7074 TCGv t1 = tcg_temp_local_new();
7075 TCGv t2 = tcg_temp_local_new();
57951c27
AJ		 7076#endif
7077 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3);
7078 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
7079#if defined(TARGET_PPC64)
7080 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF00000000ULL);
7081#else
7082 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7083#endif
7084 tcg_gen_br(l2);
7085 gen_set_label(l1);
7086#if defined(TARGET_PPC64)
7087 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0xFFFFFFFF00000000ULL);
7088#else
7089 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7090#endif
7091 gen_set_label(l2);
7092 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2);
7093 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3);
7094#if defined(TARGET_PPC64)
7095 tcg_gen_andi_tl(t2, cpu_gpr[rA(ctx->opcode)], 0x00000000FFFFFFFFULL);
7096#else
7097 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7098#endif
7099 tcg_gen_br(l4);
7100 gen_set_label(l3);
7101#if defined(TARGET_PPC64)
7102 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x00000000FFFFFFFFULL);
7103#else
7104 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7105#endif
7106 gen_set_label(l4);
a7812ae4 7107 tcg_temp_free_i32(t0);
57951c27
AJ		 7108#if defined(TARGET_PPC64)
7109 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t1, t2);
7110 tcg_temp_free(t1);
7111 tcg_temp_free(t2);
7112#endif
7113}
7114GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE)
7115{
7116 gen_evsel(ctx);
7117}
7118GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE)
7119{
7120 gen_evsel(ctx);
7121}
7122GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE)
7123{
7124 gen_evsel(ctx);
7125}
7126GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE)
7127{
7128 gen_evsel(ctx);
7129}
0487d6a8
JM		 7130
7131GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, PPC_SPE); ////
7132GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, PPC_SPE);
7133GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, PPC_SPE); ////
7134GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, PPC_SPE);
7135GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, PPC_SPE); ////
7136GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, PPC_SPE); ////
7137GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, PPC_SPE); ////
7138GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x00000000, PPC_SPE); //
7139GEN_SPE(speundef, evand, 0x08, 0x08, 0x00000000, PPC_SPE); ////
7140GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, PPC_SPE); ////
7141GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, PPC_SPE); ////
7142GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, PPC_SPE); ////
7143GEN_SPE(speundef, evorc, 0x0D, 0x08, 0x00000000, PPC_SPE); ////
7144GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, PPC_SPE); ////
7145GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, PPC_SPE); ////
7146GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, PPC_SPE);
7147GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, PPC_SPE); ////
7148GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, PPC_SPE);
7149GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, PPC_SPE); //
7150GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, PPC_SPE);
7151GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, PPC_SPE); ////
7152GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, PPC_SPE); ////
7153GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, PPC_SPE); ////
7154GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, PPC_SPE); ////
7155GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, PPC_SPE); ////
7156
6a6ae23f 7157/* SPE load and stores */
76db3ba4 7158static always_inline void gen_addr_spe_imm_index (DisasContext *ctx, TCGv EA, int sh)
6a6ae23f
AJ		 7159{
7160 target_ulong uimm = rB(ctx->opcode);
7161
76db3ba4 7162 if (rA(ctx->opcode) == 0) {
6a6ae23f 7163 tcg_gen_movi_tl(EA, uimm << sh);
76db3ba4 7164 } else {
6a6ae23f 7165 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh);
76db3ba4
AJ		 7166#if defined(TARGET_PPC64)
7167 if (!ctx->sf_mode) {
7168 tcg_gen_ext32u_tl(EA, EA);
7169 }
7170#endif
7171 }
0487d6a8 7172}
6a6ae23f
AJ		 7173
7174static always_inline void gen_op_evldd(DisasContext *ctx, TCGv addr)
7175{
7176#if defined(TARGET_PPC64)
76db3ba4 7177 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], addr);
6a6ae23f
AJ		 7178#else
7179 TCGv_i64 t0 = tcg_temp_new_i64();
76db3ba4 7180 gen_qemu_ld64(ctx, t0, addr);
6a6ae23f
AJ		 7181 tcg_gen_trunc_i64_i32(cpu_gpr[rD(ctx->opcode)], t0);
7182 tcg_gen_shri_i64(t0, t0, 32);
7183 tcg_gen_trunc_i64_i32(cpu_gprh[rD(ctx->opcode)], t0);
7184 tcg_temp_free_i64(t0);
7185#endif
0487d6a8 7186}
6a6ae23f
AJ		 7187
7188static always_inline void gen_op_evldw(DisasContext *ctx, TCGv addr)
7189{
0487d6a8 7190#if defined(TARGET_PPC64)
6a6ae23f 7191 TCGv t0 = tcg_temp_new();
76db3ba4 7192 gen_qemu_ld32u(ctx, t0, addr);
6a6ae23f 7193 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
76db3ba4
AJ		 7194 gen_addr_add(ctx, addr, addr, 4);
7195 gen_qemu_ld32u(ctx, t0, addr);
6a6ae23f
AJ		 7196 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7197 tcg_temp_free(t0);
7198#else
76db3ba4
AJ		 7199 gen_qemu_ld32u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7200 gen_addr_add(ctx, addr, addr, 4);
7201 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
6a6ae23f 7202#endif
0487d6a8 7203}
6a6ae23f
AJ		 7204
7205static always_inline void gen_op_evldh(DisasContext *ctx, TCGv addr)
7206{
7207 TCGv t0 = tcg_temp_new();
7208#if defined(TARGET_PPC64)
76db3ba4 7209 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 7210 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
76db3ba4
AJ		 7211 gen_addr_add(ctx, addr, addr, 2);
7212 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 7213 tcg_gen_shli_tl(t0, t0, 32);
7214 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
76db3ba4
AJ		 7215 gen_addr_add(ctx, addr, addr, 2);
7216 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 7217 tcg_gen_shli_tl(t0, t0, 16);
7218 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
76db3ba4
AJ		 7219 gen_addr_add(ctx, addr, addr, 2);
7220 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 7221 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
0487d6a8 7222#else
76db3ba4 7223 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 7224 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
76db3ba4
AJ		 7225 gen_addr_add(ctx, addr, addr, 2);
7226 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 7227 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
76db3ba4
AJ		 7228 gen_addr_add(ctx, addr, addr, 2);
7229 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 7230 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
76db3ba4
AJ		 7231 gen_addr_add(ctx, addr, addr, 2);
7232 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 7233 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
0487d6a8 7234#endif
6a6ae23f 7235 tcg_temp_free(t0);
0487d6a8
JM		 7236}
7237
6a6ae23f
AJ		 7238static always_inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr)
7239{
7240 TCGv t0 = tcg_temp_new();
76db3ba4 7241 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 7242#if defined(TARGET_PPC64)
7243 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7244 tcg_gen_shli_tl(t0, t0, 16);
7245 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7246#else
7247 tcg_gen_shli_tl(t0, t0, 16);
7248 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7249 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7250#endif
7251 tcg_temp_free(t0);
0487d6a8
JM		 7252}
7253
6a6ae23f
AJ		 7254static always_inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr)
7255{
7256 TCGv t0 = tcg_temp_new();
76db3ba4 7257 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 7258#if defined(TARGET_PPC64)
7259 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7260 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7261#else
7262 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7263 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7264#endif
7265 tcg_temp_free(t0);
0487d6a8
JM		 7266}
7267
6a6ae23f
AJ		 7268static always_inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr)
7269{
7270 TCGv t0 = tcg_temp_new();
76db3ba4 7271 gen_qemu_ld16s(ctx, t0, addr);
6a6ae23f
AJ		 7272#if defined(TARGET_PPC64)
7273 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7274 tcg_gen_ext32u_tl(t0, t0);
7275 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7276#else
7277 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7278 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7279#endif
7280 tcg_temp_free(t0);
7281}
7282
7283static always_inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr)
7284{
7285 TCGv t0 = tcg_temp_new();
7286#if defined(TARGET_PPC64)
76db3ba4 7287 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 7288 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
76db3ba4
AJ		 7289 gen_addr_add(ctx, addr, addr, 2);
7290 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 7291 tcg_gen_shli_tl(t0, t0, 16);
7292 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7293#else
76db3ba4 7294 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 7295 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
76db3ba4
AJ		 7296 gen_addr_add(ctx, addr, addr, 2);
7297 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 7298 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
7299#endif
7300 tcg_temp_free(t0);
7301}
7302
7303static always_inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr)
7304{
7305#if defined(TARGET_PPC64)
7306 TCGv t0 = tcg_temp_new();
76db3ba4
AJ		 7307 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7308 gen_addr_add(ctx, addr, addr, 2);
7309 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 7310 tcg_gen_shli_tl(t0, t0, 32);
7311 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7312 tcg_temp_free(t0);
7313#else
76db3ba4
AJ		 7314 gen_qemu_ld16u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7315 gen_addr_add(ctx, addr, addr, 2);
7316 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
6a6ae23f
AJ		 7317#endif
7318}
7319
7320static always_inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr)
7321{
7322#if defined(TARGET_PPC64)
7323 TCGv t0 = tcg_temp_new();
76db3ba4 7324 gen_qemu_ld16s(ctx, t0, addr);
6a6ae23f 7325 tcg_gen_ext32u_tl(cpu_gpr[rD(ctx->opcode)], t0);
76db3ba4
AJ		 7326 gen_addr_add(ctx, addr, addr, 2);
7327 gen_qemu_ld16s(ctx, t0, addr);
6a6ae23f
AJ		 7328 tcg_gen_shli_tl(t0, t0, 32);
7329 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7330 tcg_temp_free(t0);
7331#else
76db3ba4
AJ		 7332 gen_qemu_ld16s(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7333 gen_addr_add(ctx, addr, addr, 2);
7334 gen_qemu_ld16s(ctx, cpu_gpr[rD(ctx->opcode)], addr);
6a6ae23f
AJ		 7335#endif
7336}
7337
7338static always_inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr)
7339{
7340 TCGv t0 = tcg_temp_new();
76db3ba4 7341 gen_qemu_ld32u(ctx, t0, addr);
0487d6a8 7342#if defined(TARGET_PPC64)
6a6ae23f
AJ		 7343 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7344 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7345#else
7346 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7347 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7348#endif
7349 tcg_temp_free(t0);
7350}
7351
7352static always_inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr)
7353{
7354 TCGv t0 = tcg_temp_new();
7355#if defined(TARGET_PPC64)
76db3ba4 7356 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 7357 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7358 tcg_gen_shli_tl(t0, t0, 32);
7359 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
76db3ba4
AJ		 7360 gen_addr_add(ctx, addr, addr, 2);
7361 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 7362 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7363 tcg_gen_shli_tl(t0, t0, 16);
7364 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7365#else
76db3ba4 7366 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 7367 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7368 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
76db3ba4
AJ		 7369 gen_addr_add(ctx, addr, addr, 2);
7370 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 7371 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
7372 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
0487d6a8 7373#endif
6a6ae23f
AJ		 7374 tcg_temp_free(t0);
7375}
7376
7377static always_inline void gen_op_evstdd(DisasContext *ctx, TCGv addr)
7378{
7379#if defined(TARGET_PPC64)
76db3ba4 7380 gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], addr);
0487d6a8 7381#else
6a6ae23f
AJ		 7382 TCGv_i64 t0 = tcg_temp_new_i64();
7383 tcg_gen_concat_i32_i64(t0, cpu_gpr[rS(ctx->opcode)], cpu_gprh[rS(ctx->opcode)]);
76db3ba4 7384 gen_qemu_st64(ctx, t0, addr);
6a6ae23f
AJ		 7385 tcg_temp_free_i64(t0);
7386#endif
7387}
7388
7389static always_inline void gen_op_evstdw(DisasContext *ctx, TCGv addr)
7390{
0487d6a8 7391#if defined(TARGET_PPC64)
6a6ae23f
AJ		 7392 TCGv t0 = tcg_temp_new();
7393 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
76db3ba4 7394 gen_qemu_st32(ctx, t0, addr);
6a6ae23f
AJ		 7395 tcg_temp_free(t0);
7396#else
76db3ba4 7397 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
6a6ae23f 7398#endif
76db3ba4
AJ		 7399 gen_addr_add(ctx, addr, addr, 4);
7400 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
6a6ae23f
AJ		 7401}
7402
7403static always_inline void gen_op_evstdh(DisasContext *ctx, TCGv addr)
7404{
7405 TCGv t0 = tcg_temp_new();
7406#if defined(TARGET_PPC64)
7407 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
7408#else
7409 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
7410#endif
76db3ba4
AJ		 7411 gen_qemu_st16(ctx, t0, addr);
7412 gen_addr_add(ctx, addr, addr, 2);
6a6ae23f
AJ		 7413#if defined(TARGET_PPC64)
7414 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
76db3ba4 7415 gen_qemu_st16(ctx, t0, addr);
6a6ae23f 7416#else
76db3ba4 7417 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
6a6ae23f 7418#endif
76db3ba4 7419 gen_addr_add(ctx, addr, addr, 2);
6a6ae23f 7420 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
76db3ba4 7421 gen_qemu_st16(ctx, t0, addr);
6a6ae23f 7422 tcg_temp_free(t0);
76db3ba4
AJ		 7423 gen_addr_add(ctx, addr, addr, 2);
7424 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
6a6ae23f
AJ		 7425}
7426
7427static always_inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr)
7428{
7429 TCGv t0 = tcg_temp_new();
7430#if defined(TARGET_PPC64)
7431 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
7432#else
7433 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
7434#endif
76db3ba4
AJ		 7435 gen_qemu_st16(ctx, t0, addr);
7436 gen_addr_add(ctx, addr, addr, 2);
6a6ae23f 7437 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
76db3ba4 7438 gen_qemu_st16(ctx, t0, addr);
6a6ae23f
AJ		 7439 tcg_temp_free(t0);
7440}
7441
7442static always_inline void gen_op_evstwho(DisasContext *ctx, TCGv addr)
7443{
7444#if defined(TARGET_PPC64)
7445 TCGv t0 = tcg_temp_new();
7446 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
76db3ba4 7447 gen_qemu_st16(ctx, t0, addr);
6a6ae23f
AJ		 7448 tcg_temp_free(t0);
7449#else
76db3ba4 7450 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
6a6ae23f 7451#endif
76db3ba4
AJ		 7452 gen_addr_add(ctx, addr, addr, 2);
7453 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
6a6ae23f
AJ		 7454}
7455
7456static always_inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr)
7457{
7458#if defined(TARGET_PPC64)
7459 TCGv t0 = tcg_temp_new();
7460 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
76db3ba4 7461 gen_qemu_st32(ctx, t0, addr);
6a6ae23f
AJ		 7462 tcg_temp_free(t0);
7463#else
76db3ba4 7464 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
6a6ae23f
AJ		 7465#endif
7466}
7467
7468static always_inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr)
7469{
76db3ba4 7470 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
6a6ae23f
AJ		 7471}
7472
7473#define GEN_SPEOP_LDST(name, opc2, sh) \
76db3ba4 7474GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE) \
6a6ae23f
AJ		 7475{ \
7476 TCGv t0; \
7477 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 7478 gen_exception(ctx, POWERPC_EXCP_APU); \
6a6ae23f
AJ		 7479 return; \
7480 } \
76db3ba4 7481 gen_set_access_type(ctx, ACCESS_INT); \
6a6ae23f
AJ		 7482 t0 = tcg_temp_new(); \
7483 if (Rc(ctx->opcode)) { \
76db3ba4 7484 gen_addr_spe_imm_index(ctx, t0, sh); \
6a6ae23f 7485 } else { \
76db3ba4 7486 gen_addr_reg_index(ctx, t0); \
6a6ae23f
AJ		 7487 } \
7488 gen_op_##name(ctx, t0); \
7489 tcg_temp_free(t0); \
7490}
7491
7492GEN_SPEOP_LDST(evldd, 0x00, 3);
7493GEN_SPEOP_LDST(evldw, 0x01, 3);
7494GEN_SPEOP_LDST(evldh, 0x02, 3);
7495GEN_SPEOP_LDST(evlhhesplat, 0x04, 1);
7496GEN_SPEOP_LDST(evlhhousplat, 0x06, 1);
7497GEN_SPEOP_LDST(evlhhossplat, 0x07, 1);
7498GEN_SPEOP_LDST(evlwhe, 0x08, 2);
7499GEN_SPEOP_LDST(evlwhou, 0x0A, 2);
7500GEN_SPEOP_LDST(evlwhos, 0x0B, 2);
7501GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2);
7502GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2);
7503
7504GEN_SPEOP_LDST(evstdd, 0x10, 3);
7505GEN_SPEOP_LDST(evstdw, 0x11, 3);
7506GEN_SPEOP_LDST(evstdh, 0x12, 3);
7507GEN_SPEOP_LDST(evstwhe, 0x18, 2);
7508GEN_SPEOP_LDST(evstwho, 0x1A, 2);
7509GEN_SPEOP_LDST(evstwwe, 0x1C, 2);
7510GEN_SPEOP_LDST(evstwwo, 0x1E, 2);
0487d6a8
JM		 7511
7512/* Multiply and add - TODO */
7513#if 0
7514GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0x00000000, PPC_SPE);
7515GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0x00000000, PPC_SPE);
7516GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, PPC_SPE);
7517GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0x00000000, PPC_SPE);
7518GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, PPC_SPE);
7519GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0x00000000, PPC_SPE);
7520GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0x00000000, PPC_SPE);
7521GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0x00000000, PPC_SPE);
7522GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, PPC_SPE);
7523GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0x00000000, PPC_SPE);
7524GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, PPC_SPE);
7525GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0x00000000, PPC_SPE);
7526
7527GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0x00000000, PPC_SPE);
7528GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, PPC_SPE);
7529GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, PPC_SPE);
7530GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0x00000000, PPC_SPE);
7531GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0x00000000, PPC_SPE);
7532GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, PPC_SPE);
7533GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0x00000000, PPC_SPE);
7534GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0x00000000, PPC_SPE);
7535GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, PPC_SPE);
7536GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, PPC_SPE);
7537GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0x00000000, PPC_SPE);
7538GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0x00000000, PPC_SPE);
7539GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, PPC_SPE);
7540GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0x00000000, PPC_SPE);
7541
7542GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, PPC_SPE);
7543GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, PPC_SPE);
7544GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, PPC_SPE);
7545GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, PPC_SPE);
7546GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, PPC_SPE);
7547GEN_SPE(evmra, speundef, 0x07, 0x13, 0x0000F800, PPC_SPE);
7548
7549GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, PPC_SPE);
7550GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0x00000000, PPC_SPE);
7551GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, PPC_SPE);
7552GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0x00000000, PPC_SPE);
7553GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, PPC_SPE);
7554GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0x00000000, PPC_SPE);
7555GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, PPC_SPE);
7556GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0x00000000, PPC_SPE);
7557GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, PPC_SPE);
7558GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0x00000000, PPC_SPE);
7559GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, PPC_SPE);
7560GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0x00000000, PPC_SPE);
7561
7562GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, PPC_SPE);
7563GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, PPC_SPE);
7564GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0x00000000, PPC_SPE);
7565GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, PPC_SPE);
7566GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0x00000000, PPC_SPE);
7567
7568GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, PPC_SPE);
7569GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0x00000000, PPC_SPE);
7570GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, PPC_SPE);
7571GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0x00000000, PPC_SPE);
7572GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, PPC_SPE);
7573GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0x00000000, PPC_SPE);
7574GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, PPC_SPE);
7575GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0x00000000, PPC_SPE);
7576GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, PPC_SPE);
7577GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0x00000000, PPC_SPE);
7578GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, PPC_SPE);
7579GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0x00000000, PPC_SPE);
7580
7581GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, PPC_SPE);
7582GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, PPC_SPE);
7583GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0x00000000, PPC_SPE);
7584GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, PPC_SPE);
7585GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0x00000000, PPC_SPE);
7586#endif
7587
7588/*** SPE floating-point extension ***/
1c97856d
AJ		 7589#if defined(TARGET_PPC64)
7590#define GEN_SPEFPUOP_CONV_32_32(name) \
b068d6a7 7591static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8 7592{ \
1c97856d
AJ		 7593 TCGv_i32 t0; \
7594 TCGv t1; \
7595 t0 = tcg_temp_new_i32(); \
7596 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
7597 gen_helper_##name(t0, t0); \
7598 t1 = tcg_temp_new(); \
7599 tcg_gen_extu_i32_tl(t1, t0); \
7600 tcg_temp_free_i32(t0); \
7601 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
7602 0xFFFFFFFF00000000ULL); \
7603 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
7604 tcg_temp_free(t1); \
0487d6a8 7605}
1c97856d
AJ		 7606#define GEN_SPEFPUOP_CONV_32_64(name) \
7607static always_inline void gen_##name (DisasContext *ctx) \
7608{ \
7609 TCGv_i32 t0; \
7610 TCGv t1; \
7611 t0 = tcg_temp_new_i32(); \
7612 gen_helper_##name(t0, cpu_gpr[rB(ctx->opcode)]); \
7613 t1 = tcg_temp_new(); \
7614 tcg_gen_extu_i32_tl(t1, t0); \
7615 tcg_temp_free_i32(t0); \
7616 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
7617 0xFFFFFFFF00000000ULL); \
7618 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
7619 tcg_temp_free(t1); \
7620}
7621#define GEN_SPEFPUOP_CONV_64_32(name) \
7622static always_inline void gen_##name (DisasContext *ctx) \
7623{ \
7624 TCGv_i32 t0 = tcg_temp_new_i32(); \
7625 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
7626 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], t0); \
7627 tcg_temp_free_i32(t0); \
7628}
7629#define GEN_SPEFPUOP_CONV_64_64(name) \
7630static always_inline void gen_##name (DisasContext *ctx) \
7631{ \
7632 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7633}
7634#define GEN_SPEFPUOP_ARITH2_32_32(name) \
57951c27
AJ		 7635static always_inline void gen_##name (DisasContext *ctx) \
7636{ \
1c97856d
AJ		 7637 TCGv_i32 t0, t1; \
7638 TCGv_i64 t2; \
57951c27 7639 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 7640 gen_exception(ctx, POWERPC_EXCP_APU); \
57951c27
AJ		 7641 return; \
7642 } \
1c97856d
AJ		 7643 t0 = tcg_temp_new_i32(); \
7644 t1 = tcg_temp_new_i32(); \
7645 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7646 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
7647 gen_helper_##name(t0, t0, t1); \
7648 tcg_temp_free_i32(t1); \
7649 t2 = tcg_temp_new(); \
7650 tcg_gen_extu_i32_tl(t2, t0); \
7651 tcg_temp_free_i32(t0); \
7652 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
7653 0xFFFFFFFF00000000ULL); \
7654 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t2); \
7655 tcg_temp_free(t2); \
57951c27 7656}
1c97856d 7657#define GEN_SPEFPUOP_ARITH2_64_64(name) \
57951c27
AJ		 7658static always_inline void gen_##name (DisasContext *ctx) \
7659{ \
7660 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 7661 gen_exception(ctx, POWERPC_EXCP_APU); \
57951c27
AJ		 7662 return; \
7663 } \
1c97856d
AJ		 7664 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
7665 cpu_gpr[rB(ctx->opcode)]); \
57951c27 7666}
1c97856d 7667#define GEN_SPEFPUOP_COMP_32(name) \
57951c27
AJ		 7668static always_inline void gen_##name (DisasContext *ctx) \
7669{ \
1c97856d 7670 TCGv_i32 t0, t1; \
57951c27 7671 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 7672 gen_exception(ctx, POWERPC_EXCP_APU); \
57951c27
AJ		 7673 return; \
7674 } \
1c97856d
AJ		 7675 t0 = tcg_temp_new_i32(); \
7676 t1 = tcg_temp_new_i32(); \
7677 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7678 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
7679 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], t0, t1); \
7680 tcg_temp_free_i32(t0); \
7681 tcg_temp_free_i32(t1); \
7682}
7683#define GEN_SPEFPUOP_COMP_64(name) \
7684static always_inline void gen_##name (DisasContext *ctx) \
7685{ \
7686 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 7687 gen_exception(ctx, POWERPC_EXCP_APU); \
1c97856d
AJ		 7688 return; \
7689 } \
7690 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
7691 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7692}
7693#else
7694#define GEN_SPEFPUOP_CONV_32_32(name) \
7695static always_inline void gen_##name (DisasContext *ctx) \
7696{ \
7697 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
57951c27 7698}
1c97856d
AJ		 7699#define GEN_SPEFPUOP_CONV_32_64(name) \
7700static always_inline void gen_##name (DisasContext *ctx) \
7701{ \
7702 TCGv_i64 t0 = tcg_temp_new_i64(); \
7703 gen_load_gpr64(t0, rB(ctx->opcode)); \
7704 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], t0); \
7705 tcg_temp_free_i64(t0); \
7706}
7707#define GEN_SPEFPUOP_CONV_64_32(name) \
7708static always_inline void gen_##name (DisasContext *ctx) \
7709{ \
7710 TCGv_i64 t0 = tcg_temp_new_i64(); \
7711 gen_helper_##name(t0, cpu_gpr[rB(ctx->opcode)]); \
7712 gen_store_gpr64(rD(ctx->opcode), t0); \
7713 tcg_temp_free_i64(t0); \
7714}
7715#define GEN_SPEFPUOP_CONV_64_64(name) \
7716static always_inline void gen_##name (DisasContext *ctx) \
7717{ \
7718 TCGv_i64 t0 = tcg_temp_new_i64(); \
7719 gen_load_gpr64(t0, rB(ctx->opcode)); \
7720 gen_helper_##name(t0, t0); \
7721 gen_store_gpr64(rD(ctx->opcode), t0); \
7722 tcg_temp_free_i64(t0); \
7723}
7724#define GEN_SPEFPUOP_ARITH2_32_32(name) \
7725static always_inline void gen_##name (DisasContext *ctx) \
7726{ \
7727 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 7728 gen_exception(ctx, POWERPC_EXCP_APU); \
1c97856d
AJ		 7729 return; \
7730 } \
7731 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], \
7732 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7733}
7734#define GEN_SPEFPUOP_ARITH2_64_64(name) \
7735static always_inline void gen_##name (DisasContext *ctx) \
7736{ \
7737 TCGv_i64 t0, t1; \
7738 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 7739 gen_exception(ctx, POWERPC_EXCP_APU); \
1c97856d
AJ		 7740 return; \
7741 } \
7742 t0 = tcg_temp_new_i64(); \
7743 t1 = tcg_temp_new_i64(); \
7744 gen_load_gpr64(t0, rA(ctx->opcode)); \
7745 gen_load_gpr64(t1, rB(ctx->opcode)); \
7746 gen_helper_##name(t0, t0, t1); \
7747 gen_store_gpr64(rD(ctx->opcode), t0); \
7748 tcg_temp_free_i64(t0); \
7749 tcg_temp_free_i64(t1); \
7750}
7751#define GEN_SPEFPUOP_COMP_32(name) \
7752static always_inline void gen_##name (DisasContext *ctx) \
7753{ \
7754 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 7755 gen_exception(ctx, POWERPC_EXCP_APU); \
1c97856d
AJ		 7756 return; \
7757 } \
7758 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
7759 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7760}
7761#define GEN_SPEFPUOP_COMP_64(name) \
7762static always_inline void gen_##name (DisasContext *ctx) \
7763{ \
7764 TCGv_i64 t0, t1; \
7765 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 7766 gen_exception(ctx, POWERPC_EXCP_APU); \
1c97856d
AJ		 7767 return; \
7768 } \
7769 t0 = tcg_temp_new_i64(); \
7770 t1 = tcg_temp_new_i64(); \
7771 gen_load_gpr64(t0, rA(ctx->opcode)); \
7772 gen_load_gpr64(t1, rB(ctx->opcode)); \
7773 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], t0, t1); \
7774 tcg_temp_free_i64(t0); \
7775 tcg_temp_free_i64(t1); \
7776}
7777#endif
57951c27 7778
0487d6a8
JM		 7779/* Single precision floating-point vectors operations */
7780/* Arithmetic */
1c97856d
AJ		 7781GEN_SPEFPUOP_ARITH2_64_64(evfsadd);
7782GEN_SPEFPUOP_ARITH2_64_64(evfssub);
7783GEN_SPEFPUOP_ARITH2_64_64(evfsmul);
7784GEN_SPEFPUOP_ARITH2_64_64(evfsdiv);
7785static always_inline void gen_evfsabs (DisasContext *ctx)
7786{
7787 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 7788 gen_exception(ctx, POWERPC_EXCP_APU);
1c97856d
AJ		 7789 return;
7790 }
7791#if defined(TARGET_PPC64)
7792 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000080000000LL);
7793#else
7794 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x80000000);
7795 tcg_gen_andi_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
7796#endif
7797}
7798static always_inline void gen_evfsnabs (DisasContext *ctx)
7799{
7800 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 7801 gen_exception(ctx, POWERPC_EXCP_APU);
1c97856d
AJ		 7802 return;
7803 }
7804#if defined(TARGET_PPC64)
7805 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
7806#else
7807 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7808 tcg_gen_ori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
7809#endif
7810}
7811static always_inline void gen_evfsneg (DisasContext *ctx)
7812{
7813 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 7814 gen_exception(ctx, POWERPC_EXCP_APU);
1c97856d
AJ		 7815 return;
7816 }
7817#if defined(TARGET_PPC64)
7818 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
7819#else
7820 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7821 tcg_gen_xori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
7822#endif
7823}
7824
0487d6a8 7825/* Conversion */
1c97856d
AJ		 7826GEN_SPEFPUOP_CONV_64_64(evfscfui);
7827GEN_SPEFPUOP_CONV_64_64(evfscfsi);
7828GEN_SPEFPUOP_CONV_64_64(evfscfuf);
7829GEN_SPEFPUOP_CONV_64_64(evfscfsf);
7830GEN_SPEFPUOP_CONV_64_64(evfsctui);
7831GEN_SPEFPUOP_CONV_64_64(evfsctsi);
7832GEN_SPEFPUOP_CONV_64_64(evfsctuf);
7833GEN_SPEFPUOP_CONV_64_64(evfsctsf);
7834GEN_SPEFPUOP_CONV_64_64(evfsctuiz);
7835GEN_SPEFPUOP_CONV_64_64(evfsctsiz);
7836
0487d6a8 7837/* Comparison */
1c97856d
AJ		 7838GEN_SPEFPUOP_COMP_64(evfscmpgt);
7839GEN_SPEFPUOP_COMP_64(evfscmplt);
7840GEN_SPEFPUOP_COMP_64(evfscmpeq);
7841GEN_SPEFPUOP_COMP_64(evfststgt);
7842GEN_SPEFPUOP_COMP_64(evfststlt);
7843GEN_SPEFPUOP_COMP_64(evfststeq);
0487d6a8
JM		 7844
7845/* Opcodes definitions */
7846GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, PPC_SPEFPU); //
7847GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, PPC_SPEFPU); //
7848GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, PPC_SPEFPU); //
7849GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, PPC_SPEFPU); //
7850GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, PPC_SPEFPU); //
7851GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, PPC_SPEFPU); //
7852GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, PPC_SPEFPU); //
7853GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, PPC_SPEFPU); //
7854GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, PPC_SPEFPU); //
7855GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, PPC_SPEFPU); //
7856GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, PPC_SPEFPU); //
7857GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, PPC_SPEFPU); //
7858GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, PPC_SPEFPU); //
7859GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, PPC_SPEFPU); //
7860
7861/* Single precision floating-point operations */
7862/* Arithmetic */
1c97856d
AJ		 7863GEN_SPEFPUOP_ARITH2_32_32(efsadd);
7864GEN_SPEFPUOP_ARITH2_32_32(efssub);
7865GEN_SPEFPUOP_ARITH2_32_32(efsmul);
7866GEN_SPEFPUOP_ARITH2_32_32(efsdiv);
7867static always_inline void gen_efsabs (DisasContext *ctx)
7868{
7869 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 7870 gen_exception(ctx, POWERPC_EXCP_APU);
1c97856d
AJ		 7871 return;
7872 }
7873 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL);
7874}
7875static always_inline void gen_efsnabs (DisasContext *ctx)
7876{
7877 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 7878 gen_exception(ctx, POWERPC_EXCP_APU);
1c97856d
AJ		 7879 return;
7880 }
7881 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7882}
7883static always_inline void gen_efsneg (DisasContext *ctx)
7884{
7885 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 7886 gen_exception(ctx, POWERPC_EXCP_APU);
1c97856d
AJ		 7887 return;
7888 }
7889 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7890}
7891
0487d6a8 7892/* Conversion */
1c97856d
AJ		 7893GEN_SPEFPUOP_CONV_32_32(efscfui);
7894GEN_SPEFPUOP_CONV_32_32(efscfsi);
7895GEN_SPEFPUOP_CONV_32_32(efscfuf);
7896GEN_SPEFPUOP_CONV_32_32(efscfsf);
7897GEN_SPEFPUOP_CONV_32_32(efsctui);
7898GEN_SPEFPUOP_CONV_32_32(efsctsi);
7899GEN_SPEFPUOP_CONV_32_32(efsctuf);
7900GEN_SPEFPUOP_CONV_32_32(efsctsf);
7901GEN_SPEFPUOP_CONV_32_32(efsctuiz);
7902GEN_SPEFPUOP_CONV_32_32(efsctsiz);
7903GEN_SPEFPUOP_CONV_32_64(efscfd);
7904
0487d6a8 7905/* Comparison */
1c97856d
AJ		 7906GEN_SPEFPUOP_COMP_32(efscmpgt);
7907GEN_SPEFPUOP_COMP_32(efscmplt);
7908GEN_SPEFPUOP_COMP_32(efscmpeq);
7909GEN_SPEFPUOP_COMP_32(efststgt);
7910GEN_SPEFPUOP_COMP_32(efststlt);
7911GEN_SPEFPUOP_COMP_32(efststeq);
0487d6a8
JM		 7912
7913/* Opcodes definitions */
05332d70 7914GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, PPC_SPEFPU); //
0487d6a8
JM		 7915GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, PPC_SPEFPU); //
7916GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, PPC_SPEFPU); //
7917GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, PPC_SPEFPU); //
7918GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, PPC_SPEFPU); //
7919GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, PPC_SPEFPU); //
7920GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, PPC_SPEFPU); //
7921GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, PPC_SPEFPU); //
7922GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, PPC_SPEFPU); //
7923GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, PPC_SPEFPU); //
9ceb2a77
TS		 7924GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, PPC_SPEFPU); //
7925GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, PPC_SPEFPU); //
0487d6a8
JM		 7926GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, PPC_SPEFPU); //
7927GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, PPC_SPEFPU); //
7928
7929/* Double precision floating-point operations */
7930/* Arithmetic */
1c97856d
AJ		 7931GEN_SPEFPUOP_ARITH2_64_64(efdadd);
7932GEN_SPEFPUOP_ARITH2_64_64(efdsub);
7933GEN_SPEFPUOP_ARITH2_64_64(efdmul);
7934GEN_SPEFPUOP_ARITH2_64_64(efddiv);
7935static always_inline void gen_efdabs (DisasContext *ctx)
7936{
7937 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 7938 gen_exception(ctx, POWERPC_EXCP_APU);
1c97856d
AJ		 7939 return;
7940 }
7941#if defined(TARGET_PPC64)
7942 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000000000000LL);
7943#else
7944 tcg_gen_andi_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
7945#endif
7946}
7947static always_inline void gen_efdnabs (DisasContext *ctx)
7948{
7949 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 7950 gen_exception(ctx, POWERPC_EXCP_APU);
1c97856d
AJ		 7951 return;
7952 }
7953#if defined(TARGET_PPC64)
7954 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
7955#else
7956 tcg_gen_ori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
7957#endif
7958}
7959static always_inline void gen_efdneg (DisasContext *ctx)
7960{
7961 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 7962 gen_exception(ctx, POWERPC_EXCP_APU);
1c97856d
AJ		 7963 return;
7964 }
7965#if defined(TARGET_PPC64)
7966 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
7967#else
7968 tcg_gen_xori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
7969#endif
7970}
7971
0487d6a8 7972/* Conversion */
1c97856d
AJ		 7973GEN_SPEFPUOP_CONV_64_32(efdcfui);
7974GEN_SPEFPUOP_CONV_64_32(efdcfsi);
7975GEN_SPEFPUOP_CONV_64_32(efdcfuf);
7976GEN_SPEFPUOP_CONV_64_32(efdcfsf);
7977GEN_SPEFPUOP_CONV_32_64(efdctui);
7978GEN_SPEFPUOP_CONV_32_64(efdctsi);
7979GEN_SPEFPUOP_CONV_32_64(efdctuf);
7980GEN_SPEFPUOP_CONV_32_64(efdctsf);
7981GEN_SPEFPUOP_CONV_32_64(efdctuiz);
7982GEN_SPEFPUOP_CONV_32_64(efdctsiz);
7983GEN_SPEFPUOP_CONV_64_32(efdcfs);
7984GEN_SPEFPUOP_CONV_64_64(efdcfuid);
7985GEN_SPEFPUOP_CONV_64_64(efdcfsid);
7986GEN_SPEFPUOP_CONV_64_64(efdctuidz);
7987GEN_SPEFPUOP_CONV_64_64(efdctsidz);
0487d6a8 7988
0487d6a8 7989/* Comparison */
1c97856d
AJ		 7990GEN_SPEFPUOP_COMP_64(efdcmpgt);
7991GEN_SPEFPUOP_COMP_64(efdcmplt);
7992GEN_SPEFPUOP_COMP_64(efdcmpeq);
7993GEN_SPEFPUOP_COMP_64(efdtstgt);
7994GEN_SPEFPUOP_COMP_64(efdtstlt);
7995GEN_SPEFPUOP_COMP_64(efdtsteq);
0487d6a8
JM		 7996
7997/* Opcodes definitions */
7998GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, PPC_SPEFPU); //
7999GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, PPC_SPEFPU); //
8000GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, PPC_SPEFPU); //
8001GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, PPC_SPEFPU); //
8002GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, PPC_SPEFPU); //
8003GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, PPC_SPEFPU); //
8004GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, PPC_SPEFPU); //
8005GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, PPC_SPEFPU); //
8006GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, PPC_SPEFPU); //
8007GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, PPC_SPEFPU); //
8008GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, PPC_SPEFPU); //
8009GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, PPC_SPEFPU); //
8010GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, PPC_SPEFPU); //
8011GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, PPC_SPEFPU); //
8012GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, PPC_SPEFPU); //
8013GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, PPC_SPEFPU); //
0487d6a8 8014
79aceca5
FB		 8015/* End opcode list */
8016GEN_OPCODE_MARK(end);
8017
3fc6c082 8018#include "translate_init.c"
0411a972 8019#include "helper_regs.h"
79aceca5 8020
9a64fbe4 8021/*****************************************************************************/
3fc6c082 8022/* Misc PowerPC helpers */
36081602
JM		 8023void cpu_dump_state (CPUState *env, FILE *f,
8024 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
8025 int flags)
79aceca5 8026{
3fc6c082
FB		 8027#define RGPL 4
8028#define RFPL 4
3fc6c082 8029
79aceca5
FB		 8030 int i;
8031
077fc206 8032 cpu_fprintf(f, "NIP " ADDRX " LR " ADDRX " CTR " ADDRX " XER %08x\n",
3d7b417e 8033 env->nip, env->lr, env->ctr, env->xer);
6b542af7
JM		 8034 cpu_fprintf(f, "MSR " ADDRX " HID0 " ADDRX " HF " ADDRX " idx %d\n",
8035 env->msr, env->spr[SPR_HID0], env->hflags, env->mmu_idx);
d9bce9d9 8036#if !defined(NO_TIMER_DUMP)
077fc206 8037 cpu_fprintf(f, "TB %08x %08x "
76a66253
JM		 8038#if !defined(CONFIG_USER_ONLY)
8039 "DECR %08x"
8040#endif
8041 "\n",
077fc206 8042 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
76a66253
JM		 8043#if !defined(CONFIG_USER_ONLY)
8044 , cpu_ppc_load_decr(env)
8045#endif
8046 );
077fc206 8047#endif
76a66253 8048 for (i = 0; i < 32; i++) {
3fc6c082
FB		 8049 if ((i & (RGPL - 1)) == 0)
8050 cpu_fprintf(f, "GPR%02d", i);
6b542af7 8051 cpu_fprintf(f, " " REGX, ppc_dump_gpr(env, i));
3fc6c082 8052 if ((i & (RGPL - 1)) == (RGPL - 1))
7fe48483 8053 cpu_fprintf(f, "\n");
76a66253 8054 }
3fc6c082 8055 cpu_fprintf(f, "CR ");
76a66253 8056 for (i = 0; i < 8; i++)
7fe48483
FB		 8057 cpu_fprintf(f, "%01x", env->crf[i]);
8058 cpu_fprintf(f, " [");
76a66253
JM		 8059 for (i = 0; i < 8; i++) {
8060 char a = '-';
8061 if (env->crf[i] & 0x08)
8062 a = 'L';
8063 else if (env->crf[i] & 0x04)
8064 a = 'G';
8065 else if (env->crf[i] & 0x02)
8066 a = 'E';
7fe48483 8067 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
76a66253 8068 }
6b542af7 8069 cpu_fprintf(f, " ] RES " ADDRX "\n", env->reserve);
3fc6c082
FB		 8070 for (i = 0; i < 32; i++) {
8071 if ((i & (RFPL - 1)) == 0)
8072 cpu_fprintf(f, "FPR%02d", i);
26a76461 8073 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
3fc6c082 8074 if ((i & (RFPL - 1)) == (RFPL - 1))
7fe48483 8075 cpu_fprintf(f, "\n");
79aceca5 8076 }
7889270a 8077 cpu_fprintf(f, "FPSCR %08x\n", env->fpscr);
f2e63a42 8078#if !defined(CONFIG_USER_ONLY)
6b542af7 8079 cpu_fprintf(f, "SRR0 " ADDRX " SRR1 " ADDRX " SDR1 " ADDRX "\n",
3fc6c082 8080 env->spr[SPR_SRR0], env->spr[SPR_SRR1], env->sdr1);
f2e63a42 8081#endif
79aceca5 8082
3fc6c082
FB		 8083#undef RGPL
8084#undef RFPL
79aceca5
FB		 8085}
8086
76a66253
JM		 8087void cpu_dump_statistics (CPUState *env, FILE*f,
8088 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
8089 int flags)
8090{
8091#if defined(DO_PPC_STATISTICS)
8092 opc_handler_t **t1, **t2, **t3, *handler;
8093 int op1, op2, op3;
8094
8095 t1 = env->opcodes;
8096 for (op1 = 0; op1 < 64; op1++) {
8097 handler = t1[op1];
8098 if (is_indirect_opcode(handler)) {
8099 t2 = ind_table(handler);
8100 for (op2 = 0; op2 < 32; op2++) {
8101 handler = t2[op2];
8102 if (is_indirect_opcode(handler)) {
8103 t3 = ind_table(handler);
8104 for (op3 = 0; op3 < 32; op3++) {
8105 handler = t3[op3];
8106 if (handler->count == 0)
8107 continue;
8108 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
8109 "%016llx %lld\n",
8110 op1, op2, op3, op1, (op3 << 5) | op2,
8111 handler->oname,
8112 handler->count, handler->count);
8113 }
8114 } else {
8115 if (handler->count == 0)
8116 continue;
8117 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
8118 "%016llx %lld\n",
8119 op1, op2, op1, op2, handler->oname,
8120 handler->count, handler->count);
8121 }
8122 }
8123 } else {
8124 if (handler->count == 0)
8125 continue;
8126 cpu_fprintf(f, "%02x (%02x ) %16s: %016llx %lld\n",
8127 op1, op1, handler->oname,
8128 handler->count, handler->count);
8129 }
8130 }
8131#endif
8132}
8133
9a64fbe4 8134/*****************************************************************************/
2cfc5f17
TS		 8135static always_inline void gen_intermediate_code_internal (CPUState *env,
8136 TranslationBlock *tb,
8137 int search_pc)
79aceca5 8138{
9fddaa0c 8139 DisasContext ctx, *ctxp = &ctx;
79aceca5 8140 opc_handler_t **table, *handler;
0fa85d43 8141 target_ulong pc_start;
79aceca5 8142 uint16_t *gen_opc_end;
a1d1bb31 8143 CPUBreakpoint *bp;
79aceca5 8144 int j, lj = -1;
2e70f6ef
PB		 8145 int num_insns;
8146 int max_insns;
79aceca5
FB		 8147
8148 pc_start = tb->pc;
79aceca5 8149 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
046d6672 8150 ctx.nip = pc_start;
79aceca5 8151 ctx.tb = tb;
e1833e1f 8152 ctx.exception = POWERPC_EXCP_NONE;
3fc6c082 8153 ctx.spr_cb = env->spr_cb;
76db3ba4
AJ		 8154 ctx.mem_idx = env->mmu_idx;
8155 ctx.access_type = -1;
8156 ctx.le_mode = env->hflags & (1 << MSR_LE) ? 1 : 0;
d9bce9d9
JM		 8157#if defined(TARGET_PPC64)
8158 ctx.sf_mode = msr_sf;
9a64fbe4 8159#endif
3cc62370 8160 ctx.fpu_enabled = msr_fp;
a9d9eb8f 8161 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
d26bfc9a
JM		 8162 ctx.spe_enabled = msr_spe;
8163 else
8164 ctx.spe_enabled = 0;
a9d9eb8f
JM		 8165 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
8166 ctx.altivec_enabled = msr_vr;
8167 else
8168 ctx.altivec_enabled = 0;
d26bfc9a 8169 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
8cbcb4fa 8170 ctx.singlestep_enabled = CPU_SINGLE_STEP;
d26bfc9a 8171 else
8cbcb4fa 8172 ctx.singlestep_enabled = 0;
d26bfc9a 8173 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
8cbcb4fa
AJ		 8174 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
8175 if (unlikely(env->singlestep_enabled))
8176 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
3fc6c082 8177#if defined (DO_SINGLE_STEP) && 0
9a64fbe4
FB		 8178 /* Single step trace mode */
8179 msr_se = 1;
8180#endif
2e70f6ef
PB		 8181 num_insns = 0;
8182 max_insns = tb->cflags & CF_COUNT_MASK;
8183 if (max_insns == 0)
8184 max_insns = CF_COUNT_MASK;
8185
8186 gen_icount_start();
9a64fbe4 8187 /* Set env in case of segfault during code fetch */
e1833e1f 8188 while (ctx.exception == POWERPC_EXCP_NONE && gen_opc_ptr < gen_opc_end) {
c0ce998e
AL		 8189 if (unlikely(!TAILQ_EMPTY(&env->breakpoints))) {
8190 TAILQ_FOREACH(bp, &env->breakpoints, entry) {
a1d1bb31 8191 if (bp->pc == ctx.nip) {
e06fcd75 8192 gen_debug_exception(ctxp);
ea4e754f
FB		 8193 break;
8194 }
8195 }
8196 }
76a66253 8197 if (unlikely(search_pc)) {
79aceca5
FB		 8198 j = gen_opc_ptr - gen_opc_buf;
8199 if (lj < j) {
8200 lj++;
8201 while (lj < j)
8202 gen_opc_instr_start[lj++] = 0;
046d6672 8203 gen_opc_pc[lj] = ctx.nip;
79aceca5 8204 gen_opc_instr_start[lj] = 1;
2e70f6ef 8205 gen_opc_icount[lj] = num_insns;
79aceca5
FB		 8206 }
8207 }
9fddaa0c
FB		 8208#if defined PPC_DEBUG_DISAS
8209 if (loglevel & CPU_LOG_TB_IN_ASM) {
79aceca5 8210 fprintf(logfile, "----------------\n");
1b9eb036 8211 fprintf(logfile, "nip=" ADDRX " super=%d ir=%d\n",
76db3ba4 8212 ctx.nip, ctx.mem_idx, (int)msr_ir);
9a64fbe4
FB		 8213 }
8214#endif
2e70f6ef
PB		 8215 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
8216 gen_io_start();
76db3ba4 8217 if (unlikely(ctx.le_mode)) {
056401ea
JM		 8218 ctx.opcode = bswap32(ldl_code(ctx.nip));
8219 } else {
8220 ctx.opcode = ldl_code(ctx.nip);
111bfab3 8221 }
9fddaa0c
FB		 8222#if defined PPC_DEBUG_DISAS
8223 if (loglevel & CPU_LOG_TB_IN_ASM) {
111bfab3 8224 fprintf(logfile, "translate opcode %08x (%02x %02x %02x) (%s)\n",
9a64fbe4 8225 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
056401ea 8226 opc3(ctx.opcode), little_endian ? "little" : "big");
79aceca5
FB		 8227 }
8228#endif
046d6672 8229 ctx.nip += 4;
3fc6c082 8230 table = env->opcodes;
2e70f6ef 8231 num_insns++;
79aceca5
FB		 8232 handler = table[opc1(ctx.opcode)];
8233 if (is_indirect_opcode(handler)) {
8234 table = ind_table(handler);
8235 handler = table[opc2(ctx.opcode)];
8236 if (is_indirect_opcode(handler)) {
8237 table = ind_table(handler);
8238 handler = table[opc3(ctx.opcode)];
8239 }
8240 }
8241 /* Is opcode *REALLY* valid ? */
76a66253 8242 if (unlikely(handler->handler == &gen_invalid)) {
4a057712 8243 if (loglevel != 0) {
76a66253 8244 fprintf(logfile, "invalid/unsupported opcode: "
6b542af7 8245 "%02x - %02x - %02x (%08x) " ADDRX " %d\n",
76a66253 8246 opc1(ctx.opcode), opc2(ctx.opcode),
0411a972 8247 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
4b3686fa
FB		 8248 } else {
8249 printf("invalid/unsupported opcode: "
6b542af7 8250 "%02x - %02x - %02x (%08x) " ADDRX " %d\n",
4b3686fa 8251 opc1(ctx.opcode), opc2(ctx.opcode),
0411a972 8252 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
4b3686fa 8253 }
76a66253
JM		 8254 } else {
8255 if (unlikely((ctx.opcode & handler->inval) != 0)) {
4a057712 8256 if (loglevel != 0) {
79aceca5 8257 fprintf(logfile, "invalid bits: %08x for opcode: "
6b542af7 8258 "%02x - %02x - %02x (%08x) " ADDRX "\n",
79aceca5
FB		 8259 ctx.opcode & handler->inval, opc1(ctx.opcode),
8260 opc2(ctx.opcode), opc3(ctx.opcode),
046d6672 8261 ctx.opcode, ctx.nip - 4);
9a64fbe4
FB		 8262 } else {
8263 printf("invalid bits: %08x for opcode: "
6b542af7 8264 "%02x - %02x - %02x (%08x) " ADDRX "\n",
76a66253
JM		 8265 ctx.opcode & handler->inval, opc1(ctx.opcode),
8266 opc2(ctx.opcode), opc3(ctx.opcode),
046d6672 8267 ctx.opcode, ctx.nip - 4);
76a66253 8268 }
e06fcd75 8269 gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL);
4b3686fa 8270 break;
79aceca5 8271 }
79aceca5 8272 }
4b3686fa 8273 (*(handler->handler))(&ctx);
76a66253
JM		 8274#if defined(DO_PPC_STATISTICS)
8275 handler->count++;
8276#endif
9a64fbe4 8277 /* Check trace mode exceptions */
8cbcb4fa
AJ		 8278 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
8279 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
8280 ctx.exception != POWERPC_SYSCALL &&
8281 ctx.exception != POWERPC_EXCP_TRAP &&
8282 ctx.exception != POWERPC_EXCP_BRANCH)) {
e06fcd75 8283 gen_exception(ctxp, POWERPC_EXCP_TRACE);
d26bfc9a 8284 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
2e70f6ef
PB		 8285 (env->singlestep_enabled) ||
8286 num_insns >= max_insns)) {
d26bfc9a
JM		 8287 /* if we reach a page boundary or are single stepping, stop
8288 * generation
8289 */
8dd4983c 8290 break;
76a66253 8291 }
3fc6c082
FB		 8292#if defined (DO_SINGLE_STEP)
8293 break;
8294#endif
8295 }
2e70f6ef
PB		 8296 if (tb->cflags & CF_LAST_IO)
8297 gen_io_end();
e1833e1f 8298 if (ctx.exception == POWERPC_EXCP_NONE) {
c1942362 8299 gen_goto_tb(&ctx, 0, ctx.nip);
e1833e1f 8300 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
8cbcb4fa 8301 if (unlikely(env->singlestep_enabled)) {
e06fcd75 8302 gen_debug_exception(ctxp);
8cbcb4fa 8303 }
76a66253 8304 /* Generate the return instruction */
57fec1fe 8305 tcg_gen_exit_tb(0);
9a64fbe4 8306 }
2e70f6ef 8307 gen_icount_end(tb, num_insns);
79aceca5 8308 *gen_opc_ptr = INDEX_op_end;
76a66253 8309 if (unlikely(search_pc)) {
9a64fbe4
FB		 8310 j = gen_opc_ptr - gen_opc_buf;
8311 lj++;
8312 while (lj <= j)
8313 gen_opc_instr_start[lj++] = 0;
9a64fbe4 8314 } else {
046d6672 8315 tb->size = ctx.nip - pc_start;
2e70f6ef 8316 tb->icount = num_insns;
9a64fbe4 8317 }
d9bce9d9 8318#if defined(DEBUG_DISAS)
9fddaa0c 8319 if (loglevel & CPU_LOG_TB_CPU) {
9a64fbe4 8320 fprintf(logfile, "---------------- excp: %04x\n", ctx.exception);
7fe48483 8321 cpu_dump_state(env, logfile, fprintf, 0);
9fddaa0c
FB		 8322 }
8323 if (loglevel & CPU_LOG_TB_IN_ASM) {
76a66253 8324 int flags;
237c0af0 8325 flags = env->bfd_mach;
76db3ba4 8326 flags |= ctx.le_mode << 16;
0fa85d43 8327 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
76a66253 8328 target_disas(logfile, pc_start, ctx.nip - pc_start, flags);
79aceca5 8329 fprintf(logfile, "\n");
9fddaa0c 8330 }
79aceca5 8331#endif
79aceca5
FB		 8332}
8333
2cfc5f17 8334void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
79aceca5 8335{
2cfc5f17 8336 gen_intermediate_code_internal(env, tb, 0);
79aceca5
FB		 8337}
8338
2cfc5f17 8339void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
79aceca5 8340{
2cfc5f17 8341 gen_intermediate_code_internal(env, tb, 1);
79aceca5 8342}
d2856f1a
AJ		 8343
8344void gen_pc_load(CPUState *env, TranslationBlock *tb,
8345 unsigned long searched_pc, int pc_pos, void *puc)
8346{
d2856f1a 8347 env->nip = gen_opc_pc[pc_pos];
d2856f1a 8348}
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