]> Git Repo - qemu.git/blame - target-ppc/translate.c
projects / qemu.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
target-ppc: remove dead code
[qemu.git] / target-ppc / translate.c
CommitLineData
79aceca5 1/*
3fc6c082 2 * PowerPC emulation for qemu: main translation routines.
5fafdf24 3 *
76a66253 4 * Copyright (c) 2003-2007 Jocelyn Mayer
79aceca5
FB		 5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
c6a1c22b
FB		 20#include <stdarg.h>
21#include <stdlib.h>
22#include <stdio.h>
23#include <string.h>
24#include <inttypes.h>
25
79aceca5 26#include "cpu.h"
c6a1c22b 27#include "exec-all.h"
79aceca5 28#include "disas.h"
57fec1fe 29#include "tcg-op.h"
ca10f867 30#include "qemu-common.h"
79aceca5 31
a7812ae4
PB		 32#include "helper.h"
33#define GEN_HELPER 1
34#include "helper.h"
35
8cbcb4fa
AJ		 36#define CPU_SINGLE_STEP 0x1
37#define CPU_BRANCH_STEP 0x2
38#define GDBSTUB_SINGLE_STEP 0x4
39
a750fc0b 40/* Include definitions for instructions classes and implementations flags */
79aceca5 41//#define DO_SINGLE_STEP
9fddaa0c 42//#define PPC_DEBUG_DISAS
76a66253 43//#define DO_PPC_STATISTICS
7c58044c 44//#define OPTIMIZE_FPRF_UPDATE
79aceca5 45
a750fc0b
JM		 46/*****************************************************************************/
47/* Code translation helpers */
c53be334 48
f78fb44e 49/* global register indexes */
a7812ae4 50static TCGv_ptr cpu_env;
1d542695 51static char cpu_reg_names[10*3 + 22*4 /* GPR */
f78fb44e 52#if !defined(TARGET_PPC64)
1d542695 53 + 10*4 + 22*5 /* SPE GPRh */
f78fb44e 54#endif
a5e26afa 55 + 10*4 + 22*5 /* FPR */
47e4661c
AJ		 56 + 2*(10*6 + 22*7) /* AVRh, AVRl */
57 + 8*5 /* CRF */];
f78fb44e
AJ		 58static TCGv cpu_gpr[32];
59#if !defined(TARGET_PPC64)
60static TCGv cpu_gprh[32];
61#endif
a7812ae4
PB		 62static TCGv_i64 cpu_fpr[32];
63static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
64static TCGv_i32 cpu_crf[8];
bd568f18 65static TCGv cpu_nip;
6527f6ea 66static TCGv cpu_msr;
cfdcd37a
AJ		 67static TCGv cpu_ctr;
68static TCGv cpu_lr;
3d7b417e 69static TCGv cpu_xer;
cf360a32 70static TCGv cpu_reserve;
a7812ae4 71static TCGv_i32 cpu_fpscr;
a7859e89 72static TCGv_i32 cpu_access_type;
f78fb44e
AJ		 73
74/* dyngen register indexes */
8983da70 75static TCGv cpu_T[1];
2e70f6ef
PB		 76
77#include "gen-icount.h"
78
79void ppc_translate_init(void)
80{
f78fb44e
AJ		 81 int i;
82 char* p;
b2437bf2 83 static int done_init = 0;
f78fb44e 84
2e70f6ef
PB		 85 if (done_init)
86 return;
f78fb44e 87
a7812ae4 88 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
1c73fe5b 89#if TARGET_LONG_BITS > HOST_LONG_BITS
a7812ae4 90 cpu_T[0] = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, t0), "T0");
1c73fe5b 91#else
a7812ae4 92 cpu_T[0] = tcg_global_reg_new(TCG_AREG1, "T0");
a7812ae4
PB		 93#endif
94
f78fb44e 95 p = cpu_reg_names;
47e4661c
AJ		 96
97 for (i = 0; i < 8; i++) {
98 sprintf(p, "crf%d", i);
a7812ae4
PB		 99 cpu_crf[i] = tcg_global_mem_new_i32(TCG_AREG0,
100 offsetof(CPUState, crf[i]), p);
47e4661c
AJ		 101 p += 5;
102 }
103
f78fb44e
AJ		 104 for (i = 0; i < 32; i++) {
105 sprintf(p, "r%d", i);
a7812ae4 106 cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0,
f78fb44e
AJ		 107 offsetof(CPUState, gpr[i]), p);
108 p += (i < 10) ? 3 : 4;
109#if !defined(TARGET_PPC64)
110 sprintf(p, "r%dH", i);
a7812ae4
PB		 111 cpu_gprh[i] = tcg_global_mem_new_i32(TCG_AREG0,
112 offsetof(CPUState, gprh[i]), p);
f78fb44e
AJ		 113 p += (i < 10) ? 4 : 5;
114#endif
1d542695 115
a5e26afa 116 sprintf(p, "fp%d", i);
a7812ae4
PB		 117 cpu_fpr[i] = tcg_global_mem_new_i64(TCG_AREG0,
118 offsetof(CPUState, fpr[i]), p);
ec1ac72d 119 p += (i < 10) ? 4 : 5;
a5e26afa 120
1d542695 121 sprintf(p, "avr%dH", i);
fe1e5c53
AJ		 122#ifdef WORDS_BIGENDIAN
123 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
124 offsetof(CPUState, avr[i].u64[0]), p);
125#else
a7812ae4 126 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
fe1e5c53
AJ		 127 offsetof(CPUState, avr[i].u64[1]), p);
128#endif
1d542695 129 p += (i < 10) ? 6 : 7;
ec1ac72d 130
1d542695 131 sprintf(p, "avr%dL", i);
fe1e5c53
AJ		 132#ifdef WORDS_BIGENDIAN
133 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
134 offsetof(CPUState, avr[i].u64[1]), p);
135#else
a7812ae4 136 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
fe1e5c53
AJ		 137 offsetof(CPUState, avr[i].u64[0]), p);
138#endif
1d542695 139 p += (i < 10) ? 6 : 7;
f78fb44e 140 }
f10dc08e 141
a7812ae4 142 cpu_nip = tcg_global_mem_new(TCG_AREG0,
bd568f18
AJ		 143 offsetof(CPUState, nip), "nip");
144
6527f6ea
AJ		 145 cpu_msr = tcg_global_mem_new(TCG_AREG0,
146 offsetof(CPUState, msr), "msr");
147
a7812ae4 148 cpu_ctr = tcg_global_mem_new(TCG_AREG0,
cfdcd37a
AJ		 149 offsetof(CPUState, ctr), "ctr");
150
a7812ae4 151 cpu_lr = tcg_global_mem_new(TCG_AREG0,
cfdcd37a
AJ		 152 offsetof(CPUState, lr), "lr");
153
a7812ae4 154 cpu_xer = tcg_global_mem_new(TCG_AREG0,
3d7b417e
AJ		 155 offsetof(CPUState, xer), "xer");
156
cf360a32
AJ		 157 cpu_reserve = tcg_global_mem_new(TCG_AREG0,
158 offsetof(CPUState, reserve), "reserve");
159
a7812ae4
PB		 160 cpu_fpscr = tcg_global_mem_new_i32(TCG_AREG0,
161 offsetof(CPUState, fpscr), "fpscr");
e1571908 162
a7859e89
AJ		 163 cpu_access_type = tcg_global_mem_new_i32(TCG_AREG0,
164 offsetof(CPUState, access_type), "access_type");
165
f10dc08e 166 /* register helpers */
a7812ae4 167#define GEN_HELPER 2
f10dc08e
AJ		 168#include "helper.h"
169
2e70f6ef
PB		 170 done_init = 1;
171}
172
7c58044c
JM		 173#if defined(OPTIMIZE_FPRF_UPDATE)
174static uint16_t *gen_fprf_buf[OPC_BUF_SIZE];
175static uint16_t **gen_fprf_ptr;
176#endif
79aceca5 177
79aceca5
FB		 178/* internal defines */
179typedef struct DisasContext {
180 struct TranslationBlock *tb;
0fa85d43 181 target_ulong nip;
79aceca5 182 uint32_t opcode;
9a64fbe4 183 uint32_t exception;
3cc62370
FB		 184 /* Routine used to access memory */
185 int mem_idx;
186 /* Translation flags */
9a64fbe4 187#if !defined(CONFIG_USER_ONLY)
79aceca5 188 int supervisor;
d9bce9d9
JM		 189#endif
190#if defined(TARGET_PPC64)
191 int sf_mode;
9a64fbe4 192#endif
3cc62370 193 int fpu_enabled;
a9d9eb8f 194 int altivec_enabled;
0487d6a8 195 int spe_enabled;
3fc6c082 196 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
ea4e754f 197 int singlestep_enabled;
79aceca5
FB		 198} DisasContext;
199
3fc6c082 200struct opc_handler_t {
79aceca5
FB		 201 /* invalid bits */
202 uint32_t inval;
9a64fbe4 203 /* instruction type */
0487d6a8 204 uint64_t type;
79aceca5
FB		 205 /* handler */
206 void (*handler)(DisasContext *ctx);
a750fc0b 207#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
b55266b5 208 const char *oname;
a750fc0b
JM		 209#endif
210#if defined(DO_PPC_STATISTICS)
76a66253
JM		 211 uint64_t count;
212#endif
3fc6c082 213};
79aceca5 214
7c58044c
JM		 215static always_inline void gen_reset_fpstatus (void)
216{
217#ifdef CONFIG_SOFTFLOAT
218 gen_op_reset_fpstatus();
219#endif
220}
221
0f2f39c2 222static always_inline void gen_compute_fprf (TCGv_i64 arg, int set_fprf, int set_rc)
7c58044c 223{
0f2f39c2 224 TCGv_i32 t0 = tcg_temp_new_i32();
af12906f 225
7c58044c
JM		 226 if (set_fprf != 0) {
227 /* This case might be optimized later */
228#if defined(OPTIMIZE_FPRF_UPDATE)
229 *gen_fprf_ptr++ = gen_opc_ptr;
230#endif
0f2f39c2 231 tcg_gen_movi_i32(t0, 1);
af12906f 232 gen_helper_compute_fprf(t0, arg, t0);
a7812ae4 233 if (unlikely(set_rc)) {
0f2f39c2 234 tcg_gen_mov_i32(cpu_crf[1], t0);
a7812ae4 235 }
af12906f 236 gen_helper_float_check_status();
7c58044c
JM		 237 } else if (unlikely(set_rc)) {
238 /* We always need to compute fpcc */
0f2f39c2 239 tcg_gen_movi_i32(t0, 0);
af12906f 240 gen_helper_compute_fprf(t0, arg, t0);
0f2f39c2 241 tcg_gen_mov_i32(cpu_crf[1], t0);
7c58044c 242 if (set_fprf)
af12906f 243 gen_helper_float_check_status();
7c58044c 244 }
af12906f 245
0f2f39c2 246 tcg_temp_free_i32(t0);
7c58044c
JM		 247}
248
249static always_inline void gen_optimize_fprf (void)
250{
251#if defined(OPTIMIZE_FPRF_UPDATE)
252 uint16_t **ptr;
253
254 for (ptr = gen_fprf_buf; ptr != (gen_fprf_ptr - 1); ptr++)
255 *ptr = INDEX_op_nop1;
256 gen_fprf_ptr = gen_fprf_buf;
257#endif
258}
259
a7859e89
AJ		 260static always_inline void gen_set_access_type(int access_type)
261{
262 tcg_gen_movi_i32(cpu_access_type, access_type);
263}
264
b068d6a7 265static always_inline void gen_update_nip (DisasContext *ctx, target_ulong nip)
d9bce9d9
JM		 266{
267#if defined(TARGET_PPC64)
268 if (ctx->sf_mode)
bd568f18 269 tcg_gen_movi_tl(cpu_nip, nip);
d9bce9d9
JM		 270 else
271#endif
bd568f18 272 tcg_gen_movi_tl(cpu_nip, (uint32_t)nip);
d9bce9d9
JM		 273}
274
e1833e1f 275#define GEN_EXCP(ctx, excp, error) \
79aceca5 276do { \
64adab3f
AJ		 277 TCGv_i32 t0 = tcg_const_i32(excp); \
278 TCGv_i32 t1 = tcg_const_i32(error); \
e1833e1f 279 if ((ctx)->exception == POWERPC_EXCP_NONE) { \
d9bce9d9 280 gen_update_nip(ctx, (ctx)->nip); \
9fddaa0c 281 } \
64adab3f
AJ		 282 gen_helper_raise_exception_err(t0, t1); \
283 tcg_temp_free_i32(t0); \
284 tcg_temp_free_i32(t1); \
9fddaa0c 285 ctx->exception = (excp); \
79aceca5
FB		 286} while (0)
287
e1833e1f
JM		 288#define GEN_EXCP_INVAL(ctx) \
289GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \
290 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL)
9fddaa0c 291
e1833e1f
JM		 292#define GEN_EXCP_PRIVOPC(ctx) \
293GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \
294 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_OPC)
9a64fbe4 295
e1833e1f
JM		 296#define GEN_EXCP_PRIVREG(ctx) \
297GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \
298 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG)
299
300#define GEN_EXCP_NO_FP(ctx) \
301GEN_EXCP(ctx, POWERPC_EXCP_FPU, 0)
302
303#define GEN_EXCP_NO_AP(ctx) \
304GEN_EXCP(ctx, POWERPC_EXCP_APU, 0)
9a64fbe4 305
a9d9eb8f
JM		 306#define GEN_EXCP_NO_VR(ctx) \
307GEN_EXCP(ctx, POWERPC_EXCP_VPU, 0)
308
f24e5695 309/* Stop translation */
b068d6a7 310static always_inline void GEN_STOP (DisasContext *ctx)
3fc6c082 311{
d9bce9d9 312 gen_update_nip(ctx, ctx->nip);
e1833e1f 313 ctx->exception = POWERPC_EXCP_STOP;
3fc6c082
FB		 314}
315
f24e5695 316/* No need to update nip here, as execution flow will change */
b068d6a7 317static always_inline void GEN_SYNC (DisasContext *ctx)
2be0071f 318{
e1833e1f 319 ctx->exception = POWERPC_EXCP_SYNC;
2be0071f
FB		 320}
321
79aceca5
FB		 322#define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
323static void gen_##name (DisasContext *ctx); \
324GEN_OPCODE(name, opc1, opc2, opc3, inval, type); \
325static void gen_##name (DisasContext *ctx)
326
c7697e1f
JM		 327#define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
328static void gen_##name (DisasContext *ctx); \
329GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type); \
330static void gen_##name (DisasContext *ctx)
331
79aceca5
FB		 332typedef struct opcode_t {
333 unsigned char opc1, opc2, opc3;
1235fc06 334#if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
18fba28c
FB		 335 unsigned char pad[5];
336#else
337 unsigned char pad[1];
338#endif
79aceca5 339 opc_handler_t handler;
b55266b5 340 const char *oname;
79aceca5
FB		 341} opcode_t;
342
a750fc0b 343/*****************************************************************************/
79aceca5
FB		 344/*** Instruction decoding ***/
345#define EXTRACT_HELPER(name, shift, nb) \
b068d6a7 346static always_inline uint32_t name (uint32_t opcode) \
79aceca5
FB		 347{ \
348 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
349}
350
351#define EXTRACT_SHELPER(name, shift, nb) \
b068d6a7 352static always_inline int32_t name (uint32_t opcode) \
79aceca5 353{ \
18fba28c 354 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
79aceca5
FB		 355}
356
357/* Opcode part 1 */
358EXTRACT_HELPER(opc1, 26, 6);
359/* Opcode part 2 */
360EXTRACT_HELPER(opc2, 1, 5);
361/* Opcode part 3 */
362EXTRACT_HELPER(opc3, 6, 5);
363/* Update Cr0 flags */
364EXTRACT_HELPER(Rc, 0, 1);
365/* Destination */
366EXTRACT_HELPER(rD, 21, 5);
367/* Source */
368EXTRACT_HELPER(rS, 21, 5);
369/* First operand */
370EXTRACT_HELPER(rA, 16, 5);
371/* Second operand */
372EXTRACT_HELPER(rB, 11, 5);
373/* Third operand */
374EXTRACT_HELPER(rC, 6, 5);
375/*** Get CRn ***/
376EXTRACT_HELPER(crfD, 23, 3);
377EXTRACT_HELPER(crfS, 18, 3);
378EXTRACT_HELPER(crbD, 21, 5);
379EXTRACT_HELPER(crbA, 16, 5);
380EXTRACT_HELPER(crbB, 11, 5);
381/* SPR / TBL */
3fc6c082 382EXTRACT_HELPER(_SPR, 11, 10);
b068d6a7 383static always_inline uint32_t SPR (uint32_t opcode)
3fc6c082
FB		 384{
385 uint32_t sprn = _SPR(opcode);
386
387 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
388}
79aceca5
FB		 389/*** Get constants ***/
390EXTRACT_HELPER(IMM, 12, 8);
391/* 16 bits signed immediate value */
392EXTRACT_SHELPER(SIMM, 0, 16);
393/* 16 bits unsigned immediate value */
394EXTRACT_HELPER(UIMM, 0, 16);
395/* Bit count */
396EXTRACT_HELPER(NB, 11, 5);
397/* Shift count */
398EXTRACT_HELPER(SH, 11, 5);
399/* Mask start */
400EXTRACT_HELPER(MB, 6, 5);
401/* Mask end */
402EXTRACT_HELPER(ME, 1, 5);
fb0eaffc
FB		 403/* Trap operand */
404EXTRACT_HELPER(TO, 21, 5);
79aceca5
FB		 405
406EXTRACT_HELPER(CRM, 12, 8);
407EXTRACT_HELPER(FM, 17, 8);
408EXTRACT_HELPER(SR, 16, 4);
e4bb997e 409EXTRACT_HELPER(FPIMM, 12, 4);
fb0eaffc 410
79aceca5
FB		 411/*** Jump target decoding ***/
412/* Displacement */
413EXTRACT_SHELPER(d, 0, 16);
414/* Immediate address */
b068d6a7 415static always_inline target_ulong LI (uint32_t opcode)
79aceca5
FB		 416{
417 return (opcode >> 0) & 0x03FFFFFC;
418}
419
b068d6a7 420static always_inline uint32_t BD (uint32_t opcode)
79aceca5
FB		 421{
422 return (opcode >> 0) & 0xFFFC;
423}
424
425EXTRACT_HELPER(BO, 21, 5);
426EXTRACT_HELPER(BI, 16, 5);
427/* Absolute/relative address */
428EXTRACT_HELPER(AA, 1, 1);
429/* Link */
430EXTRACT_HELPER(LK, 0, 1);
431
432/* Create a mask between <start> and <end> bits */
b068d6a7 433static always_inline target_ulong MASK (uint32_t start, uint32_t end)
79aceca5 434{
76a66253 435 target_ulong ret;
79aceca5 436
76a66253
JM		 437#if defined(TARGET_PPC64)
438 if (likely(start == 0)) {
6f2d8978 439 ret = UINT64_MAX << (63 - end);
76a66253 440 } else if (likely(end == 63)) {
6f2d8978 441 ret = UINT64_MAX >> start;
76a66253
JM		 442 }
443#else
444 if (likely(start == 0)) {
6f2d8978 445 ret = UINT32_MAX << (31 - end);
76a66253 446 } else if (likely(end == 31)) {
6f2d8978 447 ret = UINT32_MAX >> start;
76a66253
JM		 448 }
449#endif
450 else {
451 ret = (((target_ulong)(-1ULL)) >> (start)) ^
452 (((target_ulong)(-1ULL) >> (end)) >> 1);
453 if (unlikely(start > end))
454 return ~ret;
455 }
79aceca5
FB		 456
457 return ret;
458}
459
a750fc0b
JM		 460/*****************************************************************************/
461/* PowerPC Instructions types definitions */
462enum {
1b413d55 463 PPC_NONE = 0x0000000000000000ULL,
12de9a39 464 /* PowerPC base instructions set */
1b413d55
JM		 465 PPC_INSNS_BASE = 0x0000000000000001ULL,
466 /* integer operations instructions */
a750fc0b 467#define PPC_INTEGER PPC_INSNS_BASE
1b413d55 468 /* flow control instructions */
a750fc0b 469#define PPC_FLOW PPC_INSNS_BASE
1b413d55 470 /* virtual memory instructions */
a750fc0b 471#define PPC_MEM PPC_INSNS_BASE
1b413d55 472 /* ld/st with reservation instructions */
a750fc0b 473#define PPC_RES PPC_INSNS_BASE
1b413d55 474 /* spr/msr access instructions */
a750fc0b 475#define PPC_MISC PPC_INSNS_BASE
1b413d55
JM		 476 /* Deprecated instruction sets */
477 /* Original POWER instruction set */
f610349f 478 PPC_POWER = 0x0000000000000002ULL,
1b413d55 479 /* POWER2 instruction set extension */
f610349f 480 PPC_POWER2 = 0x0000000000000004ULL,
1b413d55 481 /* Power RTC support */
f610349f 482 PPC_POWER_RTC = 0x0000000000000008ULL,
1b413d55 483 /* Power-to-PowerPC bridge (601) */
f610349f 484 PPC_POWER_BR = 0x0000000000000010ULL,
1b413d55 485 /* 64 bits PowerPC instruction set */
f610349f 486 PPC_64B = 0x0000000000000020ULL,
1b413d55 487 /* New 64 bits extensions (PowerPC 2.0x) */
f610349f 488 PPC_64BX = 0x0000000000000040ULL,
1b413d55 489 /* 64 bits hypervisor extensions */
f610349f 490 PPC_64H = 0x0000000000000080ULL,
1b413d55 491 /* New wait instruction (PowerPC 2.0x) */
f610349f 492 PPC_WAIT = 0x0000000000000100ULL,
1b413d55 493 /* Time base mftb instruction */
f610349f 494 PPC_MFTB = 0x0000000000000200ULL,
1b413d55
JM		 495
496 /* Fixed-point unit extensions */
497 /* PowerPC 602 specific */
f610349f 498 PPC_602_SPEC = 0x0000000000000400ULL,
05332d70
JM		 499 /* isel instruction */
500 PPC_ISEL = 0x0000000000000800ULL,
501 /* popcntb instruction */
502 PPC_POPCNTB = 0x0000000000001000ULL,
503 /* string load / store */
504 PPC_STRING = 0x0000000000002000ULL,
1b413d55
JM		 505
506 /* Floating-point unit extensions */
507 /* Optional floating point instructions */
508 PPC_FLOAT = 0x0000000000010000ULL,
509 /* New floating-point extensions (PowerPC 2.0x) */
510 PPC_FLOAT_EXT = 0x0000000000020000ULL,
511 PPC_FLOAT_FSQRT = 0x0000000000040000ULL,
512 PPC_FLOAT_FRES = 0x0000000000080000ULL,
513 PPC_FLOAT_FRSQRTE = 0x0000000000100000ULL,
514 PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
515 PPC_FLOAT_FSEL = 0x0000000000400000ULL,
516 PPC_FLOAT_STFIWX = 0x0000000000800000ULL,
517
518 /* Vector/SIMD extensions */
519 /* Altivec support */
520 PPC_ALTIVEC = 0x0000000001000000ULL,
1b413d55 521 /* PowerPC 2.03 SPE extension */
05332d70 522 PPC_SPE = 0x0000000002000000ULL,
1b413d55 523 /* PowerPC 2.03 SPE floating-point extension */
05332d70 524 PPC_SPEFPU = 0x0000000004000000ULL,
1b413d55 525
12de9a39 526 /* Optional memory control instructions */
1b413d55
JM		 527 PPC_MEM_TLBIA = 0x0000000010000000ULL,
528 PPC_MEM_TLBIE = 0x0000000020000000ULL,
529 PPC_MEM_TLBSYNC = 0x0000000040000000ULL,
530 /* sync instruction */
531 PPC_MEM_SYNC = 0x0000000080000000ULL,
532 /* eieio instruction */
533 PPC_MEM_EIEIO = 0x0000000100000000ULL,
534
535 /* Cache control instructions */
c8623f2e 536 PPC_CACHE = 0x0000000200000000ULL,
1b413d55 537 /* icbi instruction */
05332d70 538 PPC_CACHE_ICBI = 0x0000000400000000ULL,
1b413d55 539 /* dcbz instruction with fixed cache line size */
05332d70 540 PPC_CACHE_DCBZ = 0x0000000800000000ULL,
1b413d55 541 /* dcbz instruction with tunable cache line size */
05332d70 542 PPC_CACHE_DCBZT = 0x0000001000000000ULL,
1b413d55 543 /* dcba instruction */
05332d70
JM		 544 PPC_CACHE_DCBA = 0x0000002000000000ULL,
545 /* Freescale cache locking instructions */
546 PPC_CACHE_LOCK = 0x0000004000000000ULL,
1b413d55
JM		 547
548 /* MMU related extensions */
549 /* external control instructions */
05332d70 550 PPC_EXTERN = 0x0000010000000000ULL,
1b413d55 551 /* segment register access instructions */
05332d70 552 PPC_SEGMENT = 0x0000020000000000ULL,
1b413d55 553 /* PowerPC 6xx TLB management instructions */
05332d70 554 PPC_6xx_TLB = 0x0000040000000000ULL,
1b413d55 555 /* PowerPC 74xx TLB management instructions */
05332d70 556 PPC_74xx_TLB = 0x0000080000000000ULL,
1b413d55 557 /* PowerPC 40x TLB management instructions */
05332d70 558 PPC_40x_TLB = 0x0000100000000000ULL,
1b413d55 559 /* segment register access instructions for PowerPC 64 "bridge" */
05332d70 560 PPC_SEGMENT_64B = 0x0000200000000000ULL,
1b413d55 561 /* SLB management */
05332d70 562 PPC_SLBI = 0x0000400000000000ULL,
1b413d55 563
12de9a39 564 /* Embedded PowerPC dedicated instructions */
05332d70 565 PPC_WRTEE = 0x0001000000000000ULL,
12de9a39 566 /* PowerPC 40x exception model */
05332d70 567 PPC_40x_EXCP = 0x0002000000000000ULL,
12de9a39 568 /* PowerPC 405 Mac instructions */
05332d70 569 PPC_405_MAC = 0x0004000000000000ULL,
12de9a39 570 /* PowerPC 440 specific instructions */
05332d70 571 PPC_440_SPEC = 0x0008000000000000ULL,
12de9a39 572 /* BookE (embedded) PowerPC specification */
05332d70
JM		 573 PPC_BOOKE = 0x0010000000000000ULL,
574 /* mfapidi instruction */
575 PPC_MFAPIDI = 0x0020000000000000ULL,
576 /* tlbiva instruction */
577 PPC_TLBIVA = 0x0040000000000000ULL,
578 /* tlbivax instruction */
579 PPC_TLBIVAX = 0x0080000000000000ULL,
12de9a39 580 /* PowerPC 4xx dedicated instructions */
05332d70 581 PPC_4xx_COMMON = 0x0100000000000000ULL,
12de9a39 582 /* PowerPC 40x ibct instructions */
05332d70 583 PPC_40x_ICBT = 0x0200000000000000ULL,
12de9a39 584 /* rfmci is not implemented in all BookE PowerPC */
05332d70
JM		 585 PPC_RFMCI = 0x0400000000000000ULL,
586 /* rfdi instruction */
587 PPC_RFDI = 0x0800000000000000ULL,
588 /* DCR accesses */
589 PPC_DCR = 0x1000000000000000ULL,
590 /* DCR extended accesse */
591 PPC_DCRX = 0x2000000000000000ULL,
12de9a39 592 /* user-mode DCR access, implemented in PowerPC 460 */
05332d70 593 PPC_DCRUX = 0x4000000000000000ULL,
a750fc0b
JM		 594};
595
596/*****************************************************************************/
597/* PowerPC instructions table */
3fc6c082
FB		 598#if HOST_LONG_BITS == 64
599#define OPC_ALIGN 8
600#else
601#define OPC_ALIGN 4
602#endif
1b039c09 603#if defined(__APPLE__)
d9bce9d9 604#define OPCODES_SECTION \
3fc6c082 605 __attribute__ ((section("__TEXT,__opcodes"), unused, aligned (OPC_ALIGN) ))
933dc6eb 606#else
d9bce9d9 607#define OPCODES_SECTION \
3fc6c082 608 __attribute__ ((section(".opcodes"), unused, aligned (OPC_ALIGN) ))
933dc6eb
FB		 609#endif
610
76a66253 611#if defined(DO_PPC_STATISTICS)
79aceca5 612#define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
18fba28c 613OPCODES_SECTION opcode_t opc_##name = { \
79aceca5
FB		 614 .opc1 = op1, \
615 .opc2 = op2, \
616 .opc3 = op3, \
18fba28c 617 .pad = { 0, }, \
79aceca5
FB		 618 .handler = { \
619 .inval = invl, \
9a64fbe4 620 .type = _typ, \
79aceca5 621 .handler = &gen_##name, \
76a66253 622 .oname = stringify(name), \
79aceca5 623 }, \
3fc6c082 624 .oname = stringify(name), \
79aceca5 625}
c7697e1f
JM		 626#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
627OPCODES_SECTION opcode_t opc_##name = { \
628 .opc1 = op1, \
629 .opc2 = op2, \
630 .opc3 = op3, \
631 .pad = { 0, }, \
632 .handler = { \
633 .inval = invl, \
634 .type = _typ, \
635 .handler = &gen_##name, \
636 .oname = onam, \
637 }, \
638 .oname = onam, \
639}
76a66253
JM		 640#else
641#define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
642OPCODES_SECTION opcode_t opc_##name = { \
643 .opc1 = op1, \
644 .opc2 = op2, \
645 .opc3 = op3, \
646 .pad = { 0, }, \
647 .handler = { \
648 .inval = invl, \
649 .type = _typ, \
650 .handler = &gen_##name, \
651 }, \
652 .oname = stringify(name), \
653}
c7697e1f
JM		 654#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
655OPCODES_SECTION opcode_t opc_##name = { \
656 .opc1 = op1, \
657 .opc2 = op2, \
658 .opc3 = op3, \
659 .pad = { 0, }, \
660 .handler = { \
661 .inval = invl, \
662 .type = _typ, \
663 .handler = &gen_##name, \
664 }, \
665 .oname = onam, \
666}
76a66253 667#endif
79aceca5
FB		 668
669#define GEN_OPCODE_MARK(name) \
18fba28c 670OPCODES_SECTION opcode_t opc_##name = { \
79aceca5
FB		 671 .opc1 = 0xFF, \
672 .opc2 = 0xFF, \
673 .opc3 = 0xFF, \
18fba28c 674 .pad = { 0, }, \
79aceca5
FB		 675 .handler = { \
676 .inval = 0x00000000, \
9a64fbe4 677 .type = 0x00, \
79aceca5
FB		 678 .handler = NULL, \
679 }, \
3fc6c082 680 .oname = stringify(name), \
79aceca5
FB		 681}
682
54cdcae6
AJ		 683/* SPR load/store helpers */
684static always_inline void gen_load_spr(TCGv t, int reg)
685{
686 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUState, spr[reg]));
687}
688
689static always_inline void gen_store_spr(int reg, TCGv t)
690{
691 tcg_gen_st_tl(t, cpu_env, offsetof(CPUState, spr[reg]));
692}
693
79aceca5
FB		 694/* Start opcode list */
695GEN_OPCODE_MARK(start);
696
697/* Invalid instruction */
9a64fbe4
FB		 698GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE)
699{
e1833e1f 700 GEN_EXCP_INVAL(ctx);
9a64fbe4
FB		 701}
702
79aceca5
FB		 703static opc_handler_t invalid_handler = {
704 .inval = 0xFFFFFFFF,
9a64fbe4 705 .type = PPC_NONE,
79aceca5
FB		 706 .handler = gen_invalid,
707};
708
e1571908
AJ		 709/*** Integer comparison ***/
710
ea363694 711static always_inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
e1571908
AJ		 712{
713 int l1, l2, l3;
714
269f3e95
AJ		 715 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_xer);
716 tcg_gen_shri_i32(cpu_crf[crf], cpu_crf[crf], XER_SO);
e1571908
AJ		 717 tcg_gen_andi_i32(cpu_crf[crf], cpu_crf[crf], 1);
718
719 l1 = gen_new_label();
720 l2 = gen_new_label();
721 l3 = gen_new_label();
722 if (s) {
ea363694
AJ		 723 tcg_gen_brcond_tl(TCG_COND_LT, arg0, arg1, l1);
724 tcg_gen_brcond_tl(TCG_COND_GT, arg0, arg1, l2);
e1571908 725 } else {
ea363694
AJ		 726 tcg_gen_brcond_tl(TCG_COND_LTU, arg0, arg1, l1);
727 tcg_gen_brcond_tl(TCG_COND_GTU, arg0, arg1, l2);
e1571908
AJ		 728 }
729 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_EQ);
730 tcg_gen_br(l3);
731 gen_set_label(l1);
732 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_LT);
733 tcg_gen_br(l3);
734 gen_set_label(l2);
735 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_GT);
736 gen_set_label(l3);
737}
738
ea363694 739static always_inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
e1571908 740{
ea363694
AJ		 741 TCGv t0 = tcg_const_local_tl(arg1);
742 gen_op_cmp(arg0, t0, s, crf);
743 tcg_temp_free(t0);
e1571908
AJ		 744}
745
746#if defined(TARGET_PPC64)
ea363694 747static always_inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
e1571908 748{
ea363694 749 TCGv t0, t1;
a7812ae4
PB		 750 t0 = tcg_temp_local_new();
751 t1 = tcg_temp_local_new();
e1571908 752 if (s) {
ea363694
AJ		 753 tcg_gen_ext32s_tl(t0, arg0);
754 tcg_gen_ext32s_tl(t1, arg1);
e1571908 755 } else {
ea363694
AJ		 756 tcg_gen_ext32u_tl(t0, arg0);
757 tcg_gen_ext32u_tl(t1, arg1);
e1571908 758 }
ea363694
AJ		 759 gen_op_cmp(t0, t1, s, crf);
760 tcg_temp_free(t1);
761 tcg_temp_free(t0);
e1571908
AJ		 762}
763
ea363694 764static always_inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
e1571908 765{
ea363694
AJ		 766 TCGv t0 = tcg_const_local_tl(arg1);
767 gen_op_cmp32(arg0, t0, s, crf);
768 tcg_temp_free(t0);
e1571908
AJ		 769}
770#endif
771
772static always_inline void gen_set_Rc0 (DisasContext *ctx, TCGv reg)
773{
774#if defined(TARGET_PPC64)
775 if (!(ctx->sf_mode))
776 gen_op_cmpi32(reg, 0, 1, 0);
777 else
778#endif
779 gen_op_cmpi(reg, 0, 1, 0);
780}
781
782/* cmp */
783GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER)
784{
785#if defined(TARGET_PPC64)
786 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
787 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
788 1, crfD(ctx->opcode));
789 else
790#endif
791 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
792 1, crfD(ctx->opcode));
793}
794
795/* cmpi */
796GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
797{
798#if defined(TARGET_PPC64)
799 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
800 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
801 1, crfD(ctx->opcode));
802 else
803#endif
804 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
805 1, crfD(ctx->opcode));
806}
807
808/* cmpl */
809GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER)
810{
811#if defined(TARGET_PPC64)
812 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
813 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
814 0, crfD(ctx->opcode));
815 else
816#endif
817 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
818 0, crfD(ctx->opcode));
819}
820
821/* cmpli */
822GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
823{
824#if defined(TARGET_PPC64)
825 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
826 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
827 0, crfD(ctx->opcode));
828 else
829#endif
830 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
831 0, crfD(ctx->opcode));
832}
833
834/* isel (PowerPC 2.03 specification) */
835GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL)
836{
837 int l1, l2;
838 uint32_t bi = rC(ctx->opcode);
839 uint32_t mask;
a7812ae4 840 TCGv_i32 t0;
e1571908
AJ		 841
842 l1 = gen_new_label();
843 l2 = gen_new_label();
844
845 mask = 1 << (3 - (bi & 0x03));
a7812ae4 846 t0 = tcg_temp_new_i32();
fea0c503
AJ		 847 tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask);
848 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
e1571908
AJ		 849 if (rA(ctx->opcode) == 0)
850 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
851 else
852 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
853 tcg_gen_br(l2);
854 gen_set_label(l1);
855 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
856 gen_set_label(l2);
a7812ae4 857 tcg_temp_free_i32(t0);
e1571908
AJ		 858}
859
79aceca5 860/*** Integer arithmetic ***/
79aceca5 861
74637406
AJ		 862static always_inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, TCGv arg1, TCGv arg2, int sub)
863{
864 int l1;
865 TCGv t0;
79aceca5 866
74637406
AJ		 867 l1 = gen_new_label();
868 /* Start with XER OV disabled, the most likely case */
869 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
a7812ae4 870 t0 = tcg_temp_local_new();
74637406
AJ		 871 tcg_gen_xor_tl(t0, arg0, arg1);
872#if defined(TARGET_PPC64)
873 if (!ctx->sf_mode)
874 tcg_gen_ext32s_tl(t0, t0);
875#endif
876 if (sub)
877 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1);
878 else
879 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
880 tcg_gen_xor_tl(t0, arg1, arg2);
881#if defined(TARGET_PPC64)
882 if (!ctx->sf_mode)
883 tcg_gen_ext32s_tl(t0, t0);
884#endif
885 if (sub)
886 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
887 else
888 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1);
889 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
890 gen_set_label(l1);
891 tcg_temp_free(t0);
79aceca5
FB		 892}
893
74637406
AJ		 894static always_inline void gen_op_arith_compute_ca(DisasContext *ctx, TCGv arg1, TCGv arg2, int sub)
895{
896 int l1 = gen_new_label();
d9bce9d9
JM		 897
898#if defined(TARGET_PPC64)
74637406
AJ		 899 if (!(ctx->sf_mode)) {
900 TCGv t0, t1;
a7812ae4
PB		 901 t0 = tcg_temp_new();
902 t1 = tcg_temp_new();
d9bce9d9 903
74637406
AJ		 904 tcg_gen_ext32u_tl(t0, arg1);
905 tcg_gen_ext32u_tl(t1, arg2);
906 if (sub) {
907 tcg_gen_brcond_tl(TCG_COND_GTU, t0, t1, l1);
bdc4e053 908 } else {
74637406
AJ		 909 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
910 }
a9730017
AJ		 911 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
912 gen_set_label(l1);
913 tcg_temp_free(t0);
914 tcg_temp_free(t1);
74637406
AJ		 915 } else
916#endif
a9730017
AJ		 917 {
918 if (sub) {
919 tcg_gen_brcond_tl(TCG_COND_GTU, arg1, arg2, l1);
920 } else {
921 tcg_gen_brcond_tl(TCG_COND_GEU, arg1, arg2, l1);
922 }
923 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
924 gen_set_label(l1);
74637406 925 }
d9bce9d9
JM		 926}
927
74637406
AJ		 928/* Common add function */
929static always_inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
930 int add_ca, int compute_ca, int compute_ov)
931{
932 TCGv t0, t1;
d9bce9d9 933
74637406 934 if ((!compute_ca && !compute_ov) ||
a7812ae4 935 (!TCGV_EQUAL(ret,arg1) && !TCGV_EQUAL(ret, arg2))) {
74637406
AJ		 936 t0 = ret;
937 } else {
a7812ae4 938 t0 = tcg_temp_local_new();
74637406 939 }
79aceca5 940
74637406 941 if (add_ca) {
a7812ae4 942 t1 = tcg_temp_local_new();
74637406
AJ		 943 tcg_gen_andi_tl(t1, cpu_xer, (1 << XER_CA));
944 tcg_gen_shri_tl(t1, t1, XER_CA);
945 }
79aceca5 946
74637406
AJ		 947 if (compute_ca && compute_ov) {
948 /* Start with XER CA and OV disabled, the most likely case */
949 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~((1 << XER_CA) | (1 << XER_OV)));
950 } else if (compute_ca) {
951 /* Start with XER CA disabled, the most likely case */
952 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
953 } else if (compute_ov) {
954 /* Start with XER OV disabled, the most likely case */
955 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
956 }
79aceca5 957
74637406
AJ		 958 tcg_gen_add_tl(t0, arg1, arg2);
959
960 if (compute_ca) {
961 gen_op_arith_compute_ca(ctx, t0, arg1, 0);
962 }
963 if (add_ca) {
964 tcg_gen_add_tl(t0, t0, t1);
965 gen_op_arith_compute_ca(ctx, t0, t1, 0);
966 tcg_temp_free(t1);
967 }
968 if (compute_ov) {
969 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
970 }
971
972 if (unlikely(Rc(ctx->opcode) != 0))
973 gen_set_Rc0(ctx, t0);
974
a7812ae4 975 if (!TCGV_EQUAL(t0, ret)) {
74637406
AJ		 976 tcg_gen_mov_tl(ret, t0);
977 tcg_temp_free(t0);
978 }
39dd32ee 979}
74637406
AJ		 980/* Add functions with two operands */
981#define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
982GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER) \
983{ \
984 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
985 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
986 add_ca, compute_ca, compute_ov); \
987}
988/* Add functions with one operand and one immediate */
989#define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
990 add_ca, compute_ca, compute_ov) \
991GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER) \
992{ \
993 TCGv t0 = tcg_const_local_tl(const_val); \
994 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
995 cpu_gpr[rA(ctx->opcode)], t0, \
996 add_ca, compute_ca, compute_ov); \
997 tcg_temp_free(t0); \
998}
999
1000/* add add. addo addo. */
1001GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
1002GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
1003/* addc addc. addco addco. */
1004GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
1005GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
1006/* adde adde. addeo addeo. */
1007GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
1008GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
1009/* addme addme. addmeo addmeo. */
1010GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
1011GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
1012/* addze addze. addzeo addzeo.*/
1013GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
1014GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
1015/* addi */
1016GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
d9bce9d9 1017{
74637406
AJ		 1018 target_long simm = SIMM(ctx->opcode);
1019
1020 if (rA(ctx->opcode) == 0) {
1021 /* li case */
1022 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
1023 } else {
1024 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm);
1025 }
d9bce9d9 1026}
74637406
AJ		 1027/* addic addic.*/
1028static always_inline void gen_op_addic (DisasContext *ctx, TCGv ret, TCGv arg1,
1029 int compute_Rc0)
d9bce9d9 1030{
74637406
AJ		 1031 target_long simm = SIMM(ctx->opcode);
1032
1033 /* Start with XER CA and OV disabled, the most likely case */
1034 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1035
1036 if (likely(simm != 0)) {
a7812ae4 1037 TCGv t0 = tcg_temp_local_new();
74637406
AJ		 1038 tcg_gen_addi_tl(t0, arg1, simm);
1039 gen_op_arith_compute_ca(ctx, t0, arg1, 0);
1040 tcg_gen_mov_tl(ret, t0);
1041 tcg_temp_free(t0);
1042 } else {
1043 tcg_gen_mov_tl(ret, arg1);
1044 }
1045 if (compute_Rc0) {
1046 gen_set_Rc0(ctx, ret);
1047 }
d9bce9d9 1048}
74637406 1049GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
d9bce9d9 1050{
74637406 1051 gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0);
d9bce9d9 1052}
74637406 1053GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
d9bce9d9 1054{
74637406 1055 gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1);
d9bce9d9 1056}
74637406
AJ		 1057/* addis */
1058GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
d9bce9d9 1059{
74637406
AJ		 1060 target_long simm = SIMM(ctx->opcode);
1061
1062 if (rA(ctx->opcode) == 0) {
1063 /* lis case */
1064 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
1065 } else {
1066 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm << 16);
1067 }
d9bce9d9 1068}
74637406
AJ		 1069
1070static always_inline void gen_op_arith_divw (DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
1071 int sign, int compute_ov)
d9bce9d9 1072{
2ef1b120
AJ		 1073 int l1 = gen_new_label();
1074 int l2 = gen_new_label();
a7812ae4
PB		 1075 TCGv_i32 t0 = tcg_temp_local_new_i32();
1076 TCGv_i32 t1 = tcg_temp_local_new_i32();
74637406 1077
2ef1b120
AJ		 1078 tcg_gen_trunc_tl_i32(t0, arg1);
1079 tcg_gen_trunc_tl_i32(t1, arg2);
1080 tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
74637406 1081 if (sign) {
2ef1b120
AJ		 1082 int l3 = gen_new_label();
1083 tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
1084 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
74637406 1085 gen_set_label(l3);
2ef1b120 1086 tcg_gen_div_i32(t0, t0, t1);
74637406 1087 } else {
2ef1b120 1088 tcg_gen_divu_i32(t0, t0, t1);
74637406
AJ		 1089 }
1090 if (compute_ov) {
1091 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1092 }
1093 tcg_gen_br(l2);
1094 gen_set_label(l1);
1095 if (sign) {
2ef1b120 1096 tcg_gen_sari_i32(t0, t0, 31);
74637406
AJ		 1097 } else {
1098 tcg_gen_movi_i32(t0, 0);
1099 }
1100 if (compute_ov) {
1101 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1102 }
1103 gen_set_label(l2);
2ef1b120 1104 tcg_gen_extu_i32_tl(ret, t0);
a7812ae4
PB		 1105 tcg_temp_free_i32(t0);
1106 tcg_temp_free_i32(t1);
74637406
AJ		 1107 if (unlikely(Rc(ctx->opcode) != 0))
1108 gen_set_Rc0(ctx, ret);
d9bce9d9 1109}
74637406
AJ		 1110/* Div functions */
1111#define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
1112GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER) \
1113{ \
1114 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
1115 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1116 sign, compute_ov); \
1117}
1118/* divwu divwu. divwuo divwuo. */
1119GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
1120GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
1121/* divw divw. divwo divwo. */
1122GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
1123GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
d9bce9d9 1124#if defined(TARGET_PPC64)
2ef1b120
AJ		 1125static always_inline void gen_op_arith_divd (DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
1126 int sign, int compute_ov)
d9bce9d9 1127{
2ef1b120
AJ		 1128 int l1 = gen_new_label();
1129 int l2 = gen_new_label();
74637406
AJ		 1130
1131 tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
1132 if (sign) {
2ef1b120 1133 int l3 = gen_new_label();
74637406
AJ		 1134 tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
1135 tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);
1136 gen_set_label(l3);
74637406
AJ		 1137 tcg_gen_div_i64(ret, arg1, arg2);
1138 } else {
1139 tcg_gen_divu_i64(ret, arg1, arg2);
1140 }
1141 if (compute_ov) {
1142 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1143 }
1144 tcg_gen_br(l2);
1145 gen_set_label(l1);
1146 if (sign) {
1147 tcg_gen_sari_i64(ret, arg1, 63);
1148 } else {
1149 tcg_gen_movi_i64(ret, 0);
1150 }
1151 if (compute_ov) {
1152 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1153 }
1154 gen_set_label(l2);
1155 if (unlikely(Rc(ctx->opcode) != 0))
1156 gen_set_Rc0(ctx, ret);
d9bce9d9 1157}
74637406
AJ		 1158#define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1159GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) \
1160{ \
2ef1b120
AJ		 1161 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1162 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1163 sign, compute_ov); \
74637406
AJ		 1164}
1165/* divwu divwu. divwuo divwuo. */
1166GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1167GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1168/* divw divw. divwo divwo. */
1169GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1170GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
d9bce9d9 1171#endif
74637406
AJ		 1172
1173/* mulhw mulhw. */
1174GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER)
d9bce9d9 1175{
a7812ae4 1176 TCGv_i64 t0, t1;
74637406 1177
a7812ae4
PB		 1178 t0 = tcg_temp_new_i64();
1179 t1 = tcg_temp_new_i64();
74637406
AJ		 1180#if defined(TARGET_PPC64)
1181 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
1182 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
1183 tcg_gen_mul_i64(t0, t0, t1);
1184 tcg_gen_shri_i64(cpu_gpr[rD(ctx->opcode)], t0, 32);
1185#else
1186 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1187 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1188 tcg_gen_mul_i64(t0, t0, t1);
1189 tcg_gen_shri_i64(t0, t0, 32);
1190 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1191#endif
a7812ae4
PB		 1192 tcg_temp_free_i64(t0);
1193 tcg_temp_free_i64(t1);
74637406
AJ		 1194 if (unlikely(Rc(ctx->opcode) != 0))
1195 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1196}
74637406
AJ		 1197/* mulhwu mulhwu. */
1198GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER)
d9bce9d9 1199{
a7812ae4 1200 TCGv_i64 t0, t1;
74637406 1201
a7812ae4
PB		 1202 t0 = tcg_temp_new_i64();
1203 t1 = tcg_temp_new_i64();
d9bce9d9 1204#if defined(TARGET_PPC64)
74637406
AJ		 1205 tcg_gen_ext32u_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1206 tcg_gen_ext32u_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1207 tcg_gen_mul_i64(t0, t0, t1);
1208 tcg_gen_shri_i64(cpu_gpr[rD(ctx->opcode)], t0, 32);
1209#else
1210 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1211 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1212 tcg_gen_mul_i64(t0, t0, t1);
1213 tcg_gen_shri_i64(t0, t0, 32);
1214 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1215#endif
a7812ae4
PB		 1216 tcg_temp_free_i64(t0);
1217 tcg_temp_free_i64(t1);
74637406
AJ		 1218 if (unlikely(Rc(ctx->opcode) != 0))
1219 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1220}
74637406
AJ		 1221/* mullw mullw. */
1222GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER)
d9bce9d9 1223{
74637406
AJ		 1224 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1225 cpu_gpr[rB(ctx->opcode)]);
1e4c090f 1226 tcg_gen_ext32s_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)]);
74637406
AJ		 1227 if (unlikely(Rc(ctx->opcode) != 0))
1228 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1229}
74637406
AJ		 1230/* mullwo mullwo. */
1231GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER)
d9bce9d9 1232{
74637406 1233 int l1;
a7812ae4 1234 TCGv_i64 t0, t1;
74637406 1235
a7812ae4
PB		 1236 t0 = tcg_temp_new_i64();
1237 t1 = tcg_temp_new_i64();
74637406
AJ		 1238 l1 = gen_new_label();
1239 /* Start with XER OV disabled, the most likely case */
1240 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1241#if defined(TARGET_PPC64)
1242 tcg_gen_ext32s_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1243 tcg_gen_ext32s_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1244#else
1245 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1246 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
d9bce9d9 1247#endif
74637406
AJ		 1248 tcg_gen_mul_i64(t0, t0, t1);
1249#if defined(TARGET_PPC64)
1250 tcg_gen_ext32s_i64(cpu_gpr[rD(ctx->opcode)], t0);
1251 tcg_gen_brcond_i64(TCG_COND_EQ, t0, cpu_gpr[rD(ctx->opcode)], l1);
1252#else
1253 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1254 tcg_gen_ext32s_i64(t1, t0);
1255 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
1256#endif
1257 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1258 gen_set_label(l1);
a7812ae4
PB		 1259 tcg_temp_free_i64(t0);
1260 tcg_temp_free_i64(t1);
74637406
AJ		 1261 if (unlikely(Rc(ctx->opcode) != 0))
1262 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1263}
74637406
AJ		 1264/* mulli */
1265GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
d9bce9d9 1266{
74637406
AJ		 1267 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1268 SIMM(ctx->opcode));
d9bce9d9
JM		 1269}
1270#if defined(TARGET_PPC64)
74637406
AJ		 1271#define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
1272GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) \
1273{ \
a7812ae4 1274 gen_helper_##name (cpu_gpr[rD(ctx->opcode)], \
74637406
AJ		 1275 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
1276 if (unlikely(Rc(ctx->opcode) != 0)) \
1277 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
d9bce9d9 1278}
74637406
AJ		 1279/* mulhd mulhd. */
1280GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00);
1281/* mulhdu mulhdu. */
1282GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02);
1283/* mulld mulld. */
1284GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B)
d9bce9d9 1285{
74637406
AJ		 1286 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1287 cpu_gpr[rB(ctx->opcode)]);
1288 if (unlikely(Rc(ctx->opcode) != 0))
1289 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1290}
74637406
AJ		 1291/* mulldo mulldo. */
1292GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17);
d9bce9d9 1293#endif
74637406
AJ		 1294
1295/* neg neg. nego nego. */
ec6469a3 1296static always_inline void gen_op_arith_neg (DisasContext *ctx, TCGv ret, TCGv arg1, int ov_check)
d9bce9d9 1297{
ec6469a3
AJ		 1298 int l1 = gen_new_label();
1299 int l2 = gen_new_label();
a7812ae4 1300 TCGv t0 = tcg_temp_local_new();
d9bce9d9 1301#if defined(TARGET_PPC64)
74637406 1302 if (ctx->sf_mode) {
741a7444 1303 tcg_gen_mov_tl(t0, arg1);
ec6469a3
AJ		 1304 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT64_MIN, l1);
1305 } else
1306#endif
1307 {
1308 tcg_gen_ext32s_tl(t0, arg1);
74637406
AJ		 1309 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT32_MIN, l1);
1310 }
74637406
AJ		 1311 tcg_gen_neg_tl(ret, arg1);
1312 if (ov_check) {
1313 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1314 }
1315 tcg_gen_br(l2);
1316 gen_set_label(l1);
ec6469a3 1317 tcg_gen_mov_tl(ret, t0);
74637406
AJ		 1318 if (ov_check) {
1319 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1320 }
1321 gen_set_label(l2);
ec6469a3 1322 tcg_temp_free(t0);
74637406
AJ		 1323 if (unlikely(Rc(ctx->opcode) != 0))
1324 gen_set_Rc0(ctx, ret);
1325}
1326GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER)
d9bce9d9 1327{
ec6469a3 1328 gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0);
d9bce9d9 1329}
74637406 1330GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER)
79aceca5 1331{
ec6469a3 1332 gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1);
79aceca5 1333}
74637406
AJ		 1334
1335/* Common subf function */
1336static always_inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
1337 int add_ca, int compute_ca, int compute_ov)
79aceca5 1338{
74637406 1339 TCGv t0, t1;
76a66253 1340
74637406 1341 if ((!compute_ca && !compute_ov) ||
a7812ae4 1342 (!TCGV_EQUAL(ret, arg1) && !TCGV_EQUAL(ret, arg2))) {
74637406 1343 t0 = ret;
e864cabd 1344 } else {
a7812ae4 1345 t0 = tcg_temp_local_new();
d9bce9d9 1346 }
76a66253 1347
74637406 1348 if (add_ca) {
a7812ae4 1349 t1 = tcg_temp_local_new();
74637406
AJ		 1350 tcg_gen_andi_tl(t1, cpu_xer, (1 << XER_CA));
1351 tcg_gen_shri_tl(t1, t1, XER_CA);
d9bce9d9 1352 }
79aceca5 1353
74637406
AJ		 1354 if (compute_ca && compute_ov) {
1355 /* Start with XER CA and OV disabled, the most likely case */
1356 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~((1 << XER_CA) | (1 << XER_OV)));
1357 } else if (compute_ca) {
1358 /* Start with XER CA disabled, the most likely case */
1359 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1360 } else if (compute_ov) {
1361 /* Start with XER OV disabled, the most likely case */
1362 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1363 }
1364
1365 if (add_ca) {
1366 tcg_gen_not_tl(t0, arg1);
1367 tcg_gen_add_tl(t0, t0, arg2);
1368 gen_op_arith_compute_ca(ctx, t0, arg2, 0);
1369 tcg_gen_add_tl(t0, t0, t1);
1370 gen_op_arith_compute_ca(ctx, t0, t1, 0);
1371 tcg_temp_free(t1);
79aceca5 1372 } else {
74637406
AJ		 1373 tcg_gen_sub_tl(t0, arg2, arg1);
1374 if (compute_ca) {
1375 gen_op_arith_compute_ca(ctx, t0, arg2, 1);
1376 }
1377 }
1378 if (compute_ov) {
1379 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1380 }
1381
1382 if (unlikely(Rc(ctx->opcode) != 0))
1383 gen_set_Rc0(ctx, t0);
1384
a7812ae4 1385 if (!TCGV_EQUAL(t0, ret)) {
74637406
AJ		 1386 tcg_gen_mov_tl(ret, t0);
1387 tcg_temp_free(t0);
79aceca5 1388 }
79aceca5 1389}
74637406
AJ		 1390/* Sub functions with Two operands functions */
1391#define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1392GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER) \
1393{ \
1394 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1395 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1396 add_ca, compute_ca, compute_ov); \
1397}
1398/* Sub functions with one operand and one immediate */
1399#define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1400 add_ca, compute_ca, compute_ov) \
1401GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER) \
1402{ \
1403 TCGv t0 = tcg_const_local_tl(const_val); \
1404 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1405 cpu_gpr[rA(ctx->opcode)], t0, \
1406 add_ca, compute_ca, compute_ov); \
1407 tcg_temp_free(t0); \
1408}
1409/* subf subf. subfo subfo. */
1410GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1411GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1412/* subfc subfc. subfco subfco. */
1413GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1414GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1415/* subfe subfe. subfeo subfo. */
1416GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1417GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1418/* subfme subfme. subfmeo subfmeo. */
1419GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1420GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1421/* subfze subfze. subfzeo subfzeo.*/
1422GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1423GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
79aceca5
FB		 1424/* subfic */
1425GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1426{
74637406
AJ		 1427 /* Start with XER CA and OV disabled, the most likely case */
1428 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
a7812ae4 1429 TCGv t0 = tcg_temp_local_new();
74637406
AJ		 1430 TCGv t1 = tcg_const_local_tl(SIMM(ctx->opcode));
1431 tcg_gen_sub_tl(t0, t1, cpu_gpr[rA(ctx->opcode)]);
1432 gen_op_arith_compute_ca(ctx, t0, t1, 1);
1433 tcg_temp_free(t1);
1434 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
1435 tcg_temp_free(t0);
79aceca5
FB		 1436}
1437
79aceca5 1438/*** Integer logical ***/
26d67362
AJ		 1439#define GEN_LOGICAL2(name, tcg_op, opc, type) \
1440GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) \
79aceca5 1441{ \
26d67362
AJ		 1442 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1443 cpu_gpr[rB(ctx->opcode)]); \
76a66253 1444 if (unlikely(Rc(ctx->opcode) != 0)) \
26d67362 1445 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
79aceca5 1446}
79aceca5 1447
26d67362 1448#define GEN_LOGICAL1(name, tcg_op, opc, type) \
d9bce9d9 1449GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) \
79aceca5 1450{ \
26d67362 1451 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
76a66253 1452 if (unlikely(Rc(ctx->opcode) != 0)) \
26d67362 1453 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
79aceca5
FB		 1454}
1455
1456/* and & and. */
26d67362 1457GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
79aceca5 1458/* andc & andc. */
26d67362 1459GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
79aceca5 1460/* andi. */
c7697e1f 1461GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
79aceca5 1462{
26d67362
AJ		 1463 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1464 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5
FB		 1465}
1466/* andis. */
c7697e1f 1467GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
79aceca5 1468{
26d67362
AJ		 1469 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1470 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5 1471}
79aceca5 1472/* cntlzw */
26d67362
AJ		 1473GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER)
1474{
a7812ae4 1475 gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
26d67362 1476 if (unlikely(Rc(ctx->opcode) != 0))
2e31f5d3 1477 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
26d67362 1478}
79aceca5 1479/* eqv & eqv. */
26d67362 1480GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
79aceca5 1481/* extsb & extsb. */
26d67362 1482GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
79aceca5 1483/* extsh & extsh. */
26d67362 1484GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
79aceca5 1485/* nand & nand. */
26d67362 1486GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
79aceca5 1487/* nor & nor. */
26d67362 1488GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
79aceca5 1489/* or & or. */
9a64fbe4
FB		 1490GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER)
1491{
76a66253
JM		 1492 int rs, ra, rb;
1493
1494 rs = rS(ctx->opcode);
1495 ra = rA(ctx->opcode);
1496 rb = rB(ctx->opcode);
1497 /* Optimisation for mr. ri case */
1498 if (rs != ra || rs != rb) {
26d67362
AJ		 1499 if (rs != rb)
1500 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1501 else
1502 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
76a66253 1503 if (unlikely(Rc(ctx->opcode) != 0))
26d67362 1504 gen_set_Rc0(ctx, cpu_gpr[ra]);
76a66253 1505 } else if (unlikely(Rc(ctx->opcode) != 0)) {
26d67362 1506 gen_set_Rc0(ctx, cpu_gpr[rs]);
c80f84e3
JM		 1507#if defined(TARGET_PPC64)
1508 } else {
26d67362
AJ		 1509 int prio = 0;
1510
c80f84e3
JM		 1511 switch (rs) {
1512 case 1:
1513 /* Set process priority to low */
26d67362 1514 prio = 2;
c80f84e3
JM		 1515 break;
1516 case 6:
1517 /* Set process priority to medium-low */
26d67362 1518 prio = 3;
c80f84e3
JM		 1519 break;
1520 case 2:
1521 /* Set process priority to normal */
26d67362 1522 prio = 4;
c80f84e3 1523 break;
be147d08
JM		 1524#if !defined(CONFIG_USER_ONLY)
1525 case 31:
1526 if (ctx->supervisor > 0) {
1527 /* Set process priority to very low */
26d67362 1528 prio = 1;
be147d08
JM		 1529 }
1530 break;
1531 case 5:
1532 if (ctx->supervisor > 0) {
1533 /* Set process priority to medium-hight */
26d67362 1534 prio = 5;
be147d08
JM		 1535 }
1536 break;
1537 case 3:
1538 if (ctx->supervisor > 0) {
1539 /* Set process priority to high */
26d67362 1540 prio = 6;
be147d08
JM		 1541 }
1542 break;
be147d08
JM		 1543 case 7:
1544 if (ctx->supervisor > 1) {
1545 /* Set process priority to very high */
26d67362 1546 prio = 7;
be147d08
JM		 1547 }
1548 break;
be147d08 1549#endif
c80f84e3
JM		 1550 default:
1551 /* nop */
1552 break;
1553 }
26d67362 1554 if (prio) {
a7812ae4 1555 TCGv t0 = tcg_temp_new();
54cdcae6 1556 gen_load_spr(t0, SPR_PPR);
ea363694
AJ		 1557 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1558 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
54cdcae6 1559 gen_store_spr(SPR_PPR, t0);
ea363694 1560 tcg_temp_free(t0);
26d67362 1561 }
c80f84e3 1562#endif
9a64fbe4 1563 }
9a64fbe4 1564}
79aceca5 1565/* orc & orc. */
26d67362 1566GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
79aceca5 1567/* xor & xor. */
9a64fbe4
FB		 1568GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER)
1569{
9a64fbe4 1570 /* Optimisation for "set to zero" case */
26d67362 1571 if (rS(ctx->opcode) != rB(ctx->opcode))
312179c4 1572 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
26d67362
AJ		 1573 else
1574 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
76a66253 1575 if (unlikely(Rc(ctx->opcode) != 0))
26d67362 1576 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
9a64fbe4 1577}
79aceca5
FB		 1578/* ori */
1579GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1580{
76a66253 1581 target_ulong uimm = UIMM(ctx->opcode);
79aceca5 1582
9a64fbe4
FB		 1583 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1584 /* NOP */
76a66253 1585 /* XXX: should handle special NOPs for POWER series */
9a64fbe4 1586 return;
76a66253 1587 }
26d67362 1588 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
79aceca5
FB		 1589}
1590/* oris */
1591GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1592{
76a66253 1593 target_ulong uimm = UIMM(ctx->opcode);
79aceca5 1594
9a64fbe4
FB		 1595 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1596 /* NOP */
1597 return;
76a66253 1598 }
26d67362 1599 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
79aceca5
FB		 1600}
1601/* xori */
1602GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1603{
76a66253 1604 target_ulong uimm = UIMM(ctx->opcode);
9a64fbe4
FB		 1605
1606 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1607 /* NOP */
1608 return;
1609 }
26d67362 1610 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
79aceca5 1611}
79aceca5
FB		 1612/* xoris */
1613GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1614{
76a66253 1615 target_ulong uimm = UIMM(ctx->opcode);
9a64fbe4
FB		 1616
1617 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1618 /* NOP */
1619 return;
1620 }
26d67362 1621 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
79aceca5 1622}
d9bce9d9 1623/* popcntb : PowerPC 2.03 specification */
05332d70 1624GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB)
d9bce9d9 1625{
d9bce9d9
JM		 1626#if defined(TARGET_PPC64)
1627 if (ctx->sf_mode)
a7812ae4 1628 gen_helper_popcntb_64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
d9bce9d9
JM		 1629 else
1630#endif
a7812ae4 1631 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
d9bce9d9
JM		 1632}
1633
1634#if defined(TARGET_PPC64)
1635/* extsw & extsw. */
26d67362 1636GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
d9bce9d9 1637/* cntlzd */
26d67362
AJ		 1638GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B)
1639{
a7812ae4 1640 gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
26d67362
AJ		 1641 if (unlikely(Rc(ctx->opcode) != 0))
1642 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1643}
d9bce9d9
JM		 1644#endif
1645
79aceca5
FB		 1646/*** Integer rotate ***/
1647/* rlwimi & rlwimi. */
1648GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1649{
76a66253 1650 uint32_t mb, me, sh;
79aceca5
FB		 1651
1652 mb = MB(ctx->opcode);
1653 me = ME(ctx->opcode);
76a66253 1654 sh = SH(ctx->opcode);
d03ef511
AJ		 1655 if (likely(sh == 0 && mb == 0 && me == 31)) {
1656 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1657 } else {
d03ef511 1658 target_ulong mask;
a7812ae4
PB		 1659 TCGv t1;
1660 TCGv t0 = tcg_temp_new();
54843a58 1661#if defined(TARGET_PPC64)
a7812ae4
PB		 1662 TCGv_i32 t2 = tcg_temp_new_i32();
1663 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rS(ctx->opcode)]);
1664 tcg_gen_rotli_i32(t2, t2, sh);
1665 tcg_gen_extu_i32_i64(t0, t2);
1666 tcg_temp_free_i32(t2);
54843a58
AJ		 1667#else
1668 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1669#endif
76a66253 1670#if defined(TARGET_PPC64)
d03ef511
AJ		 1671 mb += 32;
1672 me += 32;
76a66253 1673#endif
d03ef511 1674 mask = MASK(mb, me);
a7812ae4 1675 t1 = tcg_temp_new();
d03ef511
AJ		 1676 tcg_gen_andi_tl(t0, t0, mask);
1677 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1678 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1679 tcg_temp_free(t0);
1680 tcg_temp_free(t1);
1681 }
76a66253 1682 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1683 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5
FB		 1684}
1685/* rlwinm & rlwinm. */
1686GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1687{
1688 uint32_t mb, me, sh;
3b46e624 1689
79aceca5
FB		 1690 sh = SH(ctx->opcode);
1691 mb = MB(ctx->opcode);
1692 me = ME(ctx->opcode);
d03ef511
AJ		 1693
1694 if (likely(mb == 0 && me == (31 - sh))) {
1695 if (likely(sh == 0)) {
1696 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1697 } else {
a7812ae4 1698 TCGv t0 = tcg_temp_new();
d03ef511
AJ		 1699 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1700 tcg_gen_shli_tl(t0, t0, sh);
1701 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1702 tcg_temp_free(t0);
79aceca5 1703 }
d03ef511 1704 } else if (likely(sh != 0 && me == 31 && sh == (32 - mb))) {
a7812ae4 1705 TCGv t0 = tcg_temp_new();
d03ef511
AJ		 1706 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1707 tcg_gen_shri_tl(t0, t0, mb);
1708 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1709 tcg_temp_free(t0);
1710 } else {
a7812ae4 1711 TCGv t0 = tcg_temp_new();
54843a58 1712#if defined(TARGET_PPC64)
a7812ae4 1713 TCGv_i32 t1 = tcg_temp_new_i32();
54843a58
AJ		 1714 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1715 tcg_gen_rotli_i32(t1, t1, sh);
1716 tcg_gen_extu_i32_i64(t0, t1);
a7812ae4 1717 tcg_temp_free_i32(t1);
54843a58
AJ		 1718#else
1719 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1720#endif
76a66253 1721#if defined(TARGET_PPC64)
d03ef511
AJ		 1722 mb += 32;
1723 me += 32;
76a66253 1724#endif
d03ef511
AJ		 1725 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1726 tcg_temp_free(t0);
1727 }
76a66253 1728 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1729 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5
FB		 1730}
1731/* rlwnm & rlwnm. */
1732GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1733{
1734 uint32_t mb, me;
54843a58
AJ		 1735 TCGv t0;
1736#if defined(TARGET_PPC64)
a7812ae4 1737 TCGv_i32 t1, t2;
54843a58 1738#endif
79aceca5
FB		 1739
1740 mb = MB(ctx->opcode);
1741 me = ME(ctx->opcode);
a7812ae4 1742 t0 = tcg_temp_new();
d03ef511 1743 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f);
54843a58 1744#if defined(TARGET_PPC64)
a7812ae4
PB		 1745 t1 = tcg_temp_new_i32();
1746 t2 = tcg_temp_new_i32();
54843a58
AJ		 1747 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1748 tcg_gen_trunc_i64_i32(t2, t0);
1749 tcg_gen_rotl_i32(t1, t1, t2);
1750 tcg_gen_extu_i32_i64(t0, t1);
a7812ae4
PB		 1751 tcg_temp_free_i32(t1);
1752 tcg_temp_free_i32(t2);
54843a58
AJ		 1753#else
1754 tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0);
1755#endif
76a66253
JM		 1756 if (unlikely(mb != 0 || me != 31)) {
1757#if defined(TARGET_PPC64)
1758 mb += 32;
1759 me += 32;
1760#endif
54843a58 1761 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
d03ef511 1762 } else {
54843a58 1763 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
79aceca5 1764 }
54843a58 1765 tcg_temp_free(t0);
76a66253 1766 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1767 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5
FB		 1768}
1769
d9bce9d9
JM		 1770#if defined(TARGET_PPC64)
1771#define GEN_PPC64_R2(name, opc1, opc2) \
c7697e1f 1772GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
d9bce9d9
JM		 1773{ \
1774 gen_##name(ctx, 0); \
1775} \
c7697e1f
JM		 1776GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
1777 PPC_64B) \
d9bce9d9
JM		 1778{ \
1779 gen_##name(ctx, 1); \
1780}
1781#define GEN_PPC64_R4(name, opc1, opc2) \
c7697e1f 1782GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
d9bce9d9
JM		 1783{ \
1784 gen_##name(ctx, 0, 0); \
1785} \
c7697e1f
JM		 1786GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
1787 PPC_64B) \
d9bce9d9
JM		 1788{ \
1789 gen_##name(ctx, 0, 1); \
1790} \
c7697e1f
JM		 1791GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
1792 PPC_64B) \
d9bce9d9
JM		 1793{ \
1794 gen_##name(ctx, 1, 0); \
1795} \
c7697e1f
JM		 1796GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
1797 PPC_64B) \
d9bce9d9
JM		 1798{ \
1799 gen_##name(ctx, 1, 1); \
1800}
51789c41 1801
b068d6a7
JM		 1802static always_inline void gen_rldinm (DisasContext *ctx, uint32_t mb,
1803 uint32_t me, uint32_t sh)
51789c41 1804{
d03ef511
AJ		 1805 if (likely(sh != 0 && mb == 0 && me == (63 - sh))) {
1806 tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1807 } else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) {
1808 tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb);
1809 } else {
a7812ae4 1810 TCGv t0 = tcg_temp_new();
54843a58 1811 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
d03ef511 1812 if (likely(mb == 0 && me == 63)) {
54843a58 1813 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
d03ef511
AJ		 1814 } else {
1815 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
51789c41 1816 }
d03ef511 1817 tcg_temp_free(t0);
51789c41 1818 }
51789c41 1819 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1820 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
51789c41 1821}
d9bce9d9 1822/* rldicl - rldicl. */
b068d6a7 1823static always_inline void gen_rldicl (DisasContext *ctx, int mbn, int shn)
d9bce9d9 1824{
51789c41 1825 uint32_t sh, mb;
d9bce9d9 1826
9d53c753
JM		 1827 sh = SH(ctx->opcode) | (shn << 5);
1828 mb = MB(ctx->opcode) | (mbn << 5);
51789c41 1829 gen_rldinm(ctx, mb, 63, sh);
d9bce9d9 1830}
51789c41 1831GEN_PPC64_R4(rldicl, 0x1E, 0x00);
d9bce9d9 1832/* rldicr - rldicr. */
b068d6a7 1833static always_inline void gen_rldicr (DisasContext *ctx, int men, int shn)
d9bce9d9 1834{
51789c41 1835 uint32_t sh, me;
d9bce9d9 1836
9d53c753
JM		 1837 sh = SH(ctx->opcode) | (shn << 5);
1838 me = MB(ctx->opcode) | (men << 5);
51789c41 1839 gen_rldinm(ctx, 0, me, sh);
d9bce9d9 1840}
51789c41 1841GEN_PPC64_R4(rldicr, 0x1E, 0x02);
d9bce9d9 1842/* rldic - rldic. */
b068d6a7 1843static always_inline void gen_rldic (DisasContext *ctx, int mbn, int shn)
d9bce9d9 1844{
51789c41 1845 uint32_t sh, mb;
d9bce9d9 1846
9d53c753
JM		 1847 sh = SH(ctx->opcode) | (shn << 5);
1848 mb = MB(ctx->opcode) | (mbn << 5);
51789c41
JM		 1849 gen_rldinm(ctx, mb, 63 - sh, sh);
1850}
1851GEN_PPC64_R4(rldic, 0x1E, 0x04);
1852
b068d6a7
JM		 1853static always_inline void gen_rldnm (DisasContext *ctx, uint32_t mb,
1854 uint32_t me)
51789c41 1855{
54843a58 1856 TCGv t0;
d03ef511
AJ		 1857
1858 mb = MB(ctx->opcode);
1859 me = ME(ctx->opcode);
a7812ae4 1860 t0 = tcg_temp_new();
d03ef511 1861 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
54843a58 1862 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
51789c41 1863 if (unlikely(mb != 0 || me != 63)) {
54843a58
AJ		 1864 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1865 } else {
1866 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1867 }
1868 tcg_temp_free(t0);
51789c41 1869 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1870 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
d9bce9d9 1871}
51789c41 1872
d9bce9d9 1873/* rldcl - rldcl. */
b068d6a7 1874static always_inline void gen_rldcl (DisasContext *ctx, int mbn)
d9bce9d9 1875{
51789c41 1876 uint32_t mb;
d9bce9d9 1877
9d53c753 1878 mb = MB(ctx->opcode) | (mbn << 5);
51789c41 1879 gen_rldnm(ctx, mb, 63);
d9bce9d9 1880}
36081602 1881GEN_PPC64_R2(rldcl, 0x1E, 0x08);
d9bce9d9 1882/* rldcr - rldcr. */
b068d6a7 1883static always_inline void gen_rldcr (DisasContext *ctx, int men)
d9bce9d9 1884{
51789c41 1885 uint32_t me;
d9bce9d9 1886
9d53c753 1887 me = MB(ctx->opcode) | (men << 5);
51789c41 1888 gen_rldnm(ctx, 0, me);
d9bce9d9 1889}
36081602 1890GEN_PPC64_R2(rldcr, 0x1E, 0x09);
d9bce9d9 1891/* rldimi - rldimi. */
b068d6a7 1892static always_inline void gen_rldimi (DisasContext *ctx, int mbn, int shn)
d9bce9d9 1893{
271a916e 1894 uint32_t sh, mb, me;
d9bce9d9 1895
9d53c753
JM		 1896 sh = SH(ctx->opcode) | (shn << 5);
1897 mb = MB(ctx->opcode) | (mbn << 5);
271a916e 1898 me = 63 - sh;
d03ef511
AJ		 1899 if (unlikely(sh == 0 && mb == 0)) {
1900 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1901 } else {
1902 TCGv t0, t1;
1903 target_ulong mask;
1904
a7812ae4 1905 t0 = tcg_temp_new();
54843a58 1906 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
a7812ae4 1907 t1 = tcg_temp_new();
d03ef511
AJ		 1908 mask = MASK(mb, me);
1909 tcg_gen_andi_tl(t0, t0, mask);
1910 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1911 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1912 tcg_temp_free(t0);
1913 tcg_temp_free(t1);
51789c41 1914 }
51789c41 1915 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1916 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
d9bce9d9 1917}
36081602 1918GEN_PPC64_R4(rldimi, 0x1E, 0x06);
d9bce9d9
JM		 1919#endif
1920
79aceca5
FB		 1921/*** Integer shift ***/
1922/* slw & slw. */
26d67362
AJ		 1923GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER)
1924{
fea0c503 1925 TCGv t0;
26d67362
AJ		 1926 int l1, l2;
1927 l1 = gen_new_label();
1928 l2 = gen_new_label();
1929
a7812ae4 1930 t0 = tcg_temp_local_new();
0cfe58cd
AJ		 1931 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1932 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x20, l1);
26d67362
AJ		 1933 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1934 tcg_gen_br(l2);
1935 gen_set_label(l1);
fea0c503 1936 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
26d67362
AJ		 1937 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
1938 gen_set_label(l2);
fea0c503 1939 tcg_temp_free(t0);
26d67362
AJ		 1940 if (unlikely(Rc(ctx->opcode) != 0))
1941 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1942}
79aceca5 1943/* sraw & sraw. */
26d67362
AJ		 1944GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER)
1945{
a7812ae4
PB		 1946 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)],
1947 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
26d67362
AJ		 1948 if (unlikely(Rc(ctx->opcode) != 0))
1949 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1950}
79aceca5
FB		 1951/* srawi & srawi. */
1952GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER)
1953{
26d67362
AJ		 1954 int sh = SH(ctx->opcode);
1955 if (sh != 0) {
1956 int l1, l2;
fea0c503 1957 TCGv t0;
26d67362
AJ		 1958 l1 = gen_new_label();
1959 l2 = gen_new_label();
a7812ae4 1960 t0 = tcg_temp_local_new();
fea0c503
AJ		 1961 tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1962 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
1963 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
1964 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
269f3e95 1965 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
26d67362
AJ		 1966 tcg_gen_br(l2);
1967 gen_set_label(l1);
269f3e95 1968 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
26d67362 1969 gen_set_label(l2);
fea0c503
AJ		 1970 tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1971 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], t0, sh);
1972 tcg_temp_free(t0);
26d67362
AJ		 1973 } else {
1974 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
269f3e95 1975 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
d9bce9d9 1976 }
76a66253 1977 if (unlikely(Rc(ctx->opcode) != 0))
26d67362 1978 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5
FB		 1979}
1980/* srw & srw. */
26d67362
AJ		 1981GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER)
1982{
fea0c503 1983 TCGv t0, t1;
26d67362
AJ		 1984 int l1, l2;
1985 l1 = gen_new_label();
1986 l2 = gen_new_label();
d9bce9d9 1987
a7812ae4 1988 t0 = tcg_temp_local_new();
0cfe58cd
AJ		 1989 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1990 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x20, l1);
26d67362
AJ		 1991 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1992 tcg_gen_br(l2);
1993 gen_set_label(l1);
a7812ae4 1994 t1 = tcg_temp_new();
fea0c503
AJ		 1995 tcg_gen_ext32u_tl(t1, cpu_gpr[rS(ctx->opcode)]);
1996 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t1, t0);
1997 tcg_temp_free(t1);
26d67362 1998 gen_set_label(l2);
fea0c503 1999 tcg_temp_free(t0);
26d67362
AJ		 2000 if (unlikely(Rc(ctx->opcode) != 0))
2001 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2002}
d9bce9d9
JM		 2003#if defined(TARGET_PPC64)
2004/* sld & sld. */
26d67362
AJ		 2005GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B)
2006{
fea0c503 2007 TCGv t0;
26d67362
AJ		 2008 int l1, l2;
2009 l1 = gen_new_label();
2010 l2 = gen_new_label();
2011
a7812ae4 2012 t0 = tcg_temp_local_new();
0cfe58cd
AJ		 2013 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x7f);
2014 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x40, l1);
26d67362
AJ		 2015 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
2016 tcg_gen_br(l2);
2017 gen_set_label(l1);
fea0c503 2018 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
26d67362 2019 gen_set_label(l2);
fea0c503 2020 tcg_temp_free(t0);
26d67362
AJ		 2021 if (unlikely(Rc(ctx->opcode) != 0))
2022 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2023}
d9bce9d9 2024/* srad & srad. */
26d67362
AJ		 2025GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B)
2026{
a7812ae4
PB		 2027 gen_helper_srad(cpu_gpr[rA(ctx->opcode)],
2028 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
26d67362
AJ		 2029 if (unlikely(Rc(ctx->opcode) != 0))
2030 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2031}
d9bce9d9 2032/* sradi & sradi. */
b068d6a7 2033static always_inline void gen_sradi (DisasContext *ctx, int n)
d9bce9d9 2034{
26d67362 2035 int sh = SH(ctx->opcode) + (n << 5);
d9bce9d9 2036 if (sh != 0) {
26d67362 2037 int l1, l2;
fea0c503 2038 TCGv t0;
26d67362
AJ		 2039 l1 = gen_new_label();
2040 l2 = gen_new_label();
a7812ae4 2041 t0 = tcg_temp_local_new();
26d67362 2042 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
fea0c503
AJ		 2043 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
2044 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
269f3e95 2045 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
26d67362
AJ		 2046 tcg_gen_br(l2);
2047 gen_set_label(l1);
269f3e95 2048 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
26d67362 2049 gen_set_label(l2);
a9730017 2050 tcg_temp_free(t0);
26d67362
AJ		 2051 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
2052 } else {
2053 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
269f3e95 2054 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
d9bce9d9 2055 }
d9bce9d9 2056 if (unlikely(Rc(ctx->opcode) != 0))
26d67362 2057 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
d9bce9d9 2058}
c7697e1f 2059GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B)
d9bce9d9
JM		 2060{
2061 gen_sradi(ctx, 0);
2062}
c7697e1f 2063GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B)
d9bce9d9
JM		 2064{
2065 gen_sradi(ctx, 1);
2066}
2067/* srd & srd. */
26d67362
AJ		 2068GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B)
2069{
fea0c503 2070 TCGv t0;
26d67362
AJ		 2071 int l1, l2;
2072 l1 = gen_new_label();
2073 l2 = gen_new_label();
2074
a7812ae4 2075 t0 = tcg_temp_local_new();
0cfe58cd
AJ		 2076 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x7f);
2077 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x40, l1);
26d67362
AJ		 2078 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
2079 tcg_gen_br(l2);
2080 gen_set_label(l1);
fea0c503 2081 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
26d67362 2082 gen_set_label(l2);
fea0c503 2083 tcg_temp_free(t0);
26d67362
AJ		 2084 if (unlikely(Rc(ctx->opcode) != 0))
2085 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2086}
d9bce9d9 2087#endif
79aceca5
FB		 2088
2089/*** Floating-Point arithmetic ***/
7c58044c 2090#define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
a750fc0b 2091GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type) \
9a64fbe4 2092{ \
76a66253 2093 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 2094 GEN_EXCP_NO_FP(ctx); \
3cc62370
FB		 2095 return; \
2096 } \
7c58044c 2097 gen_reset_fpstatus(); \
af12906f
AJ		 2098 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
2099 cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
4ecc3190 2100 if (isfloat) { \
af12906f 2101 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
4ecc3190 2102 } \
af12906f
AJ		 2103 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf, \
2104 Rc(ctx->opcode) != 0); \
9a64fbe4
FB		 2105}
2106
7c58044c
JM		 2107#define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
2108_GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
2109_GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
9a64fbe4 2110
7c58044c
JM		 2111#define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2112GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \
9a64fbe4 2113{ \
76a66253 2114 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 2115 GEN_EXCP_NO_FP(ctx); \
3cc62370
FB		 2116 return; \
2117 } \
7c58044c 2118 gen_reset_fpstatus(); \
af12906f
AJ		 2119 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
2120 cpu_fpr[rB(ctx->opcode)]); \
4ecc3190 2121 if (isfloat) { \
af12906f 2122 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
4ecc3190 2123 } \
af12906f
AJ		 2124 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2125 set_fprf, Rc(ctx->opcode) != 0); \
9a64fbe4 2126}
7c58044c
JM		 2127#define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
2128_GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2129_GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
9a64fbe4 2130
7c58044c
JM		 2131#define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2132GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \
9a64fbe4 2133{ \
76a66253 2134 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 2135 GEN_EXCP_NO_FP(ctx); \
3cc62370
FB		 2136 return; \
2137 } \
7c58044c 2138 gen_reset_fpstatus(); \
af12906f
AJ		 2139 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
2140 cpu_fpr[rC(ctx->opcode)]); \
4ecc3190 2141 if (isfloat) { \
af12906f 2142 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
4ecc3190 2143 } \
af12906f
AJ		 2144 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2145 set_fprf, Rc(ctx->opcode) != 0); \
9a64fbe4 2146}
7c58044c
JM		 2147#define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
2148_GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2149_GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
9a64fbe4 2150
7c58044c 2151#define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
a750fc0b 2152GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type) \
9a64fbe4 2153{ \
76a66253 2154 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 2155 GEN_EXCP_NO_FP(ctx); \
3cc62370
FB		 2156 return; \
2157 } \
7c58044c 2158 gen_reset_fpstatus(); \
af12906f
AJ		 2159 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2160 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2161 set_fprf, Rc(ctx->opcode) != 0); \
79aceca5
FB		 2162}
2163
7c58044c 2164#define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
a750fc0b 2165GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type) \
9a64fbe4 2166{ \
76a66253 2167 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 2168 GEN_EXCP_NO_FP(ctx); \
3cc62370
FB		 2169 return; \
2170 } \
7c58044c 2171 gen_reset_fpstatus(); \
af12906f
AJ		 2172 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2173 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2174 set_fprf, Rc(ctx->opcode) != 0); \
79aceca5
FB		 2175}
2176
9a64fbe4 2177/* fadd - fadds */
7c58044c 2178GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
4ecc3190 2179/* fdiv - fdivs */
7c58044c 2180GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
4ecc3190 2181/* fmul - fmuls */
7c58044c 2182GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
79aceca5 2183
d7e4b87e 2184/* fre */
7c58044c 2185GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
d7e4b87e 2186
a750fc0b 2187/* fres */
7c58044c 2188GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
79aceca5 2189
a750fc0b 2190/* frsqrte */
7c58044c
JM		 2191GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
2192
2193/* frsqrtes */
af12906f 2194GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES)
7c58044c 2195{
af12906f
AJ		 2196 if (unlikely(!ctx->fpu_enabled)) {
2197 GEN_EXCP_NO_FP(ctx);
2198 return;
2199 }
2200 gen_reset_fpstatus();
2201 gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2202 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]);
2203 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
7c58044c 2204}
79aceca5 2205
a750fc0b 2206/* fsel */
7c58044c 2207_GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
4ecc3190 2208/* fsub - fsubs */
7c58044c 2209GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
79aceca5
FB		 2210/* Optional: */
2211/* fsqrt */
a750fc0b 2212GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
c7d344af 2213{
76a66253 2214 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2215 GEN_EXCP_NO_FP(ctx);
c7d344af
FB		 2216 return;
2217 }
7c58044c 2218 gen_reset_fpstatus();
af12906f
AJ		 2219 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2220 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
c7d344af 2221}
79aceca5 2222
a750fc0b 2223GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
79aceca5 2224{
76a66253 2225 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2226 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2227 return;
2228 }
7c58044c 2229 gen_reset_fpstatus();
af12906f
AJ		 2230 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2231 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]);
2232 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
79aceca5
FB		 2233}
2234
2235/*** Floating-Point multiply-and-add ***/
4ecc3190 2236/* fmadd - fmadds */
7c58044c 2237GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
4ecc3190 2238/* fmsub - fmsubs */
7c58044c 2239GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
4ecc3190 2240/* fnmadd - fnmadds */
7c58044c 2241GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
4ecc3190 2242/* fnmsub - fnmsubs */
7c58044c 2243GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
79aceca5
FB		 2244
2245/*** Floating-Point round & convert ***/
2246/* fctiw */
7c58044c 2247GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
79aceca5 2248/* fctiwz */
7c58044c 2249GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
79aceca5 2250/* frsp */
7c58044c 2251GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
426613db
JM		 2252#if defined(TARGET_PPC64)
2253/* fcfid */
7c58044c 2254GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B);
426613db 2255/* fctid */
7c58044c 2256GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B);
426613db 2257/* fctidz */
7c58044c 2258GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B);
426613db 2259#endif
79aceca5 2260
d7e4b87e 2261/* frin */
7c58044c 2262GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
d7e4b87e 2263/* friz */
7c58044c 2264GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
d7e4b87e 2265/* frip */
7c58044c 2266GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
d7e4b87e 2267/* frim */
7c58044c 2268GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
d7e4b87e 2269
79aceca5
FB		 2270/*** Floating-Point compare ***/
2271/* fcmpo */
76a66253 2272GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT)
79aceca5 2273{
76a66253 2274 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2275 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2276 return;
2277 }
7c58044c 2278 gen_reset_fpstatus();
af12906f
AJ		 2279 gen_helper_fcmpo(cpu_crf[crfD(ctx->opcode)],
2280 cpu_fpr[rA(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2281 gen_helper_float_check_status();
79aceca5
FB		 2282}
2283
2284/* fcmpu */
76a66253 2285GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT)
79aceca5 2286{
76a66253 2287 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2288 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2289 return;
2290 }
7c58044c 2291 gen_reset_fpstatus();
af12906f
AJ		 2292 gen_helper_fcmpu(cpu_crf[crfD(ctx->opcode)],
2293 cpu_fpr[rA(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2294 gen_helper_float_check_status();
79aceca5
FB		 2295}
2296
9a64fbe4
FB		 2297/*** Floating-point move ***/
2298/* fabs */
7c58044c
JM		 2299/* XXX: beware that fabs never checks for NaNs nor update FPSCR */
2300GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT);
9a64fbe4
FB		 2301
2302/* fmr - fmr. */
7c58044c 2303/* XXX: beware that fmr never checks for NaNs nor update FPSCR */
9a64fbe4
FB		 2304GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT)
2305{
76a66253 2306 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2307 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2308 return;
2309 }
af12906f
AJ		 2310 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2311 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
9a64fbe4
FB		 2312}
2313
2314/* fnabs */
7c58044c
JM		 2315/* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
2316GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT);
9a64fbe4 2317/* fneg */
7c58044c
JM		 2318/* XXX: beware that fneg never checks for NaNs nor update FPSCR */
2319GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT);
9a64fbe4 2320
79aceca5
FB		 2321/*** Floating-Point status & ctrl register ***/
2322/* mcrfs */
2323GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT)
2324{
7c58044c
JM		 2325 int bfa;
2326
76a66253 2327 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2328 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2329 return;
2330 }
7c58044c
JM		 2331 gen_optimize_fprf();
2332 bfa = 4 * (7 - crfS(ctx->opcode));
e1571908
AJ		 2333 tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_fpscr, bfa);
2334 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
af12906f 2335 tcg_gen_andi_i32(cpu_fpscr, cpu_fpscr, ~(0xF << bfa));
79aceca5
FB		 2336}
2337
2338/* mffs */
2339GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT)
2340{
76a66253 2341 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2342 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2343 return;
2344 }
7c58044c
JM		 2345 gen_optimize_fprf();
2346 gen_reset_fpstatus();
af12906f
AJ		 2347 tcg_gen_extu_i32_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr);
2348 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
79aceca5
FB		 2349}
2350
2351/* mtfsb0 */
2352GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT)
2353{
fb0eaffc 2354 uint8_t crb;
3b46e624 2355
76a66253 2356 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2357 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2358 return;
2359 }
7c58044c
JM		 2360 crb = 32 - (crbD(ctx->opcode) >> 2);
2361 gen_optimize_fprf();
2362 gen_reset_fpstatus();
2363 if (likely(crb != 30 && crb != 29))
af12906f 2364 tcg_gen_andi_i32(cpu_fpscr, cpu_fpscr, ~(1 << crb));
7c58044c 2365 if (unlikely(Rc(ctx->opcode) != 0)) {
e1571908 2366 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
7c58044c 2367 }
79aceca5
FB		 2368}
2369
2370/* mtfsb1 */
2371GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT)
2372{
fb0eaffc 2373 uint8_t crb;
3b46e624 2374
76a66253 2375 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2376 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2377 return;
2378 }
7c58044c
JM		 2379 crb = 32 - (crbD(ctx->opcode) >> 2);
2380 gen_optimize_fprf();
2381 gen_reset_fpstatus();
2382 /* XXX: we pretend we can only do IEEE floating-point computations */
af12906f 2383 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
0f2f39c2 2384 TCGv_i32 t0 = tcg_const_i32(crb);
af12906f 2385 gen_helper_fpscr_setbit(t0);
0f2f39c2 2386 tcg_temp_free_i32(t0);
af12906f 2387 }
7c58044c 2388 if (unlikely(Rc(ctx->opcode) != 0)) {
e1571908 2389 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
7c58044c
JM		 2390 }
2391 /* We can raise a differed exception */
af12906f 2392 gen_helper_float_check_status();
79aceca5
FB		 2393}
2394
2395/* mtfsf */
2396GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x02010000, PPC_FLOAT)
2397{
0f2f39c2 2398 TCGv_i32 t0;
af12906f 2399
76a66253 2400 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2401 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2402 return;
2403 }
7c58044c 2404 gen_optimize_fprf();
7c58044c 2405 gen_reset_fpstatus();
af12906f
AJ		 2406 t0 = tcg_const_i32(FM(ctx->opcode));
2407 gen_helper_store_fpscr(cpu_fpr[rB(ctx->opcode)], t0);
0f2f39c2 2408 tcg_temp_free_i32(t0);
7c58044c 2409 if (unlikely(Rc(ctx->opcode) != 0)) {
e1571908 2410 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
7c58044c
JM		 2411 }
2412 /* We can raise a differed exception */
af12906f 2413 gen_helper_float_check_status();
79aceca5
FB		 2414}
2415
2416/* mtfsfi */
2417GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT)
2418{
7c58044c 2419 int bf, sh;
0f2f39c2
AJ		 2420 TCGv_i64 t0;
2421 TCGv_i32 t1;
7c58044c 2422
76a66253 2423 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2424 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2425 return;
2426 }
7c58044c
JM		 2427 bf = crbD(ctx->opcode) >> 2;
2428 sh = 7 - bf;
2429 gen_optimize_fprf();
7c58044c 2430 gen_reset_fpstatus();
0f2f39c2 2431 t0 = tcg_const_i64(FPIMM(ctx->opcode) << (4 * sh));
af12906f
AJ		 2432 t1 = tcg_const_i32(1 << sh);
2433 gen_helper_store_fpscr(t0, t1);
0f2f39c2
AJ		 2434 tcg_temp_free_i64(t0);
2435 tcg_temp_free_i32(t1);
7c58044c 2436 if (unlikely(Rc(ctx->opcode) != 0)) {
e1571908 2437 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
7c58044c
JM		 2438 }
2439 /* We can raise a differed exception */
af12906f 2440 gen_helper_float_check_status();
79aceca5
FB		 2441}
2442
76a66253
JM		 2443/*** Addressing modes ***/
2444/* Register indirect with immediate index : EA = (rA|0) + SIMM */
e2be8d8d
AJ		 2445static always_inline void gen_addr_imm_index (TCGv EA,
2446 DisasContext *ctx,
b068d6a7 2447 target_long maskl)
76a66253
JM		 2448{
2449 target_long simm = SIMM(ctx->opcode);
2450
be147d08 2451 simm &= ~maskl;
e2be8d8d
AJ		 2452 if (rA(ctx->opcode) == 0)
2453 tcg_gen_movi_tl(EA, simm);
2454 else if (likely(simm != 0))
2455 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2456 else
2457 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 2458}
2459
e2be8d8d
AJ		 2460static always_inline void gen_addr_reg_index (TCGv EA,
2461 DisasContext *ctx)
76a66253 2462{
e2be8d8d
AJ		 2463 if (rA(ctx->opcode) == 0)
2464 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2465 else
2466 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
76a66253
JM		 2467}
2468
e2be8d8d
AJ		 2469static always_inline void gen_addr_register (TCGv EA,
2470 DisasContext *ctx)
76a66253 2471{
e2be8d8d
AJ		 2472 if (rA(ctx->opcode) == 0)
2473 tcg_gen_movi_tl(EA, 0);
2474 else
2475 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 2476}
2477
cf360a32
AJ		 2478static always_inline void gen_check_align (DisasContext *ctx, TCGv EA, int mask)
2479{
2480 int l1 = gen_new_label();
2481 TCGv t0 = tcg_temp_new();
2482 TCGv_i32 t1, t2;
2483 /* NIP cannot be restored if the memory exception comes from an helper */
2484 gen_update_nip(ctx, ctx->nip - 4);
2485 tcg_gen_andi_tl(t0, EA, mask);
2486 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2487 t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
2488 t2 = tcg_const_i32(0);
2489 gen_helper_raise_exception_err(t1, t2);
2490 tcg_temp_free_i32(t1);
2491 tcg_temp_free_i32(t2);
2492 gen_set_label(l1);
2493 tcg_temp_free(t0);
2494}
2495
7863667f 2496/*** Integer load ***/
b61f2753
AJ		 2497#if defined(TARGET_PPC64)
2498#define GEN_QEMU_LD_PPC64(width) \
2499static always_inline void gen_qemu_ld##width##_ppc64(TCGv t0, TCGv t1, int flags)\
2500{ \
2501 if (likely(flags & 2)) \
2502 tcg_gen_qemu_ld##width(t0, t1, flags >> 2); \
2503 else { \
a7812ae4 2504 TCGv addr = tcg_temp_new(); \
b61f2753
AJ		 2505 tcg_gen_ext32u_tl(addr, t1); \
2506 tcg_gen_qemu_ld##width(t0, addr, flags >> 2); \
2507 tcg_temp_free(addr); \
2508 } \
2509}
2510GEN_QEMU_LD_PPC64(8u)
2511GEN_QEMU_LD_PPC64(8s)
2512GEN_QEMU_LD_PPC64(16u)
2513GEN_QEMU_LD_PPC64(16s)
2514GEN_QEMU_LD_PPC64(32u)
2515GEN_QEMU_LD_PPC64(32s)
2516GEN_QEMU_LD_PPC64(64)
2517
2518#define GEN_QEMU_ST_PPC64(width) \
2519static always_inline void gen_qemu_st##width##_ppc64(TCGv t0, TCGv t1, int flags)\
2520{ \
2521 if (likely(flags & 2)) \
2522 tcg_gen_qemu_st##width(t0, t1, flags >> 2); \
2523 else { \
a7812ae4 2524 TCGv addr = tcg_temp_new(); \
b61f2753
AJ		 2525 tcg_gen_ext32u_tl(addr, t1); \
2526 tcg_gen_qemu_st##width(t0, addr, flags >> 2); \
2527 tcg_temp_free(addr); \
2528 } \
2529}
2530GEN_QEMU_ST_PPC64(8)
2531GEN_QEMU_ST_PPC64(16)
2532GEN_QEMU_ST_PPC64(32)
2533GEN_QEMU_ST_PPC64(64)
2534
ea363694 2535static always_inline void gen_qemu_ld8u(TCGv arg0, TCGv arg1, int flags)
b61f2753 2536{
ea363694 2537 gen_qemu_ld8u_ppc64(arg0, arg1, flags);
b61f2753
AJ		 2538}
2539
ea363694 2540static always_inline void gen_qemu_ld8s(TCGv arg0, TCGv arg1, int flags)
b61f2753 2541{
ea363694 2542 gen_qemu_ld8s_ppc64(arg0, arg1, flags);
b61f2753
AJ		 2543}
2544
ea363694 2545static always_inline void gen_qemu_ld16u(TCGv arg0, TCGv arg1, int flags)
b61f2753
AJ		 2546{
2547 if (unlikely(flags & 1)) {
a7812ae4 2548 TCGv_i32 t0;
ea363694 2549 gen_qemu_ld16u_ppc64(arg0, arg1, flags);
a7812ae4 2550 t0 = tcg_temp_new_i32();
ea363694
AJ		 2551 tcg_gen_trunc_tl_i32(t0, arg0);
2552 tcg_gen_bswap16_i32(t0, t0);
2553 tcg_gen_extu_i32_tl(arg0, t0);
a7812ae4 2554 tcg_temp_free_i32(t0);
b61f2753 2555 } else
ea363694 2556 gen_qemu_ld16u_ppc64(arg0, arg1, flags);
b61f2753
AJ		 2557}
2558
ea363694 2559static always_inline void gen_qemu_ld16s(TCGv arg0, TCGv arg1, int flags)
b61f2753
AJ		 2560{
2561 if (unlikely(flags & 1)) {
a7812ae4 2562 TCGv_i32 t0;
ea363694 2563 gen_qemu_ld16u_ppc64(arg0, arg1, flags);
a7812ae4 2564 t0 = tcg_temp_new_i32();
ea363694
AJ		 2565 tcg_gen_trunc_tl_i32(t0, arg0);
2566 tcg_gen_bswap16_i32(t0, t0);
2567 tcg_gen_extu_i32_tl(arg0, t0);
2568 tcg_gen_ext16s_tl(arg0, arg0);
a7812ae4 2569 tcg_temp_free_i32(t0);
b61f2753 2570 } else
ea363694 2571 gen_qemu_ld16s_ppc64(arg0, arg1, flags);
b61f2753
AJ		 2572}
2573
ea363694 2574static always_inline void gen_qemu_ld32u(TCGv arg0, TCGv arg1, int flags)
b61f2753
AJ		 2575{
2576 if (unlikely(flags & 1)) {
a7812ae4 2577 TCGv_i32 t0;
ea363694 2578 gen_qemu_ld32u_ppc64(arg0, arg1, flags);
a7812ae4 2579 t0 = tcg_temp_new_i32();
ea363694
AJ		 2580 tcg_gen_trunc_tl_i32(t0, arg0);
2581 tcg_gen_bswap_i32(t0, t0);
2582 tcg_gen_extu_i32_tl(arg0, t0);
a7812ae4 2583 tcg_temp_free_i32(t0);
b61f2753 2584 } else
ea363694 2585 gen_qemu_ld32u_ppc64(arg0, arg1, flags);
b61f2753
AJ		 2586}
2587
ea363694 2588static always_inline void gen_qemu_ld32s(TCGv arg0, TCGv arg1, int flags)
b61f2753
AJ		 2589{
2590 if (unlikely(flags & 1)) {
a7812ae4 2591 TCGv_i32 t0;
ea363694 2592 gen_qemu_ld32u_ppc64(arg0, arg1, flags);
a7812ae4 2593 t0 = tcg_temp_new_i32();
ea363694
AJ		 2594 tcg_gen_trunc_tl_i32(t0, arg0);
2595 tcg_gen_bswap_i32(t0, t0);
2596 tcg_gen_ext_i32_tl(arg0, t0);
a7812ae4 2597 tcg_temp_free_i32(t0);
b61f2753 2598 } else
ea363694 2599 gen_qemu_ld32s_ppc64(arg0, arg1, flags);
b61f2753
AJ		 2600}
2601
ea363694 2602static always_inline void gen_qemu_ld64(TCGv arg0, TCGv arg1, int flags)
b61f2753 2603{
ea363694 2604 gen_qemu_ld64_ppc64(arg0, arg1, flags);
b61f2753 2605 if (unlikely(flags & 1))
ea363694 2606 tcg_gen_bswap_i64(arg0, arg0);
b61f2753
AJ		 2607}
2608
ea363694 2609static always_inline void gen_qemu_st8(TCGv arg0, TCGv arg1, int flags)
b61f2753 2610{
ea363694 2611 gen_qemu_st8_ppc64(arg0, arg1, flags);
b61f2753
AJ		 2612}
2613
ea363694 2614static always_inline void gen_qemu_st16(TCGv arg0, TCGv arg1, int flags)
b61f2753
AJ		 2615{
2616 if (unlikely(flags & 1)) {
a7812ae4
PB		 2617 TCGv_i32 t0;
2618 TCGv_i64 t1;
2619 t0 = tcg_temp_new_i32();
ea363694
AJ		 2620 tcg_gen_trunc_tl_i32(t0, arg0);
2621 tcg_gen_ext16u_i32(t0, t0);
2622 tcg_gen_bswap16_i32(t0, t0);
a7812ae4 2623 t1 = tcg_temp_new_i64();
ea363694 2624 tcg_gen_extu_i32_tl(t1, t0);
a7812ae4 2625 tcg_temp_free_i32(t0);
ea363694 2626 gen_qemu_st16_ppc64(t1, arg1, flags);
a7812ae4 2627 tcg_temp_free_i64(t1);
b61f2753 2628 } else
ea363694 2629 gen_qemu_st16_ppc64(arg0, arg1, flags);
b61f2753
AJ		 2630}
2631
ea363694 2632static always_inline void gen_qemu_st32(TCGv arg0, TCGv arg1, int flags)
b61f2753
AJ		 2633{
2634 if (unlikely(flags & 1)) {
a7812ae4
PB		 2635 TCGv_i32 t0;
2636 TCGv_i64 t1;
2637 t0 = tcg_temp_new_i32();
ea363694
AJ		 2638 tcg_gen_trunc_tl_i32(t0, arg0);
2639 tcg_gen_bswap_i32(t0, t0);
a7812ae4 2640 t1 = tcg_temp_new_i64();
ea363694 2641 tcg_gen_extu_i32_tl(t1, t0);
a7812ae4 2642 tcg_temp_free_i32(t0);
ea363694 2643 gen_qemu_st32_ppc64(t1, arg1, flags);
a7812ae4 2644 tcg_temp_free_i64(t1);
b61f2753 2645 } else
ea363694 2646 gen_qemu_st32_ppc64(arg0, arg1, flags);
b61f2753
AJ		 2647}
2648
ea363694 2649static always_inline void gen_qemu_st64(TCGv arg0, TCGv arg1, int flags)
b61f2753
AJ		 2650{
2651 if (unlikely(flags & 1)) {
a7812ae4 2652 TCGv_i64 t0 = tcg_temp_new_i64();
ea363694
AJ		 2653 tcg_gen_bswap_i64(t0, arg0);
2654 gen_qemu_st64_ppc64(t0, arg1, flags);
a7812ae4 2655 tcg_temp_free_i64(t0);
b61f2753 2656 } else
ea363694 2657 gen_qemu_st64_ppc64(arg0, arg1, flags);
b61f2753
AJ		 2658}
2659
2660
2661#else /* defined(TARGET_PPC64) */
a0d7d5a7
AJ		 2662#define GEN_QEMU_LD_PPC32(width) \
2663static always_inline void gen_qemu_ld##width##_ppc32(TCGv arg0, TCGv arg1, int flags) \
2664{ \
2665 tcg_gen_qemu_ld##width(arg0, arg1, flags >> 1); \
b61f2753
AJ		 2666}
2667GEN_QEMU_LD_PPC32(8u)
2668GEN_QEMU_LD_PPC32(8s)
2669GEN_QEMU_LD_PPC32(16u)
2670GEN_QEMU_LD_PPC32(16s)
2671GEN_QEMU_LD_PPC32(32u)
2672GEN_QEMU_LD_PPC32(32s)
a0d7d5a7
AJ		 2673static always_inline void gen_qemu_ld64_ppc32(TCGv_i64 arg0, TCGv arg1, int flags)
2674{
2675 tcg_gen_qemu_ld64(arg0, arg1, flags >> 1);
2676}
b61f2753 2677
a0d7d5a7
AJ		 2678#define GEN_QEMU_ST_PPC32(width) \
2679static always_inline void gen_qemu_st##width##_ppc32(TCGv arg0, TCGv arg1, int flags) \
2680{ \
2681 tcg_gen_qemu_st##width(arg0, arg1, flags >> 1); \
b61f2753
AJ		 2682}
2683GEN_QEMU_ST_PPC32(8)
2684GEN_QEMU_ST_PPC32(16)
2685GEN_QEMU_ST_PPC32(32)
a0d7d5a7
AJ		 2686static always_inline void gen_qemu_st64_ppc32(TCGv_i64 arg0, TCGv arg1, int flags)
2687{
2688 tcg_gen_qemu_st64(arg0, arg1, flags >> 1);
2689}
b61f2753 2690
ea363694 2691static always_inline void gen_qemu_ld8u(TCGv arg0, TCGv arg1, int flags)
b61f2753 2692{
ea363694 2693 gen_qemu_ld8u_ppc32(arg0, arg1, flags >> 1);
b61f2753
AJ		 2694}
2695
ea363694 2696static always_inline void gen_qemu_ld8s(TCGv arg0, TCGv arg1, int flags)
b61f2753 2697{
ea363694 2698 gen_qemu_ld8s_ppc32(arg0, arg1, flags >> 1);
b61f2753
AJ		 2699}
2700
ea363694 2701static always_inline void gen_qemu_ld16u(TCGv arg0, TCGv arg1, int flags)
b61f2753 2702{
ea363694 2703 gen_qemu_ld16u_ppc32(arg0, arg1, flags >> 1);
b61f2753 2704 if (unlikely(flags & 1))
ea363694 2705 tcg_gen_bswap16_i32(arg0, arg0);
b61f2753
AJ		 2706}
2707
ea363694 2708static always_inline void gen_qemu_ld16s(TCGv arg0, TCGv arg1, int flags)
b61f2753
AJ		 2709{
2710 if (unlikely(flags & 1)) {
ea363694
AJ		 2711 gen_qemu_ld16u_ppc32(arg0, arg1, flags);
2712 tcg_gen_bswap16_i32(arg0, arg0);
2713 tcg_gen_ext16s_i32(arg0, arg0);
b61f2753 2714 } else
ea363694 2715 gen_qemu_ld16s_ppc32(arg0, arg1, flags);
b61f2753
AJ		 2716}
2717
ea363694 2718static always_inline void gen_qemu_ld32u(TCGv arg0, TCGv arg1, int flags)
b61f2753 2719{
ea363694 2720 gen_qemu_ld32u_ppc32(arg0, arg1, flags);
b61f2753 2721 if (unlikely(flags & 1))
ea363694 2722 tcg_gen_bswap_i32(arg0, arg0);
b61f2753
AJ		 2723}
2724
a0d7d5a7
AJ		 2725static always_inline void gen_qemu_ld64(TCGv_i64 arg0, TCGv arg1, int flags)
2726{
2727 gen_qemu_ld64_ppc32(arg0, arg1, flags);
2728 if (unlikely(flags & 1))
2729 tcg_gen_bswap_i64(arg0, arg0);
2730}
2731
ea363694 2732static always_inline void gen_qemu_st8(TCGv arg0, TCGv arg1, int flags)
b61f2753 2733{
e32ad5c2 2734 gen_qemu_st8_ppc32(arg0, arg1, flags);
b61f2753
AJ		 2735}
2736
ea363694 2737static always_inline void gen_qemu_st16(TCGv arg0, TCGv arg1, int flags)
b61f2753
AJ		 2738{
2739 if (unlikely(flags & 1)) {
a7812ae4 2740 TCGv_i32 temp = tcg_temp_new_i32();
ea363694 2741 tcg_gen_ext16u_i32(temp, arg0);
b61f2753 2742 tcg_gen_bswap16_i32(temp, temp);
e32ad5c2 2743 gen_qemu_st16_ppc32(temp, arg1, flags);
a7812ae4 2744 tcg_temp_free_i32(temp);
b61f2753 2745 } else
e32ad5c2 2746 gen_qemu_st16_ppc32(arg0, arg1, flags);
b61f2753
AJ		 2747}
2748
ea363694 2749static always_inline void gen_qemu_st32(TCGv arg0, TCGv arg1, int flags)
b61f2753
AJ		 2750{
2751 if (unlikely(flags & 1)) {
a7812ae4 2752 TCGv_i32 temp = tcg_temp_new_i32();
ea363694 2753 tcg_gen_bswap_i32(temp, arg0);
e32ad5c2 2754 gen_qemu_st32_ppc32(temp, arg1, flags);
a7812ae4 2755 tcg_temp_free_i32(temp);
b61f2753 2756 } else
e32ad5c2 2757 gen_qemu_st32_ppc32(arg0, arg1, flags);
b61f2753
AJ		 2758}
2759
a0d7d5a7
AJ		 2760static always_inline void gen_qemu_st64(TCGv_i64 arg0, TCGv arg1, int flags)
2761{
2762 if (unlikely(flags & 1)) {
2763 TCGv_i64 temp = tcg_temp_new_i64();
2764 tcg_gen_bswap_i64(temp, arg0);
2765 gen_qemu_st64_ppc32(temp, arg1, flags);
2766 tcg_temp_free_i64(temp);
2767 } else
2768 gen_qemu_st64_ppc32(arg0, arg1, flags);
2769}
b61f2753
AJ		 2770#endif
2771
0c8aacd4
AJ		 2772#define GEN_LD(name, ldop, opc, type) \
2773GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2774{ \
0c8aacd4 2775 TCGv EA = tcg_temp_new(); \
a7859e89 2776 gen_set_access_type(ACCESS_INT); \
b61f2753 2777 gen_addr_imm_index(EA, ctx, 0); \
0c8aacd4 2778 gen_qemu_##ldop(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
b61f2753 2779 tcg_temp_free(EA); \
79aceca5
FB		 2780}
2781
0c8aacd4
AJ		 2782#define GEN_LDU(name, ldop, opc, type) \
2783GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2784{ \
b61f2753 2785 TCGv EA; \
76a66253
JM		 2786 if (unlikely(rA(ctx->opcode) == 0 || \
2787 rA(ctx->opcode) == rD(ctx->opcode))) { \
e1833e1f 2788 GEN_EXCP_INVAL(ctx); \
9fddaa0c 2789 return; \
9a64fbe4 2790 } \
0c8aacd4 2791 EA = tcg_temp_new(); \
a7859e89 2792 gen_set_access_type(ACCESS_INT); \
9d53c753 2793 if (type == PPC_64B) \
b61f2753 2794 gen_addr_imm_index(EA, ctx, 0x03); \
9d53c753 2795 else \
b61f2753 2796 gen_addr_imm_index(EA, ctx, 0); \
0c8aacd4 2797 gen_qemu_##ldop(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
b61f2753
AJ		 2798 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2799 tcg_temp_free(EA); \
79aceca5
FB		 2800}
2801
0c8aacd4
AJ		 2802#define GEN_LDUX(name, ldop, opc2, opc3, type) \
2803GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2804{ \
b61f2753 2805 TCGv EA; \
76a66253
JM		 2806 if (unlikely(rA(ctx->opcode) == 0 || \
2807 rA(ctx->opcode) == rD(ctx->opcode))) { \
e1833e1f 2808 GEN_EXCP_INVAL(ctx); \
9fddaa0c 2809 return; \
9a64fbe4 2810 } \
0c8aacd4 2811 EA = tcg_temp_new(); \
a7859e89 2812 gen_set_access_type(ACCESS_INT); \
b61f2753 2813 gen_addr_reg_index(EA, ctx); \
0c8aacd4 2814 gen_qemu_##ldop(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
b61f2753
AJ		 2815 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2816 tcg_temp_free(EA); \
79aceca5
FB		 2817}
2818
0c8aacd4
AJ		 2819#define GEN_LDX(name, ldop, opc2, opc3, type) \
2820GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2821{ \
0c8aacd4 2822 TCGv EA = tcg_temp_new(); \
a7859e89 2823 gen_set_access_type(ACCESS_INT); \
b61f2753 2824 gen_addr_reg_index(EA, ctx); \
0c8aacd4 2825 gen_qemu_##ldop(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
b61f2753 2826 tcg_temp_free(EA); \
79aceca5
FB		 2827}
2828
0c8aacd4
AJ		 2829#define GEN_LDS(name, ldop, op, type) \
2830GEN_LD(name, ldop, op | 0x20, type); \
2831GEN_LDU(name, ldop, op | 0x21, type); \
2832GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2833GEN_LDX(name, ldop, 0x17, op | 0x00, type)
79aceca5
FB		 2834
2835/* lbz lbzu lbzux lbzx */
0c8aacd4 2836GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
79aceca5 2837/* lha lhau lhaux lhax */
0c8aacd4 2838GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
79aceca5 2839/* lhz lhzu lhzux lhzx */
0c8aacd4 2840GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
79aceca5 2841/* lwz lwzu lwzux lwzx */
0c8aacd4 2842GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
d9bce9d9 2843#if defined(TARGET_PPC64)
d9bce9d9 2844/* lwaux */
0c8aacd4 2845GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
d9bce9d9 2846/* lwax */
0c8aacd4 2847GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
d9bce9d9 2848/* ldux */
0c8aacd4 2849GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B);
d9bce9d9 2850/* ldx */
0c8aacd4 2851GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B);
d9bce9d9
JM		 2852GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B)
2853{
b61f2753 2854 TCGv EA;
d9bce9d9
JM		 2855 if (Rc(ctx->opcode)) {
2856 if (unlikely(rA(ctx->opcode) == 0 ||
2857 rA(ctx->opcode) == rD(ctx->opcode))) {
e1833e1f 2858 GEN_EXCP_INVAL(ctx);
d9bce9d9
JM		 2859 return;
2860 }
2861 }
a7812ae4 2862 EA = tcg_temp_new();
a7859e89 2863 gen_set_access_type(ACCESS_INT);
b61f2753 2864 gen_addr_imm_index(EA, ctx, 0x03);
d9bce9d9
JM		 2865 if (ctx->opcode & 0x02) {
2866 /* lwa (lwau is undefined) */
b61f2753 2867 gen_qemu_ld32s(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx);
d9bce9d9
JM		 2868 } else {
2869 /* ld - ldu */
b61f2753 2870 gen_qemu_ld64(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx);
d9bce9d9 2871 }
d9bce9d9 2872 if (Rc(ctx->opcode))
b61f2753
AJ		 2873 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2874 tcg_temp_free(EA);
d9bce9d9 2875}
be147d08
JM		 2876/* lq */
2877GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX)
2878{
2879#if defined(CONFIG_USER_ONLY)
2880 GEN_EXCP_PRIVOPC(ctx);
2881#else
2882 int ra, rd;
b61f2753 2883 TCGv EA;
be147d08
JM		 2884
2885 /* Restore CPU state */
2886 if (unlikely(ctx->supervisor == 0)) {
2887 GEN_EXCP_PRIVOPC(ctx);
2888 return;
2889 }
2890 ra = rA(ctx->opcode);
2891 rd = rD(ctx->opcode);
2892 if (unlikely((rd & 1) || rd == ra)) {
2893 GEN_EXCP_INVAL(ctx);
2894 return;
2895 }
2896 if (unlikely(ctx->mem_idx & 1)) {
2897 /* Little-endian mode is not handled */
2898 GEN_EXCP(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2899 return;
2900 }
a7812ae4 2901 EA = tcg_temp_new();
a7859e89 2902 gen_set_access_type(ACCESS_INT);
b61f2753
AJ		 2903 gen_addr_imm_index(EA, ctx, 0x0F);
2904 gen_qemu_ld64(cpu_gpr[rd], EA, ctx->mem_idx);
2905 tcg_gen_addi_tl(EA, EA, 8);
2906 gen_qemu_ld64(cpu_gpr[rd+1], EA, ctx->mem_idx);
2907 tcg_temp_free(EA);
be147d08
JM		 2908#endif
2909}
d9bce9d9 2910#endif
79aceca5
FB		 2911
2912/*** Integer store ***/
0c8aacd4
AJ		 2913#define GEN_ST(name, stop, opc, type) \
2914GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2915{ \
0c8aacd4 2916 TCGv EA = tcg_temp_new(); \
a7859e89 2917 gen_set_access_type(ACCESS_INT); \
b61f2753 2918 gen_addr_imm_index(EA, ctx, 0); \
0c8aacd4 2919 gen_qemu_##stop(cpu_gpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
b61f2753 2920 tcg_temp_free(EA); \
79aceca5
FB		 2921}
2922
0c8aacd4
AJ		 2923#define GEN_STU(name, stop, opc, type) \
2924GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2925{ \
b61f2753 2926 TCGv EA; \
76a66253 2927 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 2928 GEN_EXCP_INVAL(ctx); \
9fddaa0c 2929 return; \
9a64fbe4 2930 } \
0c8aacd4 2931 EA = tcg_temp_new(); \
a7859e89 2932 gen_set_access_type(ACCESS_INT); \
9d53c753 2933 if (type == PPC_64B) \
b61f2753 2934 gen_addr_imm_index(EA, ctx, 0x03); \
9d53c753 2935 else \
b61f2753 2936 gen_addr_imm_index(EA, ctx, 0); \
0c8aacd4 2937 gen_qemu_##stop(cpu_gpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
b61f2753
AJ		 2938 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2939 tcg_temp_free(EA); \
79aceca5
FB		 2940}
2941
0c8aacd4
AJ		 2942#define GEN_STUX(name, stop, opc2, opc3, type) \
2943GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2944{ \
b61f2753 2945 TCGv EA; \
76a66253 2946 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 2947 GEN_EXCP_INVAL(ctx); \
9fddaa0c 2948 return; \
9a64fbe4 2949 } \
0c8aacd4 2950 EA = tcg_temp_new(); \
a7859e89 2951 gen_set_access_type(ACCESS_INT); \
b61f2753 2952 gen_addr_reg_index(EA, ctx); \
0c8aacd4 2953 gen_qemu_##stop(cpu_gpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
b61f2753
AJ		 2954 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2955 tcg_temp_free(EA); \
79aceca5
FB		 2956}
2957
0c8aacd4
AJ		 2958#define GEN_STX(name, stop, opc2, opc3, type) \
2959GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2960{ \
0c8aacd4 2961 TCGv EA = tcg_temp_new(); \
a7859e89 2962 gen_set_access_type(ACCESS_INT); \
b61f2753 2963 gen_addr_reg_index(EA, ctx); \
0c8aacd4 2964 gen_qemu_##stop(cpu_gpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
b61f2753 2965 tcg_temp_free(EA); \
79aceca5
FB		 2966}
2967
0c8aacd4
AJ		 2968#define GEN_STS(name, stop, op, type) \
2969GEN_ST(name, stop, op | 0x20, type); \
2970GEN_STU(name, stop, op | 0x21, type); \
2971GEN_STUX(name, stop, 0x17, op | 0x01, type); \
2972GEN_STX(name, stop, 0x17, op | 0x00, type)
79aceca5
FB		 2973
2974/* stb stbu stbux stbx */
0c8aacd4 2975GEN_STS(stb, st8, 0x06, PPC_INTEGER);
79aceca5 2976/* sth sthu sthux sthx */
0c8aacd4 2977GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
79aceca5 2978/* stw stwu stwux stwx */
0c8aacd4 2979GEN_STS(stw, st32, 0x04, PPC_INTEGER);
d9bce9d9 2980#if defined(TARGET_PPC64)
0c8aacd4
AJ		 2981GEN_STUX(std, st64, 0x15, 0x05, PPC_64B);
2982GEN_STX(std, st64, 0x15, 0x04, PPC_64B);
be147d08 2983GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B)
d9bce9d9 2984{
be147d08 2985 int rs;
b61f2753 2986 TCGv EA;
be147d08
JM		 2987
2988 rs = rS(ctx->opcode);
2989 if ((ctx->opcode & 0x3) == 0x2) {
2990#if defined(CONFIG_USER_ONLY)
2991 GEN_EXCP_PRIVOPC(ctx);
2992#else
2993 /* stq */
2994 if (unlikely(ctx->supervisor == 0)) {
2995 GEN_EXCP_PRIVOPC(ctx);
2996 return;
2997 }
2998 if (unlikely(rs & 1)) {
e1833e1f 2999 GEN_EXCP_INVAL(ctx);
d9bce9d9
JM		 3000 return;
3001 }
be147d08
JM		 3002 if (unlikely(ctx->mem_idx & 1)) {
3003 /* Little-endian mode is not handled */
3004 GEN_EXCP(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
3005 return;
3006 }
a7812ae4 3007 EA = tcg_temp_new();
a7859e89 3008 gen_set_access_type(ACCESS_INT);
b61f2753
AJ		 3009 gen_addr_imm_index(EA, ctx, 0x03);
3010 gen_qemu_st64(cpu_gpr[rs], EA, ctx->mem_idx);
3011 tcg_gen_addi_tl(EA, EA, 8);
3012 gen_qemu_st64(cpu_gpr[rs+1], EA, ctx->mem_idx);
3013 tcg_temp_free(EA);
be147d08
JM		 3014#endif
3015 } else {
3016 /* std / stdu */
3017 if (Rc(ctx->opcode)) {
3018 if (unlikely(rA(ctx->opcode) == 0)) {
3019 GEN_EXCP_INVAL(ctx);
3020 return;
3021 }
3022 }
a7812ae4 3023 EA = tcg_temp_new();
a7859e89 3024 gen_set_access_type(ACCESS_INT);
b61f2753
AJ		 3025 gen_addr_imm_index(EA, ctx, 0x03);
3026 gen_qemu_st64(cpu_gpr[rs], EA, ctx->mem_idx);
be147d08 3027 if (Rc(ctx->opcode))
b61f2753
AJ		 3028 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
3029 tcg_temp_free(EA);
d9bce9d9 3030 }
d9bce9d9
JM		 3031}
3032#endif
79aceca5
FB		 3033/*** Integer load and store with byte reverse ***/
3034/* lhbrx */
b61f2753
AJ		 3035void always_inline gen_qemu_ld16ur(TCGv t0, TCGv t1, int flags)
3036{
a7812ae4
PB		 3037 TCGv_i32 temp = tcg_temp_new_i32();
3038 gen_qemu_ld16u(t0, t1, flags);
3039 tcg_gen_trunc_tl_i32(temp, t0);
b61f2753
AJ		 3040 tcg_gen_bswap16_i32(temp, temp);
3041 tcg_gen_extu_i32_tl(t0, temp);
a7812ae4 3042 tcg_temp_free_i32(temp);
b61f2753 3043}
0c8aacd4 3044GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
b61f2753 3045
79aceca5 3046/* lwbrx */
b61f2753
AJ		 3047void always_inline gen_qemu_ld32ur(TCGv t0, TCGv t1, int flags)
3048{
a7812ae4
PB		 3049 TCGv_i32 temp = tcg_temp_new_i32();
3050 gen_qemu_ld32u(t0, t1, flags);
3051 tcg_gen_trunc_tl_i32(temp, t0);
b61f2753
AJ		 3052 tcg_gen_bswap_i32(temp, temp);
3053 tcg_gen_extu_i32_tl(t0, temp);
a7812ae4 3054 tcg_temp_free_i32(temp);
b61f2753 3055}
0c8aacd4 3056GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
b61f2753 3057
79aceca5 3058/* sthbrx */
b61f2753
AJ		 3059void always_inline gen_qemu_st16r(TCGv t0, TCGv t1, int flags)
3060{
a7812ae4
PB		 3061 TCGv_i32 temp = tcg_temp_new_i32();
3062 TCGv t2 = tcg_temp_new();
b61f2753
AJ		 3063 tcg_gen_trunc_tl_i32(temp, t0);
3064 tcg_gen_ext16u_i32(temp, temp);
3065 tcg_gen_bswap16_i32(temp, temp);
a7812ae4
PB		 3066 tcg_gen_extu_i32_tl(t2, temp);
3067 tcg_temp_free_i32(temp);
3068 gen_qemu_st16(t2, t1, flags);
3069 tcg_temp_free(t2);
b61f2753 3070}
0c8aacd4 3071GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
b61f2753 3072
79aceca5 3073/* stwbrx */
b61f2753
AJ		 3074void always_inline gen_qemu_st32r(TCGv t0, TCGv t1, int flags)
3075{
a7812ae4
PB		 3076 TCGv_i32 temp = tcg_temp_new_i32();
3077 TCGv t2 = tcg_temp_new();
b61f2753
AJ		 3078 tcg_gen_trunc_tl_i32(temp, t0);
3079 tcg_gen_bswap_i32(temp, temp);
a7812ae4
PB		 3080 tcg_gen_extu_i32_tl(t2, temp);
3081 tcg_temp_free_i32(temp);
87006d13 3082 gen_qemu_st32(t2, t1, flags);
a7812ae4 3083 tcg_temp_free(t2);
b61f2753 3084}
0c8aacd4 3085GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
79aceca5
FB		 3086
3087/*** Integer load and store multiple ***/
3088/* lmw */
3089GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
3090{
ff4a62cd
AJ		 3091 TCGv t0 = tcg_temp_new();
3092 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
76a66253 3093 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3094 gen_update_nip(ctx, ctx->nip - 4);
ff4a62cd
AJ		 3095 gen_addr_imm_index(t0, ctx, 0);
3096 gen_helper_lmw(t0, t1);
3097 tcg_temp_free(t0);
3098 tcg_temp_free_i32(t1);
79aceca5
FB		 3099}
3100
3101/* stmw */
3102GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
3103{
ff4a62cd
AJ		 3104 TCGv t0 = tcg_temp_new();
3105 TCGv_i32 t1 = tcg_const_i32(rS(ctx->opcode));
76a66253 3106 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3107 gen_update_nip(ctx, ctx->nip - 4);
ff4a62cd
AJ		 3108 gen_addr_imm_index(t0, ctx, 0);
3109 gen_helper_stmw(t0, t1);
3110 tcg_temp_free(t0);
3111 tcg_temp_free_i32(t1);
79aceca5
FB		 3112}
3113
3114/*** Integer load and store strings ***/
3115/* lswi */
3fc6c082 3116/* PowerPC32 specification says we must generate an exception if
9a64fbe4
FB		 3117 * rA is in the range of registers to be loaded.
3118 * In an other hand, IBM says this is valid, but rA won't be loaded.
3119 * For now, I'll follow the spec...
3120 */
05332d70 3121GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING)
79aceca5 3122{
dfbc799d
AJ		 3123 TCGv t0;
3124 TCGv_i32 t1, t2;
79aceca5
FB		 3125 int nb = NB(ctx->opcode);
3126 int start = rD(ctx->opcode);
9a64fbe4 3127 int ra = rA(ctx->opcode);
79aceca5
FB		 3128 int nr;
3129
3130 if (nb == 0)
3131 nb = 32;
3132 nr = nb / 4;
76a66253
JM		 3133 if (unlikely(((start + nr) > 32 &&
3134 start <= ra && (start + nr - 32) > ra) ||
3135 ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
e1833e1f
JM		 3136 GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,
3137 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_LSWX);
9fddaa0c 3138 return;
297d8e62 3139 }
8dd4983c 3140 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3141 gen_update_nip(ctx, ctx->nip - 4);
dfbc799d
AJ		 3142 t0 = tcg_temp_new();
3143 gen_addr_register(t0, ctx);
3144 t1 = tcg_const_i32(nb);
3145 t2 = tcg_const_i32(start);
3146 gen_helper_lsw(t0, t1, t2);
3147 tcg_temp_free(t0);
3148 tcg_temp_free_i32(t1);
3149 tcg_temp_free_i32(t2);
79aceca5
FB		 3150}
3151
3152/* lswx */
05332d70 3153GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING)
79aceca5 3154{
dfbc799d
AJ		 3155 TCGv t0 = tcg_temp_new();
3156 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
3157 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
3158 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
76a66253 3159 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3160 gen_update_nip(ctx, ctx->nip - 4);
dfbc799d
AJ		 3161 gen_addr_reg_index(t0, ctx);
3162 gen_helper_lswx(t0, t1, t2, t3);
3163 tcg_temp_free(t0);
3164 tcg_temp_free_i32(t1);
3165 tcg_temp_free_i32(t2);
3166 tcg_temp_free_i32(t3);
79aceca5
FB		 3167}
3168
3169/* stswi */
05332d70 3170GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING)
79aceca5 3171{
4b3686fa 3172 int nb = NB(ctx->opcode);
dfbc799d
AJ		 3173 TCGv t0 = tcg_temp_new();
3174 TCGv_i32 t1;
3175 TCGv_i32 t2 = tcg_const_i32(rS(ctx->opcode));
76a66253 3176 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3177 gen_update_nip(ctx, ctx->nip - 4);
dfbc799d 3178 gen_addr_register(t0, ctx);
4b3686fa
FB		 3179 if (nb == 0)
3180 nb = 32;
dfbc799d
AJ		 3181 t1 = tcg_const_i32(nb);
3182 gen_helper_stsw(t0, t1, t2);
3183 tcg_temp_free(t0);
3184 tcg_temp_free_i32(t1);
3185 tcg_temp_free_i32(t2);
79aceca5
FB		 3186}
3187
3188/* stswx */
05332d70 3189GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING)
79aceca5 3190{
dfbc799d
AJ		 3191 TCGv t0 = tcg_temp_new();
3192 TCGv_i32 t1 = tcg_temp_new_i32();
3193 TCGv_i32 t2 = tcg_const_i32(rS(ctx->opcode));
8dd4983c 3194 /* NIP cannot be restored if the memory exception comes from an helper */
5fafdf24 3195 gen_update_nip(ctx, ctx->nip - 4);
dfbc799d
AJ		 3196 gen_addr_reg_index(t0, ctx);
3197 tcg_gen_trunc_tl_i32(t1, cpu_xer);
3198 tcg_gen_andi_i32(t1, t1, 0x7F);
3199 gen_helper_stsw(t0, t1, t2);
3200 tcg_temp_free(t0);
3201 tcg_temp_free_i32(t1);
3202 tcg_temp_free_i32(t2);
79aceca5
FB		 3203}
3204
3205/*** Memory synchronisation ***/
3206/* eieio */
0db1b20e 3207GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO)
79aceca5 3208{
79aceca5
FB		 3209}
3210
3211/* isync */
0db1b20e 3212GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM)
79aceca5 3213{
e1833e1f 3214 GEN_STOP(ctx);
79aceca5
FB		 3215}
3216
111bfab3 3217/* lwarx */
76a66253 3218GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000001, PPC_RES)
79aceca5 3219{
cf360a32 3220 TCGv t0 = tcg_temp_local_new();
a7859e89 3221 gen_set_access_type(ACCESS_RES);
cf360a32
AJ		 3222 gen_addr_reg_index(t0, ctx);
3223 gen_check_align(ctx, t0, 0x03);
3224#if defined(TARGET_PPC64)
3225 if (!ctx->sf_mode)
3226 tcg_gen_ext32u_tl(t0, t0);
3227#endif
3228 gen_qemu_ld32u(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx);
3229 tcg_gen_mov_tl(cpu_reserve, t0);
3230 tcg_temp_free(t0);
79aceca5
FB		 3231}
3232
3233/* stwcx. */
c7697e1f 3234GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES)
79aceca5 3235{
cf360a32
AJ		 3236 int l1 = gen_new_label();
3237 TCGv t0 = tcg_temp_local_new();
a7859e89 3238 gen_set_access_type(ACCESS_RES);
cf360a32
AJ		 3239 gen_addr_reg_index(t0, ctx);
3240 gen_check_align(ctx, t0, 0x03);
3241#if defined(TARGET_PPC64)
3242 if (!ctx->sf_mode)
3243 tcg_gen_ext32u_tl(t0, t0);
3244#endif
3245 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
3246 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
3247 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
3248 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3249 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3250 gen_qemu_st32(cpu_gpr[rS(ctx->opcode)], t0, ctx->mem_idx);
3251 gen_set_label(l1);
3252 tcg_gen_movi_tl(cpu_reserve, -1);
3253 tcg_temp_free(t0);
79aceca5
FB		 3254}
3255
426613db 3256#if defined(TARGET_PPC64)
426613db 3257/* ldarx */
a750fc0b 3258GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000001, PPC_64B)
426613db 3259{
cf360a32 3260 TCGv t0 = tcg_temp_local_new();
a7859e89 3261 gen_set_access_type(ACCESS_RES);
cf360a32
AJ		 3262 gen_addr_reg_index(t0, ctx);
3263 gen_check_align(ctx, t0, 0x07);
3264 if (!ctx->sf_mode)
3265 tcg_gen_ext32u_tl(t0, t0);
3266 gen_qemu_ld64(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx);
3267 tcg_gen_mov_tl(cpu_reserve, t0);
3268 tcg_temp_free(t0);
426613db
JM		 3269}
3270
3271/* stdcx. */
c7697e1f 3272GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B)
426613db 3273{
cf360a32
AJ		 3274 int l1 = gen_new_label();
3275 TCGv t0 = tcg_temp_local_new();
a7859e89 3276 gen_set_access_type(ACCESS_RES);
cf360a32
AJ		 3277 gen_addr_reg_index(t0, ctx);
3278 gen_check_align(ctx, t0, 0x07);
3279 if (!ctx->sf_mode)
3280 tcg_gen_ext32u_tl(t0, t0);
3281 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
3282 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
3283 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
3284 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3285 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3286 gen_qemu_st64(cpu_gpr[rS(ctx->opcode)], t0, ctx->mem_idx);
3287 gen_set_label(l1);
3288 tcg_gen_movi_tl(cpu_reserve, -1);
3289 tcg_temp_free(t0);
426613db
JM		 3290}
3291#endif /* defined(TARGET_PPC64) */
3292
79aceca5 3293/* sync */
a902d886 3294GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC)
79aceca5 3295{
79aceca5
FB		 3296}
3297
0db1b20e
JM		 3298/* wait */
3299GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT)
3300{
931ff272
AJ		 3301 TCGv_i32 t0 = tcg_temp_new_i32();
3302 tcg_gen_st_i32(t0, cpu_env, offsetof(CPUState, halted));
3303 tcg_temp_free_i32(t0);
0db1b20e 3304 /* Stop translation, as the CPU is supposed to sleep from now */
be147d08 3305 GEN_EXCP(ctx, EXCP_HLT, 1);
0db1b20e
JM		 3306}
3307
79aceca5 3308/*** Floating-point load ***/
a0d7d5a7
AJ		 3309#define GEN_LDF(name, ldop, opc, type) \
3310GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 3311{ \
a0d7d5a7 3312 TCGv EA; \
76a66253 3313 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 3314 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 3315 return; \
3316 } \
a7859e89 3317 gen_set_access_type(ACCESS_FLOAT); \
a0d7d5a7
AJ		 3318 EA = tcg_temp_new(); \
3319 gen_addr_imm_index(EA, ctx, 0); \
3320 gen_qemu_##ldop(cpu_fpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
3321 tcg_temp_free(EA); \
79aceca5
FB		 3322}
3323
a0d7d5a7
AJ		 3324#define GEN_LDUF(name, ldop, opc, type) \
3325GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 3326{ \
a0d7d5a7 3327 TCGv EA; \
76a66253 3328 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 3329 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 3330 return; \
3331 } \
76a66253 3332 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 3333 GEN_EXCP_INVAL(ctx); \
9fddaa0c 3334 return; \
9a64fbe4 3335 } \
a7859e89 3336 gen_set_access_type(ACCESS_FLOAT); \
a0d7d5a7
AJ		 3337 EA = tcg_temp_new(); \
3338 gen_addr_imm_index(EA, ctx, 0); \
3339 gen_qemu_##ldop(cpu_fpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
3340 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3341 tcg_temp_free(EA); \
79aceca5
FB		 3342}
3343
a0d7d5a7
AJ		 3344#define GEN_LDUXF(name, ldop, opc, type) \
3345GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type) \
79aceca5 3346{ \
a0d7d5a7 3347 TCGv EA; \
76a66253 3348 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 3349 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 3350 return; \
3351 } \
76a66253 3352 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 3353 GEN_EXCP_INVAL(ctx); \
9fddaa0c 3354 return; \
9a64fbe4 3355 } \
a7859e89 3356 gen_set_access_type(ACCESS_FLOAT); \
a0d7d5a7
AJ		 3357 EA = tcg_temp_new(); \
3358 gen_addr_reg_index(EA, ctx); \
3359 gen_qemu_##ldop(cpu_fpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
3360 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3361 tcg_temp_free(EA); \
79aceca5
FB		 3362}
3363
a0d7d5a7
AJ		 3364#define GEN_LDXF(name, ldop, opc2, opc3, type) \
3365GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 3366{ \
a0d7d5a7 3367 TCGv EA; \
76a66253 3368 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 3369 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 3370 return; \
3371 } \
a7859e89 3372 gen_set_access_type(ACCESS_FLOAT); \
a0d7d5a7
AJ		 3373 EA = tcg_temp_new(); \
3374 gen_addr_reg_index(EA, ctx); \
3375 gen_qemu_##ldop(cpu_fpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
3376 tcg_temp_free(EA); \
79aceca5
FB		 3377}
3378
a0d7d5a7
AJ		 3379#define GEN_LDFS(name, ldop, op, type) \
3380GEN_LDF(name, ldop, op | 0x20, type); \
3381GEN_LDUF(name, ldop, op | 0x21, type); \
3382GEN_LDUXF(name, ldop, op | 0x01, type); \
3383GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
3384
3385static always_inline void gen_qemu_ld32fs(TCGv_i64 arg1, TCGv arg2, int flags)
3386{
3387 TCGv t0 = tcg_temp_new();
3388 TCGv_i32 t1 = tcg_temp_new_i32();
3389 gen_qemu_ld32u(t0, arg2, flags);
3390 tcg_gen_trunc_tl_i32(t1, t0);
3391 tcg_temp_free(t0);
3392 gen_helper_float32_to_float64(arg1, t1);
3393 tcg_temp_free_i32(t1);
3394}
79aceca5 3395
a0d7d5a7
AJ		 3396 /* lfd lfdu lfdux lfdx */
3397GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT);
3398 /* lfs lfsu lfsux lfsx */
3399GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
79aceca5
FB		 3400
3401/*** Floating-point store ***/
a0d7d5a7
AJ		 3402#define GEN_STF(name, stop, opc, type) \
3403GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 3404{ \
a0d7d5a7 3405 TCGv EA; \
76a66253 3406 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 3407 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 3408 return; \
3409 } \
a7859e89 3410 gen_set_access_type(ACCESS_FLOAT); \
a0d7d5a7
AJ		 3411 EA = tcg_temp_new(); \
3412 gen_addr_imm_index(EA, ctx, 0); \
3413 gen_qemu_##stop(cpu_fpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
3414 tcg_temp_free(EA); \
79aceca5
FB		 3415}
3416
a0d7d5a7
AJ		 3417#define GEN_STUF(name, stop, opc, type) \
3418GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 3419{ \
a0d7d5a7 3420 TCGv EA; \
76a66253 3421 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 3422 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 3423 return; \
3424 } \
76a66253 3425 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 3426 GEN_EXCP_INVAL(ctx); \
9fddaa0c 3427 return; \
9a64fbe4 3428 } \
a7859e89 3429 gen_set_access_type(ACCESS_FLOAT); \
a0d7d5a7
AJ		 3430 EA = tcg_temp_new(); \
3431 gen_addr_imm_index(EA, ctx, 0); \
3432 gen_qemu_##stop(cpu_fpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
3433 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3434 tcg_temp_free(EA); \
79aceca5
FB		 3435}
3436
a0d7d5a7
AJ		 3437#define GEN_STUXF(name, stop, opc, type) \
3438GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type) \
79aceca5 3439{ \
a0d7d5a7 3440 TCGv EA; \
76a66253 3441 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 3442 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 3443 return; \
3444 } \
76a66253 3445 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 3446 GEN_EXCP_INVAL(ctx); \
9fddaa0c 3447 return; \
9a64fbe4 3448 } \
a7859e89 3449 gen_set_access_type(ACCESS_FLOAT); \
a0d7d5a7
AJ		 3450 EA = tcg_temp_new(); \
3451 gen_addr_reg_index(EA, ctx); \
3452 gen_qemu_##stop(cpu_fpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
3453 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3454 tcg_temp_free(EA); \
79aceca5
FB		 3455}
3456
a0d7d5a7
AJ		 3457#define GEN_STXF(name, stop, opc2, opc3, type) \
3458GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 3459{ \
a0d7d5a7 3460 TCGv EA; \
76a66253 3461 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 3462 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 3463 return; \
3464 } \
a7859e89 3465 gen_set_access_type(ACCESS_FLOAT); \
a0d7d5a7
AJ		 3466 EA = tcg_temp_new(); \
3467 gen_addr_reg_index(EA, ctx); \
3468 gen_qemu_##stop(cpu_fpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
3469 tcg_temp_free(EA); \
79aceca5
FB		 3470}
3471
a0d7d5a7
AJ		 3472#define GEN_STFS(name, stop, op, type) \
3473GEN_STF(name, stop, op | 0x20, type); \
3474GEN_STUF(name, stop, op | 0x21, type); \
3475GEN_STUXF(name, stop, op | 0x01, type); \
3476GEN_STXF(name, stop, 0x17, op | 0x00, type)
3477
3478static always_inline void gen_qemu_st32fs(TCGv_i64 arg1, TCGv arg2, int flags)
3479{
3480 TCGv_i32 t0 = tcg_temp_new_i32();
3481 TCGv t1 = tcg_temp_new();
3482 gen_helper_float64_to_float32(t0, arg1);
3483 tcg_gen_extu_i32_tl(t1, t0);
3484 tcg_temp_free_i32(t0);
3485 gen_qemu_st32(t1, arg2, flags);
3486 tcg_temp_free(t1);
3487}
79aceca5
FB		 3488
3489/* stfd stfdu stfdux stfdx */
a0d7d5a7 3490GEN_STFS(stfd, st64, 0x16, PPC_FLOAT);
79aceca5 3491/* stfs stfsu stfsux stfsx */
a0d7d5a7 3492GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
79aceca5
FB		 3493
3494/* Optional: */
a0d7d5a7
AJ		 3495static always_inline void gen_qemu_st32fiw(TCGv_i64 arg1, TCGv arg2, int flags)
3496{
3497 TCGv t0 = tcg_temp_new();
3498 tcg_gen_trunc_i64_tl(t0, arg1),
3499 gen_qemu_st32(t0, arg2, flags);
3500 tcg_temp_free(t0);
3501}
79aceca5 3502/* stfiwx */
a0d7d5a7 3503GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
79aceca5
FB		 3504
3505/*** Branch ***/
b068d6a7
JM		 3506static always_inline void gen_goto_tb (DisasContext *ctx, int n,
3507 target_ulong dest)
c1942362
FB		 3508{
3509 TranslationBlock *tb;
3510 tb = ctx->tb;
a2ffb812
AJ		 3511#if defined(TARGET_PPC64)
3512 if (!ctx->sf_mode)
3513 dest = (uint32_t) dest;
3514#endif
57fec1fe 3515 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
8cbcb4fa 3516 likely(!ctx->singlestep_enabled)) {
57fec1fe 3517 tcg_gen_goto_tb(n);
a2ffb812 3518 tcg_gen_movi_tl(cpu_nip, dest & ~3);
57fec1fe 3519 tcg_gen_exit_tb((long)tb + n);
c1942362 3520 } else {
a2ffb812 3521 tcg_gen_movi_tl(cpu_nip, dest & ~3);
8cbcb4fa
AJ		 3522 if (unlikely(ctx->singlestep_enabled)) {
3523 if ((ctx->singlestep_enabled &
bdc4e053 3524 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
8cbcb4fa
AJ		 3525 ctx->exception == POWERPC_EXCP_BRANCH) {
3526 target_ulong tmp = ctx->nip;
3527 ctx->nip = dest;
3528 GEN_EXCP(ctx, POWERPC_EXCP_TRACE, 0);
3529 ctx->nip = tmp;
3530 }
3531 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
3532 gen_update_nip(ctx, dest);
64adab3f 3533 gen_helper_raise_debug();
8cbcb4fa
AJ		 3534 }
3535 }
57fec1fe 3536 tcg_gen_exit_tb(0);
c1942362 3537 }
c53be334
FB		 3538}
3539
b068d6a7 3540static always_inline void gen_setlr (DisasContext *ctx, target_ulong nip)
e1833e1f
JM		 3541{
3542#if defined(TARGET_PPC64)
a2ffb812
AJ		 3543 if (ctx->sf_mode == 0)
3544 tcg_gen_movi_tl(cpu_lr, (uint32_t)nip);
e1833e1f
JM		 3545 else
3546#endif
a2ffb812 3547 tcg_gen_movi_tl(cpu_lr, nip);
e1833e1f
JM		 3548}
3549
79aceca5
FB		 3550/* b ba bl bla */
3551GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3552{
76a66253 3553 target_ulong li, target;
38a64f9d 3554
8cbcb4fa 3555 ctx->exception = POWERPC_EXCP_BRANCH;
38a64f9d 3556 /* sign extend LI */
76a66253 3557#if defined(TARGET_PPC64)
d9bce9d9
JM		 3558 if (ctx->sf_mode)
3559 li = ((int64_t)LI(ctx->opcode) << 38) >> 38;
3560 else
76a66253 3561#endif
d9bce9d9 3562 li = ((int32_t)LI(ctx->opcode) << 6) >> 6;
76a66253 3563 if (likely(AA(ctx->opcode) == 0))
046d6672 3564 target = ctx->nip + li - 4;
79aceca5 3565 else
9a64fbe4 3566 target = li;
e1833e1f
JM		 3567 if (LK(ctx->opcode))
3568 gen_setlr(ctx, ctx->nip);
c1942362 3569 gen_goto_tb(ctx, 0, target);
79aceca5
FB		 3570}
3571
e98a6e40
FB		 3572#define BCOND_IM 0
3573#define BCOND_LR 1
3574#define BCOND_CTR 2
3575
b068d6a7 3576static always_inline void gen_bcond (DisasContext *ctx, int type)
d9bce9d9 3577{
d9bce9d9 3578 uint32_t bo = BO(ctx->opcode);
a2ffb812
AJ		 3579 int l1 = gen_new_label();
3580 TCGv target;
e98a6e40 3581
8cbcb4fa 3582 ctx->exception = POWERPC_EXCP_BRANCH;
a2ffb812 3583 if (type == BCOND_LR || type == BCOND_CTR) {
a7812ae4 3584 target = tcg_temp_local_new();
a2ffb812
AJ		 3585 if (type == BCOND_CTR)
3586 tcg_gen_mov_tl(target, cpu_ctr);
3587 else
3588 tcg_gen_mov_tl(target, cpu_lr);
e98a6e40 3589 }
e1833e1f
JM		 3590 if (LK(ctx->opcode))
3591 gen_setlr(ctx, ctx->nip);
a2ffb812
AJ		 3592 l1 = gen_new_label();
3593 if ((bo & 0x4) == 0) {
3594 /* Decrement and test CTR */
a7812ae4 3595 TCGv temp = tcg_temp_new();
a2ffb812
AJ		 3596 if (unlikely(type == BCOND_CTR)) {
3597 GEN_EXCP_INVAL(ctx);
3598 return;
3599 }
3600 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
d9bce9d9 3601#if defined(TARGET_PPC64)
a2ffb812
AJ		 3602 if (!ctx->sf_mode)
3603 tcg_gen_ext32u_tl(temp, cpu_ctr);
3604 else
d9bce9d9 3605#endif
a2ffb812
AJ		 3606 tcg_gen_mov_tl(temp, cpu_ctr);
3607 if (bo & 0x2) {
3608 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3609 } else {
3610 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
e98a6e40 3611 }
a7812ae4 3612 tcg_temp_free(temp);
a2ffb812
AJ		 3613 }
3614 if ((bo & 0x10) == 0) {
3615 /* Test CR */
3616 uint32_t bi = BI(ctx->opcode);
3617 uint32_t mask = 1 << (3 - (bi & 0x03));
a7812ae4 3618 TCGv_i32 temp = tcg_temp_new_i32();
a2ffb812 3619
d9bce9d9 3620 if (bo & 0x8) {
a2ffb812
AJ		 3621 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3622 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
d9bce9d9 3623 } else {
a2ffb812
AJ		 3624 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3625 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
d9bce9d9 3626 }
a7812ae4 3627 tcg_temp_free_i32(temp);
d9bce9d9 3628 }
e98a6e40 3629 if (type == BCOND_IM) {
a2ffb812
AJ		 3630 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3631 if (likely(AA(ctx->opcode) == 0)) {
3632 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3633 } else {
3634 gen_goto_tb(ctx, 0, li);
3635 }
c53be334 3636 gen_set_label(l1);
c1942362 3637 gen_goto_tb(ctx, 1, ctx->nip);
e98a6e40 3638 } else {
d9bce9d9 3639#if defined(TARGET_PPC64)
a2ffb812
AJ		 3640 if (!(ctx->sf_mode))
3641 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3642 else
3643#endif
3644 tcg_gen_andi_tl(cpu_nip, target, ~3);
3645 tcg_gen_exit_tb(0);
3646 gen_set_label(l1);
3647#if defined(TARGET_PPC64)
3648 if (!(ctx->sf_mode))
3649 tcg_gen_movi_tl(cpu_nip, (uint32_t)ctx->nip);
d9bce9d9
JM		 3650 else
3651#endif
a2ffb812 3652 tcg_gen_movi_tl(cpu_nip, ctx->nip);
57fec1fe 3653 tcg_gen_exit_tb(0);
08e46e54 3654 }
e98a6e40
FB		 3655}
3656
3657GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3b46e624 3658{
e98a6e40
FB		 3659 gen_bcond(ctx, BCOND_IM);
3660}
3661
3662GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW)
3b46e624 3663{
e98a6e40
FB		 3664 gen_bcond(ctx, BCOND_CTR);
3665}
3666
3667GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW)
3b46e624 3668{
e98a6e40
FB		 3669 gen_bcond(ctx, BCOND_LR);
3670}
79aceca5
FB		 3671
3672/*** Condition register logical ***/
e1571908
AJ		 3673#define GEN_CRLOGIC(name, tcg_op, opc) \
3674GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) \
79aceca5 3675{ \
fc0d441e
JM		 3676 uint8_t bitmask; \
3677 int sh; \
a7812ae4 3678 TCGv_i32 t0, t1; \
fc0d441e 3679 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
a7812ae4 3680 t0 = tcg_temp_new_i32(); \
fc0d441e 3681 if (sh > 0) \
fea0c503 3682 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
fc0d441e 3683 else if (sh < 0) \
fea0c503 3684 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
e1571908 3685 else \
fea0c503 3686 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
a7812ae4 3687 t1 = tcg_temp_new_i32(); \
fc0d441e
JM		 3688 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3689 if (sh > 0) \
fea0c503 3690 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
fc0d441e 3691 else if (sh < 0) \
fea0c503 3692 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
e1571908 3693 else \
fea0c503
AJ		 3694 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3695 tcg_op(t0, t0, t1); \
fc0d441e 3696 bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \
fea0c503
AJ		 3697 tcg_gen_andi_i32(t0, t0, bitmask); \
3698 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3699 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
a7812ae4
PB		 3700 tcg_temp_free_i32(t0); \
3701 tcg_temp_free_i32(t1); \
79aceca5
FB		 3702}
3703
3704/* crand */
e1571908 3705GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
79aceca5 3706/* crandc */
e1571908 3707GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
79aceca5 3708/* creqv */
e1571908 3709GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
79aceca5 3710/* crnand */
e1571908 3711GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
79aceca5 3712/* crnor */
e1571908 3713GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
79aceca5 3714/* cror */
e1571908 3715GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
79aceca5 3716/* crorc */
e1571908 3717GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
79aceca5 3718/* crxor */
e1571908 3719GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
79aceca5
FB		 3720/* mcrf */
3721GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER)
3722{
47e4661c 3723 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
79aceca5
FB		 3724}
3725
3726/*** System linkage ***/
3727/* rfi (supervisor only) */
76a66253 3728GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW)
79aceca5 3729{
9a64fbe4 3730#if defined(CONFIG_USER_ONLY)
e1833e1f 3731 GEN_EXCP_PRIVOPC(ctx);
9a64fbe4
FB		 3732#else
3733 /* Restore CPU state */
76a66253 3734 if (unlikely(!ctx->supervisor)) {
e1833e1f 3735 GEN_EXCP_PRIVOPC(ctx);
9fddaa0c 3736 return;
9a64fbe4 3737 }
d72a19f7 3738 gen_helper_rfi();
e1833e1f 3739 GEN_SYNC(ctx);
9a64fbe4 3740#endif
79aceca5
FB		 3741}
3742
426613db 3743#if defined(TARGET_PPC64)
a750fc0b 3744GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B)
426613db
JM		 3745{
3746#if defined(CONFIG_USER_ONLY)
e1833e1f 3747 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 3748#else
3749 /* Restore CPU state */
3750 if (unlikely(!ctx->supervisor)) {
e1833e1f 3751 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 3752 return;
3753 }
d72a19f7 3754 gen_helper_rfid();
e1833e1f 3755 GEN_SYNC(ctx);
426613db
JM		 3756#endif
3757}
426613db 3758
5b8105fa 3759GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H)
be147d08
JM		 3760{
3761#if defined(CONFIG_USER_ONLY)
3762 GEN_EXCP_PRIVOPC(ctx);
3763#else
3764 /* Restore CPU state */
3765 if (unlikely(ctx->supervisor <= 1)) {
3766 GEN_EXCP_PRIVOPC(ctx);
3767 return;
3768 }
d72a19f7 3769 gen_helper_hrfid();
be147d08
JM		 3770 GEN_SYNC(ctx);
3771#endif
3772}
3773#endif
3774
79aceca5 3775/* sc */
417bf010
JM		 3776#if defined(CONFIG_USER_ONLY)
3777#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3778#else
3779#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3780#endif
e1833e1f 3781GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW)
79aceca5 3782{
e1833e1f
JM		 3783 uint32_t lev;
3784
3785 lev = (ctx->opcode >> 5) & 0x7F;
417bf010 3786 GEN_EXCP(ctx, POWERPC_SYSCALL, lev);
79aceca5
FB		 3787}
3788
3789/*** Trap ***/
3790/* tw */
76a66253 3791GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW)
79aceca5 3792{
cab3bee2 3793 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
a0ae05aa 3794 /* Update the nip since this might generate a trap exception */
d9bce9d9 3795 gen_update_nip(ctx, ctx->nip);
cab3bee2
AJ		 3796 gen_helper_tw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
3797 tcg_temp_free_i32(t0);
79aceca5
FB		 3798}
3799
3800/* twi */
3801GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3802{
cab3bee2
AJ		 3803 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3804 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
d9bce9d9
JM		 3805 /* Update the nip since this might generate a trap exception */
3806 gen_update_nip(ctx, ctx->nip);
cab3bee2
AJ		 3807 gen_helper_tw(cpu_gpr[rA(ctx->opcode)], t0, t1);
3808 tcg_temp_free(t0);
3809 tcg_temp_free_i32(t1);
79aceca5
FB		 3810}
3811
d9bce9d9
JM		 3812#if defined(TARGET_PPC64)
3813/* td */
3814GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B)
3815{
cab3bee2 3816 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
d9bce9d9
JM		 3817 /* Update the nip since this might generate a trap exception */
3818 gen_update_nip(ctx, ctx->nip);
cab3bee2
AJ		 3819 gen_helper_td(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
3820 tcg_temp_free_i32(t0);
d9bce9d9
JM		 3821}
3822
3823/* tdi */
3824GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B)
3825{
cab3bee2
AJ		 3826 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3827 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
d9bce9d9
JM		 3828 /* Update the nip since this might generate a trap exception */
3829 gen_update_nip(ctx, ctx->nip);
cab3bee2
AJ		 3830 gen_helper_td(cpu_gpr[rA(ctx->opcode)], t0, t1);
3831 tcg_temp_free(t0);
3832 tcg_temp_free_i32(t1);
d9bce9d9
JM		 3833}
3834#endif
3835
79aceca5 3836/*** Processor control ***/
79aceca5
FB		 3837/* mcrxr */
3838GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC)
3839{
3d7b417e
AJ		 3840 tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], cpu_xer);
3841 tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], XER_CA);
269f3e95 3842 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_SO | 1 << XER_OV | 1 << XER_CA));
79aceca5
FB		 3843}
3844
3845/* mfcr */
76a66253 3846GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC)
79aceca5 3847{
76a66253 3848 uint32_t crm, crn;
3b46e624 3849
76a66253
JM		 3850 if (likely(ctx->opcode & 0x00100000)) {
3851 crm = CRM(ctx->opcode);
3852 if (likely((crm ^ (crm - 1)) == 0)) {
3853 crn = ffs(crm);
e1571908 3854 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
76a66253 3855 }
d9bce9d9 3856 } else {
a7812ae4 3857 gen_helper_load_cr(cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 3858 }
79aceca5
FB		 3859}
3860
3861/* mfmsr */
3862GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC)
3863{
9a64fbe4 3864#if defined(CONFIG_USER_ONLY)
e1833e1f 3865 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 3866#else
76a66253 3867 if (unlikely(!ctx->supervisor)) {
e1833e1f 3868 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 3869 return;
9a64fbe4 3870 }
6527f6ea 3871 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
9a64fbe4 3872#endif
79aceca5
FB		 3873}
3874
a11b8151 3875#if 1
6f2d8978 3876#define SPR_NOACCESS ((void *)(-1UL))
3fc6c082
FB		 3877#else
3878static void spr_noaccess (void *opaque, int sprn)
3879{
3880 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
3881 printf("ERROR: try to access SPR %d !\n", sprn);
3882}
3883#define SPR_NOACCESS (&spr_noaccess)
3884#endif
3885
79aceca5 3886/* mfspr */
b068d6a7 3887static always_inline void gen_op_mfspr (DisasContext *ctx)
79aceca5 3888{
3fc6c082 3889 void (*read_cb)(void *opaque, int sprn);
79aceca5
FB		 3890 uint32_t sprn = SPR(ctx->opcode);
3891
3fc6c082 3892#if !defined(CONFIG_USER_ONLY)
be147d08
JM		 3893 if (ctx->supervisor == 2)
3894 read_cb = ctx->spr_cb[sprn].hea_read;
7863667f 3895 else if (ctx->supervisor)
3fc6c082
FB		 3896 read_cb = ctx->spr_cb[sprn].oea_read;
3897 else
9a64fbe4 3898#endif
3fc6c082 3899 read_cb = ctx->spr_cb[sprn].uea_read;
76a66253
JM		 3900 if (likely(read_cb != NULL)) {
3901 if (likely(read_cb != SPR_NOACCESS)) {
3fc6c082 3902 (*read_cb)(ctx, sprn);
f78fb44e 3903 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
3fc6c082
FB		 3904 } else {
3905 /* Privilege exception */
9fceefa7
JM		 3906 /* This is a hack to avoid warnings when running Linux:
3907 * this OS breaks the PowerPC virtualisation model,
3908 * allowing userland application to read the PVR
3909 */
3910 if (sprn != SPR_PVR) {
3911 if (loglevel != 0) {
6b542af7 3912 fprintf(logfile, "Trying to read privileged spr %d %03x at "
077fc206 3913 ADDRX "\n", sprn, sprn, ctx->nip);
9fceefa7 3914 }
077fc206
JM		 3915 printf("Trying to read privileged spr %d %03x at " ADDRX "\n",
3916 sprn, sprn, ctx->nip);
f24e5695 3917 }
e1833e1f 3918 GEN_EXCP_PRIVREG(ctx);
79aceca5 3919 }
3fc6c082
FB		 3920 } else {
3921 /* Not defined */
4a057712 3922 if (loglevel != 0) {
077fc206
JM		 3923 fprintf(logfile, "Trying to read invalid spr %d %03x at "
3924 ADDRX "\n", sprn, sprn, ctx->nip);
f24e5695 3925 }
077fc206
JM		 3926 printf("Trying to read invalid spr %d %03x at " ADDRX "\n",
3927 sprn, sprn, ctx->nip);
e1833e1f
JM		 3928 GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,
3929 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_SPR);
79aceca5 3930 }
79aceca5
FB		 3931}
3932
3fc6c082 3933GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC)
79aceca5 3934{
3fc6c082 3935 gen_op_mfspr(ctx);
76a66253 3936}
3fc6c082
FB		 3937
3938/* mftb */
a750fc0b 3939GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB)
3fc6c082
FB		 3940{
3941 gen_op_mfspr(ctx);
79aceca5
FB		 3942}
3943
3944/* mtcrf */
8dd4983c 3945GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC)
79aceca5 3946{
76a66253 3947 uint32_t crm, crn;
3b46e624 3948
76a66253
JM		 3949 crm = CRM(ctx->opcode);
3950 if (likely((ctx->opcode & 0x00100000) || (crm ^ (crm - 1)) == 0)) {
a7812ae4 3951 TCGv_i32 temp = tcg_temp_new_i32();
76a66253 3952 crn = ffs(crm);
a7812ae4
PB		 3953 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
3954 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
e1571908 3955 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
a7812ae4 3956 tcg_temp_free_i32(temp);
76a66253 3957 } else {
a7812ae4
PB		 3958 TCGv_i32 temp = tcg_const_i32(crm);
3959 gen_helper_store_cr(cpu_gpr[rS(ctx->opcode)], temp);
3960 tcg_temp_free_i32(temp);
76a66253 3961 }
79aceca5
FB		 3962}
3963
3964/* mtmsr */
426613db 3965#if defined(TARGET_PPC64)
be147d08 3966GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B)
426613db
JM		 3967{
3968#if defined(CONFIG_USER_ONLY)
e1833e1f 3969 GEN_EXCP_PRIVREG(ctx);
426613db
JM		 3970#else
3971 if (unlikely(!ctx->supervisor)) {
e1833e1f 3972 GEN_EXCP_PRIVREG(ctx);
426613db
JM		 3973 return;
3974 }
f78fb44e 3975 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
be147d08
JM		 3976 if (ctx->opcode & 0x00010000) {
3977 /* Special form that does not need any synchronisation */
6527f6ea
AJ		 3978 TCGv t0 = tcg_temp_new();
3979 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
3980 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
3981 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
3982 tcg_temp_free(t0);
be147d08 3983 } else {
056b05f8
JM		 3984 /* XXX: we need to update nip before the store
3985 * if we enter power saving mode, we will exit the loop
3986 * directly from ppc_store_msr
3987 */
be147d08 3988 gen_update_nip(ctx, ctx->nip);
6527f6ea 3989 gen_helper_store_msr(cpu_gpr[rS(ctx->opcode)]);
be147d08
JM		 3990 /* Must stop the translation as machine state (may have) changed */
3991 /* Note that mtmsr is not always defined as context-synchronizing */
056b05f8 3992 ctx->exception = POWERPC_EXCP_STOP;
be147d08 3993 }
426613db
JM		 3994#endif
3995}
3996#endif
3997
79aceca5
FB		 3998GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC)
3999{
9a64fbe4 4000#if defined(CONFIG_USER_ONLY)
e1833e1f 4001 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 4002#else
76a66253 4003 if (unlikely(!ctx->supervisor)) {
e1833e1f 4004 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 4005 return;
9a64fbe4 4006 }
f78fb44e 4007 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
be147d08
JM		 4008 if (ctx->opcode & 0x00010000) {
4009 /* Special form that does not need any synchronisation */
6527f6ea
AJ		 4010 TCGv t0 = tcg_temp_new();
4011 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
4012 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
4013 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4014 tcg_temp_free(t0);
be147d08 4015 } else {
056b05f8
JM		 4016 /* XXX: we need to update nip before the store
4017 * if we enter power saving mode, we will exit the loop
4018 * directly from ppc_store_msr
4019 */
be147d08 4020 gen_update_nip(ctx, ctx->nip);
d9bce9d9 4021#if defined(TARGET_PPC64)
6527f6ea
AJ		 4022 if (!ctx->sf_mode) {
4023 TCGv t0 = tcg_temp_new();
4024 TCGv t1 = tcg_temp_new();
4025 tcg_gen_andi_tl(t0, cpu_msr, 0xFFFFFFFF00000000ULL);
4026 tcg_gen_ext32u_tl(t1, cpu_gpr[rS(ctx->opcode)]);
4027 tcg_gen_or_tl(t0, t0, t1);
4028 tcg_temp_free(t1);
4029 gen_helper_store_msr(t0);
4030 tcg_temp_free(t0);
4031 } else
d9bce9d9 4032#endif
6527f6ea 4033 gen_helper_store_msr(cpu_gpr[rS(ctx->opcode)]);
be147d08 4034 /* Must stop the translation as machine state (may have) changed */
6527f6ea 4035 /* Note that mtmsr is not always defined as context-synchronizing */
056b05f8 4036 ctx->exception = POWERPC_EXCP_STOP;
be147d08 4037 }
9a64fbe4 4038#endif
79aceca5
FB		 4039}
4040
4041/* mtspr */
4042GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC)
4043{
3fc6c082 4044 void (*write_cb)(void *opaque, int sprn);
79aceca5
FB		 4045 uint32_t sprn = SPR(ctx->opcode);
4046
3fc6c082 4047#if !defined(CONFIG_USER_ONLY)
be147d08
JM		 4048 if (ctx->supervisor == 2)
4049 write_cb = ctx->spr_cb[sprn].hea_write;
7863667f 4050 else if (ctx->supervisor)
3fc6c082
FB		 4051 write_cb = ctx->spr_cb[sprn].oea_write;
4052 else
9a64fbe4 4053#endif
3fc6c082 4054 write_cb = ctx->spr_cb[sprn].uea_write;
76a66253
JM		 4055 if (likely(write_cb != NULL)) {
4056 if (likely(write_cb != SPR_NOACCESS)) {
f78fb44e 4057 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
3fc6c082
FB		 4058 (*write_cb)(ctx, sprn);
4059 } else {
4060 /* Privilege exception */
4a057712 4061 if (loglevel != 0) {
077fc206
JM		 4062 fprintf(logfile, "Trying to write privileged spr %d %03x at "
4063 ADDRX "\n", sprn, sprn, ctx->nip);
f24e5695 4064 }
077fc206
JM		 4065 printf("Trying to write privileged spr %d %03x at " ADDRX "\n",
4066 sprn, sprn, ctx->nip);
e1833e1f 4067 GEN_EXCP_PRIVREG(ctx);
76a66253 4068 }
3fc6c082
FB		 4069 } else {
4070 /* Not defined */
4a057712 4071 if (loglevel != 0) {
077fc206
JM		 4072 fprintf(logfile, "Trying to write invalid spr %d %03x at "
4073 ADDRX "\n", sprn, sprn, ctx->nip);
f24e5695 4074 }
077fc206
JM		 4075 printf("Trying to write invalid spr %d %03x at " ADDRX "\n",
4076 sprn, sprn, ctx->nip);
e1833e1f
JM		 4077 GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,
4078 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_SPR);
79aceca5 4079 }
79aceca5
FB		 4080}
4081
4082/*** Cache management ***/
79aceca5 4083/* dcbf */
0db1b20e 4084GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE)
79aceca5 4085{
dac454af 4086 /* XXX: specification says this is treated as a load by the MMU */
a7812ae4 4087 TCGv t0 = tcg_temp_new();
a7859e89 4088 gen_set_access_type(ACCESS_CACHE);
fea0c503
AJ		 4089 gen_addr_reg_index(t0, ctx);
4090 gen_qemu_ld8u(t0, t0, ctx->mem_idx);
4091 tcg_temp_free(t0);
79aceca5
FB		 4092}
4093
4094/* dcbi (Supervisor only) */
9a64fbe4 4095GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE)
79aceca5 4096{
a541f297 4097#if defined(CONFIG_USER_ONLY)
e1833e1f 4098 GEN_EXCP_PRIVOPC(ctx);
a541f297 4099#else
b61f2753 4100 TCGv EA, val;
76a66253 4101 if (unlikely(!ctx->supervisor)) {
e1833e1f 4102 GEN_EXCP_PRIVOPC(ctx);
9fddaa0c 4103 return;
9a64fbe4 4104 }
a7812ae4 4105 EA = tcg_temp_new();
a7859e89 4106 gen_set_access_type(ACCESS_CACHE);
b61f2753 4107 gen_addr_reg_index(EA, ctx);
a7812ae4 4108 val = tcg_temp_new();
76a66253 4109 /* XXX: specification says this should be treated as a store by the MMU */
b61f2753
AJ		 4110 gen_qemu_ld8u(val, EA, ctx->mem_idx);
4111 gen_qemu_st8(val, EA, ctx->mem_idx);
4112 tcg_temp_free(val);
4113 tcg_temp_free(EA);
a541f297 4114#endif
79aceca5
FB		 4115}
4116
4117/* dcdst */
9a64fbe4 4118GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE)
79aceca5 4119{
76a66253 4120 /* XXX: specification say this is treated as a load by the MMU */
a7812ae4 4121 TCGv t0 = tcg_temp_new();
a7859e89 4122 gen_set_access_type(ACCESS_CACHE);
fea0c503
AJ		 4123 gen_addr_reg_index(t0, ctx);
4124 gen_qemu_ld8u(t0, t0, ctx->mem_idx);
4125 tcg_temp_free(t0);
79aceca5
FB		 4126}
4127
4128/* dcbt */
0db1b20e 4129GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE)
79aceca5 4130{
0db1b20e 4131 /* interpreted as no-op */
76a66253
JM		 4132 /* XXX: specification say this is treated as a load by the MMU
4133 * but does not generate any exception
4134 */
79aceca5
FB		 4135}
4136
4137/* dcbtst */
0db1b20e 4138GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE)
79aceca5 4139{
0db1b20e 4140 /* interpreted as no-op */
76a66253
JM		 4141 /* XXX: specification say this is treated as a load by the MMU
4142 * but does not generate any exception
4143 */
79aceca5
FB		 4144}
4145
4146/* dcbz */
d63001d1 4147GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE_DCBZ)
79aceca5 4148{
799a8c8d
AJ		 4149 TCGv t0 = tcg_temp_new();
4150 gen_addr_reg_index(t0, ctx);
4151 /* NIP cannot be restored if the memory exception comes from an helper */
4152 gen_update_nip(ctx, ctx->nip - 4);
4153 gen_helper_dcbz(t0);
4154 tcg_temp_free(t0);
d63001d1
JM		 4155}
4156
c7697e1f 4157GEN_HANDLER2(dcbz_970, "dcbz", 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZT)
d63001d1 4158{
799a8c8d
AJ		 4159 TCGv t0 = tcg_temp_new();
4160 gen_addr_reg_index(t0, ctx);
4161 /* NIP cannot be restored if the memory exception comes from an helper */
4162 gen_update_nip(ctx, ctx->nip - 4);
d63001d1 4163 if (ctx->opcode & 0x00200000)
799a8c8d 4164 gen_helper_dcbz(t0);
d63001d1 4165 else
799a8c8d
AJ		 4166 gen_helper_dcbz_970(t0);
4167 tcg_temp_free(t0);
79aceca5
FB		 4168}
4169
4170/* icbi */
1b413d55 4171GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI)
79aceca5 4172{
37d269df 4173 TCGv t0 = tcg_temp_new();
30032c94
JM		 4174 /* NIP cannot be restored if the memory exception comes from an helper */
4175 gen_update_nip(ctx, ctx->nip - 4);
37d269df
AJ		 4176 gen_addr_reg_index(t0, ctx);
4177 gen_helper_icbi(t0);
4178 tcg_temp_free(t0);
79aceca5
FB		 4179}
4180
4181/* Optional: */
4182/* dcba */
a750fc0b 4183GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA)
79aceca5 4184{
0db1b20e
JM		 4185 /* interpreted as no-op */
4186 /* XXX: specification say this is treated as a store by the MMU
4187 * but does not generate any exception
4188 */
79aceca5
FB		 4189}
4190
4191/*** Segment register manipulation ***/
4192/* Supervisor only: */
4193/* mfsr */
4194GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT)
4195{
9a64fbe4 4196#if defined(CONFIG_USER_ONLY)
e1833e1f 4197 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 4198#else
74d37793 4199 TCGv t0;
76a66253 4200 if (unlikely(!ctx->supervisor)) {
e1833e1f 4201 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 4202 return;
9a64fbe4 4203 }
74d37793
AJ		 4204 t0 = tcg_const_tl(SR(ctx->opcode));
4205 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0);
4206 tcg_temp_free(t0);
9a64fbe4 4207#endif
79aceca5
FB		 4208}
4209
4210/* mfsrin */
9a64fbe4 4211GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT)
79aceca5 4212{
9a64fbe4 4213#if defined(CONFIG_USER_ONLY)
e1833e1f 4214 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 4215#else
74d37793 4216 TCGv t0;
76a66253 4217 if (unlikely(!ctx->supervisor)) {
e1833e1f 4218 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 4219 return;
9a64fbe4 4220 }
74d37793
AJ		 4221 t0 = tcg_temp_new();
4222 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4223 tcg_gen_andi_tl(t0, t0, 0xF);
4224 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0);
4225 tcg_temp_free(t0);
9a64fbe4 4226#endif
79aceca5
FB		 4227}
4228
4229/* mtsr */
e63c59cb 4230GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT)
79aceca5 4231{
9a64fbe4 4232#if defined(CONFIG_USER_ONLY)
e1833e1f 4233 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 4234#else
74d37793 4235 TCGv t0;
76a66253 4236 if (unlikely(!ctx->supervisor)) {
e1833e1f 4237 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 4238 return;
9a64fbe4 4239 }
74d37793
AJ		 4240 t0 = tcg_const_tl(SR(ctx->opcode));
4241 gen_helper_store_sr(t0, cpu_gpr[rS(ctx->opcode)]);
4242 tcg_temp_free(t0);
9a64fbe4 4243#endif
79aceca5
FB		 4244}
4245
4246/* mtsrin */
9a64fbe4 4247GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT)
79aceca5 4248{
9a64fbe4 4249#if defined(CONFIG_USER_ONLY)
e1833e1f 4250 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 4251#else
74d37793 4252 TCGv t0;
76a66253 4253 if (unlikely(!ctx->supervisor)) {
e1833e1f 4254 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 4255 return;
9a64fbe4 4256 }
74d37793
AJ		 4257 t0 = tcg_temp_new();
4258 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4259 tcg_gen_andi_tl(t0, t0, 0xF);
4260 gen_helper_store_sr(t0, cpu_gpr[rD(ctx->opcode)]);
4261 tcg_temp_free(t0);
9a64fbe4 4262#endif
79aceca5
FB		 4263}
4264
12de9a39
JM		 4265#if defined(TARGET_PPC64)
4266/* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4267/* mfsr */
c7697e1f 4268GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B)
12de9a39
JM		 4269{
4270#if defined(CONFIG_USER_ONLY)
4271 GEN_EXCP_PRIVREG(ctx);
4272#else
74d37793 4273 TCGv t0;
12de9a39
JM		 4274 if (unlikely(!ctx->supervisor)) {
4275 GEN_EXCP_PRIVREG(ctx);
4276 return;
4277 }
74d37793
AJ		 4278 t0 = tcg_const_tl(SR(ctx->opcode));
4279 gen_helper_load_slb(cpu_gpr[rD(ctx->opcode)], t0);
4280 tcg_temp_free(t0);
12de9a39
JM		 4281#endif
4282}
4283
4284/* mfsrin */
c7697e1f
JM		 4285GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
4286 PPC_SEGMENT_64B)
12de9a39
JM		 4287{
4288#if defined(CONFIG_USER_ONLY)
4289 GEN_EXCP_PRIVREG(ctx);
4290#else
74d37793 4291 TCGv t0;
12de9a39
JM		 4292 if (unlikely(!ctx->supervisor)) {
4293 GEN_EXCP_PRIVREG(ctx);
4294 return;
4295 }
74d37793
AJ		 4296 t0 = tcg_temp_new();
4297 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4298 tcg_gen_andi_tl(t0, t0, 0xF);
4299 gen_helper_load_slb(cpu_gpr[rD(ctx->opcode)], t0);
4300 tcg_temp_free(t0);
12de9a39
JM		 4301#endif
4302}
4303
4304/* mtsr */
c7697e1f 4305GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B)
12de9a39
JM		 4306{
4307#if defined(CONFIG_USER_ONLY)
4308 GEN_EXCP_PRIVREG(ctx);
4309#else
74d37793 4310 TCGv t0;
12de9a39
JM		 4311 if (unlikely(!ctx->supervisor)) {
4312 GEN_EXCP_PRIVREG(ctx);
4313 return;
4314 }
74d37793
AJ		 4315 t0 = tcg_const_tl(SR(ctx->opcode));
4316 gen_helper_store_slb(t0, cpu_gpr[rS(ctx->opcode)]);
4317 tcg_temp_free(t0);
12de9a39
JM		 4318#endif
4319}
4320
4321/* mtsrin */
c7697e1f
JM		 4322GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
4323 PPC_SEGMENT_64B)
12de9a39
JM		 4324{
4325#if defined(CONFIG_USER_ONLY)
4326 GEN_EXCP_PRIVREG(ctx);
4327#else
74d37793 4328 TCGv t0;
12de9a39
JM		 4329 if (unlikely(!ctx->supervisor)) {
4330 GEN_EXCP_PRIVREG(ctx);
4331 return;
4332 }
74d37793
AJ		 4333 t0 = tcg_temp_new();
4334 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4335 tcg_gen_andi_tl(t0, t0, 0xF);
4336 gen_helper_store_slb(t0, cpu_gpr[rS(ctx->opcode)]);
4337 tcg_temp_free(t0);
12de9a39
JM		 4338#endif
4339}
4340#endif /* defined(TARGET_PPC64) */
4341
79aceca5
FB		 4342/*** Lookaside buffer management ***/
4343/* Optional & supervisor only: */
4344/* tlbia */
3fc6c082 4345GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA)
79aceca5 4346{
9a64fbe4 4347#if defined(CONFIG_USER_ONLY)
e1833e1f 4348 GEN_EXCP_PRIVOPC(ctx);
9a64fbe4 4349#else
76a66253 4350 if (unlikely(!ctx->supervisor)) {
e1833e1f 4351 GEN_EXCP_PRIVOPC(ctx);
9fddaa0c 4352 return;
9a64fbe4 4353 }
74d37793 4354 gen_helper_tlbia();
9a64fbe4 4355#endif
79aceca5
FB		 4356}
4357
4358/* tlbie */
76a66253 4359GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE)
79aceca5 4360{
9a64fbe4 4361#if defined(CONFIG_USER_ONLY)
e1833e1f 4362 GEN_EXCP_PRIVOPC(ctx);
9a64fbe4 4363#else
76a66253 4364 if (unlikely(!ctx->supervisor)) {
e1833e1f 4365 GEN_EXCP_PRIVOPC(ctx);
9fddaa0c 4366 return;
9a64fbe4 4367 }
d9bce9d9 4368#if defined(TARGET_PPC64)
74d37793
AJ		 4369 if (!ctx->sf_mode) {
4370 TCGv t0 = tcg_temp_new();
4371 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
4372 gen_helper_tlbie(t0);
4373 tcg_temp_free(t0);
4374 } else
d9bce9d9 4375#endif
74d37793 4376 gen_helper_tlbie(cpu_gpr[rB(ctx->opcode)]);
9a64fbe4 4377#endif
79aceca5
FB		 4378}
4379
4380/* tlbsync */
76a66253 4381GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC)
79aceca5 4382{
9a64fbe4 4383#if defined(CONFIG_USER_ONLY)
e1833e1f 4384 GEN_EXCP_PRIVOPC(ctx);
9a64fbe4 4385#else
76a66253 4386 if (unlikely(!ctx->supervisor)) {
e1833e1f 4387 GEN_EXCP_PRIVOPC(ctx);
9fddaa0c 4388 return;
9a64fbe4
FB		 4389 }
4390 /* This has no effect: it should ensure that all previous
4391 * tlbie have completed
4392 */
e1833e1f 4393 GEN_STOP(ctx);
9a64fbe4 4394#endif
79aceca5
FB		 4395}
4396
426613db
JM		 4397#if defined(TARGET_PPC64)
4398/* slbia */
4399GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI)
4400{
4401#if defined(CONFIG_USER_ONLY)
e1833e1f 4402 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 4403#else
4404 if (unlikely(!ctx->supervisor)) {
e1833e1f 4405 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 4406 return;
4407 }
74d37793 4408 gen_helper_slbia();
426613db
JM		 4409#endif
4410}
4411
4412/* slbie */
4413GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI)
4414{
4415#if defined(CONFIG_USER_ONLY)
e1833e1f 4416 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 4417#else
4418 if (unlikely(!ctx->supervisor)) {
e1833e1f 4419 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 4420 return;
4421 }
74d37793 4422 gen_helper_slbie(cpu_gpr[rB(ctx->opcode)]);
426613db
JM		 4423#endif
4424}
4425#endif
4426
79aceca5
FB		 4427/*** External control ***/
4428/* Optional: */
111bfab3 4429/* eciwx */
79aceca5
FB		 4430GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN)
4431{
fa407c03
AJ		 4432 /* Should check EAR[E] ! */
4433 TCGv t0 = tcg_temp_new();
a7859e89 4434 gen_set_access_type(ACCESS_RES);
fa407c03
AJ		 4435 gen_addr_reg_index(t0, ctx);
4436 gen_check_align(ctx, t0, 0x03);
4437 gen_qemu_ld32u(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx);
4438 tcg_temp_free(t0);
76a66253
JM		 4439}
4440
4441/* ecowx */
4442GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN)
4443{
fa407c03
AJ		 4444 /* Should check EAR[E] ! */
4445 TCGv t0 = tcg_temp_new();
4446 gen_set_access_type(ACCESS_RES);
4447 gen_addr_reg_index(t0, ctx);
4448 gen_check_align(ctx, t0, 0x03);
4449 gen_qemu_st32(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx);
4450 tcg_temp_free(t0);
76a66253
JM		 4451}
4452
4453/* PowerPC 601 specific instructions */
4454/* abs - abs. */
4455GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR)
4456{
22e0e173
AJ		 4457 int l1 = gen_new_label();
4458 int l2 = gen_new_label();
4459 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
4460 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4461 tcg_gen_br(l2);
4462 gen_set_label(l1);
4463 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4464 gen_set_label(l2);
76a66253 4465 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4466 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4467}
4468
4469/* abso - abso. */
4470GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR)
4471{
22e0e173
AJ		 4472 int l1 = gen_new_label();
4473 int l2 = gen_new_label();
4474 int l3 = gen_new_label();
4475 /* Start with XER OV disabled, the most likely case */
4476 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4477 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
4478 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
4479 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
4480 tcg_gen_br(l2);
4481 gen_set_label(l1);
4482 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4483 tcg_gen_br(l3);
4484 gen_set_label(l2);
4485 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4486 gen_set_label(l3);
76a66253 4487 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4488 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4489}
4490
4491/* clcs */
a750fc0b 4492GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR)
76a66253 4493{
22e0e173
AJ		 4494 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
4495 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], t0);
4496 tcg_temp_free_i32(t0);
c7697e1f 4497 /* Rc=1 sets CR0 to an undefined state */
76a66253
JM		 4498}
4499
4500/* div - div. */
4501GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR)
4502{
22e0e173 4503 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
76a66253 4504 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4505 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4506}
4507
4508/* divo - divo. */
4509GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR)
4510{
22e0e173 4511 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
76a66253 4512 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4513 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4514}
4515
4516/* divs - divs. */
4517GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR)
4518{
22e0e173 4519 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
76a66253 4520 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4521 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4522}
4523
4524/* divso - divso. */
4525GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR)
4526{
22e0e173 4527 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
76a66253 4528 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4529 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4530}
4531
4532/* doz - doz. */
4533GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR)
4534{
22e0e173
AJ		 4535 int l1 = gen_new_label();
4536 int l2 = gen_new_label();
4537 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4538 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4539 tcg_gen_br(l2);
4540 gen_set_label(l1);
4541 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4542 gen_set_label(l2);
76a66253 4543 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4544 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4545}
4546
4547/* dozo - dozo. */
4548GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR)
4549{
22e0e173
AJ		 4550 int l1 = gen_new_label();
4551 int l2 = gen_new_label();
4552 TCGv t0 = tcg_temp_new();
4553 TCGv t1 = tcg_temp_new();
4554 TCGv t2 = tcg_temp_new();
4555 /* Start with XER OV disabled, the most likely case */
4556 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4557 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4558 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4559 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4560 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
4561 tcg_gen_andc_tl(t1, t1, t2);
4562 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
4563 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4564 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
4565 tcg_gen_br(l2);
4566 gen_set_label(l1);
4567 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4568 gen_set_label(l2);
4569 tcg_temp_free(t0);
4570 tcg_temp_free(t1);
4571 tcg_temp_free(t2);
76a66253 4572 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4573 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4574}
4575
4576/* dozi */
4577GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
4578{
22e0e173
AJ		 4579 target_long simm = SIMM(ctx->opcode);
4580 int l1 = gen_new_label();
4581 int l2 = gen_new_label();
4582 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
4583 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
4584 tcg_gen_br(l2);
4585 gen_set_label(l1);
4586 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4587 gen_set_label(l2);
4588 if (unlikely(Rc(ctx->opcode) != 0))
4589 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4590}
4591
76a66253
JM		 4592/* lscbx - lscbx. */
4593GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR)
4594{
bdb4b689
AJ		 4595 TCGv t0 = tcg_temp_new();
4596 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
4597 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
4598 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
76a66253 4599
bdb4b689 4600 gen_addr_reg_index(t0, ctx);
76a66253 4601 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 4602 gen_update_nip(ctx, ctx->nip - 4);
bdb4b689
AJ		 4603 gen_helper_lscbx(t0, t0, t1, t2, t3);
4604 tcg_temp_free_i32(t1);
4605 tcg_temp_free_i32(t2);
4606 tcg_temp_free_i32(t3);
3d7b417e 4607 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
bdb4b689 4608 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
76a66253 4609 if (unlikely(Rc(ctx->opcode) != 0))
bdb4b689
AJ		 4610 gen_set_Rc0(ctx, t0);
4611 tcg_temp_free(t0);
76a66253
JM		 4612}
4613
4614/* maskg - maskg. */
4615GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR)
4616{
22e0e173
AJ		 4617 int l1 = gen_new_label();
4618 TCGv t0 = tcg_temp_new();
4619 TCGv t1 = tcg_temp_new();
4620 TCGv t2 = tcg_temp_new();
4621 TCGv t3 = tcg_temp_new();
4622 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
4623 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4624 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
4625 tcg_gen_addi_tl(t2, t0, 1);
4626 tcg_gen_shr_tl(t2, t3, t2);
4627 tcg_gen_shr_tl(t3, t3, t1);
4628 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
4629 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
4630 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4631 gen_set_label(l1);
4632 tcg_temp_free(t0);
4633 tcg_temp_free(t1);
4634 tcg_temp_free(t2);
4635 tcg_temp_free(t3);
76a66253 4636 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4637 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4638}
4639
4640/* maskir - maskir. */
4641GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR)
4642{
22e0e173
AJ		 4643 TCGv t0 = tcg_temp_new();
4644 TCGv t1 = tcg_temp_new();
4645 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4646 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4647 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4648 tcg_temp_free(t0);
4649 tcg_temp_free(t1);
76a66253 4650 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4651 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4652}
4653
4654/* mul - mul. */
4655GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR)
4656{
22e0e173
AJ		 4657 TCGv_i64 t0 = tcg_temp_new_i64();
4658 TCGv_i64 t1 = tcg_temp_new_i64();
4659 TCGv t2 = tcg_temp_new();
4660 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4661 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4662 tcg_gen_mul_i64(t0, t0, t1);
4663 tcg_gen_trunc_i64_tl(t2, t0);
4664 gen_store_spr(SPR_MQ, t2);
4665 tcg_gen_shri_i64(t1, t0, 32);
4666 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4667 tcg_temp_free_i64(t0);
4668 tcg_temp_free_i64(t1);
4669 tcg_temp_free(t2);
76a66253 4670 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4671 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4672}
4673
4674/* mulo - mulo. */
4675GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR)
4676{
22e0e173
AJ		 4677 int l1 = gen_new_label();
4678 TCGv_i64 t0 = tcg_temp_new_i64();
4679 TCGv_i64 t1 = tcg_temp_new_i64();
4680 TCGv t2 = tcg_temp_new();
4681 /* Start with XER OV disabled, the most likely case */
4682 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4683 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4684 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4685 tcg_gen_mul_i64(t0, t0, t1);
4686 tcg_gen_trunc_i64_tl(t2, t0);
4687 gen_store_spr(SPR_MQ, t2);
4688 tcg_gen_shri_i64(t1, t0, 32);
4689 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4690 tcg_gen_ext32s_i64(t1, t0);
4691 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
4692 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
4693 gen_set_label(l1);
4694 tcg_temp_free_i64(t0);
4695 tcg_temp_free_i64(t1);
4696 tcg_temp_free(t2);
76a66253 4697 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4698 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4699}
4700
4701/* nabs - nabs. */
4702GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR)
4703{
22e0e173
AJ		 4704 int l1 = gen_new_label();
4705 int l2 = gen_new_label();
4706 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4707 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4708 tcg_gen_br(l2);
4709 gen_set_label(l1);
4710 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4711 gen_set_label(l2);
76a66253 4712 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4713 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4714}
4715
4716/* nabso - nabso. */
4717GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR)
4718{
22e0e173
AJ		 4719 int l1 = gen_new_label();
4720 int l2 = gen_new_label();
4721 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4722 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4723 tcg_gen_br(l2);
4724 gen_set_label(l1);
4725 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4726 gen_set_label(l2);
4727 /* nabs never overflows */
4728 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
76a66253 4729 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4730 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4731}
4732
4733/* rlmi - rlmi. */
4734GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
4735{
7487953d
AJ		 4736 uint32_t mb = MB(ctx->opcode);
4737 uint32_t me = ME(ctx->opcode);
4738 TCGv t0 = tcg_temp_new();
4739 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4740 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4741 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
4742 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
4743 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
4744 tcg_temp_free(t0);
76a66253 4745 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4746 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4747}
4748
4749/* rrib - rrib. */
4750GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR)
4751{
7487953d
AJ		 4752 TCGv t0 = tcg_temp_new();
4753 TCGv t1 = tcg_temp_new();
4754 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4755 tcg_gen_movi_tl(t1, 0x80000000);
4756 tcg_gen_shr_tl(t1, t1, t0);
4757 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4758 tcg_gen_and_tl(t0, t0, t1);
4759 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
4760 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4761 tcg_temp_free(t0);
4762 tcg_temp_free(t1);
76a66253 4763 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4764 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4765}
4766
4767/* sle - sle. */
4768GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR)
4769{
7487953d
AJ		 4770 TCGv t0 = tcg_temp_new();
4771 TCGv t1 = tcg_temp_new();
4772 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4773 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4774 tcg_gen_subfi_tl(t1, 32, t1);
4775 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4776 tcg_gen_or_tl(t1, t0, t1);
4777 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4778 gen_store_spr(SPR_MQ, t1);
4779 tcg_temp_free(t0);
4780 tcg_temp_free(t1);
76a66253 4781 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4782 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4783}
4784
4785/* sleq - sleq. */
4786GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR)
4787{
7487953d
AJ		 4788 TCGv t0 = tcg_temp_new();
4789 TCGv t1 = tcg_temp_new();
4790 TCGv t2 = tcg_temp_new();
4791 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4792 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
4793 tcg_gen_shl_tl(t2, t2, t0);
4794 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4795 gen_load_spr(t1, SPR_MQ);
4796 gen_store_spr(SPR_MQ, t0);
4797 tcg_gen_and_tl(t0, t0, t2);
4798 tcg_gen_andc_tl(t1, t1, t2);
4799 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4800 tcg_temp_free(t0);
4801 tcg_temp_free(t1);
4802 tcg_temp_free(t2);
76a66253 4803 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4804 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4805}
4806
4807/* sliq - sliq. */
4808GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR)
4809{
7487953d
AJ		 4810 int sh = SH(ctx->opcode);
4811 TCGv t0 = tcg_temp_new();
4812 TCGv t1 = tcg_temp_new();
4813 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4814 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4815 tcg_gen_or_tl(t1, t0, t1);
4816 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4817 gen_store_spr(SPR_MQ, t1);
4818 tcg_temp_free(t0);
4819 tcg_temp_free(t1);
76a66253 4820 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4821 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4822}
4823
4824/* slliq - slliq. */
4825GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR)
4826{
7487953d
AJ		 4827 int sh = SH(ctx->opcode);
4828 TCGv t0 = tcg_temp_new();
4829 TCGv t1 = tcg_temp_new();
4830 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4831 gen_load_spr(t1, SPR_MQ);
4832 gen_store_spr(SPR_MQ, t0);
4833 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
4834 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
4835 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4836 tcg_temp_free(t0);
4837 tcg_temp_free(t1);
76a66253 4838 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4839 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4840}
4841
4842/* sllq - sllq. */
4843GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR)
4844{
7487953d
AJ		 4845 int l1 = gen_new_label();
4846 int l2 = gen_new_label();
4847 TCGv t0 = tcg_temp_local_new();
4848 TCGv t1 = tcg_temp_local_new();
4849 TCGv t2 = tcg_temp_local_new();
4850 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4851 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
4852 tcg_gen_shl_tl(t1, t1, t2);
4853 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4854 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
4855 gen_load_spr(t0, SPR_MQ);
4856 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4857 tcg_gen_br(l2);
4858 gen_set_label(l1);
4859 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4860 gen_load_spr(t2, SPR_MQ);
4861 tcg_gen_andc_tl(t1, t2, t1);
4862 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4863 gen_set_label(l2);
4864 tcg_temp_free(t0);
4865 tcg_temp_free(t1);
4866 tcg_temp_free(t2);
76a66253 4867 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4868 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4869}
4870
4871/* slq - slq. */
4872GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR)
4873{
7487953d
AJ		 4874 int l1 = gen_new_label();
4875 TCGv t0 = tcg_temp_new();
4876 TCGv t1 = tcg_temp_new();
4877 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4878 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4879 tcg_gen_subfi_tl(t1, 32, t1);
4880 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4881 tcg_gen_or_tl(t1, t0, t1);
4882 gen_store_spr(SPR_MQ, t1);
4883 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
4884 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4885 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4886 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
4887 gen_set_label(l1);
4888 tcg_temp_free(t0);
4889 tcg_temp_free(t1);
76a66253 4890 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4891 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4892}
4893
d9bce9d9 4894/* sraiq - sraiq. */
76a66253
JM		 4895GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR)
4896{
7487953d
AJ		 4897 int sh = SH(ctx->opcode);
4898 int l1 = gen_new_label();
4899 TCGv t0 = tcg_temp_new();
4900 TCGv t1 = tcg_temp_new();
4901 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4902 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4903 tcg_gen_or_tl(t0, t0, t1);
4904 gen_store_spr(SPR_MQ, t0);
4905 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
4906 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4907 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
4908 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_CA));
4909 gen_set_label(l1);
4910 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
4911 tcg_temp_free(t0);
4912 tcg_temp_free(t1);
76a66253 4913 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4914 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4915}
4916
4917/* sraq - sraq. */
4918GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR)
4919{
7487953d
AJ		 4920 int l1 = gen_new_label();
4921 int l2 = gen_new_label();
4922 TCGv t0 = tcg_temp_new();
4923 TCGv t1 = tcg_temp_local_new();
4924 TCGv t2 = tcg_temp_local_new();
4925 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4926 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4927 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
4928 tcg_gen_subfi_tl(t2, 32, t2);
4929 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
4930 tcg_gen_or_tl(t0, t0, t2);
4931 gen_store_spr(SPR_MQ, t0);
4932 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4933 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
4934 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
4935 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
4936 gen_set_label(l1);
4937 tcg_temp_free(t0);
4938 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
4939 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
4940 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4941 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
4942 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_CA));
4943 gen_set_label(l2);
4944 tcg_temp_free(t1);
4945 tcg_temp_free(t2);
76a66253 4946 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4947 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4948}
4949
4950/* sre - sre. */
4951GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR)
4952{
7487953d
AJ		 4953 TCGv t0 = tcg_temp_new();
4954 TCGv t1 = tcg_temp_new();
4955 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4956 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4957 tcg_gen_subfi_tl(t1, 32, t1);
4958 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4959 tcg_gen_or_tl(t1, t0, t1);
4960 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4961 gen_store_spr(SPR_MQ, t1);
4962 tcg_temp_free(t0);
4963 tcg_temp_free(t1);
76a66253 4964 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4965 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4966}
4967
4968/* srea - srea. */
4969GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR)
4970{
7487953d
AJ		 4971 TCGv t0 = tcg_temp_new();
4972 TCGv t1 = tcg_temp_new();
4973 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4974 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4975 gen_store_spr(SPR_MQ, t0);
4976 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
4977 tcg_temp_free(t0);
4978 tcg_temp_free(t1);
76a66253 4979 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4980 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4981}
4982
4983/* sreq */
4984GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR)
4985{
7487953d
AJ		 4986 TCGv t0 = tcg_temp_new();
4987 TCGv t1 = tcg_temp_new();
4988 TCGv t2 = tcg_temp_new();
4989 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4990 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
4991 tcg_gen_shr_tl(t1, t1, t0);
4992 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4993 gen_load_spr(t2, SPR_MQ);
4994 gen_store_spr(SPR_MQ, t0);
4995 tcg_gen_and_tl(t0, t0, t1);
4996 tcg_gen_andc_tl(t2, t2, t1);
4997 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
4998 tcg_temp_free(t0);
4999 tcg_temp_free(t1);
5000 tcg_temp_free(t2);
76a66253 5001 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5002 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5003}
5004
5005/* sriq */
5006GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR)
5007{
7487953d
AJ		 5008 int sh = SH(ctx->opcode);
5009 TCGv t0 = tcg_temp_new();
5010 TCGv t1 = tcg_temp_new();
5011 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5012 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5013 tcg_gen_or_tl(t1, t0, t1);
5014 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5015 gen_store_spr(SPR_MQ, t1);
5016 tcg_temp_free(t0);
5017 tcg_temp_free(t1);
76a66253 5018 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5019 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5020}
5021
5022/* srliq */
5023GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR)
5024{
7487953d
AJ		 5025 int sh = SH(ctx->opcode);
5026 TCGv t0 = tcg_temp_new();
5027 TCGv t1 = tcg_temp_new();
5028 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5029 gen_load_spr(t1, SPR_MQ);
5030 gen_store_spr(SPR_MQ, t0);
5031 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
5032 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
5033 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5034 tcg_temp_free(t0);
5035 tcg_temp_free(t1);
76a66253 5036 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5037 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5038}
5039
5040/* srlq */
5041GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR)
5042{
7487953d
AJ		 5043 int l1 = gen_new_label();
5044 int l2 = gen_new_label();
5045 TCGv t0 = tcg_temp_local_new();
5046 TCGv t1 = tcg_temp_local_new();
5047 TCGv t2 = tcg_temp_local_new();
5048 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5049 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5050 tcg_gen_shr_tl(t2, t1, t2);
5051 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5052 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5053 gen_load_spr(t0, SPR_MQ);
5054 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5055 tcg_gen_br(l2);
5056 gen_set_label(l1);
5057 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5058 tcg_gen_and_tl(t0, t0, t2);
5059 gen_load_spr(t1, SPR_MQ);
5060 tcg_gen_andc_tl(t1, t1, t2);
5061 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5062 gen_set_label(l2);
5063 tcg_temp_free(t0);
5064 tcg_temp_free(t1);
5065 tcg_temp_free(t2);
76a66253 5066 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5067 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5068}
5069
5070/* srq */
5071GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR)
5072{
7487953d
AJ		 5073 int l1 = gen_new_label();
5074 TCGv t0 = tcg_temp_new();
5075 TCGv t1 = tcg_temp_new();
5076 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5077 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5078 tcg_gen_subfi_tl(t1, 32, t1);
5079 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5080 tcg_gen_or_tl(t1, t0, t1);
5081 gen_store_spr(SPR_MQ, t1);
5082 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5083 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5084 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5085 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5086 gen_set_label(l1);
5087 tcg_temp_free(t0);
5088 tcg_temp_free(t1);
76a66253 5089 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5090 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5091}
5092
5093/* PowerPC 602 specific instructions */
5094/* dsa */
5095GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC)
5096{
5097 /* XXX: TODO */
e1833e1f 5098 GEN_EXCP_INVAL(ctx);
76a66253
JM		 5099}
5100
5101/* esa */
5102GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC)
5103{
5104 /* XXX: TODO */
e1833e1f 5105 GEN_EXCP_INVAL(ctx);
76a66253
JM		 5106}
5107
5108/* mfrom */
5109GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC)
5110{
5111#if defined(CONFIG_USER_ONLY)
e1833e1f 5112 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5113#else
5114 if (unlikely(!ctx->supervisor)) {
e1833e1f 5115 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5116 return;
5117 }
cf02a65c 5118 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5119#endif
5120}
5121
5122/* 602 - 603 - G2 TLB management */
5123/* tlbld */
c7697e1f 5124GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB)
76a66253
JM		 5125{
5126#if defined(CONFIG_USER_ONLY)
e1833e1f 5127 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5128#else
5129 if (unlikely(!ctx->supervisor)) {
e1833e1f 5130 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5131 return;
5132 }
74d37793 5133 gen_helper_6xx_tlbd(cpu_gpr[rB(ctx->opcode)]);
76a66253
JM		 5134#endif
5135}
5136
5137/* tlbli */
c7697e1f 5138GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB)
76a66253
JM		 5139{
5140#if defined(CONFIG_USER_ONLY)
e1833e1f 5141 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5142#else
5143 if (unlikely(!ctx->supervisor)) {
e1833e1f 5144 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5145 return;
5146 }
74d37793 5147 gen_helper_6xx_tlbi(cpu_gpr[rB(ctx->opcode)]);
76a66253
JM		 5148#endif
5149}
5150
7dbe11ac
JM		 5151/* 74xx TLB management */
5152/* tlbld */
c7697e1f 5153GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB)
7dbe11ac
JM		 5154{
5155#if defined(CONFIG_USER_ONLY)
5156 GEN_EXCP_PRIVOPC(ctx);
5157#else
5158 if (unlikely(!ctx->supervisor)) {
5159 GEN_EXCP_PRIVOPC(ctx);
5160 return;
5161 }
74d37793 5162 gen_helper_74xx_tlbd(cpu_gpr[rB(ctx->opcode)]);
7dbe11ac
JM		 5163#endif
5164}
5165
5166/* tlbli */
c7697e1f 5167GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB)
7dbe11ac
JM		 5168{
5169#if defined(CONFIG_USER_ONLY)
5170 GEN_EXCP_PRIVOPC(ctx);
5171#else
5172 if (unlikely(!ctx->supervisor)) {
5173 GEN_EXCP_PRIVOPC(ctx);
5174 return;
5175 }
74d37793 5176 gen_helper_74xx_tlbi(cpu_gpr[rB(ctx->opcode)]);
7dbe11ac
JM		 5177#endif
5178}
5179
76a66253
JM		 5180/* POWER instructions not in PowerPC 601 */
5181/* clf */
5182GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER)
5183{
5184 /* Cache line flush: implemented as no-op */
5185}
5186
5187/* cli */
5188GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER)
5189{
7f75ffd3 5190 /* Cache line invalidate: privileged and treated as no-op */
76a66253 5191#if defined(CONFIG_USER_ONLY)
e1833e1f 5192 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5193#else
5194 if (unlikely(!ctx->supervisor)) {
e1833e1f 5195 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5196 return;
5197 }
5198#endif
5199}
5200
5201/* dclst */
5202GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER)
5203{
5204 /* Data cache line store: treated as no-op */
5205}
5206
5207GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER)
5208{
5209#if defined(CONFIG_USER_ONLY)
e1833e1f 5210 GEN_EXCP_PRIVOPC(ctx);
76a66253 5211#else
74d37793
AJ		 5212 int ra = rA(ctx->opcode);
5213 int rd = rD(ctx->opcode);
5214 TCGv t0;
76a66253 5215 if (unlikely(!ctx->supervisor)) {
e1833e1f 5216 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5217 return;
5218 }
74d37793
AJ		 5219 t0 = tcg_temp_new();
5220 gen_addr_reg_index(t0, ctx);
5221 tcg_gen_shri_tl(t0, t0, 28);
5222 tcg_gen_andi_tl(t0, t0, 0xF);
5223 gen_helper_load_sr(cpu_gpr[rd], t0);
5224 tcg_temp_free(t0);
76a66253 5225 if (ra != 0 && ra != rd)
74d37793 5226 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
76a66253
JM		 5227#endif
5228}
5229
5230GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER)
5231{
5232#if defined(CONFIG_USER_ONLY)
e1833e1f 5233 GEN_EXCP_PRIVOPC(ctx);
76a66253 5234#else
22e0e173 5235 TCGv t0;
76a66253 5236 if (unlikely(!ctx->supervisor)) {
e1833e1f 5237 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5238 return;
5239 }
22e0e173
AJ		 5240 t0 = tcg_temp_new();
5241 gen_addr_reg_index(t0, ctx);
5242 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], t0);
5243 tcg_temp_free(t0);
76a66253
JM		 5244#endif
5245}
5246
5247GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER)
5248{
5249#if defined(CONFIG_USER_ONLY)
e1833e1f 5250 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5251#else
5252 if (unlikely(!ctx->supervisor)) {
e1833e1f 5253 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5254 return;
5255 }
d72a19f7 5256 gen_helper_rfsvc();
e1833e1f 5257 GEN_SYNC(ctx);
76a66253
JM		 5258#endif
5259}
5260
5261/* svc is not implemented for now */
5262
5263/* POWER2 specific instructions */
5264/* Quad manipulation (load/store two floats at a time) */
76a66253
JM		 5265
5266/* lfq */
5267GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5268{
01a4afeb
AJ		 5269 int rd = rD(ctx->opcode);
5270 TCGv t0 = tcg_temp_new();
5271 gen_addr_imm_index(t0, ctx, 0);
5272 gen_qemu_ld64(cpu_fpr[rd], t0, ctx->mem_idx);
5273 tcg_gen_addi_tl(t0, t0, 8);
5274 gen_qemu_ld64(cpu_fpr[(rd + 1) % 32], t0, ctx->mem_idx);
5275 tcg_temp_free(t0);
76a66253
JM		 5276}
5277
5278/* lfqu */
5279GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5280{
5281 int ra = rA(ctx->opcode);
01a4afeb
AJ		 5282 int rd = rD(ctx->opcode);
5283 TCGv t0 = tcg_temp_new();
5284 TCGv t1 = tcg_temp_new();
5285 gen_addr_imm_index(t0, ctx, 0);
5286 gen_qemu_ld64(cpu_fpr[rd], t0, ctx->mem_idx);
5287 tcg_gen_addi_tl(t1, t0, 8);
5288 gen_qemu_ld64(cpu_fpr[(rd + 1) % 32], t1, ctx->mem_idx);
76a66253 5289 if (ra != 0)
01a4afeb
AJ		 5290 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5291 tcg_temp_free(t0);
5292 tcg_temp_free(t1);
76a66253
JM		 5293}
5294
5295/* lfqux */
5296GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2)
5297{
5298 int ra = rA(ctx->opcode);
01a4afeb
AJ		 5299 int rd = rD(ctx->opcode);
5300 TCGv t0 = tcg_temp_new();
5301 TCGv t1 = tcg_temp_new();
5302 gen_addr_reg_index(t0, ctx);
5303 gen_qemu_ld64(cpu_fpr[rd], t0, ctx->mem_idx);
5304 tcg_gen_addi_tl(t1, t0, 8);
5305 gen_qemu_ld64(cpu_fpr[(rd + 1) % 32], t1, ctx->mem_idx);
76a66253 5306 if (ra != 0)
01a4afeb
AJ		 5307 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5308 tcg_temp_free(t0);
5309 tcg_temp_free(t1);
76a66253
JM		 5310}
5311
5312/* lfqx */
5313GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2)
5314{
01a4afeb
AJ		 5315 int rd = rD(ctx->opcode);
5316 TCGv t0 = tcg_temp_new();
5317 gen_addr_reg_index(t0, ctx);
5318 gen_qemu_ld64(cpu_fpr[rd], t0, ctx->mem_idx);
5319 tcg_gen_addi_tl(t0, t0, 8);
5320 gen_qemu_ld64(cpu_fpr[(rd + 1) % 32], t0, ctx->mem_idx);
5321 tcg_temp_free(t0);
76a66253
JM		 5322}
5323
5324/* stfq */
5325GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5326{
01a4afeb
AJ		 5327 int rd = rD(ctx->opcode);
5328 TCGv t0 = tcg_temp_new();
5329 gen_addr_imm_index(t0, ctx, 0);
5330 gen_qemu_st64(cpu_fpr[rd], t0, ctx->mem_idx);
5331 tcg_gen_addi_tl(t0, t0, 8);
5332 gen_qemu_st64(cpu_fpr[(rd + 1) % 32], t0, ctx->mem_idx);
5333 tcg_temp_free(t0);
76a66253
JM		 5334}
5335
5336/* stfqu */
5337GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5338{
5339 int ra = rA(ctx->opcode);
01a4afeb
AJ		 5340 int rd = rD(ctx->opcode);
5341 TCGv t0 = tcg_temp_new();
5342 TCGv t1 = tcg_temp_new();
5343 gen_addr_imm_index(t0, ctx, 0);
5344 gen_qemu_st64(cpu_fpr[rd], t0, ctx->mem_idx);
5345 tcg_gen_addi_tl(t1, t0, 8);
5346 gen_qemu_st64(cpu_fpr[(rd + 1) % 32], t1, ctx->mem_idx);
76a66253 5347 if (ra != 0)
01a4afeb
AJ		 5348 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5349 tcg_temp_free(t0);
5350 tcg_temp_free(t1);
76a66253
JM		 5351}
5352
5353/* stfqux */
5354GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2)
5355{
5356 int ra = rA(ctx->opcode);
01a4afeb
AJ		 5357 int rd = rD(ctx->opcode);
5358 TCGv t0 = tcg_temp_new();
5359 TCGv t1 = tcg_temp_new();
5360 gen_addr_reg_index(t0, ctx);
5361 gen_qemu_st64(cpu_fpr[rd], t0, ctx->mem_idx);
5362 tcg_gen_addi_tl(t1, t0, 8);
5363 gen_qemu_st64(cpu_fpr[(rd + 1) % 32], t1, ctx->mem_idx);
76a66253 5364 if (ra != 0)
01a4afeb
AJ		 5365 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5366 tcg_temp_free(t0);
5367 tcg_temp_free(t1);
76a66253
JM		 5368}
5369
5370/* stfqx */
5371GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2)
5372{
01a4afeb
AJ		 5373 int rd = rD(ctx->opcode);
5374 TCGv t0 = tcg_temp_new();
5375 gen_addr_reg_index(t0, ctx);
5376 gen_qemu_st64(cpu_fpr[rd], t0, ctx->mem_idx);
5377 tcg_gen_addi_tl(t0, t0, 8);
5378 gen_qemu_st64(cpu_fpr[(rd + 1) % 32], t0, ctx->mem_idx);
5379 tcg_temp_free(t0);
76a66253
JM		 5380}
5381
5382/* BookE specific instructions */
2662a059 5383/* XXX: not implemented on 440 ? */
05332d70 5384GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI)
76a66253
JM		 5385{
5386 /* XXX: TODO */
e1833e1f 5387 GEN_EXCP_INVAL(ctx);
76a66253
JM		 5388}
5389
2662a059 5390/* XXX: not implemented on 440 ? */
05332d70 5391GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA)
76a66253
JM		 5392{
5393#if defined(CONFIG_USER_ONLY)
e1833e1f 5394 GEN_EXCP_PRIVOPC(ctx);
76a66253 5395#else
74d37793 5396 TCGv t0;
76a66253 5397 if (unlikely(!ctx->supervisor)) {
e1833e1f 5398 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5399 return;
5400 }
74d37793 5401 gen_addr_reg_index(t0, ctx);
d9bce9d9 5402#if defined(TARGET_PPC64)
74d37793
AJ		 5403 if (!ctx->sf_mode)
5404 tcg_gen_ext32u_tl(t0, t0);
d9bce9d9 5405#endif
74d37793
AJ		 5406 gen_helper_tlbie(cpu_gpr[rB(ctx->opcode)]);
5407 tcg_temp_free(t0);
76a66253
JM		 5408#endif
5409}
5410
5411/* All 405 MAC instructions are translated here */
b068d6a7
JM		 5412static always_inline void gen_405_mulladd_insn (DisasContext *ctx,
5413 int opc2, int opc3,
5414 int ra, int rb, int rt, int Rc)
76a66253 5415{
182608d4
AJ		 5416 TCGv t0, t1;
5417
a7812ae4
PB		 5418 t0 = tcg_temp_local_new();
5419 t1 = tcg_temp_local_new();
182608d4 5420
76a66253
JM		 5421 switch (opc3 & 0x0D) {
5422 case 0x05:
5423 /* macchw - macchw. - macchwo - macchwo. */
5424 /* macchws - macchws. - macchwso - macchwso. */
5425 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5426 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5427 /* mulchw - mulchw. */
182608d4
AJ		 5428 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5429 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5430 tcg_gen_ext16s_tl(t1, t1);
76a66253
JM		 5431 break;
5432 case 0x04:
5433 /* macchwu - macchwu. - macchwuo - macchwuo. */
5434 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5435 /* mulchwu - mulchwu. */
182608d4
AJ		 5436 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5437 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5438 tcg_gen_ext16u_tl(t1, t1);
76a66253
JM		 5439 break;
5440 case 0x01:
5441 /* machhw - machhw. - machhwo - machhwo. */
5442 /* machhws - machhws. - machhwso - machhwso. */
5443 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5444 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5445 /* mulhhw - mulhhw. */
182608d4
AJ		 5446 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5447 tcg_gen_ext16s_tl(t0, t0);
5448 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5449 tcg_gen_ext16s_tl(t1, t1);
76a66253
JM		 5450 break;
5451 case 0x00:
5452 /* machhwu - machhwu. - machhwuo - machhwuo. */
5453 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5454 /* mulhhwu - mulhhwu. */
182608d4
AJ		 5455 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5456 tcg_gen_ext16u_tl(t0, t0);
5457 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5458 tcg_gen_ext16u_tl(t1, t1);
76a66253
JM		 5459 break;
5460 case 0x0D:
5461 /* maclhw - maclhw. - maclhwo - maclhwo. */
5462 /* maclhws - maclhws. - maclhwso - maclhwso. */
5463 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5464 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5465 /* mullhw - mullhw. */
182608d4
AJ		 5466 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5467 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
76a66253
JM		 5468 break;
5469 case 0x0C:
5470 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5471 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5472 /* mullhwu - mullhwu. */
182608d4
AJ		 5473 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5474 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
76a66253
JM		 5475 break;
5476 }
76a66253 5477 if (opc2 & 0x04) {
182608d4
AJ		 5478 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5479 tcg_gen_mul_tl(t1, t0, t1);
5480 if (opc2 & 0x02) {
5481 /* nmultiply-and-accumulate (0x0E) */
5482 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
5483 } else {
5484 /* multiply-and-accumulate (0x0C) */
5485 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
5486 }
5487
5488 if (opc3 & 0x12) {
5489 /* Check overflow and/or saturate */
5490 int l1 = gen_new_label();
5491
5492 if (opc3 & 0x10) {
5493 /* Start with XER OV disabled, the most likely case */
5494 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
5495 }
5496 if (opc3 & 0x01) {
5497 /* Signed */
5498 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
5499 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
5500 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
5501 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
bdc4e053 5502 if (opc3 & 0x02) {
182608d4
AJ		 5503 /* Saturate */
5504 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
5505 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
5506 }
5507 } else {
5508 /* Unsigned */
5509 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
bdc4e053 5510 if (opc3 & 0x02) {
182608d4
AJ		 5511 /* Saturate */
5512 tcg_gen_movi_tl(t0, UINT32_MAX);
5513 }
5514 }
5515 if (opc3 & 0x10) {
5516 /* Check overflow */
5517 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
5518 }
5519 gen_set_label(l1);
5520 tcg_gen_mov_tl(cpu_gpr[rt], t0);
5521 }
5522 } else {
5523 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
76a66253 5524 }
182608d4
AJ		 5525 tcg_temp_free(t0);
5526 tcg_temp_free(t1);
76a66253
JM		 5527 if (unlikely(Rc) != 0) {
5528 /* Update Rc0 */
182608d4 5529 gen_set_Rc0(ctx, cpu_gpr[rt]);
76a66253
JM		 5530 }
5531}
5532
a750fc0b
JM		 5533#define GEN_MAC_HANDLER(name, opc2, opc3) \
5534GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) \
76a66253
JM		 5535{ \
5536 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5537 rD(ctx->opcode), Rc(ctx->opcode)); \
5538}
5539
5540/* macchw - macchw. */
a750fc0b 5541GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
76a66253 5542/* macchwo - macchwo. */
a750fc0b 5543GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
76a66253 5544/* macchws - macchws. */
a750fc0b 5545GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
76a66253 5546/* macchwso - macchwso. */
a750fc0b 5547GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
76a66253 5548/* macchwsu - macchwsu. */
a750fc0b 5549GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
76a66253 5550/* macchwsuo - macchwsuo. */
a750fc0b 5551GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
76a66253 5552/* macchwu - macchwu. */
a750fc0b 5553GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
76a66253 5554/* macchwuo - macchwuo. */
a750fc0b 5555GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
76a66253 5556/* machhw - machhw. */
a750fc0b 5557GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
76a66253 5558/* machhwo - machhwo. */
a750fc0b 5559GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
76a66253 5560/* machhws - machhws. */
a750fc0b 5561GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
76a66253 5562/* machhwso - machhwso. */
a750fc0b 5563GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
76a66253 5564/* machhwsu - machhwsu. */
a750fc0b 5565GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
76a66253 5566/* machhwsuo - machhwsuo. */
a750fc0b 5567GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
76a66253 5568/* machhwu - machhwu. */
a750fc0b 5569GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
76a66253 5570/* machhwuo - machhwuo. */
a750fc0b 5571GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
76a66253 5572/* maclhw - maclhw. */
a750fc0b 5573GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
76a66253 5574/* maclhwo - maclhwo. */
a750fc0b 5575GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
76a66253 5576/* maclhws - maclhws. */
a750fc0b 5577GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
76a66253 5578/* maclhwso - maclhwso. */
a750fc0b 5579GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
76a66253 5580/* maclhwu - maclhwu. */
a750fc0b 5581GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
76a66253 5582/* maclhwuo - maclhwuo. */
a750fc0b 5583GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
76a66253 5584/* maclhwsu - maclhwsu. */
a750fc0b 5585GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
76a66253 5586/* maclhwsuo - maclhwsuo. */
a750fc0b 5587GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
76a66253 5588/* nmacchw - nmacchw. */
a750fc0b 5589GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
76a66253 5590/* nmacchwo - nmacchwo. */
a750fc0b 5591GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
76a66253 5592/* nmacchws - nmacchws. */
a750fc0b 5593GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
76a66253 5594/* nmacchwso - nmacchwso. */
a750fc0b 5595GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
76a66253 5596/* nmachhw - nmachhw. */
a750fc0b 5597GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
76a66253 5598/* nmachhwo - nmachhwo. */
a750fc0b 5599GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
76a66253 5600/* nmachhws - nmachhws. */
a750fc0b 5601GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
76a66253 5602/* nmachhwso - nmachhwso. */
a750fc0b 5603GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
76a66253 5604/* nmaclhw - nmaclhw. */
a750fc0b 5605GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
76a66253 5606/* nmaclhwo - nmaclhwo. */
a750fc0b 5607GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
76a66253 5608/* nmaclhws - nmaclhws. */
a750fc0b 5609GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
76a66253 5610/* nmaclhwso - nmaclhwso. */
a750fc0b 5611GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
76a66253
JM		 5612
5613/* mulchw - mulchw. */
a750fc0b 5614GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
76a66253 5615/* mulchwu - mulchwu. */
a750fc0b 5616GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
76a66253 5617/* mulhhw - mulhhw. */
a750fc0b 5618GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
76a66253 5619/* mulhhwu - mulhhwu. */
a750fc0b 5620GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
76a66253 5621/* mullhw - mullhw. */
a750fc0b 5622GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
76a66253 5623/* mullhwu - mullhwu. */
a750fc0b 5624GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
76a66253
JM		 5625
5626/* mfdcr */
05332d70 5627GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR)
76a66253
JM		 5628{
5629#if defined(CONFIG_USER_ONLY)
e1833e1f 5630 GEN_EXCP_PRIVREG(ctx);
76a66253 5631#else
06dca6a7 5632 TCGv dcrn;
76a66253 5633 if (unlikely(!ctx->supervisor)) {
e1833e1f 5634 GEN_EXCP_PRIVREG(ctx);
76a66253
JM		 5635 return;
5636 }
06dca6a7
AJ		 5637 /* NIP cannot be restored if the memory exception comes from an helper */
5638 gen_update_nip(ctx, ctx->nip - 4);
5639 dcrn = tcg_const_tl(SPR(ctx->opcode));
5640 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], dcrn);
5641 tcg_temp_free(dcrn);
76a66253
JM		 5642#endif
5643}
5644
5645/* mtdcr */
05332d70 5646GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR)
76a66253
JM		 5647{
5648#if defined(CONFIG_USER_ONLY)
e1833e1f 5649 GEN_EXCP_PRIVREG(ctx);
76a66253 5650#else
06dca6a7 5651 TCGv dcrn;
76a66253 5652 if (unlikely(!ctx->supervisor)) {
e1833e1f 5653 GEN_EXCP_PRIVREG(ctx);
76a66253
JM		 5654 return;
5655 }
06dca6a7
AJ		 5656 /* NIP cannot be restored if the memory exception comes from an helper */
5657 gen_update_nip(ctx, ctx->nip - 4);
5658 dcrn = tcg_const_tl(SPR(ctx->opcode));
5659 gen_helper_store_dcr(dcrn, cpu_gpr[rS(ctx->opcode)]);
5660 tcg_temp_free(dcrn);
a42bd6cc
JM		 5661#endif
5662}
5663
5664/* mfdcrx */
2662a059 5665/* XXX: not implemented on 440 ? */
05332d70 5666GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX)
a42bd6cc
JM		 5667{
5668#if defined(CONFIG_USER_ONLY)
e1833e1f 5669 GEN_EXCP_PRIVREG(ctx);
a42bd6cc
JM		 5670#else
5671 if (unlikely(!ctx->supervisor)) {
e1833e1f 5672 GEN_EXCP_PRIVREG(ctx);
a42bd6cc
JM		 5673 return;
5674 }
06dca6a7
AJ		 5675 /* NIP cannot be restored if the memory exception comes from an helper */
5676 gen_update_nip(ctx, ctx->nip - 4);
5677 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
a750fc0b 5678 /* Note: Rc update flag set leads to undefined state of Rc0 */
a42bd6cc
JM		 5679#endif
5680}
5681
5682/* mtdcrx */
2662a059 5683/* XXX: not implemented on 440 ? */
05332d70 5684GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX)
a42bd6cc
JM		 5685{
5686#if defined(CONFIG_USER_ONLY)
e1833e1f 5687 GEN_EXCP_PRIVREG(ctx);
a42bd6cc
JM		 5688#else
5689 if (unlikely(!ctx->supervisor)) {
e1833e1f 5690 GEN_EXCP_PRIVREG(ctx);
a42bd6cc
JM		 5691 return;
5692 }
06dca6a7
AJ		 5693 /* NIP cannot be restored if the memory exception comes from an helper */
5694 gen_update_nip(ctx, ctx->nip - 4);
5695 gen_helper_store_dcr(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
a750fc0b 5696 /* Note: Rc update flag set leads to undefined state of Rc0 */
76a66253
JM		 5697#endif
5698}
5699
a750fc0b
JM		 5700/* mfdcrux (PPC 460) : user-mode access to DCR */
5701GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX)
5702{
06dca6a7
AJ		 5703 /* NIP cannot be restored if the memory exception comes from an helper */
5704 gen_update_nip(ctx, ctx->nip - 4);
5705 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
a750fc0b
JM		 5706 /* Note: Rc update flag set leads to undefined state of Rc0 */
5707}
5708
5709/* mtdcrux (PPC 460) : user-mode access to DCR */
5710GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX)
5711{
06dca6a7
AJ		 5712 /* NIP cannot be restored if the memory exception comes from an helper */
5713 gen_update_nip(ctx, ctx->nip - 4);
5714 gen_helper_store_dcr(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
a750fc0b
JM		 5715 /* Note: Rc update flag set leads to undefined state of Rc0 */
5716}
5717
76a66253
JM		 5718/* dccci */
5719GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON)
5720{
5721#if defined(CONFIG_USER_ONLY)
e1833e1f 5722 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5723#else
5724 if (unlikely(!ctx->supervisor)) {
e1833e1f 5725 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5726 return;
5727 }
5728 /* interpreted as no-op */
5729#endif
5730}
5731
5732/* dcread */
5733GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON)
5734{
5735#if defined(CONFIG_USER_ONLY)
e1833e1f 5736 GEN_EXCP_PRIVOPC(ctx);
76a66253 5737#else
b61f2753 5738 TCGv EA, val;
76a66253 5739 if (unlikely(!ctx->supervisor)) {
e1833e1f 5740 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5741 return;
5742 }
a7812ae4 5743 EA = tcg_temp_new();
a7859e89 5744 gen_set_access_type(ACCESS_CACHE);
b61f2753 5745 gen_addr_reg_index(EA, ctx);
a7812ae4 5746 val = tcg_temp_new();
b61f2753
AJ		 5747 gen_qemu_ld32u(val, EA, ctx->mem_idx);
5748 tcg_temp_free(val);
5749 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
5750 tcg_temp_free(EA);
76a66253
JM		 5751#endif
5752}
5753
5754/* icbt */
c7697e1f 5755GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT)
76a66253
JM		 5756{
5757 /* interpreted as no-op */
5758 /* XXX: specification say this is treated as a load by the MMU
5759 * but does not generate any exception
5760 */
5761}
5762
5763/* iccci */
5764GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON)
5765{
5766#if defined(CONFIG_USER_ONLY)
e1833e1f 5767 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5768#else
5769 if (unlikely(!ctx->supervisor)) {
e1833e1f 5770 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5771 return;
5772 }
5773 /* interpreted as no-op */
5774#endif
5775}
5776
5777/* icread */
5778GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON)
5779{
5780#if defined(CONFIG_USER_ONLY)
e1833e1f 5781 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5782#else
5783 if (unlikely(!ctx->supervisor)) {
e1833e1f 5784 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5785 return;
5786 }
5787 /* interpreted as no-op */
5788#endif
5789}
5790
5791/* rfci (supervisor only) */
c7697e1f 5792GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP)
a42bd6cc
JM		 5793{
5794#if defined(CONFIG_USER_ONLY)
e1833e1f 5795 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 5796#else
5797 if (unlikely(!ctx->supervisor)) {
e1833e1f 5798 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 5799 return;
5800 }
5801 /* Restore CPU state */
d72a19f7 5802 gen_helper_40x_rfci();
e1833e1f 5803 GEN_SYNC(ctx);
a42bd6cc
JM		 5804#endif
5805}
5806
5807GEN_HANDLER(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE)
5808{
5809#if defined(CONFIG_USER_ONLY)
e1833e1f 5810 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 5811#else
5812 if (unlikely(!ctx->supervisor)) {
e1833e1f 5813 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 5814 return;
5815 }
5816 /* Restore CPU state */
d72a19f7 5817 gen_helper_rfci();
e1833e1f 5818 GEN_SYNC(ctx);
a42bd6cc
JM		 5819#endif
5820}
5821
5822/* BookE specific */
2662a059 5823/* XXX: not implemented on 440 ? */
05332d70 5824GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI)
76a66253
JM		 5825{
5826#if defined(CONFIG_USER_ONLY)
e1833e1f 5827 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5828#else
5829 if (unlikely(!ctx->supervisor)) {
e1833e1f 5830 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5831 return;
5832 }
5833 /* Restore CPU state */
d72a19f7 5834 gen_helper_rfdi();
e1833e1f 5835 GEN_SYNC(ctx);
76a66253
JM		 5836#endif
5837}
5838
2662a059 5839/* XXX: not implemented on 440 ? */
a750fc0b 5840GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI)
a42bd6cc
JM		 5841{
5842#if defined(CONFIG_USER_ONLY)
e1833e1f 5843 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 5844#else
5845 if (unlikely(!ctx->supervisor)) {
e1833e1f 5846 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 5847 return;
5848 }
5849 /* Restore CPU state */
d72a19f7 5850 gen_helper_rfmci();
e1833e1f 5851 GEN_SYNC(ctx);
a42bd6cc
JM		 5852#endif
5853}
5eb7995e 5854
d9bce9d9 5855/* TLB management - PowerPC 405 implementation */
76a66253 5856/* tlbre */
c7697e1f 5857GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB)
76a66253
JM		 5858{
5859#if defined(CONFIG_USER_ONLY)
e1833e1f 5860 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5861#else
5862 if (unlikely(!ctx->supervisor)) {
e1833e1f 5863 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5864 return;
5865 }
5866 switch (rB(ctx->opcode)) {
5867 case 0:
74d37793 5868 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5869 break;
5870 case 1:
74d37793 5871 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5872 break;
5873 default:
e1833e1f 5874 GEN_EXCP_INVAL(ctx);
76a66253 5875 break;
9a64fbe4 5876 }
76a66253
JM		 5877#endif
5878}
5879
d9bce9d9 5880/* tlbsx - tlbsx. */
c7697e1f 5881GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB)
76a66253
JM		 5882{
5883#if defined(CONFIG_USER_ONLY)
e1833e1f 5884 GEN_EXCP_PRIVOPC(ctx);
76a66253 5885#else
74d37793 5886 TCGv t0;
76a66253 5887 if (unlikely(!ctx->supervisor)) {
e1833e1f 5888 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5889 return;
5890 }
74d37793
AJ		 5891 t0 = tcg_temp_new();
5892 gen_addr_reg_index(t0, ctx);
5893 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], t0);
5894 tcg_temp_free(t0);
5895 if (Rc(ctx->opcode)) {
5896 int l1 = gen_new_label();
5897 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
5898 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
5899 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
5900 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5901 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5902 gen_set_label(l1);
5903 }
76a66253 5904#endif
79aceca5
FB		 5905}
5906
76a66253 5907/* tlbwe */
c7697e1f 5908GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB)
79aceca5 5909{
76a66253 5910#if defined(CONFIG_USER_ONLY)
e1833e1f 5911 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5912#else
5913 if (unlikely(!ctx->supervisor)) {
e1833e1f 5914 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5915 return;
5916 }
5917 switch (rB(ctx->opcode)) {
5918 case 0:
74d37793 5919 gen_helper_4xx_tlbwe_hi(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
76a66253
JM		 5920 break;
5921 case 1:
74d37793 5922 gen_helper_4xx_tlbwe_lo(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
76a66253
JM		 5923 break;
5924 default:
e1833e1f 5925 GEN_EXCP_INVAL(ctx);
76a66253 5926 break;
9a64fbe4 5927 }
76a66253
JM		 5928#endif
5929}
5930
a4bb6c3e 5931/* TLB management - PowerPC 440 implementation */
5eb7995e 5932/* tlbre */
c7697e1f 5933GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE)
5eb7995e
JM		 5934{
5935#if defined(CONFIG_USER_ONLY)
e1833e1f 5936 GEN_EXCP_PRIVOPC(ctx);
5eb7995e
JM		 5937#else
5938 if (unlikely(!ctx->supervisor)) {
e1833e1f 5939 GEN_EXCP_PRIVOPC(ctx);
5eb7995e
JM		 5940 return;
5941 }
5942 switch (rB(ctx->opcode)) {
5943 case 0:
5eb7995e 5944 case 1:
5eb7995e 5945 case 2:
74d37793
AJ		 5946 {
5947 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
5948 gen_helper_440_tlbwe(t0, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5949 tcg_temp_free_i32(t0);
5950 }
5eb7995e
JM		 5951 break;
5952 default:
e1833e1f 5953 GEN_EXCP_INVAL(ctx);
5eb7995e
JM		 5954 break;
5955 }
5956#endif
5957}
5958
5959/* tlbsx - tlbsx. */
c7697e1f 5960GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE)
5eb7995e
JM		 5961{
5962#if defined(CONFIG_USER_ONLY)
e1833e1f 5963 GEN_EXCP_PRIVOPC(ctx);
5eb7995e 5964#else
74d37793 5965 TCGv t0;
5eb7995e 5966 if (unlikely(!ctx->supervisor)) {
e1833e1f 5967 GEN_EXCP_PRIVOPC(ctx);
5eb7995e
JM		 5968 return;
5969 }
74d37793
AJ		 5970 t0 = tcg_temp_new();
5971 gen_addr_reg_index(t0, ctx);
5972 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], t0);
5973 tcg_temp_free(t0);
5974 if (Rc(ctx->opcode)) {
5975 int l1 = gen_new_label();
5976 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
5977 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
5978 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
5979 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5980 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5981 gen_set_label(l1);
5982 }
5eb7995e
JM		 5983#endif
5984}
5985
5986/* tlbwe */
c7697e1f 5987GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE)
5eb7995e
JM		 5988{
5989#if defined(CONFIG_USER_ONLY)
e1833e1f 5990 GEN_EXCP_PRIVOPC(ctx);
5eb7995e
JM		 5991#else
5992 if (unlikely(!ctx->supervisor)) {
e1833e1f 5993 GEN_EXCP_PRIVOPC(ctx);
5eb7995e
JM		 5994 return;
5995 }
5996 switch (rB(ctx->opcode)) {
5997 case 0:
5eb7995e 5998 case 1:
5eb7995e 5999 case 2:
74d37793
AJ		 6000 {
6001 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6002 gen_helper_440_tlbwe(t0, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
6003 tcg_temp_free_i32(t0);
6004 }
5eb7995e
JM		 6005 break;
6006 default:
e1833e1f 6007 GEN_EXCP_INVAL(ctx);
5eb7995e
JM		 6008 break;
6009 }
6010#endif
6011}
6012
76a66253 6013/* wrtee */
05332d70 6014GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE)
76a66253
JM		 6015{
6016#if defined(CONFIG_USER_ONLY)
e1833e1f 6017 GEN_EXCP_PRIVOPC(ctx);
76a66253 6018#else
6527f6ea 6019 TCGv t0;
76a66253 6020 if (unlikely(!ctx->supervisor)) {
e1833e1f 6021 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 6022 return;
6023 }
6527f6ea
AJ		 6024 t0 = tcg_temp_new();
6025 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
6026 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6027 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
6028 tcg_temp_free(t0);
dee96f6c
JM		 6029 /* Stop translation to have a chance to raise an exception
6030 * if we just set msr_ee to 1
6031 */
e1833e1f 6032 GEN_STOP(ctx);
76a66253
JM		 6033#endif
6034}
6035
6036/* wrteei */
05332d70 6037GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000EFC01, PPC_WRTEE)
76a66253
JM		 6038{
6039#if defined(CONFIG_USER_ONLY)
e1833e1f 6040 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 6041#else
6042 if (unlikely(!ctx->supervisor)) {
e1833e1f 6043 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 6044 return;
6045 }
6527f6ea
AJ		 6046 if (ctx->opcode & 0x00010000) {
6047 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
6048 /* Stop translation to have a chance to raise an exception */
6049 GEN_STOP(ctx);
6050 } else {
6051 tcg_gen_andi_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
6052 }
76a66253
JM		 6053#endif
6054}
6055
08e46e54 6056/* PowerPC 440 specific instructions */
76a66253
JM		 6057/* dlmzb */
6058GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC)
6059{
ef0d51af
AJ		 6060 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
6061 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
6062 cpu_gpr[rB(ctx->opcode)], t0);
6063 tcg_temp_free_i32(t0);
76a66253
JM		 6064}
6065
6066/* mbar replaces eieio on 440 */
6067GEN_HANDLER(mbar, 0x1F, 0x16, 0x13, 0x001FF801, PPC_BOOKE)
6068{
6069 /* interpreted as no-op */
6070}
6071
6072/* msync replaces sync on 440 */
0db1b20e 6073GEN_HANDLER(msync, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE)
76a66253
JM		 6074{
6075 /* interpreted as no-op */
6076}
6077
6078/* icbt */
c7697e1f 6079GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, PPC_BOOKE)
76a66253
JM		 6080{
6081 /* interpreted as no-op */
6082 /* XXX: specification say this is treated as a load by the MMU
6083 * but does not generate any exception
6084 */
79aceca5
FB		 6085}
6086
a9d9eb8f
JM		 6087/*** Altivec vector extension ***/
6088/* Altivec registers moves */
a9d9eb8f 6089
a9d9eb8f 6090#define GEN_VR_LDX(name, opc2, opc3) \
fe1e5c53 6091GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
a9d9eb8f 6092{ \
fe1e5c53 6093 TCGv EA; \
a9d9eb8f
JM		 6094 if (unlikely(!ctx->altivec_enabled)) { \
6095 GEN_EXCP_NO_VR(ctx); \
6096 return; \
6097 } \
fe1e5c53
AJ		 6098 EA = tcg_temp_new(); \
6099 gen_addr_reg_index(EA, ctx); \
6100 tcg_gen_andi_tl(EA, EA, ~0xf); \
6101 if (ctx->mem_idx & 1) { \
6102 gen_qemu_ld64(cpu_avrl[rD(ctx->opcode)], EA, ctx->mem_idx); \
6103 tcg_gen_addi_tl(EA, EA, 8); \
6104 gen_qemu_ld64(cpu_avrh[rD(ctx->opcode)], EA, ctx->mem_idx); \
6105 } else { \
6106 gen_qemu_ld64(cpu_avrh[rD(ctx->opcode)], EA, ctx->mem_idx); \
6107 tcg_gen_addi_tl(EA, EA, 8); \
6108 gen_qemu_ld64(cpu_avrl[rD(ctx->opcode)], EA, ctx->mem_idx); \
6109 } \
6110 tcg_temp_free(EA); \
a9d9eb8f
JM		 6111}
6112
6113#define GEN_VR_STX(name, opc2, opc3) \
6114GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
6115{ \
fe1e5c53 6116 TCGv EA; \
a9d9eb8f
JM		 6117 if (unlikely(!ctx->altivec_enabled)) { \
6118 GEN_EXCP_NO_VR(ctx); \
6119 return; \
6120 } \
fe1e5c53
AJ		 6121 EA = tcg_temp_new(); \
6122 gen_addr_reg_index(EA, ctx); \
6123 tcg_gen_andi_tl(EA, EA, ~0xf); \
6124 if (ctx->mem_idx & 1) { \
6125 gen_qemu_st64(cpu_avrl[rD(ctx->opcode)], EA, ctx->mem_idx); \
6126 tcg_gen_addi_tl(EA, EA, 8); \
6127 gen_qemu_st64(cpu_avrh[rD(ctx->opcode)], EA, ctx->mem_idx); \
6128 } else { \
6129 gen_qemu_st64(cpu_avrh[rD(ctx->opcode)], EA, ctx->mem_idx); \
6130 tcg_gen_addi_tl(EA, EA, 8); \
6131 gen_qemu_st64(cpu_avrl[rD(ctx->opcode)], EA, ctx->mem_idx); \
6132 } \
6133 tcg_temp_free(EA); \
a9d9eb8f
JM		 6134}
6135
fe1e5c53 6136GEN_VR_LDX(lvx, 0x07, 0x03);
a9d9eb8f 6137/* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
fe1e5c53 6138GEN_VR_LDX(lvxl, 0x07, 0x0B);
a9d9eb8f 6139
fe1e5c53 6140GEN_VR_STX(svx, 0x07, 0x07);
a9d9eb8f 6141/* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
fe1e5c53 6142GEN_VR_STX(svxl, 0x07, 0x0F);
a9d9eb8f 6143
0487d6a8 6144/*** SPE extension ***/
0487d6a8 6145/* Register moves */
3cd7d1dd 6146
a7812ae4 6147static always_inline void gen_load_gpr64(TCGv_i64 t, int reg) {
f78fb44e
AJ		 6148#if defined(TARGET_PPC64)
6149 tcg_gen_mov_i64(t, cpu_gpr[reg]);
6150#else
36aa55dc 6151 tcg_gen_concat_i32_i64(t, cpu_gpr[reg], cpu_gprh[reg]);
3cd7d1dd 6152#endif
f78fb44e 6153}
3cd7d1dd 6154
a7812ae4 6155static always_inline void gen_store_gpr64(int reg, TCGv_i64 t) {
f78fb44e
AJ		 6156#if defined(TARGET_PPC64)
6157 tcg_gen_mov_i64(cpu_gpr[reg], t);
6158#else
a7812ae4 6159 TCGv_i64 tmp = tcg_temp_new_i64();
f78fb44e 6160 tcg_gen_trunc_i64_i32(cpu_gpr[reg], t);
f78fb44e
AJ		 6161 tcg_gen_shri_i64(tmp, t, 32);
6162 tcg_gen_trunc_i64_i32(cpu_gprh[reg], tmp);
a7812ae4 6163 tcg_temp_free_i64(tmp);
3cd7d1dd 6164#endif
f78fb44e 6165}
3cd7d1dd 6166
0487d6a8
JM		 6167#define GEN_SPE(name0, name1, opc2, opc3, inval, type) \
6168GEN_HANDLER(name0##_##name1, 0x04, opc2, opc3, inval, type) \
6169{ \
6170 if (Rc(ctx->opcode)) \
6171 gen_##name1(ctx); \
6172 else \
6173 gen_##name0(ctx); \
6174}
6175
6176/* Handler for undefined SPE opcodes */
b068d6a7 6177static always_inline void gen_speundef (DisasContext *ctx)
0487d6a8 6178{
e1833e1f 6179 GEN_EXCP_INVAL(ctx);
0487d6a8
JM		 6180}
6181
57951c27
AJ		 6182/* SPE logic */
6183#if defined(TARGET_PPC64)
6184#define GEN_SPEOP_LOGIC2(name, tcg_op) \
b068d6a7 6185static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 6186{ \
6187 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 6188 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 6189 return; \
6190 } \
57951c27
AJ		 6191 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6192 cpu_gpr[rB(ctx->opcode)]); \
6193}
6194#else
6195#define GEN_SPEOP_LOGIC2(name, tcg_op) \
6196static always_inline void gen_##name (DisasContext *ctx) \
6197{ \
6198 if (unlikely(!ctx->spe_enabled)) { \
6199 GEN_EXCP_NO_AP(ctx); \
6200 return; \
6201 } \
6202 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6203 cpu_gpr[rB(ctx->opcode)]); \
6204 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6205 cpu_gprh[rB(ctx->opcode)]); \
0487d6a8 6206}
57951c27
AJ		 6207#endif
6208
6209GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl);
6210GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl);
6211GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl);
6212GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl);
6213GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl);
6214GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl);
6215GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl);
6216GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl);
0487d6a8 6217
57951c27
AJ		 6218/* SPE logic immediate */
6219#if defined(TARGET_PPC64)
6220#define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
3d3a6a0a
AJ		 6221static always_inline void gen_##name (DisasContext *ctx) \
6222{ \
6223 if (unlikely(!ctx->spe_enabled)) { \
6224 GEN_EXCP_NO_AP(ctx); \
6225 return; \
6226 } \
a7812ae4
PB		 6227 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6228 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6229 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
57951c27
AJ		 6230 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6231 tcg_opi(t0, t0, rB(ctx->opcode)); \
6232 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6233 tcg_gen_trunc_i64_i32(t1, t2); \
a7812ae4 6234 tcg_temp_free_i64(t2); \
57951c27
AJ		 6235 tcg_opi(t1, t1, rB(ctx->opcode)); \
6236 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
a7812ae4
PB		 6237 tcg_temp_free_i32(t0); \
6238 tcg_temp_free_i32(t1); \
3d3a6a0a 6239}
57951c27
AJ		 6240#else
6241#define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
b068d6a7 6242static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 6243{ \
6244 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 6245 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 6246 return; \
6247 } \
57951c27
AJ		 6248 tcg_opi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6249 rB(ctx->opcode)); \
6250 tcg_opi(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6251 rB(ctx->opcode)); \
0487d6a8 6252}
57951c27
AJ		 6253#endif
6254GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32);
6255GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32);
6256GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32);
6257GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32);
0487d6a8 6258
57951c27
AJ		 6259/* SPE arithmetic */
6260#if defined(TARGET_PPC64)
6261#define GEN_SPEOP_ARITH1(name, tcg_op) \
b068d6a7 6262static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 6263{ \
6264 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 6265 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 6266 return; \
6267 } \
a7812ae4
PB		 6268 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6269 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6270 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
57951c27
AJ		 6271 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6272 tcg_op(t0, t0); \
6273 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6274 tcg_gen_trunc_i64_i32(t1, t2); \
a7812ae4 6275 tcg_temp_free_i64(t2); \
57951c27
AJ		 6276 tcg_op(t1, t1); \
6277 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
a7812ae4
PB		 6278 tcg_temp_free_i32(t0); \
6279 tcg_temp_free_i32(t1); \
0487d6a8 6280}
57951c27 6281#else
a7812ae4 6282#define GEN_SPEOP_ARITH1(name, tcg_op) \
57951c27
AJ		 6283static always_inline void gen_##name (DisasContext *ctx) \
6284{ \
6285 if (unlikely(!ctx->spe_enabled)) { \
6286 GEN_EXCP_NO_AP(ctx); \
6287 return; \
6288 } \
6289 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \
6290 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \
6291}
6292#endif
0487d6a8 6293
a7812ae4 6294static always_inline void gen_op_evabs (TCGv_i32 ret, TCGv_i32 arg1)
57951c27
AJ		 6295{
6296 int l1 = gen_new_label();
6297 int l2 = gen_new_label();
0487d6a8 6298
57951c27
AJ		 6299 tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1);
6300 tcg_gen_neg_i32(ret, arg1);
6301 tcg_gen_br(l2);
6302 gen_set_label(l1);
a7812ae4 6303 tcg_gen_mov_i32(ret, arg1);
57951c27
AJ		 6304 gen_set_label(l2);
6305}
6306GEN_SPEOP_ARITH1(evabs, gen_op_evabs);
6307GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32);
6308GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32);
6309GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32);
a7812ae4 6310static always_inline void gen_op_evrndw (TCGv_i32 ret, TCGv_i32 arg1)
0487d6a8 6311{
57951c27
AJ		 6312 tcg_gen_addi_i32(ret, arg1, 0x8000);
6313 tcg_gen_ext16u_i32(ret, ret);
6314}
6315GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw);
a7812ae4
PB		 6316GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32);
6317GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32);
0487d6a8 6318
57951c27
AJ		 6319#if defined(TARGET_PPC64)
6320#define GEN_SPEOP_ARITH2(name, tcg_op) \
6321static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 6322{ \
6323 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 6324 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 6325 return; \
6326 } \
a7812ae4
PB		 6327 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6328 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6329 TCGv_i32 t2 = tcg_temp_local_new_i32(); \
6330 TCGv_i64 t3 = tcg_temp_local_new(TCG_TYPE_I64); \
57951c27
AJ		 6331 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6332 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rB(ctx->opcode)]); \
6333 tcg_op(t0, t0, t2); \
6334 tcg_gen_shri_i64(t3, cpu_gpr[rA(ctx->opcode)], 32); \
6335 tcg_gen_trunc_i64_i32(t1, t3); \
6336 tcg_gen_shri_i64(t3, cpu_gpr[rB(ctx->opcode)], 32); \
6337 tcg_gen_trunc_i64_i32(t2, t3); \
a7812ae4 6338 tcg_temp_free_i64(t3); \
57951c27 6339 tcg_op(t1, t1, t2); \
a7812ae4 6340 tcg_temp_free_i32(t2); \
57951c27 6341 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
a7812ae4
PB		 6342 tcg_temp_free_i32(t0); \
6343 tcg_temp_free_i32(t1); \
0487d6a8 6344}
57951c27
AJ		 6345#else
6346#define GEN_SPEOP_ARITH2(name, tcg_op) \
6347static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 6348{ \
6349 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 6350 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 6351 return; \
6352 } \
57951c27
AJ		 6353 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6354 cpu_gpr[rB(ctx->opcode)]); \
6355 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6356 cpu_gprh[rB(ctx->opcode)]); \
0487d6a8 6357}
57951c27 6358#endif
0487d6a8 6359
a7812ae4 6360static always_inline void gen_op_evsrwu (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
57951c27 6361{
a7812ae4 6362 TCGv_i32 t0;
57951c27 6363 int l1, l2;
0487d6a8 6364
57951c27
AJ		 6365 l1 = gen_new_label();
6366 l2 = gen_new_label();
a7812ae4 6367 t0 = tcg_temp_local_new_i32();
57951c27
AJ		 6368 /* No error here: 6 bits are used */
6369 tcg_gen_andi_i32(t0, arg2, 0x3F);
6370 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
6371 tcg_gen_shr_i32(ret, arg1, t0);
6372 tcg_gen_br(l2);
6373 gen_set_label(l1);
6374 tcg_gen_movi_i32(ret, 0);
6375 tcg_gen_br(l2);
a7812ae4 6376 tcg_temp_free_i32(t0);
57951c27
AJ		 6377}
6378GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu);
a7812ae4 6379static always_inline void gen_op_evsrws (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
57951c27 6380{
a7812ae4 6381 TCGv_i32 t0;
57951c27
AJ		 6382 int l1, l2;
6383
6384 l1 = gen_new_label();
6385 l2 = gen_new_label();
a7812ae4 6386 t0 = tcg_temp_local_new_i32();
57951c27
AJ		 6387 /* No error here: 6 bits are used */
6388 tcg_gen_andi_i32(t0, arg2, 0x3F);
6389 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
6390 tcg_gen_sar_i32(ret, arg1, t0);
6391 tcg_gen_br(l2);
6392 gen_set_label(l1);
6393 tcg_gen_movi_i32(ret, 0);
6394 tcg_gen_br(l2);
a7812ae4 6395 tcg_temp_free_i32(t0);
57951c27
AJ		 6396}
6397GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws);
a7812ae4 6398static always_inline void gen_op_evslw (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
57951c27 6399{
a7812ae4 6400 TCGv_i32 t0;
57951c27
AJ		 6401 int l1, l2;
6402
6403 l1 = gen_new_label();
6404 l2 = gen_new_label();
a7812ae4 6405 t0 = tcg_temp_local_new_i32();
57951c27
AJ		 6406 /* No error here: 6 bits are used */
6407 tcg_gen_andi_i32(t0, arg2, 0x3F);
6408 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
6409 tcg_gen_shl_i32(ret, arg1, t0);
6410 tcg_gen_br(l2);
6411 gen_set_label(l1);
6412 tcg_gen_movi_i32(ret, 0);
6413 tcg_gen_br(l2);
a7812ae4 6414 tcg_temp_free_i32(t0);
57951c27
AJ		 6415}
6416GEN_SPEOP_ARITH2(evslw, gen_op_evslw);
a7812ae4 6417static always_inline void gen_op_evrlw (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
57951c27 6418{
a7812ae4 6419 TCGv_i32 t0 = tcg_temp_new_i32();
57951c27
AJ		 6420 tcg_gen_andi_i32(t0, arg2, 0x1F);
6421 tcg_gen_rotl_i32(ret, arg1, t0);
a7812ae4 6422 tcg_temp_free_i32(t0);
57951c27
AJ		 6423}
6424GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw);
6425static always_inline void gen_evmergehi (DisasContext *ctx)
6426{
6427 if (unlikely(!ctx->spe_enabled)) {
6428 GEN_EXCP_NO_AP(ctx);
6429 return;
6430 }
6431#if defined(TARGET_PPC64)
a7812ae4
PB		 6432 TCGv t0 = tcg_temp_new();
6433 TCGv t1 = tcg_temp_new();
57951c27
AJ		 6434 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
6435 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
6436 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
6437 tcg_temp_free(t0);
6438 tcg_temp_free(t1);
6439#else
6440 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
6441 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6442#endif
6443}
6444GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32);
a7812ae4 6445static always_inline void gen_op_evsubf (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
0487d6a8 6446{
57951c27
AJ		 6447 tcg_gen_sub_i32(ret, arg2, arg1);
6448}
6449GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf);
0487d6a8 6450
57951c27
AJ		 6451/* SPE arithmetic immediate */
6452#if defined(TARGET_PPC64)
6453#define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
6454static always_inline void gen_##name (DisasContext *ctx) \
6455{ \
6456 if (unlikely(!ctx->spe_enabled)) { \
6457 GEN_EXCP_NO_AP(ctx); \
6458 return; \
6459 } \
a7812ae4
PB		 6460 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6461 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6462 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
57951c27
AJ		 6463 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
6464 tcg_op(t0, t0, rA(ctx->opcode)); \
6465 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
6466 tcg_gen_trunc_i64_i32(t1, t2); \
a7812ae4 6467 tcg_temp_free_i64(t2); \
57951c27
AJ		 6468 tcg_op(t1, t1, rA(ctx->opcode)); \
6469 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
a7812ae4
PB		 6470 tcg_temp_free_i32(t0); \
6471 tcg_temp_free_i32(t1); \
57951c27
AJ		 6472}
6473#else
6474#define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
6475static always_inline void gen_##name (DisasContext *ctx) \
6476{ \
6477 if (unlikely(!ctx->spe_enabled)) { \
6478 GEN_EXCP_NO_AP(ctx); \
6479 return; \
6480 } \
6481 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
6482 rA(ctx->opcode)); \
6483 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)], \
6484 rA(ctx->opcode)); \
6485}
6486#endif
6487GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32);
6488GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32);
6489
6490/* SPE comparison */
6491#if defined(TARGET_PPC64)
6492#define GEN_SPEOP_COMP(name, tcg_cond) \
6493static always_inline void gen_##name (DisasContext *ctx) \
6494{ \
6495 if (unlikely(!ctx->spe_enabled)) { \
6496 GEN_EXCP_NO_AP(ctx); \
6497 return; \
6498 } \
6499 int l1 = gen_new_label(); \
6500 int l2 = gen_new_label(); \
6501 int l3 = gen_new_label(); \
6502 int l4 = gen_new_label(); \
a7812ae4
PB		 6503 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6504 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6505 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
57951c27
AJ		 6506 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6507 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
6508 tcg_gen_brcond_i32(tcg_cond, t0, t1, l1); \
a7812ae4 6509 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \
57951c27
AJ		 6510 tcg_gen_br(l2); \
6511 gen_set_label(l1); \
6512 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
6513 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
6514 gen_set_label(l2); \
6515 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6516 tcg_gen_trunc_i64_i32(t0, t2); \
6517 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
6518 tcg_gen_trunc_i64_i32(t1, t2); \
a7812ae4 6519 tcg_temp_free_i64(t2); \
57951c27
AJ		 6520 tcg_gen_brcond_i32(tcg_cond, t0, t1, l3); \
6521 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
6522 ~(CRF_CH | CRF_CH_AND_CL)); \
6523 tcg_gen_br(l4); \
6524 gen_set_label(l3); \
6525 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
6526 CRF_CH | CRF_CH_OR_CL); \
6527 gen_set_label(l4); \
a7812ae4
PB		 6528 tcg_temp_free_i32(t0); \
6529 tcg_temp_free_i32(t1); \
57951c27
AJ		 6530}
6531#else
6532#define GEN_SPEOP_COMP(name, tcg_cond) \
6533static always_inline void gen_##name (DisasContext *ctx) \
6534{ \
6535 if (unlikely(!ctx->spe_enabled)) { \
6536 GEN_EXCP_NO_AP(ctx); \
6537 return; \
6538 } \
6539 int l1 = gen_new_label(); \
6540 int l2 = gen_new_label(); \
6541 int l3 = gen_new_label(); \
6542 int l4 = gen_new_label(); \
6543 \
6544 tcg_gen_brcond_i32(tcg_cond, cpu_gpr[rA(ctx->opcode)], \
6545 cpu_gpr[rB(ctx->opcode)], l1); \
6546 tcg_gen_movi_tl(cpu_crf[crfD(ctx->opcode)], 0); \
6547 tcg_gen_br(l2); \
6548 gen_set_label(l1); \
6549 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
6550 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
6551 gen_set_label(l2); \
6552 tcg_gen_brcond_i32(tcg_cond, cpu_gprh[rA(ctx->opcode)], \
6553 cpu_gprh[rB(ctx->opcode)], l3); \
6554 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
6555 ~(CRF_CH | CRF_CH_AND_CL)); \
6556 tcg_gen_br(l4); \
6557 gen_set_label(l3); \
6558 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
6559 CRF_CH | CRF_CH_OR_CL); \
6560 gen_set_label(l4); \
6561}
6562#endif
6563GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU);
6564GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT);
6565GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU);
6566GEN_SPEOP_COMP(evcmplts, TCG_COND_LT);
6567GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ);
6568
6569/* SPE misc */
6570static always_inline void gen_brinc (DisasContext *ctx)
6571{
6572 /* Note: brinc is usable even if SPE is disabled */
a7812ae4
PB		 6573 gen_helper_brinc(cpu_gpr[rD(ctx->opcode)],
6574 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
0487d6a8 6575}
57951c27
AJ		 6576static always_inline void gen_evmergelo (DisasContext *ctx)
6577{
6578 if (unlikely(!ctx->spe_enabled)) {
6579 GEN_EXCP_NO_AP(ctx);
6580 return;
6581 }
6582#if defined(TARGET_PPC64)
a7812ae4
PB		 6583 TCGv t0 = tcg_temp_new();
6584 TCGv t1 = tcg_temp_new();
57951c27
AJ		 6585 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x00000000FFFFFFFFLL);
6586 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
6587 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
6588 tcg_temp_free(t0);
6589 tcg_temp_free(t1);
6590#else
6591 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
6592 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6593#endif
6594}
6595static always_inline void gen_evmergehilo (DisasContext *ctx)
6596{
6597 if (unlikely(!ctx->spe_enabled)) {
6598 GEN_EXCP_NO_AP(ctx);
6599 return;
6600 }
6601#if defined(TARGET_PPC64)
a7812ae4
PB		 6602 TCGv t0 = tcg_temp_new();
6603 TCGv t1 = tcg_temp_new();
57951c27
AJ		 6604 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x00000000FFFFFFFFLL);
6605 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
6606 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
6607 tcg_temp_free(t0);
6608 tcg_temp_free(t1);
6609#else
6610 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
6611 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6612#endif
6613}
6614static always_inline void gen_evmergelohi (DisasContext *ctx)
6615{
6616 if (unlikely(!ctx->spe_enabled)) {
6617 GEN_EXCP_NO_AP(ctx);
6618 return;
6619 }
6620#if defined(TARGET_PPC64)
a7812ae4
PB		 6621 TCGv t0 = tcg_temp_new();
6622 TCGv t1 = tcg_temp_new();
57951c27
AJ		 6623 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
6624 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
6625 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
6626 tcg_temp_free(t0);
6627 tcg_temp_free(t1);
6628#else
6629 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
6630 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6631#endif
6632}
6633static always_inline void gen_evsplati (DisasContext *ctx)
6634{
38d14952 6635 uint64_t imm = ((int32_t)(rA(ctx->opcode) << 11)) >> 27;
0487d6a8 6636
57951c27 6637#if defined(TARGET_PPC64)
38d14952 6638 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
57951c27
AJ		 6639#else
6640 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
6641 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
6642#endif
6643}
b068d6a7 6644static always_inline void gen_evsplatfi (DisasContext *ctx)
0487d6a8 6645{
38d14952 6646 uint64_t imm = rA(ctx->opcode) << 11;
0487d6a8 6647
57951c27 6648#if defined(TARGET_PPC64)
38d14952 6649 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
57951c27
AJ		 6650#else
6651 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
6652 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
6653#endif
0487d6a8
JM		 6654}
6655
57951c27
AJ		 6656static always_inline void gen_evsel (DisasContext *ctx)
6657{
6658 int l1 = gen_new_label();
6659 int l2 = gen_new_label();
6660 int l3 = gen_new_label();
6661 int l4 = gen_new_label();
a7812ae4 6662 TCGv_i32 t0 = tcg_temp_local_new_i32();
57951c27 6663#if defined(TARGET_PPC64)
a7812ae4
PB		 6664 TCGv t1 = tcg_temp_local_new();
6665 TCGv t2 = tcg_temp_local_new();
57951c27
AJ		 6666#endif
6667 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3);
6668 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
6669#if defined(TARGET_PPC64)
6670 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF00000000ULL);
6671#else
6672 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6673#endif
6674 tcg_gen_br(l2);
6675 gen_set_label(l1);
6676#if defined(TARGET_PPC64)
6677 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0xFFFFFFFF00000000ULL);
6678#else
6679 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
6680#endif
6681 gen_set_label(l2);
6682 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2);
6683 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3);
6684#if defined(TARGET_PPC64)
6685 tcg_gen_andi_tl(t2, cpu_gpr[rA(ctx->opcode)], 0x00000000FFFFFFFFULL);
6686#else
6687 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6688#endif
6689 tcg_gen_br(l4);
6690 gen_set_label(l3);
6691#if defined(TARGET_PPC64)
6692 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x00000000FFFFFFFFULL);
6693#else
6694 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
6695#endif
6696 gen_set_label(l4);
a7812ae4 6697 tcg_temp_free_i32(t0);
57951c27
AJ		 6698#if defined(TARGET_PPC64)
6699 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t1, t2);
6700 tcg_temp_free(t1);
6701 tcg_temp_free(t2);
6702#endif
6703}
6704GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE)
6705{
6706 gen_evsel(ctx);
6707}
6708GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE)
6709{
6710 gen_evsel(ctx);
6711}
6712GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE)
6713{
6714 gen_evsel(ctx);
6715}
6716GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE)
6717{
6718 gen_evsel(ctx);
6719}
0487d6a8
JM		 6720
6721GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, PPC_SPE); ////
6722GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, PPC_SPE);
6723GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, PPC_SPE); ////
6724GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, PPC_SPE);
6725GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, PPC_SPE); ////
6726GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, PPC_SPE); ////
6727GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, PPC_SPE); ////
6728GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x00000000, PPC_SPE); //
6729GEN_SPE(speundef, evand, 0x08, 0x08, 0x00000000, PPC_SPE); ////
6730GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, PPC_SPE); ////
6731GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, PPC_SPE); ////
6732GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, PPC_SPE); ////
6733GEN_SPE(speundef, evorc, 0x0D, 0x08, 0x00000000, PPC_SPE); ////
6734GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, PPC_SPE); ////
6735GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, PPC_SPE); ////
6736GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, PPC_SPE);
6737GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, PPC_SPE); ////
6738GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, PPC_SPE);
6739GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, PPC_SPE); //
6740GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, PPC_SPE);
6741GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, PPC_SPE); ////
6742GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, PPC_SPE); ////
6743GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, PPC_SPE); ////
6744GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, PPC_SPE); ////
6745GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, PPC_SPE); ////
6746
6a6ae23f
AJ		 6747/* SPE load and stores */
6748static always_inline void gen_addr_spe_imm_index (TCGv EA, DisasContext *ctx, int sh)
6749{
6750 target_ulong uimm = rB(ctx->opcode);
6751
6752 if (rA(ctx->opcode) == 0)
6753 tcg_gen_movi_tl(EA, uimm << sh);
6754 else
6755 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh);
0487d6a8 6756}
6a6ae23f
AJ		 6757
6758static always_inline void gen_op_evldd(DisasContext *ctx, TCGv addr)
6759{
6760#if defined(TARGET_PPC64)
6761 gen_qemu_ld64(cpu_gpr[rD(ctx->opcode)], addr, ctx->mem_idx);
6762#else
6763 TCGv_i64 t0 = tcg_temp_new_i64();
6764 gen_qemu_ld64(t0, addr, ctx->mem_idx);
6765 tcg_gen_trunc_i64_i32(cpu_gpr[rD(ctx->opcode)], t0);
6766 tcg_gen_shri_i64(t0, t0, 32);
6767 tcg_gen_trunc_i64_i32(cpu_gprh[rD(ctx->opcode)], t0);
6768 tcg_temp_free_i64(t0);
6769#endif
0487d6a8 6770}
6a6ae23f
AJ		 6771
6772static always_inline void gen_op_evldw(DisasContext *ctx, TCGv addr)
6773{
0487d6a8 6774#if defined(TARGET_PPC64)
6a6ae23f
AJ		 6775 TCGv t0 = tcg_temp_new();
6776 gen_qemu_ld32u(t0, addr, ctx->mem_idx);
6777 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
6778 tcg_gen_addi_tl(addr, addr, 4);
6779 gen_qemu_ld32u(t0, addr, ctx->mem_idx);
6780 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6781 tcg_temp_free(t0);
6782#else
6783 gen_qemu_ld32u(cpu_gprh[rD(ctx->opcode)], addr, ctx->mem_idx);
6784 tcg_gen_addi_tl(addr, addr, 4);
6785 gen_qemu_ld32u(cpu_gpr[rD(ctx->opcode)], addr, ctx->mem_idx);
6786#endif
0487d6a8 6787}
6a6ae23f
AJ		 6788
6789static always_inline void gen_op_evldh(DisasContext *ctx, TCGv addr)
6790{
6791 TCGv t0 = tcg_temp_new();
6792#if defined(TARGET_PPC64)
6793 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6794 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
6795 tcg_gen_addi_tl(addr, addr, 2);
6796 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6797 tcg_gen_shli_tl(t0, t0, 32);
6798 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6799 tcg_gen_addi_tl(addr, addr, 2);
6800 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6801 tcg_gen_shli_tl(t0, t0, 16);
6802 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6803 tcg_gen_addi_tl(addr, addr, 2);
6804 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6805 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
0487d6a8 6806#else
6a6ae23f
AJ		 6807 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6808 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
6809 tcg_gen_addi_tl(addr, addr, 2);
6810 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6811 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
6812 tcg_gen_addi_tl(addr, addr, 2);
6813 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6814 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
6815 tcg_gen_addi_tl(addr, addr, 2);
6816 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6817 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
0487d6a8 6818#endif
6a6ae23f 6819 tcg_temp_free(t0);
0487d6a8
JM		 6820}
6821
6a6ae23f
AJ		 6822static always_inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr)
6823{
6824 TCGv t0 = tcg_temp_new();
6825 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6826#if defined(TARGET_PPC64)
6827 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
6828 tcg_gen_shli_tl(t0, t0, 16);
6829 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6830#else
6831 tcg_gen_shli_tl(t0, t0, 16);
6832 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
6833 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
6834#endif
6835 tcg_temp_free(t0);
0487d6a8
JM		 6836}
6837
6a6ae23f
AJ		 6838static always_inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr)
6839{
6840 TCGv t0 = tcg_temp_new();
6841 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6842#if defined(TARGET_PPC64)
6843 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
6844 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6845#else
6846 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
6847 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
6848#endif
6849 tcg_temp_free(t0);
0487d6a8
JM		 6850}
6851
6a6ae23f
AJ		 6852static always_inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr)
6853{
6854 TCGv t0 = tcg_temp_new();
6855 gen_qemu_ld16s(t0, addr, ctx->mem_idx);
6856#if defined(TARGET_PPC64)
6857 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
6858 tcg_gen_ext32u_tl(t0, t0);
6859 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6860#else
6861 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
6862 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
6863#endif
6864 tcg_temp_free(t0);
6865}
6866
6867static always_inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr)
6868{
6869 TCGv t0 = tcg_temp_new();
6870#if defined(TARGET_PPC64)
6871 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6872 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
6873 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6874 tcg_gen_shli_tl(t0, t0, 16);
6875 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6876#else
6877 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6878 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
6879 tcg_gen_addi_tl(addr, addr, 2);
6880 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6881 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
6882#endif
6883 tcg_temp_free(t0);
6884}
6885
6886static always_inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr)
6887{
6888#if defined(TARGET_PPC64)
6889 TCGv t0 = tcg_temp_new();
6890 gen_qemu_ld16u(cpu_gpr[rD(ctx->opcode)], addr, ctx->mem_idx);
6891 tcg_gen_addi_tl(addr, addr, 2);
6892 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6893 tcg_gen_shli_tl(t0, t0, 32);
6894 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6895 tcg_temp_free(t0);
6896#else
6897 gen_qemu_ld16u(cpu_gprh[rD(ctx->opcode)], addr, ctx->mem_idx);
6898 tcg_gen_addi_tl(addr, addr, 2);
6899 gen_qemu_ld16u(cpu_gpr[rD(ctx->opcode)], addr, ctx->mem_idx);
6900#endif
6901}
6902
6903static always_inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr)
6904{
6905#if defined(TARGET_PPC64)
6906 TCGv t0 = tcg_temp_new();
6907 gen_qemu_ld16s(t0, addr, ctx->mem_idx);
6908 tcg_gen_ext32u_tl(cpu_gpr[rD(ctx->opcode)], t0);
6909 tcg_gen_addi_tl(addr, addr, 2);
6910 gen_qemu_ld16s(t0, addr, ctx->mem_idx);
6911 tcg_gen_shli_tl(t0, t0, 32);
6912 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6913 tcg_temp_free(t0);
6914#else
6915 gen_qemu_ld16s(cpu_gprh[rD(ctx->opcode)], addr, ctx->mem_idx);
6916 tcg_gen_addi_tl(addr, addr, 2);
6917 gen_qemu_ld16s(cpu_gpr[rD(ctx->opcode)], addr, ctx->mem_idx);
6918#endif
6919}
6920
6921static always_inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr)
6922{
6923 TCGv t0 = tcg_temp_new();
6924 gen_qemu_ld32u(t0, addr, ctx->mem_idx);
0487d6a8 6925#if defined(TARGET_PPC64)
6a6ae23f
AJ		 6926 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
6927 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6928#else
6929 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
6930 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
6931#endif
6932 tcg_temp_free(t0);
6933}
6934
6935static always_inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr)
6936{
6937 TCGv t0 = tcg_temp_new();
6938#if defined(TARGET_PPC64)
6939 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6940 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
6941 tcg_gen_shli_tl(t0, t0, 32);
6942 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6943 tcg_gen_addi_tl(addr, addr, 2);
6944 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6945 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6946 tcg_gen_shli_tl(t0, t0, 16);
6947 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6948#else
6949 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6950 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
6951 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
6952 tcg_gen_addi_tl(addr, addr, 2);
6953 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6954 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
6955 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
0487d6a8 6956#endif
6a6ae23f
AJ		 6957 tcg_temp_free(t0);
6958}
6959
6960static always_inline void gen_op_evstdd(DisasContext *ctx, TCGv addr)
6961{
6962#if defined(TARGET_PPC64)
6963 gen_qemu_st64(cpu_gpr[rS(ctx->opcode)], addr, ctx->mem_idx);
0487d6a8 6964#else
6a6ae23f
AJ		 6965 TCGv_i64 t0 = tcg_temp_new_i64();
6966 tcg_gen_concat_i32_i64(t0, cpu_gpr[rS(ctx->opcode)], cpu_gprh[rS(ctx->opcode)]);
6967 gen_qemu_st64(t0, addr, ctx->mem_idx);
6968 tcg_temp_free_i64(t0);
6969#endif
6970}
6971
6972static always_inline void gen_op_evstdw(DisasContext *ctx, TCGv addr)
6973{
0487d6a8 6974#if defined(TARGET_PPC64)
6a6ae23f
AJ		 6975 TCGv t0 = tcg_temp_new();
6976 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
6977 gen_qemu_st32(t0, addr, ctx->mem_idx);
6978 tcg_temp_free(t0);
6979#else
6980 gen_qemu_st32(cpu_gprh[rS(ctx->opcode)], addr, ctx->mem_idx);
6981#endif
6982 tcg_gen_addi_tl(addr, addr, 4);
6983 gen_qemu_st32(cpu_gpr[rS(ctx->opcode)], addr, ctx->mem_idx);
6984}
6985
6986static always_inline void gen_op_evstdh(DisasContext *ctx, TCGv addr)
6987{
6988 TCGv t0 = tcg_temp_new();
6989#if defined(TARGET_PPC64)
6990 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
6991#else
6992 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
6993#endif
6994 gen_qemu_st16(t0, addr, ctx->mem_idx);
6995 tcg_gen_addi_tl(addr, addr, 2);
6996#if defined(TARGET_PPC64)
6997 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
6998 gen_qemu_st16(t0, addr, ctx->mem_idx);
6999#else
7000 gen_qemu_st16(cpu_gprh[rS(ctx->opcode)], addr, ctx->mem_idx);
7001#endif
7002 tcg_gen_addi_tl(addr, addr, 2);
7003 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
7004 gen_qemu_st16(t0, addr, ctx->mem_idx);
7005 tcg_temp_free(t0);
7006 tcg_gen_addi_tl(addr, addr, 2);
7007 gen_qemu_st16(cpu_gpr[rS(ctx->opcode)], addr, ctx->mem_idx);
7008}
7009
7010static always_inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr)
7011{
7012 TCGv t0 = tcg_temp_new();
7013#if defined(TARGET_PPC64)
7014 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
7015#else
7016 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
7017#endif
7018 gen_qemu_st16(t0, addr, ctx->mem_idx);
7019 tcg_gen_addi_tl(addr, addr, 2);
7020 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
7021 gen_qemu_st16(t0, addr, ctx->mem_idx);
7022 tcg_temp_free(t0);
7023}
7024
7025static always_inline void gen_op_evstwho(DisasContext *ctx, TCGv addr)
7026{
7027#if defined(TARGET_PPC64)
7028 TCGv t0 = tcg_temp_new();
7029 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7030 gen_qemu_st16(t0, addr, ctx->mem_idx);
7031 tcg_temp_free(t0);
7032#else
7033 gen_qemu_st16(cpu_gprh[rS(ctx->opcode)], addr, ctx->mem_idx);
7034#endif
7035 tcg_gen_addi_tl(addr, addr, 2);
7036 gen_qemu_st16(cpu_gpr[rS(ctx->opcode)], addr, ctx->mem_idx);
7037}
7038
7039static always_inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr)
7040{
7041#if defined(TARGET_PPC64)
7042 TCGv t0 = tcg_temp_new();
7043 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7044 gen_qemu_st32(t0, addr, ctx->mem_idx);
7045 tcg_temp_free(t0);
7046#else
7047 gen_qemu_st32(cpu_gprh[rS(ctx->opcode)], addr, ctx->mem_idx);
7048#endif
7049}
7050
7051static always_inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr)
7052{
7053 gen_qemu_st32(cpu_gpr[rS(ctx->opcode)], addr, ctx->mem_idx);
7054}
7055
7056#define GEN_SPEOP_LDST(name, opc2, sh) \
7057GEN_HANDLER(gen_##name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE) \
7058{ \
7059 TCGv t0; \
7060 if (unlikely(!ctx->spe_enabled)) { \
7061 GEN_EXCP_NO_AP(ctx); \
7062 return; \
7063 } \
7064 t0 = tcg_temp_new(); \
7065 if (Rc(ctx->opcode)) { \
7066 gen_addr_spe_imm_index(t0, ctx, sh); \
7067 } else { \
7068 gen_addr_reg_index(t0, ctx); \
7069 } \
7070 gen_op_##name(ctx, t0); \
7071 tcg_temp_free(t0); \
7072}
7073
7074GEN_SPEOP_LDST(evldd, 0x00, 3);
7075GEN_SPEOP_LDST(evldw, 0x01, 3);
7076GEN_SPEOP_LDST(evldh, 0x02, 3);
7077GEN_SPEOP_LDST(evlhhesplat, 0x04, 1);
7078GEN_SPEOP_LDST(evlhhousplat, 0x06, 1);
7079GEN_SPEOP_LDST(evlhhossplat, 0x07, 1);
7080GEN_SPEOP_LDST(evlwhe, 0x08, 2);
7081GEN_SPEOP_LDST(evlwhou, 0x0A, 2);
7082GEN_SPEOP_LDST(evlwhos, 0x0B, 2);
7083GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2);
7084GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2);
7085
7086GEN_SPEOP_LDST(evstdd, 0x10, 3);
7087GEN_SPEOP_LDST(evstdw, 0x11, 3);
7088GEN_SPEOP_LDST(evstdh, 0x12, 3);
7089GEN_SPEOP_LDST(evstwhe, 0x18, 2);
7090GEN_SPEOP_LDST(evstwho, 0x1A, 2);
7091GEN_SPEOP_LDST(evstwwe, 0x1C, 2);
7092GEN_SPEOP_LDST(evstwwo, 0x1E, 2);
0487d6a8
JM		 7093
7094/* Multiply and add - TODO */
7095#if 0
7096GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0x00000000, PPC_SPE);
7097GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0x00000000, PPC_SPE);
7098GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, PPC_SPE);
7099GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0x00000000, PPC_SPE);
7100GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, PPC_SPE);
7101GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0x00000000, PPC_SPE);
7102GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0x00000000, PPC_SPE);
7103GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0x00000000, PPC_SPE);
7104GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, PPC_SPE);
7105GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0x00000000, PPC_SPE);
7106GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, PPC_SPE);
7107GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0x00000000, PPC_SPE);
7108
7109GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0x00000000, PPC_SPE);
7110GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, PPC_SPE);
7111GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, PPC_SPE);
7112GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0x00000000, PPC_SPE);
7113GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0x00000000, PPC_SPE);
7114GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, PPC_SPE);
7115GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0x00000000, PPC_SPE);
7116GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0x00000000, PPC_SPE);
7117GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, PPC_SPE);
7118GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, PPC_SPE);
7119GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0x00000000, PPC_SPE);
7120GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0x00000000, PPC_SPE);
7121GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, PPC_SPE);
7122GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0x00000000, PPC_SPE);
7123
7124GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, PPC_SPE);
7125GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, PPC_SPE);
7126GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, PPC_SPE);
7127GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, PPC_SPE);
7128GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, PPC_SPE);
7129GEN_SPE(evmra, speundef, 0x07, 0x13, 0x0000F800, PPC_SPE);
7130
7131GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, PPC_SPE);
7132GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0x00000000, PPC_SPE);
7133GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, PPC_SPE);
7134GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0x00000000, PPC_SPE);
7135GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, PPC_SPE);
7136GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0x00000000, PPC_SPE);
7137GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, PPC_SPE);
7138GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0x00000000, PPC_SPE);
7139GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, PPC_SPE);
7140GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0x00000000, PPC_SPE);
7141GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, PPC_SPE);
7142GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0x00000000, PPC_SPE);
7143
7144GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, PPC_SPE);
7145GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, PPC_SPE);
7146GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0x00000000, PPC_SPE);
7147GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, PPC_SPE);
7148GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0x00000000, PPC_SPE);
7149
7150GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, PPC_SPE);
7151GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0x00000000, PPC_SPE);
7152GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, PPC_SPE);
7153GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0x00000000, PPC_SPE);
7154GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, PPC_SPE);
7155GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0x00000000, PPC_SPE);
7156GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, PPC_SPE);
7157GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0x00000000, PPC_SPE);
7158GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, PPC_SPE);
7159GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0x00000000, PPC_SPE);
7160GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, PPC_SPE);
7161GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0x00000000, PPC_SPE);
7162
7163GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, PPC_SPE);
7164GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, PPC_SPE);
7165GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0x00000000, PPC_SPE);
7166GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, PPC_SPE);
7167GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0x00000000, PPC_SPE);
7168#endif
7169
7170/*** SPE floating-point extension ***/
1c97856d
AJ		 7171#if defined(TARGET_PPC64)
7172#define GEN_SPEFPUOP_CONV_32_32(name) \
b068d6a7 7173static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8 7174{ \
1c97856d
AJ		 7175 TCGv_i32 t0; \
7176 TCGv t1; \
7177 t0 = tcg_temp_new_i32(); \
7178 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
7179 gen_helper_##name(t0, t0); \
7180 t1 = tcg_temp_new(); \
7181 tcg_gen_extu_i32_tl(t1, t0); \
7182 tcg_temp_free_i32(t0); \
7183 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
7184 0xFFFFFFFF00000000ULL); \
7185 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
7186 tcg_temp_free(t1); \
0487d6a8 7187}
1c97856d
AJ		 7188#define GEN_SPEFPUOP_CONV_32_64(name) \
7189static always_inline void gen_##name (DisasContext *ctx) \
7190{ \
7191 TCGv_i32 t0; \
7192 TCGv t1; \
7193 t0 = tcg_temp_new_i32(); \
7194 gen_helper_##name(t0, cpu_gpr[rB(ctx->opcode)]); \
7195 t1 = tcg_temp_new(); \
7196 tcg_gen_extu_i32_tl(t1, t0); \
7197 tcg_temp_free_i32(t0); \
7198 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
7199 0xFFFFFFFF00000000ULL); \
7200 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
7201 tcg_temp_free(t1); \
7202}
7203#define GEN_SPEFPUOP_CONV_64_32(name) \
7204static always_inline void gen_##name (DisasContext *ctx) \
7205{ \
7206 TCGv_i32 t0 = tcg_temp_new_i32(); \
7207 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
7208 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], t0); \
7209 tcg_temp_free_i32(t0); \
7210}
7211#define GEN_SPEFPUOP_CONV_64_64(name) \
7212static always_inline void gen_##name (DisasContext *ctx) \
7213{ \
7214 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7215}
7216#define GEN_SPEFPUOP_ARITH2_32_32(name) \
57951c27
AJ		 7217static always_inline void gen_##name (DisasContext *ctx) \
7218{ \
1c97856d
AJ		 7219 TCGv_i32 t0, t1; \
7220 TCGv_i64 t2; \
57951c27
AJ		 7221 if (unlikely(!ctx->spe_enabled)) { \
7222 GEN_EXCP_NO_AP(ctx); \
7223 return; \
7224 } \
1c97856d
AJ		 7225 t0 = tcg_temp_new_i32(); \
7226 t1 = tcg_temp_new_i32(); \
7227 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7228 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
7229 gen_helper_##name(t0, t0, t1); \
7230 tcg_temp_free_i32(t1); \
7231 t2 = tcg_temp_new(); \
7232 tcg_gen_extu_i32_tl(t2, t0); \
7233 tcg_temp_free_i32(t0); \
7234 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
7235 0xFFFFFFFF00000000ULL); \
7236 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t2); \
7237 tcg_temp_free(t2); \
57951c27 7238}
1c97856d 7239#define GEN_SPEFPUOP_ARITH2_64_64(name) \
57951c27
AJ		 7240static always_inline void gen_##name (DisasContext *ctx) \
7241{ \
7242 if (unlikely(!ctx->spe_enabled)) { \
7243 GEN_EXCP_NO_AP(ctx); \
7244 return; \
7245 } \
1c97856d
AJ		 7246 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
7247 cpu_gpr[rB(ctx->opcode)]); \
57951c27 7248}
1c97856d 7249#define GEN_SPEFPUOP_COMP_32(name) \
57951c27
AJ		 7250static always_inline void gen_##name (DisasContext *ctx) \
7251{ \
1c97856d 7252 TCGv_i32 t0, t1; \
57951c27
AJ		 7253 if (unlikely(!ctx->spe_enabled)) { \
7254 GEN_EXCP_NO_AP(ctx); \
7255 return; \
7256 } \
1c97856d
AJ		 7257 t0 = tcg_temp_new_i32(); \
7258 t1 = tcg_temp_new_i32(); \
7259 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7260 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
7261 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], t0, t1); \
7262 tcg_temp_free_i32(t0); \
7263 tcg_temp_free_i32(t1); \
7264}
7265#define GEN_SPEFPUOP_COMP_64(name) \
7266static always_inline void gen_##name (DisasContext *ctx) \
7267{ \
7268 if (unlikely(!ctx->spe_enabled)) { \
7269 GEN_EXCP_NO_AP(ctx); \
7270 return; \
7271 } \
7272 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
7273 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7274}
7275#else
7276#define GEN_SPEFPUOP_CONV_32_32(name) \
7277static always_inline void gen_##name (DisasContext *ctx) \
7278{ \
7279 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
57951c27 7280}
1c97856d
AJ		 7281#define GEN_SPEFPUOP_CONV_32_64(name) \
7282static always_inline void gen_##name (DisasContext *ctx) \
7283{ \
7284 TCGv_i64 t0 = tcg_temp_new_i64(); \
7285 gen_load_gpr64(t0, rB(ctx->opcode)); \
7286 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], t0); \
7287 tcg_temp_free_i64(t0); \
7288}
7289#define GEN_SPEFPUOP_CONV_64_32(name) \
7290static always_inline void gen_##name (DisasContext *ctx) \
7291{ \
7292 TCGv_i64 t0 = tcg_temp_new_i64(); \
7293 gen_helper_##name(t0, cpu_gpr[rB(ctx->opcode)]); \
7294 gen_store_gpr64(rD(ctx->opcode), t0); \
7295 tcg_temp_free_i64(t0); \
7296}
7297#define GEN_SPEFPUOP_CONV_64_64(name) \
7298static always_inline void gen_##name (DisasContext *ctx) \
7299{ \
7300 TCGv_i64 t0 = tcg_temp_new_i64(); \
7301 gen_load_gpr64(t0, rB(ctx->opcode)); \
7302 gen_helper_##name(t0, t0); \
7303 gen_store_gpr64(rD(ctx->opcode), t0); \
7304 tcg_temp_free_i64(t0); \
7305}
7306#define GEN_SPEFPUOP_ARITH2_32_32(name) \
7307static always_inline void gen_##name (DisasContext *ctx) \
7308{ \
7309 if (unlikely(!ctx->spe_enabled)) { \
7310 GEN_EXCP_NO_AP(ctx); \
7311 return; \
7312 } \
7313 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], \
7314 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7315}
7316#define GEN_SPEFPUOP_ARITH2_64_64(name) \
7317static always_inline void gen_##name (DisasContext *ctx) \
7318{ \
7319 TCGv_i64 t0, t1; \
7320 if (unlikely(!ctx->spe_enabled)) { \
7321 GEN_EXCP_NO_AP(ctx); \
7322 return; \
7323 } \
7324 t0 = tcg_temp_new_i64(); \
7325 t1 = tcg_temp_new_i64(); \
7326 gen_load_gpr64(t0, rA(ctx->opcode)); \
7327 gen_load_gpr64(t1, rB(ctx->opcode)); \
7328 gen_helper_##name(t0, t0, t1); \
7329 gen_store_gpr64(rD(ctx->opcode), t0); \
7330 tcg_temp_free_i64(t0); \
7331 tcg_temp_free_i64(t1); \
7332}
7333#define GEN_SPEFPUOP_COMP_32(name) \
7334static always_inline void gen_##name (DisasContext *ctx) \
7335{ \
7336 if (unlikely(!ctx->spe_enabled)) { \
7337 GEN_EXCP_NO_AP(ctx); \
7338 return; \
7339 } \
7340 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
7341 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7342}
7343#define GEN_SPEFPUOP_COMP_64(name) \
7344static always_inline void gen_##name (DisasContext *ctx) \
7345{ \
7346 TCGv_i64 t0, t1; \
7347 if (unlikely(!ctx->spe_enabled)) { \
7348 GEN_EXCP_NO_AP(ctx); \
7349 return; \
7350 } \
7351 t0 = tcg_temp_new_i64(); \
7352 t1 = tcg_temp_new_i64(); \
7353 gen_load_gpr64(t0, rA(ctx->opcode)); \
7354 gen_load_gpr64(t1, rB(ctx->opcode)); \
7355 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], t0, t1); \
7356 tcg_temp_free_i64(t0); \
7357 tcg_temp_free_i64(t1); \
7358}
7359#endif
57951c27 7360
0487d6a8
JM		 7361/* Single precision floating-point vectors operations */
7362/* Arithmetic */
1c97856d
AJ		 7363GEN_SPEFPUOP_ARITH2_64_64(evfsadd);
7364GEN_SPEFPUOP_ARITH2_64_64(evfssub);
7365GEN_SPEFPUOP_ARITH2_64_64(evfsmul);
7366GEN_SPEFPUOP_ARITH2_64_64(evfsdiv);
7367static always_inline void gen_evfsabs (DisasContext *ctx)
7368{
7369 if (unlikely(!ctx->spe_enabled)) {
7370 GEN_EXCP_NO_AP(ctx);
7371 return;
7372 }
7373#if defined(TARGET_PPC64)
7374 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000080000000LL);
7375#else
7376 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x80000000);
7377 tcg_gen_andi_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
7378#endif
7379}
7380static always_inline void gen_evfsnabs (DisasContext *ctx)
7381{
7382 if (unlikely(!ctx->spe_enabled)) {
7383 GEN_EXCP_NO_AP(ctx);
7384 return;
7385 }
7386#if defined(TARGET_PPC64)
7387 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
7388#else
7389 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7390 tcg_gen_ori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
7391#endif
7392}
7393static always_inline void gen_evfsneg (DisasContext *ctx)
7394{
7395 if (unlikely(!ctx->spe_enabled)) {
7396 GEN_EXCP_NO_AP(ctx);
7397 return;
7398 }
7399#if defined(TARGET_PPC64)
7400 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
7401#else
7402 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7403 tcg_gen_xori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
7404#endif
7405}
7406
0487d6a8 7407/* Conversion */
1c97856d
AJ		 7408GEN_SPEFPUOP_CONV_64_64(evfscfui);
7409GEN_SPEFPUOP_CONV_64_64(evfscfsi);
7410GEN_SPEFPUOP_CONV_64_64(evfscfuf);
7411GEN_SPEFPUOP_CONV_64_64(evfscfsf);
7412GEN_SPEFPUOP_CONV_64_64(evfsctui);
7413GEN_SPEFPUOP_CONV_64_64(evfsctsi);
7414GEN_SPEFPUOP_CONV_64_64(evfsctuf);
7415GEN_SPEFPUOP_CONV_64_64(evfsctsf);
7416GEN_SPEFPUOP_CONV_64_64(evfsctuiz);
7417GEN_SPEFPUOP_CONV_64_64(evfsctsiz);
7418
0487d6a8 7419/* Comparison */
1c97856d
AJ		 7420GEN_SPEFPUOP_COMP_64(evfscmpgt);
7421GEN_SPEFPUOP_COMP_64(evfscmplt);
7422GEN_SPEFPUOP_COMP_64(evfscmpeq);
7423GEN_SPEFPUOP_COMP_64(evfststgt);
7424GEN_SPEFPUOP_COMP_64(evfststlt);
7425GEN_SPEFPUOP_COMP_64(evfststeq);
0487d6a8
JM		 7426
7427/* Opcodes definitions */
7428GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, PPC_SPEFPU); //
7429GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, PPC_SPEFPU); //
7430GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, PPC_SPEFPU); //
7431GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, PPC_SPEFPU); //
7432GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, PPC_SPEFPU); //
7433GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, PPC_SPEFPU); //
7434GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, PPC_SPEFPU); //
7435GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, PPC_SPEFPU); //
7436GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, PPC_SPEFPU); //
7437GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, PPC_SPEFPU); //
7438GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, PPC_SPEFPU); //
7439GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, PPC_SPEFPU); //
7440GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, PPC_SPEFPU); //
7441GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, PPC_SPEFPU); //
7442
7443/* Single precision floating-point operations */
7444/* Arithmetic */
1c97856d
AJ		 7445GEN_SPEFPUOP_ARITH2_32_32(efsadd);
7446GEN_SPEFPUOP_ARITH2_32_32(efssub);
7447GEN_SPEFPUOP_ARITH2_32_32(efsmul);
7448GEN_SPEFPUOP_ARITH2_32_32(efsdiv);
7449static always_inline void gen_efsabs (DisasContext *ctx)
7450{
7451 if (unlikely(!ctx->spe_enabled)) {
7452 GEN_EXCP_NO_AP(ctx);
7453 return;
7454 }
7455 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL);
7456}
7457static always_inline void gen_efsnabs (DisasContext *ctx)
7458{
7459 if (unlikely(!ctx->spe_enabled)) {
7460 GEN_EXCP_NO_AP(ctx);
7461 return;
7462 }
7463 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7464}
7465static always_inline void gen_efsneg (DisasContext *ctx)
7466{
7467 if (unlikely(!ctx->spe_enabled)) {
7468 GEN_EXCP_NO_AP(ctx);
7469 return;
7470 }
7471 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7472}
7473
0487d6a8 7474/* Conversion */
1c97856d
AJ		 7475GEN_SPEFPUOP_CONV_32_32(efscfui);
7476GEN_SPEFPUOP_CONV_32_32(efscfsi);
7477GEN_SPEFPUOP_CONV_32_32(efscfuf);
7478GEN_SPEFPUOP_CONV_32_32(efscfsf);
7479GEN_SPEFPUOP_CONV_32_32(efsctui);
7480GEN_SPEFPUOP_CONV_32_32(efsctsi);
7481GEN_SPEFPUOP_CONV_32_32(efsctuf);
7482GEN_SPEFPUOP_CONV_32_32(efsctsf);
7483GEN_SPEFPUOP_CONV_32_32(efsctuiz);
7484GEN_SPEFPUOP_CONV_32_32(efsctsiz);
7485GEN_SPEFPUOP_CONV_32_64(efscfd);
7486
0487d6a8 7487/* Comparison */
1c97856d
AJ		 7488GEN_SPEFPUOP_COMP_32(efscmpgt);
7489GEN_SPEFPUOP_COMP_32(efscmplt);
7490GEN_SPEFPUOP_COMP_32(efscmpeq);
7491GEN_SPEFPUOP_COMP_32(efststgt);
7492GEN_SPEFPUOP_COMP_32(efststlt);
7493GEN_SPEFPUOP_COMP_32(efststeq);
0487d6a8
JM		 7494
7495/* Opcodes definitions */
05332d70 7496GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, PPC_SPEFPU); //
0487d6a8
JM		 7497GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, PPC_SPEFPU); //
7498GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, PPC_SPEFPU); //
7499GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, PPC_SPEFPU); //
7500GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, PPC_SPEFPU); //
7501GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, PPC_SPEFPU); //
7502GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, PPC_SPEFPU); //
7503GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, PPC_SPEFPU); //
7504GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, PPC_SPEFPU); //
7505GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, PPC_SPEFPU); //
9ceb2a77
TS		 7506GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, PPC_SPEFPU); //
7507GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, PPC_SPEFPU); //
0487d6a8
JM		 7508GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, PPC_SPEFPU); //
7509GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, PPC_SPEFPU); //
7510
7511/* Double precision floating-point operations */
7512/* Arithmetic */
1c97856d
AJ		 7513GEN_SPEFPUOP_ARITH2_64_64(efdadd);
7514GEN_SPEFPUOP_ARITH2_64_64(efdsub);
7515GEN_SPEFPUOP_ARITH2_64_64(efdmul);
7516GEN_SPEFPUOP_ARITH2_64_64(efddiv);
7517static always_inline void gen_efdabs (DisasContext *ctx)
7518{
7519 if (unlikely(!ctx->spe_enabled)) {
7520 GEN_EXCP_NO_AP(ctx);
7521 return;
7522 }
7523#if defined(TARGET_PPC64)
7524 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000000000000LL);
7525#else
7526 tcg_gen_andi_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
7527#endif
7528}
7529static always_inline void gen_efdnabs (DisasContext *ctx)
7530{
7531 if (unlikely(!ctx->spe_enabled)) {
7532 GEN_EXCP_NO_AP(ctx);
7533 return;
7534 }
7535#if defined(TARGET_PPC64)
7536 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
7537#else
7538 tcg_gen_ori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
7539#endif
7540}
7541static always_inline void gen_efdneg (DisasContext *ctx)
7542{
7543 if (unlikely(!ctx->spe_enabled)) {
7544 GEN_EXCP_NO_AP(ctx);
7545 return;
7546 }
7547#if defined(TARGET_PPC64)
7548 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
7549#else
7550 tcg_gen_xori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
7551#endif
7552}
7553
0487d6a8 7554/* Conversion */
1c97856d
AJ		 7555GEN_SPEFPUOP_CONV_64_32(efdcfui);
7556GEN_SPEFPUOP_CONV_64_32(efdcfsi);
7557GEN_SPEFPUOP_CONV_64_32(efdcfuf);
7558GEN_SPEFPUOP_CONV_64_32(efdcfsf);
7559GEN_SPEFPUOP_CONV_32_64(efdctui);
7560GEN_SPEFPUOP_CONV_32_64(efdctsi);
7561GEN_SPEFPUOP_CONV_32_64(efdctuf);
7562GEN_SPEFPUOP_CONV_32_64(efdctsf);
7563GEN_SPEFPUOP_CONV_32_64(efdctuiz);
7564GEN_SPEFPUOP_CONV_32_64(efdctsiz);
7565GEN_SPEFPUOP_CONV_64_32(efdcfs);
7566GEN_SPEFPUOP_CONV_64_64(efdcfuid);
7567GEN_SPEFPUOP_CONV_64_64(efdcfsid);
7568GEN_SPEFPUOP_CONV_64_64(efdctuidz);
7569GEN_SPEFPUOP_CONV_64_64(efdctsidz);
0487d6a8 7570
0487d6a8 7571/* Comparison */
1c97856d
AJ		 7572GEN_SPEFPUOP_COMP_64(efdcmpgt);
7573GEN_SPEFPUOP_COMP_64(efdcmplt);
7574GEN_SPEFPUOP_COMP_64(efdcmpeq);
7575GEN_SPEFPUOP_COMP_64(efdtstgt);
7576GEN_SPEFPUOP_COMP_64(efdtstlt);
7577GEN_SPEFPUOP_COMP_64(efdtsteq);
0487d6a8
JM		 7578
7579/* Opcodes definitions */
7580GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, PPC_SPEFPU); //
7581GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, PPC_SPEFPU); //
7582GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, PPC_SPEFPU); //
7583GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, PPC_SPEFPU); //
7584GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, PPC_SPEFPU); //
7585GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, PPC_SPEFPU); //
7586GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, PPC_SPEFPU); //
7587GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, PPC_SPEFPU); //
7588GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, PPC_SPEFPU); //
7589GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, PPC_SPEFPU); //
7590GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, PPC_SPEFPU); //
7591GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, PPC_SPEFPU); //
7592GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, PPC_SPEFPU); //
7593GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, PPC_SPEFPU); //
7594GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, PPC_SPEFPU); //
7595GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, PPC_SPEFPU); //
0487d6a8 7596
79aceca5
FB		 7597/* End opcode list */
7598GEN_OPCODE_MARK(end);
7599
3fc6c082 7600#include "translate_init.c"
0411a972 7601#include "helper_regs.h"
79aceca5 7602
9a64fbe4 7603/*****************************************************************************/
3fc6c082 7604/* Misc PowerPC helpers */
36081602
JM		 7605void cpu_dump_state (CPUState *env, FILE *f,
7606 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
7607 int flags)
79aceca5 7608{
3fc6c082
FB		 7609#define RGPL 4
7610#define RFPL 4
3fc6c082 7611
79aceca5
FB		 7612 int i;
7613
077fc206 7614 cpu_fprintf(f, "NIP " ADDRX " LR " ADDRX " CTR " ADDRX " XER %08x\n",
3d7b417e 7615 env->nip, env->lr, env->ctr, env->xer);
6b542af7
JM		 7616 cpu_fprintf(f, "MSR " ADDRX " HID0 " ADDRX " HF " ADDRX " idx %d\n",
7617 env->msr, env->spr[SPR_HID0], env->hflags, env->mmu_idx);
d9bce9d9 7618#if !defined(NO_TIMER_DUMP)
077fc206 7619 cpu_fprintf(f, "TB %08x %08x "
76a66253
JM		 7620#if !defined(CONFIG_USER_ONLY)
7621 "DECR %08x"
7622#endif
7623 "\n",
077fc206 7624 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
76a66253
JM		 7625#if !defined(CONFIG_USER_ONLY)
7626 , cpu_ppc_load_decr(env)
7627#endif
7628 );
077fc206 7629#endif
76a66253 7630 for (i = 0; i < 32; i++) {
3fc6c082
FB		 7631 if ((i & (RGPL - 1)) == 0)
7632 cpu_fprintf(f, "GPR%02d", i);
6b542af7 7633 cpu_fprintf(f, " " REGX, ppc_dump_gpr(env, i));
3fc6c082 7634 if ((i & (RGPL - 1)) == (RGPL - 1))
7fe48483 7635 cpu_fprintf(f, "\n");
76a66253 7636 }
3fc6c082 7637 cpu_fprintf(f, "CR ");
76a66253 7638 for (i = 0; i < 8; i++)
7fe48483
FB		 7639 cpu_fprintf(f, "%01x", env->crf[i]);
7640 cpu_fprintf(f, " [");
76a66253
JM		 7641 for (i = 0; i < 8; i++) {
7642 char a = '-';
7643 if (env->crf[i] & 0x08)
7644 a = 'L';
7645 else if (env->crf[i] & 0x04)
7646 a = 'G';
7647 else if (env->crf[i] & 0x02)
7648 a = 'E';
7fe48483 7649 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
76a66253 7650 }
6b542af7 7651 cpu_fprintf(f, " ] RES " ADDRX "\n", env->reserve);
3fc6c082
FB		 7652 for (i = 0; i < 32; i++) {
7653 if ((i & (RFPL - 1)) == 0)
7654 cpu_fprintf(f, "FPR%02d", i);
26a76461 7655 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
3fc6c082 7656 if ((i & (RFPL - 1)) == (RFPL - 1))
7fe48483 7657 cpu_fprintf(f, "\n");
79aceca5 7658 }
f2e63a42 7659#if !defined(CONFIG_USER_ONLY)
6b542af7 7660 cpu_fprintf(f, "SRR0 " ADDRX " SRR1 " ADDRX " SDR1 " ADDRX "\n",
3fc6c082 7661 env->spr[SPR_SRR0], env->spr[SPR_SRR1], env->sdr1);
f2e63a42 7662#endif
79aceca5 7663
3fc6c082
FB		 7664#undef RGPL
7665#undef RFPL
79aceca5
FB		 7666}
7667
76a66253
JM		 7668void cpu_dump_statistics (CPUState *env, FILE*f,
7669 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
7670 int flags)
7671{
7672#if defined(DO_PPC_STATISTICS)
7673 opc_handler_t **t1, **t2, **t3, *handler;
7674 int op1, op2, op3;
7675
7676 t1 = env->opcodes;
7677 for (op1 = 0; op1 < 64; op1++) {
7678 handler = t1[op1];
7679 if (is_indirect_opcode(handler)) {
7680 t2 = ind_table(handler);
7681 for (op2 = 0; op2 < 32; op2++) {
7682 handler = t2[op2];
7683 if (is_indirect_opcode(handler)) {
7684 t3 = ind_table(handler);
7685 for (op3 = 0; op3 < 32; op3++) {
7686 handler = t3[op3];
7687 if (handler->count == 0)
7688 continue;
7689 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
7690 "%016llx %lld\n",
7691 op1, op2, op3, op1, (op3 << 5) | op2,
7692 handler->oname,
7693 handler->count, handler->count);
7694 }
7695 } else {
7696 if (handler->count == 0)
7697 continue;
7698 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
7699 "%016llx %lld\n",
7700 op1, op2, op1, op2, handler->oname,
7701 handler->count, handler->count);
7702 }
7703 }
7704 } else {
7705 if (handler->count == 0)
7706 continue;
7707 cpu_fprintf(f, "%02x (%02x ) %16s: %016llx %lld\n",
7708 op1, op1, handler->oname,
7709 handler->count, handler->count);
7710 }
7711 }
7712#endif
7713}
7714
9a64fbe4 7715/*****************************************************************************/
2cfc5f17
TS		 7716static always_inline void gen_intermediate_code_internal (CPUState *env,
7717 TranslationBlock *tb,
7718 int search_pc)
79aceca5 7719{
9fddaa0c 7720 DisasContext ctx, *ctxp = &ctx;
79aceca5 7721 opc_handler_t **table, *handler;
0fa85d43 7722 target_ulong pc_start;
79aceca5 7723 uint16_t *gen_opc_end;
056401ea 7724 int supervisor, little_endian;
a1d1bb31 7725 CPUBreakpoint *bp;
79aceca5 7726 int j, lj = -1;
2e70f6ef
PB		 7727 int num_insns;
7728 int max_insns;
79aceca5
FB		 7729
7730 pc_start = tb->pc;
79aceca5 7731 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
7c58044c
JM		 7732#if defined(OPTIMIZE_FPRF_UPDATE)
7733 gen_fprf_ptr = gen_fprf_buf;
7734#endif
046d6672 7735 ctx.nip = pc_start;
79aceca5 7736 ctx.tb = tb;
e1833e1f 7737 ctx.exception = POWERPC_EXCP_NONE;
3fc6c082 7738 ctx.spr_cb = env->spr_cb;
6ebbf390
JM		 7739 supervisor = env->mmu_idx;
7740#if !defined(CONFIG_USER_ONLY)
2857068e 7741 ctx.supervisor = supervisor;
d9bce9d9 7742#endif
056401ea 7743 little_endian = env->hflags & (1 << MSR_LE) ? 1 : 0;
d9bce9d9
JM		 7744#if defined(TARGET_PPC64)
7745 ctx.sf_mode = msr_sf;
056401ea 7746 ctx.mem_idx = (supervisor << 2) | (msr_sf << 1) | little_endian;
2857068e 7747#else
056401ea 7748 ctx.mem_idx = (supervisor << 1) | little_endian;
9a64fbe4 7749#endif
3cc62370 7750 ctx.fpu_enabled = msr_fp;
a9d9eb8f 7751 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
d26bfc9a
JM		 7752 ctx.spe_enabled = msr_spe;
7753 else
7754 ctx.spe_enabled = 0;
a9d9eb8f
JM		 7755 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
7756 ctx.altivec_enabled = msr_vr;
7757 else
7758 ctx.altivec_enabled = 0;
d26bfc9a 7759 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
8cbcb4fa 7760 ctx.singlestep_enabled = CPU_SINGLE_STEP;
d26bfc9a 7761 else
8cbcb4fa 7762 ctx.singlestep_enabled = 0;
d26bfc9a 7763 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
8cbcb4fa
AJ		 7764 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
7765 if (unlikely(env->singlestep_enabled))
7766 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
3fc6c082 7767#if defined (DO_SINGLE_STEP) && 0
9a64fbe4
FB		 7768 /* Single step trace mode */
7769 msr_se = 1;
7770#endif
2e70f6ef
PB		 7771 num_insns = 0;
7772 max_insns = tb->cflags & CF_COUNT_MASK;
7773 if (max_insns == 0)
7774 max_insns = CF_COUNT_MASK;
7775
7776 gen_icount_start();
9a64fbe4 7777 /* Set env in case of segfault during code fetch */
e1833e1f 7778 while (ctx.exception == POWERPC_EXCP_NONE && gen_opc_ptr < gen_opc_end) {
c0ce998e
AL		 7779 if (unlikely(!TAILQ_EMPTY(&env->breakpoints))) {
7780 TAILQ_FOREACH(bp, &env->breakpoints, entry) {
a1d1bb31 7781 if (bp->pc == ctx.nip) {
5fafdf24 7782 gen_update_nip(&ctx, ctx.nip);
64adab3f 7783 gen_helper_raise_debug();
ea4e754f
FB		 7784 break;
7785 }
7786 }
7787 }
76a66253 7788 if (unlikely(search_pc)) {
79aceca5
FB		 7789 j = gen_opc_ptr - gen_opc_buf;
7790 if (lj < j) {
7791 lj++;
7792 while (lj < j)
7793 gen_opc_instr_start[lj++] = 0;
046d6672 7794 gen_opc_pc[lj] = ctx.nip;
79aceca5 7795 gen_opc_instr_start[lj] = 1;
2e70f6ef 7796 gen_opc_icount[lj] = num_insns;
79aceca5
FB		 7797 }
7798 }
9fddaa0c
FB		 7799#if defined PPC_DEBUG_DISAS
7800 if (loglevel & CPU_LOG_TB_IN_ASM) {
79aceca5 7801 fprintf(logfile, "----------------\n");
1b9eb036 7802 fprintf(logfile, "nip=" ADDRX " super=%d ir=%d\n",
0411a972 7803 ctx.nip, supervisor, (int)msr_ir);
9a64fbe4
FB		 7804 }
7805#endif
2e70f6ef
PB		 7806 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
7807 gen_io_start();
056401ea
JM		 7808 if (unlikely(little_endian)) {
7809 ctx.opcode = bswap32(ldl_code(ctx.nip));
7810 } else {
7811 ctx.opcode = ldl_code(ctx.nip);
111bfab3 7812 }
9fddaa0c
FB		 7813#if defined PPC_DEBUG_DISAS
7814 if (loglevel & CPU_LOG_TB_IN_ASM) {
111bfab3 7815 fprintf(logfile, "translate opcode %08x (%02x %02x %02x) (%s)\n",
9a64fbe4 7816 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
056401ea 7817 opc3(ctx.opcode), little_endian ? "little" : "big");
79aceca5
FB		 7818 }
7819#endif
046d6672 7820 ctx.nip += 4;
3fc6c082 7821 table = env->opcodes;
2e70f6ef 7822 num_insns++;
79aceca5
FB		 7823 handler = table[opc1(ctx.opcode)];
7824 if (is_indirect_opcode(handler)) {
7825 table = ind_table(handler);
7826 handler = table[opc2(ctx.opcode)];
7827 if (is_indirect_opcode(handler)) {
7828 table = ind_table(handler);
7829 handler = table[opc3(ctx.opcode)];
7830 }
7831 }
7832 /* Is opcode *REALLY* valid ? */
76a66253 7833 if (unlikely(handler->handler == &gen_invalid)) {
4a057712 7834 if (loglevel != 0) {
76a66253 7835 fprintf(logfile, "invalid/unsupported opcode: "
6b542af7 7836 "%02x - %02x - %02x (%08x) " ADDRX " %d\n",
76a66253 7837 opc1(ctx.opcode), opc2(ctx.opcode),
0411a972 7838 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
4b3686fa
FB		 7839 } else {
7840 printf("invalid/unsupported opcode: "
6b542af7 7841 "%02x - %02x - %02x (%08x) " ADDRX " %d\n",
4b3686fa 7842 opc1(ctx.opcode), opc2(ctx.opcode),
0411a972 7843 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
4b3686fa 7844 }
76a66253
JM		 7845 } else {
7846 if (unlikely((ctx.opcode & handler->inval) != 0)) {
4a057712 7847 if (loglevel != 0) {
79aceca5 7848 fprintf(logfile, "invalid bits: %08x for opcode: "
6b542af7 7849 "%02x - %02x - %02x (%08x) " ADDRX "\n",
79aceca5
FB		 7850 ctx.opcode & handler->inval, opc1(ctx.opcode),
7851 opc2(ctx.opcode), opc3(ctx.opcode),
046d6672 7852 ctx.opcode, ctx.nip - 4);
9a64fbe4
FB		 7853 } else {
7854 printf("invalid bits: %08x for opcode: "
6b542af7 7855 "%02x - %02x - %02x (%08x) " ADDRX "\n",
76a66253
JM		 7856 ctx.opcode & handler->inval, opc1(ctx.opcode),
7857 opc2(ctx.opcode), opc3(ctx.opcode),
046d6672 7858 ctx.opcode, ctx.nip - 4);
76a66253 7859 }
e1833e1f 7860 GEN_EXCP_INVAL(ctxp);
4b3686fa 7861 break;
79aceca5 7862 }
79aceca5 7863 }
4b3686fa 7864 (*(handler->handler))(&ctx);
76a66253
JM		 7865#if defined(DO_PPC_STATISTICS)
7866 handler->count++;
7867#endif
9a64fbe4 7868 /* Check trace mode exceptions */
8cbcb4fa
AJ		 7869 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
7870 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
7871 ctx.exception != POWERPC_SYSCALL &&
7872 ctx.exception != POWERPC_EXCP_TRAP &&
7873 ctx.exception != POWERPC_EXCP_BRANCH)) {
e1833e1f 7874 GEN_EXCP(ctxp, POWERPC_EXCP_TRACE, 0);
d26bfc9a 7875 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
2e70f6ef
PB		 7876 (env->singlestep_enabled) ||
7877 num_insns >= max_insns)) {
d26bfc9a
JM		 7878 /* if we reach a page boundary or are single stepping, stop
7879 * generation
7880 */
8dd4983c 7881 break;
76a66253 7882 }
3fc6c082
FB		 7883#if defined (DO_SINGLE_STEP)
7884 break;
7885#endif
7886 }
2e70f6ef
PB		 7887 if (tb->cflags & CF_LAST_IO)
7888 gen_io_end();
e1833e1f 7889 if (ctx.exception == POWERPC_EXCP_NONE) {
c1942362 7890 gen_goto_tb(&ctx, 0, ctx.nip);
e1833e1f 7891 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
8cbcb4fa
AJ		 7892 if (unlikely(env->singlestep_enabled)) {
7893 gen_update_nip(&ctx, ctx.nip);
64adab3f 7894 gen_helper_raise_debug();
8cbcb4fa 7895 }
76a66253 7896 /* Generate the return instruction */
57fec1fe 7897 tcg_gen_exit_tb(0);
9a64fbe4 7898 }
2e70f6ef 7899 gen_icount_end(tb, num_insns);
79aceca5 7900 *gen_opc_ptr = INDEX_op_end;
76a66253 7901 if (unlikely(search_pc)) {
9a64fbe4
FB		 7902 j = gen_opc_ptr - gen_opc_buf;
7903 lj++;
7904 while (lj <= j)
7905 gen_opc_instr_start[lj++] = 0;
9a64fbe4 7906 } else {
046d6672 7907 tb->size = ctx.nip - pc_start;
2e70f6ef 7908 tb->icount = num_insns;
9a64fbe4 7909 }
d9bce9d9 7910#if defined(DEBUG_DISAS)
9fddaa0c 7911 if (loglevel & CPU_LOG_TB_CPU) {
9a64fbe4 7912 fprintf(logfile, "---------------- excp: %04x\n", ctx.exception);
7fe48483 7913 cpu_dump_state(env, logfile, fprintf, 0);
9fddaa0c
FB		 7914 }
7915 if (loglevel & CPU_LOG_TB_IN_ASM) {
76a66253 7916 int flags;
237c0af0 7917 flags = env->bfd_mach;
056401ea 7918 flags |= little_endian << 16;
0fa85d43 7919 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
76a66253 7920 target_disas(logfile, pc_start, ctx.nip - pc_start, flags);
79aceca5 7921 fprintf(logfile, "\n");
9fddaa0c 7922 }
79aceca5 7923#endif
79aceca5
FB		 7924}
7925
2cfc5f17 7926void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
79aceca5 7927{
2cfc5f17 7928 gen_intermediate_code_internal(env, tb, 0);
79aceca5
FB		 7929}
7930
2cfc5f17 7931void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
79aceca5 7932{
2cfc5f17 7933 gen_intermediate_code_internal(env, tb, 1);
79aceca5 7934}
d2856f1a
AJ		 7935
7936void gen_pc_load(CPUState *env, TranslationBlock *tb,
7937 unsigned long searched_pc, int pc_pos, void *puc)
7938{
d2856f1a 7939 env->nip = gen_opc_pc[pc_pos];
d2856f1a 7940}
Empty description
This page took 1.551177 seconds and 4 git commands to generate.