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ppc fixes (Jocelyn Mayer)
[qemu.git] / target-ppc / translate.c
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79aceca5
FB		 1/*
2 * PPC emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2003 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
c6a1c22b
FB		 20#include <stdarg.h>
21#include <stdlib.h>
22#include <stdio.h>
23#include <string.h>
24#include <inttypes.h>
25
79aceca5 26#include "cpu.h"
c6a1c22b 27#include "exec-all.h"
79aceca5
FB		 28#include "disas.h"
29
30//#define DO_SINGLE_STEP
9fddaa0c 31//#define PPC_DEBUG_DISAS
79aceca5
FB		 32
33enum {
34#define DEF(s, n, copy_size) INDEX_op_ ## s,
35#include "opc.h"
36#undef DEF
37 NB_OPS,
38};
39
40static uint16_t *gen_opc_ptr;
41static uint32_t *gen_opparam_ptr;
42
43#include "gen-op.h"
28b6751f 44
28b6751f 45#define GEN8(func, NAME) \
9a64fbe4
FB		 46static GenOpFunc *NAME ## _table [8] = { \
47NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
48NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
49}; \
50static inline void func(int n) \
51{ \
52 NAME ## _table[n](); \
53}
54
55#define GEN16(func, NAME) \
56static GenOpFunc *NAME ## _table [16] = { \
57NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
58NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
59NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
60NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
61}; \
62static inline void func(int n) \
63{ \
64 NAME ## _table[n](); \
28b6751f
FB		 65}
66
67#define GEN32(func, NAME) \
9a64fbe4
FB		 68static GenOpFunc *NAME ## _table [32] = { \
69NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
70NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
71NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
72NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
73NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
74NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
75NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
76NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
77}; \
78static inline void func(int n) \
79{ \
80 NAME ## _table[n](); \
81}
82
83/* Condition register moves */
84GEN8(gen_op_load_crf_T0, gen_op_load_crf_T0_crf);
85GEN8(gen_op_load_crf_T1, gen_op_load_crf_T1_crf);
86GEN8(gen_op_store_T0_crf, gen_op_store_T0_crf_crf);
87GEN8(gen_op_store_T1_crf, gen_op_store_T1_crf_crf);
28b6751f 88
fb0eaffc
FB		 89/* Floating point condition and status register moves */
90GEN8(gen_op_load_fpscr_T0, gen_op_load_fpscr_T0_fpscr);
91GEN8(gen_op_store_T0_fpscr, gen_op_store_T0_fpscr_fpscr);
92GEN8(gen_op_clear_fpscr, gen_op_clear_fpscr_fpscr);
93static GenOpFunc1 *gen_op_store_T0_fpscri_fpscr_table[8] = {
94 &gen_op_store_T0_fpscri_fpscr0,
95 &gen_op_store_T0_fpscri_fpscr1,
96 &gen_op_store_T0_fpscri_fpscr2,
97 &gen_op_store_T0_fpscri_fpscr3,
98 &gen_op_store_T0_fpscri_fpscr4,
99 &gen_op_store_T0_fpscri_fpscr5,
100 &gen_op_store_T0_fpscri_fpscr6,
101 &gen_op_store_T0_fpscri_fpscr7,
102};
103static inline void gen_op_store_T0_fpscri(int n, uint8_t param)
104{
105 (*gen_op_store_T0_fpscri_fpscr_table[n])(param);
106}
107
9a64fbe4
FB		 108/* Segment register moves */
109GEN16(gen_op_load_sr, gen_op_load_sr);
110GEN16(gen_op_store_sr, gen_op_store_sr);
28b6751f 111
9a64fbe4
FB		 112/* General purpose registers moves */
113GEN32(gen_op_load_gpr_T0, gen_op_load_gpr_T0_gpr);
114GEN32(gen_op_load_gpr_T1, gen_op_load_gpr_T1_gpr);
115GEN32(gen_op_load_gpr_T2, gen_op_load_gpr_T2_gpr);
116
117GEN32(gen_op_store_T0_gpr, gen_op_store_T0_gpr_gpr);
118GEN32(gen_op_store_T1_gpr, gen_op_store_T1_gpr_gpr);
119GEN32(gen_op_store_T2_gpr, gen_op_store_T2_gpr_gpr);
28b6751f 120
fb0eaffc
FB		 121/* floating point registers moves */
122GEN32(gen_op_load_fpr_FT0, gen_op_load_fpr_FT0_fpr);
123GEN32(gen_op_load_fpr_FT1, gen_op_load_fpr_FT1_fpr);
124GEN32(gen_op_load_fpr_FT2, gen_op_load_fpr_FT2_fpr);
125GEN32(gen_op_store_FT0_fpr, gen_op_store_FT0_fpr_fpr);
126GEN32(gen_op_store_FT1_fpr, gen_op_store_FT1_fpr_fpr);
127GEN32(gen_op_store_FT2_fpr, gen_op_store_FT2_fpr_fpr);
79aceca5
FB		 128
129static uint8_t spr_access[1024 / 2];
130
131/* internal defines */
132typedef struct DisasContext {
133 struct TranslationBlock *tb;
0fa85d43 134 target_ulong nip;
79aceca5 135 uint32_t opcode;
9a64fbe4 136 uint32_t exception;
9a64fbe4
FB		 137 /* Execution mode */
138#if !defined(CONFIG_USER_ONLY)
79aceca5 139 int supervisor;
9a64fbe4
FB		 140#endif
141 /* Routine used to access memory */
142 int mem_idx;
79aceca5
FB		 143} DisasContext;
144
145typedef struct opc_handler_t {
146 /* invalid bits */
147 uint32_t inval;
9a64fbe4
FB		 148 /* instruction type */
149 uint32_t type;
79aceca5
FB		 150 /* handler */
151 void (*handler)(DisasContext *ctx);
152} opc_handler_t;
153
9fddaa0c 154#define RET_EXCP(ctx, excp, error) \
79aceca5 155do { \
9fddaa0c
FB		 156 if ((ctx)->exception == EXCP_NONE) { \
157 gen_op_update_nip((ctx)->nip); \
158 } \
159 gen_op_raise_exception_err((excp), (error)); \
160 ctx->exception = (excp); \
79aceca5
FB		 161} while (0)
162
9fddaa0c
FB		 163#define RET_INVAL(ctx) \
164RET_EXCP((ctx), EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_INVAL)
165
166#define RET_PRIVOPC(ctx) \
167RET_EXCP((ctx), EXCP_PROGRAM, EXCP_INVAL | EXCP_PRIV_OPC)
9a64fbe4 168
9fddaa0c
FB		 169#define RET_PRIVREG(ctx) \
170RET_EXCP((ctx), EXCP_PROGRAM, EXCP_INVAL | EXCP_PRIV_REG)
9a64fbe4 171
9fddaa0c
FB		 172#define RET_MTMSR(ctx) \
173RET_EXCP((ctx), EXCP_MTMSR, 0)
79aceca5
FB		 174
175#define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
176static void gen_##name (DisasContext *ctx); \
177GEN_OPCODE(name, opc1, opc2, opc3, inval, type); \
178static void gen_##name (DisasContext *ctx)
179
79aceca5
FB		 180typedef struct opcode_t {
181 unsigned char opc1, opc2, opc3;
18fba28c
FB		 182#if HOST_LONG_BITS == 64 /* Explicitely align to 64 bits */
183 unsigned char pad[5];
184#else
185 unsigned char pad[1];
186#endif
79aceca5
FB		 187 opc_handler_t handler;
188} opcode_t;
189
79aceca5
FB		 190/*** Instruction decoding ***/
191#define EXTRACT_HELPER(name, shift, nb) \
192static inline uint32_t name (uint32_t opcode) \
193{ \
194 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
195}
196
197#define EXTRACT_SHELPER(name, shift, nb) \
198static inline int32_t name (uint32_t opcode) \
199{ \
18fba28c 200 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
79aceca5
FB		 201}
202
203/* Opcode part 1 */
204EXTRACT_HELPER(opc1, 26, 6);
205/* Opcode part 2 */
206EXTRACT_HELPER(opc2, 1, 5);
207/* Opcode part 3 */
208EXTRACT_HELPER(opc3, 6, 5);
209/* Update Cr0 flags */
210EXTRACT_HELPER(Rc, 0, 1);
211/* Destination */
212EXTRACT_HELPER(rD, 21, 5);
213/* Source */
214EXTRACT_HELPER(rS, 21, 5);
215/* First operand */
216EXTRACT_HELPER(rA, 16, 5);
217/* Second operand */
218EXTRACT_HELPER(rB, 11, 5);
219/* Third operand */
220EXTRACT_HELPER(rC, 6, 5);
221/*** Get CRn ***/
222EXTRACT_HELPER(crfD, 23, 3);
223EXTRACT_HELPER(crfS, 18, 3);
224EXTRACT_HELPER(crbD, 21, 5);
225EXTRACT_HELPER(crbA, 16, 5);
226EXTRACT_HELPER(crbB, 11, 5);
227/* SPR / TBL */
228EXTRACT_HELPER(SPR, 11, 10);
229/*** Get constants ***/
230EXTRACT_HELPER(IMM, 12, 8);
231/* 16 bits signed immediate value */
232EXTRACT_SHELPER(SIMM, 0, 16);
233/* 16 bits unsigned immediate value */
234EXTRACT_HELPER(UIMM, 0, 16);
235/* Bit count */
236EXTRACT_HELPER(NB, 11, 5);
237/* Shift count */
238EXTRACT_HELPER(SH, 11, 5);
239/* Mask start */
240EXTRACT_HELPER(MB, 6, 5);
241/* Mask end */
242EXTRACT_HELPER(ME, 1, 5);
fb0eaffc
FB		 243/* Trap operand */
244EXTRACT_HELPER(TO, 21, 5);
79aceca5
FB		 245
246EXTRACT_HELPER(CRM, 12, 8);
247EXTRACT_HELPER(FM, 17, 8);
248EXTRACT_HELPER(SR, 16, 4);
fb0eaffc
FB		 249EXTRACT_HELPER(FPIMM, 20, 4);
250
79aceca5
FB		 251/*** Jump target decoding ***/
252/* Displacement */
253EXTRACT_SHELPER(d, 0, 16);
254/* Immediate address */
255static inline uint32_t LI (uint32_t opcode)
256{
257 return (opcode >> 0) & 0x03FFFFFC;
258}
259
260static inline uint32_t BD (uint32_t opcode)
261{
262 return (opcode >> 0) & 0xFFFC;
263}
264
265EXTRACT_HELPER(BO, 21, 5);
266EXTRACT_HELPER(BI, 16, 5);
267/* Absolute/relative address */
268EXTRACT_HELPER(AA, 1, 1);
269/* Link */
270EXTRACT_HELPER(LK, 0, 1);
271
272/* Create a mask between <start> and <end> bits */
273static inline uint32_t MASK (uint32_t start, uint32_t end)
274{
275 uint32_t ret;
276
277 ret = (((uint32_t)(-1)) >> (start)) ^ (((uint32_t)(-1) >> (end)) >> 1);
278 if (start > end)
279 return ~ret;
280
281 return ret;
282}
283
1b039c09 284#if defined(__APPLE__)
933dc6eb 285#define OPCODES_SECTION \
1b039c09 286 __attribute__ ((section("__TEXT,__opcodes"), unused, aligned (8) ))
933dc6eb 287#else
1b039c09
FB		 288#define OPCODES_SECTION \
289 __attribute__ ((section(".opcodes"), unused, aligned (8) ))
933dc6eb
FB		 290#endif
291
79aceca5 292#define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
18fba28c 293OPCODES_SECTION opcode_t opc_##name = { \
79aceca5
FB		 294 .opc1 = op1, \
295 .opc2 = op2, \
296 .opc3 = op3, \
18fba28c 297 .pad = { 0, }, \
79aceca5
FB		 298 .handler = { \
299 .inval = invl, \
9a64fbe4 300 .type = _typ, \
79aceca5
FB		 301 .handler = &gen_##name, \
302 }, \
303}
304
305#define GEN_OPCODE_MARK(name) \
18fba28c 306OPCODES_SECTION opcode_t opc_##name = { \
79aceca5
FB		 307 .opc1 = 0xFF, \
308 .opc2 = 0xFF, \
309 .opc3 = 0xFF, \
18fba28c 310 .pad = { 0, }, \
79aceca5
FB		 311 .handler = { \
312 .inval = 0x00000000, \
9a64fbe4 313 .type = 0x00, \
79aceca5
FB		 314 .handler = NULL, \
315 }, \
316}
317
318/* Start opcode list */
319GEN_OPCODE_MARK(start);
320
321/* Invalid instruction */
9a64fbe4
FB		 322GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE)
323{
9fddaa0c 324 RET_INVAL(ctx);
9a64fbe4
FB		 325}
326
327/* Special opcode to stop emulation */
328GEN_HANDLER(stop, 0x06, 0x00, 0xFF, 0x03FFFFC1, PPC_COMMON)
79aceca5 329{
9fddaa0c 330 RET_EXCP(ctx, EXCP_HLT, 0);
9a64fbe4
FB		 331}
332
333/* Special opcode to call open-firmware */
334GEN_HANDLER(of_enter, 0x06, 0x01, 0xFF, 0x03FFFFC1, PPC_COMMON)
335{
9fddaa0c 336 RET_EXCP(ctx, EXCP_OFCALL, 0);
9a64fbe4
FB		 337}
338
339/* Special opcode to call RTAS */
340GEN_HANDLER(rtas_enter, 0x06, 0x02, 0xFF, 0x03FFFFC1, PPC_COMMON)
341{
342 printf("RTAS entry point !\n");
9fddaa0c 343 RET_EXCP(ctx, EXCP_RTASCALL, 0);
79aceca5
FB		 344}
345
346static opc_handler_t invalid_handler = {
347 .inval = 0xFFFFFFFF,
9a64fbe4 348 .type = PPC_NONE,
79aceca5
FB		 349 .handler = gen_invalid,
350};
351
352/*** Integer arithmetic ***/
353#define __GEN_INT_ARITH2(name, opc1, opc2, opc3, inval) \
354GEN_HANDLER(name, opc1, opc2, opc3, inval, PPC_INTEGER) \
355{ \
356 gen_op_load_gpr_T0(rA(ctx->opcode)); \
357 gen_op_load_gpr_T1(rB(ctx->opcode)); \
358 gen_op_##name(); \
359 if (Rc(ctx->opcode) != 0) \
360 gen_op_set_Rc0(); \
361 gen_op_store_T0_gpr(rD(ctx->opcode)); \
79aceca5
FB		 362}
363
364#define __GEN_INT_ARITH2_O(name, opc1, opc2, opc3, inval) \
365GEN_HANDLER(name, opc1, opc2, opc3, inval, PPC_INTEGER) \
366{ \
367 gen_op_load_gpr_T0(rA(ctx->opcode)); \
368 gen_op_load_gpr_T1(rB(ctx->opcode)); \
369 gen_op_##name(); \
370 if (Rc(ctx->opcode) != 0) \
18fba28c 371 gen_op_set_Rc0(); \
79aceca5 372 gen_op_store_T0_gpr(rD(ctx->opcode)); \
79aceca5
FB		 373}
374
375#define __GEN_INT_ARITH1(name, opc1, opc2, opc3) \
376GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, PPC_INTEGER) \
377{ \
378 gen_op_load_gpr_T0(rA(ctx->opcode)); \
379 gen_op_##name(); \
380 if (Rc(ctx->opcode) != 0) \
381 gen_op_set_Rc0(); \
382 gen_op_store_T0_gpr(rD(ctx->opcode)); \
79aceca5
FB		 383}
384#define __GEN_INT_ARITH1_O(name, opc1, opc2, opc3) \
385GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, PPC_INTEGER) \
386{ \
387 gen_op_load_gpr_T0(rA(ctx->opcode)); \
388 gen_op_##name(); \
389 if (Rc(ctx->opcode) != 0) \
18fba28c 390 gen_op_set_Rc0(); \
79aceca5 391 gen_op_store_T0_gpr(rD(ctx->opcode)); \
79aceca5
FB		 392}
393
394/* Two operands arithmetic functions */
395#define GEN_INT_ARITH2(name, opc1, opc2, opc3) \
396__GEN_INT_ARITH2(name, opc1, opc2, opc3, 0x00000000) \
397__GEN_INT_ARITH2_O(name##o, opc1, opc2, opc3 | 0x10, 0x00000000)
398
399/* Two operands arithmetic functions with no overflow allowed */
400#define GEN_INT_ARITHN(name, opc1, opc2, opc3) \
401__GEN_INT_ARITH2(name, opc1, opc2, opc3, 0x00000400)
402
403/* One operand arithmetic functions */
404#define GEN_INT_ARITH1(name, opc1, opc2, opc3) \
405__GEN_INT_ARITH1(name, opc1, opc2, opc3) \
406__GEN_INT_ARITH1_O(name##o, opc1, opc2, opc3 | 0x10)
407
408/* add add. addo addo. */
409GEN_INT_ARITH2 (add, 0x1F, 0x0A, 0x08);
410/* addc addc. addco addco. */
411GEN_INT_ARITH2 (addc, 0x1F, 0x0A, 0x00);
412/* adde adde. addeo addeo. */
413GEN_INT_ARITH2 (adde, 0x1F, 0x0A, 0x04);
414/* addme addme. addmeo addmeo. */
415GEN_INT_ARITH1 (addme, 0x1F, 0x0A, 0x07);
416/* addze addze. addzeo addzeo. */
417GEN_INT_ARITH1 (addze, 0x1F, 0x0A, 0x06);
418/* divw divw. divwo divwo. */
419GEN_INT_ARITH2 (divw, 0x1F, 0x0B, 0x0F);
420/* divwu divwu. divwuo divwuo. */
421GEN_INT_ARITH2 (divwu, 0x1F, 0x0B, 0x0E);
422/* mulhw mulhw. */
423GEN_INT_ARITHN (mulhw, 0x1F, 0x0B, 0x02);
424/* mulhwu mulhwu. */
425GEN_INT_ARITHN (mulhwu, 0x1F, 0x0B, 0x00);
426/* mullw mullw. mullwo mullwo. */
427GEN_INT_ARITH2 (mullw, 0x1F, 0x0B, 0x07);
428/* neg neg. nego nego. */
429GEN_INT_ARITH1 (neg, 0x1F, 0x08, 0x03);
430/* subf subf. subfo subfo. */
431GEN_INT_ARITH2 (subf, 0x1F, 0x08, 0x01);
432/* subfc subfc. subfco subfco. */
433GEN_INT_ARITH2 (subfc, 0x1F, 0x08, 0x00);
434/* subfe subfe. subfeo subfeo. */
435GEN_INT_ARITH2 (subfe, 0x1F, 0x08, 0x04);
436/* subfme subfme. subfmeo subfmeo. */
437GEN_INT_ARITH1 (subfme, 0x1F, 0x08, 0x07);
438/* subfze subfze. subfzeo subfzeo. */
439GEN_INT_ARITH1 (subfze, 0x1F, 0x08, 0x06);
440/* addi */
441GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
442{
443 int32_t simm = SIMM(ctx->opcode);
444
445 if (rA(ctx->opcode) == 0) {
446 gen_op_set_T0(simm);
447 } else {
448 gen_op_load_gpr_T0(rA(ctx->opcode));
449 gen_op_addi(simm);
450 }
451 gen_op_store_T0_gpr(rD(ctx->opcode));
79aceca5
FB		 452}
453/* addic */
454GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
455{
456 gen_op_load_gpr_T0(rA(ctx->opcode));
457 gen_op_addic(SIMM(ctx->opcode));
458 gen_op_store_T0_gpr(rD(ctx->opcode));
79aceca5
FB		 459}
460/* addic. */
461GEN_HANDLER(addic_, 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
462{
463 gen_op_load_gpr_T0(rA(ctx->opcode));
464 gen_op_addic(SIMM(ctx->opcode));
465 gen_op_set_Rc0();
466 gen_op_store_T0_gpr(rD(ctx->opcode));
79aceca5
FB		 467}
468/* addis */
469GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
470{
471 int32_t simm = SIMM(ctx->opcode);
472
473 if (rA(ctx->opcode) == 0) {
474 gen_op_set_T0(simm << 16);
475 } else {
476 gen_op_load_gpr_T0(rA(ctx->opcode));
477 gen_op_addi(simm << 16);
478 }
479 gen_op_store_T0_gpr(rD(ctx->opcode));
79aceca5
FB		 480}
481/* mulli */
482GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
483{
484 gen_op_load_gpr_T0(rA(ctx->opcode));
485 gen_op_mulli(SIMM(ctx->opcode));
486 gen_op_store_T0_gpr(rD(ctx->opcode));
79aceca5
FB		 487}
488/* subfic */
489GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
490{
491 gen_op_load_gpr_T0(rA(ctx->opcode));
492 gen_op_subfic(SIMM(ctx->opcode));
493 gen_op_store_T0_gpr(rD(ctx->opcode));
79aceca5
FB		 494}
495
496/*** Integer comparison ***/
497#define GEN_CMP(name, opc) \
498GEN_HANDLER(name, 0x1F, 0x00, opc, 0x00400000, PPC_INTEGER) \
499{ \
500 gen_op_load_gpr_T0(rA(ctx->opcode)); \
501 gen_op_load_gpr_T1(rB(ctx->opcode)); \
502 gen_op_##name(); \
503 gen_op_store_T0_crf(crfD(ctx->opcode)); \
79aceca5
FB		 504}
505
506/* cmp */
507GEN_CMP(cmp, 0x00);
508/* cmpi */
509GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
510{
511 gen_op_load_gpr_T0(rA(ctx->opcode));
512 gen_op_cmpi(SIMM(ctx->opcode));
513 gen_op_store_T0_crf(crfD(ctx->opcode));
79aceca5
FB		 514}
515/* cmpl */
516GEN_CMP(cmpl, 0x01);
517/* cmpli */
518GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
519{
520 gen_op_load_gpr_T0(rA(ctx->opcode));
521 gen_op_cmpli(UIMM(ctx->opcode));
522 gen_op_store_T0_crf(crfD(ctx->opcode));
79aceca5
FB		 523}
524
525/*** Integer logical ***/
526#define __GEN_LOGICAL2(name, opc2, opc3) \
527GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000000, PPC_INTEGER) \
528{ \
529 gen_op_load_gpr_T0(rS(ctx->opcode)); \
530 gen_op_load_gpr_T1(rB(ctx->opcode)); \
531 gen_op_##name(); \
532 if (Rc(ctx->opcode) != 0) \
533 gen_op_set_Rc0(); \
534 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 535}
536#define GEN_LOGICAL2(name, opc) \
537__GEN_LOGICAL2(name, 0x1C, opc)
538
539#define GEN_LOGICAL1(name, opc) \
540GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, PPC_INTEGER) \
541{ \
542 gen_op_load_gpr_T0(rS(ctx->opcode)); \
543 gen_op_##name(); \
544 if (Rc(ctx->opcode) != 0) \
545 gen_op_set_Rc0(); \
546 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 547}
548
549/* and & and. */
550GEN_LOGICAL2(and, 0x00);
551/* andc & andc. */
552GEN_LOGICAL2(andc, 0x01);
553/* andi. */
554GEN_HANDLER(andi_, 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
555{
556 gen_op_load_gpr_T0(rS(ctx->opcode));
557 gen_op_andi_(UIMM(ctx->opcode));
558 gen_op_set_Rc0();
559 gen_op_store_T0_gpr(rA(ctx->opcode));
79aceca5
FB		 560}
561/* andis. */
562GEN_HANDLER(andis_, 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
563{
564 gen_op_load_gpr_T0(rS(ctx->opcode));
565 gen_op_andi_(UIMM(ctx->opcode) << 16);
566 gen_op_set_Rc0();
567 gen_op_store_T0_gpr(rA(ctx->opcode));
79aceca5
FB		 568}
569
570/* cntlzw */
571GEN_LOGICAL1(cntlzw, 0x00);
572/* eqv & eqv. */
573GEN_LOGICAL2(eqv, 0x08);
574/* extsb & extsb. */
575GEN_LOGICAL1(extsb, 0x1D);
576/* extsh & extsh. */
577GEN_LOGICAL1(extsh, 0x1C);
578/* nand & nand. */
579GEN_LOGICAL2(nand, 0x0E);
580/* nor & nor. */
581GEN_LOGICAL2(nor, 0x03);
9a64fbe4 582
79aceca5 583/* or & or. */
9a64fbe4
FB		 584GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER)
585{
586 gen_op_load_gpr_T0(rS(ctx->opcode));
587 /* Optimisation for mr case */
588 if (rS(ctx->opcode) != rB(ctx->opcode)) {
589 gen_op_load_gpr_T1(rB(ctx->opcode));
590 gen_op_or();
591 }
592 if (Rc(ctx->opcode) != 0)
593 gen_op_set_Rc0();
594 gen_op_store_T0_gpr(rA(ctx->opcode));
595}
596
79aceca5
FB		 597/* orc & orc. */
598GEN_LOGICAL2(orc, 0x0C);
599/* xor & xor. */
9a64fbe4
FB		 600GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER)
601{
602 gen_op_load_gpr_T0(rS(ctx->opcode));
603 /* Optimisation for "set to zero" case */
604 if (rS(ctx->opcode) != rB(ctx->opcode)) {
605 gen_op_load_gpr_T1(rB(ctx->opcode));
606 gen_op_xor();
607 } else {
608 gen_op_set_T0(0);
609 }
610 if (Rc(ctx->opcode) != 0)
611 gen_op_set_Rc0();
612 gen_op_store_T0_gpr(rA(ctx->opcode));
613}
79aceca5
FB		 614/* ori */
615GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
616{
617 uint32_t uimm = UIMM(ctx->opcode);
618
9a64fbe4
FB		 619 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
620 /* NOP */
621 return;
79aceca5 622 }
79aceca5 623 gen_op_load_gpr_T0(rS(ctx->opcode));
9a64fbe4 624 if (uimm != 0)
79aceca5
FB		 625 gen_op_ori(uimm);
626 gen_op_store_T0_gpr(rA(ctx->opcode));
79aceca5
FB		 627}
628/* oris */
629GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
630{
631 uint32_t uimm = UIMM(ctx->opcode);
632
9a64fbe4
FB		 633 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
634 /* NOP */
635 return;
79aceca5 636 }
79aceca5 637 gen_op_load_gpr_T0(rS(ctx->opcode));
9a64fbe4 638 if (uimm != 0)
79aceca5
FB		 639 gen_op_ori(uimm << 16);
640 gen_op_store_T0_gpr(rA(ctx->opcode));
79aceca5
FB		 641}
642/* xori */
643GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
644{
9a64fbe4
FB		 645 uint32_t uimm = UIMM(ctx->opcode);
646
647 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
648 /* NOP */
649 return;
650 }
79aceca5 651 gen_op_load_gpr_T0(rS(ctx->opcode));
9a64fbe4 652 if (uimm != 0)
4b3686fa 653 gen_op_xori(uimm);
79aceca5 654 gen_op_store_T0_gpr(rA(ctx->opcode));
79aceca5
FB		 655}
656
657/* xoris */
658GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
659{
9a64fbe4
FB		 660 uint32_t uimm = UIMM(ctx->opcode);
661
662 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
663 /* NOP */
664 return;
665 }
79aceca5 666 gen_op_load_gpr_T0(rS(ctx->opcode));
9a64fbe4 667 if (uimm != 0)
4b3686fa 668 gen_op_xori(uimm << 16);
79aceca5 669 gen_op_store_T0_gpr(rA(ctx->opcode));
79aceca5
FB		 670}
671
672/*** Integer rotate ***/
673/* rlwimi & rlwimi. */
674GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
675{
676 uint32_t mb, me;
677
678 mb = MB(ctx->opcode);
679 me = ME(ctx->opcode);
680 gen_op_load_gpr_T0(rS(ctx->opcode));
fb0eaffc 681 gen_op_load_gpr_T1(rA(ctx->opcode));
79aceca5
FB		 682 gen_op_rlwimi(SH(ctx->opcode), MASK(mb, me), ~MASK(mb, me));
683 if (Rc(ctx->opcode) != 0)
684 gen_op_set_Rc0();
685 gen_op_store_T0_gpr(rA(ctx->opcode));
79aceca5
FB		 686}
687/* rlwinm & rlwinm. */
688GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
689{
690 uint32_t mb, me, sh;
691
692 sh = SH(ctx->opcode);
693 mb = MB(ctx->opcode);
694 me = ME(ctx->opcode);
695 gen_op_load_gpr_T0(rS(ctx->opcode));
4b3686fa
FB		 696#if 1 // TRY
697 if (sh == 0) {
698 gen_op_andi_(MASK(mb, me));
699 goto store;
700 }
701#endif
79aceca5
FB		 702 if (mb == 0) {
703 if (me == 31) {
704 gen_op_rotlwi(sh);
705 goto store;
4b3686fa 706#if 0
79aceca5
FB		 707 } else if (me == (31 - sh)) {
708 gen_op_slwi(sh);
709 goto store;
4b3686fa 710#endif
79aceca5
FB		 711 }
712 } else if (me == 31) {
4b3686fa 713#if 0
79aceca5
FB		 714 if (sh == (32 - mb)) {
715 gen_op_srwi(mb);
716 goto store;
79aceca5 717 }
4b3686fa 718#endif
79aceca5
FB		 719 }
720 gen_op_rlwinm(sh, MASK(mb, me));
721store:
722 if (Rc(ctx->opcode) != 0)
723 gen_op_set_Rc0();
724 gen_op_store_T0_gpr(rA(ctx->opcode));
79aceca5
FB		 725}
726/* rlwnm & rlwnm. */
727GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
728{
729 uint32_t mb, me;
730
731 mb = MB(ctx->opcode);
732 me = ME(ctx->opcode);
733 gen_op_load_gpr_T0(rS(ctx->opcode));
734 gen_op_load_gpr_T1(rB(ctx->opcode));
735 if (mb == 0 && me == 31) {
736 gen_op_rotl();
737 } else
738 {
739 gen_op_rlwnm(MASK(mb, me));
740 }
741 if (Rc(ctx->opcode) != 0)
742 gen_op_set_Rc0();
743 gen_op_store_T0_gpr(rA(ctx->opcode));
79aceca5
FB		 744}
745
746/*** Integer shift ***/
747/* slw & slw. */
748__GEN_LOGICAL2(slw, 0x18, 0x00);
749/* sraw & sraw. */
750__GEN_LOGICAL2(sraw, 0x18, 0x18);
751/* srawi & srawi. */
752GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER)
753{
754 gen_op_load_gpr_T0(rS(ctx->opcode));
755 gen_op_srawi(SH(ctx->opcode), MASK(32 - SH(ctx->opcode), 31));
756 if (Rc(ctx->opcode) != 0)
757 gen_op_set_Rc0();
758 gen_op_store_T0_gpr(rA(ctx->opcode));
79aceca5
FB		 759}
760/* srw & srw. */
761__GEN_LOGICAL2(srw, 0x18, 0x10);
762
763/*** Floating-Point arithmetic ***/
9a64fbe4
FB		 764#define _GEN_FLOAT_ACB(name, op1, op2) \
765GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, PPC_FLOAT) \
766{ \
767 gen_op_reset_scrfx(); \
768 gen_op_load_fpr_FT0(rA(ctx->opcode)); \
769 gen_op_load_fpr_FT1(rC(ctx->opcode)); \
770 gen_op_load_fpr_FT2(rB(ctx->opcode)); \
771 gen_op_f##name(); \
772 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
773 if (Rc(ctx->opcode)) \
774 gen_op_set_Rc1(); \
775}
776
777#define GEN_FLOAT_ACB(name, op2) \
778_GEN_FLOAT_ACB(name, 0x3F, op2); \
779_GEN_FLOAT_ACB(name##s, 0x3B, op2);
780
781#define _GEN_FLOAT_AB(name, op1, op2, inval) \
782GEN_HANDLER(f##name, op1, op2, 0xFF, inval, PPC_FLOAT) \
783{ \
784 gen_op_reset_scrfx(); \
785 gen_op_load_fpr_FT0(rA(ctx->opcode)); \
786 gen_op_load_fpr_FT1(rB(ctx->opcode)); \
787 gen_op_f##name(); \
788 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
789 if (Rc(ctx->opcode)) \
790 gen_op_set_Rc1(); \
791}
792#define GEN_FLOAT_AB(name, op2, inval) \
793_GEN_FLOAT_AB(name, 0x3F, op2, inval); \
794_GEN_FLOAT_AB(name##s, 0x3B, op2, inval);
795
796#define _GEN_FLOAT_AC(name, op1, op2, inval) \
797GEN_HANDLER(f##name, op1, op2, 0xFF, inval, PPC_FLOAT) \
798{ \
799 gen_op_reset_scrfx(); \
800 gen_op_load_fpr_FT0(rA(ctx->opcode)); \
801 gen_op_load_fpr_FT1(rC(ctx->opcode)); \
802 gen_op_f##name(); \
803 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
804 if (Rc(ctx->opcode)) \
805 gen_op_set_Rc1(); \
806}
807#define GEN_FLOAT_AC(name, op2, inval) \
808_GEN_FLOAT_AC(name, 0x3F, op2, inval); \
809_GEN_FLOAT_AC(name##s, 0x3B, op2, inval);
810
811#define GEN_FLOAT_B(name, op2, op3) \
812GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, PPC_FLOAT) \
813{ \
814 gen_op_reset_scrfx(); \
815 gen_op_load_fpr_FT0(rB(ctx->opcode)); \
816 gen_op_f##name(); \
817 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
818 if (Rc(ctx->opcode)) \
819 gen_op_set_Rc1(); \
79aceca5
FB		 820}
821
9a64fbe4
FB		 822#define GEN_FLOAT_BS(name, op2) \
823GEN_HANDLER(f##name, 0x3F, op2, 0xFF, 0x001F07C0, PPC_FLOAT) \
824{ \
825 gen_op_reset_scrfx(); \
826 gen_op_load_fpr_FT0(rB(ctx->opcode)); \
827 gen_op_f##name(); \
828 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
829 if (Rc(ctx->opcode)) \
830 gen_op_set_Rc1(); \
79aceca5
FB		 831}
832
9a64fbe4
FB		 833/* fadd - fadds */
834GEN_FLOAT_AB(add, 0x15, 0x000007C0);
79aceca5 835/* fdiv */
9a64fbe4 836GEN_FLOAT_AB(div, 0x12, 0x000007C0);
79aceca5 837/* fmul */
9a64fbe4 838GEN_FLOAT_AC(mul, 0x19, 0x0000F800);
79aceca5
FB		 839
840/* fres */
9a64fbe4 841GEN_FLOAT_BS(res, 0x18);
79aceca5
FB		 842
843/* frsqrte */
9a64fbe4 844GEN_FLOAT_BS(rsqrte, 0x1A);
79aceca5
FB		 845
846/* fsel */
9a64fbe4 847_GEN_FLOAT_ACB(sel, 0x3F, 0x17);
79aceca5 848/* fsub */
9a64fbe4 849GEN_FLOAT_AB(sub, 0x14, 0x000007C0);
79aceca5
FB		 850/* Optional: */
851/* fsqrt */
9a64fbe4 852GEN_FLOAT_BS(sqrt, 0x16);
79aceca5 853
9a64fbe4 854GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_OPT)
79aceca5 855{
9a64fbe4
FB		 856 gen_op_reset_scrfx();
857 gen_op_load_fpr_FT0(rB(ctx->opcode));
858 gen_op_fsqrts();
859 gen_op_store_FT0_fpr(rD(ctx->opcode));
860 if (Rc(ctx->opcode))
861 gen_op_set_Rc1();
79aceca5
FB		 862}
863
864/*** Floating-Point multiply-and-add ***/
865/* fmadd */
9a64fbe4 866GEN_FLOAT_ACB(madd, 0x1D);
79aceca5 867/* fmsub */
9a64fbe4 868GEN_FLOAT_ACB(msub, 0x1C);
79aceca5 869/* fnmadd */
9a64fbe4 870GEN_FLOAT_ACB(nmadd, 0x1F);
79aceca5 871/* fnmsub */
9a64fbe4 872GEN_FLOAT_ACB(nmsub, 0x1E);
79aceca5
FB		 873
874/*** Floating-Point round & convert ***/
875/* fctiw */
9a64fbe4 876GEN_FLOAT_B(ctiw, 0x0E, 0x00);
79aceca5 877/* fctiwz */
9a64fbe4 878GEN_FLOAT_B(ctiwz, 0x0F, 0x00);
79aceca5 879/* frsp */
9a64fbe4 880GEN_FLOAT_B(rsp, 0x0C, 0x00);
79aceca5
FB		 881
882/*** Floating-Point compare ***/
883/* fcmpo */
884GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT)
885{
9a64fbe4
FB		 886 gen_op_reset_scrfx();
887 gen_op_load_fpr_FT0(rA(ctx->opcode));
888 gen_op_load_fpr_FT1(rB(ctx->opcode));
889 gen_op_fcmpo();
890 gen_op_store_T0_crf(crfD(ctx->opcode));
79aceca5
FB		 891}
892
893/* fcmpu */
894GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT)
895{
9a64fbe4
FB		 896 gen_op_reset_scrfx();
897 gen_op_load_fpr_FT0(rA(ctx->opcode));
898 gen_op_load_fpr_FT1(rB(ctx->opcode));
899 gen_op_fcmpu();
900 gen_op_store_T0_crf(crfD(ctx->opcode));
79aceca5
FB		 901}
902
9a64fbe4
FB		 903/*** Floating-point move ***/
904/* fabs */
905GEN_FLOAT_B(abs, 0x08, 0x08);
906
907/* fmr - fmr. */
908GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT)
909{
910 gen_op_reset_scrfx();
911 gen_op_load_fpr_FT0(rB(ctx->opcode));
912 gen_op_store_FT0_fpr(rD(ctx->opcode));
913 if (Rc(ctx->opcode))
914 gen_op_set_Rc1();
915}
916
917/* fnabs */
918GEN_FLOAT_B(nabs, 0x08, 0x04);
919/* fneg */
920GEN_FLOAT_B(neg, 0x08, 0x01);
921
79aceca5
FB		 922/*** Floating-Point status & ctrl register ***/
923/* mcrfs */
924GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT)
925{
fb0eaffc
FB		 926 gen_op_load_fpscr_T0(crfS(ctx->opcode));
927 gen_op_store_T0_crf(crfD(ctx->opcode));
928 gen_op_clear_fpscr(crfS(ctx->opcode));
79aceca5
FB		 929}
930
931/* mffs */
932GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT)
933{
28b6751f 934 gen_op_load_fpscr();
fb0eaffc
FB		 935 gen_op_store_FT0_fpr(rD(ctx->opcode));
936 if (Rc(ctx->opcode))
937 gen_op_set_Rc1();
79aceca5
FB		 938}
939
940/* mtfsb0 */
941GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT)
942{
fb0eaffc
FB		 943 uint8_t crb;
944
945 crb = crbD(ctx->opcode) >> 2;
946 gen_op_load_fpscr_T0(crb);
947 gen_op_andi_(~(1 << (crbD(ctx->opcode) & 0x03)));
948 gen_op_store_T0_fpscr(crb);
949 if (Rc(ctx->opcode))
950 gen_op_set_Rc1();
79aceca5
FB		 951}
952
953/* mtfsb1 */
954GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT)
955{
fb0eaffc
FB		 956 uint8_t crb;
957
958 crb = crbD(ctx->opcode) >> 2;
959 gen_op_load_fpscr_T0(crb);
960 gen_op_ori(1 << (crbD(ctx->opcode) & 0x03));
961 gen_op_store_T0_fpscr(crb);
962 if (Rc(ctx->opcode))
963 gen_op_set_Rc1();
79aceca5
FB		 964}
965
966/* mtfsf */
967GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x02010000, PPC_FLOAT)
968{
fb0eaffc 969 gen_op_load_fpr_FT0(rB(ctx->opcode));
28b6751f 970 gen_op_store_fpscr(FM(ctx->opcode));
fb0eaffc
FB		 971 if (Rc(ctx->opcode))
972 gen_op_set_Rc1();
79aceca5
FB		 973}
974
975/* mtfsfi */
976GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT)
977{
fb0eaffc
FB		 978 gen_op_store_T0_fpscri(crbD(ctx->opcode) >> 2, FPIMM(ctx->opcode));
979 if (Rc(ctx->opcode))
980 gen_op_set_Rc1();
79aceca5
FB		 981}
982
983/*** Integer load ***/
9a64fbe4
FB		 984#if defined(CONFIG_USER_ONLY)
985#define op_ldst(name) gen_op_##name##_raw()
986#define OP_LD_TABLE(width)
987#define OP_ST_TABLE(width)
988#else
989#define op_ldst(name) (*gen_op_##name[ctx->mem_idx])()
990#define OP_LD_TABLE(width) \
991static GenOpFunc *gen_op_l##width[] = { \
992 &gen_op_l##width##_user, \
993 &gen_op_l##width##_kernel, \
994}
995#define OP_ST_TABLE(width) \
996static GenOpFunc *gen_op_st##width[] = { \
997 &gen_op_st##width##_user, \
998 &gen_op_st##width##_kernel, \
999}
1000#endif
1001
1002#define GEN_LD(width, opc) \
79aceca5
FB		 1003GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \
1004{ \
1005 uint32_t simm = SIMM(ctx->opcode); \
1006 if (rA(ctx->opcode) == 0) { \
9a64fbe4 1007 gen_op_set_T0(simm); \
79aceca5
FB		 1008 } else { \
1009 gen_op_load_gpr_T0(rA(ctx->opcode)); \
9a64fbe4
FB		 1010 if (simm != 0) \
1011 gen_op_addi(simm); \
79aceca5 1012 } \
9a64fbe4 1013 op_ldst(l##width); \
79aceca5 1014 gen_op_store_T1_gpr(rD(ctx->opcode)); \
79aceca5
FB		 1015}
1016
9a64fbe4 1017#define GEN_LDU(width, opc) \
79aceca5
FB		 1018GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \
1019{ \
9a64fbe4 1020 uint32_t simm = SIMM(ctx->opcode); \
79aceca5 1021 if (rA(ctx->opcode) == 0 || \
9a64fbe4 1022 rA(ctx->opcode) == rD(ctx->opcode)) { \
9fddaa0c
FB		 1023 RET_INVAL(ctx); \
1024 return; \
9a64fbe4 1025 } \
79aceca5 1026 gen_op_load_gpr_T0(rA(ctx->opcode)); \
9a64fbe4
FB		 1027 if (simm != 0) \
1028 gen_op_addi(simm); \
1029 op_ldst(l##width); \
79aceca5
FB		 1030 gen_op_store_T1_gpr(rD(ctx->opcode)); \
1031 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 1032}
1033
9a64fbe4 1034#define GEN_LDUX(width, opc) \
79aceca5
FB		 1035GEN_HANDLER(l##width##ux, 0x1F, 0x17, opc, 0x00000001, PPC_INTEGER) \
1036{ \
1037 if (rA(ctx->opcode) == 0 || \
9a64fbe4 1038 rA(ctx->opcode) == rD(ctx->opcode)) { \
9fddaa0c
FB		 1039 RET_INVAL(ctx); \
1040 return; \
9a64fbe4 1041 } \
79aceca5
FB		 1042 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1043 gen_op_load_gpr_T1(rB(ctx->opcode)); \
9a64fbe4
FB		 1044 gen_op_add(); \
1045 op_ldst(l##width); \
79aceca5
FB		 1046 gen_op_store_T1_gpr(rD(ctx->opcode)); \
1047 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 1048}
1049
9a64fbe4 1050#define GEN_LDX(width, opc2, opc3) \
79aceca5
FB		 1051GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, PPC_INTEGER) \
1052{ \
1053 if (rA(ctx->opcode) == 0) { \
1054 gen_op_load_gpr_T0(rB(ctx->opcode)); \
79aceca5
FB		 1055 } else { \
1056 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1057 gen_op_load_gpr_T1(rB(ctx->opcode)); \
9a64fbe4 1058 gen_op_add(); \
79aceca5 1059 } \
9a64fbe4 1060 op_ldst(l##width); \
79aceca5 1061 gen_op_store_T1_gpr(rD(ctx->opcode)); \
79aceca5
FB		 1062}
1063
9a64fbe4
FB		 1064#define GEN_LDS(width, op) \
1065OP_LD_TABLE(width); \
1066GEN_LD(width, op | 0x20); \
1067GEN_LDU(width, op | 0x21); \
1068GEN_LDUX(width, op | 0x01); \
1069GEN_LDX(width, 0x17, op | 0x00)
79aceca5
FB		 1070
1071/* lbz lbzu lbzux lbzx */
9a64fbe4 1072GEN_LDS(bz, 0x02);
79aceca5 1073/* lha lhau lhaux lhax */
9a64fbe4 1074GEN_LDS(ha, 0x0A);
79aceca5 1075/* lhz lhzu lhzux lhzx */
9a64fbe4 1076GEN_LDS(hz, 0x08);
79aceca5 1077/* lwz lwzu lwzux lwzx */
9a64fbe4 1078GEN_LDS(wz, 0x00);
79aceca5
FB		 1079
1080/*** Integer store ***/
9a64fbe4 1081#define GEN_ST(width, opc) \
79aceca5
FB		 1082GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \
1083{ \
1084 uint32_t simm = SIMM(ctx->opcode); \
1085 if (rA(ctx->opcode) == 0) { \
9a64fbe4 1086 gen_op_set_T0(simm); \
79aceca5
FB		 1087 } else { \
1088 gen_op_load_gpr_T0(rA(ctx->opcode)); \
9a64fbe4
FB		 1089 if (simm != 0) \
1090 gen_op_addi(simm); \
79aceca5 1091 } \
9a64fbe4
FB		 1092 gen_op_load_gpr_T1(rS(ctx->opcode)); \
1093 op_ldst(st##width); \
79aceca5
FB		 1094}
1095
9a64fbe4 1096#define GEN_STU(width, opc) \
79aceca5
FB		 1097GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \
1098{ \
9a64fbe4
FB		 1099 uint32_t simm = SIMM(ctx->opcode); \
1100 if (rA(ctx->opcode) == 0) { \
9fddaa0c
FB		 1101 RET_INVAL(ctx); \
1102 return; \
9a64fbe4 1103 } \
79aceca5 1104 gen_op_load_gpr_T0(rA(ctx->opcode)); \
9a64fbe4
FB		 1105 if (simm != 0) \
1106 gen_op_addi(simm); \
79aceca5 1107 gen_op_load_gpr_T1(rS(ctx->opcode)); \
9a64fbe4 1108 op_ldst(st##width); \
79aceca5 1109 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 1110}
1111
9a64fbe4 1112#define GEN_STUX(width, opc) \
79aceca5
FB		 1113GEN_HANDLER(st##width##ux, 0x1F, 0x17, opc, 0x00000001, PPC_INTEGER) \
1114{ \
9a64fbe4 1115 if (rA(ctx->opcode) == 0) { \
9fddaa0c
FB		 1116 RET_INVAL(ctx); \
1117 return; \
9a64fbe4 1118 } \
79aceca5
FB		 1119 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1120 gen_op_load_gpr_T1(rB(ctx->opcode)); \
9a64fbe4
FB		 1121 gen_op_add(); \
1122 gen_op_load_gpr_T1(rS(ctx->opcode)); \
1123 op_ldst(st##width); \
79aceca5 1124 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 1125}
1126
9a64fbe4 1127#define GEN_STX(width, opc2, opc3) \
79aceca5
FB		 1128GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, PPC_INTEGER) \
1129{ \
1130 if (rA(ctx->opcode) == 0) { \
1131 gen_op_load_gpr_T0(rB(ctx->opcode)); \
79aceca5
FB		 1132 } else { \
1133 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1134 gen_op_load_gpr_T1(rB(ctx->opcode)); \
9a64fbe4 1135 gen_op_add(); \
79aceca5 1136 } \
9a64fbe4
FB		 1137 gen_op_load_gpr_T1(rS(ctx->opcode)); \
1138 op_ldst(st##width); \
79aceca5
FB		 1139}
1140
9a64fbe4
FB		 1141#define GEN_STS(width, op) \
1142OP_ST_TABLE(width); \
1143GEN_ST(width, op | 0x20); \
1144GEN_STU(width, op | 0x21); \
1145GEN_STUX(width, op | 0x01); \
1146GEN_STX(width, 0x17, op | 0x00)
79aceca5
FB		 1147
1148/* stb stbu stbux stbx */
9a64fbe4 1149GEN_STS(b, 0x06);
79aceca5 1150/* sth sthu sthux sthx */
9a64fbe4 1151GEN_STS(h, 0x0C);
79aceca5 1152/* stw stwu stwux stwx */
9a64fbe4 1153GEN_STS(w, 0x04);
79aceca5
FB		 1154
1155/*** Integer load and store with byte reverse ***/
1156/* lhbrx */
9a64fbe4
FB		 1157OP_LD_TABLE(hbr);
1158GEN_LDX(hbr, 0x16, 0x18);
79aceca5 1159/* lwbrx */
9a64fbe4
FB		 1160OP_LD_TABLE(wbr);
1161GEN_LDX(wbr, 0x16, 0x10);
79aceca5 1162/* sthbrx */
9a64fbe4
FB		 1163OP_ST_TABLE(hbr);
1164GEN_STX(hbr, 0x16, 0x1C);
79aceca5 1165/* stwbrx */
9a64fbe4
FB		 1166OP_ST_TABLE(wbr);
1167GEN_STX(wbr, 0x16, 0x14);
79aceca5
FB		 1168
1169/*** Integer load and store multiple ***/
9a64fbe4
FB		 1170#if defined(CONFIG_USER_ONLY)
1171#define op_ldstm(name, reg) gen_op_##name##_raw(reg)
1172#else
1173#define op_ldstm(name, reg) (*gen_op_##name[ctx->mem_idx])(reg)
1174static GenOpFunc1 *gen_op_lmw[] = {
1175 &gen_op_lmw_user,
1176 &gen_op_lmw_kernel,
1177};
1178static GenOpFunc1 *gen_op_stmw[] = {
1179 &gen_op_stmw_user,
1180 &gen_op_stmw_kernel,
1181};
1182#endif
1183
79aceca5
FB		 1184/* lmw */
1185GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1186{
9a64fbe4
FB		 1187 int simm = SIMM(ctx->opcode);
1188
79aceca5 1189 if (rA(ctx->opcode) == 0) {
9a64fbe4 1190 gen_op_set_T0(simm);
79aceca5
FB		 1191 } else {
1192 gen_op_load_gpr_T0(rA(ctx->opcode));
9a64fbe4
FB		 1193 if (simm != 0)
1194 gen_op_addi(simm);
79aceca5 1195 }
9a64fbe4 1196 op_ldstm(lmw, rD(ctx->opcode));
79aceca5
FB		 1197}
1198
1199/* stmw */
1200GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1201{
9a64fbe4
FB		 1202 int simm = SIMM(ctx->opcode);
1203
79aceca5 1204 if (rA(ctx->opcode) == 0) {
9a64fbe4 1205 gen_op_set_T0(simm);
79aceca5
FB		 1206 } else {
1207 gen_op_load_gpr_T0(rA(ctx->opcode));
9a64fbe4
FB		 1208 if (simm != 0)
1209 gen_op_addi(simm);
79aceca5 1210 }
9a64fbe4 1211 op_ldstm(stmw, rS(ctx->opcode));
79aceca5
FB		 1212}
1213
1214/*** Integer load and store strings ***/
9a64fbe4
FB		 1215#if defined(CONFIG_USER_ONLY)
1216#define op_ldsts(name, start) gen_op_##name##_raw(start)
1217#define op_ldstsx(name, rd, ra, rb) gen_op_##name##_raw(rd, ra, rb)
1218#else
1219#define op_ldsts(name, start) (*gen_op_##name[ctx->mem_idx])(start)
1220#define op_ldstsx(name, rd, ra, rb) (*gen_op_##name[ctx->mem_idx])(rd, ra, rb)
1221static GenOpFunc1 *gen_op_lswi[] = {
1222 &gen_op_lswi_user,
1223 &gen_op_lswi_kernel,
1224};
1225static GenOpFunc3 *gen_op_lswx[] = {
1226 &gen_op_lswx_user,
1227 &gen_op_lswx_kernel,
1228};
1229static GenOpFunc1 *gen_op_stsw[] = {
1230 &gen_op_stsw_user,
1231 &gen_op_stsw_kernel,
1232};
1233#endif
1234
79aceca5 1235/* lswi */
9a64fbe4
FB		 1236/* PPC32 specification says we must generate an exception if
1237 * rA is in the range of registers to be loaded.
1238 * In an other hand, IBM says this is valid, but rA won't be loaded.
1239 * For now, I'll follow the spec...
1240 */
79aceca5
FB		 1241GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_INTEGER)
1242{
1243 int nb = NB(ctx->opcode);
1244 int start = rD(ctx->opcode);
9a64fbe4 1245 int ra = rA(ctx->opcode);
79aceca5
FB		 1246 int nr;
1247
1248 if (nb == 0)
1249 nb = 32;
1250 nr = nb / 4;
297d8e62
FB		 1251 if (((start + nr) > 32 && start <= ra && (start + nr - 32) > ra) ||
1252 ((start + nr) <= 32 && start <= ra && (start + nr) > ra)) {
9fddaa0c
FB		 1253 RET_EXCP(ctx, EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_LSWX);
1254 return;
297d8e62 1255 }
9a64fbe4 1256 if (ra == 0) {
79aceca5
FB		 1257 gen_op_set_T0(0);
1258 } else {
9a64fbe4 1259 gen_op_load_gpr_T0(ra);
79aceca5 1260 }
9a64fbe4
FB		 1261 gen_op_set_T1(nb);
1262 op_ldsts(lswi, start);
79aceca5
FB		 1263}
1264
1265/* lswx */
1266GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_INTEGER)
1267{
9a64fbe4
FB		 1268 int ra = rA(ctx->opcode);
1269 int rb = rB(ctx->opcode);
1270
1271 if (ra == 0) {
1272 gen_op_load_gpr_T0(rb);
1273 ra = rb;
79aceca5 1274 } else {
9a64fbe4
FB		 1275 gen_op_load_gpr_T0(ra);
1276 gen_op_load_gpr_T1(rb);
1277 gen_op_add();
79aceca5 1278 }
9a64fbe4
FB		 1279 gen_op_load_xer_bc();
1280 op_ldstsx(lswx, rD(ctx->opcode), ra, rb);
79aceca5
FB		 1281}
1282
1283/* stswi */
1284GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_INTEGER)
1285{
4b3686fa
FB		 1286 int nb = NB(ctx->opcode);
1287
79aceca5
FB		 1288 if (rA(ctx->opcode) == 0) {
1289 gen_op_set_T0(0);
1290 } else {
1291 gen_op_load_gpr_T0(rA(ctx->opcode));
1292 }
4b3686fa
FB		 1293 if (nb == 0)
1294 nb = 32;
1295 gen_op_set_T1(nb);
9a64fbe4 1296 op_ldsts(stsw, rS(ctx->opcode));
79aceca5
FB		 1297}
1298
1299/* stswx */
1300GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_INTEGER)
1301{
9a64fbe4
FB		 1302 int ra = rA(ctx->opcode);
1303
1304 if (ra == 0) {
1305 gen_op_load_gpr_T0(rB(ctx->opcode));
1306 ra = rB(ctx->opcode);
79aceca5 1307 } else {
9a64fbe4
FB		 1308 gen_op_load_gpr_T0(ra);
1309 gen_op_load_gpr_T1(rB(ctx->opcode));
1310 gen_op_add();
79aceca5 1311 }
9a64fbe4
FB		 1312 gen_op_load_xer_bc();
1313 op_ldsts(stsw, rS(ctx->opcode));
79aceca5
FB		 1314}
1315
1316/*** Memory synchronisation ***/
1317/* eieio */
1318GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FF0801, PPC_MEM)
1319{
79aceca5
FB		 1320}
1321
1322/* isync */
1323GEN_HANDLER(isync, 0x13, 0x16, 0xFF, 0x03FF0801, PPC_MEM)
1324{
79aceca5
FB		 1325}
1326
1327/* lwarx */
9a64fbe4 1328#if defined(CONFIG_USER_ONLY)
985a19d6 1329#define op_lwarx() gen_op_lwarx_raw()
9a64fbe4
FB		 1330#define op_stwcx() gen_op_stwcx_raw()
1331#else
985a19d6
FB		 1332#define op_lwarx() (*gen_op_lwarx[ctx->mem_idx])()
1333static GenOpFunc *gen_op_lwarx[] = {
1334 &gen_op_lwarx_user,
1335 &gen_op_lwarx_kernel,
1336};
9a64fbe4
FB		 1337#define op_stwcx() (*gen_op_stwcx[ctx->mem_idx])()
1338static GenOpFunc *gen_op_stwcx[] = {
1339 &gen_op_stwcx_user,
1340 &gen_op_stwcx_kernel,
1341};
1342#endif
1343
1344GEN_HANDLER(lwarx, 0x1F, 0x14, 0xFF, 0x00000001, PPC_RES)
79aceca5 1345{
79aceca5
FB		 1346 if (rA(ctx->opcode) == 0) {
1347 gen_op_load_gpr_T0(rB(ctx->opcode));
79aceca5
FB		 1348 } else {
1349 gen_op_load_gpr_T0(rA(ctx->opcode));
1350 gen_op_load_gpr_T1(rB(ctx->opcode));
9a64fbe4 1351 gen_op_add();
79aceca5 1352 }
985a19d6 1353 op_lwarx();
79aceca5 1354 gen_op_store_T1_gpr(rD(ctx->opcode));
79aceca5
FB		 1355}
1356
1357/* stwcx. */
9a64fbe4 1358GEN_HANDLER(stwcx_, 0x1F, 0x16, 0x04, 0x00000000, PPC_RES)
79aceca5 1359{
79aceca5
FB		 1360 if (rA(ctx->opcode) == 0) {
1361 gen_op_load_gpr_T0(rB(ctx->opcode));
79aceca5
FB		 1362 } else {
1363 gen_op_load_gpr_T0(rA(ctx->opcode));
1364 gen_op_load_gpr_T1(rB(ctx->opcode));
9a64fbe4 1365 gen_op_add();
79aceca5 1366 }
9a64fbe4
FB		 1367 gen_op_load_gpr_T1(rS(ctx->opcode));
1368 op_stwcx();
79aceca5
FB		 1369}
1370
1371/* sync */
1372GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x03FF0801, PPC_MEM)
1373{
79aceca5
FB		 1374}
1375
1376/*** Floating-point load ***/
9a64fbe4
FB		 1377#define GEN_LDF(width, opc) \
1378GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \
79aceca5
FB		 1379{ \
1380 uint32_t simm = SIMM(ctx->opcode); \
1381 if (rA(ctx->opcode) == 0) { \
9a64fbe4 1382 gen_op_set_T0(simm); \
79aceca5
FB		 1383 } else { \
1384 gen_op_load_gpr_T0(rA(ctx->opcode)); \
9a64fbe4
FB		 1385 if (simm != 0) \
1386 gen_op_addi(simm); \
79aceca5 1387 } \
9a64fbe4
FB		 1388 op_ldst(l##width); \
1389 gen_op_store_FT1_fpr(rD(ctx->opcode)); \
79aceca5
FB		 1390}
1391
9a64fbe4
FB		 1392#define GEN_LDUF(width, opc) \
1393GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \
79aceca5 1394{ \
9a64fbe4 1395 uint32_t simm = SIMM(ctx->opcode); \
79aceca5 1396 if (rA(ctx->opcode) == 0 || \
9a64fbe4 1397 rA(ctx->opcode) == rD(ctx->opcode)) { \
9fddaa0c
FB		 1398 RET_INVAL(ctx); \
1399 return; \
9a64fbe4 1400 } \
79aceca5 1401 gen_op_load_gpr_T0(rA(ctx->opcode)); \
9a64fbe4
FB		 1402 if (simm != 0) \
1403 gen_op_addi(simm); \
1404 op_ldst(l##width); \
1405 gen_op_store_FT1_fpr(rD(ctx->opcode)); \
79aceca5 1406 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 1407}
1408
9a64fbe4
FB		 1409#define GEN_LDUXF(width, opc) \
1410GEN_HANDLER(l##width##ux, 0x1F, 0x17, opc, 0x00000001, PPC_INTEGER) \
79aceca5
FB		 1411{ \
1412 if (rA(ctx->opcode) == 0 || \
9a64fbe4 1413 rA(ctx->opcode) == rD(ctx->opcode)) { \
9fddaa0c
FB		 1414 RET_INVAL(ctx); \
1415 return; \
9a64fbe4 1416 } \
79aceca5
FB		 1417 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1418 gen_op_load_gpr_T1(rB(ctx->opcode)); \
9a64fbe4
FB		 1419 gen_op_add(); \
1420 op_ldst(l##width); \
1421 gen_op_store_FT1_fpr(rD(ctx->opcode)); \
79aceca5 1422 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 1423}
1424
9a64fbe4
FB		 1425#define GEN_LDXF(width, opc2, opc3) \
1426GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, PPC_INTEGER) \
79aceca5
FB		 1427{ \
1428 if (rA(ctx->opcode) == 0) { \
1429 gen_op_load_gpr_T0(rB(ctx->opcode)); \
79aceca5
FB		 1430 } else { \
1431 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1432 gen_op_load_gpr_T1(rB(ctx->opcode)); \
9a64fbe4 1433 gen_op_add(); \
79aceca5 1434 } \
9a64fbe4
FB		 1435 op_ldst(l##width); \
1436 gen_op_store_FT1_fpr(rD(ctx->opcode)); \
79aceca5
FB		 1437}
1438
9a64fbe4
FB		 1439#define GEN_LDFS(width, op) \
1440OP_LD_TABLE(width); \
1441GEN_LDF(width, op | 0x20); \
1442GEN_LDUF(width, op | 0x21); \
1443GEN_LDUXF(width, op | 0x01); \
1444GEN_LDXF(width, 0x17, op | 0x00)
79aceca5
FB		 1445
1446/* lfd lfdu lfdux lfdx */
9a64fbe4 1447GEN_LDFS(fd, 0x12);
79aceca5 1448/* lfs lfsu lfsux lfsx */
9a64fbe4 1449GEN_LDFS(fs, 0x10);
79aceca5
FB		 1450
1451/*** Floating-point store ***/
1452#define GEN_STF(width, opc) \
9a64fbe4 1453GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \
79aceca5
FB		 1454{ \
1455 uint32_t simm = SIMM(ctx->opcode); \
1456 if (rA(ctx->opcode) == 0) { \
9a64fbe4 1457 gen_op_set_T0(simm); \
79aceca5
FB		 1458 } else { \
1459 gen_op_load_gpr_T0(rA(ctx->opcode)); \
9a64fbe4
FB		 1460 if (simm != 0) \
1461 gen_op_addi(simm); \
79aceca5 1462 } \
9a64fbe4
FB		 1463 gen_op_load_fpr_FT1(rS(ctx->opcode)); \
1464 op_ldst(st##width); \
79aceca5
FB		 1465}
1466
9a64fbe4
FB		 1467#define GEN_STUF(width, opc) \
1468GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \
79aceca5 1469{ \
9a64fbe4
FB		 1470 uint32_t simm = SIMM(ctx->opcode); \
1471 if (rA(ctx->opcode) == 0) { \
9fddaa0c
FB		 1472 RET_INVAL(ctx); \
1473 return; \
9a64fbe4 1474 } \
79aceca5 1475 gen_op_load_gpr_T0(rA(ctx->opcode)); \
9a64fbe4
FB		 1476 if (simm != 0) \
1477 gen_op_addi(simm); \
1478 gen_op_load_fpr_FT1(rS(ctx->opcode)); \
1479 op_ldst(st##width); \
79aceca5 1480 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 1481}
1482
9a64fbe4
FB		 1483#define GEN_STUXF(width, opc) \
1484GEN_HANDLER(st##width##ux, 0x1F, 0x17, opc, 0x00000001, PPC_INTEGER) \
79aceca5 1485{ \
9a64fbe4 1486 if (rA(ctx->opcode) == 0) { \
9fddaa0c
FB		 1487 RET_INVAL(ctx); \
1488 return; \
9a64fbe4 1489 } \
79aceca5
FB		 1490 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1491 gen_op_load_gpr_T1(rB(ctx->opcode)); \
9a64fbe4
FB		 1492 gen_op_add(); \
1493 gen_op_load_fpr_FT1(rS(ctx->opcode)); \
1494 op_ldst(st##width); \
79aceca5 1495 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 1496}
1497
9a64fbe4
FB		 1498#define GEN_STXF(width, opc2, opc3) \
1499GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, PPC_INTEGER) \
79aceca5
FB		 1500{ \
1501 if (rA(ctx->opcode) == 0) { \
1502 gen_op_load_gpr_T0(rB(ctx->opcode)); \
79aceca5
FB		 1503 } else { \
1504 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1505 gen_op_load_gpr_T1(rB(ctx->opcode)); \
9a64fbe4 1506 gen_op_add(); \
79aceca5 1507 } \
9a64fbe4
FB		 1508 gen_op_load_fpr_FT1(rS(ctx->opcode)); \
1509 op_ldst(st##width); \
79aceca5
FB		 1510}
1511
9a64fbe4
FB		 1512#define GEN_STFS(width, op) \
1513OP_ST_TABLE(width); \
1514GEN_STF(width, op | 0x20); \
1515GEN_STUF(width, op | 0x21); \
1516GEN_STUXF(width, op | 0x01); \
1517GEN_STXF(width, 0x17, op | 0x00)
79aceca5
FB		 1518
1519/* stfd stfdu stfdux stfdx */
9a64fbe4 1520GEN_STFS(fd, 0x16);
79aceca5 1521/* stfs stfsu stfsux stfsx */
9a64fbe4 1522GEN_STFS(fs, 0x14);
79aceca5
FB		 1523
1524/* Optional: */
1525/* stfiwx */
1526GEN_HANDLER(stfiwx, 0x1F, 0x17, 0x1E, 0x00000001, PPC_FLOAT)
1527{
9fddaa0c 1528 RET_INVAL(ctx);
79aceca5
FB		 1529}
1530
1531/*** Branch ***/
79aceca5
FB		 1532
1533/* b ba bl bla */
1534GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
1535{
38a64f9d
FB		 1536 uint32_t li, target;
1537
1538 /* sign extend LI */
1539 li = ((int32_t)LI(ctx->opcode) << 6) >> 6;
79aceca5
FB		 1540
1541 if (AA(ctx->opcode) == 0)
046d6672 1542 target = ctx->nip + li - 4;
79aceca5 1543 else
9a64fbe4 1544 target = li;
9a64fbe4 1545 if (LK(ctx->opcode)) {
046d6672 1546 gen_op_setlr(ctx->nip);
9a64fbe4 1547 }
e98a6e40 1548 gen_op_b((long)ctx->tb, target);
9a64fbe4 1549 ctx->exception = EXCP_BRANCH;
79aceca5
FB		 1550}
1551
e98a6e40
FB		 1552#define BCOND_IM 0
1553#define BCOND_LR 1
1554#define BCOND_CTR 2
1555
1556static inline void gen_bcond(DisasContext *ctx, int type)
1557{
1558 uint32_t target = 0;
1559 uint32_t bo = BO(ctx->opcode);
1560 uint32_t bi = BI(ctx->opcode);
1561 uint32_t mask;
1562 uint32_t li;
1563
e98a6e40
FB		 1564 if ((bo & 0x4) == 0)
1565 gen_op_dec_ctr();
1566 switch(type) {
1567 case BCOND_IM:
18fba28c 1568 li = (int32_t)((int16_t)(BD(ctx->opcode)));
e98a6e40 1569 if (AA(ctx->opcode) == 0) {
046d6672 1570 target = ctx->nip + li - 4;
e98a6e40
FB		 1571 } else {
1572 target = li;
1573 }
1574 break;
1575 case BCOND_CTR:
1576 gen_op_movl_T1_ctr();
1577 break;
1578 default:
1579 case BCOND_LR:
1580 gen_op_movl_T1_lr();
1581 break;
1582 }
1583 if (LK(ctx->opcode)) {
046d6672 1584 gen_op_setlr(ctx->nip);
e98a6e40
FB		 1585 }
1586 if (bo & 0x10) {
1587 /* No CR condition */
1588 switch (bo & 0x6) {
1589 case 0:
1590 gen_op_test_ctr();
1591 break;
1592 case 2:
1593 gen_op_test_ctrz();
1594 break;
1595 default:
1596 case 4:
1597 case 6:
1598 if (type == BCOND_IM) {
1599 gen_op_b((long)ctx->tb, target);
1600 } else {
1601 gen_op_b_T1();
e98a6e40
FB		 1602 }
1603 goto no_test;
1604 }
1605 } else {
1606 mask = 1 << (3 - (bi & 0x03));
1607 gen_op_load_crf_T0(bi >> 2);
1608 if (bo & 0x8) {
1609 switch (bo & 0x6) {
1610 case 0:
1611 gen_op_test_ctr_true(mask);
1612 break;
1613 case 2:
1614 gen_op_test_ctrz_true(mask);
1615 break;
1616 default:
1617 case 4:
1618 case 6:
1619 gen_op_test_true(mask);
1620 break;
1621 }
1622 } else {
1623 switch (bo & 0x6) {
1624 case 0:
1625 gen_op_test_ctr_false(mask);
1626 break;
1627 case 2:
1628 gen_op_test_ctrz_false(mask);
1629 break;
1630 default:
1631 case 4:
1632 case 6:
1633 gen_op_test_false(mask);
1634 break;
1635 }
1636 }
1637 }
1638 if (type == BCOND_IM) {
046d6672 1639 gen_op_btest((long)ctx->tb, target, ctx->nip);
e98a6e40 1640 } else {
046d6672 1641 gen_op_btest_T1(ctx->nip);
e98a6e40
FB		 1642 }
1643 no_test:
1644 ctx->exception = EXCP_BRANCH;
1645}
1646
1647GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
1648{
1649 gen_bcond(ctx, BCOND_IM);
1650}
1651
1652GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW)
1653{
1654 gen_bcond(ctx, BCOND_CTR);
1655}
1656
1657GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW)
1658{
1659 gen_bcond(ctx, BCOND_LR);
1660}
79aceca5
FB		 1661
1662/*** Condition register logical ***/
1663#define GEN_CRLOGIC(op, opc) \
1664GEN_HANDLER(cr##op, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) \
1665{ \
1666 gen_op_load_crf_T0(crbA(ctx->opcode) >> 2); \
1667 gen_op_getbit_T0(3 - (crbA(ctx->opcode) & 0x03)); \
1668 gen_op_load_crf_T1(crbB(ctx->opcode) >> 2); \
1669 gen_op_getbit_T1(3 - (crbB(ctx->opcode) & 0x03)); \
1670 gen_op_##op(); \
1671 gen_op_load_crf_T1(crbD(ctx->opcode) >> 2); \
1672 gen_op_setcrfbit(~(1 << (3 - (crbD(ctx->opcode) & 0x03))), \
1673 3 - (crbD(ctx->opcode) & 0x03)); \
1674 gen_op_store_T1_crf(crbD(ctx->opcode) >> 2); \
79aceca5
FB		 1675}
1676
1677/* crand */
1678GEN_CRLOGIC(and, 0x08)
1679/* crandc */
1680GEN_CRLOGIC(andc, 0x04)
1681/* creqv */
1682GEN_CRLOGIC(eqv, 0x09)
1683/* crnand */
1684GEN_CRLOGIC(nand, 0x07)
1685/* crnor */
1686GEN_CRLOGIC(nor, 0x01)
1687/* cror */
1688GEN_CRLOGIC(or, 0x0E)
1689/* crorc */
1690GEN_CRLOGIC(orc, 0x0D)
1691/* crxor */
1692GEN_CRLOGIC(xor, 0x06)
1693/* mcrf */
1694GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER)
1695{
1696 gen_op_load_crf_T0(crfS(ctx->opcode));
1697 gen_op_store_T0_crf(crfD(ctx->opcode));
79aceca5
FB		 1698}
1699
1700/*** System linkage ***/
1701/* rfi (supervisor only) */
1702GEN_HANDLER(rfi, 0x13, 0x12, 0xFF, 0x03FF8001, PPC_FLOW)
1703{
9a64fbe4 1704#if defined(CONFIG_USER_ONLY)
9fddaa0c 1705 RET_PRIVOPC(ctx);
9a64fbe4
FB		 1706#else
1707 /* Restore CPU state */
1708 if (!ctx->supervisor) {
9fddaa0c
FB		 1709 RET_PRIVOPC(ctx);
1710 return;
9a64fbe4
FB		 1711 }
1712 gen_op_rfi();
9fddaa0c 1713 RET_EXCP(ctx, EXCP_RFI, 0);
9a64fbe4 1714#endif
79aceca5
FB		 1715}
1716
1717/* sc */
1718GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFFFFD, PPC_FLOW)
1719{
9a64fbe4 1720#if defined(CONFIG_USER_ONLY)
9fddaa0c 1721 RET_EXCP(ctx, EXCP_SYSCALL_USER, 0);
9a64fbe4 1722#else
9fddaa0c 1723 RET_EXCP(ctx, EXCP_SYSCALL, 0);
9a64fbe4 1724#endif
79aceca5
FB		 1725}
1726
1727/*** Trap ***/
1728/* tw */
1729GEN_HANDLER(tw, 0x1F, 0x04, 0xFF, 0x00000001, PPC_FLOW)
1730{
9a64fbe4
FB		 1731 gen_op_load_gpr_T0(rA(ctx->opcode));
1732 gen_op_load_gpr_T1(rB(ctx->opcode));
1733 gen_op_tw(TO(ctx->opcode));
79aceca5
FB		 1734}
1735
1736/* twi */
1737GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
1738{
9a64fbe4
FB		 1739 gen_op_load_gpr_T0(rA(ctx->opcode));
1740#if 0
1741 printf("%s: param=0x%04x T0=0x%04x\n", __func__,
1742 SIMM(ctx->opcode), TO(ctx->opcode));
1743#endif
1744 gen_op_twi(SIMM(ctx->opcode), TO(ctx->opcode));
79aceca5
FB		 1745}
1746
1747/*** Processor control ***/
1748static inline int check_spr_access (int spr, int rw, int supervisor)
1749{
1750 uint32_t rights = spr_access[spr >> 1] >> (4 * (spr & 1));
1751
9a64fbe4
FB		 1752#if 0
1753 if (spr != LR && spr != CTR) {
1754 if (loglevel > 0) {
1755 fprintf(logfile, "%s reg=%d s=%d rw=%d r=0x%02x 0x%02x\n", __func__,
1756 SPR_ENCODE(spr), supervisor, rw, rights,
1757 (rights >> ((2 * supervisor) + rw)) & 1);
1758 } else {
1759 printf("%s reg=%d s=%d rw=%d r=0x%02x 0x%02x\n", __func__,
1760 SPR_ENCODE(spr), supervisor, rw, rights,
1761 (rights >> ((2 * supervisor) + rw)) & 1);
1762 }
1763 }
1764#endif
1765 if (rights == 0)
1766 return -1;
79aceca5
FB		 1767 rights = rights >> (2 * supervisor);
1768 rights = rights >> rw;
1769
1770 return rights & 1;
1771}
1772
1773/* mcrxr */
1774GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC)
1775{
1776 gen_op_load_xer_cr();
1777 gen_op_store_T0_crf(crfD(ctx->opcode));
1778 gen_op_clear_xer_cr();
79aceca5
FB		 1779}
1780
1781/* mfcr */
1782GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x001FF801, PPC_MISC)
1783{
1784 gen_op_load_cr();
1785 gen_op_store_T0_gpr(rD(ctx->opcode));
79aceca5
FB		 1786}
1787
1788/* mfmsr */
1789GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC)
1790{
9a64fbe4 1791#if defined(CONFIG_USER_ONLY)
9fddaa0c 1792 RET_PRIVREG(ctx);
9a64fbe4
FB		 1793#else
1794 if (!ctx->supervisor) {
9fddaa0c
FB		 1795 RET_PRIVREG(ctx);
1796 return;
9a64fbe4 1797 }
79aceca5
FB		 1798 gen_op_load_msr();
1799 gen_op_store_T0_gpr(rD(ctx->opcode));
9a64fbe4 1800#endif
79aceca5
FB		 1801}
1802
1803/* mfspr */
1804GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC)
1805{
1806 uint32_t sprn = SPR(ctx->opcode);
1807
9a64fbe4
FB		 1808#if defined(CONFIG_USER_ONLY)
1809 switch (check_spr_access(sprn, 0, 0))
1810#else
1811 switch (check_spr_access(sprn, 0, ctx->supervisor))
1812#endif
1813 {
1814 case -1:
9fddaa0c
FB		 1815 RET_EXCP(ctx, EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_SPR);
1816 return;
9a64fbe4 1817 case 0:
9fddaa0c
FB		 1818 RET_PRIVREG(ctx);
1819 return;
9a64fbe4
FB		 1820 default:
1821 break;
79aceca5 1822 }
9a64fbe4
FB		 1823 switch (sprn) {
1824 case XER:
79aceca5
FB		 1825 gen_op_load_xer();
1826 break;
9a64fbe4
FB		 1827 case LR:
1828 gen_op_load_lr();
1829 break;
1830 case CTR:
1831 gen_op_load_ctr();
1832 break;
1833 case IBAT0U:
1834 gen_op_load_ibat(0, 0);
1835 break;
1836 case IBAT1U:
1837 gen_op_load_ibat(0, 1);
1838 break;
1839 case IBAT2U:
1840 gen_op_load_ibat(0, 2);
1841 break;
1842 case IBAT3U:
1843 gen_op_load_ibat(0, 3);
1844 break;
1845 case IBAT4U:
1846 gen_op_load_ibat(0, 4);
1847 break;
1848 case IBAT5U:
1849 gen_op_load_ibat(0, 5);
1850 break;
1851 case IBAT6U:
1852 gen_op_load_ibat(0, 6);
1853 break;
1854 case IBAT7U:
1855 gen_op_load_ibat(0, 7);
1856 break;
1857 case IBAT0L:
1858 gen_op_load_ibat(1, 0);
1859 break;
1860 case IBAT1L:
1861 gen_op_load_ibat(1, 1);
1862 break;
1863 case IBAT2L:
1864 gen_op_load_ibat(1, 2);
1865 break;
1866 case IBAT3L:
1867 gen_op_load_ibat(1, 3);
1868 break;
1869 case IBAT4L:
1870 gen_op_load_ibat(1, 4);
1871 break;
1872 case IBAT5L:
1873 gen_op_load_ibat(1, 5);
1874 break;
1875 case IBAT6L:
1876 gen_op_load_ibat(1, 6);
1877 break;
1878 case IBAT7L:
1879 gen_op_load_ibat(1, 7);
1880 break;
1881 case DBAT0U:
1882 gen_op_load_dbat(0, 0);
1883 break;
1884 case DBAT1U:
1885 gen_op_load_dbat(0, 1);
1886 break;
1887 case DBAT2U:
1888 gen_op_load_dbat(0, 2);
1889 break;
1890 case DBAT3U:
1891 gen_op_load_dbat(0, 3);
1892 break;
1893 case DBAT4U:
1894 gen_op_load_dbat(0, 4);
1895 break;
1896 case DBAT5U:
1897 gen_op_load_dbat(0, 5);
1898 break;
1899 case DBAT6U:
1900 gen_op_load_dbat(0, 6);
1901 break;
1902 case DBAT7U:
1903 gen_op_load_dbat(0, 7);
1904 break;
1905 case DBAT0L:
1906 gen_op_load_dbat(1, 0);
1907 break;
1908 case DBAT1L:
1909 gen_op_load_dbat(1, 1);
1910 break;
1911 case DBAT2L:
1912 gen_op_load_dbat(1, 2);
1913 break;
1914 case DBAT3L:
1915 gen_op_load_dbat(1, 3);
1916 break;
1917 case DBAT4L:
1918 gen_op_load_dbat(1, 4);
1919 break;
1920 case DBAT5L:
1921 gen_op_load_dbat(1, 5);
1922 break;
1923 case DBAT6L:
1924 gen_op_load_dbat(1, 6);
1925 break;
1926 case DBAT7L:
1927 gen_op_load_dbat(1, 7);
1928 break;
1929 case SDR1:
1930 gen_op_load_sdr1();
1931 break;
1932 case V_TBL:
9fddaa0c 1933 gen_op_load_tbl();
79aceca5 1934 break;
9a64fbe4 1935 case V_TBU:
9fddaa0c 1936 gen_op_load_tbu();
9a64fbe4
FB		 1937 break;
1938 case DECR:
9fddaa0c 1939 gen_op_load_decr();
79aceca5
FB		 1940 break;
1941 default:
1942 gen_op_load_spr(sprn);
1943 break;
1944 }
9a64fbe4 1945 gen_op_store_T0_gpr(rD(ctx->opcode));
79aceca5
FB		 1946}
1947
1948/* mftb */
1949GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MISC)
1950{
1951 uint32_t sprn = SPR(ctx->opcode);
1952
79aceca5 1953 /* We need to update the time base before reading it */
9a64fbe4
FB		 1954 switch (sprn) {
1955 case V_TBL:
9fddaa0c 1956 gen_op_load_tbl();
79aceca5 1957 break;
9a64fbe4 1958 case V_TBU:
9fddaa0c 1959 gen_op_load_tbu();
79aceca5
FB		 1960 break;
1961 default:
9fddaa0c
FB		 1962 RET_INVAL(ctx);
1963 return;
79aceca5 1964 }
9a64fbe4 1965 gen_op_store_T0_gpr(rD(ctx->opcode));
79aceca5
FB		 1966}
1967
1968/* mtcrf */
1969GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00100801, PPC_MISC)
1970{
1971 gen_op_load_gpr_T0(rS(ctx->opcode));
1972 gen_op_store_cr(CRM(ctx->opcode));
79aceca5
FB		 1973}
1974
1975/* mtmsr */
1976GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC)
1977{
9a64fbe4 1978#if defined(CONFIG_USER_ONLY)
9fddaa0c 1979 RET_PRIVREG(ctx);
9a64fbe4
FB		 1980#else
1981 if (!ctx->supervisor) {
9fddaa0c
FB		 1982 RET_PRIVREG(ctx);
1983 return;
9a64fbe4 1984 }
79aceca5
FB		 1985 gen_op_load_gpr_T0(rS(ctx->opcode));
1986 gen_op_store_msr();
1987 /* Must stop the translation as machine state (may have) changed */
9fddaa0c 1988 RET_MTMSR(ctx);
9a64fbe4 1989#endif
79aceca5
FB		 1990}
1991
1992/* mtspr */
1993GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC)
1994{
1995 uint32_t sprn = SPR(ctx->opcode);
1996
9a64fbe4
FB		 1997#if 0
1998 if (loglevel > 0) {
1999 fprintf(logfile, "MTSPR %d src=%d (%d)\n", SPR_ENCODE(sprn),
2000 rS(ctx->opcode), sprn);
2001 }
2002#endif
2003#if defined(CONFIG_USER_ONLY)
2004 switch (check_spr_access(sprn, 1, 0))
2005#else
2006 switch (check_spr_access(sprn, 1, ctx->supervisor))
2007#endif
2008 {
2009 case -1:
9fddaa0c 2010 RET_EXCP(ctx, EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_SPR);
9a64fbe4
FB		 2011 break;
2012 case 0:
9fddaa0c 2013 RET_PRIVREG(ctx);
9a64fbe4
FB		 2014 break;
2015 default:
2016 break;
2017 }
79aceca5 2018 gen_op_load_gpr_T0(rS(ctx->opcode));
9a64fbe4
FB		 2019 switch (sprn) {
2020 case XER:
79aceca5 2021 gen_op_store_xer();
9a64fbe4
FB		 2022 break;
2023 case LR:
9a64fbe4
FB		 2024 gen_op_store_lr();
2025 break;
2026 case CTR:
2027 gen_op_store_ctr();
2028 break;
2029 case IBAT0U:
2030 gen_op_store_ibat(0, 0);
4b3686fa 2031 RET_MTMSR(ctx);
9a64fbe4
FB		 2032 break;
2033 case IBAT1U:
2034 gen_op_store_ibat(0, 1);
4b3686fa 2035 RET_MTMSR(ctx);
9a64fbe4
FB		 2036 break;
2037 case IBAT2U:
2038 gen_op_store_ibat(0, 2);
4b3686fa 2039 RET_MTMSR(ctx);
9a64fbe4
FB		 2040 break;
2041 case IBAT3U:
2042 gen_op_store_ibat(0, 3);
4b3686fa 2043 RET_MTMSR(ctx);
9a64fbe4
FB		 2044 break;
2045 case IBAT4U:
2046 gen_op_store_ibat(0, 4);
4b3686fa 2047 RET_MTMSR(ctx);
9a64fbe4
FB		 2048 break;
2049 case IBAT5U:
2050 gen_op_store_ibat(0, 5);
4b3686fa 2051 RET_MTMSR(ctx);
9a64fbe4
FB		 2052 break;
2053 case IBAT6U:
2054 gen_op_store_ibat(0, 6);
4b3686fa 2055 RET_MTMSR(ctx);
9a64fbe4
FB		 2056 break;
2057 case IBAT7U:
2058 gen_op_store_ibat(0, 7);
4b3686fa 2059 RET_MTMSR(ctx);
9a64fbe4
FB		 2060 break;
2061 case IBAT0L:
2062 gen_op_store_ibat(1, 0);
4b3686fa 2063 RET_MTMSR(ctx);
9a64fbe4
FB		 2064 break;
2065 case IBAT1L:
2066 gen_op_store_ibat(1, 1);
4b3686fa 2067 RET_MTMSR(ctx);
9a64fbe4
FB		 2068 break;
2069 case IBAT2L:
2070 gen_op_store_ibat(1, 2);
4b3686fa 2071 RET_MTMSR(ctx);
9a64fbe4
FB		 2072 break;
2073 case IBAT3L:
2074 gen_op_store_ibat(1, 3);
4b3686fa 2075 RET_MTMSR(ctx);
9a64fbe4
FB		 2076 break;
2077 case IBAT4L:
2078 gen_op_store_ibat(1, 4);
4b3686fa 2079 RET_MTMSR(ctx);
9a64fbe4
FB		 2080 break;
2081 case IBAT5L:
2082 gen_op_store_ibat(1, 5);
4b3686fa 2083 RET_MTMSR(ctx);
9a64fbe4
FB		 2084 break;
2085 case IBAT6L:
2086 gen_op_store_ibat(1, 6);
4b3686fa 2087 RET_MTMSR(ctx);
9a64fbe4
FB		 2088 break;
2089 case IBAT7L:
2090 gen_op_store_ibat(1, 7);
4b3686fa 2091 RET_MTMSR(ctx);
9a64fbe4
FB		 2092 break;
2093 case DBAT0U:
2094 gen_op_store_dbat(0, 0);
4b3686fa 2095 RET_MTMSR(ctx);
9a64fbe4
FB		 2096 break;
2097 case DBAT1U:
2098 gen_op_store_dbat(0, 1);
4b3686fa 2099 RET_MTMSR(ctx);
9a64fbe4
FB		 2100 break;
2101 case DBAT2U:
2102 gen_op_store_dbat(0, 2);
4b3686fa 2103 RET_MTMSR(ctx);
9a64fbe4
FB		 2104 break;
2105 case DBAT3U:
2106 gen_op_store_dbat(0, 3);
4b3686fa 2107 RET_MTMSR(ctx);
9a64fbe4
FB		 2108 break;
2109 case DBAT4U:
2110 gen_op_store_dbat(0, 4);
4b3686fa 2111 RET_MTMSR(ctx);
9a64fbe4
FB		 2112 break;
2113 case DBAT5U:
2114 gen_op_store_dbat(0, 5);
4b3686fa 2115 RET_MTMSR(ctx);
9a64fbe4
FB		 2116 break;
2117 case DBAT6U:
2118 gen_op_store_dbat(0, 6);
4b3686fa 2119 RET_MTMSR(ctx);
9a64fbe4
FB		 2120 break;
2121 case DBAT7U:
2122 gen_op_store_dbat(0, 7);
4b3686fa 2123 RET_MTMSR(ctx);
9a64fbe4
FB		 2124 break;
2125 case DBAT0L:
2126 gen_op_store_dbat(1, 0);
4b3686fa 2127 RET_MTMSR(ctx);
9a64fbe4
FB		 2128 break;
2129 case DBAT1L:
2130 gen_op_store_dbat(1, 1);
4b3686fa 2131 RET_MTMSR(ctx);
9a64fbe4
FB		 2132 break;
2133 case DBAT2L:
2134 gen_op_store_dbat(1, 2);
4b3686fa 2135 RET_MTMSR(ctx);
9a64fbe4
FB		 2136 break;
2137 case DBAT3L:
2138 gen_op_store_dbat(1, 3);
4b3686fa 2139 RET_MTMSR(ctx);
9a64fbe4
FB		 2140 break;
2141 case DBAT4L:
2142 gen_op_store_dbat(1, 4);
4b3686fa 2143 RET_MTMSR(ctx);
9a64fbe4
FB		 2144 break;
2145 case DBAT5L:
2146 gen_op_store_dbat(1, 5);
4b3686fa 2147 RET_MTMSR(ctx);
9a64fbe4
FB		 2148 break;
2149 case DBAT6L:
2150 gen_op_store_dbat(1, 6);
4b3686fa 2151 RET_MTMSR(ctx);
9a64fbe4
FB		 2152 break;
2153 case DBAT7L:
2154 gen_op_store_dbat(1, 7);
4b3686fa 2155 RET_MTMSR(ctx);
9a64fbe4
FB		 2156 break;
2157 case SDR1:
2158 gen_op_store_sdr1();
4b3686fa 2159 RET_MTMSR(ctx);
9a64fbe4
FB		 2160 break;
2161 case O_TBL:
9fddaa0c 2162 gen_op_store_tbl();
9a64fbe4
FB		 2163 break;
2164 case O_TBU:
9fddaa0c 2165 gen_op_store_tbu();
9a64fbe4
FB		 2166 break;
2167 case DECR:
2168 gen_op_store_decr();
9a64fbe4
FB		 2169 break;
2170 default:
79aceca5 2171 gen_op_store_spr(sprn);
9a64fbe4 2172 break;
79aceca5 2173 }
79aceca5
FB		 2174}
2175
2176/*** Cache management ***/
2177/* For now, all those will be implemented as nop:
2178 * this is valid, regarding the PowerPC specs...
9a64fbe4 2179 * We just have to flush tb while invalidating instruction cache lines...
79aceca5
FB		 2180 */
2181/* dcbf */
9a64fbe4 2182GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03E00001, PPC_CACHE)
79aceca5 2183{
a541f297
FB		 2184 if (rA(ctx->opcode) == 0) {
2185 gen_op_load_gpr_T0(rB(ctx->opcode));
2186 } else {
2187 gen_op_load_gpr_T0(rA(ctx->opcode));
2188 gen_op_load_gpr_T1(rB(ctx->opcode));
2189 gen_op_add();
2190 }
2191 op_ldst(lbz);
79aceca5
FB		 2192}
2193
2194/* dcbi (Supervisor only) */
9a64fbe4 2195GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE)
79aceca5 2196{
a541f297 2197#if defined(CONFIG_USER_ONLY)
9fddaa0c 2198 RET_PRIVOPC(ctx);
a541f297
FB		 2199#else
2200 if (!ctx->supervisor) {
9fddaa0c
FB		 2201 RET_PRIVOPC(ctx);
2202 return;
9a64fbe4 2203 }
a541f297
FB		 2204 if (rA(ctx->opcode) == 0) {
2205 gen_op_load_gpr_T0(rB(ctx->opcode));
2206 } else {
2207 gen_op_load_gpr_T0(rA(ctx->opcode));
2208 gen_op_load_gpr_T1(rB(ctx->opcode));
2209 gen_op_add();
2210 }
2211 op_ldst(lbz);
2212 op_ldst(stb);
2213#endif
79aceca5
FB		 2214}
2215
2216/* dcdst */
9a64fbe4 2217GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE)
79aceca5 2218{
a541f297
FB		 2219 if (rA(ctx->opcode) == 0) {
2220 gen_op_load_gpr_T0(rB(ctx->opcode));
2221 } else {
2222 gen_op_load_gpr_T0(rA(ctx->opcode));
2223 gen_op_load_gpr_T1(rB(ctx->opcode));
2224 gen_op_add();
2225 }
2226 op_ldst(lbz);
79aceca5
FB		 2227}
2228
2229/* dcbt */
9a64fbe4 2230GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x03E00001, PPC_CACHE)
79aceca5 2231{
79aceca5
FB		 2232}
2233
2234/* dcbtst */
9a64fbe4 2235GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x03E00001, PPC_CACHE)
79aceca5 2236{
79aceca5
FB		 2237}
2238
2239/* dcbz */
9a64fbe4
FB		 2240#if defined(CONFIG_USER_ONLY)
2241#define op_dcbz() gen_op_dcbz_raw()
2242#else
2243#define op_dcbz() (*gen_op_dcbz[ctx->mem_idx])()
2244static GenOpFunc *gen_op_dcbz[] = {
2245 &gen_op_dcbz_user,
2246 &gen_op_dcbz_kernel,
2247};
2248#endif
2249
2250GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE)
79aceca5 2251{
fb0eaffc
FB		 2252 if (rA(ctx->opcode) == 0) {
2253 gen_op_load_gpr_T0(rB(ctx->opcode));
fb0eaffc
FB		 2254 } else {
2255 gen_op_load_gpr_T0(rA(ctx->opcode));
2256 gen_op_load_gpr_T1(rB(ctx->opcode));
9a64fbe4 2257 gen_op_add();
fb0eaffc 2258 }
9a64fbe4 2259 op_dcbz();
4b3686fa 2260 gen_op_check_reservation();
79aceca5
FB		 2261}
2262
2263/* icbi */
9a64fbe4 2264GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE)
79aceca5 2265{
fb0eaffc
FB		 2266 if (rA(ctx->opcode) == 0) {
2267 gen_op_load_gpr_T0(rB(ctx->opcode));
fb0eaffc
FB		 2268 } else {
2269 gen_op_load_gpr_T0(rA(ctx->opcode));
2270 gen_op_load_gpr_T1(rB(ctx->opcode));
9a64fbe4 2271 gen_op_add();
fb0eaffc 2272 }
9a64fbe4 2273 gen_op_icbi();
79aceca5
FB		 2274}
2275
2276/* Optional: */
2277/* dcba */
9a64fbe4 2278GEN_HANDLER(dcba, 0x1F, 0x16, 0x07, 0x03E00001, PPC_CACHE_OPT)
79aceca5 2279{
79aceca5
FB		 2280}
2281
2282/*** Segment register manipulation ***/
2283/* Supervisor only: */
2284/* mfsr */
2285GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT)
2286{
9a64fbe4 2287#if defined(CONFIG_USER_ONLY)
9fddaa0c 2288 RET_PRIVREG(ctx);
9a64fbe4
FB		 2289#else
2290 if (!ctx->supervisor) {
9fddaa0c
FB		 2291 RET_PRIVREG(ctx);
2292 return;
9a64fbe4
FB		 2293 }
2294 gen_op_load_sr(SR(ctx->opcode));
2295 gen_op_store_T0_gpr(rD(ctx->opcode));
2296#endif
79aceca5
FB		 2297}
2298
2299/* mfsrin */
9a64fbe4 2300GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT)
79aceca5 2301{
9a64fbe4 2302#if defined(CONFIG_USER_ONLY)
9fddaa0c 2303 RET_PRIVREG(ctx);
9a64fbe4
FB		 2304#else
2305 if (!ctx->supervisor) {
9fddaa0c
FB		 2306 RET_PRIVREG(ctx);
2307 return;
9a64fbe4
FB		 2308 }
2309 gen_op_load_gpr_T1(rB(ctx->opcode));
2310 gen_op_load_srin();
2311 gen_op_store_T0_gpr(rD(ctx->opcode));
2312#endif
79aceca5
FB		 2313}
2314
2315/* mtsr */
e63c59cb 2316GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT)
79aceca5 2317{
9a64fbe4 2318#if defined(CONFIG_USER_ONLY)
9fddaa0c 2319 RET_PRIVREG(ctx);
9a64fbe4
FB		 2320#else
2321 if (!ctx->supervisor) {
9fddaa0c
FB		 2322 RET_PRIVREG(ctx);
2323 return;
9a64fbe4
FB		 2324 }
2325 gen_op_load_gpr_T0(rS(ctx->opcode));
2326 gen_op_store_sr(SR(ctx->opcode));
9a64fbe4 2327#endif
79aceca5
FB		 2328}
2329
2330/* mtsrin */
9a64fbe4 2331GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT)
79aceca5 2332{
9a64fbe4 2333#if defined(CONFIG_USER_ONLY)
9fddaa0c 2334 RET_PRIVREG(ctx);
9a64fbe4
FB		 2335#else
2336 if (!ctx->supervisor) {
9fddaa0c
FB		 2337 RET_PRIVREG(ctx);
2338 return;
9a64fbe4
FB		 2339 }
2340 gen_op_load_gpr_T0(rS(ctx->opcode));
2341 gen_op_load_gpr_T1(rB(ctx->opcode));
2342 gen_op_store_srin();
9a64fbe4 2343#endif
79aceca5
FB		 2344}
2345
2346/*** Lookaside buffer management ***/
2347/* Optional & supervisor only: */
2348/* tlbia */
9a64fbe4 2349GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_OPT)
79aceca5 2350{
9a64fbe4 2351#if defined(CONFIG_USER_ONLY)
9fddaa0c 2352 RET_PRIVOPC(ctx);
9a64fbe4
FB		 2353#else
2354 if (!ctx->supervisor) {
9fddaa0c
FB		 2355 if (loglevel)
2356 fprintf(logfile, "%s: ! supervisor\n", __func__);
2357 RET_PRIVOPC(ctx);
2358 return;
9a64fbe4
FB		 2359 }
2360 gen_op_tlbia();
4b3686fa 2361 RET_MTMSR(ctx);
9a64fbe4 2362#endif
79aceca5
FB		 2363}
2364
2365/* tlbie */
9a64fbe4 2366GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM)
79aceca5 2367{
9a64fbe4 2368#if defined(CONFIG_USER_ONLY)
9fddaa0c 2369 RET_PRIVOPC(ctx);
9a64fbe4
FB		 2370#else
2371 if (!ctx->supervisor) {
9fddaa0c
FB		 2372 RET_PRIVOPC(ctx);
2373 return;
9a64fbe4
FB		 2374 }
2375 gen_op_load_gpr_T0(rB(ctx->opcode));
2376 gen_op_tlbie();
4b3686fa 2377 RET_MTMSR(ctx);
9a64fbe4 2378#endif
79aceca5
FB		 2379}
2380
2381/* tlbsync */
e63c59cb 2382GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM)
79aceca5 2383{
9a64fbe4 2384#if defined(CONFIG_USER_ONLY)
9fddaa0c 2385 RET_PRIVOPC(ctx);
9a64fbe4
FB		 2386#else
2387 if (!ctx->supervisor) {
9fddaa0c
FB		 2388 RET_PRIVOPC(ctx);
2389 return;
9a64fbe4
FB		 2390 }
2391 /* This has no effect: it should ensure that all previous
2392 * tlbie have completed
2393 */
4b3686fa 2394 RET_MTMSR(ctx);
9a64fbe4 2395#endif
79aceca5
FB		 2396}
2397
2398/*** External control ***/
2399/* Optional: */
2400/* eciwx */
9a64fbe4
FB		 2401#if defined(CONFIG_USER_ONLY)
2402#define op_eciwx() gen_op_eciwx_raw()
2403#define op_ecowx() gen_op_ecowx_raw()
2404#else
2405#define op_eciwx() (*gen_op_eciwx[ctx->mem_idx])()
2406#define op_ecowx() (*gen_op_ecowx[ctx->mem_idx])()
2407static GenOpFunc *gen_op_eciwx[] = {
2408 &gen_op_eciwx_user,
2409 &gen_op_eciwx_kernel,
2410};
2411static GenOpFunc *gen_op_ecowx[] = {
2412 &gen_op_ecowx_user,
2413 &gen_op_ecowx_kernel,
2414};
2415#endif
2416
79aceca5
FB		 2417GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN)
2418{
9a64fbe4
FB		 2419 /* Should check EAR[E] & alignment ! */
2420 if (rA(ctx->opcode) == 0) {
2421 gen_op_load_gpr_T0(rB(ctx->opcode));
2422 } else {
2423 gen_op_load_gpr_T0(rA(ctx->opcode));
2424 gen_op_load_gpr_T1(rB(ctx->opcode));
2425 gen_op_add();
2426 }
2427 op_eciwx();
2428 gen_op_store_T0_gpr(rD(ctx->opcode));
79aceca5
FB		 2429}
2430
2431/* ecowx */
2432GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN)
2433{
9a64fbe4
FB		 2434 /* Should check EAR[E] & alignment ! */
2435 if (rA(ctx->opcode) == 0) {
2436 gen_op_load_gpr_T0(rB(ctx->opcode));
2437 } else {
2438 gen_op_load_gpr_T0(rA(ctx->opcode));
2439 gen_op_load_gpr_T1(rB(ctx->opcode));
2440 gen_op_add();
2441 }
2442 gen_op_load_gpr_T2(rS(ctx->opcode));
2443 op_ecowx();
79aceca5
FB		 2444}
2445
2446/* End opcode list */
2447GEN_OPCODE_MARK(end);
2448
2449/*****************************************************************************/
9a64fbe4 2450#include <stdlib.h>
79aceca5 2451#include <string.h>
9a64fbe4
FB		 2452
2453int fflush (FILE *stream);
79aceca5
FB		 2454
2455/* Main ppc opcodes table:
2456 * at init, all opcodes are invalids
2457 */
2458static opc_handler_t *ppc_opcodes[0x40];
2459
2460/* Opcode types */
2461enum {
2462 PPC_DIRECT = 0, /* Opcode routine */
2463 PPC_INDIRECT = 1, /* Indirect opcode table */
2464};
2465
2466static inline int is_indirect_opcode (void *handler)
2467{
2468 return ((unsigned long)handler & 0x03) == PPC_INDIRECT;
2469}
2470
2471static inline opc_handler_t **ind_table(void *handler)
2472{
2473 return (opc_handler_t **)((unsigned long)handler & ~3);
2474}
2475
9a64fbe4 2476/* Instruction table creation */
79aceca5
FB		 2477/* Opcodes tables creation */
2478static void fill_new_table (opc_handler_t **table, int len)
2479{
2480 int i;
2481
2482 for (i = 0; i < len; i++)
2483 table[i] = &invalid_handler;
2484}
2485
2486static int create_new_table (opc_handler_t **table, unsigned char idx)
2487{
2488 opc_handler_t **tmp;
2489
2490 tmp = malloc(0x20 * sizeof(opc_handler_t));
2491 if (tmp == NULL)
2492 return -1;
2493 fill_new_table(tmp, 0x20);
2494 table[idx] = (opc_handler_t *)((unsigned long)tmp | PPC_INDIRECT);
2495
2496 return 0;
2497}
2498
2499static int insert_in_table (opc_handler_t **table, unsigned char idx,
2500 opc_handler_t *handler)
2501{
2502 if (table[idx] != &invalid_handler)
2503 return -1;
2504 table[idx] = handler;
2505
2506 return 0;
2507}
2508
9a64fbe4
FB		 2509static int register_direct_insn (opc_handler_t **ppc_opcodes,
2510 unsigned char idx, opc_handler_t *handler)
79aceca5
FB		 2511{
2512 if (insert_in_table(ppc_opcodes, idx, handler) < 0) {
9a64fbe4 2513 printf("*** ERROR: opcode %02x already assigned in main "
79aceca5
FB		 2514 "opcode table\n", idx);
2515 return -1;
2516 }
2517
2518 return 0;
2519}
2520
2521static int register_ind_in_table (opc_handler_t **table,
2522 unsigned char idx1, unsigned char idx2,
2523 opc_handler_t *handler)
2524{
2525 if (table[idx1] == &invalid_handler) {
2526 if (create_new_table(table, idx1) < 0) {
9a64fbe4 2527 printf("*** ERROR: unable to create indirect table "
79aceca5
FB		 2528 "idx=%02x\n", idx1);
2529 return -1;
2530 }
2531 } else {
2532 if (!is_indirect_opcode(table[idx1])) {
9a64fbe4 2533 printf("*** ERROR: idx %02x already assigned to a direct "
79aceca5
FB		 2534 "opcode\n", idx1);
2535 return -1;
2536 }
2537 }
2538 if (handler != NULL &&
2539 insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) {
9a64fbe4 2540 printf("*** ERROR: opcode %02x already assigned in "
79aceca5
FB		 2541 "opcode table %02x\n", idx2, idx1);
2542 return -1;
2543 }
2544
2545 return 0;
2546}
2547
9a64fbe4
FB		 2548static int register_ind_insn (opc_handler_t **ppc_opcodes,
2549 unsigned char idx1, unsigned char idx2,
79aceca5
FB		 2550 opc_handler_t *handler)
2551{
2552 int ret;
2553
2554 ret = register_ind_in_table(ppc_opcodes, idx1, idx2, handler);
2555
2556 return ret;
2557}
2558
9a64fbe4
FB		 2559static int register_dblind_insn (opc_handler_t **ppc_opcodes,
2560 unsigned char idx1, unsigned char idx2,
79aceca5
FB		 2561 unsigned char idx3, opc_handler_t *handler)
2562{
2563 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
9a64fbe4 2564 printf("*** ERROR: unable to join indirect table idx "
79aceca5
FB		 2565 "[%02x-%02x]\n", idx1, idx2);
2566 return -1;
2567 }
2568 if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3,
2569 handler) < 0) {
9a64fbe4 2570 printf("*** ERROR: unable to insert opcode "
79aceca5
FB		 2571 "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
2572 return -1;
2573 }
2574
2575 return 0;
2576}
2577
9a64fbe4 2578static int register_insn (opc_handler_t **ppc_opcodes, opcode_t *insn)
79aceca5
FB		 2579{
2580 if (insn->opc2 != 0xFF) {
2581 if (insn->opc3 != 0xFF) {
9a64fbe4
FB		 2582 if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2,
2583 insn->opc3, &insn->handler) < 0)
79aceca5
FB		 2584 return -1;
2585 } else {
9a64fbe4
FB		 2586 if (register_ind_insn(ppc_opcodes, insn->opc1,
2587 insn->opc2, &insn->handler) < 0)
79aceca5
FB		 2588 return -1;
2589 }
2590 } else {
9a64fbe4 2591 if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0)
79aceca5
FB		 2592 return -1;
2593 }
2594
2595 return 0;
2596}
2597
2598static int test_opcode_table (opc_handler_t **table, int len)
2599{
2600 int i, count, tmp;
2601
2602 for (i = 0, count = 0; i < len; i++) {
2603 /* Consistency fixup */
2604 if (table[i] == NULL)
2605 table[i] = &invalid_handler;
2606 if (table[i] != &invalid_handler) {
2607 if (is_indirect_opcode(table[i])) {
2608 tmp = test_opcode_table(ind_table(table[i]), 0x20);
2609 if (tmp == 0) {
2610 free(table[i]);
2611 table[i] = &invalid_handler;
2612 } else {
2613 count++;
2614 }
2615 } else {
2616 count++;
2617 }
2618 }
2619 }
2620
2621 return count;
2622}
2623
9a64fbe4 2624static void fix_opcode_tables (opc_handler_t **ppc_opcodes)
79aceca5
FB		 2625{
2626 if (test_opcode_table(ppc_opcodes, 0x40) == 0)
9a64fbe4 2627 printf("*** WARNING: no opcode defined !\n");
79aceca5
FB		 2628}
2629
9a64fbe4 2630#define SPR_RIGHTS(rw, priv) (1 << ((2 * (priv)) + (rw)))
79aceca5
FB		 2631#define SPR_UR SPR_RIGHTS(0, 0)
2632#define SPR_UW SPR_RIGHTS(1, 0)
2633#define SPR_SR SPR_RIGHTS(0, 1)
2634#define SPR_SW SPR_RIGHTS(1, 1)
2635
2636#define spr_set_rights(spr, rights) \
2637do { \
2638 spr_access[(spr) >> 1] |= ((rights) << (4 * ((spr) & 1))); \
2639} while (0)
2640
9a64fbe4 2641static void init_spr_rights (uint32_t pvr)
79aceca5
FB		 2642{
2643 /* XER (SPR 1) */
9a64fbe4 2644 spr_set_rights(XER, SPR_UR | SPR_UW | SPR_SR | SPR_SW);
79aceca5 2645 /* LR (SPR 8) */
9a64fbe4 2646 spr_set_rights(LR, SPR_UR | SPR_UW | SPR_SR | SPR_SW);
79aceca5 2647 /* CTR (SPR 9) */
9a64fbe4 2648 spr_set_rights(CTR, SPR_UR | SPR_UW | SPR_SR | SPR_SW);
79aceca5 2649 /* TBL (SPR 268) */
9a64fbe4 2650 spr_set_rights(V_TBL, SPR_UR | SPR_SR);
79aceca5 2651 /* TBU (SPR 269) */
9a64fbe4 2652 spr_set_rights(V_TBU, SPR_UR | SPR_SR);
79aceca5 2653 /* DSISR (SPR 18) */
9a64fbe4 2654 spr_set_rights(DSISR, SPR_SR | SPR_SW);
79aceca5 2655 /* DAR (SPR 19) */
9a64fbe4 2656 spr_set_rights(DAR, SPR_SR | SPR_SW);
79aceca5 2657 /* DEC (SPR 22) */
9a64fbe4 2658 spr_set_rights(DECR, SPR_SR | SPR_SW);
79aceca5 2659 /* SDR1 (SPR 25) */
9a64fbe4
FB		 2660 spr_set_rights(SDR1, SPR_SR | SPR_SW);
2661 /* SRR0 (SPR 26) */
2662 spr_set_rights(SRR0, SPR_SR | SPR_SW);
2663 /* SRR1 (SPR 27) */
2664 spr_set_rights(SRR1, SPR_SR | SPR_SW);
79aceca5 2665 /* SPRG0 (SPR 272) */
9a64fbe4 2666 spr_set_rights(SPRG0, SPR_SR | SPR_SW);
79aceca5 2667 /* SPRG1 (SPR 273) */
9a64fbe4 2668 spr_set_rights(SPRG1, SPR_SR | SPR_SW);
79aceca5 2669 /* SPRG2 (SPR 274) */
9a64fbe4 2670 spr_set_rights(SPRG2, SPR_SR | SPR_SW);
79aceca5 2671 /* SPRG3 (SPR 275) */
9a64fbe4 2672 spr_set_rights(SPRG3, SPR_SR | SPR_SW);
79aceca5 2673 /* ASR (SPR 280) */
9a64fbe4 2674 spr_set_rights(ASR, SPR_SR | SPR_SW);
79aceca5 2675 /* EAR (SPR 282) */
9a64fbe4
FB		 2676 spr_set_rights(EAR, SPR_SR | SPR_SW);
2677 /* TBL (SPR 284) */
2678 spr_set_rights(O_TBL, SPR_SW);
2679 /* TBU (SPR 285) */
2680 spr_set_rights(O_TBU, SPR_SW);
2681 /* PVR (SPR 287) */
2682 spr_set_rights(PVR, SPR_SR);
79aceca5 2683 /* IBAT0U (SPR 528) */
9a64fbe4 2684 spr_set_rights(IBAT0U, SPR_SR | SPR_SW);
79aceca5 2685 /* IBAT0L (SPR 529) */
9a64fbe4 2686 spr_set_rights(IBAT0L, SPR_SR | SPR_SW);
79aceca5 2687 /* IBAT1U (SPR 530) */
9a64fbe4 2688 spr_set_rights(IBAT1U, SPR_SR | SPR_SW);
79aceca5 2689 /* IBAT1L (SPR 531) */
9a64fbe4 2690 spr_set_rights(IBAT1L, SPR_SR | SPR_SW);
79aceca5 2691 /* IBAT2U (SPR 532) */
9a64fbe4 2692 spr_set_rights(IBAT2U, SPR_SR | SPR_SW);
79aceca5 2693 /* IBAT2L (SPR 533) */
9a64fbe4 2694 spr_set_rights(IBAT2L, SPR_SR | SPR_SW);
79aceca5 2695 /* IBAT3U (SPR 534) */
9a64fbe4 2696 spr_set_rights(IBAT3U, SPR_SR | SPR_SW);
79aceca5 2697 /* IBAT3L (SPR 535) */
9a64fbe4 2698 spr_set_rights(IBAT3L, SPR_SR | SPR_SW);
79aceca5 2699 /* DBAT0U (SPR 536) */
9a64fbe4 2700 spr_set_rights(DBAT0U, SPR_SR | SPR_SW);
79aceca5 2701 /* DBAT0L (SPR 537) */
9a64fbe4 2702 spr_set_rights(DBAT0L, SPR_SR | SPR_SW);
79aceca5 2703 /* DBAT1U (SPR 538) */
9a64fbe4 2704 spr_set_rights(DBAT1U, SPR_SR | SPR_SW);
79aceca5 2705 /* DBAT1L (SPR 539) */
9a64fbe4 2706 spr_set_rights(DBAT1L, SPR_SR | SPR_SW);
79aceca5 2707 /* DBAT2U (SPR 540) */
9a64fbe4 2708 spr_set_rights(DBAT2U, SPR_SR | SPR_SW);
79aceca5 2709 /* DBAT2L (SPR 541) */
9a64fbe4 2710 spr_set_rights(DBAT2L, SPR_SR | SPR_SW);
79aceca5 2711 /* DBAT3U (SPR 542) */
9a64fbe4 2712 spr_set_rights(DBAT3U, SPR_SR | SPR_SW);
79aceca5 2713 /* DBAT3L (SPR 543) */
9a64fbe4 2714 spr_set_rights(DBAT3L, SPR_SR | SPR_SW);
79aceca5 2715 /* FPECR (SPR 1022) */
9a64fbe4 2716 spr_set_rights(FPECR, SPR_SR | SPR_SW);
4b3686fa
FB		 2717 /* Special registers for PPC 604 */
2718 if ((pvr & 0xFFFF0000) == 0x00040000) {
2719 /* IABR */
2720 spr_set_rights(IABR , SPR_SR | SPR_SW);
2721 /* DABR (SPR 1013) */
2722 spr_set_rights(DABR, SPR_SR | SPR_SW);
2723 /* HID0 */
2724 spr_set_rights(HID0, SPR_SR | SPR_SW);
2725 /* PIR */
9a64fbe4 2726 spr_set_rights(PIR, SPR_SR | SPR_SW);
4b3686fa
FB		 2727 /* PMC1 */
2728 spr_set_rights(PMC1, SPR_SR | SPR_SW);
2729 /* PMC2 */
2730 spr_set_rights(PMC2, SPR_SR | SPR_SW);
2731 /* MMCR0 */
2732 spr_set_rights(MMCR0, SPR_SR | SPR_SW);
2733 /* SIA */
2734 spr_set_rights(SIA, SPR_SR | SPR_SW);
2735 /* SDA */
2736 spr_set_rights(SDA, SPR_SR | SPR_SW);
2737 }
9a64fbe4
FB		 2738 /* Special registers for MPC740/745/750/755 (aka G3) & IBM 750 */
2739 if ((pvr & 0xFFFF0000) == 0x00080000 ||
2740 (pvr & 0xFFFF0000) == 0x70000000) {
2741 /* HID0 */
4b3686fa 2742 spr_set_rights(HID0, SPR_SR | SPR_SW);
9a64fbe4 2743 /* HID1 */
4b3686fa 2744 spr_set_rights(HID1, SPR_SR | SPR_SW);
9a64fbe4 2745 /* IABR */
4b3686fa 2746 spr_set_rights(IABR, SPR_SR | SPR_SW);
9a64fbe4 2747 /* ICTC */
4b3686fa 2748 spr_set_rights(ICTC, SPR_SR | SPR_SW);
9a64fbe4 2749 /* L2CR */
4b3686fa 2750 spr_set_rights(L2CR, SPR_SR | SPR_SW);
9a64fbe4 2751 /* MMCR0 */
4b3686fa 2752 spr_set_rights(MMCR0, SPR_SR | SPR_SW);
9a64fbe4 2753 /* MMCR1 */
4b3686fa 2754 spr_set_rights(MMCR1, SPR_SR | SPR_SW);
9a64fbe4 2755 /* PMC1 */
4b3686fa 2756 spr_set_rights(PMC1, SPR_SR | SPR_SW);
9a64fbe4 2757 /* PMC2 */
4b3686fa 2758 spr_set_rights(PMC2, SPR_SR | SPR_SW);
9a64fbe4 2759 /* PMC3 */
4b3686fa 2760 spr_set_rights(PMC3, SPR_SR | SPR_SW);
9a64fbe4 2761 /* PMC4 */
4b3686fa 2762 spr_set_rights(PMC4, SPR_SR | SPR_SW);
9a64fbe4 2763 /* SIA */
4b3686fa
FB		 2764 spr_set_rights(SIA, SPR_SR | SPR_SW);
2765 /* SDA */
2766 spr_set_rights(SDA, SPR_SR | SPR_SW);
9a64fbe4 2767 /* THRM1 */
4b3686fa 2768 spr_set_rights(THRM1, SPR_SR | SPR_SW);
9a64fbe4 2769 /* THRM2 */
4b3686fa 2770 spr_set_rights(THRM2, SPR_SR | SPR_SW);
9a64fbe4 2771 /* THRM3 */
4b3686fa 2772 spr_set_rights(THRM3, SPR_SR | SPR_SW);
9a64fbe4 2773 /* UMMCR0 */
4b3686fa 2774 spr_set_rights(UMMCR0, SPR_UR | SPR_UW);
9a64fbe4 2775 /* UMMCR1 */
4b3686fa 2776 spr_set_rights(UMMCR1, SPR_UR | SPR_UW);
9a64fbe4 2777 /* UPMC1 */
4b3686fa 2778 spr_set_rights(UPMC1, SPR_UR | SPR_UW);
9a64fbe4 2779 /* UPMC2 */
4b3686fa 2780 spr_set_rights(UPMC2, SPR_UR | SPR_UW);
9a64fbe4 2781 /* UPMC3 */
4b3686fa 2782 spr_set_rights(UPMC3, SPR_UR | SPR_UW);
9a64fbe4 2783 /* UPMC4 */
4b3686fa 2784 spr_set_rights(UPMC4, SPR_UR | SPR_UW);
9a64fbe4 2785 /* USIA */
4b3686fa 2786 spr_set_rights(USIA, SPR_UR | SPR_UW);
9a64fbe4
FB		 2787 }
2788 /* MPC755 has special registers */
2789 if (pvr == 0x00083100) {
2790 /* SPRG4 */
2791 spr_set_rights(SPRG4, SPR_SR | SPR_SW);
2792 /* SPRG5 */
2793 spr_set_rights(SPRG5, SPR_SR | SPR_SW);
2794 /* SPRG6 */
2795 spr_set_rights(SPRG6, SPR_SR | SPR_SW);
2796 /* SPRG7 */
2797 spr_set_rights(SPRG7, SPR_SR | SPR_SW);
2798 /* IBAT4U */
2799 spr_set_rights(IBAT4U, SPR_SR | SPR_SW);
2800 /* IBAT4L */
2801 spr_set_rights(IBAT4L, SPR_SR | SPR_SW);
2802 /* IBAT5U */
2803 spr_set_rights(IBAT5U, SPR_SR | SPR_SW);
2804 /* IBAT5L */
2805 spr_set_rights(IBAT5L, SPR_SR | SPR_SW);
2806 /* IBAT6U */
2807 spr_set_rights(IBAT6U, SPR_SR | SPR_SW);
2808 /* IBAT6L */
2809 spr_set_rights(IBAT6L, SPR_SR | SPR_SW);
2810 /* IBAT7U */
2811 spr_set_rights(IBAT7U, SPR_SR | SPR_SW);
2812 /* IBAT7L */
2813 spr_set_rights(IBAT7L, SPR_SR | SPR_SW);
2814 /* DBAT4U */
2815 spr_set_rights(DBAT4U, SPR_SR | SPR_SW);
2816 /* DBAT4L */
2817 spr_set_rights(DBAT4L, SPR_SR | SPR_SW);
2818 /* DBAT5U */
2819 spr_set_rights(DBAT5U, SPR_SR | SPR_SW);
2820 /* DBAT5L */
2821 spr_set_rights(DBAT5L, SPR_SR | SPR_SW);
2822 /* DBAT6U */
2823 spr_set_rights(DBAT6U, SPR_SR | SPR_SW);
2824 /* DBAT6L */
2825 spr_set_rights(DBAT6L, SPR_SR | SPR_SW);
2826 /* DBAT7U */
2827 spr_set_rights(DBAT7U, SPR_SR | SPR_SW);
2828 /* DBAT7L */
2829 spr_set_rights(DBAT7L, SPR_SR | SPR_SW);
2830 /* DMISS */
4b3686fa 2831 spr_set_rights(DMISS, SPR_SR | SPR_SW);
9a64fbe4 2832 /* DCMP */
4b3686fa 2833 spr_set_rights(DCMP, SPR_SR | SPR_SW);
9a64fbe4 2834 /* DHASH1 */
4b3686fa 2835 spr_set_rights(DHASH1, SPR_SR | SPR_SW);
9a64fbe4 2836 /* DHASH2 */
4b3686fa 2837 spr_set_rights(DHASH2, SPR_SR | SPR_SW);
9a64fbe4 2838 /* IMISS */
4b3686fa 2839 spr_set_rights(IMISS, SPR_SR | SPR_SW);
9a64fbe4 2840 /* ICMP */
4b3686fa 2841 spr_set_rights(ICMP, SPR_SR | SPR_SW);
9a64fbe4 2842 /* RPA */
4b3686fa 2843 spr_set_rights(RPA, SPR_SR | SPR_SW);
9a64fbe4 2844 /* HID2 */
4b3686fa 2845 spr_set_rights(HID2, SPR_SR | SPR_SW);
9a64fbe4 2846 /* L2PM */
4b3686fa 2847 spr_set_rights(L2PM, SPR_SR | SPR_SW);
9a64fbe4 2848 }
79aceca5
FB		 2849}
2850
9a64fbe4
FB		 2851/*****************************************************************************/
2852/* PPC "main stream" common instructions (no optional ones) */
79aceca5
FB		 2853
2854typedef struct ppc_proc_t {
2855 int flags;
2856 void *specific;
2857} ppc_proc_t;
2858
2859typedef struct ppc_def_t {
2860 unsigned long pvr;
2861 unsigned long pvr_mask;
2862 ppc_proc_t *proc;
2863} ppc_def_t;
2864
2865static ppc_proc_t ppc_proc_common = {
2866 .flags = PPC_COMMON,
2867 .specific = NULL,
2868};
2869
9a64fbe4
FB		 2870static ppc_proc_t ppc_proc_G3 = {
2871 .flags = PPC_750,
2872 .specific = NULL,
2873};
2874
79aceca5
FB		 2875static ppc_def_t ppc_defs[] =
2876{
9a64fbe4
FB		 2877 /* MPC740/745/750/755 (G3) */
2878 {
2879 .pvr = 0x00080000,
2880 .pvr_mask = 0xFFFF0000,
2881 .proc = &ppc_proc_G3,
2882 },
2883 /* IBM 750FX (G3 embedded) */
2884 {
2885 .pvr = 0x70000000,
2886 .pvr_mask = 0xFFFF0000,
2887 .proc = &ppc_proc_G3,
2888 },
2889 /* Fallback (generic PPC) */
79aceca5
FB		 2890 {
2891 .pvr = 0x00000000,
2892 .pvr_mask = 0x00000000,
2893 .proc = &ppc_proc_common,
2894 },
2895};
2896
9a64fbe4 2897static int create_ppc_proc (opc_handler_t **ppc_opcodes, unsigned long pvr)
79aceca5 2898{
18fba28c 2899 opcode_t *opc, *start, *end;
79aceca5
FB		 2900 int i, flags;
2901
2902 fill_new_table(ppc_opcodes, 0x40);
2903 for (i = 0; ; i++) {
2904 if ((ppc_defs[i].pvr & ppc_defs[i].pvr_mask) ==
2905 (pvr & ppc_defs[i].pvr_mask)) {
2906 flags = ppc_defs[i].proc->flags;
2907 break;
2908 }
2909 }
2910
18fba28c
FB		 2911 if (&opc_start < &opc_end) {
2912 start = &opc_start;
2913 end = &opc_end;
2914 } else {
2915 start = &opc_end;
2916 end = &opc_start;
2917 }
2918 for (opc = start + 1; opc != end; opc++) {
9a64fbe4
FB		 2919 if ((opc->handler.type & flags) != 0)
2920 if (register_insn(ppc_opcodes, opc) < 0) {
2921 printf("*** ERROR initializing PPC instruction "
79aceca5
FB		 2922 "0x%02x 0x%02x 0x%02x\n", opc->opc1, opc->opc2,
2923 opc->opc3);
2924 return -1;
2925 }
2926 }
9a64fbe4 2927 fix_opcode_tables(ppc_opcodes);
79aceca5
FB		 2928
2929 return 0;
2930}
2931
9a64fbe4 2932
79aceca5 2933/*****************************************************************************/
9a64fbe4 2934/* Misc PPC helpers */
79aceca5 2935
7fe48483
FB		 2936void cpu_dump_state(CPUState *env, FILE *f,
2937 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
2938 int flags)
79aceca5
FB		 2939{
2940 int i;
2941
7fe48483 2942 cpu_fprintf(f, "nip=0x%08x LR=0x%08x CTR=0x%08x XER=0x%08x "
9a64fbe4 2943 "MSR=0x%08x\n", env->nip, env->lr, env->ctr,
a541f297 2944 _load_xer(env), _load_msr(env));
79aceca5
FB		 2945 for (i = 0; i < 32; i++) {
2946 if ((i & 7) == 0)
7fe48483
FB		 2947 cpu_fprintf(f, "GPR%02d:", i);
2948 cpu_fprintf(f, " %08x", env->gpr[i]);
79aceca5 2949 if ((i & 7) == 7)
7fe48483 2950 cpu_fprintf(f, "\n");
79aceca5 2951 }
7fe48483 2952 cpu_fprintf(f, "CR: 0x");
79aceca5 2953 for (i = 0; i < 8; i++)
7fe48483
FB		 2954 cpu_fprintf(f, "%01x", env->crf[i]);
2955 cpu_fprintf(f, " [");
79aceca5
FB		 2956 for (i = 0; i < 8; i++) {
2957 char a = '-';
79aceca5
FB		 2958 if (env->crf[i] & 0x08)
2959 a = 'L';
2960 else if (env->crf[i] & 0x04)
2961 a = 'G';
2962 else if (env->crf[i] & 0x02)
2963 a = 'E';
7fe48483 2964 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
79aceca5 2965 }
7fe48483
FB		 2966 cpu_fprintf(f, " ] ");
2967 cpu_fprintf(f, "TB: 0x%08x %08x\n", cpu_ppc_load_tbu(env),
9fddaa0c 2968 cpu_ppc_load_tbl(env));
79aceca5
FB		 2969 for (i = 0; i < 16; i++) {
2970 if ((i & 3) == 0)
7fe48483
FB		 2971 cpu_fprintf(f, "FPR%02d:", i);
2972 cpu_fprintf(f, " %016llx", *((uint64_t *)&env->fpr[i]));
79aceca5 2973 if ((i & 3) == 3)
7fe48483 2974 cpu_fprintf(f, "\n");
79aceca5 2975 }
7fe48483 2976 cpu_fprintf(f, "SRR0 0x%08x SRR1 0x%08x DECR=0x%08x\n",
9fddaa0c 2977 env->spr[SRR0], env->spr[SRR1], cpu_ppc_load_decr(env));
7fe48483 2978 cpu_fprintf(f, "reservation 0x%08x\n", env->reserve);
79aceca5
FB		 2979}
2980
9a64fbe4
FB		 2981#if !defined(CONFIG_USER_ONLY) && defined (USE_OPENFIRMWARE)
2982int setup_machine (CPUPPCState *env, uint32_t mid);
2983#endif
2984
79aceca5
FB		 2985CPUPPCState *cpu_ppc_init(void)
2986{
2987 CPUPPCState *env;
2988
2989 cpu_exec_init();
2990
4b3686fa 2991 env = qemu_mallocz(sizeof(CPUPPCState));
79aceca5
FB		 2992 if (!env)
2993 return NULL;
9a64fbe4
FB		 2994#if !defined(CONFIG_USER_ONLY) && defined (USE_OPEN_FIRMWARE)
2995 setup_machine(env, 0);
2996#else
2997// env->spr[PVR] = 0; /* Basic PPC */
2998 env->spr[PVR] = 0x00080100; /* G3 CPU */
2999// env->spr[PVR] = 0x00083100; /* MPC755 (G3 embedded) */
3000// env->spr[PVR] = 0x00070100; /* IBM 750FX */
3001#endif
ad081323 3002 tlb_flush(env, 1);
9a64fbe4
FB		 3003#if defined (DO_SINGLE_STEP)
3004 /* Single step trace mode */
3005 msr_se = 1;
3006#endif
4b3686fa
FB		 3007 msr_fp = 1; /* Allow floating point exceptions */
3008 msr_me = 1; /* Allow machine check exceptions */
9a64fbe4
FB		 3009#if defined(CONFIG_USER_ONLY)
3010 msr_pr = 1;
4b3686fa
FB		 3011 cpu_ppc_register(env, 0x00080000);
3012#else
3013 env->nip = 0xFFFFFFFC;
9a64fbe4 3014#endif
7496f526 3015 cpu_single_env = env;
79aceca5
FB		 3016 return env;
3017}
3018
4b3686fa
FB		 3019int cpu_ppc_register (CPUPPCState *env, uint32_t pvr)
3020{
3021 env->spr[PVR] = pvr;
3022 if (create_ppc_proc(ppc_opcodes, env->spr[PVR]) < 0)
3023 return -1;
3024 init_spr_rights(env->spr[PVR]);
3025
3026 return 0;
3027}
3028
79aceca5
FB		 3029void cpu_ppc_close(CPUPPCState *env)
3030{
3031 /* Should also remove all opcode tables... */
3032 free(env);
3033}
3034
9a64fbe4 3035/*****************************************************************************/
79aceca5
FB		 3036int gen_intermediate_code_internal (CPUState *env, TranslationBlock *tb,
3037 int search_pc)
3038{
9fddaa0c 3039 DisasContext ctx, *ctxp = &ctx;
79aceca5 3040 opc_handler_t **table, *handler;
0fa85d43 3041 target_ulong pc_start;
79aceca5
FB		 3042 uint16_t *gen_opc_end;
3043 int j, lj = -1;
79aceca5
FB		 3044
3045 pc_start = tb->pc;
3046 gen_opc_ptr = gen_opc_buf;
3047 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
3048 gen_opparam_ptr = gen_opparam_buf;
046d6672 3049 ctx.nip = pc_start;
79aceca5 3050 ctx.tb = tb;
9a64fbe4
FB		 3051 ctx.exception = EXCP_NONE;
3052#if defined(CONFIG_USER_ONLY)
3053 ctx.mem_idx = 0;
3054#else
3055 ctx.supervisor = 1 - msr_pr;
3056 ctx.mem_idx = (1 - msr_pr);
3057#endif
3058#if defined (DO_SINGLE_STEP)
3059 /* Single step trace mode */
3060 msr_se = 1;
3061#endif
3062 /* Set env in case of segfault during code fetch */
3063 while (ctx.exception == EXCP_NONE && gen_opc_ptr < gen_opc_end) {
79aceca5 3064 if (search_pc) {
79aceca5
FB		 3065 j = gen_opc_ptr - gen_opc_buf;
3066 if (lj < j) {
3067 lj++;
3068 while (lj < j)
3069 gen_opc_instr_start[lj++] = 0;
046d6672 3070 gen_opc_pc[lj] = ctx.nip;
79aceca5
FB		 3071 gen_opc_instr_start[lj] = 1;
3072 }
3073 }
9fddaa0c
FB		 3074#if defined PPC_DEBUG_DISAS
3075 if (loglevel & CPU_LOG_TB_IN_ASM) {
79aceca5 3076 fprintf(logfile, "----------------\n");
046d6672 3077 fprintf(logfile, "nip=%08x super=%d ir=%d\n",
9a64fbe4
FB		 3078 ctx.nip, 1 - msr_pr, msr_ir);
3079 }
3080#endif
0fa85d43 3081 ctx.opcode = ldl_code(ctx.nip);
9fddaa0c
FB		 3082#if defined PPC_DEBUG_DISAS
3083 if (loglevel & CPU_LOG_TB_IN_ASM) {
9a64fbe4
FB		 3084 fprintf(logfile, "translate opcode %08x (%02x %02x %02x)\n",
3085 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
3086 opc3(ctx.opcode));
79aceca5
FB		 3087 }
3088#endif
046d6672 3089 ctx.nip += 4;
79aceca5
FB		 3090 table = ppc_opcodes;
3091 handler = table[opc1(ctx.opcode)];
3092 if (is_indirect_opcode(handler)) {
3093 table = ind_table(handler);
3094 handler = table[opc2(ctx.opcode)];
3095 if (is_indirect_opcode(handler)) {
3096 table = ind_table(handler);
3097 handler = table[opc3(ctx.opcode)];
3098 }
3099 }
3100 /* Is opcode *REALLY* valid ? */
79aceca5 3101 if (handler->handler == &gen_invalid) {
4b3686fa 3102 if (loglevel > 0) {
79aceca5 3103 fprintf(logfile, "invalid/unsupported opcode: "
4b3686fa 3104 "%02x - %02x - %02x (%08x) 0x%08x %d\n",
9a64fbe4 3105 opc1(ctx.opcode), opc2(ctx.opcode),
4b3686fa
FB		 3106 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, msr_ir);
3107 } else {
3108 printf("invalid/unsupported opcode: "
3109 "%02x - %02x - %02x (%08x) 0x%08x %d\n",
3110 opc1(ctx.opcode), opc2(ctx.opcode),
3111 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, msr_ir);
3112 }
79aceca5 3113 } else {
4b3686fa
FB		 3114 if ((ctx.opcode & handler->inval) != 0) {
3115 if (loglevel > 0) {
79aceca5 3116 fprintf(logfile, "invalid bits: %08x for opcode: "
046d6672 3117 "%02x -%02x - %02x (0x%08x) (0x%08x)\n",
79aceca5
FB		 3118 ctx.opcode & handler->inval, opc1(ctx.opcode),
3119 opc2(ctx.opcode), opc3(ctx.opcode),
046d6672 3120 ctx.opcode, ctx.nip - 4);
9a64fbe4
FB		 3121 } else {
3122 printf("invalid bits: %08x for opcode: "
046d6672 3123 "%02x -%02x - %02x (0x%08x) (0x%08x)\n",
9a64fbe4
FB		 3124 ctx.opcode & handler->inval, opc1(ctx.opcode),
3125 opc2(ctx.opcode), opc3(ctx.opcode),
046d6672 3126 ctx.opcode, ctx.nip - 4);
9a64fbe4 3127 }
4b3686fa
FB		 3128 RET_INVAL(ctxp);
3129 break;
79aceca5 3130 }
79aceca5 3131 }
4b3686fa 3132 (*(handler->handler))(&ctx);
9a64fbe4
FB		 3133 /* Check trace mode exceptions */
3134 if ((msr_be && ctx.exception == EXCP_BRANCH) ||
3135 /* Check in single step trace mode
3136 * we need to stop except if:
3137 * - rfi, trap or syscall
3138 * - first instruction of an exception handler
3139 */
046d6672
FB		 3140 (msr_se && (ctx.nip < 0x100 ||
3141 ctx.nip > 0xF00 ||
3142 (ctx.nip & 0xFC) != 0x04) &&
9a64fbe4
FB		 3143 ctx.exception != EXCP_SYSCALL && ctx.exception != EXCP_RFI &&
3144 ctx.exception != EXCP_TRAP)) {
9fddaa0c 3145 RET_EXCP(ctxp, EXCP_TRACE, 0);
9a64fbe4 3146 }
a541f297 3147 /* if we reach a page boundary, stop generation */
046d6672 3148 if ((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) {
9fddaa0c 3149 RET_EXCP(ctxp, EXCP_BRANCH, 0);
79aceca5 3150 }
9a64fbe4 3151 }
9fddaa0c
FB		 3152 if (ctx.exception == EXCP_NONE) {
3153 gen_op_b((unsigned long)ctx.tb, ctx.nip);
3154 } else if (ctx.exception != EXCP_BRANCH) {
3155 gen_op_set_T0(0);
9a64fbe4
FB		 3156 }
3157#if 1
79aceca5
FB		 3158 /* TO BE FIXED: T0 hasn't got a proper value, which makes tb_add_jump
3159 * do bad business and then qemu crashes !
3160 */
3161 gen_op_set_T0(0);
9a64fbe4 3162#endif
79aceca5
FB		 3163 /* Generate the return instruction */
3164 gen_op_exit_tb();
3165 *gen_opc_ptr = INDEX_op_end;
9a64fbe4
FB		 3166 if (search_pc) {
3167 j = gen_opc_ptr - gen_opc_buf;
3168 lj++;
3169 while (lj <= j)
3170 gen_opc_instr_start[lj++] = 0;
79aceca5 3171 tb->size = 0;
985a19d6 3172#if 0
9a64fbe4
FB		 3173 if (loglevel > 0) {
3174 page_dump(logfile);
3175 }
985a19d6 3176#endif
9a64fbe4 3177 } else {
046d6672 3178 tb->size = ctx.nip - pc_start;
9a64fbe4 3179 }
79aceca5 3180#ifdef DEBUG_DISAS
9fddaa0c 3181 if (loglevel & CPU_LOG_TB_CPU) {
9a64fbe4 3182 fprintf(logfile, "---------------- excp: %04x\n", ctx.exception);
7fe48483 3183 cpu_dump_state(env, logfile, fprintf, 0);
9fddaa0c
FB		 3184 }
3185 if (loglevel & CPU_LOG_TB_IN_ASM) {
0fa85d43
FB		 3186 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
3187 target_disas(logfile, pc_start, ctx.nip - pc_start, 0);
79aceca5 3188 fprintf(logfile, "\n");
9fddaa0c
FB		 3189 }
3190 if (loglevel & CPU_LOG_TB_OP) {
79aceca5
FB		 3191 fprintf(logfile, "OP:\n");
3192 dump_ops(gen_opc_buf, gen_opparam_buf);
3193 fprintf(logfile, "\n");
3194 }
3195#endif
79aceca5
FB		 3196 return 0;
3197}
3198
9a64fbe4 3199int gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
79aceca5
FB		 3200{
3201 return gen_intermediate_code_internal(env, tb, 0);
3202}
3203
9a64fbe4 3204int gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
79aceca5
FB		 3205{
3206 return gen_intermediate_code_internal(env, tb, 1);
3207}
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