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target-ppc: xer access prototypes no more used & implemented
[qemu.git] / target-ppc / translate.c
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79aceca5 1/*
3fc6c082 2 * PowerPC emulation for qemu: main translation routines.
5fafdf24 3 *
76a66253 4 * Copyright (c) 2003-2007 Jocelyn Mayer
79aceca5
FB		 5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
c6a1c22b
FB		 20#include <stdarg.h>
21#include <stdlib.h>
22#include <stdio.h>
23#include <string.h>
24#include <inttypes.h>
25
79aceca5 26#include "cpu.h"
c6a1c22b 27#include "exec-all.h"
79aceca5 28#include "disas.h"
f10dc08e 29#include "helper.h"
57fec1fe 30#include "tcg-op.h"
ca10f867 31#include "qemu-common.h"
79aceca5 32
8cbcb4fa
AJ		 33#define CPU_SINGLE_STEP 0x1
34#define CPU_BRANCH_STEP 0x2
35#define GDBSTUB_SINGLE_STEP 0x4
36
a750fc0b 37/* Include definitions for instructions classes and implementations flags */
79aceca5 38//#define DO_SINGLE_STEP
9fddaa0c 39//#define PPC_DEBUG_DISAS
76a66253 40//#define DO_PPC_STATISTICS
7c58044c 41//#define OPTIMIZE_FPRF_UPDATE
79aceca5 42
a750fc0b
JM		 43/*****************************************************************************/
44/* Code translation helpers */
c53be334 45
f78fb44e
AJ		 46/* global register indexes */
47static TCGv cpu_env;
1d542695 48static char cpu_reg_names[10*3 + 22*4 /* GPR */
f78fb44e 49#if !defined(TARGET_PPC64)
1d542695 50 + 10*4 + 22*5 /* SPE GPRh */
f78fb44e 51#endif
a5e26afa 52 + 10*4 + 22*5 /* FPR */
47e4661c
AJ		 53 + 2*(10*6 + 22*7) /* AVRh, AVRl */
54 + 8*5 /* CRF */];
f78fb44e
AJ		 55static TCGv cpu_gpr[32];
56#if !defined(TARGET_PPC64)
57static TCGv cpu_gprh[32];
58#endif
a5e26afa 59static TCGv cpu_fpr[32];
1d542695 60static TCGv cpu_avrh[32], cpu_avrl[32];
47e4661c 61static TCGv cpu_crf[8];
bd568f18 62static TCGv cpu_nip;
cfdcd37a
AJ		 63static TCGv cpu_ctr;
64static TCGv cpu_lr;
3d7b417e 65static TCGv cpu_xer;
e1571908 66static TCGv cpu_fpscr;
f78fb44e
AJ		 67
68/* dyngen register indexes */
69static TCGv cpu_T[3];
70#if defined(TARGET_PPC64)
71#define cpu_T64 cpu_T
72#else
73static TCGv cpu_T64[3];
74#endif
a5e26afa 75static TCGv cpu_FT[3];
1d542695 76static TCGv cpu_AVRh[3], cpu_AVRl[3];
2e70f6ef
PB		 77
78#include "gen-icount.h"
79
80void ppc_translate_init(void)
81{
f78fb44e
AJ		 82 int i;
83 char* p;
b2437bf2 84 static int done_init = 0;
f78fb44e 85
2e70f6ef
PB		 86 if (done_init)
87 return;
f78fb44e 88
2e70f6ef 89 cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");
1c73fe5b
AJ		 90#if TARGET_LONG_BITS > HOST_LONG_BITS
91 cpu_T[0] = tcg_global_mem_new(TCG_TYPE_TL,
92 TCG_AREG0, offsetof(CPUState, t0), "T0");
93 cpu_T[1] = tcg_global_mem_new(TCG_TYPE_TL,
94 TCG_AREG0, offsetof(CPUState, t1), "T1");
95 cpu_T[2] = tcg_global_mem_new(TCG_TYPE_TL,
96 TCG_AREG0, offsetof(CPUState, t2), "T2");
97#else
98 cpu_T[0] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG1, "T0");
99 cpu_T[1] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG2, "T1");
100 cpu_T[2] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG3, "T2");
101#endif
f78fb44e
AJ		 102#if !defined(TARGET_PPC64)
103 cpu_T64[0] = tcg_global_mem_new(TCG_TYPE_I64,
bd7d9a6d 104 TCG_AREG0, offsetof(CPUState, t0_64),
f78fb44e
AJ		 105 "T0_64");
106 cpu_T64[1] = tcg_global_mem_new(TCG_TYPE_I64,
bd7d9a6d 107 TCG_AREG0, offsetof(CPUState, t1_64),
f78fb44e
AJ		 108 "T1_64");
109 cpu_T64[2] = tcg_global_mem_new(TCG_TYPE_I64,
bd7d9a6d 110 TCG_AREG0, offsetof(CPUState, t2_64),
f78fb44e
AJ		 111 "T2_64");
112#endif
a5e26afa
AJ		 113
114 cpu_FT[0] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
115 offsetof(CPUState, ft0), "FT0");
116 cpu_FT[1] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
117 offsetof(CPUState, ft1), "FT1");
118 cpu_FT[2] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
119 offsetof(CPUState, ft2), "FT2");
120
1d542695
AJ		 121 cpu_AVRh[0] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
122 offsetof(CPUState, avr0.u64[0]), "AVR0H");
123 cpu_AVRl[0] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
124 offsetof(CPUState, avr0.u64[1]), "AVR0L");
125 cpu_AVRh[1] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
126 offsetof(CPUState, avr1.u64[0]), "AVR1H");
127 cpu_AVRl[1] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
128 offsetof(CPUState, avr1.u64[1]), "AVR1L");
129 cpu_AVRh[2] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
130 offsetof(CPUState, avr2.u64[0]), "AVR2H");
131 cpu_AVRl[2] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
132 offsetof(CPUState, avr2.u64[1]), "AVR2L");
133
f78fb44e 134 p = cpu_reg_names;
47e4661c
AJ		 135
136 for (i = 0; i < 8; i++) {
137 sprintf(p, "crf%d", i);
138 cpu_crf[i] = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
139 offsetof(CPUState, crf[i]), p);
140 p += 5;
141 }
142
f78fb44e
AJ		 143 for (i = 0; i < 32; i++) {
144 sprintf(p, "r%d", i);
145 cpu_gpr[i] = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
146 offsetof(CPUState, gpr[i]), p);
147 p += (i < 10) ? 3 : 4;
148#if !defined(TARGET_PPC64)
149 sprintf(p, "r%dH", i);
150 cpu_gprh[i] = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
151 offsetof(CPUState, gprh[i]), p);
152 p += (i < 10) ? 4 : 5;
153#endif
1d542695 154
a5e26afa
AJ		 155 sprintf(p, "fp%d", i);
156 cpu_fpr[i] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
157 offsetof(CPUState, fpr[i]), p);
ec1ac72d 158 p += (i < 10) ? 4 : 5;
a5e26afa 159
1d542695
AJ		 160 sprintf(p, "avr%dH", i);
161 cpu_avrh[i] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
162 offsetof(CPUState, avr[i].u64[0]), p);
163 p += (i < 10) ? 6 : 7;
ec1ac72d 164
1d542695
AJ		 165 sprintf(p, "avr%dL", i);
166 cpu_avrl[i] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
167 offsetof(CPUState, avr[i].u64[1]), p);
168 p += (i < 10) ? 6 : 7;
f78fb44e 169 }
f10dc08e 170
bd568f18
AJ		 171 cpu_nip = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
172 offsetof(CPUState, nip), "nip");
173
cfdcd37a
AJ		 174 cpu_ctr = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
175 offsetof(CPUState, ctr), "ctr");
176
177 cpu_lr = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
178 offsetof(CPUState, lr), "lr");
179
3d7b417e
AJ		 180 cpu_xer = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
181 offsetof(CPUState, xer), "xer");
182
e1571908
AJ		 183 cpu_fpscr = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
184 offsetof(CPUState, fpscr), "fpscr");
185
f10dc08e
AJ		 186 /* register helpers */
187#undef DEF_HELPER
188#define DEF_HELPER(ret, name, params) tcg_register_helper(name, #name);
189#include "helper.h"
190
2e70f6ef
PB		 191 done_init = 1;
192}
193
7c58044c
JM		 194#if defined(OPTIMIZE_FPRF_UPDATE)
195static uint16_t *gen_fprf_buf[OPC_BUF_SIZE];
196static uint16_t **gen_fprf_ptr;
197#endif
79aceca5 198
79aceca5
FB		 199/* internal defines */
200typedef struct DisasContext {
201 struct TranslationBlock *tb;
0fa85d43 202 target_ulong nip;
79aceca5 203 uint32_t opcode;
9a64fbe4 204 uint32_t exception;
3cc62370
FB		 205 /* Routine used to access memory */
206 int mem_idx;
207 /* Translation flags */
9a64fbe4 208#if !defined(CONFIG_USER_ONLY)
79aceca5 209 int supervisor;
d9bce9d9
JM		 210#endif
211#if defined(TARGET_PPC64)
212 int sf_mode;
9a64fbe4 213#endif
3cc62370 214 int fpu_enabled;
a9d9eb8f 215 int altivec_enabled;
0487d6a8 216 int spe_enabled;
3fc6c082 217 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
ea4e754f 218 int singlestep_enabled;
d63001d1 219 int dcache_line_size;
79aceca5
FB		 220} DisasContext;
221
3fc6c082 222struct opc_handler_t {
79aceca5
FB		 223 /* invalid bits */
224 uint32_t inval;
9a64fbe4 225 /* instruction type */
0487d6a8 226 uint64_t type;
79aceca5
FB		 227 /* handler */
228 void (*handler)(DisasContext *ctx);
a750fc0b 229#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
b55266b5 230 const char *oname;
a750fc0b
JM		 231#endif
232#if defined(DO_PPC_STATISTICS)
76a66253
JM		 233 uint64_t count;
234#endif
3fc6c082 235};
79aceca5 236
7c58044c
JM		 237static always_inline void gen_reset_fpstatus (void)
238{
239#ifdef CONFIG_SOFTFLOAT
240 gen_op_reset_fpstatus();
241#endif
242}
243
244static always_inline void gen_compute_fprf (int set_fprf, int set_rc)
245{
246 if (set_fprf != 0) {
247 /* This case might be optimized later */
248#if defined(OPTIMIZE_FPRF_UPDATE)
249 *gen_fprf_ptr++ = gen_opc_ptr;
250#endif
251 gen_op_compute_fprf(1);
252 if (unlikely(set_rc))
47e4661c 253 tcg_gen_andi_i32(cpu_crf[1], cpu_T[0], 0xf);
7c58044c
JM		 254 gen_op_float_check_status();
255 } else if (unlikely(set_rc)) {
256 /* We always need to compute fpcc */
257 gen_op_compute_fprf(0);
47e4661c 258 tcg_gen_andi_i32(cpu_crf[1], cpu_T[0], 0xf);
7c58044c
JM		 259 if (set_fprf)
260 gen_op_float_check_status();
261 }
262}
263
264static always_inline void gen_optimize_fprf (void)
265{
266#if defined(OPTIMIZE_FPRF_UPDATE)
267 uint16_t **ptr;
268
269 for (ptr = gen_fprf_buf; ptr != (gen_fprf_ptr - 1); ptr++)
270 *ptr = INDEX_op_nop1;
271 gen_fprf_ptr = gen_fprf_buf;
272#endif
273}
274
b068d6a7 275static always_inline void gen_update_nip (DisasContext *ctx, target_ulong nip)
d9bce9d9
JM		 276{
277#if defined(TARGET_PPC64)
278 if (ctx->sf_mode)
bd568f18 279 tcg_gen_movi_tl(cpu_nip, nip);
d9bce9d9
JM		 280 else
281#endif
bd568f18 282 tcg_gen_movi_tl(cpu_nip, (uint32_t)nip);
d9bce9d9
JM		 283}
284
e1833e1f 285#define GEN_EXCP(ctx, excp, error) \
79aceca5 286do { \
e1833e1f 287 if ((ctx)->exception == POWERPC_EXCP_NONE) { \
d9bce9d9 288 gen_update_nip(ctx, (ctx)->nip); \
9fddaa0c
FB		 289 } \
290 gen_op_raise_exception_err((excp), (error)); \
291 ctx->exception = (excp); \
79aceca5
FB		 292} while (0)
293
e1833e1f
JM		 294#define GEN_EXCP_INVAL(ctx) \
295GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \
296 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL)
9fddaa0c 297
e1833e1f
JM		 298#define GEN_EXCP_PRIVOPC(ctx) \
299GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \
300 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_OPC)
9a64fbe4 301
e1833e1f
JM		 302#define GEN_EXCP_PRIVREG(ctx) \
303GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \
304 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG)
305
306#define GEN_EXCP_NO_FP(ctx) \
307GEN_EXCP(ctx, POWERPC_EXCP_FPU, 0)
308
309#define GEN_EXCP_NO_AP(ctx) \
310GEN_EXCP(ctx, POWERPC_EXCP_APU, 0)
9a64fbe4 311
a9d9eb8f
JM		 312#define GEN_EXCP_NO_VR(ctx) \
313GEN_EXCP(ctx, POWERPC_EXCP_VPU, 0)
314
f24e5695 315/* Stop translation */
b068d6a7 316static always_inline void GEN_STOP (DisasContext *ctx)
3fc6c082 317{
d9bce9d9 318 gen_update_nip(ctx, ctx->nip);
e1833e1f 319 ctx->exception = POWERPC_EXCP_STOP;
3fc6c082
FB		 320}
321
f24e5695 322/* No need to update nip here, as execution flow will change */
b068d6a7 323static always_inline void GEN_SYNC (DisasContext *ctx)
2be0071f 324{
e1833e1f 325 ctx->exception = POWERPC_EXCP_SYNC;
2be0071f
FB		 326}
327
79aceca5
FB		 328#define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
329static void gen_##name (DisasContext *ctx); \
330GEN_OPCODE(name, opc1, opc2, opc3, inval, type); \
331static void gen_##name (DisasContext *ctx)
332
c7697e1f
JM		 333#define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
334static void gen_##name (DisasContext *ctx); \
335GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type); \
336static void gen_##name (DisasContext *ctx)
337
79aceca5
FB		 338typedef struct opcode_t {
339 unsigned char opc1, opc2, opc3;
1235fc06 340#if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
18fba28c
FB		 341 unsigned char pad[5];
342#else
343 unsigned char pad[1];
344#endif
79aceca5 345 opc_handler_t handler;
b55266b5 346 const char *oname;
79aceca5
FB		 347} opcode_t;
348
a750fc0b 349/*****************************************************************************/
79aceca5
FB		 350/*** Instruction decoding ***/
351#define EXTRACT_HELPER(name, shift, nb) \
b068d6a7 352static always_inline uint32_t name (uint32_t opcode) \
79aceca5
FB		 353{ \
354 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
355}
356
357#define EXTRACT_SHELPER(name, shift, nb) \
b068d6a7 358static always_inline int32_t name (uint32_t opcode) \
79aceca5 359{ \
18fba28c 360 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
79aceca5
FB		 361}
362
363/* Opcode part 1 */
364EXTRACT_HELPER(opc1, 26, 6);
365/* Opcode part 2 */
366EXTRACT_HELPER(opc2, 1, 5);
367/* Opcode part 3 */
368EXTRACT_HELPER(opc3, 6, 5);
369/* Update Cr0 flags */
370EXTRACT_HELPER(Rc, 0, 1);
371/* Destination */
372EXTRACT_HELPER(rD, 21, 5);
373/* Source */
374EXTRACT_HELPER(rS, 21, 5);
375/* First operand */
376EXTRACT_HELPER(rA, 16, 5);
377/* Second operand */
378EXTRACT_HELPER(rB, 11, 5);
379/* Third operand */
380EXTRACT_HELPER(rC, 6, 5);
381/*** Get CRn ***/
382EXTRACT_HELPER(crfD, 23, 3);
383EXTRACT_HELPER(crfS, 18, 3);
384EXTRACT_HELPER(crbD, 21, 5);
385EXTRACT_HELPER(crbA, 16, 5);
386EXTRACT_HELPER(crbB, 11, 5);
387/* SPR / TBL */
3fc6c082 388EXTRACT_HELPER(_SPR, 11, 10);
b068d6a7 389static always_inline uint32_t SPR (uint32_t opcode)
3fc6c082
FB		 390{
391 uint32_t sprn = _SPR(opcode);
392
393 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
394}
79aceca5
FB		 395/*** Get constants ***/
396EXTRACT_HELPER(IMM, 12, 8);
397/* 16 bits signed immediate value */
398EXTRACT_SHELPER(SIMM, 0, 16);
399/* 16 bits unsigned immediate value */
400EXTRACT_HELPER(UIMM, 0, 16);
401/* Bit count */
402EXTRACT_HELPER(NB, 11, 5);
403/* Shift count */
404EXTRACT_HELPER(SH, 11, 5);
405/* Mask start */
406EXTRACT_HELPER(MB, 6, 5);
407/* Mask end */
408EXTRACT_HELPER(ME, 1, 5);
fb0eaffc
FB		 409/* Trap operand */
410EXTRACT_HELPER(TO, 21, 5);
79aceca5
FB		 411
412EXTRACT_HELPER(CRM, 12, 8);
413EXTRACT_HELPER(FM, 17, 8);
414EXTRACT_HELPER(SR, 16, 4);
e4bb997e 415EXTRACT_HELPER(FPIMM, 12, 4);
fb0eaffc 416
79aceca5
FB		 417/*** Jump target decoding ***/
418/* Displacement */
419EXTRACT_SHELPER(d, 0, 16);
420/* Immediate address */
b068d6a7 421static always_inline target_ulong LI (uint32_t opcode)
79aceca5
FB		 422{
423 return (opcode >> 0) & 0x03FFFFFC;
424}
425
b068d6a7 426static always_inline uint32_t BD (uint32_t opcode)
79aceca5
FB		 427{
428 return (opcode >> 0) & 0xFFFC;
429}
430
431EXTRACT_HELPER(BO, 21, 5);
432EXTRACT_HELPER(BI, 16, 5);
433/* Absolute/relative address */
434EXTRACT_HELPER(AA, 1, 1);
435/* Link */
436EXTRACT_HELPER(LK, 0, 1);
437
438/* Create a mask between <start> and <end> bits */
b068d6a7 439static always_inline target_ulong MASK (uint32_t start, uint32_t end)
79aceca5 440{
76a66253 441 target_ulong ret;
79aceca5 442
76a66253
JM		 443#if defined(TARGET_PPC64)
444 if (likely(start == 0)) {
6f2d8978 445 ret = UINT64_MAX << (63 - end);
76a66253 446 } else if (likely(end == 63)) {
6f2d8978 447 ret = UINT64_MAX >> start;
76a66253
JM		 448 }
449#else
450 if (likely(start == 0)) {
6f2d8978 451 ret = UINT32_MAX << (31 - end);
76a66253 452 } else if (likely(end == 31)) {
6f2d8978 453 ret = UINT32_MAX >> start;
76a66253
JM		 454 }
455#endif
456 else {
457 ret = (((target_ulong)(-1ULL)) >> (start)) ^
458 (((target_ulong)(-1ULL) >> (end)) >> 1);
459 if (unlikely(start > end))
460 return ~ret;
461 }
79aceca5
FB		 462
463 return ret;
464}
465
a750fc0b
JM		 466/*****************************************************************************/
467/* PowerPC Instructions types definitions */
468enum {
1b413d55 469 PPC_NONE = 0x0000000000000000ULL,
12de9a39 470 /* PowerPC base instructions set */
1b413d55
JM		 471 PPC_INSNS_BASE = 0x0000000000000001ULL,
472 /* integer operations instructions */
a750fc0b 473#define PPC_INTEGER PPC_INSNS_BASE
1b413d55 474 /* flow control instructions */
a750fc0b 475#define PPC_FLOW PPC_INSNS_BASE
1b413d55 476 /* virtual memory instructions */
a750fc0b 477#define PPC_MEM PPC_INSNS_BASE
1b413d55 478 /* ld/st with reservation instructions */
a750fc0b 479#define PPC_RES PPC_INSNS_BASE
1b413d55 480 /* spr/msr access instructions */
a750fc0b 481#define PPC_MISC PPC_INSNS_BASE
1b413d55
JM		 482 /* Deprecated instruction sets */
483 /* Original POWER instruction set */
f610349f 484 PPC_POWER = 0x0000000000000002ULL,
1b413d55 485 /* POWER2 instruction set extension */
f610349f 486 PPC_POWER2 = 0x0000000000000004ULL,
1b413d55 487 /* Power RTC support */
f610349f 488 PPC_POWER_RTC = 0x0000000000000008ULL,
1b413d55 489 /* Power-to-PowerPC bridge (601) */
f610349f 490 PPC_POWER_BR = 0x0000000000000010ULL,
1b413d55 491 /* 64 bits PowerPC instruction set */
f610349f 492 PPC_64B = 0x0000000000000020ULL,
1b413d55 493 /* New 64 bits extensions (PowerPC 2.0x) */
f610349f 494 PPC_64BX = 0x0000000000000040ULL,
1b413d55 495 /* 64 bits hypervisor extensions */
f610349f 496 PPC_64H = 0x0000000000000080ULL,
1b413d55 497 /* New wait instruction (PowerPC 2.0x) */
f610349f 498 PPC_WAIT = 0x0000000000000100ULL,
1b413d55 499 /* Time base mftb instruction */
f610349f 500 PPC_MFTB = 0x0000000000000200ULL,
1b413d55
JM		 501
502 /* Fixed-point unit extensions */
503 /* PowerPC 602 specific */
f610349f 504 PPC_602_SPEC = 0x0000000000000400ULL,
05332d70
JM		 505 /* isel instruction */
506 PPC_ISEL = 0x0000000000000800ULL,
507 /* popcntb instruction */
508 PPC_POPCNTB = 0x0000000000001000ULL,
509 /* string load / store */
510 PPC_STRING = 0x0000000000002000ULL,
1b413d55
JM		 511
512 /* Floating-point unit extensions */
513 /* Optional floating point instructions */
514 PPC_FLOAT = 0x0000000000010000ULL,
515 /* New floating-point extensions (PowerPC 2.0x) */
516 PPC_FLOAT_EXT = 0x0000000000020000ULL,
517 PPC_FLOAT_FSQRT = 0x0000000000040000ULL,
518 PPC_FLOAT_FRES = 0x0000000000080000ULL,
519 PPC_FLOAT_FRSQRTE = 0x0000000000100000ULL,
520 PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
521 PPC_FLOAT_FSEL = 0x0000000000400000ULL,
522 PPC_FLOAT_STFIWX = 0x0000000000800000ULL,
523
524 /* Vector/SIMD extensions */
525 /* Altivec support */
526 PPC_ALTIVEC = 0x0000000001000000ULL,
1b413d55 527 /* PowerPC 2.03 SPE extension */
05332d70 528 PPC_SPE = 0x0000000002000000ULL,
1b413d55 529 /* PowerPC 2.03 SPE floating-point extension */
05332d70 530 PPC_SPEFPU = 0x0000000004000000ULL,
1b413d55 531
12de9a39 532 /* Optional memory control instructions */
1b413d55
JM		 533 PPC_MEM_TLBIA = 0x0000000010000000ULL,
534 PPC_MEM_TLBIE = 0x0000000020000000ULL,
535 PPC_MEM_TLBSYNC = 0x0000000040000000ULL,
536 /* sync instruction */
537 PPC_MEM_SYNC = 0x0000000080000000ULL,
538 /* eieio instruction */
539 PPC_MEM_EIEIO = 0x0000000100000000ULL,
540
541 /* Cache control instructions */
c8623f2e 542 PPC_CACHE = 0x0000000200000000ULL,
1b413d55 543 /* icbi instruction */
05332d70 544 PPC_CACHE_ICBI = 0x0000000400000000ULL,
1b413d55 545 /* dcbz instruction with fixed cache line size */
05332d70 546 PPC_CACHE_DCBZ = 0x0000000800000000ULL,
1b413d55 547 /* dcbz instruction with tunable cache line size */
05332d70 548 PPC_CACHE_DCBZT = 0x0000001000000000ULL,
1b413d55 549 /* dcba instruction */
05332d70
JM		 550 PPC_CACHE_DCBA = 0x0000002000000000ULL,
551 /* Freescale cache locking instructions */
552 PPC_CACHE_LOCK = 0x0000004000000000ULL,
1b413d55
JM		 553
554 /* MMU related extensions */
555 /* external control instructions */
05332d70 556 PPC_EXTERN = 0x0000010000000000ULL,
1b413d55 557 /* segment register access instructions */
05332d70 558 PPC_SEGMENT = 0x0000020000000000ULL,
1b413d55 559 /* PowerPC 6xx TLB management instructions */
05332d70 560 PPC_6xx_TLB = 0x0000040000000000ULL,
1b413d55 561 /* PowerPC 74xx TLB management instructions */
05332d70 562 PPC_74xx_TLB = 0x0000080000000000ULL,
1b413d55 563 /* PowerPC 40x TLB management instructions */
05332d70 564 PPC_40x_TLB = 0x0000100000000000ULL,
1b413d55 565 /* segment register access instructions for PowerPC 64 "bridge" */
05332d70 566 PPC_SEGMENT_64B = 0x0000200000000000ULL,
1b413d55 567 /* SLB management */
05332d70 568 PPC_SLBI = 0x0000400000000000ULL,
1b413d55 569
12de9a39 570 /* Embedded PowerPC dedicated instructions */
05332d70 571 PPC_WRTEE = 0x0001000000000000ULL,
12de9a39 572 /* PowerPC 40x exception model */
05332d70 573 PPC_40x_EXCP = 0x0002000000000000ULL,
12de9a39 574 /* PowerPC 405 Mac instructions */
05332d70 575 PPC_405_MAC = 0x0004000000000000ULL,
12de9a39 576 /* PowerPC 440 specific instructions */
05332d70 577 PPC_440_SPEC = 0x0008000000000000ULL,
12de9a39 578 /* BookE (embedded) PowerPC specification */
05332d70
JM		 579 PPC_BOOKE = 0x0010000000000000ULL,
580 /* mfapidi instruction */
581 PPC_MFAPIDI = 0x0020000000000000ULL,
582 /* tlbiva instruction */
583 PPC_TLBIVA = 0x0040000000000000ULL,
584 /* tlbivax instruction */
585 PPC_TLBIVAX = 0x0080000000000000ULL,
12de9a39 586 /* PowerPC 4xx dedicated instructions */
05332d70 587 PPC_4xx_COMMON = 0x0100000000000000ULL,
12de9a39 588 /* PowerPC 40x ibct instructions */
05332d70 589 PPC_40x_ICBT = 0x0200000000000000ULL,
12de9a39 590 /* rfmci is not implemented in all BookE PowerPC */
05332d70
JM		 591 PPC_RFMCI = 0x0400000000000000ULL,
592 /* rfdi instruction */
593 PPC_RFDI = 0x0800000000000000ULL,
594 /* DCR accesses */
595 PPC_DCR = 0x1000000000000000ULL,
596 /* DCR extended accesse */
597 PPC_DCRX = 0x2000000000000000ULL,
12de9a39 598 /* user-mode DCR access, implemented in PowerPC 460 */
05332d70 599 PPC_DCRUX = 0x4000000000000000ULL,
a750fc0b
JM		 600};
601
602/*****************************************************************************/
603/* PowerPC instructions table */
3fc6c082
FB		 604#if HOST_LONG_BITS == 64
605#define OPC_ALIGN 8
606#else
607#define OPC_ALIGN 4
608#endif
1b039c09 609#if defined(__APPLE__)
d9bce9d9 610#define OPCODES_SECTION \
3fc6c082 611 __attribute__ ((section("__TEXT,__opcodes"), unused, aligned (OPC_ALIGN) ))
933dc6eb 612#else
d9bce9d9 613#define OPCODES_SECTION \
3fc6c082 614 __attribute__ ((section(".opcodes"), unused, aligned (OPC_ALIGN) ))
933dc6eb
FB		 615#endif
616
76a66253 617#if defined(DO_PPC_STATISTICS)
79aceca5 618#define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
18fba28c 619OPCODES_SECTION opcode_t opc_##name = { \
79aceca5
FB		 620 .opc1 = op1, \
621 .opc2 = op2, \
622 .opc3 = op3, \
18fba28c 623 .pad = { 0, }, \
79aceca5
FB		 624 .handler = { \
625 .inval = invl, \
9a64fbe4 626 .type = _typ, \
79aceca5 627 .handler = &gen_##name, \
76a66253 628 .oname = stringify(name), \
79aceca5 629 }, \
3fc6c082 630 .oname = stringify(name), \
79aceca5 631}
c7697e1f
JM		 632#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
633OPCODES_SECTION opcode_t opc_##name = { \
634 .opc1 = op1, \
635 .opc2 = op2, \
636 .opc3 = op3, \
637 .pad = { 0, }, \
638 .handler = { \
639 .inval = invl, \
640 .type = _typ, \
641 .handler = &gen_##name, \
642 .oname = onam, \
643 }, \
644 .oname = onam, \
645}
76a66253
JM		 646#else
647#define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
648OPCODES_SECTION opcode_t opc_##name = { \
649 .opc1 = op1, \
650 .opc2 = op2, \
651 .opc3 = op3, \
652 .pad = { 0, }, \
653 .handler = { \
654 .inval = invl, \
655 .type = _typ, \
656 .handler = &gen_##name, \
657 }, \
658 .oname = stringify(name), \
659}
c7697e1f
JM		 660#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
661OPCODES_SECTION opcode_t opc_##name = { \
662 .opc1 = op1, \
663 .opc2 = op2, \
664 .opc3 = op3, \
665 .pad = { 0, }, \
666 .handler = { \
667 .inval = invl, \
668 .type = _typ, \
669 .handler = &gen_##name, \
670 }, \
671 .oname = onam, \
672}
76a66253 673#endif
79aceca5
FB		 674
675#define GEN_OPCODE_MARK(name) \
18fba28c 676OPCODES_SECTION opcode_t opc_##name = { \
79aceca5
FB		 677 .opc1 = 0xFF, \
678 .opc2 = 0xFF, \
679 .opc3 = 0xFF, \
18fba28c 680 .pad = { 0, }, \
79aceca5
FB		 681 .handler = { \
682 .inval = 0x00000000, \
9a64fbe4 683 .type = 0x00, \
79aceca5
FB		 684 .handler = NULL, \
685 }, \
3fc6c082 686 .oname = stringify(name), \
79aceca5
FB		 687}
688
689/* Start opcode list */
690GEN_OPCODE_MARK(start);
691
692/* Invalid instruction */
9a64fbe4
FB		 693GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE)
694{
e1833e1f 695 GEN_EXCP_INVAL(ctx);
9a64fbe4
FB		 696}
697
79aceca5
FB		 698static opc_handler_t invalid_handler = {
699 .inval = 0xFFFFFFFF,
9a64fbe4 700 .type = PPC_NONE,
79aceca5
FB		 701 .handler = gen_invalid,
702};
703
e1571908
AJ		 704/*** Integer comparison ***/
705
ea363694 706static always_inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
e1571908
AJ		 707{
708 int l1, l2, l3;
709
269f3e95
AJ		 710 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_xer);
711 tcg_gen_shri_i32(cpu_crf[crf], cpu_crf[crf], XER_SO);
e1571908
AJ		 712 tcg_gen_andi_i32(cpu_crf[crf], cpu_crf[crf], 1);
713
714 l1 = gen_new_label();
715 l2 = gen_new_label();
716 l3 = gen_new_label();
717 if (s) {
ea363694
AJ		 718 tcg_gen_brcond_tl(TCG_COND_LT, arg0, arg1, l1);
719 tcg_gen_brcond_tl(TCG_COND_GT, arg0, arg1, l2);
e1571908 720 } else {
ea363694
AJ		 721 tcg_gen_brcond_tl(TCG_COND_LTU, arg0, arg1, l1);
722 tcg_gen_brcond_tl(TCG_COND_GTU, arg0, arg1, l2);
e1571908
AJ		 723 }
724 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_EQ);
725 tcg_gen_br(l3);
726 gen_set_label(l1);
727 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_LT);
728 tcg_gen_br(l3);
729 gen_set_label(l2);
730 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_GT);
731 gen_set_label(l3);
732}
733
ea363694 734static always_inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
e1571908 735{
ea363694
AJ		 736 TCGv t0 = tcg_const_local_tl(arg1);
737 gen_op_cmp(arg0, t0, s, crf);
738 tcg_temp_free(t0);
e1571908
AJ		 739}
740
741#if defined(TARGET_PPC64)
ea363694 742static always_inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
e1571908 743{
ea363694
AJ		 744 TCGv t0, t1;
745 t0 = tcg_temp_local_new(TCG_TYPE_TL);
746 t1 = tcg_temp_local_new(TCG_TYPE_TL);
e1571908 747 if (s) {
ea363694
AJ		 748 tcg_gen_ext32s_tl(t0, arg0);
749 tcg_gen_ext32s_tl(t1, arg1);
e1571908 750 } else {
ea363694
AJ		 751 tcg_gen_ext32u_tl(t0, arg0);
752 tcg_gen_ext32u_tl(t1, arg1);
e1571908 753 }
ea363694
AJ		 754 gen_op_cmp(t0, t1, s, crf);
755 tcg_temp_free(t1);
756 tcg_temp_free(t0);
e1571908
AJ		 757}
758
ea363694 759static always_inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
e1571908 760{
ea363694
AJ		 761 TCGv t0 = tcg_const_local_tl(arg1);
762 gen_op_cmp32(arg0, t0, s, crf);
763 tcg_temp_free(t0);
e1571908
AJ		 764}
765#endif
766
767static always_inline void gen_set_Rc0 (DisasContext *ctx, TCGv reg)
768{
769#if defined(TARGET_PPC64)
770 if (!(ctx->sf_mode))
771 gen_op_cmpi32(reg, 0, 1, 0);
772 else
773#endif
774 gen_op_cmpi(reg, 0, 1, 0);
775}
776
777/* cmp */
778GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER)
779{
780#if defined(TARGET_PPC64)
781 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
782 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
783 1, crfD(ctx->opcode));
784 else
785#endif
786 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
787 1, crfD(ctx->opcode));
788}
789
790/* cmpi */
791GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
792{
793#if defined(TARGET_PPC64)
794 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
795 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
796 1, crfD(ctx->opcode));
797 else
798#endif
799 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
800 1, crfD(ctx->opcode));
801}
802
803/* cmpl */
804GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER)
805{
806#if defined(TARGET_PPC64)
807 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
808 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
809 0, crfD(ctx->opcode));
810 else
811#endif
812 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
813 0, crfD(ctx->opcode));
814}
815
816/* cmpli */
817GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
818{
819#if defined(TARGET_PPC64)
820 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
821 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
822 0, crfD(ctx->opcode));
823 else
824#endif
825 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
826 0, crfD(ctx->opcode));
827}
828
829/* isel (PowerPC 2.03 specification) */
830GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL)
831{
832 int l1, l2;
833 uint32_t bi = rC(ctx->opcode);
834 uint32_t mask;
835 TCGv temp;
836
837 l1 = gen_new_label();
838 l2 = gen_new_label();
839
840 mask = 1 << (3 - (bi & 0x03));
841 temp = tcg_temp_new(TCG_TYPE_I32);
842 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
843 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
844 if (rA(ctx->opcode) == 0)
845 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
846 else
847 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
848 tcg_gen_br(l2);
849 gen_set_label(l1);
850 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
851 gen_set_label(l2);
852}
853
79aceca5 854/*** Integer arithmetic ***/
d9bce9d9
JM		 855#define __GEN_INT_ARITH2(name, opc1, opc2, opc3, inval, type) \
856GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
79aceca5 857{ \
f78fb44e
AJ		 858 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \
859 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); \
79aceca5 860 gen_op_##name(); \
f78fb44e 861 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); \
76a66253 862 if (unlikely(Rc(ctx->opcode) != 0)) \
e1571908 863 gen_set_Rc0(ctx, cpu_T[0]); \
79aceca5
FB		 864}
865
d9bce9d9
JM		 866#define __GEN_INT_ARITH2_O(name, opc1, opc2, opc3, inval, type) \
867GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
79aceca5 868{ \
f78fb44e
AJ		 869 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \
870 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); \
79aceca5 871 gen_op_##name(); \
f78fb44e 872 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); \
76a66253 873 if (unlikely(Rc(ctx->opcode) != 0)) \
e1571908 874 gen_set_Rc0(ctx, cpu_T[0]); \
79aceca5
FB		 875}
876
d9bce9d9
JM		 877#define __GEN_INT_ARITH1(name, opc1, opc2, opc3, type) \
878GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \
79aceca5 879{ \
f78fb44e 880 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \
79aceca5 881 gen_op_##name(); \
f78fb44e 882 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); \
76a66253 883 if (unlikely(Rc(ctx->opcode) != 0)) \
e1571908 884 gen_set_Rc0(ctx, cpu_T[0]); \
79aceca5 885}
d9bce9d9
JM		 886#define __GEN_INT_ARITH1_O(name, opc1, opc2, opc3, type) \
887GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \
79aceca5 888{ \
f78fb44e 889 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \
79aceca5 890 gen_op_##name(); \
f78fb44e 891 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); \
76a66253 892 if (unlikely(Rc(ctx->opcode) != 0)) \
e1571908 893 gen_set_Rc0(ctx, cpu_T[0]); \
79aceca5
FB		 894}
895
896/* Two operands arithmetic functions */
d9bce9d9
JM		 897#define GEN_INT_ARITH2(name, opc1, opc2, opc3, type) \
898__GEN_INT_ARITH2(name, opc1, opc2, opc3, 0x00000000, type) \
899__GEN_INT_ARITH2_O(name##o, opc1, opc2, opc3 | 0x10, 0x00000000, type)
900
901/* Two operands arithmetic functions with no overflow allowed */
902#define GEN_INT_ARITHN(name, opc1, opc2, opc3, type) \
903__GEN_INT_ARITH2(name, opc1, opc2, opc3, 0x00000400, type)
904
905/* One operand arithmetic functions */
906#define GEN_INT_ARITH1(name, opc1, opc2, opc3, type) \
907__GEN_INT_ARITH1(name, opc1, opc2, opc3, type) \
908__GEN_INT_ARITH1_O(name##o, opc1, opc2, opc3 | 0x10, type)
909
910#if defined(TARGET_PPC64)
911#define __GEN_INT_ARITH2_64(name, opc1, opc2, opc3, inval, type) \
912GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
913{ \
f78fb44e
AJ		 914 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \
915 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); \
d9bce9d9
JM		 916 if (ctx->sf_mode) \
917 gen_op_##name##_64(); \
918 else \
919 gen_op_##name(); \
f78fb44e 920 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); \
d9bce9d9 921 if (unlikely(Rc(ctx->opcode) != 0)) \
e1571908 922 gen_set_Rc0(ctx, cpu_T[0]); \
d9bce9d9
JM		 923}
924
925#define __GEN_INT_ARITH2_O_64(name, opc1, opc2, opc3, inval, type) \
926GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
927{ \
f78fb44e
AJ		 928 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \
929 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); \
d9bce9d9
JM		 930 if (ctx->sf_mode) \
931 gen_op_##name##_64(); \
932 else \
933 gen_op_##name(); \
f78fb44e 934 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); \
d9bce9d9 935 if (unlikely(Rc(ctx->opcode) != 0)) \
e1571908 936 gen_set_Rc0(ctx, cpu_T[0]); \
d9bce9d9
JM		 937}
938
939#define __GEN_INT_ARITH1_64(name, opc1, opc2, opc3, type) \
940GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \
941{ \
f78fb44e 942 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \
d9bce9d9
JM		 943 if (ctx->sf_mode) \
944 gen_op_##name##_64(); \
945 else \
946 gen_op_##name(); \
f78fb44e 947 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); \
d9bce9d9 948 if (unlikely(Rc(ctx->opcode) != 0)) \
e1571908 949 gen_set_Rc0(ctx, cpu_T[0]); \
d9bce9d9
JM		 950}
951#define __GEN_INT_ARITH1_O_64(name, opc1, opc2, opc3, type) \
952GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \
953{ \
f78fb44e 954 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \
d9bce9d9
JM		 955 if (ctx->sf_mode) \
956 gen_op_##name##_64(); \
957 else \
958 gen_op_##name(); \
f78fb44e 959 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); \
d9bce9d9 960 if (unlikely(Rc(ctx->opcode) != 0)) \
e1571908 961 gen_set_Rc0(ctx, cpu_T[0]); \
d9bce9d9
JM		 962}
963
964/* Two operands arithmetic functions */
965#define GEN_INT_ARITH2_64(name, opc1, opc2, opc3, type) \
966__GEN_INT_ARITH2_64(name, opc1, opc2, opc3, 0x00000000, type) \
967__GEN_INT_ARITH2_O_64(name##o, opc1, opc2, opc3 | 0x10, 0x00000000, type)
79aceca5
FB		 968
969/* Two operands arithmetic functions with no overflow allowed */
d9bce9d9
JM		 970#define GEN_INT_ARITHN_64(name, opc1, opc2, opc3, type) \
971__GEN_INT_ARITH2_64(name, opc1, opc2, opc3, 0x00000400, type)
79aceca5
FB		 972
973/* One operand arithmetic functions */
d9bce9d9
JM		 974#define GEN_INT_ARITH1_64(name, opc1, opc2, opc3, type) \
975__GEN_INT_ARITH1_64(name, opc1, opc2, opc3, type) \
976__GEN_INT_ARITH1_O_64(name##o, opc1, opc2, opc3 | 0x10, type)
977#else
978#define GEN_INT_ARITH2_64 GEN_INT_ARITH2
979#define GEN_INT_ARITHN_64 GEN_INT_ARITHN
980#define GEN_INT_ARITH1_64 GEN_INT_ARITH1
981#endif
79aceca5
FB		 982
983/* add add. addo addo. */
39dd32ee
AJ		 984static always_inline void gen_op_add (void)
985{
986 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
987}
b068d6a7 988static always_inline void gen_op_addo (void)
d9bce9d9 989{
e55fd934 990 tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
39dd32ee 991 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
d9bce9d9
JM		 992 gen_op_check_addo();
993}
994#if defined(TARGET_PPC64)
995#define gen_op_add_64 gen_op_add
b068d6a7 996static always_inline void gen_op_addo_64 (void)
d9bce9d9 997{
e55fd934 998 tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
39dd32ee 999 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
d9bce9d9
JM		 1000 gen_op_check_addo_64();
1001}
1002#endif
1003GEN_INT_ARITH2_64 (add, 0x1F, 0x0A, 0x08, PPC_INTEGER);
79aceca5 1004/* addc addc. addco addco. */
b068d6a7 1005static always_inline void gen_op_addc (void)
d9bce9d9 1006{
e55fd934 1007 tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
39dd32ee 1008 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
d9bce9d9
JM		 1009 gen_op_check_addc();
1010}
b068d6a7 1011static always_inline void gen_op_addco (void)
d9bce9d9 1012{
e55fd934 1013 tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
39dd32ee 1014 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
d9bce9d9
JM		 1015 gen_op_check_addc();
1016 gen_op_check_addo();
1017}
1018#if defined(TARGET_PPC64)
b068d6a7 1019static always_inline void gen_op_addc_64 (void)
d9bce9d9 1020{
e55fd934 1021 tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
39dd32ee 1022 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
d9bce9d9
JM		 1023 gen_op_check_addc_64();
1024}
b068d6a7 1025static always_inline void gen_op_addco_64 (void)
d9bce9d9 1026{
e55fd934 1027 tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
39dd32ee 1028 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
d9bce9d9
JM		 1029 gen_op_check_addc_64();
1030 gen_op_check_addo_64();
1031}
1032#endif
1033GEN_INT_ARITH2_64 (addc, 0x1F, 0x0A, 0x00, PPC_INTEGER);
79aceca5 1034/* adde adde. addeo addeo. */
b068d6a7 1035static always_inline void gen_op_addeo (void)
d9bce9d9 1036{
e55fd934 1037 tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
d9bce9d9
JM		 1038 gen_op_adde();
1039 gen_op_check_addo();
1040}
1041#if defined(TARGET_PPC64)
b068d6a7 1042static always_inline void gen_op_addeo_64 (void)
d9bce9d9 1043{
e55fd934 1044 tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
d9bce9d9
JM		 1045 gen_op_adde_64();
1046 gen_op_check_addo_64();
1047}
1048#endif
1049GEN_INT_ARITH2_64 (adde, 0x1F, 0x0A, 0x04, PPC_INTEGER);
79aceca5 1050/* addme addme. addmeo addmeo. */
b068d6a7 1051static always_inline void gen_op_addme (void)
d9bce9d9 1052{
e55fd934 1053 tcg_gen_mov_tl(cpu_T[1], cpu_T[0]);
d9bce9d9
JM		 1054 gen_op_add_me();
1055}
1056#if defined(TARGET_PPC64)
b068d6a7 1057static always_inline void gen_op_addme_64 (void)
d9bce9d9 1058{
e55fd934 1059 tcg_gen_mov_tl(cpu_T[1], cpu_T[0]);
d9bce9d9
JM		 1060 gen_op_add_me_64();
1061}
1062#endif
1063GEN_INT_ARITH1_64 (addme, 0x1F, 0x0A, 0x07, PPC_INTEGER);
79aceca5 1064/* addze addze. addzeo addzeo. */
b068d6a7 1065static always_inline void gen_op_addze (void)
d9bce9d9 1066{
e55fd934 1067 tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
d9bce9d9
JM		 1068 gen_op_add_ze();
1069 gen_op_check_addc();
1070}
b068d6a7 1071static always_inline void gen_op_addzeo (void)
d9bce9d9 1072{
e55fd934 1073 tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
d9bce9d9
JM		 1074 gen_op_add_ze();
1075 gen_op_check_addc();
1076 gen_op_check_addo();
1077}
1078#if defined(TARGET_PPC64)
b068d6a7 1079static always_inline void gen_op_addze_64 (void)
d9bce9d9 1080{
e55fd934 1081 tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
d9bce9d9
JM		 1082 gen_op_add_ze();
1083 gen_op_check_addc_64();
1084}
b068d6a7 1085static always_inline void gen_op_addzeo_64 (void)
d9bce9d9 1086{
e55fd934 1087 tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
d9bce9d9
JM		 1088 gen_op_add_ze();
1089 gen_op_check_addc_64();
1090 gen_op_check_addo_64();
1091}
1092#endif
1093GEN_INT_ARITH1_64 (addze, 0x1F, 0x0A, 0x06, PPC_INTEGER);
79aceca5 1094/* divw divw. divwo divwo. */
d9bce9d9 1095GEN_INT_ARITH2 (divw, 0x1F, 0x0B, 0x0F, PPC_INTEGER);
79aceca5 1096/* divwu divwu. divwuo divwuo. */
d9bce9d9 1097GEN_INT_ARITH2 (divwu, 0x1F, 0x0B, 0x0E, PPC_INTEGER);
79aceca5 1098/* mulhw mulhw. */
d9bce9d9 1099GEN_INT_ARITHN (mulhw, 0x1F, 0x0B, 0x02, PPC_INTEGER);
79aceca5 1100/* mulhwu mulhwu. */
d9bce9d9 1101GEN_INT_ARITHN (mulhwu, 0x1F, 0x0B, 0x00, PPC_INTEGER);
79aceca5 1102/* mullw mullw. mullwo mullwo. */
d9bce9d9 1103GEN_INT_ARITH2 (mullw, 0x1F, 0x0B, 0x07, PPC_INTEGER);
79aceca5 1104/* neg neg. nego nego. */
d9bce9d9 1105GEN_INT_ARITH1_64 (neg, 0x1F, 0x08, 0x03, PPC_INTEGER);
79aceca5 1106/* subf subf. subfo subfo. */
7c417963
AJ		 1107static always_inline void gen_op_subf (void)
1108{
1109 tcg_gen_sub_tl(cpu_T[0], cpu_T[1], cpu_T[0]);
1110}
b068d6a7 1111static always_inline void gen_op_subfo (void)
d9bce9d9 1112{
f0413473 1113 tcg_gen_not_tl(cpu_T[2], cpu_T[0]);
7c417963 1114 tcg_gen_sub_tl(cpu_T[0], cpu_T[1], cpu_T[0]);
c3e10c7b 1115 gen_op_check_addo();
d9bce9d9
JM		 1116}
1117#if defined(TARGET_PPC64)
1118#define gen_op_subf_64 gen_op_subf
b068d6a7 1119static always_inline void gen_op_subfo_64 (void)
d9bce9d9 1120{
f0413473 1121 tcg_gen_not_i64(cpu_T[2], cpu_T[0]);
7c417963 1122 tcg_gen_sub_tl(cpu_T[0], cpu_T[1], cpu_T[0]);
c3e10c7b 1123 gen_op_check_addo_64();
d9bce9d9
JM		 1124}
1125#endif
1126GEN_INT_ARITH2_64 (subf, 0x1F, 0x08, 0x01, PPC_INTEGER);
79aceca5 1127/* subfc subfc. subfco subfco. */
b068d6a7 1128static always_inline void gen_op_subfc (void)
d9bce9d9 1129{
7c417963 1130 tcg_gen_sub_tl(cpu_T[0], cpu_T[1], cpu_T[0]);
d9bce9d9
JM		 1131 gen_op_check_subfc();
1132}
b068d6a7 1133static always_inline void gen_op_subfco (void)
d9bce9d9 1134{
f0413473 1135 tcg_gen_not_tl(cpu_T[2], cpu_T[0]);
7c417963 1136 tcg_gen_sub_tl(cpu_T[0], cpu_T[1], cpu_T[0]);
d9bce9d9 1137 gen_op_check_subfc();
c3e10c7b 1138 gen_op_check_addo();
d9bce9d9
JM		 1139}
1140#if defined(TARGET_PPC64)
b068d6a7 1141static always_inline void gen_op_subfc_64 (void)
d9bce9d9 1142{
7c417963 1143 tcg_gen_sub_tl(cpu_T[0], cpu_T[1], cpu_T[0]);
d9bce9d9
JM		 1144 gen_op_check_subfc_64();
1145}
b068d6a7 1146static always_inline void gen_op_subfco_64 (void)
d9bce9d9 1147{
f0413473 1148 tcg_gen_not_i64(cpu_T[2], cpu_T[0]);
7c417963 1149 tcg_gen_sub_tl(cpu_T[0], cpu_T[1], cpu_T[0]);
d9bce9d9 1150 gen_op_check_subfc_64();
c3e10c7b 1151 gen_op_check_addo_64();
d9bce9d9
JM		 1152}
1153#endif
1154GEN_INT_ARITH2_64 (subfc, 0x1F, 0x08, 0x00, PPC_INTEGER);
79aceca5 1155/* subfe subfe. subfeo subfeo. */
b068d6a7 1156static always_inline void gen_op_subfeo (void)
d9bce9d9 1157{
f0413473 1158 tcg_gen_not_tl(cpu_T[2], cpu_T[0]);
d9bce9d9 1159 gen_op_subfe();
c3e10c7b 1160 gen_op_check_addo();
d9bce9d9
JM		 1161}
1162#if defined(TARGET_PPC64)
1163#define gen_op_subfe_64 gen_op_subfe
b068d6a7 1164static always_inline void gen_op_subfeo_64 (void)
d9bce9d9 1165{
f0413473 1166 tcg_gen_not_i64(cpu_T[2], cpu_T[0]);
d9bce9d9 1167 gen_op_subfe_64();
c3e10c7b 1168 gen_op_check_addo_64();
d9bce9d9
JM		 1169}
1170#endif
1171GEN_INT_ARITH2_64 (subfe, 0x1F, 0x08, 0x04, PPC_INTEGER);
79aceca5 1172/* subfme subfme. subfmeo subfmeo. */
d9bce9d9 1173GEN_INT_ARITH1_64 (subfme, 0x1F, 0x08, 0x07, PPC_INTEGER);
79aceca5 1174/* subfze subfze. subfzeo subfzeo. */
d9bce9d9 1175GEN_INT_ARITH1_64 (subfze, 0x1F, 0x08, 0x06, PPC_INTEGER);
79aceca5
FB		 1176/* addi */
1177GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1178{
76a66253 1179 target_long simm = SIMM(ctx->opcode);
79aceca5
FB		 1180
1181 if (rA(ctx->opcode) == 0) {
76a66253 1182 /* li case */
02f4f6c2 1183 tcg_gen_movi_tl(cpu_T[0], simm);
79aceca5 1184 } else {
f78fb44e 1185 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 1186 if (likely(simm != 0))
39dd32ee 1187 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], simm);
79aceca5 1188 }
f78fb44e 1189 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
79aceca5
FB		 1190}
1191/* addic */
1192GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1193{
76a66253
JM		 1194 target_long simm = SIMM(ctx->opcode);
1195
f78fb44e 1196 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
d9bce9d9 1197 if (likely(simm != 0)) {
e55fd934 1198 tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
39dd32ee 1199 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], simm);
d9bce9d9
JM		 1200#if defined(TARGET_PPC64)
1201 if (ctx->sf_mode)
1202 gen_op_check_addc_64();
1203 else
1204#endif
1205 gen_op_check_addc();
e864cabd 1206 } else {
3d7b417e 1207 tcg_gen_andi_i32(cpu_xer, cpu_xer, ~(1 << XER_CA));
d9bce9d9 1208 }
f78fb44e 1209 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
79aceca5
FB		 1210}
1211/* addic. */
c7697e1f 1212GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
79aceca5 1213{
76a66253
JM		 1214 target_long simm = SIMM(ctx->opcode);
1215
f78fb44e 1216 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
d9bce9d9 1217 if (likely(simm != 0)) {
e55fd934 1218 tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
39dd32ee 1219 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], simm);
d9bce9d9
JM		 1220#if defined(TARGET_PPC64)
1221 if (ctx->sf_mode)
1222 gen_op_check_addc_64();
1223 else
1224#endif
1225 gen_op_check_addc();
966439a6 1226 } else {
3d7b417e 1227 tcg_gen_andi_i32(cpu_xer, cpu_xer, ~(1 << XER_CA));
d9bce9d9 1228 }
f78fb44e 1229 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
e1571908 1230 gen_set_Rc0(ctx, cpu_T[0]);
79aceca5
FB		 1231}
1232/* addis */
1233GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1234{
76a66253 1235 target_long simm = SIMM(ctx->opcode);
79aceca5
FB		 1236
1237 if (rA(ctx->opcode) == 0) {
76a66253 1238 /* lis case */
02f4f6c2 1239 tcg_gen_movi_tl(cpu_T[0], simm << 16);
79aceca5 1240 } else {
f78fb44e 1241 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 1242 if (likely(simm != 0))
39dd32ee 1243 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], simm << 16);
79aceca5 1244 }
f78fb44e 1245 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
79aceca5
FB		 1246}
1247/* mulli */
1248GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1249{
f78fb44e 1250 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
79aceca5 1251 gen_op_mulli(SIMM(ctx->opcode));
f78fb44e 1252 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
79aceca5
FB		 1253}
1254/* subfic */
1255GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1256{
f78fb44e 1257 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
d9bce9d9
JM		 1258#if defined(TARGET_PPC64)
1259 if (ctx->sf_mode)
1260 gen_op_subfic_64(SIMM(ctx->opcode));
1261 else
1262#endif
1263 gen_op_subfic(SIMM(ctx->opcode));
f78fb44e 1264 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
79aceca5
FB		 1265}
1266
d9bce9d9
JM		 1267#if defined(TARGET_PPC64)
1268/* mulhd mulhd. */
a750fc0b 1269GEN_INT_ARITHN (mulhd, 0x1F, 0x09, 0x02, PPC_64B);
d9bce9d9 1270/* mulhdu mulhdu. */
a750fc0b 1271GEN_INT_ARITHN (mulhdu, 0x1F, 0x09, 0x00, PPC_64B);
d9bce9d9 1272/* mulld mulld. mulldo mulldo. */
a750fc0b 1273GEN_INT_ARITH2 (mulld, 0x1F, 0x09, 0x07, PPC_64B);
d9bce9d9 1274/* divd divd. divdo divdo. */
a750fc0b 1275GEN_INT_ARITH2 (divd, 0x1F, 0x09, 0x0F, PPC_64B);
d9bce9d9 1276/* divdu divdu. divduo divduo. */
a750fc0b 1277GEN_INT_ARITH2 (divdu, 0x1F, 0x09, 0x0E, PPC_64B);
d9bce9d9
JM		 1278#endif
1279
79aceca5 1280/*** Integer logical ***/
26d67362
AJ		 1281#define GEN_LOGICAL2(name, tcg_op, opc, type) \
1282GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) \
79aceca5 1283{ \
26d67362
AJ		 1284 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1285 cpu_gpr[rB(ctx->opcode)]); \
76a66253 1286 if (unlikely(Rc(ctx->opcode) != 0)) \
26d67362 1287 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
79aceca5 1288}
79aceca5 1289
26d67362 1290#define GEN_LOGICAL1(name, tcg_op, opc, type) \
d9bce9d9 1291GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) \
79aceca5 1292{ \
26d67362 1293 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
76a66253 1294 if (unlikely(Rc(ctx->opcode) != 0)) \
26d67362 1295 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
79aceca5
FB		 1296}
1297
1298/* and & and. */
26d67362 1299GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
79aceca5 1300/* andc & andc. */
26d67362 1301GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
79aceca5 1302/* andi. */
c7697e1f 1303GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
79aceca5 1304{
26d67362
AJ		 1305 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1306 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5
FB		 1307}
1308/* andis. */
c7697e1f 1309GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
79aceca5 1310{
26d67362
AJ		 1311 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1312 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5 1313}
79aceca5 1314/* cntlzw */
26d67362
AJ		 1315GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER)
1316{
1317 tcg_gen_helper_1_1(helper_cntlzw, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1318 if (unlikely(Rc(ctx->opcode) != 0))
2e31f5d3 1319 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
26d67362 1320}
79aceca5 1321/* eqv & eqv. */
26d67362 1322GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
79aceca5 1323/* extsb & extsb. */
26d67362 1324GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
79aceca5 1325/* extsh & extsh. */
26d67362 1326GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
79aceca5 1327/* nand & nand. */
26d67362 1328GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
79aceca5 1329/* nor & nor. */
26d67362 1330GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
79aceca5 1331/* or & or. */
9a64fbe4
FB		 1332GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER)
1333{
76a66253
JM		 1334 int rs, ra, rb;
1335
1336 rs = rS(ctx->opcode);
1337 ra = rA(ctx->opcode);
1338 rb = rB(ctx->opcode);
1339 /* Optimisation for mr. ri case */
1340 if (rs != ra || rs != rb) {
26d67362
AJ		 1341 if (rs != rb)
1342 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1343 else
1344 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
76a66253 1345 if (unlikely(Rc(ctx->opcode) != 0))
26d67362 1346 gen_set_Rc0(ctx, cpu_gpr[ra]);
76a66253 1347 } else if (unlikely(Rc(ctx->opcode) != 0)) {
26d67362 1348 gen_set_Rc0(ctx, cpu_gpr[rs]);
c80f84e3
JM		 1349#if defined(TARGET_PPC64)
1350 } else {
26d67362
AJ		 1351 int prio = 0;
1352
c80f84e3
JM		 1353 switch (rs) {
1354 case 1:
1355 /* Set process priority to low */
26d67362 1356 prio = 2;
c80f84e3
JM		 1357 break;
1358 case 6:
1359 /* Set process priority to medium-low */
26d67362 1360 prio = 3;
c80f84e3
JM		 1361 break;
1362 case 2:
1363 /* Set process priority to normal */
26d67362 1364 prio = 4;
c80f84e3 1365 break;
be147d08
JM		 1366#if !defined(CONFIG_USER_ONLY)
1367 case 31:
1368 if (ctx->supervisor > 0) {
1369 /* Set process priority to very low */
26d67362 1370 prio = 1;
be147d08
JM		 1371 }
1372 break;
1373 case 5:
1374 if (ctx->supervisor > 0) {
1375 /* Set process priority to medium-hight */
26d67362 1376 prio = 5;
be147d08
JM		 1377 }
1378 break;
1379 case 3:
1380 if (ctx->supervisor > 0) {
1381 /* Set process priority to high */
26d67362 1382 prio = 6;
be147d08
JM		 1383 }
1384 break;
be147d08
JM		 1385 case 7:
1386 if (ctx->supervisor > 1) {
1387 /* Set process priority to very high */
26d67362 1388 prio = 7;
be147d08
JM		 1389 }
1390 break;
be147d08 1391#endif
c80f84e3
JM		 1392 default:
1393 /* nop */
1394 break;
1395 }
26d67362 1396 if (prio) {
ea363694
AJ		 1397 TCGv t0 = tcg_temp_new(TCG_TYPE_TL);
1398 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, spr[SPR_PPR]));
1399 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1400 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
1401 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, spr[SPR_PPR]));
1402 tcg_temp_free(t0);
26d67362 1403 }
c80f84e3 1404#endif
9a64fbe4 1405 }
9a64fbe4 1406}
79aceca5 1407/* orc & orc. */
26d67362 1408GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
79aceca5 1409/* xor & xor. */
9a64fbe4
FB		 1410GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER)
1411{
9a64fbe4 1412 /* Optimisation for "set to zero" case */
26d67362 1413 if (rS(ctx->opcode) != rB(ctx->opcode))
312179c4 1414 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
26d67362
AJ		 1415 else
1416 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
76a66253 1417 if (unlikely(Rc(ctx->opcode) != 0))
26d67362 1418 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
9a64fbe4 1419}
79aceca5
FB		 1420/* ori */
1421GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1422{
76a66253 1423 target_ulong uimm = UIMM(ctx->opcode);
79aceca5 1424
9a64fbe4
FB		 1425 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1426 /* NOP */
76a66253 1427 /* XXX: should handle special NOPs for POWER series */
9a64fbe4 1428 return;
76a66253 1429 }
26d67362 1430 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
79aceca5
FB		 1431}
1432/* oris */
1433GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1434{
76a66253 1435 target_ulong uimm = UIMM(ctx->opcode);
79aceca5 1436
9a64fbe4
FB		 1437 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1438 /* NOP */
1439 return;
76a66253 1440 }
26d67362 1441 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
79aceca5
FB		 1442}
1443/* xori */
1444GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1445{
76a66253 1446 target_ulong uimm = UIMM(ctx->opcode);
9a64fbe4
FB		 1447
1448 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1449 /* NOP */
1450 return;
1451 }
26d67362 1452 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
79aceca5 1453}
79aceca5
FB		 1454/* xoris */
1455GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1456{
76a66253 1457 target_ulong uimm = UIMM(ctx->opcode);
9a64fbe4
FB		 1458
1459 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1460 /* NOP */
1461 return;
1462 }
26d67362 1463 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
79aceca5 1464}
d9bce9d9 1465/* popcntb : PowerPC 2.03 specification */
05332d70 1466GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB)
d9bce9d9 1467{
d9bce9d9
JM		 1468#if defined(TARGET_PPC64)
1469 if (ctx->sf_mode)
26d67362 1470 tcg_gen_helper_1_1(helper_popcntb_64, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
d9bce9d9
JM		 1471 else
1472#endif
26d67362 1473 tcg_gen_helper_1_1(helper_popcntb, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
d9bce9d9
JM		 1474}
1475
1476#if defined(TARGET_PPC64)
1477/* extsw & extsw. */
26d67362 1478GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
d9bce9d9 1479/* cntlzd */
26d67362
AJ		 1480GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B)
1481{
1482 tcg_gen_helper_1_1(helper_cntlzd, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1483 if (unlikely(Rc(ctx->opcode) != 0))
1484 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1485}
d9bce9d9
JM		 1486#endif
1487
79aceca5
FB		 1488/*** Integer rotate ***/
1489/* rlwimi & rlwimi. */
1490GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1491{
76a66253 1492 uint32_t mb, me, sh;
79aceca5
FB		 1493
1494 mb = MB(ctx->opcode);
1495 me = ME(ctx->opcode);
76a66253 1496 sh = SH(ctx->opcode);
d03ef511
AJ		 1497 if (likely(sh == 0 && mb == 0 && me == 31)) {
1498 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1499 } else {
1500 TCGv t0, t1;
1501 target_ulong mask;
1502
1503 t0 = tcg_temp_new(TCG_TYPE_TL);
1504 t1 = tcg_temp_new(TCG_TYPE_TL);
1505 if (likely(sh == 0)) {
1506 tcg_gen_mov_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1507 } else {
1508 tcg_gen_ext32u_tl(t1, cpu_gpr[rS(ctx->opcode)]);
1509 tcg_gen_shli_tl(t0, t1, sh);
1510 tcg_gen_shri_tl(t1, t1, 32 - sh);
1511 tcg_gen_or_tl(t0, t0, t1);
76a66253 1512 }
76a66253 1513#if defined(TARGET_PPC64)
d03ef511
AJ		 1514 mb += 32;
1515 me += 32;
76a66253 1516#endif
d03ef511
AJ		 1517 mask = MASK(mb, me);
1518 tcg_gen_andi_tl(t0, t0, mask);
1519 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1520 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1521 tcg_temp_free(t0);
1522 tcg_temp_free(t1);
1523 }
76a66253 1524 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1525 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5
FB		 1526}
1527/* rlwinm & rlwinm. */
1528GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1529{
1530 uint32_t mb, me, sh;
3b46e624 1531
79aceca5
FB		 1532 sh = SH(ctx->opcode);
1533 mb = MB(ctx->opcode);
1534 me = ME(ctx->opcode);
d03ef511
AJ		 1535
1536 if (likely(mb == 0 && me == (31 - sh))) {
1537 if (likely(sh == 0)) {
1538 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1539 } else {
1540 TCGv t0 = tcg_temp_new(TCG_TYPE_TL);
1541 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1542 tcg_gen_shli_tl(t0, t0, sh);
1543 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1544 tcg_temp_free(t0);
79aceca5 1545 }
d03ef511
AJ		 1546 } else if (likely(sh != 0 && me == 31 && sh == (32 - mb))) {
1547 TCGv t0 = tcg_temp_new(TCG_TYPE_TL);
1548 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1549 tcg_gen_shri_tl(t0, t0, mb);
1550 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1551 tcg_temp_free(t0);
1552 } else {
1553 TCGv t0 = tcg_temp_new(TCG_TYPE_TL);
1554 if (likely(sh != 0)) {
1555 TCGv t1 = tcg_temp_new(TCG_TYPE_TL);
1556 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1557 tcg_gen_shli_tl(t1, t0, sh);
1558 tcg_gen_shri_tl(t0, t0, 32 - sh);
1559 tcg_gen_or_tl(t0, t0, t1);
1560 tcg_temp_free(t1);
1561 } else {
1562 tcg_gen_mov_tl(t0, cpu_gpr[rS(ctx->opcode)]);
79aceca5 1563 }
76a66253 1564#if defined(TARGET_PPC64)
d03ef511
AJ		 1565 mb += 32;
1566 me += 32;
76a66253 1567#endif
d03ef511
AJ		 1568 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1569 tcg_temp_free(t0);
1570 }
76a66253 1571 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1572 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5
FB		 1573}
1574/* rlwnm & rlwnm. */
1575GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1576{
1577 uint32_t mb, me;
d03ef511 1578 TCGv t0, t1, t2, t3;
79aceca5
FB		 1579
1580 mb = MB(ctx->opcode);
1581 me = ME(ctx->opcode);
d03ef511
AJ		 1582 t0 = tcg_temp_new(TCG_TYPE_TL);
1583 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f);
1584 t1 = tcg_temp_new(TCG_TYPE_TL);
1585 tcg_gen_ext32u_tl(t1, cpu_gpr[rS(ctx->opcode)]);
1586 t2 = tcg_temp_new(TCG_TYPE_TL);
1587 tcg_gen_shl_tl(t2, t1, t0);
1588 t3 = tcg_const_tl(32);
1589 tcg_gen_sub_tl(t0, t3, t0);
1590 tcg_temp_free(t3);
1591 tcg_gen_shr_tl(t1, t1, t0);
1592 tcg_temp_free(t0);
1593 tcg_gen_or_tl(t2, t2, t1);
1594 tcg_temp_free(t1);
76a66253
JM		 1595 if (unlikely(mb != 0 || me != 31)) {
1596#if defined(TARGET_PPC64)
1597 mb += 32;
1598 me += 32;
1599#endif
d03ef511
AJ		 1600 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t2, MASK(mb, me));
1601 } else {
1602 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t2);
79aceca5 1603 }
d03ef511 1604 tcg_temp_free(t2);
76a66253 1605 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1606 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5
FB		 1607}
1608
d9bce9d9
JM		 1609#if defined(TARGET_PPC64)
1610#define GEN_PPC64_R2(name, opc1, opc2) \
c7697e1f 1611GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
d9bce9d9
JM		 1612{ \
1613 gen_##name(ctx, 0); \
1614} \
c7697e1f
JM		 1615GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
1616 PPC_64B) \
d9bce9d9
JM		 1617{ \
1618 gen_##name(ctx, 1); \
1619}
1620#define GEN_PPC64_R4(name, opc1, opc2) \
c7697e1f 1621GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
d9bce9d9
JM		 1622{ \
1623 gen_##name(ctx, 0, 0); \
1624} \
c7697e1f
JM		 1625GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
1626 PPC_64B) \
d9bce9d9
JM		 1627{ \
1628 gen_##name(ctx, 0, 1); \
1629} \
c7697e1f
JM		 1630GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
1631 PPC_64B) \
d9bce9d9
JM		 1632{ \
1633 gen_##name(ctx, 1, 0); \
1634} \
c7697e1f
JM		 1635GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
1636 PPC_64B) \
d9bce9d9
JM		 1637{ \
1638 gen_##name(ctx, 1, 1); \
1639}
51789c41 1640
b068d6a7
JM		 1641static always_inline void gen_rldinm (DisasContext *ctx, uint32_t mb,
1642 uint32_t me, uint32_t sh)
51789c41 1643{
d03ef511
AJ		 1644 if (likely(sh != 0 && mb == 0 && me == (63 - sh))) {
1645 tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1646 } else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) {
1647 tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb);
1648 } else {
1649 TCGv t0 = tcg_temp_new(TCG_TYPE_TL);
1650 if (likely(sh != 0)) {
1651 TCGv t1 = tcg_temp_new(TCG_TYPE_TL);
1652 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1653 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 64 - sh);
1654 tcg_gen_or_tl(t0, t0, t1);
1655 tcg_temp_free(t1);
1656 } else {
1657 tcg_gen_mov_tl(t0, cpu_gpr[rS(ctx->opcode)]);
51789c41 1658 }
d03ef511
AJ		 1659 if (likely(mb == 0 && me == 63)) {
1660 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1661 } else {
1662 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
51789c41 1663 }
d03ef511 1664 tcg_temp_free(t0);
51789c41 1665 }
51789c41 1666 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1667 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
51789c41 1668}
d9bce9d9 1669/* rldicl - rldicl. */
b068d6a7 1670static always_inline void gen_rldicl (DisasContext *ctx, int mbn, int shn)
d9bce9d9 1671{
51789c41 1672 uint32_t sh, mb;
d9bce9d9 1673
9d53c753
JM		 1674 sh = SH(ctx->opcode) | (shn << 5);
1675 mb = MB(ctx->opcode) | (mbn << 5);
51789c41 1676 gen_rldinm(ctx, mb, 63, sh);
d9bce9d9 1677}
51789c41 1678GEN_PPC64_R4(rldicl, 0x1E, 0x00);
d9bce9d9 1679/* rldicr - rldicr. */
b068d6a7 1680static always_inline void gen_rldicr (DisasContext *ctx, int men, int shn)
d9bce9d9 1681{
51789c41 1682 uint32_t sh, me;
d9bce9d9 1683
9d53c753
JM		 1684 sh = SH(ctx->opcode) | (shn << 5);
1685 me = MB(ctx->opcode) | (men << 5);
51789c41 1686 gen_rldinm(ctx, 0, me, sh);
d9bce9d9 1687}
51789c41 1688GEN_PPC64_R4(rldicr, 0x1E, 0x02);
d9bce9d9 1689/* rldic - rldic. */
b068d6a7 1690static always_inline void gen_rldic (DisasContext *ctx, int mbn, int shn)
d9bce9d9 1691{
51789c41 1692 uint32_t sh, mb;
d9bce9d9 1693
9d53c753
JM		 1694 sh = SH(ctx->opcode) | (shn << 5);
1695 mb = MB(ctx->opcode) | (mbn << 5);
51789c41
JM		 1696 gen_rldinm(ctx, mb, 63 - sh, sh);
1697}
1698GEN_PPC64_R4(rldic, 0x1E, 0x04);
1699
b068d6a7
JM		 1700static always_inline void gen_rldnm (DisasContext *ctx, uint32_t mb,
1701 uint32_t me)
51789c41 1702{
d03ef511
AJ		 1703 TCGv t0, t1, t2;
1704
1705 mb = MB(ctx->opcode);
1706 me = ME(ctx->opcode);
1707 t0 = tcg_temp_new(TCG_TYPE_TL);
1708 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1709 t1 = tcg_temp_new(TCG_TYPE_TL);
1710 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t0);
1711 t2 = tcg_const_tl(32);
1712 tcg_gen_sub_tl(t0, t2, t0);
1713 tcg_temp_free(t2);
1714 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1715 tcg_gen_or_tl(t1, t1, t0);
1716 tcg_temp_free(t0);
51789c41 1717 if (unlikely(mb != 0 || me != 63)) {
d03ef511
AJ		 1718 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t1, MASK(mb, me));
1719 } else
1720 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
1721 tcg_temp_free(t1);
51789c41 1722 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1723 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
d9bce9d9 1724}
51789c41 1725
d9bce9d9 1726/* rldcl - rldcl. */
b068d6a7 1727static always_inline void gen_rldcl (DisasContext *ctx, int mbn)
d9bce9d9 1728{
51789c41 1729 uint32_t mb;
d9bce9d9 1730
9d53c753 1731 mb = MB(ctx->opcode) | (mbn << 5);
51789c41 1732 gen_rldnm(ctx, mb, 63);
d9bce9d9 1733}
36081602 1734GEN_PPC64_R2(rldcl, 0x1E, 0x08);
d9bce9d9 1735/* rldcr - rldcr. */
b068d6a7 1736static always_inline void gen_rldcr (DisasContext *ctx, int men)
d9bce9d9 1737{
51789c41 1738 uint32_t me;
d9bce9d9 1739
9d53c753 1740 me = MB(ctx->opcode) | (men << 5);
51789c41 1741 gen_rldnm(ctx, 0, me);
d9bce9d9 1742}
36081602 1743GEN_PPC64_R2(rldcr, 0x1E, 0x09);
d9bce9d9 1744/* rldimi - rldimi. */
b068d6a7 1745static always_inline void gen_rldimi (DisasContext *ctx, int mbn, int shn)
d9bce9d9 1746{
271a916e 1747 uint32_t sh, mb, me;
d9bce9d9 1748
9d53c753
JM		 1749 sh = SH(ctx->opcode) | (shn << 5);
1750 mb = MB(ctx->opcode) | (mbn << 5);
271a916e 1751 me = 63 - sh;
d03ef511
AJ		 1752 if (unlikely(sh == 0 && mb == 0)) {
1753 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1754 } else {
1755 TCGv t0, t1;
1756 target_ulong mask;
1757
1758 t0 = tcg_temp_new(TCG_TYPE_TL);
1759 t1 = tcg_temp_new(TCG_TYPE_TL);
1760 if (likely(sh == 0)) {
1761 tcg_gen_mov_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1762 } else {
1763 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1764 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 64 - sh);
1765 tcg_gen_or_tl(t0, t0, t1);
51789c41 1766 }
d03ef511
AJ		 1767 mask = MASK(mb, me);
1768 tcg_gen_andi_tl(t0, t0, mask);
1769 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1770 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1771 tcg_temp_free(t0);
1772 tcg_temp_free(t1);
51789c41 1773 }
51789c41 1774 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1775 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
d9bce9d9 1776}
36081602 1777GEN_PPC64_R4(rldimi, 0x1E, 0x06);
d9bce9d9
JM		 1778#endif
1779
79aceca5
FB		 1780/*** Integer shift ***/
1781/* slw & slw. */
26d67362
AJ		 1782GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER)
1783{
1784 TCGv temp;
1785 int l1, l2;
1786 l1 = gen_new_label();
1787 l2 = gen_new_label();
1788
1789 temp = tcg_temp_local_new(TCG_TYPE_TL);
1790 tcg_gen_andi_tl(temp, cpu_gpr[rB(ctx->opcode)], 0x20);
1791 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
1792 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1793 tcg_gen_br(l2);
1794 gen_set_label(l1);
1795 tcg_gen_andi_tl(temp, cpu_gpr[rB(ctx->opcode)], 0x3f);
1796 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], temp);
1797 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
1798 gen_set_label(l2);
1799 tcg_temp_free(temp);
1800 if (unlikely(Rc(ctx->opcode) != 0))
1801 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1802}
79aceca5 1803/* sraw & sraw. */
26d67362
AJ		 1804GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER)
1805{
1806 tcg_gen_helper_1_2(helper_sraw, cpu_gpr[rA(ctx->opcode)],
1807 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1808 if (unlikely(Rc(ctx->opcode) != 0))
1809 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1810}
79aceca5
FB		 1811/* srawi & srawi. */
1812GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER)
1813{
26d67362
AJ		 1814 int sh = SH(ctx->opcode);
1815 if (sh != 0) {
1816 int l1, l2;
1817 TCGv temp;
1818 l1 = gen_new_label();
1819 l2 = gen_new_label();
1820 temp = tcg_temp_local_new(TCG_TYPE_TL);
1821 tcg_gen_ext32s_tl(temp, cpu_gpr[rS(ctx->opcode)]);
1822 tcg_gen_brcondi_tl(TCG_COND_GE, temp, 0, l1);
1823 tcg_gen_andi_tl(temp, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
1824 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
269f3e95 1825 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
26d67362
AJ		 1826 tcg_gen_br(l2);
1827 gen_set_label(l1);
269f3e95 1828 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
26d67362
AJ		 1829 gen_set_label(l2);
1830 tcg_gen_ext32s_tl(temp, cpu_gpr[rS(ctx->opcode)]);
1831 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], temp, sh);
1832 tcg_temp_free(temp);
1833 } else {
1834 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
269f3e95 1835 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
d9bce9d9 1836 }
76a66253 1837 if (unlikely(Rc(ctx->opcode) != 0))
26d67362 1838 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5
FB		 1839}
1840/* srw & srw. */
26d67362
AJ		 1841GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER)
1842{
1843 TCGv temp;
1844 int l1, l2;
1845 l1 = gen_new_label();
1846 l2 = gen_new_label();
d9bce9d9 1847
26d67362
AJ		 1848 temp = tcg_temp_local_new(TCG_TYPE_TL);
1849 tcg_gen_andi_tl(temp, cpu_gpr[rB(ctx->opcode)], 0x20);
1850 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
1851 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1852 tcg_gen_br(l2);
1853 gen_set_label(l1);
1854 tcg_gen_andi_tl(temp, cpu_gpr[rB(ctx->opcode)], 0x3f);
1855 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], temp);
1856 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
1857 gen_set_label(l2);
1858 tcg_temp_free(temp);
1859 if (unlikely(Rc(ctx->opcode) != 0))
1860 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1861}
d9bce9d9
JM		 1862#if defined(TARGET_PPC64)
1863/* sld & sld. */
26d67362
AJ		 1864GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B)
1865{
1866 TCGv temp;
1867 int l1, l2;
1868 l1 = gen_new_label();
1869 l2 = gen_new_label();
1870
1871 temp = tcg_temp_local_new(TCG_TYPE_TL);
1872 tcg_gen_andi_tl(temp, cpu_gpr[rB(ctx->opcode)], 0x40);
1873 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
1874 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1875 tcg_gen_br(l2);
1876 gen_set_label(l1);
1877 tcg_gen_andi_tl(temp, cpu_gpr[rB(ctx->opcode)], 0x7f);
1878 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], temp);
1879 gen_set_label(l2);
1880 tcg_temp_free(temp);
1881 if (unlikely(Rc(ctx->opcode) != 0))
1882 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1883}
d9bce9d9 1884/* srad & srad. */
26d67362
AJ		 1885GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B)
1886{
1887 tcg_gen_helper_1_2(helper_srad, cpu_gpr[rA(ctx->opcode)],
1888 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1889 if (unlikely(Rc(ctx->opcode) != 0))
1890 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1891}
d9bce9d9 1892/* sradi & sradi. */
b068d6a7 1893static always_inline void gen_sradi (DisasContext *ctx, int n)
d9bce9d9 1894{
26d67362 1895 int sh = SH(ctx->opcode) + (n << 5);
d9bce9d9 1896 if (sh != 0) {
26d67362
AJ		 1897 int l1, l2;
1898 TCGv temp;
1899 l1 = gen_new_label();
1900 l2 = gen_new_label();
1901 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
1902 temp = tcg_temp_new(TCG_TYPE_TL);
1903 tcg_gen_andi_tl(temp, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
1904 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
269f3e95 1905 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
26d67362
AJ		 1906 tcg_gen_br(l2);
1907 gen_set_label(l1);
269f3e95 1908 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
26d67362
AJ		 1909 gen_set_label(l2);
1910 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1911 } else {
1912 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
269f3e95 1913 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
d9bce9d9 1914 }
d9bce9d9 1915 if (unlikely(Rc(ctx->opcode) != 0))
26d67362 1916 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
d9bce9d9 1917}
c7697e1f 1918GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B)
d9bce9d9
JM		 1919{
1920 gen_sradi(ctx, 0);
1921}
c7697e1f 1922GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B)
d9bce9d9
JM		 1923{
1924 gen_sradi(ctx, 1);
1925}
1926/* srd & srd. */
26d67362
AJ		 1927GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B)
1928{
1929 TCGv temp;
1930 int l1, l2;
1931 l1 = gen_new_label();
1932 l2 = gen_new_label();
1933
1934 temp = tcg_temp_local_new(TCG_TYPE_TL);
1935 tcg_gen_andi_tl(temp, cpu_gpr[rB(ctx->opcode)], 0x40);
1936 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
1937 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1938 tcg_gen_br(l2);
1939 gen_set_label(l1);
1940 tcg_gen_andi_tl(temp, cpu_gpr[rB(ctx->opcode)], 0x7f);
1941 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], temp);
1942 gen_set_label(l2);
1943 tcg_temp_free(temp);
1944 if (unlikely(Rc(ctx->opcode) != 0))
1945 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1946}
d9bce9d9 1947#endif
79aceca5
FB		 1948
1949/*** Floating-Point arithmetic ***/
7c58044c 1950#define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
a750fc0b 1951GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type) \
9a64fbe4 1952{ \
76a66253 1953 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 1954 GEN_EXCP_NO_FP(ctx); \
3cc62370
FB		 1955 return; \
1956 } \
a5e26afa
AJ		 1957 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rA(ctx->opcode)]); \
1958 tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rC(ctx->opcode)]); \
1959 tcg_gen_mov_i64(cpu_FT[2], cpu_fpr[rB(ctx->opcode)]); \
7c58044c 1960 gen_reset_fpstatus(); \
4ecc3190
FB		 1961 gen_op_f##op(); \
1962 if (isfloat) { \
1963 gen_op_frsp(); \
1964 } \
a5e26afa 1965 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
7c58044c 1966 gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
9a64fbe4
FB		 1967}
1968
7c58044c
JM		 1969#define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
1970_GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
1971_GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
9a64fbe4 1972
7c58044c
JM		 1973#define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
1974GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \
9a64fbe4 1975{ \
76a66253 1976 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 1977 GEN_EXCP_NO_FP(ctx); \
3cc62370
FB		 1978 return; \
1979 } \
a5e26afa
AJ		 1980 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rA(ctx->opcode)]); \
1981 tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rB(ctx->opcode)]); \
7c58044c 1982 gen_reset_fpstatus(); \
4ecc3190
FB		 1983 gen_op_f##op(); \
1984 if (isfloat) { \
1985 gen_op_frsp(); \
1986 } \
a5e26afa 1987 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
7c58044c 1988 gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
9a64fbe4 1989}
7c58044c
JM		 1990#define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
1991_GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
1992_GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
9a64fbe4 1993
7c58044c
JM		 1994#define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
1995GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \
9a64fbe4 1996{ \
76a66253 1997 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 1998 GEN_EXCP_NO_FP(ctx); \
3cc62370
FB		 1999 return; \
2000 } \
a5e26afa
AJ		 2001 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rA(ctx->opcode)]); \
2002 tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rC(ctx->opcode)]); \
7c58044c 2003 gen_reset_fpstatus(); \
4ecc3190
FB		 2004 gen_op_f##op(); \
2005 if (isfloat) { \
2006 gen_op_frsp(); \
2007 } \
a5e26afa 2008 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
7c58044c 2009 gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
9a64fbe4 2010}
7c58044c
JM		 2011#define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
2012_GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2013_GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
9a64fbe4 2014
7c58044c 2015#define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
a750fc0b 2016GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type) \
9a64fbe4 2017{ \
76a66253 2018 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 2019 GEN_EXCP_NO_FP(ctx); \
3cc62370
FB		 2020 return; \
2021 } \
a5e26afa 2022 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]); \
7c58044c 2023 gen_reset_fpstatus(); \
9a64fbe4 2024 gen_op_f##name(); \
a5e26afa 2025 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
7c58044c 2026 gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
79aceca5
FB		 2027}
2028
7c58044c 2029#define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
a750fc0b 2030GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type) \
9a64fbe4 2031{ \
76a66253 2032 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 2033 GEN_EXCP_NO_FP(ctx); \
3cc62370
FB		 2034 return; \
2035 } \
a5e26afa 2036 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]); \
7c58044c 2037 gen_reset_fpstatus(); \
9a64fbe4 2038 gen_op_f##name(); \
a5e26afa 2039 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
7c58044c 2040 gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
79aceca5
FB		 2041}
2042
9a64fbe4 2043/* fadd - fadds */
7c58044c 2044GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
4ecc3190 2045/* fdiv - fdivs */
7c58044c 2046GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
4ecc3190 2047/* fmul - fmuls */
7c58044c 2048GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
79aceca5 2049
d7e4b87e 2050/* fre */
7c58044c 2051GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
d7e4b87e 2052
a750fc0b 2053/* fres */
7c58044c 2054GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
79aceca5 2055
a750fc0b 2056/* frsqrte */
7c58044c
JM		 2057GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
2058
2059/* frsqrtes */
2060static always_inline void gen_op_frsqrtes (void)
2061{
2062 gen_op_frsqrte();
2063 gen_op_frsp();
2064}
1b413d55 2065GEN_FLOAT_BS(rsqrtes, 0x3B, 0x1A, 1, PPC_FLOAT_FRSQRTES);
79aceca5 2066
a750fc0b 2067/* fsel */
7c58044c 2068_GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
4ecc3190 2069/* fsub - fsubs */
7c58044c 2070GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
79aceca5
FB		 2071/* Optional: */
2072/* fsqrt */
a750fc0b 2073GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
c7d344af 2074{
76a66253 2075 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2076 GEN_EXCP_NO_FP(ctx);
c7d344af
FB		 2077 return;
2078 }
a5e26afa 2079 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]);
7c58044c 2080 gen_reset_fpstatus();
c7d344af 2081 gen_op_fsqrt();
a5e26afa 2082 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
7c58044c 2083 gen_compute_fprf(1, Rc(ctx->opcode) != 0);
c7d344af 2084}
79aceca5 2085
a750fc0b 2086GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
79aceca5 2087{
76a66253 2088 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2089 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2090 return;
2091 }
a5e26afa 2092 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]);
7c58044c 2093 gen_reset_fpstatus();
4ecc3190
FB		 2094 gen_op_fsqrt();
2095 gen_op_frsp();
a5e26afa 2096 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
7c58044c 2097 gen_compute_fprf(1, Rc(ctx->opcode) != 0);
79aceca5
FB		 2098}
2099
2100/*** Floating-Point multiply-and-add ***/
4ecc3190 2101/* fmadd - fmadds */
7c58044c 2102GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
4ecc3190 2103/* fmsub - fmsubs */
7c58044c 2104GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
4ecc3190 2105/* fnmadd - fnmadds */
7c58044c 2106GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
4ecc3190 2107/* fnmsub - fnmsubs */
7c58044c 2108GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
79aceca5
FB		 2109
2110/*** Floating-Point round & convert ***/
2111/* fctiw */
7c58044c 2112GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
79aceca5 2113/* fctiwz */
7c58044c 2114GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
79aceca5 2115/* frsp */
7c58044c 2116GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
426613db
JM		 2117#if defined(TARGET_PPC64)
2118/* fcfid */
7c58044c 2119GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B);
426613db 2120/* fctid */
7c58044c 2121GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B);
426613db 2122/* fctidz */
7c58044c 2123GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B);
426613db 2124#endif
79aceca5 2125
d7e4b87e 2126/* frin */
7c58044c 2127GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
d7e4b87e 2128/* friz */
7c58044c 2129GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
d7e4b87e 2130/* frip */
7c58044c 2131GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
d7e4b87e 2132/* frim */
7c58044c 2133GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
d7e4b87e 2134
79aceca5
FB		 2135/*** Floating-Point compare ***/
2136/* fcmpo */
76a66253 2137GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT)
79aceca5 2138{
76a66253 2139 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2140 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2141 return;
2142 }
a5e26afa
AJ		 2143 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rA(ctx->opcode)]);
2144 tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rB(ctx->opcode)]);
7c58044c 2145 gen_reset_fpstatus();
e1571908 2146 tcg_gen_helper_1_0(helper_fcmpo, cpu_crf[crfD(ctx->opcode)]);
7c58044c 2147 gen_op_float_check_status();
79aceca5
FB		 2148}
2149
2150/* fcmpu */
76a66253 2151GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT)
79aceca5 2152{
76a66253 2153 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2154 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2155 return;
2156 }
a5e26afa
AJ		 2157 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rA(ctx->opcode)]);
2158 tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rB(ctx->opcode)]);
7c58044c 2159 gen_reset_fpstatus();
e1571908 2160 tcg_gen_helper_1_0(helper_fcmpu, cpu_crf[crfD(ctx->opcode)]);
7c58044c 2161 gen_op_float_check_status();
79aceca5
FB		 2162}
2163
9a64fbe4
FB		 2164/*** Floating-point move ***/
2165/* fabs */
7c58044c
JM		 2166/* XXX: beware that fabs never checks for NaNs nor update FPSCR */
2167GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT);
9a64fbe4
FB		 2168
2169/* fmr - fmr. */
7c58044c 2170/* XXX: beware that fmr never checks for NaNs nor update FPSCR */
9a64fbe4
FB		 2171GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT)
2172{
76a66253 2173 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2174 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2175 return;
2176 }
a5e26afa
AJ		 2177 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]);
2178 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
7c58044c 2179 gen_compute_fprf(0, Rc(ctx->opcode) != 0);
9a64fbe4
FB		 2180}
2181
2182/* fnabs */
7c58044c
JM		 2183/* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
2184GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT);
9a64fbe4 2185/* fneg */
7c58044c
JM		 2186/* XXX: beware that fneg never checks for NaNs nor update FPSCR */
2187GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT);
9a64fbe4 2188
79aceca5
FB		 2189/*** Floating-Point status & ctrl register ***/
2190/* mcrfs */
2191GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT)
2192{
7c58044c
JM		 2193 int bfa;
2194
76a66253 2195 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2196 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2197 return;
2198 }
7c58044c
JM		 2199 gen_optimize_fprf();
2200 bfa = 4 * (7 - crfS(ctx->opcode));
e1571908
AJ		 2201 tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_fpscr, bfa);
2202 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
7c58044c 2203 gen_op_fpscr_resetbit(~(0xF << bfa));
79aceca5
FB		 2204}
2205
2206/* mffs */
2207GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT)
2208{
76a66253 2209 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2210 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2211 return;
2212 }
7c58044c
JM		 2213 gen_optimize_fprf();
2214 gen_reset_fpstatus();
2215 gen_op_load_fpscr_FT0();
a5e26afa 2216 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
7c58044c 2217 gen_compute_fprf(0, Rc(ctx->opcode) != 0);
79aceca5
FB		 2218}
2219
2220/* mtfsb0 */
2221GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT)
2222{
fb0eaffc 2223 uint8_t crb;
3b46e624 2224
76a66253 2225 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2226 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2227 return;
2228 }
7c58044c
JM		 2229 crb = 32 - (crbD(ctx->opcode) >> 2);
2230 gen_optimize_fprf();
2231 gen_reset_fpstatus();
2232 if (likely(crb != 30 && crb != 29))
2233 gen_op_fpscr_resetbit(~(1 << crb));
2234 if (unlikely(Rc(ctx->opcode) != 0)) {
e1571908 2235 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
7c58044c 2236 }
79aceca5
FB		 2237}
2238
2239/* mtfsb1 */
2240GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT)
2241{
fb0eaffc 2242 uint8_t crb;
3b46e624 2243
76a66253 2244 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2245 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2246 return;
2247 }
7c58044c
JM		 2248 crb = 32 - (crbD(ctx->opcode) >> 2);
2249 gen_optimize_fprf();
2250 gen_reset_fpstatus();
2251 /* XXX: we pretend we can only do IEEE floating-point computations */
2252 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI))
2253 gen_op_fpscr_setbit(crb);
2254 if (unlikely(Rc(ctx->opcode) != 0)) {
e1571908 2255 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
7c58044c
JM		 2256 }
2257 /* We can raise a differed exception */
2258 gen_op_float_check_status();
79aceca5
FB		 2259}
2260
2261/* mtfsf */
2262GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x02010000, PPC_FLOAT)
2263{
76a66253 2264 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2265 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2266 return;
2267 }
7c58044c 2268 gen_optimize_fprf();
a5e26afa 2269 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]);
7c58044c 2270 gen_reset_fpstatus();
28b6751f 2271 gen_op_store_fpscr(FM(ctx->opcode));
7c58044c 2272 if (unlikely(Rc(ctx->opcode) != 0)) {
e1571908 2273 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
7c58044c
JM		 2274 }
2275 /* We can raise a differed exception */
2276 gen_op_float_check_status();
79aceca5
FB		 2277}
2278
2279/* mtfsfi */
2280GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT)
2281{
7c58044c
JM		 2282 int bf, sh;
2283
76a66253 2284 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2285 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2286 return;
2287 }
7c58044c
JM		 2288 bf = crbD(ctx->opcode) >> 2;
2289 sh = 7 - bf;
2290 gen_optimize_fprf();
489251fa 2291 tcg_gen_movi_i64(cpu_FT[0], FPIMM(ctx->opcode) << (4 * sh));
7c58044c
JM		 2292 gen_reset_fpstatus();
2293 gen_op_store_fpscr(1 << sh);
2294 if (unlikely(Rc(ctx->opcode) != 0)) {
e1571908 2295 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
7c58044c
JM		 2296 }
2297 /* We can raise a differed exception */
2298 gen_op_float_check_status();
79aceca5
FB		 2299}
2300
76a66253
JM		 2301/*** Addressing modes ***/
2302/* Register indirect with immediate index : EA = (rA|0) + SIMM */
e2be8d8d
AJ		 2303static always_inline void gen_addr_imm_index (TCGv EA,
2304 DisasContext *ctx,
b068d6a7 2305 target_long maskl)
76a66253
JM		 2306{
2307 target_long simm = SIMM(ctx->opcode);
2308
be147d08 2309 simm &= ~maskl;
e2be8d8d
AJ		 2310 if (rA(ctx->opcode) == 0)
2311 tcg_gen_movi_tl(EA, simm);
2312 else if (likely(simm != 0))
2313 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2314 else
2315 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 2316}
2317
e2be8d8d
AJ		 2318static always_inline void gen_addr_reg_index (TCGv EA,
2319 DisasContext *ctx)
76a66253 2320{
e2be8d8d
AJ		 2321 if (rA(ctx->opcode) == 0)
2322 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2323 else
2324 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
76a66253
JM		 2325}
2326
e2be8d8d
AJ		 2327static always_inline void gen_addr_register (TCGv EA,
2328 DisasContext *ctx)
76a66253 2329{
e2be8d8d
AJ		 2330 if (rA(ctx->opcode) == 0)
2331 tcg_gen_movi_tl(EA, 0);
2332 else
2333 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 2334}
2335
7863667f
JM		 2336#if defined(TARGET_PPC64)
2337#define _GEN_MEM_FUNCS(name, mode) \
2338 &gen_op_##name##_##mode, \
2339 &gen_op_##name##_le_##mode, \
2340 &gen_op_##name##_64_##mode, \
2341 &gen_op_##name##_le_64_##mode
2342#else
2343#define _GEN_MEM_FUNCS(name, mode) \
2344 &gen_op_##name##_##mode, \
2345 &gen_op_##name##_le_##mode
2346#endif
9a64fbe4 2347#if defined(CONFIG_USER_ONLY)
d9bce9d9 2348#if defined(TARGET_PPC64)
7863667f 2349#define NB_MEM_FUNCS 4
d9bce9d9 2350#else
7863667f 2351#define NB_MEM_FUNCS 2
d9bce9d9 2352#endif
7863667f
JM		 2353#define GEN_MEM_FUNCS(name) \
2354 _GEN_MEM_FUNCS(name, raw)
9a64fbe4 2355#else
d9bce9d9 2356#if defined(TARGET_PPC64)
7863667f 2357#define NB_MEM_FUNCS 12
2857068e 2358#else
7863667f 2359#define NB_MEM_FUNCS 6
2857068e 2360#endif
7863667f
JM		 2361#define GEN_MEM_FUNCS(name) \
2362 _GEN_MEM_FUNCS(name, user), \
2363 _GEN_MEM_FUNCS(name, kernel), \
2364 _GEN_MEM_FUNCS(name, hypv)
2365#endif
2366
2367/*** Integer load ***/
2368#define op_ldst(name) (*gen_op_##name[ctx->mem_idx])()
d9bce9d9 2369#define OP_LD_TABLE(width) \
7863667f
JM		 2370static GenOpFunc *gen_op_l##width[NB_MEM_FUNCS] = { \
2371 GEN_MEM_FUNCS(l##width), \
d9bce9d9
JM		 2372};
2373#define OP_ST_TABLE(width) \
7863667f
JM		 2374static GenOpFunc *gen_op_st##width[NB_MEM_FUNCS] = { \
2375 GEN_MEM_FUNCS(st##width), \
d9bce9d9 2376};
9a64fbe4 2377
b61f2753
AJ		 2378
2379#if defined(TARGET_PPC64)
2380#define GEN_QEMU_LD_PPC64(width) \
2381static always_inline void gen_qemu_ld##width##_ppc64(TCGv t0, TCGv t1, int flags)\
2382{ \
2383 if (likely(flags & 2)) \
2384 tcg_gen_qemu_ld##width(t0, t1, flags >> 2); \
2385 else { \
2386 TCGv addr = tcg_temp_new(TCG_TYPE_TL); \
2387 tcg_gen_ext32u_tl(addr, t1); \
2388 tcg_gen_qemu_ld##width(t0, addr, flags >> 2); \
2389 tcg_temp_free(addr); \
2390 } \
2391}
2392GEN_QEMU_LD_PPC64(8u)
2393GEN_QEMU_LD_PPC64(8s)
2394GEN_QEMU_LD_PPC64(16u)
2395GEN_QEMU_LD_PPC64(16s)
2396GEN_QEMU_LD_PPC64(32u)
2397GEN_QEMU_LD_PPC64(32s)
2398GEN_QEMU_LD_PPC64(64)
2399
2400#define GEN_QEMU_ST_PPC64(width) \
2401static always_inline void gen_qemu_st##width##_ppc64(TCGv t0, TCGv t1, int flags)\
2402{ \
2403 if (likely(flags & 2)) \
2404 tcg_gen_qemu_st##width(t0, t1, flags >> 2); \
2405 else { \
2406 TCGv addr = tcg_temp_new(TCG_TYPE_TL); \
2407 tcg_gen_ext32u_tl(addr, t1); \
2408 tcg_gen_qemu_st##width(t0, addr, flags >> 2); \
2409 tcg_temp_free(addr); \
2410 } \
2411}
2412GEN_QEMU_ST_PPC64(8)
2413GEN_QEMU_ST_PPC64(16)
2414GEN_QEMU_ST_PPC64(32)
2415GEN_QEMU_ST_PPC64(64)
2416
ea363694 2417static always_inline void gen_qemu_ld8u(TCGv arg0, TCGv arg1, int flags)
b61f2753 2418{
ea363694 2419 gen_qemu_ld8u_ppc64(arg0, arg1, flags);
b61f2753
AJ		 2420}
2421
ea363694 2422static always_inline void gen_qemu_ld8s(TCGv arg0, TCGv arg1, int flags)
b61f2753 2423{
ea363694 2424 gen_qemu_ld8s_ppc64(arg0, arg1, flags);
b61f2753
AJ		 2425}
2426
ea363694 2427static always_inline void gen_qemu_ld16u(TCGv arg0, TCGv arg1, int flags)
b61f2753
AJ		 2428{
2429 if (unlikely(flags & 1)) {
ea363694
AJ		 2430 TCGv t0;
2431 gen_qemu_ld16u_ppc64(arg0, arg1, flags);
2432 t0 = tcg_temp_new(TCG_TYPE_I32);
2433 tcg_gen_trunc_tl_i32(t0, arg0);
2434 tcg_gen_bswap16_i32(t0, t0);
2435 tcg_gen_extu_i32_tl(arg0, t0);
2436 tcg_temp_free(t0);
b61f2753 2437 } else
ea363694 2438 gen_qemu_ld16u_ppc64(arg0, arg1, flags);
b61f2753
AJ		 2439}
2440
ea363694 2441static always_inline void gen_qemu_ld16s(TCGv arg0, TCGv arg1, int flags)
b61f2753
AJ		 2442{
2443 if (unlikely(flags & 1)) {
ea363694
AJ		 2444 TCGv t0;
2445 gen_qemu_ld16u_ppc64(arg0, arg1, flags);
2446 t0 = tcg_temp_new(TCG_TYPE_I32);
2447 tcg_gen_trunc_tl_i32(t0, arg0);
2448 tcg_gen_bswap16_i32(t0, t0);
2449 tcg_gen_extu_i32_tl(arg0, t0);
2450 tcg_gen_ext16s_tl(arg0, arg0);
2451 tcg_temp_free(t0);
b61f2753 2452 } else
ea363694 2453 gen_qemu_ld16s_ppc64(arg0, arg1, flags);
b61f2753
AJ		 2454}
2455
ea363694 2456static always_inline void gen_qemu_ld32u(TCGv arg0, TCGv arg1, int flags)
b61f2753
AJ		 2457{
2458 if (unlikely(flags & 1)) {
ea363694
AJ		 2459 TCGv t0;
2460 gen_qemu_ld32u_ppc64(arg0, arg1, flags);
2461 t0 = tcg_temp_new(TCG_TYPE_I32);
2462 tcg_gen_trunc_tl_i32(t0, arg0);
2463 tcg_gen_bswap_i32(t0, t0);
2464 tcg_gen_extu_i32_tl(arg0, t0);
2465 tcg_temp_free(t0);
b61f2753 2466 } else
ea363694 2467 gen_qemu_ld32u_ppc64(arg0, arg1, flags);
b61f2753
AJ		 2468}
2469
ea363694 2470static always_inline void gen_qemu_ld32s(TCGv arg0, TCGv arg1, int flags)
b61f2753
AJ		 2471{
2472 if (unlikely(flags & 1)) {
ea363694
AJ		 2473 TCGv t0;
2474 gen_qemu_ld32u_ppc64(arg0, arg1, flags);
2475 t0 = tcg_temp_new(TCG_TYPE_I32);
2476 tcg_gen_trunc_tl_i32(t0, arg0);
2477 tcg_gen_bswap_i32(t0, t0);
2478 tcg_gen_ext_i32_tl(arg0, t0);
2479 tcg_temp_free(t0);
b61f2753 2480 } else
ea363694 2481 gen_qemu_ld32s_ppc64(arg0, arg1, flags);
b61f2753
AJ		 2482}
2483
ea363694 2484static always_inline void gen_qemu_ld64(TCGv arg0, TCGv arg1, int flags)
b61f2753 2485{
ea363694 2486 gen_qemu_ld64_ppc64(arg0, arg1, flags);
b61f2753 2487 if (unlikely(flags & 1))
ea363694 2488 tcg_gen_bswap_i64(arg0, arg0);
b61f2753
AJ		 2489}
2490
ea363694 2491static always_inline void gen_qemu_st8(TCGv arg0, TCGv arg1, int flags)
b61f2753 2492{
ea363694 2493 gen_qemu_st8_ppc64(arg0, arg1, flags);
b61f2753
AJ		 2494}
2495
ea363694 2496static always_inline void gen_qemu_st16(TCGv arg0, TCGv arg1, int flags)
b61f2753
AJ		 2497{
2498 if (unlikely(flags & 1)) {
ea363694
AJ		 2499 TCGv t0, t1;
2500 t0 = tcg_temp_new(TCG_TYPE_I32);
2501 tcg_gen_trunc_tl_i32(t0, arg0);
2502 tcg_gen_ext16u_i32(t0, t0);
2503 tcg_gen_bswap16_i32(t0, t0);
2504 t1 = tcg_temp_new(TCG_TYPE_I64);
2505 tcg_gen_extu_i32_tl(t1, t0);
2506 tcg_temp_free(t0);
2507 gen_qemu_st16_ppc64(t1, arg1, flags);
2508 tcg_temp_free(t1);
b61f2753 2509 } else
ea363694 2510 gen_qemu_st16_ppc64(arg0, arg1, flags);
b61f2753
AJ		 2511}
2512
ea363694 2513static always_inline void gen_qemu_st32(TCGv arg0, TCGv arg1, int flags)
b61f2753
AJ		 2514{
2515 if (unlikely(flags & 1)) {
ea363694
AJ		 2516 TCGv t0, t1;
2517 t0 = tcg_temp_new(TCG_TYPE_I32);
2518 tcg_gen_trunc_tl_i32(t0, arg0);
2519 tcg_gen_bswap_i32(t0, t0);
2520 t1 = tcg_temp_new(TCG_TYPE_I64);
2521 tcg_gen_extu_i32_tl(t1, t0);
2522 tcg_temp_free(t0);
2523 gen_qemu_st32_ppc64(t1, arg1, flags);
2524 tcg_temp_free(t1);
b61f2753 2525 } else
ea363694 2526 gen_qemu_st32_ppc64(arg0, arg1, flags);
b61f2753
AJ		 2527}
2528
ea363694 2529static always_inline void gen_qemu_st64(TCGv arg0, TCGv arg1, int flags)
b61f2753
AJ		 2530{
2531 if (unlikely(flags & 1)) {
ea363694
AJ		 2532 TCGv t0 = tcg_temp_new(TCG_TYPE_I64);
2533 tcg_gen_bswap_i64(t0, arg0);
2534 gen_qemu_st64_ppc64(t0, arg1, flags);
2535 tcg_temp_free(t0);
b61f2753 2536 } else
ea363694 2537 gen_qemu_st64_ppc64(arg0, arg1, flags);
b61f2753
AJ		 2538}
2539
2540
2541#else /* defined(TARGET_PPC64) */
2542#define GEN_QEMU_LD_PPC32(width) \
ea363694 2543static always_inline void gen_qemu_ld##width##_ppc32(TCGv arg0, TCGv arg1, int flags)\
b61f2753 2544{ \
ea363694 2545 tcg_gen_qemu_ld##width(arg0, arg1, flags >> 1); \
b61f2753
AJ		 2546}
2547GEN_QEMU_LD_PPC32(8u)
2548GEN_QEMU_LD_PPC32(8s)
2549GEN_QEMU_LD_PPC32(16u)
2550GEN_QEMU_LD_PPC32(16s)
2551GEN_QEMU_LD_PPC32(32u)
2552GEN_QEMU_LD_PPC32(32s)
2553GEN_QEMU_LD_PPC32(64)
2554
2555#define GEN_QEMU_ST_PPC32(width) \
ea363694 2556static always_inline void gen_qemu_st##width##_ppc32(TCGv arg0, TCGv arg1, int flags)\
b61f2753 2557{ \
ea363694 2558 tcg_gen_qemu_st##width(arg0, arg1, flags >> 1); \
b61f2753
AJ		 2559}
2560GEN_QEMU_ST_PPC32(8)
2561GEN_QEMU_ST_PPC32(16)
2562GEN_QEMU_ST_PPC32(32)
2563GEN_QEMU_ST_PPC32(64)
2564
ea363694 2565static always_inline void gen_qemu_ld8u(TCGv arg0, TCGv arg1, int flags)
b61f2753 2566{
ea363694 2567 gen_qemu_ld8u_ppc32(arg0, arg1, flags >> 1);
b61f2753
AJ		 2568}
2569
ea363694 2570static always_inline void gen_qemu_ld8s(TCGv arg0, TCGv arg1, int flags)
b61f2753 2571{
ea363694 2572 gen_qemu_ld8s_ppc32(arg0, arg1, flags >> 1);
b61f2753
AJ		 2573}
2574
ea363694 2575static always_inline void gen_qemu_ld16u(TCGv arg0, TCGv arg1, int flags)
b61f2753 2576{
ea363694 2577 gen_qemu_ld16u_ppc32(arg0, arg1, flags >> 1);
b61f2753 2578 if (unlikely(flags & 1))
ea363694 2579 tcg_gen_bswap16_i32(arg0, arg0);
b61f2753
AJ		 2580}
2581
ea363694 2582static always_inline void gen_qemu_ld16s(TCGv arg0, TCGv arg1, int flags)
b61f2753
AJ		 2583{
2584 if (unlikely(flags & 1)) {
ea363694
AJ		 2585 gen_qemu_ld16u_ppc32(arg0, arg1, flags);
2586 tcg_gen_bswap16_i32(arg0, arg0);
2587 tcg_gen_ext16s_i32(arg0, arg0);
b61f2753 2588 } else
ea363694 2589 gen_qemu_ld16s_ppc32(arg0, arg1, flags);
b61f2753
AJ		 2590}
2591
ea363694 2592static always_inline void gen_qemu_ld32u(TCGv arg0, TCGv arg1, int flags)
b61f2753 2593{
ea363694 2594 gen_qemu_ld32u_ppc32(arg0, arg1, flags);
b61f2753 2595 if (unlikely(flags & 1))
ea363694 2596 tcg_gen_bswap_i32(arg0, arg0);
b61f2753
AJ		 2597}
2598
ea363694 2599static always_inline void gen_qemu_ld64(TCGv arg0, TCGv arg1, int flags)
b61f2753 2600{
ea363694 2601 gen_qemu_ld64_ppc32(arg0, arg1, flags);
b61f2753 2602 if (unlikely(flags & 1))
ea363694 2603 tcg_gen_bswap_i64(arg0, arg0);
b61f2753
AJ		 2604}
2605
ea363694 2606static always_inline void gen_qemu_st8(TCGv arg0, TCGv arg1, int flags)
b61f2753 2607{
ea363694 2608 gen_qemu_st8_ppc32(arg0, arg1, flags >> 1);
b61f2753
AJ		 2609}
2610
ea363694 2611static always_inline void gen_qemu_st16(TCGv arg0, TCGv arg1, int flags)
b61f2753
AJ		 2612{
2613 if (unlikely(flags & 1)) {
2614 TCGv temp = tcg_temp_new(TCG_TYPE_I32);
ea363694 2615 tcg_gen_ext16u_i32(temp, arg0);
b61f2753 2616 tcg_gen_bswap16_i32(temp, temp);
ea363694 2617 gen_qemu_st16_ppc32(temp, arg1, flags >> 1);
312179c4 2618 tcg_temp_free(temp);
b61f2753 2619 } else
ea363694 2620 gen_qemu_st16_ppc32(arg0, arg1, flags >> 1);
b61f2753
AJ		 2621}
2622
ea363694 2623static always_inline void gen_qemu_st32(TCGv arg0, TCGv arg1, int flags)
b61f2753
AJ		 2624{
2625 if (unlikely(flags & 1)) {
2626 TCGv temp = tcg_temp_new(TCG_TYPE_I32);
ea363694
AJ		 2627 tcg_gen_bswap_i32(temp, arg0);
2628 gen_qemu_st32_ppc32(temp, arg1, flags >> 1);
312179c4 2629 tcg_temp_free(temp);
b61f2753 2630 } else
ea363694 2631 gen_qemu_st32_ppc32(arg0, arg1, flags >> 1);
b61f2753
AJ		 2632}
2633
ea363694 2634static always_inline void gen_qemu_st64(TCGv arg0, TCGv arg1, int flags)
b61f2753
AJ		 2635{
2636 if (unlikely(flags & 1)) {
2637 TCGv temp = tcg_temp_new(TCG_TYPE_I64);
ea363694
AJ		 2638 tcg_gen_bswap_i64(temp, arg0);
2639 gen_qemu_st64_ppc32(temp, arg1, flags >> 1);
312179c4 2640 tcg_temp_free(temp);
b61f2753 2641 } else
ea363694 2642 gen_qemu_st64_ppc32(arg0, arg1, flags >> 1);
b61f2753
AJ		 2643}
2644
2645#endif
2646
d9bce9d9
JM		 2647#define GEN_LD(width, opc, type) \
2648GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2649{ \
b61f2753
AJ		 2650 TCGv EA = tcg_temp_new(TCG_TYPE_TL); \
2651 gen_addr_imm_index(EA, ctx, 0); \
2652 gen_qemu_ld##width(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
2653 tcg_temp_free(EA); \
79aceca5
FB		 2654}
2655
d9bce9d9
JM		 2656#define GEN_LDU(width, opc, type) \
2657GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2658{ \
b61f2753 2659 TCGv EA; \
76a66253
JM		 2660 if (unlikely(rA(ctx->opcode) == 0 || \
2661 rA(ctx->opcode) == rD(ctx->opcode))) { \
e1833e1f 2662 GEN_EXCP_INVAL(ctx); \
9fddaa0c 2663 return; \
9a64fbe4 2664 } \
b61f2753 2665 EA = tcg_temp_new(TCG_TYPE_TL); \
9d53c753 2666 if (type == PPC_64B) \
b61f2753 2667 gen_addr_imm_index(EA, ctx, 0x03); \
9d53c753 2668 else \
b61f2753
AJ		 2669 gen_addr_imm_index(EA, ctx, 0); \
2670 gen_qemu_ld##width(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
2671 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2672 tcg_temp_free(EA); \
79aceca5
FB		 2673}
2674
d9bce9d9
JM		 2675#define GEN_LDUX(width, opc2, opc3, type) \
2676GEN_HANDLER(l##width##ux, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2677{ \
b61f2753 2678 TCGv EA; \
76a66253
JM		 2679 if (unlikely(rA(ctx->opcode) == 0 || \
2680 rA(ctx->opcode) == rD(ctx->opcode))) { \
e1833e1f 2681 GEN_EXCP_INVAL(ctx); \
9fddaa0c 2682 return; \
9a64fbe4 2683 } \
b61f2753
AJ		 2684 EA = tcg_temp_new(TCG_TYPE_TL); \
2685 gen_addr_reg_index(EA, ctx); \
2686 gen_qemu_ld##width(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
2687 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2688 tcg_temp_free(EA); \
79aceca5
FB		 2689}
2690
d9bce9d9
JM		 2691#define GEN_LDX(width, opc2, opc3, type) \
2692GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2693{ \
b61f2753
AJ		 2694 TCGv EA = tcg_temp_new(TCG_TYPE_TL); \
2695 gen_addr_reg_index(EA, ctx); \
2696 gen_qemu_ld##width(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
2697 tcg_temp_free(EA); \
79aceca5
FB		 2698}
2699
d9bce9d9 2700#define GEN_LDS(width, op, type) \
d9bce9d9
JM		 2701GEN_LD(width, op | 0x20, type); \
2702GEN_LDU(width, op | 0x21, type); \
2703GEN_LDUX(width, 0x17, op | 0x01, type); \
2704GEN_LDX(width, 0x17, op | 0x00, type)
79aceca5
FB		 2705
2706/* lbz lbzu lbzux lbzx */
b61f2753 2707GEN_LDS(8u, 0x02, PPC_INTEGER);
79aceca5 2708/* lha lhau lhaux lhax */
b61f2753 2709GEN_LDS(16s, 0x0A, PPC_INTEGER);
79aceca5 2710/* lhz lhzu lhzux lhzx */
b61f2753 2711GEN_LDS(16u, 0x08, PPC_INTEGER);
79aceca5 2712/* lwz lwzu lwzux lwzx */
b61f2753 2713GEN_LDS(32u, 0x00, PPC_INTEGER);
d9bce9d9 2714#if defined(TARGET_PPC64)
d9bce9d9 2715/* lwaux */
b61f2753 2716GEN_LDUX(32s, 0x15, 0x0B, PPC_64B);
d9bce9d9 2717/* lwax */
b61f2753 2718GEN_LDX(32s, 0x15, 0x0A, PPC_64B);
d9bce9d9 2719/* ldux */
b61f2753 2720GEN_LDUX(64, 0x15, 0x01, PPC_64B);
d9bce9d9 2721/* ldx */
b61f2753 2722GEN_LDX(64, 0x15, 0x00, PPC_64B);
d9bce9d9
JM		 2723GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B)
2724{
b61f2753 2725 TCGv EA;
d9bce9d9
JM		 2726 if (Rc(ctx->opcode)) {
2727 if (unlikely(rA(ctx->opcode) == 0 ||
2728 rA(ctx->opcode) == rD(ctx->opcode))) {
e1833e1f 2729 GEN_EXCP_INVAL(ctx);
d9bce9d9
JM		 2730 return;
2731 }
2732 }
b61f2753
AJ		 2733 EA = tcg_temp_new(TCG_TYPE_TL);
2734 gen_addr_imm_index(EA, ctx, 0x03);
d9bce9d9
JM		 2735 if (ctx->opcode & 0x02) {
2736 /* lwa (lwau is undefined) */
b61f2753 2737 gen_qemu_ld32s(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx);
d9bce9d9
JM		 2738 } else {
2739 /* ld - ldu */
b61f2753 2740 gen_qemu_ld64(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx);
d9bce9d9 2741 }
d9bce9d9 2742 if (Rc(ctx->opcode))
b61f2753
AJ		 2743 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2744 tcg_temp_free(EA);
d9bce9d9 2745}
be147d08
JM		 2746/* lq */
2747GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX)
2748{
2749#if defined(CONFIG_USER_ONLY)
2750 GEN_EXCP_PRIVOPC(ctx);
2751#else
2752 int ra, rd;
b61f2753 2753 TCGv EA;
be147d08
JM		 2754
2755 /* Restore CPU state */
2756 if (unlikely(ctx->supervisor == 0)) {
2757 GEN_EXCP_PRIVOPC(ctx);
2758 return;
2759 }
2760 ra = rA(ctx->opcode);
2761 rd = rD(ctx->opcode);
2762 if (unlikely((rd & 1) || rd == ra)) {
2763 GEN_EXCP_INVAL(ctx);
2764 return;
2765 }
2766 if (unlikely(ctx->mem_idx & 1)) {
2767 /* Little-endian mode is not handled */
2768 GEN_EXCP(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2769 return;
2770 }
b61f2753
AJ		 2771 EA = tcg_temp_new(TCG_TYPE_TL);
2772 gen_addr_imm_index(EA, ctx, 0x0F);
2773 gen_qemu_ld64(cpu_gpr[rd], EA, ctx->mem_idx);
2774 tcg_gen_addi_tl(EA, EA, 8);
2775 gen_qemu_ld64(cpu_gpr[rd+1], EA, ctx->mem_idx);
2776 tcg_temp_free(EA);
be147d08
JM		 2777#endif
2778}
d9bce9d9 2779#endif
79aceca5
FB		 2780
2781/*** Integer store ***/
d9bce9d9
JM		 2782#define GEN_ST(width, opc, type) \
2783GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2784{ \
b61f2753
AJ		 2785 TCGv EA = tcg_temp_new(TCG_TYPE_TL); \
2786 gen_addr_imm_index(EA, ctx, 0); \
2787 gen_qemu_st##width(cpu_gpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
2788 tcg_temp_free(EA); \
79aceca5
FB		 2789}
2790
d9bce9d9
JM		 2791#define GEN_STU(width, opc, type) \
2792GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2793{ \
b61f2753 2794 TCGv EA; \
76a66253 2795 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 2796 GEN_EXCP_INVAL(ctx); \
9fddaa0c 2797 return; \
9a64fbe4 2798 } \
b61f2753 2799 EA = tcg_temp_new(TCG_TYPE_TL); \
9d53c753 2800 if (type == PPC_64B) \
b61f2753 2801 gen_addr_imm_index(EA, ctx, 0x03); \
9d53c753 2802 else \
b61f2753
AJ		 2803 gen_addr_imm_index(EA, ctx, 0); \
2804 gen_qemu_st##width(cpu_gpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
2805 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2806 tcg_temp_free(EA); \
79aceca5
FB		 2807}
2808
d9bce9d9
JM		 2809#define GEN_STUX(width, opc2, opc3, type) \
2810GEN_HANDLER(st##width##ux, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2811{ \
b61f2753 2812 TCGv EA; \
76a66253 2813 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 2814 GEN_EXCP_INVAL(ctx); \
9fddaa0c 2815 return; \
9a64fbe4 2816 } \
b61f2753
AJ		 2817 EA = tcg_temp_new(TCG_TYPE_TL); \
2818 gen_addr_reg_index(EA, ctx); \
2819 gen_qemu_st##width(cpu_gpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
2820 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2821 tcg_temp_free(EA); \
79aceca5
FB		 2822}
2823
d9bce9d9
JM		 2824#define GEN_STX(width, opc2, opc3, type) \
2825GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2826{ \
b61f2753
AJ		 2827 TCGv EA = tcg_temp_new(TCG_TYPE_TL); \
2828 gen_addr_reg_index(EA, ctx); \
2829 gen_qemu_st##width(cpu_gpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
2830 tcg_temp_free(EA); \
79aceca5
FB		 2831}
2832
d9bce9d9 2833#define GEN_STS(width, op, type) \
d9bce9d9
JM		 2834GEN_ST(width, op | 0x20, type); \
2835GEN_STU(width, op | 0x21, type); \
2836GEN_STUX(width, 0x17, op | 0x01, type); \
2837GEN_STX(width, 0x17, op | 0x00, type)
79aceca5
FB		 2838
2839/* stb stbu stbux stbx */
b61f2753 2840GEN_STS(8, 0x06, PPC_INTEGER);
79aceca5 2841/* sth sthu sthux sthx */
b61f2753 2842GEN_STS(16, 0x0C, PPC_INTEGER);
79aceca5 2843/* stw stwu stwux stwx */
b61f2753 2844GEN_STS(32, 0x04, PPC_INTEGER);
d9bce9d9 2845#if defined(TARGET_PPC64)
b61f2753
AJ		 2846GEN_STUX(64, 0x15, 0x05, PPC_64B);
2847GEN_STX(64, 0x15, 0x04, PPC_64B);
be147d08 2848GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B)
d9bce9d9 2849{
be147d08 2850 int rs;
b61f2753 2851 TCGv EA;
be147d08
JM		 2852
2853 rs = rS(ctx->opcode);
2854 if ((ctx->opcode & 0x3) == 0x2) {
2855#if defined(CONFIG_USER_ONLY)
2856 GEN_EXCP_PRIVOPC(ctx);
2857#else
2858 /* stq */
2859 if (unlikely(ctx->supervisor == 0)) {
2860 GEN_EXCP_PRIVOPC(ctx);
2861 return;
2862 }
2863 if (unlikely(rs & 1)) {
e1833e1f 2864 GEN_EXCP_INVAL(ctx);
d9bce9d9
JM		 2865 return;
2866 }
be147d08
JM		 2867 if (unlikely(ctx->mem_idx & 1)) {
2868 /* Little-endian mode is not handled */
2869 GEN_EXCP(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2870 return;
2871 }
b61f2753
AJ		 2872 EA = tcg_temp_new(TCG_TYPE_TL);
2873 gen_addr_imm_index(EA, ctx, 0x03);
2874 gen_qemu_st64(cpu_gpr[rs], EA, ctx->mem_idx);
2875 tcg_gen_addi_tl(EA, EA, 8);
2876 gen_qemu_st64(cpu_gpr[rs+1], EA, ctx->mem_idx);
2877 tcg_temp_free(EA);
be147d08
JM		 2878#endif
2879 } else {
2880 /* std / stdu */
2881 if (Rc(ctx->opcode)) {
2882 if (unlikely(rA(ctx->opcode) == 0)) {
2883 GEN_EXCP_INVAL(ctx);
2884 return;
2885 }
2886 }
b61f2753
AJ		 2887 EA = tcg_temp_new(TCG_TYPE_TL);
2888 gen_addr_imm_index(EA, ctx, 0x03);
2889 gen_qemu_st64(cpu_gpr[rs], EA, ctx->mem_idx);
be147d08 2890 if (Rc(ctx->opcode))
b61f2753
AJ		 2891 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2892 tcg_temp_free(EA);
d9bce9d9 2893 }
d9bce9d9
JM		 2894}
2895#endif
79aceca5
FB		 2896/*** Integer load and store with byte reverse ***/
2897/* lhbrx */
b61f2753
AJ		 2898void always_inline gen_qemu_ld16ur(TCGv t0, TCGv t1, int flags)
2899{
2900 TCGv temp = tcg_temp_new(TCG_TYPE_I32);
2901 gen_qemu_ld16u(temp, t1, flags);
2902 tcg_gen_bswap16_i32(temp, temp);
2903 tcg_gen_extu_i32_tl(t0, temp);
2904 tcg_temp_free(temp);
2905}
2906GEN_LDX(16ur, 0x16, 0x18, PPC_INTEGER);
2907
79aceca5 2908/* lwbrx */
b61f2753
AJ		 2909void always_inline gen_qemu_ld32ur(TCGv t0, TCGv t1, int flags)
2910{
2911 TCGv temp = tcg_temp_new(TCG_TYPE_I32);
2912 gen_qemu_ld32u(temp, t1, flags);
2913 tcg_gen_bswap_i32(temp, temp);
2914 tcg_gen_extu_i32_tl(t0, temp);
2915 tcg_temp_free(temp);
2916}
2917GEN_LDX(32ur, 0x16, 0x10, PPC_INTEGER);
2918
79aceca5 2919/* sthbrx */
b61f2753
AJ		 2920void always_inline gen_qemu_st16r(TCGv t0, TCGv t1, int flags)
2921{
2922 TCGv temp = tcg_temp_new(TCG_TYPE_I32);
2923 tcg_gen_trunc_tl_i32(temp, t0);
2924 tcg_gen_ext16u_i32(temp, temp);
2925 tcg_gen_bswap16_i32(temp, temp);
2926 gen_qemu_st16(temp, t1, flags);
2927 tcg_temp_free(temp);
2928}
2929GEN_STX(16r, 0x16, 0x1C, PPC_INTEGER);
2930
79aceca5 2931/* stwbrx */
b61f2753
AJ		 2932void always_inline gen_qemu_st32r(TCGv t0, TCGv t1, int flags)
2933{
2934 TCGv temp = tcg_temp_new(TCG_TYPE_I32);
2935 tcg_gen_trunc_tl_i32(temp, t0);
2936 tcg_gen_bswap_i32(temp, temp);
2937 gen_qemu_st32(temp, t1, flags);
2938 tcg_temp_free(temp);
2939}
2940GEN_STX(32r, 0x16, 0x14, PPC_INTEGER);
79aceca5
FB		 2941
2942/*** Integer load and store multiple ***/
111bfab3 2943#define op_ldstm(name, reg) (*gen_op_##name[ctx->mem_idx])(reg)
7863667f
JM		 2944static GenOpFunc1 *gen_op_lmw[NB_MEM_FUNCS] = {
2945 GEN_MEM_FUNCS(lmw),
d9bce9d9 2946};
7863667f
JM		 2947static GenOpFunc1 *gen_op_stmw[NB_MEM_FUNCS] = {
2948 GEN_MEM_FUNCS(stmw),
d9bce9d9 2949};
9a64fbe4 2950
79aceca5
FB		 2951/* lmw */
2952GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
2953{
76a66253 2954 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 2955 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 2956 gen_addr_imm_index(cpu_T[0], ctx, 0);
9a64fbe4 2957 op_ldstm(lmw, rD(ctx->opcode));
79aceca5
FB		 2958}
2959
2960/* stmw */
2961GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
2962{
76a66253 2963 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 2964 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 2965 gen_addr_imm_index(cpu_T[0], ctx, 0);
9a64fbe4 2966 op_ldstm(stmw, rS(ctx->opcode));
79aceca5
FB		 2967}
2968
2969/*** Integer load and store strings ***/
9a64fbe4
FB		 2970#define op_ldsts(name, start) (*gen_op_##name[ctx->mem_idx])(start)
2971#define op_ldstsx(name, rd, ra, rb) (*gen_op_##name[ctx->mem_idx])(rd, ra, rb)
e7c24003
JM		 2972/* string load & stores are by definition endian-safe */
2973#define gen_op_lswi_le_raw gen_op_lswi_raw
2974#define gen_op_lswi_le_user gen_op_lswi_user
2975#define gen_op_lswi_le_kernel gen_op_lswi_kernel
2976#define gen_op_lswi_le_hypv gen_op_lswi_hypv
2977#define gen_op_lswi_le_64_raw gen_op_lswi_raw
2978#define gen_op_lswi_le_64_user gen_op_lswi_user
2979#define gen_op_lswi_le_64_kernel gen_op_lswi_kernel
2980#define gen_op_lswi_le_64_hypv gen_op_lswi_hypv
7863667f
JM		 2981static GenOpFunc1 *gen_op_lswi[NB_MEM_FUNCS] = {
2982 GEN_MEM_FUNCS(lswi),
d9bce9d9 2983};
e7c24003
JM		 2984#define gen_op_lswx_le_raw gen_op_lswx_raw
2985#define gen_op_lswx_le_user gen_op_lswx_user
2986#define gen_op_lswx_le_kernel gen_op_lswx_kernel
2987#define gen_op_lswx_le_hypv gen_op_lswx_hypv
2988#define gen_op_lswx_le_64_raw gen_op_lswx_raw
2989#define gen_op_lswx_le_64_user gen_op_lswx_user
2990#define gen_op_lswx_le_64_kernel gen_op_lswx_kernel
2991#define gen_op_lswx_le_64_hypv gen_op_lswx_hypv
7863667f
JM		 2992static GenOpFunc3 *gen_op_lswx[NB_MEM_FUNCS] = {
2993 GEN_MEM_FUNCS(lswx),
d9bce9d9 2994};
e7c24003
JM		 2995#define gen_op_stsw_le_raw gen_op_stsw_raw
2996#define gen_op_stsw_le_user gen_op_stsw_user
2997#define gen_op_stsw_le_kernel gen_op_stsw_kernel
2998#define gen_op_stsw_le_hypv gen_op_stsw_hypv
2999#define gen_op_stsw_le_64_raw gen_op_stsw_raw
3000#define gen_op_stsw_le_64_user gen_op_stsw_user
3001#define gen_op_stsw_le_64_kernel gen_op_stsw_kernel
3002#define gen_op_stsw_le_64_hypv gen_op_stsw_hypv
7863667f
JM		 3003static GenOpFunc1 *gen_op_stsw[NB_MEM_FUNCS] = {
3004 GEN_MEM_FUNCS(stsw),
9a64fbe4 3005};
9a64fbe4 3006
79aceca5 3007/* lswi */
3fc6c082 3008/* PowerPC32 specification says we must generate an exception if
9a64fbe4
FB		 3009 * rA is in the range of registers to be loaded.
3010 * In an other hand, IBM says this is valid, but rA won't be loaded.
3011 * For now, I'll follow the spec...
3012 */
05332d70 3013GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING)
79aceca5
FB		 3014{
3015 int nb = NB(ctx->opcode);
3016 int start = rD(ctx->opcode);
9a64fbe4 3017 int ra = rA(ctx->opcode);
79aceca5
FB		 3018 int nr;
3019
3020 if (nb == 0)
3021 nb = 32;
3022 nr = nb / 4;
76a66253
JM		 3023 if (unlikely(((start + nr) > 32 &&
3024 start <= ra && (start + nr - 32) > ra) ||
3025 ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
e1833e1f
JM		 3026 GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,
3027 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_LSWX);
9fddaa0c 3028 return;
297d8e62 3029 }
8dd4983c 3030 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3031 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 3032 gen_addr_register(cpu_T[0], ctx);
86c581dc 3033 tcg_gen_movi_tl(cpu_T[1], nb);
9a64fbe4 3034 op_ldsts(lswi, start);
79aceca5
FB		 3035}
3036
3037/* lswx */
05332d70 3038GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING)
79aceca5 3039{
9a64fbe4
FB		 3040 int ra = rA(ctx->opcode);
3041 int rb = rB(ctx->opcode);
3042
76a66253 3043 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3044 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 3045 gen_addr_reg_index(cpu_T[0], ctx);
9a64fbe4 3046 if (ra == 0) {
9a64fbe4 3047 ra = rb;
79aceca5 3048 }
3d7b417e 3049 tcg_gen_andi_tl(cpu_T[1], cpu_xer, 0x7F);
9a64fbe4 3050 op_ldstsx(lswx, rD(ctx->opcode), ra, rb);
79aceca5
FB		 3051}
3052
3053/* stswi */
05332d70 3054GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING)
79aceca5 3055{
4b3686fa
FB		 3056 int nb = NB(ctx->opcode);
3057
76a66253 3058 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3059 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 3060 gen_addr_register(cpu_T[0], ctx);
4b3686fa
FB		 3061 if (nb == 0)
3062 nb = 32;
86c581dc 3063 tcg_gen_movi_tl(cpu_T[1], nb);
9a64fbe4 3064 op_ldsts(stsw, rS(ctx->opcode));
79aceca5
FB		 3065}
3066
3067/* stswx */
05332d70 3068GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING)
79aceca5 3069{
8dd4983c 3070 /* NIP cannot be restored if the memory exception comes from an helper */
5fafdf24 3071 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 3072 gen_addr_reg_index(cpu_T[0], ctx);
3d7b417e 3073 tcg_gen_andi_tl(cpu_T[1], cpu_xer, 0x7F);
9a64fbe4 3074 op_ldsts(stsw, rS(ctx->opcode));
79aceca5
FB		 3075}
3076
3077/*** Memory synchronisation ***/
3078/* eieio */
0db1b20e 3079GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO)
79aceca5 3080{
79aceca5
FB		 3081}
3082
3083/* isync */
0db1b20e 3084GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM)
79aceca5 3085{
e1833e1f 3086 GEN_STOP(ctx);
79aceca5
FB		 3087}
3088
111bfab3
FB		 3089#define op_lwarx() (*gen_op_lwarx[ctx->mem_idx])()
3090#define op_stwcx() (*gen_op_stwcx[ctx->mem_idx])()
7863667f
JM		 3091static GenOpFunc *gen_op_lwarx[NB_MEM_FUNCS] = {
3092 GEN_MEM_FUNCS(lwarx),
111bfab3 3093};
7863667f
JM		 3094static GenOpFunc *gen_op_stwcx[NB_MEM_FUNCS] = {
3095 GEN_MEM_FUNCS(stwcx),
985a19d6 3096};
9a64fbe4 3097
111bfab3 3098/* lwarx */
76a66253 3099GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000001, PPC_RES)
79aceca5 3100{
30032c94
JM		 3101 /* NIP cannot be restored if the memory exception comes from an helper */
3102 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 3103 gen_addr_reg_index(cpu_T[0], ctx);
985a19d6 3104 op_lwarx();
f78fb44e 3105 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[1]);
79aceca5
FB		 3106}
3107
3108/* stwcx. */
c7697e1f 3109GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES)
79aceca5 3110{
30032c94
JM		 3111 /* NIP cannot be restored if the memory exception comes from an helper */
3112 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 3113 gen_addr_reg_index(cpu_T[0], ctx);
f78fb44e 3114 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
9a64fbe4 3115 op_stwcx();
79aceca5
FB		 3116}
3117
426613db
JM		 3118#if defined(TARGET_PPC64)
3119#define op_ldarx() (*gen_op_ldarx[ctx->mem_idx])()
3120#define op_stdcx() (*gen_op_stdcx[ctx->mem_idx])()
7863667f
JM		 3121static GenOpFunc *gen_op_ldarx[NB_MEM_FUNCS] = {
3122 GEN_MEM_FUNCS(ldarx),
426613db 3123};
7863667f
JM		 3124static GenOpFunc *gen_op_stdcx[NB_MEM_FUNCS] = {
3125 GEN_MEM_FUNCS(stdcx),
426613db 3126};
426613db
JM		 3127
3128/* ldarx */
a750fc0b 3129GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000001, PPC_64B)
426613db 3130{
30032c94
JM		 3131 /* NIP cannot be restored if the memory exception comes from an helper */
3132 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 3133 gen_addr_reg_index(cpu_T[0], ctx);
426613db 3134 op_ldarx();
f78fb44e 3135 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[1]);
426613db
JM		 3136}
3137
3138/* stdcx. */
c7697e1f 3139GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B)
426613db 3140{
30032c94
JM		 3141 /* NIP cannot be restored if the memory exception comes from an helper */
3142 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 3143 gen_addr_reg_index(cpu_T[0], ctx);
f78fb44e 3144 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
426613db
JM		 3145 op_stdcx();
3146}
3147#endif /* defined(TARGET_PPC64) */
3148
79aceca5 3149/* sync */
a902d886 3150GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC)
79aceca5 3151{
79aceca5
FB		 3152}
3153
0db1b20e
JM		 3154/* wait */
3155GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT)
3156{
3157 /* Stop translation, as the CPU is supposed to sleep from now */
be147d08
JM		 3158 gen_op_wait();
3159 GEN_EXCP(ctx, EXCP_HLT, 1);
0db1b20e
JM		 3160}
3161
79aceca5 3162/*** Floating-point load ***/
477023a6
JM		 3163#define GEN_LDF(width, opc, type) \
3164GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 3165{ \
76a66253 3166 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 3167 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 3168 return; \
3169 } \
e2be8d8d 3170 gen_addr_imm_index(cpu_T[0], ctx, 0); \
9a64fbe4 3171 op_ldst(l##width); \
a5e26afa 3172 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
79aceca5
FB		 3173}
3174
477023a6
JM		 3175#define GEN_LDUF(width, opc, type) \
3176GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 3177{ \
76a66253 3178 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 3179 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 3180 return; \
3181 } \
76a66253 3182 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 3183 GEN_EXCP_INVAL(ctx); \
9fddaa0c 3184 return; \
9a64fbe4 3185 } \
e2be8d8d 3186 gen_addr_imm_index(cpu_T[0], ctx, 0); \
9a64fbe4 3187 op_ldst(l##width); \
a5e26afa 3188 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
f78fb44e 3189 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \
79aceca5
FB		 3190}
3191
477023a6
JM		 3192#define GEN_LDUXF(width, opc, type) \
3193GEN_HANDLER(l##width##ux, 0x1F, 0x17, opc, 0x00000001, type) \
79aceca5 3194{ \
76a66253 3195 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 3196 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 3197 return; \
3198 } \
76a66253 3199 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 3200 GEN_EXCP_INVAL(ctx); \
9fddaa0c 3201 return; \
9a64fbe4 3202 } \
e2be8d8d 3203 gen_addr_reg_index(cpu_T[0], ctx); \
9a64fbe4 3204 op_ldst(l##width); \
a5e26afa 3205 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
f78fb44e 3206 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \
79aceca5
FB		 3207}
3208
477023a6
JM		 3209#define GEN_LDXF(width, opc2, opc3, type) \
3210GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 3211{ \
76a66253 3212 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 3213 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 3214 return; \
3215 } \
e2be8d8d 3216 gen_addr_reg_index(cpu_T[0], ctx); \
9a64fbe4 3217 op_ldst(l##width); \
a5e26afa 3218 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
79aceca5
FB		 3219}
3220
477023a6 3221#define GEN_LDFS(width, op, type) \
9a64fbe4 3222OP_LD_TABLE(width); \
477023a6
JM		 3223GEN_LDF(width, op | 0x20, type); \
3224GEN_LDUF(width, op | 0x21, type); \
3225GEN_LDUXF(width, op | 0x01, type); \
3226GEN_LDXF(width, 0x17, op | 0x00, type)
79aceca5
FB		 3227
3228/* lfd lfdu lfdux lfdx */
477023a6 3229GEN_LDFS(fd, 0x12, PPC_FLOAT);
79aceca5 3230/* lfs lfsu lfsux lfsx */
477023a6 3231GEN_LDFS(fs, 0x10, PPC_FLOAT);
79aceca5
FB		 3232
3233/*** Floating-point store ***/
477023a6
JM		 3234#define GEN_STF(width, opc, type) \
3235GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 3236{ \
76a66253 3237 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 3238 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 3239 return; \
3240 } \
e2be8d8d 3241 gen_addr_imm_index(cpu_T[0], ctx, 0); \
a5e26afa 3242 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); \
9a64fbe4 3243 op_ldst(st##width); \
79aceca5
FB		 3244}
3245
477023a6
JM		 3246#define GEN_STUF(width, opc, type) \
3247GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 3248{ \
76a66253 3249 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 3250 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 3251 return; \
3252 } \
76a66253 3253 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 3254 GEN_EXCP_INVAL(ctx); \
9fddaa0c 3255 return; \
9a64fbe4 3256 } \
e2be8d8d 3257 gen_addr_imm_index(cpu_T[0], ctx, 0); \
a5e26afa 3258 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); \
9a64fbe4 3259 op_ldst(st##width); \
f78fb44e 3260 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \
79aceca5
FB		 3261}
3262
477023a6
JM		 3263#define GEN_STUXF(width, opc, type) \
3264GEN_HANDLER(st##width##ux, 0x1F, 0x17, opc, 0x00000001, type) \
79aceca5 3265{ \
76a66253 3266 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 3267 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 3268 return; \
3269 } \
76a66253 3270 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 3271 GEN_EXCP_INVAL(ctx); \
9fddaa0c 3272 return; \
9a64fbe4 3273 } \
e2be8d8d 3274 gen_addr_reg_index(cpu_T[0], ctx); \
a5e26afa 3275 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); \
9a64fbe4 3276 op_ldst(st##width); \
f78fb44e 3277 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \
79aceca5
FB		 3278}
3279
477023a6
JM		 3280#define GEN_STXF(width, opc2, opc3, type) \
3281GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 3282{ \
76a66253 3283 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 3284 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 3285 return; \
3286 } \
e2be8d8d 3287 gen_addr_reg_index(cpu_T[0], ctx); \
a5e26afa 3288 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); \
9a64fbe4 3289 op_ldst(st##width); \
79aceca5
FB		 3290}
3291
477023a6 3292#define GEN_STFS(width, op, type) \
9a64fbe4 3293OP_ST_TABLE(width); \
477023a6
JM		 3294GEN_STF(width, op | 0x20, type); \
3295GEN_STUF(width, op | 0x21, type); \
3296GEN_STUXF(width, op | 0x01, type); \
3297GEN_STXF(width, 0x17, op | 0x00, type)
79aceca5
FB		 3298
3299/* stfd stfdu stfdux stfdx */
477023a6 3300GEN_STFS(fd, 0x16, PPC_FLOAT);
79aceca5 3301/* stfs stfsu stfsux stfsx */
477023a6 3302GEN_STFS(fs, 0x14, PPC_FLOAT);
79aceca5
FB		 3303
3304/* Optional: */
3305/* stfiwx */
5b8105fa
JM		 3306OP_ST_TABLE(fiw);
3307GEN_STXF(fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
79aceca5
FB		 3308
3309/*** Branch ***/
b068d6a7
JM		 3310static always_inline void gen_goto_tb (DisasContext *ctx, int n,
3311 target_ulong dest)
c1942362
FB		 3312{
3313 TranslationBlock *tb;
3314 tb = ctx->tb;
a2ffb812
AJ		 3315#if defined(TARGET_PPC64)
3316 if (!ctx->sf_mode)
3317 dest = (uint32_t) dest;
3318#endif
57fec1fe 3319 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
8cbcb4fa 3320 likely(!ctx->singlestep_enabled)) {
57fec1fe 3321 tcg_gen_goto_tb(n);
a2ffb812 3322 tcg_gen_movi_tl(cpu_nip, dest & ~3);
57fec1fe 3323 tcg_gen_exit_tb((long)tb + n);
c1942362 3324 } else {
a2ffb812 3325 tcg_gen_movi_tl(cpu_nip, dest & ~3);
8cbcb4fa
AJ		 3326 if (unlikely(ctx->singlestep_enabled)) {
3327 if ((ctx->singlestep_enabled &
3328 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
3329 ctx->exception == POWERPC_EXCP_BRANCH) {
3330 target_ulong tmp = ctx->nip;
3331 ctx->nip = dest;
3332 GEN_EXCP(ctx, POWERPC_EXCP_TRACE, 0);
3333 ctx->nip = tmp;
3334 }
3335 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
3336 gen_update_nip(ctx, dest);
3337 gen_op_debug();
3338 }
3339 }
57fec1fe 3340 tcg_gen_exit_tb(0);
c1942362 3341 }
c53be334
FB		 3342}
3343
b068d6a7 3344static always_inline void gen_setlr (DisasContext *ctx, target_ulong nip)
e1833e1f
JM		 3345{
3346#if defined(TARGET_PPC64)
a2ffb812
AJ		 3347 if (ctx->sf_mode == 0)
3348 tcg_gen_movi_tl(cpu_lr, (uint32_t)nip);
e1833e1f
JM		 3349 else
3350#endif
a2ffb812 3351 tcg_gen_movi_tl(cpu_lr, nip);
e1833e1f
JM		 3352}
3353
79aceca5
FB		 3354/* b ba bl bla */
3355GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3356{
76a66253 3357 target_ulong li, target;
38a64f9d 3358
8cbcb4fa 3359 ctx->exception = POWERPC_EXCP_BRANCH;
38a64f9d 3360 /* sign extend LI */
76a66253 3361#if defined(TARGET_PPC64)
d9bce9d9
JM		 3362 if (ctx->sf_mode)
3363 li = ((int64_t)LI(ctx->opcode) << 38) >> 38;
3364 else
76a66253 3365#endif
d9bce9d9 3366 li = ((int32_t)LI(ctx->opcode) << 6) >> 6;
76a66253 3367 if (likely(AA(ctx->opcode) == 0))
046d6672 3368 target = ctx->nip + li - 4;
79aceca5 3369 else
9a64fbe4 3370 target = li;
e1833e1f
JM		 3371 if (LK(ctx->opcode))
3372 gen_setlr(ctx, ctx->nip);
c1942362 3373 gen_goto_tb(ctx, 0, target);
79aceca5
FB		 3374}
3375
e98a6e40
FB		 3376#define BCOND_IM 0
3377#define BCOND_LR 1
3378#define BCOND_CTR 2
3379
b068d6a7 3380static always_inline void gen_bcond (DisasContext *ctx, int type)
d9bce9d9 3381{
d9bce9d9 3382 uint32_t bo = BO(ctx->opcode);
a2ffb812
AJ		 3383 int l1 = gen_new_label();
3384 TCGv target;
e98a6e40 3385
8cbcb4fa 3386 ctx->exception = POWERPC_EXCP_BRANCH;
a2ffb812
AJ		 3387 if (type == BCOND_LR || type == BCOND_CTR) {
3388 target = tcg_temp_local_new(TCG_TYPE_TL);
3389 if (type == BCOND_CTR)
3390 tcg_gen_mov_tl(target, cpu_ctr);
3391 else
3392 tcg_gen_mov_tl(target, cpu_lr);
e98a6e40 3393 }
e1833e1f
JM		 3394 if (LK(ctx->opcode))
3395 gen_setlr(ctx, ctx->nip);
a2ffb812
AJ		 3396 l1 = gen_new_label();
3397 if ((bo & 0x4) == 0) {
3398 /* Decrement and test CTR */
3399 TCGv temp = tcg_temp_new(TCG_TYPE_TL);
3400 if (unlikely(type == BCOND_CTR)) {
3401 GEN_EXCP_INVAL(ctx);
3402 return;
3403 }
3404 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
d9bce9d9 3405#if defined(TARGET_PPC64)
a2ffb812
AJ		 3406 if (!ctx->sf_mode)
3407 tcg_gen_ext32u_tl(temp, cpu_ctr);
3408 else
d9bce9d9 3409#endif
a2ffb812
AJ		 3410 tcg_gen_mov_tl(temp, cpu_ctr);
3411 if (bo & 0x2) {
3412 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3413 } else {
3414 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
e98a6e40 3415 }
a2ffb812
AJ		 3416 }
3417 if ((bo & 0x10) == 0) {
3418 /* Test CR */
3419 uint32_t bi = BI(ctx->opcode);
3420 uint32_t mask = 1 << (3 - (bi & 0x03));
3421 TCGv temp = tcg_temp_new(TCG_TYPE_I32);
3422
d9bce9d9 3423 if (bo & 0x8) {
a2ffb812
AJ		 3424 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3425 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
d9bce9d9 3426 } else {
a2ffb812
AJ		 3427 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3428 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
d9bce9d9
JM		 3429 }
3430 }
e98a6e40 3431 if (type == BCOND_IM) {
a2ffb812
AJ		 3432
3433 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3434 if (likely(AA(ctx->opcode) == 0)) {
3435 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3436 } else {
3437 gen_goto_tb(ctx, 0, li);
3438 }
c53be334 3439 gen_set_label(l1);
c1942362 3440 gen_goto_tb(ctx, 1, ctx->nip);
e98a6e40 3441 } else {
d9bce9d9 3442#if defined(TARGET_PPC64)
a2ffb812
AJ		 3443 if (!(ctx->sf_mode))
3444 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3445 else
3446#endif
3447 tcg_gen_andi_tl(cpu_nip, target, ~3);
3448 tcg_gen_exit_tb(0);
3449 gen_set_label(l1);
3450#if defined(TARGET_PPC64)
3451 if (!(ctx->sf_mode))
3452 tcg_gen_movi_tl(cpu_nip, (uint32_t)ctx->nip);
d9bce9d9
JM		 3453 else
3454#endif
a2ffb812 3455 tcg_gen_movi_tl(cpu_nip, ctx->nip);
57fec1fe 3456 tcg_gen_exit_tb(0);
08e46e54 3457 }
e98a6e40
FB		 3458}
3459
3460GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3b46e624 3461{
e98a6e40
FB		 3462 gen_bcond(ctx, BCOND_IM);
3463}
3464
3465GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW)
3b46e624 3466{
e98a6e40
FB		 3467 gen_bcond(ctx, BCOND_CTR);
3468}
3469
3470GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW)
3b46e624 3471{
e98a6e40
FB		 3472 gen_bcond(ctx, BCOND_LR);
3473}
79aceca5
FB		 3474
3475/*** Condition register logical ***/
e1571908
AJ		 3476#define GEN_CRLOGIC(name, tcg_op, opc) \
3477GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) \
79aceca5 3478{ \
fc0d441e
JM		 3479 uint8_t bitmask; \
3480 int sh; \
e1571908 3481 TCGv temp1, temp2; \
fc0d441e 3482 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
e1571908 3483 temp1 = tcg_temp_new(TCG_TYPE_I32); \
fc0d441e 3484 if (sh > 0) \
e1571908 3485 tcg_gen_shri_i32(temp1, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
fc0d441e 3486 else if (sh < 0) \
e1571908
AJ		 3487 tcg_gen_shli_i32(temp1, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
3488 else \
2e31f5d3 3489 tcg_gen_mov_i32(temp1, cpu_crf[crbA(ctx->opcode) >> 2]); \
e1571908 3490 temp2 = tcg_temp_new(TCG_TYPE_I32); \
fc0d441e
JM		 3491 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3492 if (sh > 0) \
e1571908 3493 tcg_gen_shri_i32(temp2, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
fc0d441e 3494 else if (sh < 0) \
e1571908
AJ		 3495 tcg_gen_shli_i32(temp2, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
3496 else \
3497 tcg_gen_mov_i32(temp2, cpu_crf[crbB(ctx->opcode) >> 2]); \
3498 tcg_op(temp1, temp1, temp2); \
fc0d441e 3499 bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \
e1571908
AJ		 3500 tcg_gen_andi_i32(temp1, temp1, bitmask); \
3501 tcg_gen_andi_i32(temp2, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3502 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], temp1, temp2); \
3503 tcg_temp_free(temp1); \
3504 tcg_temp_free(temp2); \
79aceca5
FB		 3505}
3506
3507/* crand */
e1571908 3508GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
79aceca5 3509/* crandc */
e1571908 3510GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
79aceca5 3511/* creqv */
e1571908 3512GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
79aceca5 3513/* crnand */
e1571908 3514GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
79aceca5 3515/* crnor */
e1571908 3516GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
79aceca5 3517/* cror */
e1571908 3518GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
79aceca5 3519/* crorc */
e1571908 3520GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
79aceca5 3521/* crxor */
e1571908 3522GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
79aceca5
FB		 3523/* mcrf */
3524GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER)
3525{
47e4661c 3526 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
79aceca5
FB		 3527}
3528
3529/*** System linkage ***/
3530/* rfi (supervisor only) */
76a66253 3531GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW)
79aceca5 3532{
9a64fbe4 3533#if defined(CONFIG_USER_ONLY)
e1833e1f 3534 GEN_EXCP_PRIVOPC(ctx);
9a64fbe4
FB		 3535#else
3536 /* Restore CPU state */
76a66253 3537 if (unlikely(!ctx->supervisor)) {
e1833e1f 3538 GEN_EXCP_PRIVOPC(ctx);
9fddaa0c 3539 return;
9a64fbe4 3540 }
a42bd6cc 3541 gen_op_rfi();
e1833e1f 3542 GEN_SYNC(ctx);
9a64fbe4 3543#endif
79aceca5
FB		 3544}
3545
426613db 3546#if defined(TARGET_PPC64)
a750fc0b 3547GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B)
426613db
JM		 3548{
3549#if defined(CONFIG_USER_ONLY)
e1833e1f 3550 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 3551#else
3552 /* Restore CPU state */
3553 if (unlikely(!ctx->supervisor)) {
e1833e1f 3554 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 3555 return;
3556 }
a42bd6cc 3557 gen_op_rfid();
e1833e1f 3558 GEN_SYNC(ctx);
426613db
JM		 3559#endif
3560}
426613db 3561
5b8105fa 3562GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H)
be147d08
JM		 3563{
3564#if defined(CONFIG_USER_ONLY)
3565 GEN_EXCP_PRIVOPC(ctx);
3566#else
3567 /* Restore CPU state */
3568 if (unlikely(ctx->supervisor <= 1)) {
3569 GEN_EXCP_PRIVOPC(ctx);
3570 return;
3571 }
3572 gen_op_hrfid();
3573 GEN_SYNC(ctx);
3574#endif
3575}
3576#endif
3577
79aceca5 3578/* sc */
417bf010
JM		 3579#if defined(CONFIG_USER_ONLY)
3580#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3581#else
3582#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3583#endif
e1833e1f 3584GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW)
79aceca5 3585{
e1833e1f
JM		 3586 uint32_t lev;
3587
3588 lev = (ctx->opcode >> 5) & 0x7F;
417bf010 3589 GEN_EXCP(ctx, POWERPC_SYSCALL, lev);
79aceca5
FB		 3590}
3591
3592/*** Trap ***/
3593/* tw */
76a66253 3594GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW)
79aceca5 3595{
f78fb44e
AJ		 3596 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
3597 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
a0ae05aa 3598 /* Update the nip since this might generate a trap exception */
d9bce9d9 3599 gen_update_nip(ctx, ctx->nip);
9a64fbe4 3600 gen_op_tw(TO(ctx->opcode));
79aceca5
FB		 3601}
3602
3603/* twi */
3604GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3605{
f78fb44e 3606 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
02f4f6c2 3607 tcg_gen_movi_tl(cpu_T[1], SIMM(ctx->opcode));
d9bce9d9
JM		 3608 /* Update the nip since this might generate a trap exception */
3609 gen_update_nip(ctx, ctx->nip);
76a66253 3610 gen_op_tw(TO(ctx->opcode));
79aceca5
FB		 3611}
3612
d9bce9d9
JM		 3613#if defined(TARGET_PPC64)
3614/* td */
3615GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B)
3616{
f78fb44e
AJ		 3617 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
3618 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
d9bce9d9
JM		 3619 /* Update the nip since this might generate a trap exception */
3620 gen_update_nip(ctx, ctx->nip);
3621 gen_op_td(TO(ctx->opcode));
3622}
3623
3624/* tdi */
3625GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B)
3626{
f78fb44e 3627 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
02f4f6c2 3628 tcg_gen_movi_tl(cpu_T[1], SIMM(ctx->opcode));
d9bce9d9
JM		 3629 /* Update the nip since this might generate a trap exception */
3630 gen_update_nip(ctx, ctx->nip);
3631 gen_op_td(TO(ctx->opcode));
3632}
3633#endif
3634
79aceca5 3635/*** Processor control ***/
79aceca5
FB		 3636/* mcrxr */
3637GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC)
3638{
3d7b417e
AJ		 3639 tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], cpu_xer);
3640 tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], XER_CA);
269f3e95 3641 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_SO | 1 << XER_OV | 1 << XER_CA));
79aceca5
FB		 3642}
3643
3644/* mfcr */
76a66253 3645GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC)
79aceca5 3646{
76a66253 3647 uint32_t crm, crn;
3b46e624 3648
76a66253
JM		 3649 if (likely(ctx->opcode & 0x00100000)) {
3650 crm = CRM(ctx->opcode);
3651 if (likely((crm ^ (crm - 1)) == 0)) {
3652 crn = ffs(crm);
e1571908 3653 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
76a66253 3654 }
d9bce9d9 3655 } else {
e1571908 3656 tcg_gen_helper_1_0(helper_load_cr, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 3657 }
79aceca5
FB		 3658}
3659
3660/* mfmsr */
3661GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC)
3662{
9a64fbe4 3663#if defined(CONFIG_USER_ONLY)
e1833e1f 3664 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 3665#else
76a66253 3666 if (unlikely(!ctx->supervisor)) {
e1833e1f 3667 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 3668 return;
9a64fbe4 3669 }
6676f424 3670 gen_op_load_msr();
f78fb44e 3671 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
9a64fbe4 3672#endif
79aceca5
FB		 3673}
3674
a11b8151 3675#if 1
6f2d8978 3676#define SPR_NOACCESS ((void *)(-1UL))
3fc6c082
FB		 3677#else
3678static void spr_noaccess (void *opaque, int sprn)
3679{
3680 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
3681 printf("ERROR: try to access SPR %d !\n", sprn);
3682}
3683#define SPR_NOACCESS (&spr_noaccess)
3684#endif
3685
79aceca5 3686/* mfspr */
b068d6a7 3687static always_inline void gen_op_mfspr (DisasContext *ctx)
79aceca5 3688{
3fc6c082 3689 void (*read_cb)(void *opaque, int sprn);
79aceca5
FB		 3690 uint32_t sprn = SPR(ctx->opcode);
3691
3fc6c082 3692#if !defined(CONFIG_USER_ONLY)
be147d08
JM		 3693 if (ctx->supervisor == 2)
3694 read_cb = ctx->spr_cb[sprn].hea_read;
7863667f 3695 else if (ctx->supervisor)
3fc6c082
FB		 3696 read_cb = ctx->spr_cb[sprn].oea_read;
3697 else
9a64fbe4 3698#endif
3fc6c082 3699 read_cb = ctx->spr_cb[sprn].uea_read;
76a66253
JM		 3700 if (likely(read_cb != NULL)) {
3701 if (likely(read_cb != SPR_NOACCESS)) {
3fc6c082 3702 (*read_cb)(ctx, sprn);
f78fb44e 3703 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
3fc6c082
FB		 3704 } else {
3705 /* Privilege exception */
9fceefa7
JM		 3706 /* This is a hack to avoid warnings when running Linux:
3707 * this OS breaks the PowerPC virtualisation model,
3708 * allowing userland application to read the PVR
3709 */
3710 if (sprn != SPR_PVR) {
3711 if (loglevel != 0) {
6b542af7 3712 fprintf(logfile, "Trying to read privileged spr %d %03x at "
077fc206 3713 ADDRX "\n", sprn, sprn, ctx->nip);
9fceefa7 3714 }
077fc206
JM		 3715 printf("Trying to read privileged spr %d %03x at " ADDRX "\n",
3716 sprn, sprn, ctx->nip);
f24e5695 3717 }
e1833e1f 3718 GEN_EXCP_PRIVREG(ctx);
79aceca5 3719 }
3fc6c082
FB		 3720 } else {
3721 /* Not defined */
4a057712 3722 if (loglevel != 0) {
077fc206
JM		 3723 fprintf(logfile, "Trying to read invalid spr %d %03x at "
3724 ADDRX "\n", sprn, sprn, ctx->nip);
f24e5695 3725 }
077fc206
JM		 3726 printf("Trying to read invalid spr %d %03x at " ADDRX "\n",
3727 sprn, sprn, ctx->nip);
e1833e1f
JM		 3728 GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,
3729 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_SPR);
79aceca5 3730 }
79aceca5
FB		 3731}
3732
3fc6c082 3733GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC)
79aceca5 3734{
3fc6c082 3735 gen_op_mfspr(ctx);
76a66253 3736}
3fc6c082
FB		 3737
3738/* mftb */
a750fc0b 3739GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB)
3fc6c082
FB		 3740{
3741 gen_op_mfspr(ctx);
79aceca5
FB		 3742}
3743
3744/* mtcrf */
8dd4983c 3745GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC)
79aceca5 3746{
76a66253 3747 uint32_t crm, crn;
3b46e624 3748
76a66253
JM		 3749 crm = CRM(ctx->opcode);
3750 if (likely((ctx->opcode & 0x00100000) || (crm ^ (crm - 1)) == 0)) {
3751 crn = ffs(crm);
e1571908
AJ		 3752 tcg_gen_shri_i32(cpu_crf[7 - crn], cpu_gpr[rS(ctx->opcode)], crn * 4);
3753 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
76a66253 3754 } else {
e1571908
AJ		 3755 TCGv temp = tcg_const_tl(crm);
3756 tcg_gen_helper_0_2(helper_store_cr, cpu_gpr[rS(ctx->opcode)], temp);
3757 tcg_temp_free(temp);
76a66253 3758 }
79aceca5
FB		 3759}
3760
3761/* mtmsr */
426613db 3762#if defined(TARGET_PPC64)
be147d08 3763GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B)
426613db
JM		 3764{
3765#if defined(CONFIG_USER_ONLY)
e1833e1f 3766 GEN_EXCP_PRIVREG(ctx);
426613db
JM		 3767#else
3768 if (unlikely(!ctx->supervisor)) {
e1833e1f 3769 GEN_EXCP_PRIVREG(ctx);
426613db
JM		 3770 return;
3771 }
f78fb44e 3772 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
be147d08
JM		 3773 if (ctx->opcode & 0x00010000) {
3774 /* Special form that does not need any synchronisation */
3775 gen_op_update_riee();
3776 } else {
056b05f8
JM		 3777 /* XXX: we need to update nip before the store
3778 * if we enter power saving mode, we will exit the loop
3779 * directly from ppc_store_msr
3780 */
be147d08 3781 gen_update_nip(ctx, ctx->nip);
6676f424 3782 gen_op_store_msr();
be147d08
JM		 3783 /* Must stop the translation as machine state (may have) changed */
3784 /* Note that mtmsr is not always defined as context-synchronizing */
056b05f8 3785 ctx->exception = POWERPC_EXCP_STOP;
be147d08 3786 }
426613db
JM		 3787#endif
3788}
3789#endif
3790
79aceca5
FB		 3791GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC)
3792{
9a64fbe4 3793#if defined(CONFIG_USER_ONLY)
e1833e1f 3794 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 3795#else
76a66253 3796 if (unlikely(!ctx->supervisor)) {
e1833e1f 3797 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 3798 return;
9a64fbe4 3799 }
f78fb44e 3800 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
be147d08
JM		 3801 if (ctx->opcode & 0x00010000) {
3802 /* Special form that does not need any synchronisation */
3803 gen_op_update_riee();
3804 } else {
056b05f8
JM		 3805 /* XXX: we need to update nip before the store
3806 * if we enter power saving mode, we will exit the loop
3807 * directly from ppc_store_msr
3808 */
be147d08 3809 gen_update_nip(ctx, ctx->nip);
d9bce9d9 3810#if defined(TARGET_PPC64)
be147d08 3811 if (!ctx->sf_mode)
6676f424 3812 gen_op_store_msr_32();
be147d08 3813 else
d9bce9d9 3814#endif
6676f424 3815 gen_op_store_msr();
be147d08
JM		 3816 /* Must stop the translation as machine state (may have) changed */
3817 /* Note that mtmsrd is not always defined as context-synchronizing */
056b05f8 3818 ctx->exception = POWERPC_EXCP_STOP;
be147d08 3819 }
9a64fbe4 3820#endif
79aceca5
FB		 3821}
3822
3823/* mtspr */
3824GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC)
3825{
3fc6c082 3826 void (*write_cb)(void *opaque, int sprn);
79aceca5
FB		 3827 uint32_t sprn = SPR(ctx->opcode);
3828
3fc6c082 3829#if !defined(CONFIG_USER_ONLY)
be147d08
JM		 3830 if (ctx->supervisor == 2)
3831 write_cb = ctx->spr_cb[sprn].hea_write;
7863667f 3832 else if (ctx->supervisor)
3fc6c082
FB		 3833 write_cb = ctx->spr_cb[sprn].oea_write;
3834 else
9a64fbe4 3835#endif
3fc6c082 3836 write_cb = ctx->spr_cb[sprn].uea_write;
76a66253
JM		 3837 if (likely(write_cb != NULL)) {
3838 if (likely(write_cb != SPR_NOACCESS)) {
f78fb44e 3839 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
3fc6c082
FB		 3840 (*write_cb)(ctx, sprn);
3841 } else {
3842 /* Privilege exception */
4a057712 3843 if (loglevel != 0) {
077fc206
JM		 3844 fprintf(logfile, "Trying to write privileged spr %d %03x at "
3845 ADDRX "\n", sprn, sprn, ctx->nip);
f24e5695 3846 }
077fc206
JM		 3847 printf("Trying to write privileged spr %d %03x at " ADDRX "\n",
3848 sprn, sprn, ctx->nip);
e1833e1f 3849 GEN_EXCP_PRIVREG(ctx);
76a66253 3850 }
3fc6c082
FB		 3851 } else {
3852 /* Not defined */
4a057712 3853 if (loglevel != 0) {
077fc206
JM		 3854 fprintf(logfile, "Trying to write invalid spr %d %03x at "
3855 ADDRX "\n", sprn, sprn, ctx->nip);
f24e5695 3856 }
077fc206
JM		 3857 printf("Trying to write invalid spr %d %03x at " ADDRX "\n",
3858 sprn, sprn, ctx->nip);
e1833e1f
JM		 3859 GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,
3860 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_SPR);
79aceca5 3861 }
79aceca5
FB		 3862}
3863
3864/*** Cache management ***/
79aceca5 3865/* dcbf */
0db1b20e 3866GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE)
79aceca5 3867{
dac454af 3868 /* XXX: specification says this is treated as a load by the MMU */
b61f2753
AJ		 3869 TCGv temp = tcg_temp_new(TCG_TYPE_TL);
3870 gen_addr_reg_index(temp, ctx);
3871 gen_qemu_ld8u(temp, temp, ctx->mem_idx);
3872 tcg_temp_free(temp);
79aceca5
FB		 3873}
3874
3875/* dcbi (Supervisor only) */
9a64fbe4 3876GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE)
79aceca5 3877{
a541f297 3878#if defined(CONFIG_USER_ONLY)
e1833e1f 3879 GEN_EXCP_PRIVOPC(ctx);
a541f297 3880#else
b61f2753 3881 TCGv EA, val;
76a66253 3882 if (unlikely(!ctx->supervisor)) {
e1833e1f 3883 GEN_EXCP_PRIVOPC(ctx);
9fddaa0c 3884 return;
9a64fbe4 3885 }
b61f2753
AJ		 3886 EA = tcg_temp_new(TCG_TYPE_TL);
3887 gen_addr_reg_index(EA, ctx);
ed69522c 3888 val = tcg_temp_new(TCG_TYPE_TL);
76a66253 3889 /* XXX: specification says this should be treated as a store by the MMU */
b61f2753
AJ		 3890 gen_qemu_ld8u(val, EA, ctx->mem_idx);
3891 gen_qemu_st8(val, EA, ctx->mem_idx);
3892 tcg_temp_free(val);
3893 tcg_temp_free(EA);
a541f297 3894#endif
79aceca5
FB		 3895}
3896
3897/* dcdst */
9a64fbe4 3898GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE)
79aceca5 3899{
76a66253 3900 /* XXX: specification say this is treated as a load by the MMU */
b61f2753
AJ		 3901 TCGv temp = tcg_temp_new(TCG_TYPE_TL);
3902 gen_addr_reg_index(temp, ctx);
3903 gen_qemu_ld8u(temp, temp, ctx->mem_idx);
3904 tcg_temp_free(temp);
79aceca5
FB		 3905}
3906
3907/* dcbt */
0db1b20e 3908GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE)
79aceca5 3909{
0db1b20e 3910 /* interpreted as no-op */
76a66253
JM		 3911 /* XXX: specification say this is treated as a load by the MMU
3912 * but does not generate any exception
3913 */
79aceca5
FB		 3914}
3915
3916/* dcbtst */
0db1b20e 3917GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE)
79aceca5 3918{
0db1b20e 3919 /* interpreted as no-op */
76a66253
JM		 3920 /* XXX: specification say this is treated as a load by the MMU
3921 * but does not generate any exception
3922 */
79aceca5
FB		 3923}
3924
3925/* dcbz */
d63001d1 3926#define op_dcbz(n) (*gen_op_dcbz[n][ctx->mem_idx])()
7863667f
JM		 3927static GenOpFunc *gen_op_dcbz[4][NB_MEM_FUNCS] = {
3928 /* 32 bytes cache line size */
d63001d1 3929 {
7863667f
JM		 3930#define gen_op_dcbz_l32_le_raw gen_op_dcbz_l32_raw
3931#define gen_op_dcbz_l32_le_user gen_op_dcbz_l32_user
3932#define gen_op_dcbz_l32_le_kernel gen_op_dcbz_l32_kernel
3933#define gen_op_dcbz_l32_le_hypv gen_op_dcbz_l32_hypv
3934#define gen_op_dcbz_l32_le_64_raw gen_op_dcbz_l32_64_raw
3935#define gen_op_dcbz_l32_le_64_user gen_op_dcbz_l32_64_user
3936#define gen_op_dcbz_l32_le_64_kernel gen_op_dcbz_l32_64_kernel
3937#define gen_op_dcbz_l32_le_64_hypv gen_op_dcbz_l32_64_hypv
3938 GEN_MEM_FUNCS(dcbz_l32),
d63001d1 3939 },
7863667f 3940 /* 64 bytes cache line size */
d63001d1 3941 {
7863667f
JM		 3942#define gen_op_dcbz_l64_le_raw gen_op_dcbz_l64_raw
3943#define gen_op_dcbz_l64_le_user gen_op_dcbz_l64_user
3944#define gen_op_dcbz_l64_le_kernel gen_op_dcbz_l64_kernel
3945#define gen_op_dcbz_l64_le_hypv gen_op_dcbz_l64_hypv
3946#define gen_op_dcbz_l64_le_64_raw gen_op_dcbz_l64_64_raw
3947#define gen_op_dcbz_l64_le_64_user gen_op_dcbz_l64_64_user
3948#define gen_op_dcbz_l64_le_64_kernel gen_op_dcbz_l64_64_kernel
3949#define gen_op_dcbz_l64_le_64_hypv gen_op_dcbz_l64_64_hypv
3950 GEN_MEM_FUNCS(dcbz_l64),
d63001d1 3951 },
7863667f 3952 /* 128 bytes cache line size */
d63001d1 3953 {
7863667f
JM		 3954#define gen_op_dcbz_l128_le_raw gen_op_dcbz_l128_raw
3955#define gen_op_dcbz_l128_le_user gen_op_dcbz_l128_user
3956#define gen_op_dcbz_l128_le_kernel gen_op_dcbz_l128_kernel
3957#define gen_op_dcbz_l128_le_hypv gen_op_dcbz_l128_hypv
3958#define gen_op_dcbz_l128_le_64_raw gen_op_dcbz_l128_64_raw
3959#define gen_op_dcbz_l128_le_64_user gen_op_dcbz_l128_64_user
3960#define gen_op_dcbz_l128_le_64_kernel gen_op_dcbz_l128_64_kernel
3961#define gen_op_dcbz_l128_le_64_hypv gen_op_dcbz_l128_64_hypv
3962 GEN_MEM_FUNCS(dcbz_l128),
d63001d1 3963 },
7863667f 3964 /* tunable cache line size */
d63001d1 3965 {
7863667f
JM		 3966#define gen_op_dcbz_le_raw gen_op_dcbz_raw
3967#define gen_op_dcbz_le_user gen_op_dcbz_user
3968#define gen_op_dcbz_le_kernel gen_op_dcbz_kernel
3969#define gen_op_dcbz_le_hypv gen_op_dcbz_hypv
3970#define gen_op_dcbz_le_64_raw gen_op_dcbz_64_raw
3971#define gen_op_dcbz_le_64_user gen_op_dcbz_64_user
3972#define gen_op_dcbz_le_64_kernel gen_op_dcbz_64_kernel
3973#define gen_op_dcbz_le_64_hypv gen_op_dcbz_64_hypv
3974 GEN_MEM_FUNCS(dcbz),
d63001d1 3975 },
76a66253 3976};
9a64fbe4 3977
b068d6a7
JM		 3978static always_inline void handler_dcbz (DisasContext *ctx,
3979 int dcache_line_size)
d63001d1
JM		 3980{
3981 int n;
3982
3983 switch (dcache_line_size) {
3984 case 32:
3985 n = 0;
3986 break;
3987 case 64:
3988 n = 1;
3989 break;
3990 case 128:
3991 n = 2;
3992 break;
3993 default:
3994 n = 3;
3995 break;
3996 }
3997 op_dcbz(n);
3998}
3999
4000GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE_DCBZ)
79aceca5 4001{
e2be8d8d 4002 gen_addr_reg_index(cpu_T[0], ctx);
d63001d1
JM		 4003 handler_dcbz(ctx, ctx->dcache_line_size);
4004 gen_op_check_reservation();
4005}
4006
c7697e1f 4007GEN_HANDLER2(dcbz_970, "dcbz", 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZT)
d63001d1 4008{
e2be8d8d 4009 gen_addr_reg_index(cpu_T[0], ctx);
d63001d1
JM		 4010 if (ctx->opcode & 0x00200000)
4011 handler_dcbz(ctx, ctx->dcache_line_size);
4012 else
4013 handler_dcbz(ctx, -1);
4b3686fa 4014 gen_op_check_reservation();
79aceca5
FB		 4015}
4016
4017/* icbi */
36f69651 4018#define op_icbi() (*gen_op_icbi[ctx->mem_idx])()
7863667f
JM		 4019#define gen_op_icbi_le_raw gen_op_icbi_raw
4020#define gen_op_icbi_le_user gen_op_icbi_user
4021#define gen_op_icbi_le_kernel gen_op_icbi_kernel
4022#define gen_op_icbi_le_hypv gen_op_icbi_hypv
4023#define gen_op_icbi_le_64_raw gen_op_icbi_64_raw
4024#define gen_op_icbi_le_64_user gen_op_icbi_64_user
4025#define gen_op_icbi_le_64_kernel gen_op_icbi_64_kernel
4026#define gen_op_icbi_le_64_hypv gen_op_icbi_64_hypv
4027static GenOpFunc *gen_op_icbi[NB_MEM_FUNCS] = {
4028 GEN_MEM_FUNCS(icbi),
36f69651 4029};
e1833e1f 4030
1b413d55 4031GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI)
79aceca5 4032{
30032c94
JM		 4033 /* NIP cannot be restored if the memory exception comes from an helper */
4034 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 4035 gen_addr_reg_index(cpu_T[0], ctx);
36f69651 4036 op_icbi();
79aceca5
FB		 4037}
4038
4039/* Optional: */
4040/* dcba */
a750fc0b 4041GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA)
79aceca5 4042{
0db1b20e
JM		 4043 /* interpreted as no-op */
4044 /* XXX: specification say this is treated as a store by the MMU
4045 * but does not generate any exception
4046 */
79aceca5
FB		 4047}
4048
4049/*** Segment register manipulation ***/
4050/* Supervisor only: */
4051/* mfsr */
4052GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT)
4053{
9a64fbe4 4054#if defined(CONFIG_USER_ONLY)
e1833e1f 4055 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 4056#else
76a66253 4057 if (unlikely(!ctx->supervisor)) {
e1833e1f 4058 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 4059 return;
9a64fbe4 4060 }
86c581dc 4061 tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode));
76a66253 4062 gen_op_load_sr();
f78fb44e 4063 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
9a64fbe4 4064#endif
79aceca5
FB		 4065}
4066
4067/* mfsrin */
9a64fbe4 4068GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT)
79aceca5 4069{
9a64fbe4 4070#if defined(CONFIG_USER_ONLY)
e1833e1f 4071 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 4072#else
76a66253 4073 if (unlikely(!ctx->supervisor)) {
e1833e1f 4074 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 4075 return;
9a64fbe4 4076 }
f78fb44e 4077 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253
JM		 4078 gen_op_srli_T1(28);
4079 gen_op_load_sr();
f78fb44e 4080 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
9a64fbe4 4081#endif
79aceca5
FB		 4082}
4083
4084/* mtsr */
e63c59cb 4085GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT)
79aceca5 4086{
9a64fbe4 4087#if defined(CONFIG_USER_ONLY)
e1833e1f 4088 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 4089#else
76a66253 4090 if (unlikely(!ctx->supervisor)) {
e1833e1f 4091 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 4092 return;
9a64fbe4 4093 }
f78fb44e 4094 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
86c581dc 4095 tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode));
76a66253 4096 gen_op_store_sr();
9a64fbe4 4097#endif
79aceca5
FB		 4098}
4099
4100/* mtsrin */
9a64fbe4 4101GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT)
79aceca5 4102{
9a64fbe4 4103#if defined(CONFIG_USER_ONLY)
e1833e1f 4104 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 4105#else
76a66253 4106 if (unlikely(!ctx->supervisor)) {
e1833e1f 4107 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 4108 return;
9a64fbe4 4109 }
f78fb44e
AJ		 4110 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4111 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253
JM		 4112 gen_op_srli_T1(28);
4113 gen_op_store_sr();
9a64fbe4 4114#endif
79aceca5
FB		 4115}
4116
12de9a39
JM		 4117#if defined(TARGET_PPC64)
4118/* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4119/* mfsr */
c7697e1f 4120GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B)
12de9a39
JM		 4121{
4122#if defined(CONFIG_USER_ONLY)
4123 GEN_EXCP_PRIVREG(ctx);
4124#else
4125 if (unlikely(!ctx->supervisor)) {
4126 GEN_EXCP_PRIVREG(ctx);
4127 return;
4128 }
86c581dc 4129 tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode));
12de9a39 4130 gen_op_load_slb();
f78fb44e 4131 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
12de9a39
JM		 4132#endif
4133}
4134
4135/* mfsrin */
c7697e1f
JM		 4136GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
4137 PPC_SEGMENT_64B)
12de9a39
JM		 4138{
4139#if defined(CONFIG_USER_ONLY)
4140 GEN_EXCP_PRIVREG(ctx);
4141#else
4142 if (unlikely(!ctx->supervisor)) {
4143 GEN_EXCP_PRIVREG(ctx);
4144 return;
4145 }
f78fb44e 4146 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
12de9a39
JM		 4147 gen_op_srli_T1(28);
4148 gen_op_load_slb();
f78fb44e 4149 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
12de9a39
JM		 4150#endif
4151}
4152
4153/* mtsr */
c7697e1f 4154GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B)
12de9a39
JM		 4155{
4156#if defined(CONFIG_USER_ONLY)
4157 GEN_EXCP_PRIVREG(ctx);
4158#else
4159 if (unlikely(!ctx->supervisor)) {
4160 GEN_EXCP_PRIVREG(ctx);
4161 return;
4162 }
f78fb44e 4163 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
86c581dc 4164 tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode));
12de9a39
JM		 4165 gen_op_store_slb();
4166#endif
4167}
4168
4169/* mtsrin */
c7697e1f
JM		 4170GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
4171 PPC_SEGMENT_64B)
12de9a39
JM		 4172{
4173#if defined(CONFIG_USER_ONLY)
4174 GEN_EXCP_PRIVREG(ctx);
4175#else
4176 if (unlikely(!ctx->supervisor)) {
4177 GEN_EXCP_PRIVREG(ctx);
4178 return;
4179 }
f78fb44e
AJ		 4180 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4181 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
12de9a39
JM		 4182 gen_op_srli_T1(28);
4183 gen_op_store_slb();
4184#endif
4185}
4186#endif /* defined(TARGET_PPC64) */
4187
79aceca5
FB		 4188/*** Lookaside buffer management ***/
4189/* Optional & supervisor only: */
4190/* tlbia */
3fc6c082 4191GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA)
79aceca5 4192{
9a64fbe4 4193#if defined(CONFIG_USER_ONLY)
e1833e1f 4194 GEN_EXCP_PRIVOPC(ctx);
9a64fbe4 4195#else
76a66253 4196 if (unlikely(!ctx->supervisor)) {
e1833e1f 4197 GEN_EXCP_PRIVOPC(ctx);
9fddaa0c 4198 return;
9a64fbe4
FB		 4199 }
4200 gen_op_tlbia();
4201#endif
79aceca5
FB		 4202}
4203
4204/* tlbie */
76a66253 4205GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE)
79aceca5 4206{
9a64fbe4 4207#if defined(CONFIG_USER_ONLY)
e1833e1f 4208 GEN_EXCP_PRIVOPC(ctx);
9a64fbe4 4209#else
76a66253 4210 if (unlikely(!ctx->supervisor)) {
e1833e1f 4211 GEN_EXCP_PRIVOPC(ctx);
9fddaa0c 4212 return;
9a64fbe4 4213 }
f78fb44e 4214 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
d9bce9d9
JM		 4215#if defined(TARGET_PPC64)
4216 if (ctx->sf_mode)
4217 gen_op_tlbie_64();
4218 else
4219#endif
4220 gen_op_tlbie();
9a64fbe4 4221#endif
79aceca5
FB		 4222}
4223
4224/* tlbsync */
76a66253 4225GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC)
79aceca5 4226{
9a64fbe4 4227#if defined(CONFIG_USER_ONLY)
e1833e1f 4228 GEN_EXCP_PRIVOPC(ctx);
9a64fbe4 4229#else
76a66253 4230 if (unlikely(!ctx->supervisor)) {
e1833e1f 4231 GEN_EXCP_PRIVOPC(ctx);
9fddaa0c 4232 return;
9a64fbe4
FB		 4233 }
4234 /* This has no effect: it should ensure that all previous
4235 * tlbie have completed
4236 */
e1833e1f 4237 GEN_STOP(ctx);
9a64fbe4 4238#endif
79aceca5
FB		 4239}
4240
426613db
JM		 4241#if defined(TARGET_PPC64)
4242/* slbia */
4243GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI)
4244{
4245#if defined(CONFIG_USER_ONLY)
e1833e1f 4246 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 4247#else
4248 if (unlikely(!ctx->supervisor)) {
e1833e1f 4249 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 4250 return;
4251 }
4252 gen_op_slbia();
426613db
JM		 4253#endif
4254}
4255
4256/* slbie */
4257GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI)
4258{
4259#if defined(CONFIG_USER_ONLY)
e1833e1f 4260 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 4261#else
4262 if (unlikely(!ctx->supervisor)) {
e1833e1f 4263 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 4264 return;
4265 }
f78fb44e 4266 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
426613db 4267 gen_op_slbie();
426613db
JM		 4268#endif
4269}
4270#endif
4271
79aceca5
FB		 4272/*** External control ***/
4273/* Optional: */
9a64fbe4
FB		 4274#define op_eciwx() (*gen_op_eciwx[ctx->mem_idx])()
4275#define op_ecowx() (*gen_op_ecowx[ctx->mem_idx])()
7863667f
JM		 4276static GenOpFunc *gen_op_eciwx[NB_MEM_FUNCS] = {
4277 GEN_MEM_FUNCS(eciwx),
111bfab3 4278};
7863667f
JM		 4279static GenOpFunc *gen_op_ecowx[NB_MEM_FUNCS] = {
4280 GEN_MEM_FUNCS(ecowx),
111bfab3 4281};
9a64fbe4 4282
111bfab3 4283/* eciwx */
79aceca5
FB		 4284GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN)
4285{
9a64fbe4 4286 /* Should check EAR[E] & alignment ! */
e2be8d8d 4287 gen_addr_reg_index(cpu_T[0], ctx);
76a66253 4288 op_eciwx();
f78fb44e 4289 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4290}
4291
4292/* ecowx */
4293GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN)
4294{
4295 /* Should check EAR[E] & alignment ! */
e2be8d8d 4296 gen_addr_reg_index(cpu_T[0], ctx);
f78fb44e 4297 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
76a66253
JM		 4298 op_ecowx();
4299}
4300
4301/* PowerPC 601 specific instructions */
4302/* abs - abs. */
4303GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR)
4304{
f78fb44e 4305 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 4306 gen_op_POWER_abs();
f78fb44e 4307 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4308 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4309 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4310}
4311
4312/* abso - abso. */
4313GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR)
4314{
f78fb44e 4315 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 4316 gen_op_POWER_abso();
f78fb44e 4317 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4318 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4319 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4320}
4321
4322/* clcs */
a750fc0b 4323GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR)
76a66253 4324{
f78fb44e 4325 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 4326 gen_op_POWER_clcs();
c7697e1f 4327 /* Rc=1 sets CR0 to an undefined state */
f78fb44e 4328 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4329}
4330
4331/* div - div. */
4332GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR)
4333{
f78fb44e
AJ		 4334 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4335 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4336 gen_op_POWER_div();
f78fb44e 4337 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4338 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4339 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4340}
4341
4342/* divo - divo. */
4343GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR)
4344{
f78fb44e
AJ		 4345 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4346 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4347 gen_op_POWER_divo();
f78fb44e 4348 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4349 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4350 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4351}
4352
4353/* divs - divs. */
4354GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR)
4355{
f78fb44e
AJ		 4356 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4357 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4358 gen_op_POWER_divs();
f78fb44e 4359 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4360 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4361 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4362}
4363
4364/* divso - divso. */
4365GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR)
4366{
f78fb44e
AJ		 4367 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4368 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4369 gen_op_POWER_divso();
f78fb44e 4370 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4371 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4372 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4373}
4374
4375/* doz - doz. */
4376GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR)
4377{
f78fb44e
AJ		 4378 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4379 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4380 gen_op_POWER_doz();
f78fb44e 4381 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4382 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4383 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4384}
4385
4386/* dozo - dozo. */
4387GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR)
4388{
f78fb44e
AJ		 4389 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4390 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4391 gen_op_POWER_dozo();
f78fb44e 4392 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4393 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4394 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4395}
4396
4397/* dozi */
4398GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
4399{
f78fb44e 4400 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
86c581dc 4401 tcg_gen_movi_tl(cpu_T[1], SIMM(ctx->opcode));
76a66253 4402 gen_op_POWER_doz();
f78fb44e 4403 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4404}
4405
7863667f
JM		 4406/* As lscbx load from memory byte after byte, it's always endian safe.
4407 * Original POWER is 32 bits only, define 64 bits ops as 32 bits ones
4408 */
2857068e 4409#define op_POWER_lscbx(start, ra, rb) \
76a66253 4410(*gen_op_POWER_lscbx[ctx->mem_idx])(start, ra, rb)
7863667f
JM		 4411#define gen_op_POWER_lscbx_64_raw gen_op_POWER_lscbx_raw
4412#define gen_op_POWER_lscbx_64_user gen_op_POWER_lscbx_user
4413#define gen_op_POWER_lscbx_64_kernel gen_op_POWER_lscbx_kernel
4414#define gen_op_POWER_lscbx_64_hypv gen_op_POWER_lscbx_hypv
4415#define gen_op_POWER_lscbx_le_raw gen_op_POWER_lscbx_raw
4416#define gen_op_POWER_lscbx_le_user gen_op_POWER_lscbx_user
4417#define gen_op_POWER_lscbx_le_kernel gen_op_POWER_lscbx_kernel
4418#define gen_op_POWER_lscbx_le_hypv gen_op_POWER_lscbx_hypv
4419#define gen_op_POWER_lscbx_le_64_raw gen_op_POWER_lscbx_raw
4420#define gen_op_POWER_lscbx_le_64_user gen_op_POWER_lscbx_user
4421#define gen_op_POWER_lscbx_le_64_kernel gen_op_POWER_lscbx_kernel
4422#define gen_op_POWER_lscbx_le_64_hypv gen_op_POWER_lscbx_hypv
4423static GenOpFunc3 *gen_op_POWER_lscbx[NB_MEM_FUNCS] = {
4424 GEN_MEM_FUNCS(POWER_lscbx),
76a66253 4425};
76a66253
JM		 4426
4427/* lscbx - lscbx. */
4428GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR)
4429{
4430 int ra = rA(ctx->opcode);
4431 int rb = rB(ctx->opcode);
4432
e2be8d8d 4433 gen_addr_reg_index(cpu_T[0], ctx);
76a66253
JM		 4434 if (ra == 0) {
4435 ra = rb;
4436 }
4437 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 4438 gen_update_nip(ctx, ctx->nip - 4);
3d7b417e
AJ		 4439 tcg_gen_andi_tl(cpu_T[1], cpu_xer, 0x7F);
4440 tcg_gen_shri_tl(cpu_T[2], cpu_xer, XER_CMP);
4441 tcg_gen_andi_tl(cpu_T[2], cpu_T[2], 0xFF);
76a66253 4442 op_POWER_lscbx(rD(ctx->opcode), ra, rb);
3d7b417e
AJ		 4443 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
4444 tcg_gen_or_tl(cpu_xer, cpu_xer, cpu_T[0]);
76a66253 4445 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4446 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4447}
4448
4449/* maskg - maskg. */
4450GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR)
4451{
f78fb44e
AJ		 4452 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4453 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4454 gen_op_POWER_maskg();
f78fb44e 4455 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4456 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4457 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4458}
4459
4460/* maskir - maskir. */
4461GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR)
4462{
f78fb44e
AJ		 4463 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4464 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
4465 tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rB(ctx->opcode)]);
76a66253 4466 gen_op_POWER_maskir();
f78fb44e 4467 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4468 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4469 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4470}
4471
4472/* mul - mul. */
4473GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR)
4474{
f78fb44e
AJ		 4475 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4476 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4477 gen_op_POWER_mul();
f78fb44e 4478 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4479 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4480 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4481}
4482
4483/* mulo - mulo. */
4484GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR)
4485{
f78fb44e
AJ		 4486 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4487 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4488 gen_op_POWER_mulo();
f78fb44e 4489 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4490 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4491 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4492}
4493
4494/* nabs - nabs. */
4495GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR)
4496{
f78fb44e 4497 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 4498 gen_op_POWER_nabs();
f78fb44e 4499 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4500 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4501 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4502}
4503
4504/* nabso - nabso. */
4505GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR)
4506{
f78fb44e 4507 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 4508 gen_op_POWER_nabso();
f78fb44e 4509 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4510 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4511 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4512}
4513
4514/* rlmi - rlmi. */
4515GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
4516{
4517 uint32_t mb, me;
4518
4519 mb = MB(ctx->opcode);
4520 me = ME(ctx->opcode);
f78fb44e
AJ		 4521 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4522 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]);
4523 tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rB(ctx->opcode)]);
76a66253 4524 gen_op_POWER_rlmi(MASK(mb, me), ~MASK(mb, me));
f78fb44e 4525 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4526 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4527 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4528}
4529
4530/* rrib - rrib. */
4531GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR)
4532{
f78fb44e
AJ		 4533 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4534 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]);
4535 tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rB(ctx->opcode)]);
76a66253 4536 gen_op_POWER_rrib();
f78fb44e 4537 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4538 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4539 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4540}
4541
4542/* sle - sle. */
4543GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR)
4544{
f78fb44e
AJ		 4545 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4546 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4547 gen_op_POWER_sle();
f78fb44e 4548 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4549 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4550 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4551}
4552
4553/* sleq - sleq. */
4554GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR)
4555{
f78fb44e
AJ		 4556 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4557 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4558 gen_op_POWER_sleq();
f78fb44e 4559 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4560 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4561 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4562}
4563
4564/* sliq - sliq. */
4565GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR)
4566{
f78fb44e 4567 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
86c581dc 4568 tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
76a66253 4569 gen_op_POWER_sle();
f78fb44e 4570 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4571 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4572 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4573}
4574
4575/* slliq - slliq. */
4576GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR)
4577{
f78fb44e 4578 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
86c581dc 4579 tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
76a66253 4580 gen_op_POWER_sleq();
f78fb44e 4581 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4582 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4583 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4584}
4585
4586/* sllq - sllq. */
4587GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR)
4588{
f78fb44e
AJ		 4589 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4590 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4591 gen_op_POWER_sllq();
f78fb44e 4592 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4593 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4594 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4595}
4596
4597/* slq - slq. */
4598GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR)
4599{
f78fb44e
AJ		 4600 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4601 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4602 gen_op_POWER_slq();
f78fb44e 4603 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4604 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4605 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4606}
4607
d9bce9d9 4608/* sraiq - sraiq. */
76a66253
JM		 4609GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR)
4610{
f78fb44e 4611 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
86c581dc 4612 tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
76a66253 4613 gen_op_POWER_sraq();
f78fb44e 4614 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4615 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4616 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4617}
4618
4619/* sraq - sraq. */
4620GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR)
4621{
f78fb44e
AJ		 4622 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4623 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4624 gen_op_POWER_sraq();
f78fb44e 4625 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4626 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4627 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4628}
4629
4630/* sre - sre. */
4631GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR)
4632{
f78fb44e
AJ		 4633 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4634 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4635 gen_op_POWER_sre();
f78fb44e 4636 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4637 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4638 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4639}
4640
4641/* srea - srea. */
4642GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR)
4643{
f78fb44e
AJ		 4644 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4645 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4646 gen_op_POWER_srea();
f78fb44e 4647 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4648 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4649 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4650}
4651
4652/* sreq */
4653GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR)
4654{
f78fb44e
AJ		 4655 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4656 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4657 gen_op_POWER_sreq();
f78fb44e 4658 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4659 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4660 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4661}
4662
4663/* sriq */
4664GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR)
4665{
f78fb44e 4666 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
86c581dc 4667 tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
76a66253 4668 gen_op_POWER_srq();
f78fb44e 4669 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4670 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4671 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4672}
4673
4674/* srliq */
4675GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR)
4676{
f78fb44e
AJ		 4677 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4678 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
86c581dc 4679 tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
76a66253 4680 gen_op_POWER_srlq();
f78fb44e 4681 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4682 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4683 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4684}
4685
4686/* srlq */
4687GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR)
4688{
f78fb44e
AJ		 4689 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4690 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4691 gen_op_POWER_srlq();
f78fb44e 4692 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4693 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4694 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4695}
4696
4697/* srq */
4698GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR)
4699{
f78fb44e
AJ		 4700 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4701 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4702 gen_op_POWER_srq();
f78fb44e 4703 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4704 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4705 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4706}
4707
4708/* PowerPC 602 specific instructions */
4709/* dsa */
4710GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC)
4711{
4712 /* XXX: TODO */
e1833e1f 4713 GEN_EXCP_INVAL(ctx);
76a66253
JM		 4714}
4715
4716/* esa */
4717GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC)
4718{
4719 /* XXX: TODO */
e1833e1f 4720 GEN_EXCP_INVAL(ctx);
76a66253
JM		 4721}
4722
4723/* mfrom */
4724GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC)
4725{
4726#if defined(CONFIG_USER_ONLY)
e1833e1f 4727 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4728#else
4729 if (unlikely(!ctx->supervisor)) {
e1833e1f 4730 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4731 return;
4732 }
f78fb44e 4733 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 4734 gen_op_602_mfrom();
f78fb44e 4735 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4736#endif
4737}
4738
4739/* 602 - 603 - G2 TLB management */
4740/* tlbld */
c7697e1f 4741GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB)
76a66253
JM		 4742{
4743#if defined(CONFIG_USER_ONLY)
e1833e1f 4744 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4745#else
4746 if (unlikely(!ctx->supervisor)) {
e1833e1f 4747 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4748 return;
4749 }
f78fb44e 4750 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
76a66253 4751 gen_op_6xx_tlbld();
76a66253
JM		 4752#endif
4753}
4754
4755/* tlbli */
c7697e1f 4756GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB)
76a66253
JM		 4757{
4758#if defined(CONFIG_USER_ONLY)
e1833e1f 4759 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4760#else
4761 if (unlikely(!ctx->supervisor)) {
e1833e1f 4762 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4763 return;
4764 }
f78fb44e 4765 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
76a66253 4766 gen_op_6xx_tlbli();
76a66253
JM		 4767#endif
4768}
4769
7dbe11ac
JM		 4770/* 74xx TLB management */
4771/* tlbld */
c7697e1f 4772GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB)
7dbe11ac
JM		 4773{
4774#if defined(CONFIG_USER_ONLY)
4775 GEN_EXCP_PRIVOPC(ctx);
4776#else
4777 if (unlikely(!ctx->supervisor)) {
4778 GEN_EXCP_PRIVOPC(ctx);
4779 return;
4780 }
f78fb44e 4781 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
7dbe11ac
JM		 4782 gen_op_74xx_tlbld();
4783#endif
4784}
4785
4786/* tlbli */
c7697e1f 4787GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB)
7dbe11ac
JM		 4788{
4789#if defined(CONFIG_USER_ONLY)
4790 GEN_EXCP_PRIVOPC(ctx);
4791#else
4792 if (unlikely(!ctx->supervisor)) {
4793 GEN_EXCP_PRIVOPC(ctx);
4794 return;
4795 }
f78fb44e 4796 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
7dbe11ac
JM		 4797 gen_op_74xx_tlbli();
4798#endif
4799}
4800
76a66253
JM		 4801/* POWER instructions not in PowerPC 601 */
4802/* clf */
4803GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER)
4804{
4805 /* Cache line flush: implemented as no-op */
4806}
4807
4808/* cli */
4809GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER)
4810{
7f75ffd3 4811 /* Cache line invalidate: privileged and treated as no-op */
76a66253 4812#if defined(CONFIG_USER_ONLY)
e1833e1f 4813 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4814#else
4815 if (unlikely(!ctx->supervisor)) {
e1833e1f 4816 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4817 return;
4818 }
4819#endif
4820}
4821
4822/* dclst */
4823GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER)
4824{
4825 /* Data cache line store: treated as no-op */
4826}
4827
4828GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER)
4829{
4830#if defined(CONFIG_USER_ONLY)
e1833e1f 4831 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4832#else
4833 if (unlikely(!ctx->supervisor)) {
e1833e1f 4834 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4835 return;
4836 }
4837 int ra = rA(ctx->opcode);
4838 int rd = rD(ctx->opcode);
4839
e2be8d8d 4840 gen_addr_reg_index(cpu_T[0], ctx);
76a66253 4841 gen_op_POWER_mfsri();
f78fb44e 4842 tcg_gen_mov_tl(cpu_gpr[rd], cpu_T[0]);
76a66253 4843 if (ra != 0 && ra != rd)
f78fb44e 4844 tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[1]);
76a66253
JM		 4845#endif
4846}
4847
4848GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER)
4849{
4850#if defined(CONFIG_USER_ONLY)
e1833e1f 4851 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4852#else
4853 if (unlikely(!ctx->supervisor)) {
e1833e1f 4854 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4855 return;
4856 }
e2be8d8d 4857 gen_addr_reg_index(cpu_T[0], ctx);
76a66253 4858 gen_op_POWER_rac();
f78fb44e 4859 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4860#endif
4861}
4862
4863GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER)
4864{
4865#if defined(CONFIG_USER_ONLY)
e1833e1f 4866 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4867#else
4868 if (unlikely(!ctx->supervisor)) {
e1833e1f 4869 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4870 return;
4871 }
4872 gen_op_POWER_rfsvc();
e1833e1f 4873 GEN_SYNC(ctx);
76a66253
JM		 4874#endif
4875}
4876
4877/* svc is not implemented for now */
4878
4879/* POWER2 specific instructions */
4880/* Quad manipulation (load/store two floats at a time) */
7863667f 4881/* Original POWER2 is 32 bits only, define 64 bits ops as 32 bits ones */
76a66253
JM		 4882#define op_POWER2_lfq() (*gen_op_POWER2_lfq[ctx->mem_idx])()
4883#define op_POWER2_stfq() (*gen_op_POWER2_stfq[ctx->mem_idx])()
7863667f
JM		 4884#define gen_op_POWER2_lfq_64_raw gen_op_POWER2_lfq_raw
4885#define gen_op_POWER2_lfq_64_user gen_op_POWER2_lfq_user
4886#define gen_op_POWER2_lfq_64_kernel gen_op_POWER2_lfq_kernel
4887#define gen_op_POWER2_lfq_64_hypv gen_op_POWER2_lfq_hypv
4888#define gen_op_POWER2_lfq_le_64_raw gen_op_POWER2_lfq_le_raw
4889#define gen_op_POWER2_lfq_le_64_user gen_op_POWER2_lfq_le_user
4890#define gen_op_POWER2_lfq_le_64_kernel gen_op_POWER2_lfq_le_kernel
4891#define gen_op_POWER2_lfq_le_64_hypv gen_op_POWER2_lfq_le_hypv
4892#define gen_op_POWER2_stfq_64_raw gen_op_POWER2_stfq_raw
4893#define gen_op_POWER2_stfq_64_user gen_op_POWER2_stfq_user
4894#define gen_op_POWER2_stfq_64_kernel gen_op_POWER2_stfq_kernel
4895#define gen_op_POWER2_stfq_64_hypv gen_op_POWER2_stfq_hypv
4896#define gen_op_POWER2_stfq_le_64_raw gen_op_POWER2_stfq_le_raw
4897#define gen_op_POWER2_stfq_le_64_user gen_op_POWER2_stfq_le_user
4898#define gen_op_POWER2_stfq_le_64_kernel gen_op_POWER2_stfq_le_kernel
4899#define gen_op_POWER2_stfq_le_64_hypv gen_op_POWER2_stfq_le_hypv
4900static GenOpFunc *gen_op_POWER2_lfq[NB_MEM_FUNCS] = {
4901 GEN_MEM_FUNCS(POWER2_lfq),
76a66253 4902};
7863667f
JM		 4903static GenOpFunc *gen_op_POWER2_stfq[NB_MEM_FUNCS] = {
4904 GEN_MEM_FUNCS(POWER2_stfq),
76a66253 4905};
76a66253
JM		 4906
4907/* lfq */
4908GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
4909{
4910 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 4911 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 4912 gen_addr_imm_index(cpu_T[0], ctx, 0);
76a66253 4913 op_POWER2_lfq();
a5e26afa
AJ		 4914 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
4915 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode) + 1], cpu_FT[1]);
76a66253
JM		 4916}
4917
4918/* lfqu */
4919GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
4920{
4921 int ra = rA(ctx->opcode);
4922
4923 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 4924 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 4925 gen_addr_imm_index(cpu_T[0], ctx, 0);
76a66253 4926 op_POWER2_lfq();
a5e26afa
AJ		 4927 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
4928 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode) + 1], cpu_FT[1]);
76a66253 4929 if (ra != 0)
f78fb44e 4930 tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]);
76a66253
JM		 4931}
4932
4933/* lfqux */
4934GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2)
4935{
4936 int ra = rA(ctx->opcode);
4937
4938 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 4939 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 4940 gen_addr_reg_index(cpu_T[0], ctx);
76a66253 4941 op_POWER2_lfq();
a5e26afa
AJ		 4942 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
4943 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode) + 1], cpu_FT[1]);
76a66253 4944 if (ra != 0)
f78fb44e 4945 tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]);
76a66253
JM		 4946}
4947
4948/* lfqx */
4949GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2)
4950{
4951 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 4952 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 4953 gen_addr_reg_index(cpu_T[0], ctx);
76a66253 4954 op_POWER2_lfq();
a5e26afa
AJ		 4955 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
4956 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode) + 1], cpu_FT[1]);
76a66253
JM		 4957}
4958
4959/* stfq */
4960GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
4961{
4962 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 4963 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 4964 gen_addr_imm_index(cpu_T[0], ctx, 0);
a5e26afa
AJ		 4965 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]);
4966 tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rS(ctx->opcode) + 1]);
76a66253
JM		 4967 op_POWER2_stfq();
4968}
4969
4970/* stfqu */
4971GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
4972{
4973 int ra = rA(ctx->opcode);
4974
4975 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 4976 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 4977 gen_addr_imm_index(cpu_T[0], ctx, 0);
a5e26afa
AJ		 4978 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]);
4979 tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rS(ctx->opcode) + 1]);
76a66253
JM		 4980 op_POWER2_stfq();
4981 if (ra != 0)
f78fb44e 4982 tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]);
76a66253
JM		 4983}
4984
4985/* stfqux */
4986GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2)
4987{
4988 int ra = rA(ctx->opcode);
4989
4990 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 4991 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 4992 gen_addr_reg_index(cpu_T[0], ctx);
a5e26afa
AJ		 4993 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]);
4994 tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rS(ctx->opcode) + 1]);
76a66253
JM		 4995 op_POWER2_stfq();
4996 if (ra != 0)
f78fb44e 4997 tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]);
76a66253
JM		 4998}
4999
5000/* stfqx */
5001GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2)
5002{
5003 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 5004 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 5005 gen_addr_reg_index(cpu_T[0], ctx);
a5e26afa
AJ		 5006 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]);
5007 tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rS(ctx->opcode) + 1]);
76a66253
JM		 5008 op_POWER2_stfq();
5009}
5010
5011/* BookE specific instructions */
2662a059 5012/* XXX: not implemented on 440 ? */
05332d70 5013GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI)
76a66253
JM		 5014{
5015 /* XXX: TODO */
e1833e1f 5016 GEN_EXCP_INVAL(ctx);
76a66253
JM		 5017}
5018
2662a059 5019/* XXX: not implemented on 440 ? */
05332d70 5020GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA)
76a66253
JM		 5021{
5022#if defined(CONFIG_USER_ONLY)
e1833e1f 5023 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5024#else
5025 if (unlikely(!ctx->supervisor)) {
e1833e1f 5026 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5027 return;
5028 }
e2be8d8d 5029 gen_addr_reg_index(cpu_T[0], ctx);
76a66253 5030 /* Use the same micro-ops as for tlbie */
d9bce9d9
JM		 5031#if defined(TARGET_PPC64)
5032 if (ctx->sf_mode)
5033 gen_op_tlbie_64();
5034 else
5035#endif
5036 gen_op_tlbie();
76a66253
JM		 5037#endif
5038}
5039
5040/* All 405 MAC instructions are translated here */
b068d6a7
JM		 5041static always_inline void gen_405_mulladd_insn (DisasContext *ctx,
5042 int opc2, int opc3,
5043 int ra, int rb, int rt, int Rc)
76a66253 5044{
f78fb44e
AJ		 5045 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[ra]);
5046 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rb]);
76a66253
JM		 5047 switch (opc3 & 0x0D) {
5048 case 0x05:
5049 /* macchw - macchw. - macchwo - macchwo. */
5050 /* macchws - macchws. - macchwso - macchwso. */
5051 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5052 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5053 /* mulchw - mulchw. */
5054 gen_op_405_mulchw();
5055 break;
5056 case 0x04:
5057 /* macchwu - macchwu. - macchwuo - macchwuo. */
5058 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5059 /* mulchwu - mulchwu. */
5060 gen_op_405_mulchwu();
5061 break;
5062 case 0x01:
5063 /* machhw - machhw. - machhwo - machhwo. */
5064 /* machhws - machhws. - machhwso - machhwso. */
5065 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5066 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5067 /* mulhhw - mulhhw. */
5068 gen_op_405_mulhhw();
5069 break;
5070 case 0x00:
5071 /* machhwu - machhwu. - machhwuo - machhwuo. */
5072 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5073 /* mulhhwu - mulhhwu. */
5074 gen_op_405_mulhhwu();
5075 break;
5076 case 0x0D:
5077 /* maclhw - maclhw. - maclhwo - maclhwo. */
5078 /* maclhws - maclhws. - maclhwso - maclhwso. */
5079 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5080 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5081 /* mullhw - mullhw. */
5082 gen_op_405_mullhw();
5083 break;
5084 case 0x0C:
5085 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5086 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5087 /* mullhwu - mullhwu. */
5088 gen_op_405_mullhwu();
5089 break;
5090 }
5091 if (opc2 & 0x02) {
5092 /* nmultiply-and-accumulate (0x0E) */
5093 gen_op_neg();
5094 }
5095 if (opc2 & 0x04) {
5096 /* (n)multiply-and-accumulate (0x0C - 0x0E) */
f78fb44e 5097 tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rt]);
e55fd934 5098 tcg_gen_mov_tl(cpu_T[1], cpu_T[0]);
76a66253
JM		 5099 gen_op_405_add_T0_T2();
5100 }
5101 if (opc3 & 0x10) {
5102 /* Check overflow */
5103 if (opc3 & 0x01)
c3e10c7b 5104 gen_op_check_addo();
76a66253
JM		 5105 else
5106 gen_op_405_check_ovu();
5107 }
5108 if (opc3 & 0x02) {
5109 /* Saturate */
5110 if (opc3 & 0x01)
5111 gen_op_405_check_sat();
5112 else
5113 gen_op_405_check_satu();
5114 }
f78fb44e 5115 tcg_gen_mov_tl(cpu_gpr[rt], cpu_T[0]);
76a66253
JM		 5116 if (unlikely(Rc) != 0) {
5117 /* Update Rc0 */
e1571908 5118 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 5119 }
5120}
5121
a750fc0b
JM		 5122#define GEN_MAC_HANDLER(name, opc2, opc3) \
5123GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) \
76a66253
JM		 5124{ \
5125 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5126 rD(ctx->opcode), Rc(ctx->opcode)); \
5127}
5128
5129/* macchw - macchw. */
a750fc0b 5130GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
76a66253 5131/* macchwo - macchwo. */
a750fc0b 5132GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
76a66253 5133/* macchws - macchws. */
a750fc0b 5134GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
76a66253 5135/* macchwso - macchwso. */
a750fc0b 5136GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
76a66253 5137/* macchwsu - macchwsu. */
a750fc0b 5138GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
76a66253 5139/* macchwsuo - macchwsuo. */
a750fc0b 5140GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
76a66253 5141/* macchwu - macchwu. */
a750fc0b 5142GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
76a66253 5143/* macchwuo - macchwuo. */
a750fc0b 5144GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
76a66253 5145/* machhw - machhw. */
a750fc0b 5146GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
76a66253 5147/* machhwo - machhwo. */
a750fc0b 5148GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
76a66253 5149/* machhws - machhws. */
a750fc0b 5150GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
76a66253 5151/* machhwso - machhwso. */
a750fc0b 5152GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
76a66253 5153/* machhwsu - machhwsu. */
a750fc0b 5154GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
76a66253 5155/* machhwsuo - machhwsuo. */
a750fc0b 5156GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
76a66253 5157/* machhwu - machhwu. */
a750fc0b 5158GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
76a66253 5159/* machhwuo - machhwuo. */
a750fc0b 5160GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
76a66253 5161/* maclhw - maclhw. */
a750fc0b 5162GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
76a66253 5163/* maclhwo - maclhwo. */
a750fc0b 5164GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
76a66253 5165/* maclhws - maclhws. */
a750fc0b 5166GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
76a66253 5167/* maclhwso - maclhwso. */
a750fc0b 5168GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
76a66253 5169/* maclhwu - maclhwu. */
a750fc0b 5170GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
76a66253 5171/* maclhwuo - maclhwuo. */
a750fc0b 5172GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
76a66253 5173/* maclhwsu - maclhwsu. */
a750fc0b 5174GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
76a66253 5175/* maclhwsuo - maclhwsuo. */
a750fc0b 5176GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
76a66253 5177/* nmacchw - nmacchw. */
a750fc0b 5178GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
76a66253 5179/* nmacchwo - nmacchwo. */
a750fc0b 5180GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
76a66253 5181/* nmacchws - nmacchws. */
a750fc0b 5182GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
76a66253 5183/* nmacchwso - nmacchwso. */
a750fc0b 5184GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
76a66253 5185/* nmachhw - nmachhw. */
a750fc0b 5186GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
76a66253 5187/* nmachhwo - nmachhwo. */
a750fc0b 5188GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
76a66253 5189/* nmachhws - nmachhws. */
a750fc0b 5190GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
76a66253 5191/* nmachhwso - nmachhwso. */
a750fc0b 5192GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
76a66253 5193/* nmaclhw - nmaclhw. */
a750fc0b 5194GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
76a66253 5195/* nmaclhwo - nmaclhwo. */
a750fc0b 5196GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
76a66253 5197/* nmaclhws - nmaclhws. */
a750fc0b 5198GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
76a66253 5199/* nmaclhwso - nmaclhwso. */
a750fc0b 5200GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
76a66253
JM		 5201
5202/* mulchw - mulchw. */
a750fc0b 5203GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
76a66253 5204/* mulchwu - mulchwu. */
a750fc0b 5205GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
76a66253 5206/* mulhhw - mulhhw. */
a750fc0b 5207GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
76a66253 5208/* mulhhwu - mulhhwu. */
a750fc0b 5209GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
76a66253 5210/* mullhw - mullhw. */
a750fc0b 5211GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
76a66253 5212/* mullhwu - mullhwu. */
a750fc0b 5213GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
76a66253
JM		 5214
5215/* mfdcr */
05332d70 5216GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR)
76a66253
JM		 5217{
5218#if defined(CONFIG_USER_ONLY)
e1833e1f 5219 GEN_EXCP_PRIVREG(ctx);
76a66253
JM		 5220#else
5221 uint32_t dcrn = SPR(ctx->opcode);
5222
5223 if (unlikely(!ctx->supervisor)) {
e1833e1f 5224 GEN_EXCP_PRIVREG(ctx);
76a66253
JM		 5225 return;
5226 }
86c581dc 5227 tcg_gen_movi_tl(cpu_T[0], dcrn);
a42bd6cc 5228 gen_op_load_dcr();
f78fb44e 5229 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 5230#endif
5231}
5232
5233/* mtdcr */
05332d70 5234GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR)
76a66253
JM		 5235{
5236#if defined(CONFIG_USER_ONLY)
e1833e1f 5237 GEN_EXCP_PRIVREG(ctx);
76a66253
JM		 5238#else
5239 uint32_t dcrn = SPR(ctx->opcode);
5240
5241 if (unlikely(!ctx->supervisor)) {
e1833e1f 5242 GEN_EXCP_PRIVREG(ctx);
76a66253
JM		 5243 return;
5244 }
86c581dc 5245 tcg_gen_movi_tl(cpu_T[0], dcrn);
f78fb44e 5246 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
a42bd6cc
JM		 5247 gen_op_store_dcr();
5248#endif
5249}
5250
5251/* mfdcrx */
2662a059 5252/* XXX: not implemented on 440 ? */
05332d70 5253GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX)
a42bd6cc
JM		 5254{
5255#if defined(CONFIG_USER_ONLY)
e1833e1f 5256 GEN_EXCP_PRIVREG(ctx);
a42bd6cc
JM		 5257#else
5258 if (unlikely(!ctx->supervisor)) {
e1833e1f 5259 GEN_EXCP_PRIVREG(ctx);
a42bd6cc
JM		 5260 return;
5261 }
f78fb44e 5262 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
a42bd6cc 5263 gen_op_load_dcr();
f78fb44e 5264 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
a750fc0b 5265 /* Note: Rc update flag set leads to undefined state of Rc0 */
a42bd6cc
JM		 5266#endif
5267}
5268
5269/* mtdcrx */
2662a059 5270/* XXX: not implemented on 440 ? */
05332d70 5271GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX)
a42bd6cc
JM		 5272{
5273#if defined(CONFIG_USER_ONLY)
e1833e1f 5274 GEN_EXCP_PRIVREG(ctx);
a42bd6cc
JM		 5275#else
5276 if (unlikely(!ctx->supervisor)) {
e1833e1f 5277 GEN_EXCP_PRIVREG(ctx);
a42bd6cc
JM		 5278 return;
5279 }
f78fb44e
AJ		 5280 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5281 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
a42bd6cc 5282 gen_op_store_dcr();
a750fc0b 5283 /* Note: Rc update flag set leads to undefined state of Rc0 */
76a66253
JM		 5284#endif
5285}
5286
a750fc0b
JM		 5287/* mfdcrux (PPC 460) : user-mode access to DCR */
5288GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX)
5289{
f78fb44e 5290 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
a750fc0b 5291 gen_op_load_dcr();
f78fb44e 5292 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
a750fc0b
JM		 5293 /* Note: Rc update flag set leads to undefined state of Rc0 */
5294}
5295
5296/* mtdcrux (PPC 460) : user-mode access to DCR */
5297GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX)
5298{
f78fb44e
AJ		 5299 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5300 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
a750fc0b
JM		 5301 gen_op_store_dcr();
5302 /* Note: Rc update flag set leads to undefined state of Rc0 */
5303}
5304
76a66253
JM		 5305/* dccci */
5306GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON)
5307{
5308#if defined(CONFIG_USER_ONLY)
e1833e1f 5309 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5310#else
5311 if (unlikely(!ctx->supervisor)) {
e1833e1f 5312 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5313 return;
5314 }
5315 /* interpreted as no-op */
5316#endif
5317}
5318
5319/* dcread */
5320GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON)
5321{
5322#if defined(CONFIG_USER_ONLY)
e1833e1f 5323 GEN_EXCP_PRIVOPC(ctx);
76a66253 5324#else
b61f2753 5325 TCGv EA, val;
76a66253 5326 if (unlikely(!ctx->supervisor)) {
e1833e1f 5327 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5328 return;
5329 }
b61f2753
AJ		 5330 EA = tcg_temp_new(TCG_TYPE_TL);
5331 gen_addr_reg_index(EA, ctx);
5332 val = tcg_temp_new(TCG_TYPE_TL);
5333 gen_qemu_ld32u(val, EA, ctx->mem_idx);
5334 tcg_temp_free(val);
5335 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
5336 tcg_temp_free(EA);
76a66253
JM		 5337#endif
5338}
5339
5340/* icbt */
c7697e1f 5341GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT)
76a66253
JM		 5342{
5343 /* interpreted as no-op */
5344 /* XXX: specification say this is treated as a load by the MMU
5345 * but does not generate any exception
5346 */
5347}
5348
5349/* iccci */
5350GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON)
5351{
5352#if defined(CONFIG_USER_ONLY)
e1833e1f 5353 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5354#else
5355 if (unlikely(!ctx->supervisor)) {
e1833e1f 5356 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5357 return;
5358 }
5359 /* interpreted as no-op */
5360#endif
5361}
5362
5363/* icread */
5364GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON)
5365{
5366#if defined(CONFIG_USER_ONLY)
e1833e1f 5367 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5368#else
5369 if (unlikely(!ctx->supervisor)) {
e1833e1f 5370 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5371 return;
5372 }
5373 /* interpreted as no-op */
5374#endif
5375}
5376
5377/* rfci (supervisor only) */
c7697e1f 5378GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP)
a42bd6cc
JM		 5379{
5380#if defined(CONFIG_USER_ONLY)
e1833e1f 5381 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 5382#else
5383 if (unlikely(!ctx->supervisor)) {
e1833e1f 5384 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 5385 return;
5386 }
5387 /* Restore CPU state */
5388 gen_op_40x_rfci();
e1833e1f 5389 GEN_SYNC(ctx);
a42bd6cc
JM		 5390#endif
5391}
5392
5393GEN_HANDLER(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE)
5394{
5395#if defined(CONFIG_USER_ONLY)
e1833e1f 5396 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 5397#else
5398 if (unlikely(!ctx->supervisor)) {
e1833e1f 5399 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 5400 return;
5401 }
5402 /* Restore CPU state */
5403 gen_op_rfci();
e1833e1f 5404 GEN_SYNC(ctx);
a42bd6cc
JM		 5405#endif
5406}
5407
5408/* BookE specific */
2662a059 5409/* XXX: not implemented on 440 ? */
05332d70 5410GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI)
76a66253
JM		 5411{
5412#if defined(CONFIG_USER_ONLY)
e1833e1f 5413 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5414#else
5415 if (unlikely(!ctx->supervisor)) {
e1833e1f 5416 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5417 return;
5418 }
5419 /* Restore CPU state */
a42bd6cc 5420 gen_op_rfdi();
e1833e1f 5421 GEN_SYNC(ctx);
76a66253
JM		 5422#endif
5423}
5424
2662a059 5425/* XXX: not implemented on 440 ? */
a750fc0b 5426GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI)
a42bd6cc
JM		 5427{
5428#if defined(CONFIG_USER_ONLY)
e1833e1f 5429 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 5430#else
5431 if (unlikely(!ctx->supervisor)) {
e1833e1f 5432 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 5433 return;
5434 }
5435 /* Restore CPU state */
5436 gen_op_rfmci();
e1833e1f 5437 GEN_SYNC(ctx);
a42bd6cc
JM		 5438#endif
5439}
5eb7995e 5440
d9bce9d9 5441/* TLB management - PowerPC 405 implementation */
76a66253 5442/* tlbre */
c7697e1f 5443GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB)
76a66253
JM		 5444{
5445#if defined(CONFIG_USER_ONLY)
e1833e1f 5446 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5447#else
5448 if (unlikely(!ctx->supervisor)) {
e1833e1f 5449 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5450 return;
5451 }
5452 switch (rB(ctx->opcode)) {
5453 case 0:
f78fb44e 5454 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 5455 gen_op_4xx_tlbre_hi();
f78fb44e 5456 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 5457 break;
5458 case 1:
f78fb44e 5459 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 5460 gen_op_4xx_tlbre_lo();
f78fb44e 5461 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 5462 break;
5463 default:
e1833e1f 5464 GEN_EXCP_INVAL(ctx);
76a66253 5465 break;
9a64fbe4 5466 }
76a66253
JM		 5467#endif
5468}
5469
d9bce9d9 5470/* tlbsx - tlbsx. */
c7697e1f 5471GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB)
76a66253
JM		 5472{
5473#if defined(CONFIG_USER_ONLY)
e1833e1f 5474 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5475#else
5476 if (unlikely(!ctx->supervisor)) {
e1833e1f 5477 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5478 return;
5479 }
e2be8d8d 5480 gen_addr_reg_index(cpu_T[0], ctx);
daf4f96e 5481 gen_op_4xx_tlbsx();
76a66253 5482 if (Rc(ctx->opcode))
daf4f96e 5483 gen_op_4xx_tlbsx_check();
f78fb44e 5484 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 5485#endif
79aceca5
FB		 5486}
5487
76a66253 5488/* tlbwe */
c7697e1f 5489GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB)
79aceca5 5490{
76a66253 5491#if defined(CONFIG_USER_ONLY)
e1833e1f 5492 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5493#else
5494 if (unlikely(!ctx->supervisor)) {
e1833e1f 5495 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5496 return;
5497 }
5498 switch (rB(ctx->opcode)) {
5499 case 0:
f78fb44e
AJ		 5500 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5501 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
76a66253
JM		 5502 gen_op_4xx_tlbwe_hi();
5503 break;
5504 case 1:
f78fb44e
AJ		 5505 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5506 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
76a66253
JM		 5507 gen_op_4xx_tlbwe_lo();
5508 break;
5509 default:
e1833e1f 5510 GEN_EXCP_INVAL(ctx);
76a66253 5511 break;
9a64fbe4 5512 }
76a66253
JM		 5513#endif
5514}
5515
a4bb6c3e 5516/* TLB management - PowerPC 440 implementation */
5eb7995e 5517/* tlbre */
c7697e1f 5518GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE)
5eb7995e
JM		 5519{
5520#if defined(CONFIG_USER_ONLY)
e1833e1f 5521 GEN_EXCP_PRIVOPC(ctx);
5eb7995e
JM		 5522#else
5523 if (unlikely(!ctx->supervisor)) {
e1833e1f 5524 GEN_EXCP_PRIVOPC(ctx);
5eb7995e
JM		 5525 return;
5526 }
5527 switch (rB(ctx->opcode)) {
5528 case 0:
5eb7995e 5529 case 1:
5eb7995e 5530 case 2:
f78fb44e 5531 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
a4bb6c3e 5532 gen_op_440_tlbre(rB(ctx->opcode));
f78fb44e 5533 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
5eb7995e
JM		 5534 break;
5535 default:
e1833e1f 5536 GEN_EXCP_INVAL(ctx);
5eb7995e
JM		 5537 break;
5538 }
5539#endif
5540}
5541
5542/* tlbsx - tlbsx. */
c7697e1f 5543GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE)
5eb7995e
JM		 5544{
5545#if defined(CONFIG_USER_ONLY)
e1833e1f 5546 GEN_EXCP_PRIVOPC(ctx);
5eb7995e
JM		 5547#else
5548 if (unlikely(!ctx->supervisor)) {
e1833e1f 5549 GEN_EXCP_PRIVOPC(ctx);
5eb7995e
JM		 5550 return;
5551 }
e2be8d8d 5552 gen_addr_reg_index(cpu_T[0], ctx);
daf4f96e 5553 gen_op_440_tlbsx();
5eb7995e 5554 if (Rc(ctx->opcode))
daf4f96e 5555 gen_op_4xx_tlbsx_check();
f78fb44e 5556 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
5eb7995e
JM		 5557#endif
5558}
5559
5560/* tlbwe */
c7697e1f 5561GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE)
5eb7995e
JM		 5562{
5563#if defined(CONFIG_USER_ONLY)
e1833e1f 5564 GEN_EXCP_PRIVOPC(ctx);
5eb7995e
JM		 5565#else
5566 if (unlikely(!ctx->supervisor)) {
e1833e1f 5567 GEN_EXCP_PRIVOPC(ctx);
5eb7995e
JM		 5568 return;
5569 }
5570 switch (rB(ctx->opcode)) {
5571 case 0:
5eb7995e 5572 case 1:
5eb7995e 5573 case 2:
f78fb44e
AJ		 5574 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5575 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
a4bb6c3e 5576 gen_op_440_tlbwe(rB(ctx->opcode));
5eb7995e
JM		 5577 break;
5578 default:
e1833e1f 5579 GEN_EXCP_INVAL(ctx);
5eb7995e
JM		 5580 break;
5581 }
5582#endif
5583}
5584
76a66253 5585/* wrtee */
05332d70 5586GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE)
76a66253
JM		 5587{
5588#if defined(CONFIG_USER_ONLY)
e1833e1f 5589 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5590#else
5591 if (unlikely(!ctx->supervisor)) {
e1833e1f 5592 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5593 return;
5594 }
f78fb44e 5595 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rD(ctx->opcode)]);
a42bd6cc 5596 gen_op_wrte();
dee96f6c
JM		 5597 /* Stop translation to have a chance to raise an exception
5598 * if we just set msr_ee to 1
5599 */
e1833e1f 5600 GEN_STOP(ctx);
76a66253
JM		 5601#endif
5602}
5603
5604/* wrteei */
05332d70 5605GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000EFC01, PPC_WRTEE)
76a66253
JM		 5606{
5607#if defined(CONFIG_USER_ONLY)
e1833e1f 5608 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5609#else
5610 if (unlikely(!ctx->supervisor)) {
e1833e1f 5611 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5612 return;
5613 }
86c581dc 5614 tcg_gen_movi_tl(cpu_T[0], ctx->opcode & 0x00010000);
a42bd6cc 5615 gen_op_wrte();
dee96f6c
JM		 5616 /* Stop translation to have a chance to raise an exception
5617 * if we just set msr_ee to 1
5618 */
e1833e1f 5619 GEN_STOP(ctx);
76a66253
JM		 5620#endif
5621}
5622
08e46e54 5623/* PowerPC 440 specific instructions */
76a66253
JM		 5624/* dlmzb */
5625GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC)
5626{
f78fb44e
AJ		 5627 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
5628 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 5629 gen_op_440_dlmzb();
f78fb44e 5630 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
3d7b417e
AJ		 5631 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
5632 tcg_gen_or_tl(cpu_xer, cpu_xer, cpu_T[0]);
76a66253
JM		 5633 if (Rc(ctx->opcode)) {
5634 gen_op_440_dlmzb_update_Rc();
47e4661c 5635 tcg_gen_andi_i32(cpu_crf[0], cpu_T[0], 0xf);
76a66253
JM		 5636 }
5637}
5638
5639/* mbar replaces eieio on 440 */
5640GEN_HANDLER(mbar, 0x1F, 0x16, 0x13, 0x001FF801, PPC_BOOKE)
5641{
5642 /* interpreted as no-op */
5643}
5644
5645/* msync replaces sync on 440 */
0db1b20e 5646GEN_HANDLER(msync, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE)
76a66253
JM		 5647{
5648 /* interpreted as no-op */
5649}
5650
5651/* icbt */
c7697e1f 5652GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, PPC_BOOKE)
76a66253
JM		 5653{
5654 /* interpreted as no-op */
5655 /* XXX: specification say this is treated as a load by the MMU
5656 * but does not generate any exception
5657 */
79aceca5
FB		 5658}
5659
a9d9eb8f
JM		 5660/*** Altivec vector extension ***/
5661/* Altivec registers moves */
a9d9eb8f 5662
1d542695
AJ		 5663static always_inline void gen_load_avr(int t, int reg) {
5664 tcg_gen_mov_i64(cpu_AVRh[t], cpu_avrh[reg]);
5665 tcg_gen_mov_i64(cpu_AVRl[t], cpu_avrl[reg]);
5666}
5667
5668static always_inline void gen_store_avr(int reg, int t) {
5669 tcg_gen_mov_i64(cpu_avrh[reg], cpu_AVRh[t]);
5670 tcg_gen_mov_i64(cpu_avrl[reg], cpu_AVRl[t]);
5671}
a9d9eb8f
JM		 5672
5673#define op_vr_ldst(name) (*gen_op_##name[ctx->mem_idx])()
a9d9eb8f 5674#define OP_VR_LD_TABLE(name) \
7863667f
JM		 5675static GenOpFunc *gen_op_vr_l##name[NB_MEM_FUNCS] = { \
5676 GEN_MEM_FUNCS(vr_l##name), \
a9d9eb8f
JM		 5677};
5678#define OP_VR_ST_TABLE(name) \
7863667f
JM		 5679static GenOpFunc *gen_op_vr_st##name[NB_MEM_FUNCS] = { \
5680 GEN_MEM_FUNCS(vr_st##name), \
a9d9eb8f 5681};
a9d9eb8f
JM		 5682
5683#define GEN_VR_LDX(name, opc2, opc3) \
5684GEN_HANDLER(l##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
5685{ \
5686 if (unlikely(!ctx->altivec_enabled)) { \
5687 GEN_EXCP_NO_VR(ctx); \
5688 return; \
5689 } \
e2be8d8d 5690 gen_addr_reg_index(cpu_T[0], ctx); \
a9d9eb8f 5691 op_vr_ldst(vr_l##name); \
1d542695 5692 gen_store_avr(rD(ctx->opcode), 0); \
a9d9eb8f
JM		 5693}
5694
5695#define GEN_VR_STX(name, opc2, opc3) \
5696GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
5697{ \
5698 if (unlikely(!ctx->altivec_enabled)) { \
5699 GEN_EXCP_NO_VR(ctx); \
5700 return; \
5701 } \
e2be8d8d 5702 gen_addr_reg_index(cpu_T[0], ctx); \
1d542695 5703 gen_load_avr(0, rS(ctx->opcode)); \
a9d9eb8f
JM		 5704 op_vr_ldst(vr_st##name); \
5705}
5706
5707OP_VR_LD_TABLE(vx);
5708GEN_VR_LDX(vx, 0x07, 0x03);
5709/* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
5710#define gen_op_vr_lvxl gen_op_vr_lvx
5711GEN_VR_LDX(vxl, 0x07, 0x0B);
5712
5713OP_VR_ST_TABLE(vx);
5714GEN_VR_STX(vx, 0x07, 0x07);
5715/* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
5716#define gen_op_vr_stvxl gen_op_vr_stvx
5717GEN_VR_STX(vxl, 0x07, 0x0F);
5718
0487d6a8 5719/*** SPE extension ***/
0487d6a8 5720/* Register moves */
3cd7d1dd 5721
f78fb44e
AJ		 5722static always_inline void gen_load_gpr64(TCGv t, int reg) {
5723#if defined(TARGET_PPC64)
5724 tcg_gen_mov_i64(t, cpu_gpr[reg]);
5725#else
36aa55dc 5726 tcg_gen_concat_i32_i64(t, cpu_gpr[reg], cpu_gprh[reg]);
3cd7d1dd 5727#endif
f78fb44e 5728}
3cd7d1dd 5729
f78fb44e
AJ		 5730static always_inline void gen_store_gpr64(int reg, TCGv t) {
5731#if defined(TARGET_PPC64)
5732 tcg_gen_mov_i64(cpu_gpr[reg], t);
5733#else
5734 tcg_gen_trunc_i64_i32(cpu_gpr[reg], t);
19f98ff6 5735 TCGv tmp = tcg_temp_new(TCG_TYPE_I64);
f78fb44e
AJ		 5736 tcg_gen_shri_i64(tmp, t, 32);
5737 tcg_gen_trunc_i64_i32(cpu_gprh[reg], tmp);
5738 tcg_temp_free(tmp);
3cd7d1dd 5739#endif
f78fb44e 5740}
3cd7d1dd 5741
0487d6a8
JM		 5742#define GEN_SPE(name0, name1, opc2, opc3, inval, type) \
5743GEN_HANDLER(name0##_##name1, 0x04, opc2, opc3, inval, type) \
5744{ \
5745 if (Rc(ctx->opcode)) \
5746 gen_##name1(ctx); \
5747 else \
5748 gen_##name0(ctx); \
5749}
5750
5751/* Handler for undefined SPE opcodes */
b068d6a7 5752static always_inline void gen_speundef (DisasContext *ctx)
0487d6a8 5753{
e1833e1f 5754 GEN_EXCP_INVAL(ctx);
0487d6a8
JM		 5755}
5756
5757/* SPE load and stores */
f0aabd1a 5758static always_inline void gen_addr_spe_imm_index (TCGv EA, DisasContext *ctx, int sh)
0487d6a8
JM		 5759{
5760 target_long simm = rB(ctx->opcode);
5761
f0aabd1a
AJ		 5762 if (rA(ctx->opcode) == 0)
5763 tcg_gen_movi_tl(EA, simm << sh);
5764 else if (likely(simm != 0))
5765 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm << sh);
5766 else
5767 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
0487d6a8
JM		 5768}
5769
5770#define op_spe_ldst(name) (*gen_op_##name[ctx->mem_idx])()
0487d6a8 5771#define OP_SPE_LD_TABLE(name) \
7863667f
JM		 5772static GenOpFunc *gen_op_spe_l##name[NB_MEM_FUNCS] = { \
5773 GEN_MEM_FUNCS(spe_l##name), \
0487d6a8
JM		 5774};
5775#define OP_SPE_ST_TABLE(name) \
7863667f
JM		 5776static GenOpFunc *gen_op_spe_st##name[NB_MEM_FUNCS] = { \
5777 GEN_MEM_FUNCS(spe_st##name), \
2857068e 5778};
0487d6a8
JM		 5779
5780#define GEN_SPE_LD(name, sh) \
b068d6a7 5781static always_inline void gen_evl##name (DisasContext *ctx) \
0487d6a8
JM		 5782{ \
5783 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 5784 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 5785 return; \
5786 } \
f0aabd1a 5787 gen_addr_spe_imm_index(cpu_T[0], ctx, sh); \
0487d6a8 5788 op_spe_ldst(spe_l##name); \
f78fb44e 5789 gen_store_gpr64(rD(ctx->opcode), cpu_T64[1]); \
0487d6a8
JM		 5790}
5791
5792#define GEN_SPE_LDX(name) \
b068d6a7 5793static always_inline void gen_evl##name##x (DisasContext *ctx) \
0487d6a8
JM		 5794{ \
5795 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 5796 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 5797 return; \
5798 } \
e2be8d8d 5799 gen_addr_reg_index(cpu_T[0], ctx); \
0487d6a8 5800 op_spe_ldst(spe_l##name); \
f78fb44e 5801 gen_store_gpr64(rD(ctx->opcode), cpu_T64[1]); \
0487d6a8
JM		 5802}
5803
5804#define GEN_SPEOP_LD(name, sh) \
5805OP_SPE_LD_TABLE(name); \
5806GEN_SPE_LD(name, sh); \
5807GEN_SPE_LDX(name)
5808
5809#define GEN_SPE_ST(name, sh) \
b068d6a7 5810static always_inline void gen_evst##name (DisasContext *ctx) \
0487d6a8
JM		 5811{ \
5812 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 5813 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 5814 return; \
5815 } \
f0aabd1a 5816 gen_addr_spe_imm_index(cpu_T[0], ctx, sh); \
f78fb44e 5817 gen_load_gpr64(cpu_T64[1], rS(ctx->opcode)); \
0487d6a8
JM		 5818 op_spe_ldst(spe_st##name); \
5819}
5820
5821#define GEN_SPE_STX(name) \
b068d6a7 5822static always_inline void gen_evst##name##x (DisasContext *ctx) \
0487d6a8
JM		 5823{ \
5824 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 5825 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 5826 return; \
5827 } \
e2be8d8d 5828 gen_addr_reg_index(cpu_T[0], ctx); \
f78fb44e 5829 gen_load_gpr64(cpu_T64[1], rS(ctx->opcode)); \
0487d6a8
JM		 5830 op_spe_ldst(spe_st##name); \
5831}
5832
5833#define GEN_SPEOP_ST(name, sh) \
5834OP_SPE_ST_TABLE(name); \
5835GEN_SPE_ST(name, sh); \
5836GEN_SPE_STX(name)
5837
5838#define GEN_SPEOP_LDST(name, sh) \
5839GEN_SPEOP_LD(name, sh); \
5840GEN_SPEOP_ST(name, sh)
5841
5842/* SPE arithmetic and logic */
5843#define GEN_SPEOP_ARITH2(name) \
b068d6a7 5844static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 5845{ \
5846 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 5847 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 5848 return; \
5849 } \
f78fb44e
AJ		 5850 gen_load_gpr64(cpu_T64[0], rA(ctx->opcode)); \
5851 gen_load_gpr64(cpu_T64[1], rB(ctx->opcode)); \
0487d6a8 5852 gen_op_##name(); \
f78fb44e 5853 gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]); \
0487d6a8
JM		 5854}
5855
cf960816 5856#define GEN_SPEOP_TCG_ARITH2(name, tcg_op) \
3d3a6a0a
AJ		 5857static always_inline void gen_##name (DisasContext *ctx) \
5858{ \
5859 if (unlikely(!ctx->spe_enabled)) { \
5860 GEN_EXCP_NO_AP(ctx); \
5861 return; \
5862 } \
5863 TCGv t0 = tcg_temp_new(TCG_TYPE_I64); \
5864 TCGv t1 = tcg_temp_new(TCG_TYPE_I64); \
5865 gen_load_gpr64(t0, rA(ctx->opcode)); \
5866 gen_load_gpr64(t1, rB(ctx->opcode)); \
cf960816 5867 tcg_op(t0, t0, t1); \
3d3a6a0a
AJ		 5868 gen_store_gpr64(rD(ctx->opcode), t0); \
5869 tcg_temp_free(t0); \
5870 tcg_temp_free(t1); \
5871}
5872
0487d6a8 5873#define GEN_SPEOP_ARITH1(name) \
b068d6a7 5874static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 5875{ \
5876 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 5877 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 5878 return; \
5879 } \
f78fb44e 5880 gen_load_gpr64(cpu_T64[0], rA(ctx->opcode)); \
0487d6a8 5881 gen_op_##name(); \
f78fb44e 5882 gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]); \
0487d6a8
JM		 5883}
5884
5885#define GEN_SPEOP_COMP(name) \
b068d6a7 5886static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 5887{ \
5888 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 5889 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 5890 return; \
5891 } \
f78fb44e
AJ		 5892 gen_load_gpr64(cpu_T64[0], rA(ctx->opcode)); \
5893 gen_load_gpr64(cpu_T64[1], rB(ctx->opcode)); \
0487d6a8 5894 gen_op_##name(); \
47e4661c 5895 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_T[0], 0xf); \
0487d6a8
JM		 5896}
5897
5898/* Logical */
cf960816
AJ		 5899GEN_SPEOP_TCG_ARITH2(evand, tcg_gen_and_i64);
5900GEN_SPEOP_TCG_ARITH2(evandc, tcg_gen_andc_i64);
5901GEN_SPEOP_TCG_ARITH2(evxor, tcg_gen_xor_i64);
5902GEN_SPEOP_TCG_ARITH2(evor, tcg_gen_or_i64);
5903GEN_SPEOP_TCG_ARITH2(evnor, tcg_gen_nor_i64);
5904GEN_SPEOP_TCG_ARITH2(eveqv, tcg_gen_eqv_i64);
5905GEN_SPEOP_TCG_ARITH2(evorc, tcg_gen_orc_i64);
5906GEN_SPEOP_TCG_ARITH2(evnand, tcg_gen_nand_i64);
0487d6a8
JM		 5907GEN_SPEOP_ARITH2(evsrwu);
5908GEN_SPEOP_ARITH2(evsrws);
5909GEN_SPEOP_ARITH2(evslw);
5910GEN_SPEOP_ARITH2(evrlw);
5911GEN_SPEOP_ARITH2(evmergehi);
5912GEN_SPEOP_ARITH2(evmergelo);
5913GEN_SPEOP_ARITH2(evmergehilo);
5914GEN_SPEOP_ARITH2(evmergelohi);
5915
5916/* Arithmetic */
5917GEN_SPEOP_ARITH2(evaddw);
5918GEN_SPEOP_ARITH2(evsubfw);
5919GEN_SPEOP_ARITH1(evabs);
5920GEN_SPEOP_ARITH1(evneg);
5921GEN_SPEOP_ARITH1(evextsb);
5922GEN_SPEOP_ARITH1(evextsh);
5923GEN_SPEOP_ARITH1(evrndw);
5924GEN_SPEOP_ARITH1(evcntlzw);
5925GEN_SPEOP_ARITH1(evcntlsw);
b068d6a7 5926static always_inline void gen_brinc (DisasContext *ctx)
0487d6a8
JM		 5927{
5928 /* Note: brinc is usable even if SPE is disabled */
f78fb44e
AJ		 5929 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5930 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
0487d6a8 5931 gen_op_brinc();
f78fb44e 5932 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
0487d6a8
JM		 5933}
5934
5935#define GEN_SPEOP_ARITH_IMM2(name) \
b068d6a7 5936static always_inline void gen_##name##i (DisasContext *ctx) \
0487d6a8
JM		 5937{ \
5938 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 5939 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 5940 return; \
5941 } \
f78fb44e 5942 gen_load_gpr64(cpu_T64[0], rB(ctx->opcode)); \
0487d6a8
JM		 5943 gen_op_splatwi_T1_64(rA(ctx->opcode)); \
5944 gen_op_##name(); \
f78fb44e 5945 gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]); \
0487d6a8
JM		 5946}
5947
5948#define GEN_SPEOP_LOGIC_IMM2(name) \
b068d6a7 5949static always_inline void gen_##name##i (DisasContext *ctx) \
0487d6a8
JM		 5950{ \
5951 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 5952 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 5953 return; \
5954 } \
f78fb44e 5955 gen_load_gpr64(cpu_T64[0], rA(ctx->opcode)); \
0487d6a8
JM		 5956 gen_op_splatwi_T1_64(rB(ctx->opcode)); \
5957 gen_op_##name(); \
f78fb44e 5958 gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]); \
0487d6a8
JM		 5959}
5960
5961GEN_SPEOP_ARITH_IMM2(evaddw);
5962#define gen_evaddiw gen_evaddwi
5963GEN_SPEOP_ARITH_IMM2(evsubfw);
5964#define gen_evsubifw gen_evsubfwi
5965GEN_SPEOP_LOGIC_IMM2(evslw);
5966GEN_SPEOP_LOGIC_IMM2(evsrwu);
5967#define gen_evsrwis gen_evsrwsi
5968GEN_SPEOP_LOGIC_IMM2(evsrws);
5969#define gen_evsrwiu gen_evsrwui
5970GEN_SPEOP_LOGIC_IMM2(evrlw);
5971
b068d6a7 5972static always_inline void gen_evsplati (DisasContext *ctx)
0487d6a8
JM		 5973{
5974 int32_t imm = (int32_t)(rA(ctx->opcode) << 27) >> 27;
5975
5976 gen_op_splatwi_T0_64(imm);
f78fb44e 5977 gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]);
0487d6a8
JM		 5978}
5979
b068d6a7 5980static always_inline void gen_evsplatfi (DisasContext *ctx)
0487d6a8
JM		 5981{
5982 uint32_t imm = rA(ctx->opcode) << 27;
5983
5984 gen_op_splatwi_T0_64(imm);
f78fb44e 5985 gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]);
0487d6a8
JM		 5986}
5987
5988/* Comparison */
5989GEN_SPEOP_COMP(evcmpgtu);
5990GEN_SPEOP_COMP(evcmpgts);
5991GEN_SPEOP_COMP(evcmpltu);
5992GEN_SPEOP_COMP(evcmplts);
5993GEN_SPEOP_COMP(evcmpeq);
5994
5995GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, PPC_SPE); ////
5996GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, PPC_SPE);
5997GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, PPC_SPE); ////
5998GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, PPC_SPE);
5999GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, PPC_SPE); ////
6000GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, PPC_SPE); ////
6001GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, PPC_SPE); ////
6002GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x00000000, PPC_SPE); //
6003GEN_SPE(speundef, evand, 0x08, 0x08, 0x00000000, PPC_SPE); ////
6004GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, PPC_SPE); ////
6005GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, PPC_SPE); ////
6006GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, PPC_SPE); ////
6007GEN_SPE(speundef, evorc, 0x0D, 0x08, 0x00000000, PPC_SPE); ////
6008GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, PPC_SPE); ////
6009GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, PPC_SPE); ////
6010GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, PPC_SPE);
6011GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, PPC_SPE); ////
6012GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, PPC_SPE);
6013GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, PPC_SPE); //
6014GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, PPC_SPE);
6015GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, PPC_SPE); ////
6016GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, PPC_SPE); ////
6017GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, PPC_SPE); ////
6018GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, PPC_SPE); ////
6019GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, PPC_SPE); ////
6020
b068d6a7 6021static always_inline void gen_evsel (DisasContext *ctx)
0487d6a8
JM		 6022{
6023 if (unlikely(!ctx->spe_enabled)) {
e1833e1f 6024 GEN_EXCP_NO_AP(ctx);
0487d6a8
JM		 6025 return;
6026 }
47e4661c 6027 tcg_gen_mov_i32(cpu_T[0], cpu_crf[ctx->opcode & 0x7]);
f78fb44e
AJ		 6028 gen_load_gpr64(cpu_T64[0], rA(ctx->opcode));
6029 gen_load_gpr64(cpu_T64[1], rB(ctx->opcode));
0487d6a8 6030 gen_op_evsel();
f78fb44e 6031 gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]);
0487d6a8
JM		 6032}
6033
c7697e1f 6034GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE)
0487d6a8
JM		 6035{
6036 gen_evsel(ctx);
6037}
c7697e1f 6038GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE)
0487d6a8
JM		 6039{
6040 gen_evsel(ctx);
6041}
c7697e1f 6042GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE)
0487d6a8
JM		 6043{
6044 gen_evsel(ctx);
6045}
c7697e1f 6046GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE)
0487d6a8
JM		 6047{
6048 gen_evsel(ctx);
6049}
6050
6051/* Load and stores */
0487d6a8
JM		 6052GEN_SPEOP_LDST(dd, 3);
6053GEN_SPEOP_LDST(dw, 3);
6054GEN_SPEOP_LDST(dh, 3);
6055GEN_SPEOP_LDST(whe, 2);
6056GEN_SPEOP_LD(whou, 2);
6057GEN_SPEOP_LD(whos, 2);
6058GEN_SPEOP_ST(who, 2);
6059
0487d6a8 6060#define _GEN_OP_SPE_STWWE(suffix) \
b068d6a7 6061static always_inline void gen_op_spe_stwwe_##suffix (void) \
0487d6a8
JM		 6062{ \
6063 gen_op_srli32_T1_64(); \
6064 gen_op_spe_stwwo_##suffix(); \
6065}
6066#define _GEN_OP_SPE_STWWE_LE(suffix) \
b068d6a7 6067static always_inline void gen_op_spe_stwwe_le_##suffix (void) \
0487d6a8
JM		 6068{ \
6069 gen_op_srli32_T1_64(); \
6070 gen_op_spe_stwwo_le_##suffix(); \
6071}
6072#if defined(TARGET_PPC64)
6073#define GEN_OP_SPE_STWWE(suffix) \
6074_GEN_OP_SPE_STWWE(suffix); \
6075_GEN_OP_SPE_STWWE_LE(suffix); \
b068d6a7 6076static always_inline void gen_op_spe_stwwe_64_##suffix (void) \
0487d6a8
JM		 6077{ \
6078 gen_op_srli32_T1_64(); \
6079 gen_op_spe_stwwo_64_##suffix(); \
6080} \
b068d6a7 6081static always_inline void gen_op_spe_stwwe_le_64_##suffix (void) \
0487d6a8
JM		 6082{ \
6083 gen_op_srli32_T1_64(); \
6084 gen_op_spe_stwwo_le_64_##suffix(); \
6085}
6086#else
6087#define GEN_OP_SPE_STWWE(suffix) \
6088_GEN_OP_SPE_STWWE(suffix); \
6089_GEN_OP_SPE_STWWE_LE(suffix)
6090#endif
6091#if defined(CONFIG_USER_ONLY)
6092GEN_OP_SPE_STWWE(raw);
6093#else /* defined(CONFIG_USER_ONLY) */
0487d6a8 6094GEN_OP_SPE_STWWE(user);
7863667f
JM		 6095GEN_OP_SPE_STWWE(kernel);
6096GEN_OP_SPE_STWWE(hypv);
0487d6a8
JM		 6097#endif /* defined(CONFIG_USER_ONLY) */
6098GEN_SPEOP_ST(wwe, 2);
6099GEN_SPEOP_ST(wwo, 2);
6100
6101#define GEN_SPE_LDSPLAT(name, op, suffix) \
b068d6a7 6102static always_inline void gen_op_spe_l##name##_##suffix (void) \
0487d6a8
JM		 6103{ \
6104 gen_op_##op##_##suffix(); \
6105 gen_op_splatw_T1_64(); \
6106}
6107
6108#define GEN_OP_SPE_LHE(suffix) \
b068d6a7 6109static always_inline void gen_op_spe_lhe_##suffix (void) \
0487d6a8
JM		 6110{ \
6111 gen_op_spe_lh_##suffix(); \
6112 gen_op_sli16_T1_64(); \
6113}
6114
6115#define GEN_OP_SPE_LHX(suffix) \
b068d6a7 6116static always_inline void gen_op_spe_lhx_##suffix (void) \
0487d6a8
JM		 6117{ \
6118 gen_op_spe_lh_##suffix(); \
6119 gen_op_extsh_T1_64(); \
6120}
6121
6122#if defined(CONFIG_USER_ONLY)
6123GEN_OP_SPE_LHE(raw);
6124GEN_SPE_LDSPLAT(hhesplat, spe_lhe, raw);
6125GEN_OP_SPE_LHE(le_raw);
6126GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_raw);
6127GEN_SPE_LDSPLAT(hhousplat, spe_lh, raw);
6128GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_raw);
6129GEN_OP_SPE_LHX(raw);
6130GEN_SPE_LDSPLAT(hhossplat, spe_lhx, raw);
6131GEN_OP_SPE_LHX(le_raw);
6132GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_raw);
6133#if defined(TARGET_PPC64)
6134GEN_OP_SPE_LHE(64_raw);
6135GEN_SPE_LDSPLAT(hhesplat, spe_lhe, 64_raw);
6136GEN_OP_SPE_LHE(le_64_raw);
6137GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_64_raw);
6138GEN_SPE_LDSPLAT(hhousplat, spe_lh, 64_raw);
6139GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_64_raw);
6140GEN_OP_SPE_LHX(64_raw);
6141GEN_SPE_LDSPLAT(hhossplat, spe_lhx, 64_raw);
6142GEN_OP_SPE_LHX(le_64_raw);
6143GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_64_raw);
6144#endif
6145#else
0487d6a8 6146GEN_OP_SPE_LHE(user);
7863667f
JM		 6147GEN_OP_SPE_LHE(kernel);
6148GEN_OP_SPE_LHE(hypv);
0487d6a8 6149GEN_SPE_LDSPLAT(hhesplat, spe_lhe, user);
7863667f
JM		 6150GEN_SPE_LDSPLAT(hhesplat, spe_lhe, kernel);
6151GEN_SPE_LDSPLAT(hhesplat, spe_lhe, hypv);
0487d6a8 6152GEN_OP_SPE_LHE(le_user);
7863667f
JM		 6153GEN_OP_SPE_LHE(le_kernel);
6154GEN_OP_SPE_LHE(le_hypv);
0487d6a8 6155GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_user);
7863667f
JM		 6156GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_kernel);
6157GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_hypv);
0487d6a8 6158GEN_SPE_LDSPLAT(hhousplat, spe_lh, user);
7863667f
JM		 6159GEN_SPE_LDSPLAT(hhousplat, spe_lh, kernel);
6160GEN_SPE_LDSPLAT(hhousplat, spe_lh, hypv);
0487d6a8 6161GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_user);
7863667f
JM		 6162GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_kernel);
6163GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_hypv);
0487d6a8 6164GEN_OP_SPE_LHX(user);
7863667f
JM		 6165GEN_OP_SPE_LHX(kernel);
6166GEN_OP_SPE_LHX(hypv);
0487d6a8 6167GEN_SPE_LDSPLAT(hhossplat, spe_lhx, user);
7863667f
JM		 6168GEN_SPE_LDSPLAT(hhossplat, spe_lhx, kernel);
6169GEN_SPE_LDSPLAT(hhossplat, spe_lhx, hypv);
0487d6a8 6170GEN_OP_SPE_LHX(le_user);
7863667f
JM		 6171GEN_OP_SPE_LHX(le_kernel);
6172GEN_OP_SPE_LHX(le_hypv);
0487d6a8 6173GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_user);
7863667f
JM		 6174GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_kernel);
6175GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_hypv);
0487d6a8 6176#if defined(TARGET_PPC64)
0487d6a8 6177GEN_OP_SPE_LHE(64_user);
7863667f
JM		 6178GEN_OP_SPE_LHE(64_kernel);
6179GEN_OP_SPE_LHE(64_hypv);
0487d6a8 6180GEN_SPE_LDSPLAT(hhesplat, spe_lhe, 64_user);
7863667f
JM		 6181GEN_SPE_LDSPLAT(hhesplat, spe_lhe, 64_kernel);
6182GEN_SPE_LDSPLAT(hhesplat, spe_lhe, 64_hypv);
0487d6a8 6183GEN_OP_SPE_LHE(le_64_user);
7863667f
JM		 6184GEN_OP_SPE_LHE(le_64_kernel);
6185GEN_OP_SPE_LHE(le_64_hypv);
0487d6a8 6186GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_64_user);
7863667f
JM		 6187GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_64_kernel);
6188GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_64_hypv);
0487d6a8 6189GEN_SPE_LDSPLAT(hhousplat, spe_lh, 64_user);
7863667f
JM		 6190GEN_SPE_LDSPLAT(hhousplat, spe_lh, 64_kernel);
6191GEN_SPE_LDSPLAT(hhousplat, spe_lh, 64_hypv);
0487d6a8 6192GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_64_user);
7863667f
JM		 6193GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_64_kernel);
6194GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_64_hypv);
0487d6a8 6195GEN_OP_SPE_LHX(64_user);
7863667f
JM		 6196GEN_OP_SPE_LHX(64_kernel);
6197GEN_OP_SPE_LHX(64_hypv);
0487d6a8 6198GEN_SPE_LDSPLAT(hhossplat, spe_lhx, 64_user);
7863667f
JM		 6199GEN_SPE_LDSPLAT(hhossplat, spe_lhx, 64_kernel);
6200GEN_SPE_LDSPLAT(hhossplat, spe_lhx, 64_hypv);
0487d6a8 6201GEN_OP_SPE_LHX(le_64_user);
7863667f
JM		 6202GEN_OP_SPE_LHX(le_64_kernel);
6203GEN_OP_SPE_LHX(le_64_hypv);
0487d6a8 6204GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_64_user);
7863667f
JM		 6205GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_64_kernel);
6206GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_64_hypv);
0487d6a8
JM		 6207#endif
6208#endif
6209GEN_SPEOP_LD(hhesplat, 1);
6210GEN_SPEOP_LD(hhousplat, 1);
6211GEN_SPEOP_LD(hhossplat, 1);
6212GEN_SPEOP_LD(wwsplat, 2);
6213GEN_SPEOP_LD(whsplat, 2);
6214
6215GEN_SPE(evlddx, evldd, 0x00, 0x0C, 0x00000000, PPC_SPE); //
6216GEN_SPE(evldwx, evldw, 0x01, 0x0C, 0x00000000, PPC_SPE); //
6217GEN_SPE(evldhx, evldh, 0x02, 0x0C, 0x00000000, PPC_SPE); //
6218GEN_SPE(evlhhesplatx, evlhhesplat, 0x04, 0x0C, 0x00000000, PPC_SPE); //
6219GEN_SPE(evlhhousplatx, evlhhousplat, 0x06, 0x0C, 0x00000000, PPC_SPE); //
6220GEN_SPE(evlhhossplatx, evlhhossplat, 0x07, 0x0C, 0x00000000, PPC_SPE); //
6221GEN_SPE(evlwhex, evlwhe, 0x08, 0x0C, 0x00000000, PPC_SPE); //
6222GEN_SPE(evlwhoux, evlwhou, 0x0A, 0x0C, 0x00000000, PPC_SPE); //
6223GEN_SPE(evlwhosx, evlwhos, 0x0B, 0x0C, 0x00000000, PPC_SPE); //
6224GEN_SPE(evlwwsplatx, evlwwsplat, 0x0C, 0x0C, 0x00000000, PPC_SPE); //
6225GEN_SPE(evlwhsplatx, evlwhsplat, 0x0E, 0x0C, 0x00000000, PPC_SPE); //
6226GEN_SPE(evstddx, evstdd, 0x10, 0x0C, 0x00000000, PPC_SPE); //
6227GEN_SPE(evstdwx, evstdw, 0x11, 0x0C, 0x00000000, PPC_SPE); //
6228GEN_SPE(evstdhx, evstdh, 0x12, 0x0C, 0x00000000, PPC_SPE); //
6229GEN_SPE(evstwhex, evstwhe, 0x18, 0x0C, 0x00000000, PPC_SPE); //
6230GEN_SPE(evstwhox, evstwho, 0x1A, 0x0C, 0x00000000, PPC_SPE); //
6231GEN_SPE(evstwwex, evstwwe, 0x1C, 0x0C, 0x00000000, PPC_SPE); //
6232GEN_SPE(evstwwox, evstwwo, 0x1E, 0x0C, 0x00000000, PPC_SPE); //
6233
6234/* Multiply and add - TODO */
6235#if 0
6236GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0x00000000, PPC_SPE);
6237GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0x00000000, PPC_SPE);
6238GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, PPC_SPE);
6239GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0x00000000, PPC_SPE);
6240GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, PPC_SPE);
6241GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0x00000000, PPC_SPE);
6242GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0x00000000, PPC_SPE);
6243GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0x00000000, PPC_SPE);
6244GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, PPC_SPE);
6245GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0x00000000, PPC_SPE);
6246GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, PPC_SPE);
6247GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0x00000000, PPC_SPE);
6248
6249GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0x00000000, PPC_SPE);
6250GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, PPC_SPE);
6251GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, PPC_SPE);
6252GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0x00000000, PPC_SPE);
6253GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0x00000000, PPC_SPE);
6254GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, PPC_SPE);
6255GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0x00000000, PPC_SPE);
6256GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0x00000000, PPC_SPE);
6257GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, PPC_SPE);
6258GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, PPC_SPE);
6259GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0x00000000, PPC_SPE);
6260GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0x00000000, PPC_SPE);
6261GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, PPC_SPE);
6262GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0x00000000, PPC_SPE);
6263
6264GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, PPC_SPE);
6265GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, PPC_SPE);
6266GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, PPC_SPE);
6267GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, PPC_SPE);
6268GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, PPC_SPE);
6269GEN_SPE(evmra, speundef, 0x07, 0x13, 0x0000F800, PPC_SPE);
6270
6271GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, PPC_SPE);
6272GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0x00000000, PPC_SPE);
6273GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, PPC_SPE);
6274GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0x00000000, PPC_SPE);
6275GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, PPC_SPE);
6276GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0x00000000, PPC_SPE);
6277GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, PPC_SPE);
6278GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0x00000000, PPC_SPE);
6279GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, PPC_SPE);
6280GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0x00000000, PPC_SPE);
6281GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, PPC_SPE);
6282GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0x00000000, PPC_SPE);
6283
6284GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, PPC_SPE);
6285GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, PPC_SPE);
6286GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0x00000000, PPC_SPE);
6287GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, PPC_SPE);
6288GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0x00000000, PPC_SPE);
6289
6290GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, PPC_SPE);
6291GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0x00000000, PPC_SPE);
6292GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, PPC_SPE);
6293GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0x00000000, PPC_SPE);
6294GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, PPC_SPE);
6295GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0x00000000, PPC_SPE);
6296GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, PPC_SPE);
6297GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0x00000000, PPC_SPE);
6298GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, PPC_SPE);
6299GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0x00000000, PPC_SPE);
6300GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, PPC_SPE);
6301GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0x00000000, PPC_SPE);
6302
6303GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, PPC_SPE);
6304GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, PPC_SPE);
6305GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0x00000000, PPC_SPE);
6306GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, PPC_SPE);
6307GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0x00000000, PPC_SPE);
6308#endif
6309
6310/*** SPE floating-point extension ***/
6311#define GEN_SPEFPUOP_CONV(name) \
b068d6a7 6312static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8 6313{ \
f78fb44e 6314 gen_load_gpr64(cpu_T64[0], rB(ctx->opcode)); \
0487d6a8 6315 gen_op_##name(); \
f78fb44e 6316 gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]); \
0487d6a8
JM		 6317}
6318
6319/* Single precision floating-point vectors operations */
6320/* Arithmetic */
6321GEN_SPEOP_ARITH2(evfsadd);
6322GEN_SPEOP_ARITH2(evfssub);
6323GEN_SPEOP_ARITH2(evfsmul);
6324GEN_SPEOP_ARITH2(evfsdiv);
6325GEN_SPEOP_ARITH1(evfsabs);
6326GEN_SPEOP_ARITH1(evfsnabs);
6327GEN_SPEOP_ARITH1(evfsneg);
6328/* Conversion */
6329GEN_SPEFPUOP_CONV(evfscfui);
6330GEN_SPEFPUOP_CONV(evfscfsi);
6331GEN_SPEFPUOP_CONV(evfscfuf);
6332GEN_SPEFPUOP_CONV(evfscfsf);
6333GEN_SPEFPUOP_CONV(evfsctui);
6334GEN_SPEFPUOP_CONV(evfsctsi);
6335GEN_SPEFPUOP_CONV(evfsctuf);
6336GEN_SPEFPUOP_CONV(evfsctsf);
6337GEN_SPEFPUOP_CONV(evfsctuiz);
6338GEN_SPEFPUOP_CONV(evfsctsiz);
6339/* Comparison */
6340GEN_SPEOP_COMP(evfscmpgt);
6341GEN_SPEOP_COMP(evfscmplt);
6342GEN_SPEOP_COMP(evfscmpeq);
6343GEN_SPEOP_COMP(evfststgt);
6344GEN_SPEOP_COMP(evfststlt);
6345GEN_SPEOP_COMP(evfststeq);
6346
6347/* Opcodes definitions */
6348GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, PPC_SPEFPU); //
6349GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, PPC_SPEFPU); //
6350GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, PPC_SPEFPU); //
6351GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, PPC_SPEFPU); //
6352GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, PPC_SPEFPU); //
6353GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, PPC_SPEFPU); //
6354GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, PPC_SPEFPU); //
6355GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, PPC_SPEFPU); //
6356GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, PPC_SPEFPU); //
6357GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, PPC_SPEFPU); //
6358GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, PPC_SPEFPU); //
6359GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, PPC_SPEFPU); //
6360GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, PPC_SPEFPU); //
6361GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, PPC_SPEFPU); //
6362
6363/* Single precision floating-point operations */
6364/* Arithmetic */
6365GEN_SPEOP_ARITH2(efsadd);
6366GEN_SPEOP_ARITH2(efssub);
6367GEN_SPEOP_ARITH2(efsmul);
6368GEN_SPEOP_ARITH2(efsdiv);
6369GEN_SPEOP_ARITH1(efsabs);
6370GEN_SPEOP_ARITH1(efsnabs);
6371GEN_SPEOP_ARITH1(efsneg);
6372/* Conversion */
6373GEN_SPEFPUOP_CONV(efscfui);
6374GEN_SPEFPUOP_CONV(efscfsi);
6375GEN_SPEFPUOP_CONV(efscfuf);
6376GEN_SPEFPUOP_CONV(efscfsf);
6377GEN_SPEFPUOP_CONV(efsctui);
6378GEN_SPEFPUOP_CONV(efsctsi);
6379GEN_SPEFPUOP_CONV(efsctuf);
6380GEN_SPEFPUOP_CONV(efsctsf);
6381GEN_SPEFPUOP_CONV(efsctuiz);
6382GEN_SPEFPUOP_CONV(efsctsiz);
6383GEN_SPEFPUOP_CONV(efscfd);
6384/* Comparison */
6385GEN_SPEOP_COMP(efscmpgt);
6386GEN_SPEOP_COMP(efscmplt);
6387GEN_SPEOP_COMP(efscmpeq);
6388GEN_SPEOP_COMP(efststgt);
6389GEN_SPEOP_COMP(efststlt);
6390GEN_SPEOP_COMP(efststeq);
6391
6392/* Opcodes definitions */
05332d70 6393GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, PPC_SPEFPU); //
0487d6a8
JM		 6394GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, PPC_SPEFPU); //
6395GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, PPC_SPEFPU); //
6396GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, PPC_SPEFPU); //
6397GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, PPC_SPEFPU); //
6398GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, PPC_SPEFPU); //
6399GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, PPC_SPEFPU); //
6400GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, PPC_SPEFPU); //
6401GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, PPC_SPEFPU); //
6402GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, PPC_SPEFPU); //
9ceb2a77
TS		 6403GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, PPC_SPEFPU); //
6404GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, PPC_SPEFPU); //
0487d6a8
JM		 6405GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, PPC_SPEFPU); //
6406GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, PPC_SPEFPU); //
6407
6408/* Double precision floating-point operations */
6409/* Arithmetic */
6410GEN_SPEOP_ARITH2(efdadd);
6411GEN_SPEOP_ARITH2(efdsub);
6412GEN_SPEOP_ARITH2(efdmul);
6413GEN_SPEOP_ARITH2(efddiv);
6414GEN_SPEOP_ARITH1(efdabs);
6415GEN_SPEOP_ARITH1(efdnabs);
6416GEN_SPEOP_ARITH1(efdneg);
6417/* Conversion */
6418
6419GEN_SPEFPUOP_CONV(efdcfui);
6420GEN_SPEFPUOP_CONV(efdcfsi);
6421GEN_SPEFPUOP_CONV(efdcfuf);
6422GEN_SPEFPUOP_CONV(efdcfsf);
6423GEN_SPEFPUOP_CONV(efdctui);
6424GEN_SPEFPUOP_CONV(efdctsi);
6425GEN_SPEFPUOP_CONV(efdctuf);
6426GEN_SPEFPUOP_CONV(efdctsf);
6427GEN_SPEFPUOP_CONV(efdctuiz);
6428GEN_SPEFPUOP_CONV(efdctsiz);
6429GEN_SPEFPUOP_CONV(efdcfs);
6430GEN_SPEFPUOP_CONV(efdcfuid);
6431GEN_SPEFPUOP_CONV(efdcfsid);
6432GEN_SPEFPUOP_CONV(efdctuidz);
6433GEN_SPEFPUOP_CONV(efdctsidz);
6434/* Comparison */
6435GEN_SPEOP_COMP(efdcmpgt);
6436GEN_SPEOP_COMP(efdcmplt);
6437GEN_SPEOP_COMP(efdcmpeq);
6438GEN_SPEOP_COMP(efdtstgt);
6439GEN_SPEOP_COMP(efdtstlt);
6440GEN_SPEOP_COMP(efdtsteq);
6441
6442/* Opcodes definitions */
6443GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, PPC_SPEFPU); //
6444GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, PPC_SPEFPU); //
6445GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, PPC_SPEFPU); //
6446GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, PPC_SPEFPU); //
6447GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, PPC_SPEFPU); //
6448GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, PPC_SPEFPU); //
6449GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, PPC_SPEFPU); //
6450GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, PPC_SPEFPU); //
6451GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, PPC_SPEFPU); //
6452GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, PPC_SPEFPU); //
6453GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, PPC_SPEFPU); //
6454GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, PPC_SPEFPU); //
6455GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, PPC_SPEFPU); //
6456GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, PPC_SPEFPU); //
6457GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, PPC_SPEFPU); //
6458GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, PPC_SPEFPU); //
0487d6a8 6459
79aceca5
FB		 6460/* End opcode list */
6461GEN_OPCODE_MARK(end);
6462
3fc6c082 6463#include "translate_init.c"
0411a972 6464#include "helper_regs.h"
79aceca5 6465
9a64fbe4 6466/*****************************************************************************/
3fc6c082 6467/* Misc PowerPC helpers */
36081602
JM		 6468void cpu_dump_state (CPUState *env, FILE *f,
6469 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
6470 int flags)
79aceca5 6471{
3fc6c082
FB		 6472#define RGPL 4
6473#define RFPL 4
3fc6c082 6474
79aceca5
FB		 6475 int i;
6476
077fc206 6477 cpu_fprintf(f, "NIP " ADDRX " LR " ADDRX " CTR " ADDRX " XER %08x\n",
3d7b417e 6478 env->nip, env->lr, env->ctr, env->xer);
6b542af7
JM		 6479 cpu_fprintf(f, "MSR " ADDRX " HID0 " ADDRX " HF " ADDRX " idx %d\n",
6480 env->msr, env->spr[SPR_HID0], env->hflags, env->mmu_idx);
d9bce9d9 6481#if !defined(NO_TIMER_DUMP)
077fc206 6482 cpu_fprintf(f, "TB %08x %08x "
76a66253
JM		 6483#if !defined(CONFIG_USER_ONLY)
6484 "DECR %08x"
6485#endif
6486 "\n",
077fc206 6487 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
76a66253
JM		 6488#if !defined(CONFIG_USER_ONLY)
6489 , cpu_ppc_load_decr(env)
6490#endif
6491 );
077fc206 6492#endif
76a66253 6493 for (i = 0; i < 32; i++) {
3fc6c082
FB		 6494 if ((i & (RGPL - 1)) == 0)
6495 cpu_fprintf(f, "GPR%02d", i);
6b542af7 6496 cpu_fprintf(f, " " REGX, ppc_dump_gpr(env, i));
3fc6c082 6497 if ((i & (RGPL - 1)) == (RGPL - 1))
7fe48483 6498 cpu_fprintf(f, "\n");
76a66253 6499 }
3fc6c082 6500 cpu_fprintf(f, "CR ");
76a66253 6501 for (i = 0; i < 8; i++)
7fe48483
FB		 6502 cpu_fprintf(f, "%01x", env->crf[i]);
6503 cpu_fprintf(f, " [");
76a66253
JM		 6504 for (i = 0; i < 8; i++) {
6505 char a = '-';
6506 if (env->crf[i] & 0x08)
6507 a = 'L';
6508 else if (env->crf[i] & 0x04)
6509 a = 'G';
6510 else if (env->crf[i] & 0x02)
6511 a = 'E';
7fe48483 6512 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
76a66253 6513 }
6b542af7 6514 cpu_fprintf(f, " ] RES " ADDRX "\n", env->reserve);
3fc6c082
FB		 6515 for (i = 0; i < 32; i++) {
6516 if ((i & (RFPL - 1)) == 0)
6517 cpu_fprintf(f, "FPR%02d", i);
26a76461 6518 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
3fc6c082 6519 if ((i & (RFPL - 1)) == (RFPL - 1))
7fe48483 6520 cpu_fprintf(f, "\n");
79aceca5 6521 }
f2e63a42 6522#if !defined(CONFIG_USER_ONLY)
6b542af7 6523 cpu_fprintf(f, "SRR0 " ADDRX " SRR1 " ADDRX " SDR1 " ADDRX "\n",
3fc6c082 6524 env->spr[SPR_SRR0], env->spr[SPR_SRR1], env->sdr1);
f2e63a42 6525#endif
79aceca5 6526
3fc6c082
FB		 6527#undef RGPL
6528#undef RFPL
79aceca5
FB		 6529}
6530
76a66253
JM		 6531void cpu_dump_statistics (CPUState *env, FILE*f,
6532 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
6533 int flags)
6534{
6535#if defined(DO_PPC_STATISTICS)
6536 opc_handler_t **t1, **t2, **t3, *handler;
6537 int op1, op2, op3;
6538
6539 t1 = env->opcodes;
6540 for (op1 = 0; op1 < 64; op1++) {
6541 handler = t1[op1];
6542 if (is_indirect_opcode(handler)) {
6543 t2 = ind_table(handler);
6544 for (op2 = 0; op2 < 32; op2++) {
6545 handler = t2[op2];
6546 if (is_indirect_opcode(handler)) {
6547 t3 = ind_table(handler);
6548 for (op3 = 0; op3 < 32; op3++) {
6549 handler = t3[op3];
6550 if (handler->count == 0)
6551 continue;
6552 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
6553 "%016llx %lld\n",
6554 op1, op2, op3, op1, (op3 << 5) | op2,
6555 handler->oname,
6556 handler->count, handler->count);
6557 }
6558 } else {
6559 if (handler->count == 0)
6560 continue;
6561 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
6562 "%016llx %lld\n",
6563 op1, op2, op1, op2, handler->oname,
6564 handler->count, handler->count);
6565 }
6566 }
6567 } else {
6568 if (handler->count == 0)
6569 continue;
6570 cpu_fprintf(f, "%02x (%02x ) %16s: %016llx %lld\n",
6571 op1, op1, handler->oname,
6572 handler->count, handler->count);
6573 }
6574 }
6575#endif
6576}
6577
9a64fbe4 6578/*****************************************************************************/
2cfc5f17
TS		 6579static always_inline void gen_intermediate_code_internal (CPUState *env,
6580 TranslationBlock *tb,
6581 int search_pc)
79aceca5 6582{
9fddaa0c 6583 DisasContext ctx, *ctxp = &ctx;
79aceca5 6584 opc_handler_t **table, *handler;
0fa85d43 6585 target_ulong pc_start;
79aceca5 6586 uint16_t *gen_opc_end;
056401ea 6587 int supervisor, little_endian;
79aceca5 6588 int j, lj = -1;
2e70f6ef
PB		 6589 int num_insns;
6590 int max_insns;
79aceca5
FB		 6591
6592 pc_start = tb->pc;
79aceca5 6593 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
7c58044c
JM		 6594#if defined(OPTIMIZE_FPRF_UPDATE)
6595 gen_fprf_ptr = gen_fprf_buf;
6596#endif
046d6672 6597 ctx.nip = pc_start;
79aceca5 6598 ctx.tb = tb;
e1833e1f 6599 ctx.exception = POWERPC_EXCP_NONE;
3fc6c082 6600 ctx.spr_cb = env->spr_cb;
6ebbf390
JM		 6601 supervisor = env->mmu_idx;
6602#if !defined(CONFIG_USER_ONLY)
2857068e 6603 ctx.supervisor = supervisor;
d9bce9d9 6604#endif
056401ea 6605 little_endian = env->hflags & (1 << MSR_LE) ? 1 : 0;
d9bce9d9
JM		 6606#if defined(TARGET_PPC64)
6607 ctx.sf_mode = msr_sf;
056401ea 6608 ctx.mem_idx = (supervisor << 2) | (msr_sf << 1) | little_endian;
2857068e 6609#else
056401ea 6610 ctx.mem_idx = (supervisor << 1) | little_endian;
9a64fbe4 6611#endif
d63001d1 6612 ctx.dcache_line_size = env->dcache_line_size;
3cc62370 6613 ctx.fpu_enabled = msr_fp;
a9d9eb8f 6614 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
d26bfc9a
JM		 6615 ctx.spe_enabled = msr_spe;
6616 else
6617 ctx.spe_enabled = 0;
a9d9eb8f
JM		 6618 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
6619 ctx.altivec_enabled = msr_vr;
6620 else
6621 ctx.altivec_enabled = 0;
d26bfc9a 6622 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
8cbcb4fa 6623 ctx.singlestep_enabled = CPU_SINGLE_STEP;
d26bfc9a 6624 else
8cbcb4fa 6625 ctx.singlestep_enabled = 0;
d26bfc9a 6626 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
8cbcb4fa
AJ		 6627 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
6628 if (unlikely(env->singlestep_enabled))
6629 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
3fc6c082 6630#if defined (DO_SINGLE_STEP) && 0
9a64fbe4
FB		 6631 /* Single step trace mode */
6632 msr_se = 1;
6633#endif
2e70f6ef
PB		 6634 num_insns = 0;
6635 max_insns = tb->cflags & CF_COUNT_MASK;
6636 if (max_insns == 0)
6637 max_insns = CF_COUNT_MASK;
6638
6639 gen_icount_start();
9a64fbe4 6640 /* Set env in case of segfault during code fetch */
e1833e1f 6641 while (ctx.exception == POWERPC_EXCP_NONE && gen_opc_ptr < gen_opc_end) {
76a66253
JM		 6642 if (unlikely(env->nb_breakpoints > 0)) {
6643 for (j = 0; j < env->nb_breakpoints; j++) {
ea4e754f 6644 if (env->breakpoints[j] == ctx.nip) {
5fafdf24 6645 gen_update_nip(&ctx, ctx.nip);
ea4e754f
FB		 6646 gen_op_debug();
6647 break;
6648 }
6649 }
6650 }
76a66253 6651 if (unlikely(search_pc)) {
79aceca5
FB		 6652 j = gen_opc_ptr - gen_opc_buf;
6653 if (lj < j) {
6654 lj++;
6655 while (lj < j)
6656 gen_opc_instr_start[lj++] = 0;
046d6672 6657 gen_opc_pc[lj] = ctx.nip;
79aceca5 6658 gen_opc_instr_start[lj] = 1;
2e70f6ef 6659 gen_opc_icount[lj] = num_insns;
79aceca5
FB		 6660 }
6661 }
9fddaa0c
FB		 6662#if defined PPC_DEBUG_DISAS
6663 if (loglevel & CPU_LOG_TB_IN_ASM) {
79aceca5 6664 fprintf(logfile, "----------------\n");
1b9eb036 6665 fprintf(logfile, "nip=" ADDRX " super=%d ir=%d\n",
0411a972 6666 ctx.nip, supervisor, (int)msr_ir);
9a64fbe4
FB		 6667 }
6668#endif
2e70f6ef
PB		 6669 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
6670 gen_io_start();
056401ea
JM		 6671 if (unlikely(little_endian)) {
6672 ctx.opcode = bswap32(ldl_code(ctx.nip));
6673 } else {
6674 ctx.opcode = ldl_code(ctx.nip);
111bfab3 6675 }
9fddaa0c
FB		 6676#if defined PPC_DEBUG_DISAS
6677 if (loglevel & CPU_LOG_TB_IN_ASM) {
111bfab3 6678 fprintf(logfile, "translate opcode %08x (%02x %02x %02x) (%s)\n",
9a64fbe4 6679 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
056401ea 6680 opc3(ctx.opcode), little_endian ? "little" : "big");
79aceca5
FB		 6681 }
6682#endif
046d6672 6683 ctx.nip += 4;
3fc6c082 6684 table = env->opcodes;
2e70f6ef 6685 num_insns++;
79aceca5
FB		 6686 handler = table[opc1(ctx.opcode)];
6687 if (is_indirect_opcode(handler)) {
6688 table = ind_table(handler);
6689 handler = table[opc2(ctx.opcode)];
6690 if (is_indirect_opcode(handler)) {
6691 table = ind_table(handler);
6692 handler = table[opc3(ctx.opcode)];
6693 }
6694 }
6695 /* Is opcode *REALLY* valid ? */
76a66253 6696 if (unlikely(handler->handler == &gen_invalid)) {
4a057712 6697 if (loglevel != 0) {
76a66253 6698 fprintf(logfile, "invalid/unsupported opcode: "
6b542af7 6699 "%02x - %02x - %02x (%08x) " ADDRX " %d\n",
76a66253 6700 opc1(ctx.opcode), opc2(ctx.opcode),
0411a972 6701 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
4b3686fa
FB		 6702 } else {
6703 printf("invalid/unsupported opcode: "
6b542af7 6704 "%02x - %02x - %02x (%08x) " ADDRX " %d\n",
4b3686fa 6705 opc1(ctx.opcode), opc2(ctx.opcode),
0411a972 6706 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
4b3686fa 6707 }
76a66253
JM		 6708 } else {
6709 if (unlikely((ctx.opcode & handler->inval) != 0)) {
4a057712 6710 if (loglevel != 0) {
79aceca5 6711 fprintf(logfile, "invalid bits: %08x for opcode: "
6b542af7 6712 "%02x - %02x - %02x (%08x) " ADDRX "\n",
79aceca5
FB		 6713 ctx.opcode & handler->inval, opc1(ctx.opcode),
6714 opc2(ctx.opcode), opc3(ctx.opcode),
046d6672 6715 ctx.opcode, ctx.nip - 4);
9a64fbe4
FB		 6716 } else {
6717 printf("invalid bits: %08x for opcode: "
6b542af7 6718 "%02x - %02x - %02x (%08x) " ADDRX "\n",
76a66253
JM		 6719 ctx.opcode & handler->inval, opc1(ctx.opcode),
6720 opc2(ctx.opcode), opc3(ctx.opcode),
046d6672 6721 ctx.opcode, ctx.nip - 4);
76a66253 6722 }
e1833e1f 6723 GEN_EXCP_INVAL(ctxp);
4b3686fa 6724 break;
79aceca5 6725 }
79aceca5 6726 }
4b3686fa 6727 (*(handler->handler))(&ctx);
76a66253
JM		 6728#if defined(DO_PPC_STATISTICS)
6729 handler->count++;
6730#endif
9a64fbe4 6731 /* Check trace mode exceptions */
8cbcb4fa
AJ		 6732 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
6733 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
6734 ctx.exception != POWERPC_SYSCALL &&
6735 ctx.exception != POWERPC_EXCP_TRAP &&
6736 ctx.exception != POWERPC_EXCP_BRANCH)) {
e1833e1f 6737 GEN_EXCP(ctxp, POWERPC_EXCP_TRACE, 0);
d26bfc9a 6738 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
2e70f6ef
PB		 6739 (env->singlestep_enabled) ||
6740 num_insns >= max_insns)) {
d26bfc9a
JM		 6741 /* if we reach a page boundary or are single stepping, stop
6742 * generation
6743 */
8dd4983c 6744 break;
76a66253 6745 }
3fc6c082
FB		 6746#if defined (DO_SINGLE_STEP)
6747 break;
6748#endif
6749 }
2e70f6ef
PB		 6750 if (tb->cflags & CF_LAST_IO)
6751 gen_io_end();
e1833e1f 6752 if (ctx.exception == POWERPC_EXCP_NONE) {
c1942362 6753 gen_goto_tb(&ctx, 0, ctx.nip);
e1833e1f 6754 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
8cbcb4fa
AJ		 6755 if (unlikely(env->singlestep_enabled)) {
6756 gen_update_nip(&ctx, ctx.nip);
6757 gen_op_debug();
6758 }
76a66253 6759 /* Generate the return instruction */
57fec1fe 6760 tcg_gen_exit_tb(0);
9a64fbe4 6761 }
2e70f6ef 6762 gen_icount_end(tb, num_insns);
79aceca5 6763 *gen_opc_ptr = INDEX_op_end;
76a66253 6764 if (unlikely(search_pc)) {
9a64fbe4
FB		 6765 j = gen_opc_ptr - gen_opc_buf;
6766 lj++;
6767 while (lj <= j)
6768 gen_opc_instr_start[lj++] = 0;
9a64fbe4 6769 } else {
046d6672 6770 tb->size = ctx.nip - pc_start;
2e70f6ef 6771 tb->icount = num_insns;
9a64fbe4 6772 }
d9bce9d9 6773#if defined(DEBUG_DISAS)
9fddaa0c 6774 if (loglevel & CPU_LOG_TB_CPU) {
9a64fbe4 6775 fprintf(logfile, "---------------- excp: %04x\n", ctx.exception);
7fe48483 6776 cpu_dump_state(env, logfile, fprintf, 0);
9fddaa0c
FB		 6777 }
6778 if (loglevel & CPU_LOG_TB_IN_ASM) {
76a66253 6779 int flags;
237c0af0 6780 flags = env->bfd_mach;
056401ea 6781 flags |= little_endian << 16;
0fa85d43 6782 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
76a66253 6783 target_disas(logfile, pc_start, ctx.nip - pc_start, flags);
79aceca5 6784 fprintf(logfile, "\n");
9fddaa0c 6785 }
79aceca5 6786#endif
79aceca5
FB		 6787}
6788
2cfc5f17 6789void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
79aceca5 6790{
2cfc5f17 6791 gen_intermediate_code_internal(env, tb, 0);
79aceca5
FB		 6792}
6793
2cfc5f17 6794void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
79aceca5 6795{
2cfc5f17 6796 gen_intermediate_code_internal(env, tb, 1);
79aceca5 6797}
d2856f1a
AJ		 6798
6799void gen_pc_load(CPUState *env, TranslationBlock *tb,
6800 unsigned long searched_pc, int pc_pos, void *puc)
6801{
6802 int type, c;
6803 /* for PPC, we need to look at the micro operation to get the
6804 * access type */
6805 env->nip = gen_opc_pc[pc_pos];
6806 c = gen_opc_buf[pc_pos];
6807 switch(c) {
6808#if defined(CONFIG_USER_ONLY)
6809#define CASE3(op)\
6810 case INDEX_op_ ## op ## _raw
6811#else
6812#define CASE3(op)\
6813 case INDEX_op_ ## op ## _user:\
6814 case INDEX_op_ ## op ## _kernel:\
6815 case INDEX_op_ ## op ## _hypv
6816#endif
6817
6818 CASE3(stfd):
6819 CASE3(stfs):
6820 CASE3(lfd):
6821 CASE3(lfs):
6822 type = ACCESS_FLOAT;
6823 break;
6824 CASE3(lwarx):
6825 type = ACCESS_RES;
6826 break;
6827 CASE3(stwcx):
6828 type = ACCESS_RES;
6829 break;
6830 CASE3(eciwx):
6831 CASE3(ecowx):
6832 type = ACCESS_EXT;
6833 break;
6834 default:
6835 type = ACCESS_INT;
6836 break;
6837 }
6838 env->access_type = type;
6839}
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