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[qemu.git] / hw / display / cirrus_vga.c
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e6e5ad80 1/*
aeb3c85f 2 * QEMU Cirrus CLGD 54xx VGA Emulator.
5fafdf24 3 *
e6e5ad80 4 * Copyright (c) 2004 Fabrice Bellard
aeb3c85f 5 * Copyright (c) 2004 Makoto Suzuki (suzu)
5fafdf24 6 *
e6e5ad80
FB		 7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
aeb3c85f
FB		 25/*
26 * Reference: Finn Thogersons' VGADOC4b
27 * available at http://home.worldonline.dk/~finth/
28 */
83c9f4ca
PB		 29#include "hw/hw.h"
30#include "hw/pci/pci.h"
28ecbaee 31#include "ui/console.h"
47b43a1f 32#include "vga_int.h"
83c9f4ca 33#include "hw/loader.h"
e6e5ad80 34
a5082316
FB		 35/*
36 * TODO:
ad81218e 37 * - destination write mask support not complete (bits 5..7)
a5082316
FB		 38 * - optimize linear mappings
39 * - optimize bitblt functions
40 */
41
e36f36e1 42//#define DEBUG_CIRRUS
a21ae81d 43//#define DEBUG_BITBLT
e36f36e1 44
e6e5ad80
FB		 45/***************************************
46 *
47 * definitions
48 *
49 ***************************************/
50
e6e5ad80
FB		 51// ID
52#define CIRRUS_ID_CLGD5422 (0x23<<2)
53#define CIRRUS_ID_CLGD5426 (0x24<<2)
54#define CIRRUS_ID_CLGD5424 (0x25<<2)
55#define CIRRUS_ID_CLGD5428 (0x26<<2)
56#define CIRRUS_ID_CLGD5430 (0x28<<2)
57#define CIRRUS_ID_CLGD5434 (0x2A<<2)
a21ae81d 58#define CIRRUS_ID_CLGD5436 (0x2B<<2)
e6e5ad80
FB		 59#define CIRRUS_ID_CLGD5446 (0x2E<<2)
60
61// sequencer 0x07
62#define CIRRUS_SR7_BPP_VGA 0x00
63#define CIRRUS_SR7_BPP_SVGA 0x01
64#define CIRRUS_SR7_BPP_MASK 0x0e
65#define CIRRUS_SR7_BPP_8 0x00
66#define CIRRUS_SR7_BPP_16_DOUBLEVCLK 0x02
67#define CIRRUS_SR7_BPP_24 0x04
68#define CIRRUS_SR7_BPP_16 0x06
69#define CIRRUS_SR7_BPP_32 0x08
70#define CIRRUS_SR7_ISAADDR_MASK 0xe0
71
72// sequencer 0x0f
73#define CIRRUS_MEMSIZE_512k 0x08
74#define CIRRUS_MEMSIZE_1M 0x10
75#define CIRRUS_MEMSIZE_2M 0x18
76#define CIRRUS_MEMFLAGS_BANKSWITCH 0x80 // bank switching is enabled.
77
78// sequencer 0x12
79#define CIRRUS_CURSOR_SHOW 0x01
80#define CIRRUS_CURSOR_HIDDENPEL 0x02
81#define CIRRUS_CURSOR_LARGE 0x04 // 64x64 if set, 32x32 if clear
82
83// sequencer 0x17
84#define CIRRUS_BUSTYPE_VLBFAST 0x10
85#define CIRRUS_BUSTYPE_PCI 0x20
86#define CIRRUS_BUSTYPE_VLBSLOW 0x30
87#define CIRRUS_BUSTYPE_ISA 0x38
88#define CIRRUS_MMIO_ENABLE 0x04
89#define CIRRUS_MMIO_USE_PCIADDR 0x40 // 0xb8000 if cleared.
90#define CIRRUS_MEMSIZEEXT_DOUBLE 0x80
91
92// control 0x0b
93#define CIRRUS_BANKING_DUAL 0x01
94#define CIRRUS_BANKING_GRANULARITY_16K 0x20 // set:16k, clear:4k
95
96// control 0x30
97#define CIRRUS_BLTMODE_BACKWARDS 0x01
98#define CIRRUS_BLTMODE_MEMSYSDEST 0x02
99#define CIRRUS_BLTMODE_MEMSYSSRC 0x04
100#define CIRRUS_BLTMODE_TRANSPARENTCOMP 0x08
101#define CIRRUS_BLTMODE_PATTERNCOPY 0x40
102#define CIRRUS_BLTMODE_COLOREXPAND 0x80
103#define CIRRUS_BLTMODE_PIXELWIDTHMASK 0x30
104#define CIRRUS_BLTMODE_PIXELWIDTH8 0x00
105#define CIRRUS_BLTMODE_PIXELWIDTH16 0x10
106#define CIRRUS_BLTMODE_PIXELWIDTH24 0x20
107#define CIRRUS_BLTMODE_PIXELWIDTH32 0x30
108
109// control 0x31
110#define CIRRUS_BLT_BUSY 0x01
111#define CIRRUS_BLT_START 0x02
112#define CIRRUS_BLT_RESET 0x04
113#define CIRRUS_BLT_FIFOUSED 0x10
a5082316 114#define CIRRUS_BLT_AUTOSTART 0x80
e6e5ad80
FB		 115
116// control 0x32
117#define CIRRUS_ROP_0 0x00
118#define CIRRUS_ROP_SRC_AND_DST 0x05
119#define CIRRUS_ROP_NOP 0x06
120#define CIRRUS_ROP_SRC_AND_NOTDST 0x09
121#define CIRRUS_ROP_NOTDST 0x0b
122#define CIRRUS_ROP_SRC 0x0d
123#define CIRRUS_ROP_1 0x0e
124#define CIRRUS_ROP_NOTSRC_AND_DST 0x50
125#define CIRRUS_ROP_SRC_XOR_DST 0x59
126#define CIRRUS_ROP_SRC_OR_DST 0x6d
127#define CIRRUS_ROP_NOTSRC_OR_NOTDST 0x90
128#define CIRRUS_ROP_SRC_NOTXOR_DST 0x95
129#define CIRRUS_ROP_SRC_OR_NOTDST 0xad
130#define CIRRUS_ROP_NOTSRC 0xd0
131#define CIRRUS_ROP_NOTSRC_OR_DST 0xd6
132#define CIRRUS_ROP_NOTSRC_AND_NOTDST 0xda
133
a5082316
FB		 134#define CIRRUS_ROP_NOP_INDEX 2
135#define CIRRUS_ROP_SRC_INDEX 5
136
a21ae81d 137// control 0x33
a5082316 138#define CIRRUS_BLTMODEEXT_SOLIDFILL 0x04
4c8732d7 139#define CIRRUS_BLTMODEEXT_COLOREXPINV 0x02
a5082316 140#define CIRRUS_BLTMODEEXT_DWORDGRANULARITY 0x01
a21ae81d 141
e6e5ad80
FB		 142// memory-mapped IO
143#define CIRRUS_MMIO_BLTBGCOLOR 0x00 // dword
144#define CIRRUS_MMIO_BLTFGCOLOR 0x04 // dword
145#define CIRRUS_MMIO_BLTWIDTH 0x08 // word
146#define CIRRUS_MMIO_BLTHEIGHT 0x0a // word
147#define CIRRUS_MMIO_BLTDESTPITCH 0x0c // word
148#define CIRRUS_MMIO_BLTSRCPITCH 0x0e // word
149#define CIRRUS_MMIO_BLTDESTADDR 0x10 // dword
150#define CIRRUS_MMIO_BLTSRCADDR 0x14 // dword
151#define CIRRUS_MMIO_BLTWRITEMASK 0x17 // byte
152#define CIRRUS_MMIO_BLTMODE 0x18 // byte
153#define CIRRUS_MMIO_BLTROP 0x1a // byte
154#define CIRRUS_MMIO_BLTMODEEXT 0x1b // byte
155#define CIRRUS_MMIO_BLTTRANSPARENTCOLOR 0x1c // word?
156#define CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK 0x20 // word?
157#define CIRRUS_MMIO_LINEARDRAW_START_X 0x24 // word
158#define CIRRUS_MMIO_LINEARDRAW_START_Y 0x26 // word
159#define CIRRUS_MMIO_LINEARDRAW_END_X 0x28 // word
160#define CIRRUS_MMIO_LINEARDRAW_END_Y 0x2a // word
161#define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_INC 0x2c // byte
162#define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ROLLOVER 0x2d // byte
163#define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_MASK 0x2e // byte
164#define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ACCUM 0x2f // byte
165#define CIRRUS_MMIO_BRESENHAM_K1 0x30 // word
166#define CIRRUS_MMIO_BRESENHAM_K3 0x32 // word
167#define CIRRUS_MMIO_BRESENHAM_ERROR 0x34 // word
168#define CIRRUS_MMIO_BRESENHAM_DELTA_MAJOR 0x36 // word
169#define CIRRUS_MMIO_BRESENHAM_DIRECTION 0x38 // byte
170#define CIRRUS_MMIO_LINEDRAW_MODE 0x39 // byte
171#define CIRRUS_MMIO_BLTSTATUS 0x40 // byte
172
a21ae81d 173#define CIRRUS_PNPMMIO_SIZE 0x1000
e6e5ad80 174
b2eb849d
AJ		 175#define BLTUNSAFE(s) \
176 ( \
177 ( /* check dst is within bounds */ \
b2b183c2 178 (s)->cirrus_blt_height * ABS((s)->cirrus_blt_dstpitch) \
b2eb849d 179 + ((s)->cirrus_blt_dstaddr & (s)->cirrus_addr_mask) > \
4e12cd94 180 (s)->vga.vram_size \
b2eb849d
AJ		 181 ) || \
182 ( /* check src is within bounds */ \
b2b183c2 183 (s)->cirrus_blt_height * ABS((s)->cirrus_blt_srcpitch) \
b2eb849d 184 + ((s)->cirrus_blt_srcaddr & (s)->cirrus_addr_mask) > \
4e12cd94 185 (s)->vga.vram_size \
b2eb849d
AJ		 186 ) \
187 )
188
a5082316
FB		 189struct CirrusVGAState;
190typedef void (*cirrus_bitblt_rop_t) (struct CirrusVGAState *s,
191 uint8_t * dst, const uint8_t * src,
e6e5ad80
FB		 192 int dstpitch, int srcpitch,
193 int bltwidth, int bltheight);
a5082316
FB		 194typedef void (*cirrus_fill_t)(struct CirrusVGAState *s,
195 uint8_t *dst, int dst_pitch, int width, int height);
e6e5ad80
FB		 196
197typedef struct CirrusVGAState {
4e12cd94 198 VGACommonState vga;
e6e5ad80 199
c75e6d8e 200 MemoryRegion cirrus_vga_io;
b1950430
AK		 201 MemoryRegion cirrus_linear_io;
202 MemoryRegion cirrus_linear_bitblt_io;
203 MemoryRegion cirrus_mmio_io;
204 MemoryRegion pci_bar;
205 bool linear_vram; /* vga.vram mapped over cirrus_linear_io */
206 MemoryRegion low_mem_container; /* container for 0xa0000-0xc0000 */
207 MemoryRegion low_mem; /* always mapped, overridden by: */
7969d9ed 208 MemoryRegion cirrus_bank[2]; /* aliases at 0xa0000-0xb0000 */
e6e5ad80 209 uint32_t cirrus_addr_mask;
78e127ef 210 uint32_t linear_mmio_mask;
e6e5ad80
FB		 211 uint8_t cirrus_shadow_gr0;
212 uint8_t cirrus_shadow_gr1;
213 uint8_t cirrus_hidden_dac_lockindex;
214 uint8_t cirrus_hidden_dac_data;
215 uint32_t cirrus_bank_base[2];
216 uint32_t cirrus_bank_limit[2];
217 uint8_t cirrus_hidden_palette[48];
a5082316
FB		 218 uint32_t hw_cursor_x;
219 uint32_t hw_cursor_y;
e6e5ad80
FB		 220 int cirrus_blt_pixelwidth;
221 int cirrus_blt_width;
222 int cirrus_blt_height;
223 int cirrus_blt_dstpitch;
224 int cirrus_blt_srcpitch;
a5082316
FB		 225 uint32_t cirrus_blt_fgcol;
226 uint32_t cirrus_blt_bgcol;
e6e5ad80
FB		 227 uint32_t cirrus_blt_dstaddr;
228 uint32_t cirrus_blt_srcaddr;
229 uint8_t cirrus_blt_mode;
a5082316 230 uint8_t cirrus_blt_modeext;
e6e5ad80 231 cirrus_bitblt_rop_t cirrus_rop;
a5082316 232#define CIRRUS_BLTBUFSIZE (2048 * 4) /* one line width */
e6e5ad80
FB		 233 uint8_t cirrus_bltbuf[CIRRUS_BLTBUFSIZE];
234 uint8_t *cirrus_srcptr;
235 uint8_t *cirrus_srcptr_end;
236 uint32_t cirrus_srccounter;
a5082316
FB		 237 /* hwcursor display state */
238 int last_hw_cursor_size;
239 int last_hw_cursor_x;
240 int last_hw_cursor_y;
241 int last_hw_cursor_y_start;
242 int last_hw_cursor_y_end;
78e127ef 243 int real_vram_size; /* XXX: suppress that */
4abc796d
BS		 244 int device_id;
245 int bustype;
e6e5ad80
FB		 246} CirrusVGAState;
247
248typedef struct PCICirrusVGAState {
249 PCIDevice dev;
250 CirrusVGAState cirrus_vga;
251} PCICirrusVGAState;
252
3d402831
BS		 253typedef struct ISACirrusVGAState {
254 ISADevice dev;
255 CirrusVGAState cirrus_vga;
256} ISACirrusVGAState;
257
a5082316 258static uint8_t rop_to_index[256];
3b46e624 259
e6e5ad80
FB		 260/***************************************
261 *
262 * prototypes.
263 *
264 ***************************************/
265
266
8926b517
FB		 267static void cirrus_bitblt_reset(CirrusVGAState *s);
268static void cirrus_update_memory_access(CirrusVGAState *s);
e6e5ad80
FB		 269
270/***************************************
271 *
272 * raster operations
273 *
274 ***************************************/
275
a5082316
FB		 276static void cirrus_bitblt_rop_nop(CirrusVGAState *s,
277 uint8_t *dst,const uint8_t *src,
278 int dstpitch,int srcpitch,
279 int bltwidth,int bltheight)
280{
e6e5ad80
FB		 281}
282
a5082316
FB		 283static void cirrus_bitblt_fill_nop(CirrusVGAState *s,
284 uint8_t *dst,
285 int dstpitch, int bltwidth,int bltheight)
e6e5ad80 286{
a5082316 287}
e6e5ad80 288
a5082316 289#define ROP_NAME 0
8c78881f 290#define ROP_FN(d, s) 0
47b43a1f 291#include "cirrus_vga_rop.h"
e6e5ad80 292
a5082316 293#define ROP_NAME src_and_dst
8c78881f 294#define ROP_FN(d, s) (s) & (d)
47b43a1f 295#include "cirrus_vga_rop.h"
e6e5ad80 296
a5082316 297#define ROP_NAME src_and_notdst
8c78881f 298#define ROP_FN(d, s) (s) & (~(d))
47b43a1f 299#include "cirrus_vga_rop.h"
e6e5ad80 300
a5082316 301#define ROP_NAME notdst
8c78881f 302#define ROP_FN(d, s) ~(d)
47b43a1f 303#include "cirrus_vga_rop.h"
e6e5ad80 304
a5082316 305#define ROP_NAME src
8c78881f 306#define ROP_FN(d, s) s
47b43a1f 307#include "cirrus_vga_rop.h"
e6e5ad80 308
a5082316 309#define ROP_NAME 1
8c78881f 310#define ROP_FN(d, s) ~0
47b43a1f 311#include "cirrus_vga_rop.h"
a5082316
FB		 312
313#define ROP_NAME notsrc_and_dst
8c78881f 314#define ROP_FN(d, s) (~(s)) & (d)
47b43a1f 315#include "cirrus_vga_rop.h"
a5082316
FB		 316
317#define ROP_NAME src_xor_dst
8c78881f 318#define ROP_FN(d, s) (s) ^ (d)
47b43a1f 319#include "cirrus_vga_rop.h"
a5082316
FB		 320
321#define ROP_NAME src_or_dst
8c78881f 322#define ROP_FN(d, s) (s) | (d)
47b43a1f 323#include "cirrus_vga_rop.h"
a5082316
FB		 324
325#define ROP_NAME notsrc_or_notdst
8c78881f 326#define ROP_FN(d, s) (~(s)) | (~(d))
47b43a1f 327#include "cirrus_vga_rop.h"
a5082316
FB		 328
329#define ROP_NAME src_notxor_dst
8c78881f 330#define ROP_FN(d, s) ~((s) ^ (d))
47b43a1f 331#include "cirrus_vga_rop.h"
e6e5ad80 332
a5082316 333#define ROP_NAME src_or_notdst
8c78881f 334#define ROP_FN(d, s) (s) | (~(d))
47b43a1f 335#include "cirrus_vga_rop.h"
a5082316
FB		 336
337#define ROP_NAME notsrc
8c78881f 338#define ROP_FN(d, s) (~(s))
47b43a1f 339#include "cirrus_vga_rop.h"
a5082316
FB		 340
341#define ROP_NAME notsrc_or_dst
8c78881f 342#define ROP_FN(d, s) (~(s)) | (d)
47b43a1f 343#include "cirrus_vga_rop.h"
a5082316
FB		 344
345#define ROP_NAME notsrc_and_notdst
8c78881f 346#define ROP_FN(d, s) (~(s)) & (~(d))
47b43a1f 347#include "cirrus_vga_rop.h"
a5082316
FB		 348
349static const cirrus_bitblt_rop_t cirrus_fwd_rop[16] = {
350 cirrus_bitblt_rop_fwd_0,
351 cirrus_bitblt_rop_fwd_src_and_dst,
352 cirrus_bitblt_rop_nop,
353 cirrus_bitblt_rop_fwd_src_and_notdst,
354 cirrus_bitblt_rop_fwd_notdst,
355 cirrus_bitblt_rop_fwd_src,
356 cirrus_bitblt_rop_fwd_1,
357 cirrus_bitblt_rop_fwd_notsrc_and_dst,
358 cirrus_bitblt_rop_fwd_src_xor_dst,
359 cirrus_bitblt_rop_fwd_src_or_dst,
360 cirrus_bitblt_rop_fwd_notsrc_or_notdst,
361 cirrus_bitblt_rop_fwd_src_notxor_dst,
362 cirrus_bitblt_rop_fwd_src_or_notdst,
363 cirrus_bitblt_rop_fwd_notsrc,
364 cirrus_bitblt_rop_fwd_notsrc_or_dst,
365 cirrus_bitblt_rop_fwd_notsrc_and_notdst,
366};
367
368static const cirrus_bitblt_rop_t cirrus_bkwd_rop[16] = {
369 cirrus_bitblt_rop_bkwd_0,
370 cirrus_bitblt_rop_bkwd_src_and_dst,
371 cirrus_bitblt_rop_nop,
372 cirrus_bitblt_rop_bkwd_src_and_notdst,
373 cirrus_bitblt_rop_bkwd_notdst,
374 cirrus_bitblt_rop_bkwd_src,
375 cirrus_bitblt_rop_bkwd_1,
376 cirrus_bitblt_rop_bkwd_notsrc_and_dst,
377 cirrus_bitblt_rop_bkwd_src_xor_dst,
378 cirrus_bitblt_rop_bkwd_src_or_dst,
379 cirrus_bitblt_rop_bkwd_notsrc_or_notdst,
380 cirrus_bitblt_rop_bkwd_src_notxor_dst,
381 cirrus_bitblt_rop_bkwd_src_or_notdst,
382 cirrus_bitblt_rop_bkwd_notsrc,
383 cirrus_bitblt_rop_bkwd_notsrc_or_dst,
384 cirrus_bitblt_rop_bkwd_notsrc_and_notdst,
385};
96cf2df8
TS		 386
387#define TRANSP_ROP(name) {\
388 name ## _8,\
389 name ## _16,\
390 }
391#define TRANSP_NOP(func) {\
392 func,\
393 func,\
394 }
395
396static const cirrus_bitblt_rop_t cirrus_fwd_transp_rop[16][2] = {
397 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_0),
398 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_and_dst),
399 TRANSP_NOP(cirrus_bitblt_rop_nop),
400 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_and_notdst),
401 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notdst),
402 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src),
403 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_1),
404 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_and_dst),
405 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_xor_dst),
406 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_or_dst),
407 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_or_notdst),
408 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_notxor_dst),
409 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_or_notdst),
410 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc),
411 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_or_dst),
412 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_and_notdst),
413};
414
415static const cirrus_bitblt_rop_t cirrus_bkwd_transp_rop[16][2] = {
416 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_0),
417 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_and_dst),
418 TRANSP_NOP(cirrus_bitblt_rop_nop),
419 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_and_notdst),
420 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notdst),
421 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src),
422 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_1),
423 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_and_dst),
424 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_xor_dst),
425 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_or_dst),
426 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_or_notdst),
427 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_notxor_dst),
428 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_or_notdst),
429 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc),
430 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_or_dst),
431 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_and_notdst),
432};
433
a5082316
FB		 434#define ROP2(name) {\
435 name ## _8,\
436 name ## _16,\
437 name ## _24,\
438 name ## _32,\
439 }
440
441#define ROP_NOP2(func) {\
442 func,\
443 func,\
444 func,\
445 func,\
446 }
447
e69390ce
FB		 448static const cirrus_bitblt_rop_t cirrus_patternfill[16][4] = {
449 ROP2(cirrus_patternfill_0),
450 ROP2(cirrus_patternfill_src_and_dst),
451 ROP_NOP2(cirrus_bitblt_rop_nop),
452 ROP2(cirrus_patternfill_src_and_notdst),
453 ROP2(cirrus_patternfill_notdst),
454 ROP2(cirrus_patternfill_src),
455 ROP2(cirrus_patternfill_1),
456 ROP2(cirrus_patternfill_notsrc_and_dst),
457 ROP2(cirrus_patternfill_src_xor_dst),
458 ROP2(cirrus_patternfill_src_or_dst),
459 ROP2(cirrus_patternfill_notsrc_or_notdst),
460 ROP2(cirrus_patternfill_src_notxor_dst),
461 ROP2(cirrus_patternfill_src_or_notdst),
462 ROP2(cirrus_patternfill_notsrc),
463 ROP2(cirrus_patternfill_notsrc_or_dst),
464 ROP2(cirrus_patternfill_notsrc_and_notdst),
465};
466
a5082316
FB		 467static const cirrus_bitblt_rop_t cirrus_colorexpand_transp[16][4] = {
468 ROP2(cirrus_colorexpand_transp_0),
469 ROP2(cirrus_colorexpand_transp_src_and_dst),
470 ROP_NOP2(cirrus_bitblt_rop_nop),
471 ROP2(cirrus_colorexpand_transp_src_and_notdst),
472 ROP2(cirrus_colorexpand_transp_notdst),
473 ROP2(cirrus_colorexpand_transp_src),
474 ROP2(cirrus_colorexpand_transp_1),
475 ROP2(cirrus_colorexpand_transp_notsrc_and_dst),
476 ROP2(cirrus_colorexpand_transp_src_xor_dst),
477 ROP2(cirrus_colorexpand_transp_src_or_dst),
478 ROP2(cirrus_colorexpand_transp_notsrc_or_notdst),
479 ROP2(cirrus_colorexpand_transp_src_notxor_dst),
480 ROP2(cirrus_colorexpand_transp_src_or_notdst),
481 ROP2(cirrus_colorexpand_transp_notsrc),
482 ROP2(cirrus_colorexpand_transp_notsrc_or_dst),
483 ROP2(cirrus_colorexpand_transp_notsrc_and_notdst),
484};
485
486static const cirrus_bitblt_rop_t cirrus_colorexpand[16][4] = {
487 ROP2(cirrus_colorexpand_0),
488 ROP2(cirrus_colorexpand_src_and_dst),
489 ROP_NOP2(cirrus_bitblt_rop_nop),
490 ROP2(cirrus_colorexpand_src_and_notdst),
491 ROP2(cirrus_colorexpand_notdst),
492 ROP2(cirrus_colorexpand_src),
493 ROP2(cirrus_colorexpand_1),
494 ROP2(cirrus_colorexpand_notsrc_and_dst),
495 ROP2(cirrus_colorexpand_src_xor_dst),
496 ROP2(cirrus_colorexpand_src_or_dst),
497 ROP2(cirrus_colorexpand_notsrc_or_notdst),
498 ROP2(cirrus_colorexpand_src_notxor_dst),
499 ROP2(cirrus_colorexpand_src_or_notdst),
500 ROP2(cirrus_colorexpand_notsrc),
501 ROP2(cirrus_colorexpand_notsrc_or_dst),
502 ROP2(cirrus_colorexpand_notsrc_and_notdst),
503};
504
b30d4608
FB		 505static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern_transp[16][4] = {
506 ROP2(cirrus_colorexpand_pattern_transp_0),
507 ROP2(cirrus_colorexpand_pattern_transp_src_and_dst),
508 ROP_NOP2(cirrus_bitblt_rop_nop),
509 ROP2(cirrus_colorexpand_pattern_transp_src_and_notdst),
510 ROP2(cirrus_colorexpand_pattern_transp_notdst),
511 ROP2(cirrus_colorexpand_pattern_transp_src),
512 ROP2(cirrus_colorexpand_pattern_transp_1),
513 ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_dst),
514 ROP2(cirrus_colorexpand_pattern_transp_src_xor_dst),
515 ROP2(cirrus_colorexpand_pattern_transp_src_or_dst),
516 ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_notdst),
517 ROP2(cirrus_colorexpand_pattern_transp_src_notxor_dst),
518 ROP2(cirrus_colorexpand_pattern_transp_src_or_notdst),
519 ROP2(cirrus_colorexpand_pattern_transp_notsrc),
520 ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_dst),
521 ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_notdst),
522};
523
524static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern[16][4] = {
525 ROP2(cirrus_colorexpand_pattern_0),
526 ROP2(cirrus_colorexpand_pattern_src_and_dst),
527 ROP_NOP2(cirrus_bitblt_rop_nop),
528 ROP2(cirrus_colorexpand_pattern_src_and_notdst),
529 ROP2(cirrus_colorexpand_pattern_notdst),
530 ROP2(cirrus_colorexpand_pattern_src),
531 ROP2(cirrus_colorexpand_pattern_1),
532 ROP2(cirrus_colorexpand_pattern_notsrc_and_dst),
533 ROP2(cirrus_colorexpand_pattern_src_xor_dst),
534 ROP2(cirrus_colorexpand_pattern_src_or_dst),
535 ROP2(cirrus_colorexpand_pattern_notsrc_or_notdst),
536 ROP2(cirrus_colorexpand_pattern_src_notxor_dst),
537 ROP2(cirrus_colorexpand_pattern_src_or_notdst),
538 ROP2(cirrus_colorexpand_pattern_notsrc),
539 ROP2(cirrus_colorexpand_pattern_notsrc_or_dst),
540 ROP2(cirrus_colorexpand_pattern_notsrc_and_notdst),
541};
542
a5082316
FB		 543static const cirrus_fill_t cirrus_fill[16][4] = {
544 ROP2(cirrus_fill_0),
545 ROP2(cirrus_fill_src_and_dst),
546 ROP_NOP2(cirrus_bitblt_fill_nop),
547 ROP2(cirrus_fill_src_and_notdst),
548 ROP2(cirrus_fill_notdst),
549 ROP2(cirrus_fill_src),
550 ROP2(cirrus_fill_1),
551 ROP2(cirrus_fill_notsrc_and_dst),
552 ROP2(cirrus_fill_src_xor_dst),
553 ROP2(cirrus_fill_src_or_dst),
554 ROP2(cirrus_fill_notsrc_or_notdst),
555 ROP2(cirrus_fill_src_notxor_dst),
556 ROP2(cirrus_fill_src_or_notdst),
557 ROP2(cirrus_fill_notsrc),
558 ROP2(cirrus_fill_notsrc_or_dst),
559 ROP2(cirrus_fill_notsrc_and_notdst),
560};
561
562static inline void cirrus_bitblt_fgcol(CirrusVGAState *s)
e6e5ad80 563{
a5082316
FB		 564 unsigned int color;
565 switch (s->cirrus_blt_pixelwidth) {
566 case 1:
567 s->cirrus_blt_fgcol = s->cirrus_shadow_gr1;
568 break;
569 case 2:
4e12cd94 570 color = s->cirrus_shadow_gr1 | (s->vga.gr[0x11] << 8);
a5082316
FB		 571 s->cirrus_blt_fgcol = le16_to_cpu(color);
572 break;
573 case 3:
5fafdf24 574 s->cirrus_blt_fgcol = s->cirrus_shadow_gr1 |
4e12cd94 575 (s->vga.gr[0x11] << 8) | (s->vga.gr[0x13] << 16);
a5082316
FB		 576 break;
577 default:
578 case 4:
4e12cd94
AK		 579 color = s->cirrus_shadow_gr1 | (s->vga.gr[0x11] << 8) |
580 (s->vga.gr[0x13] << 16) | (s->vga.gr[0x15] << 24);
a5082316
FB		 581 s->cirrus_blt_fgcol = le32_to_cpu(color);
582 break;
e6e5ad80
FB		 583 }
584}
585
a5082316 586static inline void cirrus_bitblt_bgcol(CirrusVGAState *s)
e6e5ad80 587{
a5082316 588 unsigned int color;
e6e5ad80
FB		 589 switch (s->cirrus_blt_pixelwidth) {
590 case 1:
a5082316
FB		 591 s->cirrus_blt_bgcol = s->cirrus_shadow_gr0;
592 break;
e6e5ad80 593 case 2:
4e12cd94 594 color = s->cirrus_shadow_gr0 | (s->vga.gr[0x10] << 8);
a5082316
FB		 595 s->cirrus_blt_bgcol = le16_to_cpu(color);
596 break;
e6e5ad80 597 case 3:
5fafdf24 598 s->cirrus_blt_bgcol = s->cirrus_shadow_gr0 |
4e12cd94 599 (s->vga.gr[0x10] << 8) | (s->vga.gr[0x12] << 16);
a5082316 600 break;
e6e5ad80 601 default:
a5082316 602 case 4:
4e12cd94
AK		 603 color = s->cirrus_shadow_gr0 | (s->vga.gr[0x10] << 8) |
604 (s->vga.gr[0x12] << 16) | (s->vga.gr[0x14] << 24);
a5082316
FB		 605 s->cirrus_blt_bgcol = le32_to_cpu(color);
606 break;
e6e5ad80
FB		 607 }
608}
609
610static void cirrus_invalidate_region(CirrusVGAState * s, int off_begin,
611 int off_pitch, int bytesperline,
612 int lines)
613{
614 int y;
615 int off_cur;
616 int off_cur_end;
617
618 for (y = 0; y < lines; y++) {
619 off_cur = off_begin;
b2eb849d 620 off_cur_end = (off_cur + bytesperline) & s->cirrus_addr_mask;
fd4aa979 621 memory_region_set_dirty(&s->vga.vram, off_cur, off_cur_end - off_cur);
e6e5ad80
FB		 622 off_begin += off_pitch;
623 }
624}
625
e6e5ad80
FB		 626static int cirrus_bitblt_common_patterncopy(CirrusVGAState * s,
627 const uint8_t * src)
628{
e6e5ad80 629 uint8_t *dst;
e6e5ad80 630
4e12cd94 631 dst = s->vga.vram_ptr + (s->cirrus_blt_dstaddr & s->cirrus_addr_mask);
b2eb849d
AJ		 632
633 if (BLTUNSAFE(s))
634 return 0;
635
e69390ce 636 (*s->cirrus_rop) (s, dst, src,
5fafdf24 637 s->cirrus_blt_dstpitch, 0,
e69390ce 638 s->cirrus_blt_width, s->cirrus_blt_height);
e6e5ad80 639 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
e69390ce
FB		 640 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
641 s->cirrus_blt_height);
e6e5ad80
FB		 642 return 1;
643}
644
a21ae81d
FB		 645/* fill */
646
a5082316 647static int cirrus_bitblt_solidfill(CirrusVGAState *s, int blt_rop)
a21ae81d 648{
a5082316 649 cirrus_fill_t rop_func;
a21ae81d 650
b2eb849d
AJ		 651 if (BLTUNSAFE(s))
652 return 0;
a5082316 653 rop_func = cirrus_fill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
4e12cd94 654 rop_func(s, s->vga.vram_ptr + (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
a5082316
FB		 655 s->cirrus_blt_dstpitch,
656 s->cirrus_blt_width, s->cirrus_blt_height);
a21ae81d
FB		 657 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
658 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
659 s->cirrus_blt_height);
660 cirrus_bitblt_reset(s);
661 return 1;
662}
663
e6e5ad80
FB		 664/***************************************
665 *
666 * bitblt (video-to-video)
667 *
668 ***************************************/
669
670static int cirrus_bitblt_videotovideo_patterncopy(CirrusVGAState * s)
671{
672 return cirrus_bitblt_common_patterncopy(s,
4e12cd94 673 s->vga.vram_ptr + ((s->cirrus_blt_srcaddr & ~7) &
b2eb849d 674 s->cirrus_addr_mask));
e6e5ad80
FB		 675}
676
24236869 677static void cirrus_do_copy(CirrusVGAState *s, int dst, int src, int w, int h)
e6e5ad80 678{
78935c4a
AJ		 679 int sx = 0, sy = 0;
680 int dx = 0, dy = 0;
681 int depth = 0;
24236869
FB		 682 int notify = 0;
683
92d675d1
AJ		 684 /* make sure to only copy if it's a plain copy ROP */
685 if (*s->cirrus_rop == cirrus_bitblt_rop_fwd_src ||
686 *s->cirrus_rop == cirrus_bitblt_rop_bkwd_src) {
24236869 687
92d675d1
AJ		 688 int width, height;
689
690 depth = s->vga.get_bpp(&s->vga) / 8;
691 s->vga.get_resolution(&s->vga, &width, &height);
692
693 /* extra x, y */
694 sx = (src % ABS(s->cirrus_blt_srcpitch)) / depth;
695 sy = (src / ABS(s->cirrus_blt_srcpitch));
696 dx = (dst % ABS(s->cirrus_blt_dstpitch)) / depth;
697 dy = (dst / ABS(s->cirrus_blt_dstpitch));
24236869 698
92d675d1
AJ		 699 /* normalize width */
700 w /= depth;
24236869 701
92d675d1
AJ		 702 /* if we're doing a backward copy, we have to adjust
703 our x/y to be the upper left corner (instead of the lower
704 right corner) */
705 if (s->cirrus_blt_dstpitch < 0) {
706 sx -= (s->cirrus_blt_width / depth) - 1;
707 dx -= (s->cirrus_blt_width / depth) - 1;
708 sy -= s->cirrus_blt_height - 1;
709 dy -= s->cirrus_blt_height - 1;
710 }
711
712 /* are we in the visible portion of memory? */
713 if (sx >= 0 && sy >= 0 && dx >= 0 && dy >= 0 &&
714 (sx + w) <= width && (sy + h) <= height &&
715 (dx + w) <= width && (dy + h) <= height) {
716 notify = 1;
717 }
718 }
24236869
FB		 719
720 /* we have to flush all pending changes so that the copy
721 is generated at the appropriate moment in time */
722 if (notify)
1dbfa005 723 graphic_hw_update(s->vga.con);
24236869 724
4e12cd94 725 (*s->cirrus_rop) (s, s->vga.vram_ptr +
b2eb849d 726 (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
4e12cd94 727 s->vga.vram_ptr +
b2eb849d 728 (s->cirrus_blt_srcaddr & s->cirrus_addr_mask),
e6e5ad80
FB		 729 s->cirrus_blt_dstpitch, s->cirrus_blt_srcpitch,
730 s->cirrus_blt_width, s->cirrus_blt_height);
24236869 731
c78f7137
GH		 732 if (notify) {
733 qemu_console_copy(s->vga.con,
38334f76
AZ		 734 sx, sy, dx, dy,
735 s->cirrus_blt_width / depth,
736 s->cirrus_blt_height);
c78f7137 737 }
24236869
FB		 738
739 /* we don't have to notify the display that this portion has
38334f76 740 changed since qemu_console_copy implies this */
24236869 741
31c05501
AL		 742 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
743 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
744 s->cirrus_blt_height);
24236869
FB		 745}
746
747static int cirrus_bitblt_videotovideo_copy(CirrusVGAState * s)
748{
65d35a09
AJ		 749 if (BLTUNSAFE(s))
750 return 0;
751
4e12cd94
AK		 752 cirrus_do_copy(s, s->cirrus_blt_dstaddr - s->vga.start_addr,
753 s->cirrus_blt_srcaddr - s->vga.start_addr,
7d957bd8 754 s->cirrus_blt_width, s->cirrus_blt_height);
24236869 755
e6e5ad80
FB		 756 return 1;
757}
758
759/***************************************
760 *
761 * bitblt (cpu-to-video)
762 *
763 ***************************************/
764
e6e5ad80
FB		 765static void cirrus_bitblt_cputovideo_next(CirrusVGAState * s)
766{
767 int copy_count;
a5082316 768 uint8_t *end_ptr;
3b46e624 769
e6e5ad80 770 if (s->cirrus_srccounter > 0) {
a5082316
FB		 771 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
772 cirrus_bitblt_common_patterncopy(s, s->cirrus_bltbuf);
773 the_end:
774 s->cirrus_srccounter = 0;
775 cirrus_bitblt_reset(s);
776 } else {
777 /* at least one scan line */
778 do {
4e12cd94 779 (*s->cirrus_rop)(s, s->vga.vram_ptr +
b2eb849d
AJ		 780 (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
781 s->cirrus_bltbuf, 0, 0, s->cirrus_blt_width, 1);
a5082316
FB		 782 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr, 0,
783 s->cirrus_blt_width, 1);
784 s->cirrus_blt_dstaddr += s->cirrus_blt_dstpitch;
785 s->cirrus_srccounter -= s->cirrus_blt_srcpitch;
786 if (s->cirrus_srccounter <= 0)
787 goto the_end;
66a0a2cb 788 /* more bytes than needed can be transferred because of
a5082316
FB		 789 word alignment, so we keep them for the next line */
790 /* XXX: keep alignment to speed up transfer */
791 end_ptr = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
792 copy_count = s->cirrus_srcptr_end - end_ptr;
793 memmove(s->cirrus_bltbuf, end_ptr, copy_count);
794 s->cirrus_srcptr = s->cirrus_bltbuf + copy_count;
795 s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
796 } while (s->cirrus_srcptr >= s->cirrus_srcptr_end);
797 }
e6e5ad80
FB		 798 }
799}
800
801/***************************************
802 *
803 * bitblt wrapper
804 *
805 ***************************************/
806
807static void cirrus_bitblt_reset(CirrusVGAState * s)
808{
f8b237af
AL		 809 int need_update;
810
4e12cd94 811 s->vga.gr[0x31] &=
e6e5ad80 812 ~(CIRRUS_BLT_START | CIRRUS_BLT_BUSY | CIRRUS_BLT_FIFOUSED);
f8b237af
AL		 813 need_update = s->cirrus_srcptr != &s->cirrus_bltbuf[0]
814 || s->cirrus_srcptr_end != &s->cirrus_bltbuf[0];
e6e5ad80
FB		 815 s->cirrus_srcptr = &s->cirrus_bltbuf[0];
816 s->cirrus_srcptr_end = &s->cirrus_bltbuf[0];
817 s->cirrus_srccounter = 0;
f8b237af
AL		 818 if (!need_update)
819 return;
8926b517 820 cirrus_update_memory_access(s);
e6e5ad80
FB		 821}
822
823static int cirrus_bitblt_cputovideo(CirrusVGAState * s)
824{
a5082316
FB		 825 int w;
826
e6e5ad80
FB		 827 s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_MEMSYSSRC;
828 s->cirrus_srcptr = &s->cirrus_bltbuf[0];
829 s->cirrus_srcptr_end = &s->cirrus_bltbuf[0];
830
831 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
832 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
a5082316 833 s->cirrus_blt_srcpitch = 8;
e6e5ad80 834 } else {
b30d4608 835 /* XXX: check for 24 bpp */
a5082316 836 s->cirrus_blt_srcpitch = 8 * 8 * s->cirrus_blt_pixelwidth;
e6e5ad80 837 }
a5082316 838 s->cirrus_srccounter = s->cirrus_blt_srcpitch;
e6e5ad80
FB		 839 } else {
840 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
a5082316 841 w = s->cirrus_blt_width / s->cirrus_blt_pixelwidth;
5fafdf24 842 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_DWORDGRANULARITY)
a5082316
FB		 843 s->cirrus_blt_srcpitch = ((w + 31) >> 5);
844 else
845 s->cirrus_blt_srcpitch = ((w + 7) >> 3);
e6e5ad80 846 } else {
c9c0eae8
FB		 847 /* always align input size to 32 bits */
848 s->cirrus_blt_srcpitch = (s->cirrus_blt_width + 3) & ~3;
e6e5ad80 849 }
a5082316 850 s->cirrus_srccounter = s->cirrus_blt_srcpitch * s->cirrus_blt_height;
e6e5ad80 851 }
a5082316
FB		 852 s->cirrus_srcptr = s->cirrus_bltbuf;
853 s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
8926b517 854 cirrus_update_memory_access(s);
e6e5ad80
FB		 855 return 1;
856}
857
858static int cirrus_bitblt_videotocpu(CirrusVGAState * s)
859{
860 /* XXX */
a5082316 861#ifdef DEBUG_BITBLT
e6e5ad80
FB		 862 printf("cirrus: bitblt (video to cpu) is not implemented yet\n");
863#endif
864 return 0;
865}
866
867static int cirrus_bitblt_videotovideo(CirrusVGAState * s)
868{
869 int ret;
870
871 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
872 ret = cirrus_bitblt_videotovideo_patterncopy(s);
873 } else {
874 ret = cirrus_bitblt_videotovideo_copy(s);
875 }
e6e5ad80
FB		 876 if (ret)
877 cirrus_bitblt_reset(s);
878 return ret;
879}
880
881static void cirrus_bitblt_start(CirrusVGAState * s)
882{
883 uint8_t blt_rop;
884
4e12cd94 885 s->vga.gr[0x31] |= CIRRUS_BLT_BUSY;
a5082316 886
4e12cd94
AK		 887 s->cirrus_blt_width = (s->vga.gr[0x20] | (s->vga.gr[0x21] << 8)) + 1;
888 s->cirrus_blt_height = (s->vga.gr[0x22] | (s->vga.gr[0x23] << 8)) + 1;
889 s->cirrus_blt_dstpitch = (s->vga.gr[0x24] | (s->vga.gr[0x25] << 8));
890 s->cirrus_blt_srcpitch = (s->vga.gr[0x26] | (s->vga.gr[0x27] << 8));
e6e5ad80 891 s->cirrus_blt_dstaddr =
4e12cd94 892 (s->vga.gr[0x28] | (s->vga.gr[0x29] << 8) | (s->vga.gr[0x2a] << 16));
e6e5ad80 893 s->cirrus_blt_srcaddr =
4e12cd94
AK		 894 (s->vga.gr[0x2c] | (s->vga.gr[0x2d] << 8) | (s->vga.gr[0x2e] << 16));
895 s->cirrus_blt_mode = s->vga.gr[0x30];
896 s->cirrus_blt_modeext = s->vga.gr[0x33];
897 blt_rop = s->vga.gr[0x32];
e6e5ad80 898
a21ae81d 899#ifdef DEBUG_BITBLT
0b74ed78 900 printf("rop=0x%02x mode=0x%02x modeext=0x%02x w=%d h=%d dpitch=%d spitch=%d daddr=0x%08x saddr=0x%08x writemask=0x%02x\n",
5fafdf24 901 blt_rop,
a21ae81d 902 s->cirrus_blt_mode,
a5082316 903 s->cirrus_blt_modeext,
a21ae81d
FB		 904 s->cirrus_blt_width,
905 s->cirrus_blt_height,
906 s->cirrus_blt_dstpitch,
907 s->cirrus_blt_srcpitch,
908 s->cirrus_blt_dstaddr,
a5082316 909 s->cirrus_blt_srcaddr,
4e12cd94 910 s->vga.gr[0x2f]);
a21ae81d
FB		 911#endif
912
e6e5ad80
FB		 913 switch (s->cirrus_blt_mode & CIRRUS_BLTMODE_PIXELWIDTHMASK) {
914 case CIRRUS_BLTMODE_PIXELWIDTH8:
915 s->cirrus_blt_pixelwidth = 1;
916 break;
917 case CIRRUS_BLTMODE_PIXELWIDTH16:
918 s->cirrus_blt_pixelwidth = 2;
919 break;
920 case CIRRUS_BLTMODE_PIXELWIDTH24:
921 s->cirrus_blt_pixelwidth = 3;
922 break;
923 case CIRRUS_BLTMODE_PIXELWIDTH32:
924 s->cirrus_blt_pixelwidth = 4;
925 break;
926 default:
a5082316 927#ifdef DEBUG_BITBLT
e6e5ad80
FB		 928 printf("cirrus: bitblt - pixel width is unknown\n");
929#endif
930 goto bitblt_ignore;
931 }
932 s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_PIXELWIDTHMASK;
933
934 if ((s->
935 cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSSRC |
936 CIRRUS_BLTMODE_MEMSYSDEST))
937 == (CIRRUS_BLTMODE_MEMSYSSRC | CIRRUS_BLTMODE_MEMSYSDEST)) {
a5082316 938#ifdef DEBUG_BITBLT
e6e5ad80
FB		 939 printf("cirrus: bitblt - memory-to-memory copy is requested\n");
940#endif
941 goto bitblt_ignore;
942 }
943
a5082316 944 if ((s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_SOLIDFILL) &&
5fafdf24 945 (s->cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSDEST |
a21ae81d 946 CIRRUS_BLTMODE_TRANSPARENTCOMP |
5fafdf24
TS		 947 CIRRUS_BLTMODE_PATTERNCOPY |
948 CIRRUS_BLTMODE_COLOREXPAND)) ==
a21ae81d 949 (CIRRUS_BLTMODE_PATTERNCOPY | CIRRUS_BLTMODE_COLOREXPAND)) {
a5082316
FB		 950 cirrus_bitblt_fgcol(s);
951 cirrus_bitblt_solidfill(s, blt_rop);
e6e5ad80 952 } else {
5fafdf24
TS		 953 if ((s->cirrus_blt_mode & (CIRRUS_BLTMODE_COLOREXPAND |
954 CIRRUS_BLTMODE_PATTERNCOPY)) ==
a5082316
FB		 955 CIRRUS_BLTMODE_COLOREXPAND) {
956
957 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
b30d4608 958 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV)
4c8732d7 959 cirrus_bitblt_bgcol(s);
b30d4608 960 else
4c8732d7 961 cirrus_bitblt_fgcol(s);
b30d4608 962 s->cirrus_rop = cirrus_colorexpand_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
a5082316
FB		 963 } else {
964 cirrus_bitblt_fgcol(s);
965 cirrus_bitblt_bgcol(s);
966 s->cirrus_rop = cirrus_colorexpand[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
967 }
e69390ce 968 } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
b30d4608
FB		 969 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
970 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
971 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV)
972 cirrus_bitblt_bgcol(s);
973 else
974 cirrus_bitblt_fgcol(s);
975 s->cirrus_rop = cirrus_colorexpand_pattern_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
976 } else {
977 cirrus_bitblt_fgcol(s);
978 cirrus_bitblt_bgcol(s);
979 s->cirrus_rop = cirrus_colorexpand_pattern[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
980 }
981 } else {
982 s->cirrus_rop = cirrus_patternfill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
983 }
a21ae81d 984 } else {
96cf2df8
TS		 985 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
986 if (s->cirrus_blt_pixelwidth > 2) {
987 printf("src transparent without colorexpand must be 8bpp or 16bpp\n");
988 goto bitblt_ignore;
989 }
990 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) {
991 s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch;
992 s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch;
993 s->cirrus_rop = cirrus_bkwd_transp_rop[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
994 } else {
995 s->cirrus_rop = cirrus_fwd_transp_rop[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
996 }
997 } else {
998 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) {
999 s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch;
1000 s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch;
1001 s->cirrus_rop = cirrus_bkwd_rop[rop_to_index[blt_rop]];
1002 } else {
1003 s->cirrus_rop = cirrus_fwd_rop[rop_to_index[blt_rop]];
1004 }
1005 }
1006 }
a21ae81d
FB		 1007 // setup bitblt engine.
1008 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSSRC) {
1009 if (!cirrus_bitblt_cputovideo(s))
1010 goto bitblt_ignore;
1011 } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSDEST) {
1012 if (!cirrus_bitblt_videotocpu(s))
1013 goto bitblt_ignore;
1014 } else {
1015 if (!cirrus_bitblt_videotovideo(s))
1016 goto bitblt_ignore;
1017 }
e6e5ad80 1018 }
e6e5ad80
FB		 1019 return;
1020 bitblt_ignore:;
1021 cirrus_bitblt_reset(s);
1022}
1023
1024static void cirrus_write_bitblt(CirrusVGAState * s, unsigned reg_value)
1025{
1026 unsigned old_value;
1027
4e12cd94
AK		 1028 old_value = s->vga.gr[0x31];
1029 s->vga.gr[0x31] = reg_value;
e6e5ad80
FB		 1030
1031 if (((old_value & CIRRUS_BLT_RESET) != 0) &&
1032 ((reg_value & CIRRUS_BLT_RESET) == 0)) {
1033 cirrus_bitblt_reset(s);
1034 } else if (((old_value & CIRRUS_BLT_START) == 0) &&
1035 ((reg_value & CIRRUS_BLT_START) != 0)) {
e6e5ad80
FB		 1036 cirrus_bitblt_start(s);
1037 }
1038}
1039
1040
1041/***************************************
1042 *
1043 * basic parameters
1044 *
1045 ***************************************/
1046
a4a2f59c 1047static void cirrus_get_offsets(VGACommonState *s1,
83acc96b
FB		 1048 uint32_t *pline_offset,
1049 uint32_t *pstart_addr,
1050 uint32_t *pline_compare)
e6e5ad80 1051{
4e12cd94 1052 CirrusVGAState * s = container_of(s1, CirrusVGAState, vga);
83acc96b 1053 uint32_t start_addr, line_offset, line_compare;
e6e5ad80 1054
4e12cd94
AK		 1055 line_offset = s->vga.cr[0x13]
1056 | ((s->vga.cr[0x1b] & 0x10) << 4);
e6e5ad80
FB		 1057 line_offset <<= 3;
1058 *pline_offset = line_offset;
1059
4e12cd94
AK		 1060 start_addr = (s->vga.cr[0x0c] << 8)
1061 | s->vga.cr[0x0d]
1062 | ((s->vga.cr[0x1b] & 0x01) << 16)
1063 | ((s->vga.cr[0x1b] & 0x0c) << 15)
1064 | ((s->vga.cr[0x1d] & 0x80) << 12);
e6e5ad80 1065 *pstart_addr = start_addr;
83acc96b 1066
4e12cd94
AK		 1067 line_compare = s->vga.cr[0x18] |
1068 ((s->vga.cr[0x07] & 0x10) << 4) |
1069 ((s->vga.cr[0x09] & 0x40) << 3);
83acc96b 1070 *pline_compare = line_compare;
e6e5ad80
FB		 1071}
1072
1073static uint32_t cirrus_get_bpp16_depth(CirrusVGAState * s)
1074{
1075 uint32_t ret = 16;
1076
1077 switch (s->cirrus_hidden_dac_data & 0xf) {
1078 case 0:
1079 ret = 15;
1080 break; /* Sierra HiColor */
1081 case 1:
1082 ret = 16;
1083 break; /* XGA HiColor */
1084 default:
1085#ifdef DEBUG_CIRRUS
1086 printf("cirrus: invalid DAC value %x in 16bpp\n",
1087 (s->cirrus_hidden_dac_data & 0xf));
1088#endif
1089 ret = 15; /* XXX */
1090 break;
1091 }
1092 return ret;
1093}
1094
a4a2f59c 1095static int cirrus_get_bpp(VGACommonState *s1)
e6e5ad80 1096{
4e12cd94 1097 CirrusVGAState * s = container_of(s1, CirrusVGAState, vga);
e6e5ad80
FB		 1098 uint32_t ret = 8;
1099
4e12cd94 1100 if ((s->vga.sr[0x07] & 0x01) != 0) {
e6e5ad80 1101 /* Cirrus SVGA */
4e12cd94 1102 switch (s->vga.sr[0x07] & CIRRUS_SR7_BPP_MASK) {
e6e5ad80
FB		 1103 case CIRRUS_SR7_BPP_8:
1104 ret = 8;
1105 break;
1106 case CIRRUS_SR7_BPP_16_DOUBLEVCLK:
1107 ret = cirrus_get_bpp16_depth(s);
1108 break;
1109 case CIRRUS_SR7_BPP_24:
1110 ret = 24;
1111 break;
1112 case CIRRUS_SR7_BPP_16:
1113 ret = cirrus_get_bpp16_depth(s);
1114 break;
1115 case CIRRUS_SR7_BPP_32:
1116 ret = 32;
1117 break;
1118 default:
1119#ifdef DEBUG_CIRRUS
4e12cd94 1120 printf("cirrus: unknown bpp - sr7=%x\n", s->vga.sr[0x7]);
e6e5ad80
FB		 1121#endif
1122 ret = 8;
1123 break;
1124 }
1125 } else {
1126 /* VGA */
aeb3c85f 1127 ret = 0;
e6e5ad80
FB		 1128 }
1129
1130 return ret;
1131}
1132
a4a2f59c 1133static void cirrus_get_resolution(VGACommonState *s, int *pwidth, int *pheight)
78e127ef
FB		 1134{
1135 int width, height;
3b46e624 1136
78e127ef 1137 width = (s->cr[0x01] + 1) * 8;
5fafdf24
TS		 1138 height = s->cr[0x12] |
1139 ((s->cr[0x07] & 0x02) << 7) |
78e127ef
FB		 1140 ((s->cr[0x07] & 0x40) << 3);
1141 height = (height + 1);
1142 /* interlace support */
1143 if (s->cr[0x1a] & 0x01)
1144 height = height * 2;
1145 *pwidth = width;
1146 *pheight = height;
1147}
1148
e6e5ad80
FB		 1149/***************************************
1150 *
1151 * bank memory
1152 *
1153 ***************************************/
1154
1155static void cirrus_update_bank_ptr(CirrusVGAState * s, unsigned bank_index)
1156{
1157 unsigned offset;
1158 unsigned limit;
1159
4e12cd94
AK		 1160 if ((s->vga.gr[0x0b] & 0x01) != 0) /* dual bank */
1161 offset = s->vga.gr[0x09 + bank_index];
e6e5ad80 1162 else /* single bank */
4e12cd94 1163 offset = s->vga.gr[0x09];
e6e5ad80 1164
4e12cd94 1165 if ((s->vga.gr[0x0b] & 0x20) != 0)
e6e5ad80
FB		 1166 offset <<= 14;
1167 else
1168 offset <<= 12;
1169
e3a4e4b6 1170 if (s->real_vram_size <= offset)
e6e5ad80
FB		 1171 limit = 0;
1172 else
e3a4e4b6 1173 limit = s->real_vram_size - offset;
e6e5ad80 1174
4e12cd94 1175 if (((s->vga.gr[0x0b] & 0x01) == 0) && (bank_index != 0)) {
e6e5ad80
FB		 1176 if (limit > 0x8000) {
1177 offset += 0x8000;
1178 limit -= 0x8000;
1179 } else {
1180 limit = 0;
1181 }
1182 }
1183
1184 if (limit > 0) {
1185 s->cirrus_bank_base[bank_index] = offset;
1186 s->cirrus_bank_limit[bank_index] = limit;
1187 } else {
1188 s->cirrus_bank_base[bank_index] = 0;
1189 s->cirrus_bank_limit[bank_index] = 0;
1190 }
1191}
1192
1193/***************************************
1194 *
1195 * I/O access between 0x3c4-0x3c5
1196 *
1197 ***************************************/
1198
8a82c322 1199static int cirrus_vga_read_sr(CirrusVGAState * s)
e6e5ad80 1200{
8a82c322 1201 switch (s->vga.sr_index) {
e6e5ad80
FB		 1202 case 0x00: // Standard VGA
1203 case 0x01: // Standard VGA
1204 case 0x02: // Standard VGA
1205 case 0x03: // Standard VGA
1206 case 0x04: // Standard VGA
8a82c322 1207 return s->vga.sr[s->vga.sr_index];
e6e5ad80 1208 case 0x06: // Unlock Cirrus extensions
8a82c322 1209 return s->vga.sr[s->vga.sr_index];
e6e5ad80
FB		 1210 case 0x10:
1211 case 0x30:
1212 case 0x50:
1213 case 0x70: // Graphics Cursor X
1214 case 0x90:
1215 case 0xb0:
1216 case 0xd0:
1217 case 0xf0: // Graphics Cursor X
8a82c322 1218 return s->vga.sr[0x10];
e6e5ad80
FB		 1219 case 0x11:
1220 case 0x31:
1221 case 0x51:
1222 case 0x71: // Graphics Cursor Y
1223 case 0x91:
1224 case 0xb1:
1225 case 0xd1:
a5082316 1226 case 0xf1: // Graphics Cursor Y
8a82c322 1227 return s->vga.sr[0x11];
aeb3c85f
FB		 1228 case 0x05: // ???
1229 case 0x07: // Extended Sequencer Mode
1230 case 0x08: // EEPROM Control
1231 case 0x09: // Scratch Register 0
1232 case 0x0a: // Scratch Register 1
1233 case 0x0b: // VCLK 0
1234 case 0x0c: // VCLK 1
1235 case 0x0d: // VCLK 2
1236 case 0x0e: // VCLK 3
1237 case 0x0f: // DRAM Control
e6e5ad80
FB		 1238 case 0x12: // Graphics Cursor Attribute
1239 case 0x13: // Graphics Cursor Pattern Address
1240 case 0x14: // Scratch Register 2
1241 case 0x15: // Scratch Register 3
1242 case 0x16: // Performance Tuning Register
1243 case 0x17: // Configuration Readback and Extended Control
1244 case 0x18: // Signature Generator Control
1245 case 0x19: // Signal Generator Result
1246 case 0x1a: // Signal Generator Result
1247 case 0x1b: // VCLK 0 Denominator & Post
1248 case 0x1c: // VCLK 1 Denominator & Post
1249 case 0x1d: // VCLK 2 Denominator & Post
1250 case 0x1e: // VCLK 3 Denominator & Post
1251 case 0x1f: // BIOS Write Enable and MCLK select
1252#ifdef DEBUG_CIRRUS
8a82c322 1253 printf("cirrus: handled inport sr_index %02x\n", s->vga.sr_index);
e6e5ad80 1254#endif
8a82c322 1255 return s->vga.sr[s->vga.sr_index];
e6e5ad80
FB		 1256 default:
1257#ifdef DEBUG_CIRRUS
8a82c322 1258 printf("cirrus: inport sr_index %02x\n", s->vga.sr_index);
e6e5ad80 1259#endif
8a82c322 1260 return 0xff;
e6e5ad80
FB		 1261 break;
1262 }
e6e5ad80
FB		 1263}
1264
31c63201 1265static void cirrus_vga_write_sr(CirrusVGAState * s, uint32_t val)
e6e5ad80 1266{
31c63201 1267 switch (s->vga.sr_index) {
e6e5ad80
FB		 1268 case 0x00: // Standard VGA
1269 case 0x01: // Standard VGA
1270 case 0x02: // Standard VGA
1271 case 0x03: // Standard VGA
1272 case 0x04: // Standard VGA
31c63201
JQ		 1273 s->vga.sr[s->vga.sr_index] = val & sr_mask[s->vga.sr_index];
1274 if (s->vga.sr_index == 1)
1275 s->vga.update_retrace_info(&s->vga);
1276 break;
e6e5ad80 1277 case 0x06: // Unlock Cirrus extensions
31c63201
JQ		 1278 val &= 0x17;
1279 if (val == 0x12) {
1280 s->vga.sr[s->vga.sr_index] = 0x12;
e6e5ad80 1281 } else {
31c63201 1282 s->vga.sr[s->vga.sr_index] = 0x0f;
e6e5ad80
FB		 1283 }
1284 break;
1285 case 0x10:
1286 case 0x30:
1287 case 0x50:
1288 case 0x70: // Graphics Cursor X
1289 case 0x90:
1290 case 0xb0:
1291 case 0xd0:
1292 case 0xf0: // Graphics Cursor X
31c63201
JQ		 1293 s->vga.sr[0x10] = val;
1294 s->hw_cursor_x = (val << 3) | (s->vga.sr_index >> 5);
e6e5ad80
FB		 1295 break;
1296 case 0x11:
1297 case 0x31:
1298 case 0x51:
1299 case 0x71: // Graphics Cursor Y
1300 case 0x91:
1301 case 0xb1:
1302 case 0xd1:
1303 case 0xf1: // Graphics Cursor Y
31c63201
JQ		 1304 s->vga.sr[0x11] = val;
1305 s->hw_cursor_y = (val << 3) | (s->vga.sr_index >> 5);
e6e5ad80
FB		 1306 break;
1307 case 0x07: // Extended Sequencer Mode
2bec46dc 1308 cirrus_update_memory_access(s);
e6e5ad80
FB		 1309 case 0x08: // EEPROM Control
1310 case 0x09: // Scratch Register 0
1311 case 0x0a: // Scratch Register 1
1312 case 0x0b: // VCLK 0
1313 case 0x0c: // VCLK 1
1314 case 0x0d: // VCLK 2
1315 case 0x0e: // VCLK 3
1316 case 0x0f: // DRAM Control
1317 case 0x12: // Graphics Cursor Attribute
1318 case 0x13: // Graphics Cursor Pattern Address
1319 case 0x14: // Scratch Register 2
1320 case 0x15: // Scratch Register 3
1321 case 0x16: // Performance Tuning Register
e6e5ad80
FB		 1322 case 0x18: // Signature Generator Control
1323 case 0x19: // Signature Generator Result
1324 case 0x1a: // Signature Generator Result
1325 case 0x1b: // VCLK 0 Denominator & Post
1326 case 0x1c: // VCLK 1 Denominator & Post
1327 case 0x1d: // VCLK 2 Denominator & Post
1328 case 0x1e: // VCLK 3 Denominator & Post
1329 case 0x1f: // BIOS Write Enable and MCLK select
31c63201 1330 s->vga.sr[s->vga.sr_index] = val;
e6e5ad80
FB		 1331#ifdef DEBUG_CIRRUS
1332 printf("cirrus: handled outport sr_index %02x, sr_value %02x\n",
31c63201 1333 s->vga.sr_index, val);
e6e5ad80
FB		 1334#endif
1335 break;
8926b517 1336 case 0x17: // Configuration Readback and Extended Control
31c63201
JQ		 1337 s->vga.sr[s->vga.sr_index] = (s->vga.sr[s->vga.sr_index] & 0x38)
1338 | (val & 0xc7);
8926b517
FB		 1339 cirrus_update_memory_access(s);
1340 break;
e6e5ad80
FB		 1341 default:
1342#ifdef DEBUG_CIRRUS
31c63201
JQ		 1343 printf("cirrus: outport sr_index %02x, sr_value %02x\n",
1344 s->vga.sr_index, val);
e6e5ad80
FB		 1345#endif
1346 break;
1347 }
e6e5ad80
FB		 1348}
1349
1350/***************************************
1351 *
1352 * I/O access at 0x3c6
1353 *
1354 ***************************************/
1355
957c9db5 1356static int cirrus_read_hidden_dac(CirrusVGAState * s)
e6e5ad80 1357{
a21ae81d 1358 if (++s->cirrus_hidden_dac_lockindex == 5) {
957c9db5
JQ		 1359 s->cirrus_hidden_dac_lockindex = 0;
1360 return s->cirrus_hidden_dac_data;
e6e5ad80 1361 }
957c9db5 1362 return 0xff;
e6e5ad80
FB		 1363}
1364
1365static void cirrus_write_hidden_dac(CirrusVGAState * s, int reg_value)
1366{
1367 if (s->cirrus_hidden_dac_lockindex == 4) {
1368 s->cirrus_hidden_dac_data = reg_value;
a21ae81d 1369#if defined(DEBUG_CIRRUS)
e6e5ad80
FB		 1370 printf("cirrus: outport hidden DAC, value %02x\n", reg_value);
1371#endif
1372 }
1373 s->cirrus_hidden_dac_lockindex = 0;
1374}
1375
1376/***************************************
1377 *
1378 * I/O access at 0x3c9
1379 *
1380 ***************************************/
1381
5deaeee3 1382static int cirrus_vga_read_palette(CirrusVGAState * s)
e6e5ad80 1383{
5deaeee3
JQ		 1384 int val;
1385
1386 if ((s->vga.sr[0x12] & CIRRUS_CURSOR_HIDDENPEL)) {
1387 val = s->cirrus_hidden_palette[(s->vga.dac_read_index & 0x0f) * 3 +
1388 s->vga.dac_sub_index];
1389 } else {
1390 val = s->vga.palette[s->vga.dac_read_index * 3 + s->vga.dac_sub_index];
1391 }
4e12cd94
AK		 1392 if (++s->vga.dac_sub_index == 3) {
1393 s->vga.dac_sub_index = 0;
1394 s->vga.dac_read_index++;
e6e5ad80 1395 }
5deaeee3 1396 return val;
e6e5ad80
FB		 1397}
1398
86948bb1 1399static void cirrus_vga_write_palette(CirrusVGAState * s, int reg_value)
e6e5ad80 1400{
4e12cd94
AK		 1401 s->vga.dac_cache[s->vga.dac_sub_index] = reg_value;
1402 if (++s->vga.dac_sub_index == 3) {
86948bb1
JQ		 1403 if ((s->vga.sr[0x12] & CIRRUS_CURSOR_HIDDENPEL)) {
1404 memcpy(&s->cirrus_hidden_palette[(s->vga.dac_write_index & 0x0f) * 3],
1405 s->vga.dac_cache, 3);
1406 } else {
1407 memcpy(&s->vga.palette[s->vga.dac_write_index * 3], s->vga.dac_cache, 3);
1408 }
a5082316 1409 /* XXX update cursor */
4e12cd94
AK		 1410 s->vga.dac_sub_index = 0;
1411 s->vga.dac_write_index++;
e6e5ad80 1412 }
e6e5ad80
FB		 1413}
1414
1415/***************************************
1416 *
1417 * I/O access between 0x3ce-0x3cf
1418 *
1419 ***************************************/
1420
f705db9d 1421static int cirrus_vga_read_gr(CirrusVGAState * s, unsigned reg_index)
e6e5ad80
FB		 1422{
1423 switch (reg_index) {
aeb3c85f 1424 case 0x00: // Standard VGA, BGCOLOR 0x000000ff
f705db9d 1425 return s->cirrus_shadow_gr0;
aeb3c85f 1426 case 0x01: // Standard VGA, FGCOLOR 0x000000ff
f705db9d 1427 return s->cirrus_shadow_gr1;
e6e5ad80
FB		 1428 case 0x02: // Standard VGA
1429 case 0x03: // Standard VGA
1430 case 0x04: // Standard VGA
1431 case 0x06: // Standard VGA
1432 case 0x07: // Standard VGA
1433 case 0x08: // Standard VGA
f705db9d 1434 return s->vga.gr[s->vga.gr_index];
e6e5ad80
FB		 1435 case 0x05: // Standard VGA, Cirrus extended mode
1436 default:
1437 break;
1438 }
1439
1440 if (reg_index < 0x3a) {
f705db9d 1441 return s->vga.gr[reg_index];
e6e5ad80
FB		 1442 } else {
1443#ifdef DEBUG_CIRRUS
1444 printf("cirrus: inport gr_index %02x\n", reg_index);
1445#endif
f705db9d 1446 return 0xff;
e6e5ad80 1447 }
e6e5ad80
FB		 1448}
1449
22286bc6
JQ		 1450static void
1451cirrus_vga_write_gr(CirrusVGAState * s, unsigned reg_index, int reg_value)
e6e5ad80 1452{
a5082316
FB		 1453#if defined(DEBUG_BITBLT) && 0
1454 printf("gr%02x: %02x\n", reg_index, reg_value);
1455#endif
e6e5ad80
FB		 1456 switch (reg_index) {
1457 case 0x00: // Standard VGA, BGCOLOR 0x000000ff
f22f5b07 1458 s->vga.gr[reg_index] = reg_value & gr_mask[reg_index];
aeb3c85f 1459 s->cirrus_shadow_gr0 = reg_value;
22286bc6 1460 break;
e6e5ad80 1461 case 0x01: // Standard VGA, FGCOLOR 0x000000ff
f22f5b07 1462 s->vga.gr[reg_index] = reg_value & gr_mask[reg_index];
aeb3c85f 1463 s->cirrus_shadow_gr1 = reg_value;
22286bc6 1464 break;
e6e5ad80
FB		 1465 case 0x02: // Standard VGA
1466 case 0x03: // Standard VGA
1467 case 0x04: // Standard VGA
1468 case 0x06: // Standard VGA
1469 case 0x07: // Standard VGA
1470 case 0x08: // Standard VGA
22286bc6
JQ		 1471 s->vga.gr[reg_index] = reg_value & gr_mask[reg_index];
1472 break;
e6e5ad80 1473 case 0x05: // Standard VGA, Cirrus extended mode
4e12cd94 1474 s->vga.gr[reg_index] = reg_value & 0x7f;
8926b517 1475 cirrus_update_memory_access(s);
e6e5ad80
FB		 1476 break;
1477 case 0x09: // bank offset #0
1478 case 0x0A: // bank offset #1
4e12cd94 1479 s->vga.gr[reg_index] = reg_value;
8926b517
FB		 1480 cirrus_update_bank_ptr(s, 0);
1481 cirrus_update_bank_ptr(s, 1);
2bec46dc 1482 cirrus_update_memory_access(s);
8926b517 1483 break;
e6e5ad80 1484 case 0x0B:
4e12cd94 1485 s->vga.gr[reg_index] = reg_value;
e6e5ad80
FB		 1486 cirrus_update_bank_ptr(s, 0);
1487 cirrus_update_bank_ptr(s, 1);
8926b517 1488 cirrus_update_memory_access(s);
e6e5ad80
FB		 1489 break;
1490 case 0x10: // BGCOLOR 0x0000ff00
1491 case 0x11: // FGCOLOR 0x0000ff00
1492 case 0x12: // BGCOLOR 0x00ff0000
1493 case 0x13: // FGCOLOR 0x00ff0000
1494 case 0x14: // BGCOLOR 0xff000000
1495 case 0x15: // FGCOLOR 0xff000000
1496 case 0x20: // BLT WIDTH 0x0000ff
1497 case 0x22: // BLT HEIGHT 0x0000ff
1498 case 0x24: // BLT DEST PITCH 0x0000ff
1499 case 0x26: // BLT SRC PITCH 0x0000ff
1500 case 0x28: // BLT DEST ADDR 0x0000ff
1501 case 0x29: // BLT DEST ADDR 0x00ff00
1502 case 0x2c: // BLT SRC ADDR 0x0000ff
1503 case 0x2d: // BLT SRC ADDR 0x00ff00
a5082316 1504 case 0x2f: // BLT WRITEMASK
e6e5ad80
FB		 1505 case 0x30: // BLT MODE
1506 case 0x32: // RASTER OP
a21ae81d 1507 case 0x33: // BLT MODEEXT
e6e5ad80
FB		 1508 case 0x34: // BLT TRANSPARENT COLOR 0x00ff
1509 case 0x35: // BLT TRANSPARENT COLOR 0xff00
1510 case 0x38: // BLT TRANSPARENT COLOR MASK 0x00ff
1511 case 0x39: // BLT TRANSPARENT COLOR MASK 0xff00
4e12cd94 1512 s->vga.gr[reg_index] = reg_value;
e6e5ad80
FB		 1513 break;
1514 case 0x21: // BLT WIDTH 0x001f00
1515 case 0x23: // BLT HEIGHT 0x001f00
1516 case 0x25: // BLT DEST PITCH 0x001f00
1517 case 0x27: // BLT SRC PITCH 0x001f00
4e12cd94 1518 s->vga.gr[reg_index] = reg_value & 0x1f;
e6e5ad80
FB		 1519 break;
1520 case 0x2a: // BLT DEST ADDR 0x3f0000
4e12cd94 1521 s->vga.gr[reg_index] = reg_value & 0x3f;
a5082316 1522 /* if auto start mode, starts bit blt now */
4e12cd94 1523 if (s->vga.gr[0x31] & CIRRUS_BLT_AUTOSTART) {
a5082316
FB		 1524 cirrus_bitblt_start(s);
1525 }
1526 break;
e6e5ad80 1527 case 0x2e: // BLT SRC ADDR 0x3f0000
4e12cd94 1528 s->vga.gr[reg_index] = reg_value & 0x3f;
e6e5ad80
FB		 1529 break;
1530 case 0x31: // BLT STATUS/START
1531 cirrus_write_bitblt(s, reg_value);
1532 break;
1533 default:
1534#ifdef DEBUG_CIRRUS
1535 printf("cirrus: outport gr_index %02x, gr_value %02x\n", reg_index,
1536 reg_value);
1537#endif
1538 break;
1539 }
e6e5ad80
FB		 1540}
1541
1542/***************************************
1543 *
1544 * I/O access between 0x3d4-0x3d5
1545 *
1546 ***************************************/
1547
b863d514 1548static int cirrus_vga_read_cr(CirrusVGAState * s, unsigned reg_index)
e6e5ad80
FB		 1549{
1550 switch (reg_index) {
1551 case 0x00: // Standard VGA
1552 case 0x01: // Standard VGA
1553 case 0x02: // Standard VGA
1554 case 0x03: // Standard VGA
1555 case 0x04: // Standard VGA
1556 case 0x05: // Standard VGA
1557 case 0x06: // Standard VGA
1558 case 0x07: // Standard VGA
1559 case 0x08: // Standard VGA
1560 case 0x09: // Standard VGA
1561 case 0x0a: // Standard VGA
1562 case 0x0b: // Standard VGA
1563 case 0x0c: // Standard VGA
1564 case 0x0d: // Standard VGA
1565 case 0x0e: // Standard VGA
1566 case 0x0f: // Standard VGA
1567 case 0x10: // Standard VGA
1568 case 0x11: // Standard VGA
1569 case 0x12: // Standard VGA
1570 case 0x13: // Standard VGA
1571 case 0x14: // Standard VGA
1572 case 0x15: // Standard VGA
1573 case 0x16: // Standard VGA
1574 case 0x17: // Standard VGA
1575 case 0x18: // Standard VGA
b863d514 1576 return s->vga.cr[s->vga.cr_index];
ca896ef3 1577 case 0x24: // Attribute Controller Toggle Readback (R)
b863d514 1578 return (s->vga.ar_flip_flop << 7);
e6e5ad80
FB		 1579 case 0x19: // Interlace End
1580 case 0x1a: // Miscellaneous Control
1581 case 0x1b: // Extended Display Control
1582 case 0x1c: // Sync Adjust and Genlock
1583 case 0x1d: // Overlay Extended Control
1584 case 0x22: // Graphics Data Latches Readback (R)
e6e5ad80
FB		 1585 case 0x25: // Part Status
1586 case 0x27: // Part ID (R)
b863d514 1587 return s->vga.cr[s->vga.cr_index];
e6e5ad80 1588 case 0x26: // Attribute Controller Index Readback (R)
b863d514 1589 return s->vga.ar_index & 0x3f;
e6e5ad80
FB		 1590 break;
1591 default:
1592#ifdef DEBUG_CIRRUS
1593 printf("cirrus: inport cr_index %02x\n", reg_index);
e6e5ad80 1594#endif
b863d514 1595 return 0xff;
e6e5ad80 1596 }
e6e5ad80
FB		 1597}
1598
4ec1ce04 1599static void cirrus_vga_write_cr(CirrusVGAState * s, int reg_value)
e6e5ad80 1600{
4ec1ce04 1601 switch (s->vga.cr_index) {
e6e5ad80
FB		 1602 case 0x00: // Standard VGA
1603 case 0x01: // Standard VGA
1604 case 0x02: // Standard VGA
1605 case 0x03: // Standard VGA
1606 case 0x04: // Standard VGA
1607 case 0x05: // Standard VGA
1608 case 0x06: // Standard VGA
1609 case 0x07: // Standard VGA
1610 case 0x08: // Standard VGA
1611 case 0x09: // Standard VGA
1612 case 0x0a: // Standard VGA
1613 case 0x0b: // Standard VGA
1614 case 0x0c: // Standard VGA
1615 case 0x0d: // Standard VGA
1616 case 0x0e: // Standard VGA
1617 case 0x0f: // Standard VGA
1618 case 0x10: // Standard VGA
1619 case 0x11: // Standard VGA
1620 case 0x12: // Standard VGA
1621 case 0x13: // Standard VGA
1622 case 0x14: // Standard VGA
1623 case 0x15: // Standard VGA
1624 case 0x16: // Standard VGA
1625 case 0x17: // Standard VGA
1626 case 0x18: // Standard VGA
4ec1ce04
JQ		 1627 /* handle CR0-7 protection */
1628 if ((s->vga.cr[0x11] & 0x80) && s->vga.cr_index <= 7) {
1629 /* can always write bit 4 of CR7 */
1630 if (s->vga.cr_index == 7)
1631 s->vga.cr[7] = (s->vga.cr[7] & ~0x10) | (reg_value & 0x10);
1632 return;
1633 }
1634 s->vga.cr[s->vga.cr_index] = reg_value;
1635 switch(s->vga.cr_index) {
1636 case 0x00:
1637 case 0x04:
1638 case 0x05:
1639 case 0x06:
1640 case 0x07:
1641 case 0x11:
1642 case 0x17:
1643 s->vga.update_retrace_info(&s->vga);
1644 break;
1645 }
1646 break;
e6e5ad80
FB		 1647 case 0x19: // Interlace End
1648 case 0x1a: // Miscellaneous Control
1649 case 0x1b: // Extended Display Control
1650 case 0x1c: // Sync Adjust and Genlock
ae184e4a 1651 case 0x1d: // Overlay Extended Control
4ec1ce04 1652 s->vga.cr[s->vga.cr_index] = reg_value;
e6e5ad80
FB		 1653#ifdef DEBUG_CIRRUS
1654 printf("cirrus: handled outport cr_index %02x, cr_value %02x\n",
4ec1ce04 1655 s->vga.cr_index, reg_value);
e6e5ad80
FB		 1656#endif
1657 break;
1658 case 0x22: // Graphics Data Latches Readback (R)
1659 case 0x24: // Attribute Controller Toggle Readback (R)
1660 case 0x26: // Attribute Controller Index Readback (R)
1661 case 0x27: // Part ID (R)
1662 break;
e6e5ad80
FB		 1663 case 0x25: // Part Status
1664 default:
1665#ifdef DEBUG_CIRRUS
4ec1ce04
JQ		 1666 printf("cirrus: outport cr_index %02x, cr_value %02x\n",
1667 s->vga.cr_index, reg_value);
e6e5ad80
FB		 1668#endif
1669 break;
1670 }
e6e5ad80
FB		 1671}
1672
1673/***************************************
1674 *
1675 * memory-mapped I/O (bitblt)
1676 *
1677 ***************************************/
1678
1679static uint8_t cirrus_mmio_blt_read(CirrusVGAState * s, unsigned address)
1680{
1681 int value = 0xff;
1682
1683 switch (address) {
1684 case (CIRRUS_MMIO_BLTBGCOLOR + 0):
f705db9d 1685 value = cirrus_vga_read_gr(s, 0x00);
e6e5ad80
FB		 1686 break;
1687 case (CIRRUS_MMIO_BLTBGCOLOR + 1):
f705db9d 1688 value = cirrus_vga_read_gr(s, 0x10);
e6e5ad80
FB		 1689 break;
1690 case (CIRRUS_MMIO_BLTBGCOLOR + 2):
f705db9d 1691 value = cirrus_vga_read_gr(s, 0x12);
e6e5ad80
FB		 1692 break;
1693 case (CIRRUS_MMIO_BLTBGCOLOR + 3):
f705db9d 1694 value = cirrus_vga_read_gr(s, 0x14);
e6e5ad80
FB		 1695 break;
1696 case (CIRRUS_MMIO_BLTFGCOLOR + 0):
f705db9d 1697 value = cirrus_vga_read_gr(s, 0x01);
e6e5ad80
FB		 1698 break;
1699 case (CIRRUS_MMIO_BLTFGCOLOR + 1):
f705db9d 1700 value = cirrus_vga_read_gr(s, 0x11);
e6e5ad80
FB		 1701 break;
1702 case (CIRRUS_MMIO_BLTFGCOLOR + 2):
f705db9d 1703 value = cirrus_vga_read_gr(s, 0x13);
e6e5ad80
FB		 1704 break;
1705 case (CIRRUS_MMIO_BLTFGCOLOR + 3):
f705db9d 1706 value = cirrus_vga_read_gr(s, 0x15);
e6e5ad80
FB		 1707 break;
1708 case (CIRRUS_MMIO_BLTWIDTH + 0):
f705db9d 1709 value = cirrus_vga_read_gr(s, 0x20);
e6e5ad80
FB		 1710 break;
1711 case (CIRRUS_MMIO_BLTWIDTH + 1):
f705db9d 1712 value = cirrus_vga_read_gr(s, 0x21);
e6e5ad80
FB		 1713 break;
1714 case (CIRRUS_MMIO_BLTHEIGHT + 0):
f705db9d 1715 value = cirrus_vga_read_gr(s, 0x22);
e6e5ad80
FB		 1716 break;
1717 case (CIRRUS_MMIO_BLTHEIGHT + 1):
f705db9d 1718 value = cirrus_vga_read_gr(s, 0x23);
e6e5ad80
FB		 1719 break;
1720 case (CIRRUS_MMIO_BLTDESTPITCH + 0):
f705db9d 1721 value = cirrus_vga_read_gr(s, 0x24);
e6e5ad80
FB		 1722 break;
1723 case (CIRRUS_MMIO_BLTDESTPITCH + 1):
f705db9d 1724 value = cirrus_vga_read_gr(s, 0x25);
e6e5ad80
FB		 1725 break;
1726 case (CIRRUS_MMIO_BLTSRCPITCH + 0):
f705db9d 1727 value = cirrus_vga_read_gr(s, 0x26);
e6e5ad80
FB		 1728 break;
1729 case (CIRRUS_MMIO_BLTSRCPITCH + 1):
f705db9d 1730 value = cirrus_vga_read_gr(s, 0x27);
e6e5ad80
FB		 1731 break;
1732 case (CIRRUS_MMIO_BLTDESTADDR + 0):
f705db9d 1733 value = cirrus_vga_read_gr(s, 0x28);
e6e5ad80
FB		 1734 break;
1735 case (CIRRUS_MMIO_BLTDESTADDR + 1):
f705db9d 1736 value = cirrus_vga_read_gr(s, 0x29);
e6e5ad80
FB		 1737 break;
1738 case (CIRRUS_MMIO_BLTDESTADDR + 2):
f705db9d 1739 value = cirrus_vga_read_gr(s, 0x2a);
e6e5ad80
FB		 1740 break;
1741 case (CIRRUS_MMIO_BLTSRCADDR + 0):
f705db9d 1742 value = cirrus_vga_read_gr(s, 0x2c);
e6e5ad80
FB		 1743 break;
1744 case (CIRRUS_MMIO_BLTSRCADDR + 1):
f705db9d 1745 value = cirrus_vga_read_gr(s, 0x2d);
e6e5ad80
FB		 1746 break;
1747 case (CIRRUS_MMIO_BLTSRCADDR + 2):
f705db9d 1748 value = cirrus_vga_read_gr(s, 0x2e);
e6e5ad80
FB		 1749 break;
1750 case CIRRUS_MMIO_BLTWRITEMASK:
f705db9d 1751 value = cirrus_vga_read_gr(s, 0x2f);
e6e5ad80
FB		 1752 break;
1753 case CIRRUS_MMIO_BLTMODE:
f705db9d 1754 value = cirrus_vga_read_gr(s, 0x30);
e6e5ad80
FB		 1755 break;
1756 case CIRRUS_MMIO_BLTROP:
f705db9d 1757 value = cirrus_vga_read_gr(s, 0x32);
e6e5ad80 1758 break;
a21ae81d 1759 case CIRRUS_MMIO_BLTMODEEXT:
f705db9d 1760 value = cirrus_vga_read_gr(s, 0x33);
a21ae81d 1761 break;
e6e5ad80 1762 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0):
f705db9d 1763 value = cirrus_vga_read_gr(s, 0x34);
e6e5ad80
FB		 1764 break;
1765 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1):
f705db9d 1766 value = cirrus_vga_read_gr(s, 0x35);
e6e5ad80
FB		 1767 break;
1768 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0):
f705db9d 1769 value = cirrus_vga_read_gr(s, 0x38);
e6e5ad80
FB		 1770 break;
1771 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1):
f705db9d 1772 value = cirrus_vga_read_gr(s, 0x39);
e6e5ad80
FB		 1773 break;
1774 case CIRRUS_MMIO_BLTSTATUS:
f705db9d 1775 value = cirrus_vga_read_gr(s, 0x31);
e6e5ad80
FB		 1776 break;
1777 default:
1778#ifdef DEBUG_CIRRUS
1779 printf("cirrus: mmio read - address 0x%04x\n", address);
1780#endif
1781 break;
1782 }
1783
1784 return (uint8_t) value;
1785}
1786
1787static void cirrus_mmio_blt_write(CirrusVGAState * s, unsigned address,
1788 uint8_t value)
1789{
1790 switch (address) {
1791 case (CIRRUS_MMIO_BLTBGCOLOR + 0):
22286bc6 1792 cirrus_vga_write_gr(s, 0x00, value);
e6e5ad80
FB		 1793 break;
1794 case (CIRRUS_MMIO_BLTBGCOLOR + 1):
22286bc6 1795 cirrus_vga_write_gr(s, 0x10, value);
e6e5ad80
FB		 1796 break;
1797 case (CIRRUS_MMIO_BLTBGCOLOR + 2):
22286bc6 1798 cirrus_vga_write_gr(s, 0x12, value);
e6e5ad80
FB		 1799 break;
1800 case (CIRRUS_MMIO_BLTBGCOLOR + 3):
22286bc6 1801 cirrus_vga_write_gr(s, 0x14, value);
e6e5ad80
FB		 1802 break;
1803 case (CIRRUS_MMIO_BLTFGCOLOR + 0):
22286bc6 1804 cirrus_vga_write_gr(s, 0x01, value);
e6e5ad80
FB		 1805 break;
1806 case (CIRRUS_MMIO_BLTFGCOLOR + 1):
22286bc6 1807 cirrus_vga_write_gr(s, 0x11, value);
e6e5ad80
FB		 1808 break;
1809 case (CIRRUS_MMIO_BLTFGCOLOR + 2):
22286bc6 1810 cirrus_vga_write_gr(s, 0x13, value);
e6e5ad80
FB		 1811 break;
1812 case (CIRRUS_MMIO_BLTFGCOLOR + 3):
22286bc6 1813 cirrus_vga_write_gr(s, 0x15, value);
e6e5ad80
FB		 1814 break;
1815 case (CIRRUS_MMIO_BLTWIDTH + 0):
22286bc6 1816 cirrus_vga_write_gr(s, 0x20, value);
e6e5ad80
FB		 1817 break;
1818 case (CIRRUS_MMIO_BLTWIDTH + 1):
22286bc6 1819 cirrus_vga_write_gr(s, 0x21, value);
e6e5ad80
FB		 1820 break;
1821 case (CIRRUS_MMIO_BLTHEIGHT + 0):
22286bc6 1822 cirrus_vga_write_gr(s, 0x22, value);
e6e5ad80
FB		 1823 break;
1824 case (CIRRUS_MMIO_BLTHEIGHT + 1):
22286bc6 1825 cirrus_vga_write_gr(s, 0x23, value);
e6e5ad80
FB		 1826 break;
1827 case (CIRRUS_MMIO_BLTDESTPITCH + 0):
22286bc6 1828 cirrus_vga_write_gr(s, 0x24, value);
e6e5ad80
FB		 1829 break;
1830 case (CIRRUS_MMIO_BLTDESTPITCH + 1):
22286bc6 1831 cirrus_vga_write_gr(s, 0x25, value);
e6e5ad80
FB		 1832 break;
1833 case (CIRRUS_MMIO_BLTSRCPITCH + 0):
22286bc6 1834 cirrus_vga_write_gr(s, 0x26, value);
e6e5ad80
FB		 1835 break;
1836 case (CIRRUS_MMIO_BLTSRCPITCH + 1):
22286bc6 1837 cirrus_vga_write_gr(s, 0x27, value);
e6e5ad80
FB		 1838 break;
1839 case (CIRRUS_MMIO_BLTDESTADDR + 0):
22286bc6 1840 cirrus_vga_write_gr(s, 0x28, value);
e6e5ad80
FB		 1841 break;
1842 case (CIRRUS_MMIO_BLTDESTADDR + 1):
22286bc6 1843 cirrus_vga_write_gr(s, 0x29, value);
e6e5ad80
FB		 1844 break;
1845 case (CIRRUS_MMIO_BLTDESTADDR + 2):
22286bc6 1846 cirrus_vga_write_gr(s, 0x2a, value);
e6e5ad80
FB		 1847 break;
1848 case (CIRRUS_MMIO_BLTDESTADDR + 3):
1849 /* ignored */
1850 break;
1851 case (CIRRUS_MMIO_BLTSRCADDR + 0):
22286bc6 1852 cirrus_vga_write_gr(s, 0x2c, value);
e6e5ad80
FB		 1853 break;
1854 case (CIRRUS_MMIO_BLTSRCADDR + 1):
22286bc6 1855 cirrus_vga_write_gr(s, 0x2d, value);
e6e5ad80
FB		 1856 break;
1857 case (CIRRUS_MMIO_BLTSRCADDR + 2):
22286bc6 1858 cirrus_vga_write_gr(s, 0x2e, value);
e6e5ad80
FB		 1859 break;
1860 case CIRRUS_MMIO_BLTWRITEMASK:
22286bc6 1861 cirrus_vga_write_gr(s, 0x2f, value);
e6e5ad80
FB		 1862 break;
1863 case CIRRUS_MMIO_BLTMODE:
22286bc6 1864 cirrus_vga_write_gr(s, 0x30, value);
e6e5ad80
FB		 1865 break;
1866 case CIRRUS_MMIO_BLTROP:
22286bc6 1867 cirrus_vga_write_gr(s, 0x32, value);
e6e5ad80 1868 break;
a21ae81d 1869 case CIRRUS_MMIO_BLTMODEEXT:
22286bc6 1870 cirrus_vga_write_gr(s, 0x33, value);
a21ae81d 1871 break;
e6e5ad80 1872 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0):
22286bc6 1873 cirrus_vga_write_gr(s, 0x34, value);
e6e5ad80
FB		 1874 break;
1875 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1):
22286bc6 1876 cirrus_vga_write_gr(s, 0x35, value);
e6e5ad80
FB		 1877 break;
1878 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0):
22286bc6 1879 cirrus_vga_write_gr(s, 0x38, value);
e6e5ad80
FB		 1880 break;
1881 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1):
22286bc6 1882 cirrus_vga_write_gr(s, 0x39, value);
e6e5ad80
FB		 1883 break;
1884 case CIRRUS_MMIO_BLTSTATUS:
22286bc6 1885 cirrus_vga_write_gr(s, 0x31, value);
e6e5ad80
FB		 1886 break;
1887 default:
1888#ifdef DEBUG_CIRRUS
1889 printf("cirrus: mmio write - addr 0x%04x val 0x%02x (ignored)\n",
1890 address, value);
1891#endif
1892 break;
1893 }
1894}
1895
e6e5ad80
FB		 1896/***************************************
1897 *
1898 * write mode 4/5
1899 *
e6e5ad80
FB		 1900 ***************************************/
1901
1902static void cirrus_mem_writeb_mode4and5_8bpp(CirrusVGAState * s,
1903 unsigned mode,
1904 unsigned offset,
1905 uint32_t mem_value)
1906{
1907 int x;
1908 unsigned val = mem_value;
1909 uint8_t *dst;
1910
4e12cd94 1911 dst = s->vga.vram_ptr + (offset &= s->cirrus_addr_mask);
e6e5ad80
FB		 1912 for (x = 0; x < 8; x++) {
1913 if (val & 0x80) {
0b74ed78 1914 *dst = s->cirrus_shadow_gr1;
e6e5ad80 1915 } else if (mode == 5) {
0b74ed78 1916 *dst = s->cirrus_shadow_gr0;
e6e5ad80
FB		 1917 }
1918 val <<= 1;
0b74ed78 1919 dst++;
e6e5ad80 1920 }
fd4aa979 1921 memory_region_set_dirty(&s->vga.vram, offset, 8);
e6e5ad80
FB		 1922}
1923
1924static void cirrus_mem_writeb_mode4and5_16bpp(CirrusVGAState * s,
1925 unsigned mode,
1926 unsigned offset,
1927 uint32_t mem_value)
1928{
1929 int x;
1930 unsigned val = mem_value;
1931 uint8_t *dst;
1932
4e12cd94 1933 dst = s->vga.vram_ptr + (offset &= s->cirrus_addr_mask);
e6e5ad80
FB		 1934 for (x = 0; x < 8; x++) {
1935 if (val & 0x80) {
0b74ed78 1936 *dst = s->cirrus_shadow_gr1;
4e12cd94 1937 *(dst + 1) = s->vga.gr[0x11];
e6e5ad80 1938 } else if (mode == 5) {
0b74ed78 1939 *dst = s->cirrus_shadow_gr0;
4e12cd94 1940 *(dst + 1) = s->vga.gr[0x10];
e6e5ad80
FB		 1941 }
1942 val <<= 1;
0b74ed78 1943 dst += 2;
e6e5ad80 1944 }
fd4aa979 1945 memory_region_set_dirty(&s->vga.vram, offset, 16);
e6e5ad80
FB		 1946}
1947
1948/***************************************
1949 *
1950 * memory access between 0xa0000-0xbffff
1951 *
1952 ***************************************/
1953
a815b166 1954static uint64_t cirrus_vga_mem_read(void *opaque,
a8170e5e 1955 hwaddr addr,
a815b166 1956 uint32_t size)
e6e5ad80
FB		 1957{
1958 CirrusVGAState *s = opaque;
1959 unsigned bank_index;
1960 unsigned bank_offset;
1961 uint32_t val;
1962
4e12cd94 1963 if ((s->vga.sr[0x07] & 0x01) == 0) {
b2a5e761 1964 return vga_mem_readb(&s->vga, addr);
e6e5ad80
FB		 1965 }
1966
1967 if (addr < 0x10000) {
1968 /* XXX handle bitblt */
1969 /* video memory */
1970 bank_index = addr >> 15;
1971 bank_offset = addr & 0x7fff;
1972 if (bank_offset < s->cirrus_bank_limit[bank_index]) {
1973 bank_offset += s->cirrus_bank_base[bank_index];
4e12cd94 1974 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
e6e5ad80 1975 bank_offset <<= 4;
4e12cd94 1976 } else if (s->vga.gr[0x0B] & 0x02) {
e6e5ad80
FB		 1977 bank_offset <<= 3;
1978 }
1979 bank_offset &= s->cirrus_addr_mask;
4e12cd94 1980 val = *(s->vga.vram_ptr + bank_offset);
e6e5ad80
FB		 1981 } else
1982 val = 0xff;
1983 } else if (addr >= 0x18000 && addr < 0x18100) {
1984 /* memory-mapped I/O */
1985 val = 0xff;
4e12cd94 1986 if ((s->vga.sr[0x17] & 0x44) == 0x04) {
e6e5ad80
FB		 1987 val = cirrus_mmio_blt_read(s, addr & 0xff);
1988 }
1989 } else {
1990 val = 0xff;
1991#ifdef DEBUG_CIRRUS
0bf9e31a 1992 printf("cirrus: mem_readb " TARGET_FMT_plx "\n", addr);
e6e5ad80
FB		 1993#endif
1994 }
1995 return val;
1996}
1997
a815b166 1998static void cirrus_vga_mem_write(void *opaque,
a8170e5e 1999 hwaddr addr,
a815b166
AK		 2000 uint64_t mem_value,
2001 uint32_t size)
e6e5ad80
FB		 2002{
2003 CirrusVGAState *s = opaque;
2004 unsigned bank_index;
2005 unsigned bank_offset;
2006 unsigned mode;
2007
4e12cd94 2008 if ((s->vga.sr[0x07] & 0x01) == 0) {
b2a5e761 2009 vga_mem_writeb(&s->vga, addr, mem_value);
e6e5ad80
FB		 2010 return;
2011 }
2012
2013 if (addr < 0x10000) {
2014 if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2015 /* bitblt */
2016 *s->cirrus_srcptr++ = (uint8_t) mem_value;
a5082316 2017 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
e6e5ad80
FB		 2018 cirrus_bitblt_cputovideo_next(s);
2019 }
2020 } else {
2021 /* video memory */
2022 bank_index = addr >> 15;
2023 bank_offset = addr & 0x7fff;
2024 if (bank_offset < s->cirrus_bank_limit[bank_index]) {
2025 bank_offset += s->cirrus_bank_base[bank_index];
4e12cd94 2026 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
e6e5ad80 2027 bank_offset <<= 4;
4e12cd94 2028 } else if (s->vga.gr[0x0B] & 0x02) {
e6e5ad80
FB		 2029 bank_offset <<= 3;
2030 }
2031 bank_offset &= s->cirrus_addr_mask;
4e12cd94
AK		 2032 mode = s->vga.gr[0x05] & 0x7;
2033 if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) {
2034 *(s->vga.vram_ptr + bank_offset) = mem_value;
fd4aa979
BS		 2035 memory_region_set_dirty(&s->vga.vram, bank_offset,
2036 sizeof(mem_value));
e6e5ad80 2037 } else {
4e12cd94 2038 if ((s->vga.gr[0x0B] & 0x14) != 0x14) {
e6e5ad80
FB		 2039 cirrus_mem_writeb_mode4and5_8bpp(s, mode,
2040 bank_offset,
2041 mem_value);
2042 } else {
2043 cirrus_mem_writeb_mode4and5_16bpp(s, mode,
2044 bank_offset,
2045 mem_value);
2046 }
2047 }
2048 }
2049 }
2050 } else if (addr >= 0x18000 && addr < 0x18100) {
2051 /* memory-mapped I/O */
4e12cd94 2052 if ((s->vga.sr[0x17] & 0x44) == 0x04) {
e6e5ad80
FB		 2053 cirrus_mmio_blt_write(s, addr & 0xff, mem_value);
2054 }
2055 } else {
2056#ifdef DEBUG_CIRRUS
08406b03 2057 printf("cirrus: mem_writeb " TARGET_FMT_plx " value %02x\n", addr,
2058 mem_value);
e6e5ad80
FB		 2059#endif
2060 }
2061}
2062
b1950430
AK		 2063static const MemoryRegionOps cirrus_vga_mem_ops = {
2064 .read = cirrus_vga_mem_read,
2065 .write = cirrus_vga_mem_write,
2066 .endianness = DEVICE_LITTLE_ENDIAN,
a815b166
AK		 2067 .impl = {
2068 .min_access_size = 1,
2069 .max_access_size = 1,
2070 },
e6e5ad80
FB		 2071};
2072
a5082316
FB		 2073/***************************************
2074 *
2075 * hardware cursor
2076 *
2077 ***************************************/
2078
2079static inline void invalidate_cursor1(CirrusVGAState *s)
2080{
2081 if (s->last_hw_cursor_size) {
4e12cd94 2082 vga_invalidate_scanlines(&s->vga,
a5082316
FB		 2083 s->last_hw_cursor_y + s->last_hw_cursor_y_start,
2084 s->last_hw_cursor_y + s->last_hw_cursor_y_end);
2085 }
2086}
2087
2088static inline void cirrus_cursor_compute_yrange(CirrusVGAState *s)
2089{
2090 const uint8_t *src;
2091 uint32_t content;
2092 int y, y_min, y_max;
2093
4e12cd94
AK		 2094 src = s->vga.vram_ptr + s->real_vram_size - 16 * 1024;
2095 if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) {
2096 src += (s->vga.sr[0x13] & 0x3c) * 256;
a5082316
FB		 2097 y_min = 64;
2098 y_max = -1;
2099 for(y = 0; y < 64; y++) {
2100 content = ((uint32_t *)src)[0] |
2101 ((uint32_t *)src)[1] |
2102 ((uint32_t *)src)[2] |
2103 ((uint32_t *)src)[3];
2104 if (content) {
2105 if (y < y_min)
2106 y_min = y;
2107 if (y > y_max)
2108 y_max = y;
2109 }
2110 src += 16;
2111 }
2112 } else {
4e12cd94 2113 src += (s->vga.sr[0x13] & 0x3f) * 256;
a5082316
FB		 2114 y_min = 32;
2115 y_max = -1;
2116 for(y = 0; y < 32; y++) {
2117 content = ((uint32_t *)src)[0] |
2118 ((uint32_t *)(src + 128))[0];
2119 if (content) {
2120 if (y < y_min)
2121 y_min = y;
2122 if (y > y_max)
2123 y_max = y;
2124 }
2125 src += 4;
2126 }
2127 }
2128 if (y_min > y_max) {
2129 s->last_hw_cursor_y_start = 0;
2130 s->last_hw_cursor_y_end = 0;
2131 } else {
2132 s->last_hw_cursor_y_start = y_min;
2133 s->last_hw_cursor_y_end = y_max + 1;
2134 }
2135}
2136
2137/* NOTE: we do not currently handle the cursor bitmap change, so we
2138 update the cursor only if it moves. */
a4a2f59c 2139static void cirrus_cursor_invalidate(VGACommonState *s1)
a5082316 2140{
4e12cd94 2141 CirrusVGAState *s = container_of(s1, CirrusVGAState, vga);
a5082316
FB		 2142 int size;
2143
4e12cd94 2144 if (!(s->vga.sr[0x12] & CIRRUS_CURSOR_SHOW)) {
a5082316
FB		 2145 size = 0;
2146 } else {
4e12cd94 2147 if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE)
a5082316
FB		 2148 size = 64;
2149 else
2150 size = 32;
2151 }
2152 /* invalidate last cursor and new cursor if any change */
2153 if (s->last_hw_cursor_size != size ||
2154 s->last_hw_cursor_x != s->hw_cursor_x ||
2155 s->last_hw_cursor_y != s->hw_cursor_y) {
2156
2157 invalidate_cursor1(s);
3b46e624 2158
a5082316
FB		 2159 s->last_hw_cursor_size = size;
2160 s->last_hw_cursor_x = s->hw_cursor_x;
2161 s->last_hw_cursor_y = s->hw_cursor_y;
2162 /* compute the real cursor min and max y */
2163 cirrus_cursor_compute_yrange(s);
2164 invalidate_cursor1(s);
2165 }
2166}
2167
94d7b483 2168#define DEPTH 8
47b43a1f 2169#include "cirrus_vga_template.h"
94d7b483
BS		 2170
2171#define DEPTH 16
47b43a1f 2172#include "cirrus_vga_template.h"
94d7b483
BS		 2173
2174#define DEPTH 32
47b43a1f 2175#include "cirrus_vga_template.h"
94d7b483 2176
a4a2f59c 2177static void cirrus_cursor_draw_line(VGACommonState *s1, uint8_t *d1, int scr_y)
a5082316 2178{
4e12cd94 2179 CirrusVGAState *s = container_of(s1, CirrusVGAState, vga);
c78f7137 2180 DisplaySurface *surface = qemu_console_surface(s->vga.con);
a5082316
FB		 2181 int w, h, bpp, x1, x2, poffset;
2182 unsigned int color0, color1;
2183 const uint8_t *palette, *src;
2184 uint32_t content;
3b46e624 2185
4e12cd94 2186 if (!(s->vga.sr[0x12] & CIRRUS_CURSOR_SHOW))
a5082316
FB		 2187 return;
2188 /* fast test to see if the cursor intersects with the scan line */
4e12cd94 2189 if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) {
a5082316
FB		 2190 h = 64;
2191 } else {
2192 h = 32;
2193 }
2194 if (scr_y < s->hw_cursor_y ||
2195 scr_y >= (s->hw_cursor_y + h))
2196 return;
3b46e624 2197
4e12cd94
AK		 2198 src = s->vga.vram_ptr + s->real_vram_size - 16 * 1024;
2199 if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) {
2200 src += (s->vga.sr[0x13] & 0x3c) * 256;
a5082316
FB		 2201 src += (scr_y - s->hw_cursor_y) * 16;
2202 poffset = 8;
2203 content = ((uint32_t *)src)[0] |
2204 ((uint32_t *)src)[1] |
2205 ((uint32_t *)src)[2] |
2206 ((uint32_t *)src)[3];
2207 } else {
4e12cd94 2208 src += (s->vga.sr[0x13] & 0x3f) * 256;
a5082316
FB		 2209 src += (scr_y - s->hw_cursor_y) * 4;
2210 poffset = 128;
2211 content = ((uint32_t *)src)[0] |
2212 ((uint32_t *)(src + 128))[0];
2213 }
2214 /* if nothing to draw, no need to continue */
2215 if (!content)
2216 return;
2217 w = h;
2218
2219 x1 = s->hw_cursor_x;
4e12cd94 2220 if (x1 >= s->vga.last_scr_width)
a5082316
FB		 2221 return;
2222 x2 = s->hw_cursor_x + w;
4e12cd94
AK		 2223 if (x2 > s->vga.last_scr_width)
2224 x2 = s->vga.last_scr_width;
a5082316
FB		 2225 w = x2 - x1;
2226 palette = s->cirrus_hidden_palette;
4e12cd94
AK		 2227 color0 = s->vga.rgb_to_pixel(c6_to_8(palette[0x0 * 3]),
2228 c6_to_8(palette[0x0 * 3 + 1]),
2229 c6_to_8(palette[0x0 * 3 + 2]));
2230 color1 = s->vga.rgb_to_pixel(c6_to_8(palette[0xf * 3]),
2231 c6_to_8(palette[0xf * 3 + 1]),
2232 c6_to_8(palette[0xf * 3 + 2]));
c78f7137 2233 bpp = surface_bytes_per_pixel(surface);
a5082316 2234 d1 += x1 * bpp;
c78f7137 2235 switch (surface_bits_per_pixel(surface)) {
a5082316
FB		 2236 default:
2237 break;
2238 case 8:
2239 vga_draw_cursor_line_8(d1, src, poffset, w, color0, color1, 0xff);
2240 break;
2241 case 15:
2242 vga_draw_cursor_line_16(d1, src, poffset, w, color0, color1, 0x7fff);
2243 break;
2244 case 16:
2245 vga_draw_cursor_line_16(d1, src, poffset, w, color0, color1, 0xffff);
2246 break;
2247 case 32:
2248 vga_draw_cursor_line_32(d1, src, poffset, w, color0, color1, 0xffffff);
2249 break;
2250 }
2251}
2252
e6e5ad80
FB		 2253/***************************************
2254 *
2255 * LFB memory access
2256 *
2257 ***************************************/
2258
a8170e5e 2259static uint64_t cirrus_linear_read(void *opaque, hwaddr addr,
899adf81 2260 unsigned size)
e6e5ad80 2261{
e05587e8 2262 CirrusVGAState *s = opaque;
e6e5ad80
FB		 2263 uint32_t ret;
2264
e6e5ad80
FB		 2265 addr &= s->cirrus_addr_mask;
2266
4e12cd94 2267 if (((s->vga.sr[0x17] & 0x44) == 0x44) &&
78e127ef 2268 ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) {
e6e5ad80
FB		 2269 /* memory-mapped I/O */
2270 ret = cirrus_mmio_blt_read(s, addr & 0xff);
2271 } else if (0) {
2272 /* XXX handle bitblt */
2273 ret = 0xff;
2274 } else {
2275 /* video memory */
4e12cd94 2276 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
e6e5ad80 2277 addr <<= 4;
4e12cd94 2278 } else if (s->vga.gr[0x0B] & 0x02) {
e6e5ad80
FB		 2279 addr <<= 3;
2280 }
2281 addr &= s->cirrus_addr_mask;
4e12cd94 2282 ret = *(s->vga.vram_ptr + addr);
e6e5ad80
FB		 2283 }
2284
2285 return ret;
2286}
2287
a8170e5e 2288static void cirrus_linear_write(void *opaque, hwaddr addr,
899adf81 2289 uint64_t val, unsigned size)
e6e5ad80 2290{
e05587e8 2291 CirrusVGAState *s = opaque;
e6e5ad80
FB		 2292 unsigned mode;
2293
2294 addr &= s->cirrus_addr_mask;
3b46e624 2295
4e12cd94 2296 if (((s->vga.sr[0x17] & 0x44) == 0x44) &&
78e127ef 2297 ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) {
e6e5ad80
FB		 2298 /* memory-mapped I/O */
2299 cirrus_mmio_blt_write(s, addr & 0xff, val);
2300 } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2301 /* bitblt */
2302 *s->cirrus_srcptr++ = (uint8_t) val;
a5082316 2303 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
e6e5ad80
FB		 2304 cirrus_bitblt_cputovideo_next(s);
2305 }
2306 } else {
2307 /* video memory */
4e12cd94 2308 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
e6e5ad80 2309 addr <<= 4;
4e12cd94 2310 } else if (s->vga.gr[0x0B] & 0x02) {
e6e5ad80
FB		 2311 addr <<= 3;
2312 }
2313 addr &= s->cirrus_addr_mask;
2314
4e12cd94
AK		 2315 mode = s->vga.gr[0x05] & 0x7;
2316 if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) {
2317 *(s->vga.vram_ptr + addr) = (uint8_t) val;
fd4aa979 2318 memory_region_set_dirty(&s->vga.vram, addr, 1);
e6e5ad80 2319 } else {
4e12cd94 2320 if ((s->vga.gr[0x0B] & 0x14) != 0x14) {
e6e5ad80
FB		 2321 cirrus_mem_writeb_mode4and5_8bpp(s, mode, addr, val);
2322 } else {
2323 cirrus_mem_writeb_mode4and5_16bpp(s, mode, addr, val);
2324 }
2325 }
2326 }
2327}
2328
a5082316
FB		 2329/***************************************
2330 *
2331 * system to screen memory access
2332 *
2333 ***************************************/
2334
2335
4e56f089 2336static uint64_t cirrus_linear_bitblt_read(void *opaque,
a8170e5e 2337 hwaddr addr,
4e56f089 2338 unsigned size)
a5082316 2339{
4e56f089 2340 CirrusVGAState *s = opaque;
a5082316
FB		 2341 uint32_t ret;
2342
2343 /* XXX handle bitblt */
4e56f089 2344 (void)s;
a5082316
FB		 2345 ret = 0xff;
2346 return ret;
2347}
2348
4e56f089 2349static void cirrus_linear_bitblt_write(void *opaque,
a8170e5e 2350 hwaddr addr,
4e56f089
AK		 2351 uint64_t val,
2352 unsigned size)
a5082316 2353{
e05587e8 2354 CirrusVGAState *s = opaque;
a5082316
FB		 2355
2356 if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2357 /* bitblt */
2358 *s->cirrus_srcptr++ = (uint8_t) val;
2359 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
2360 cirrus_bitblt_cputovideo_next(s);
2361 }
2362 }
2363}
2364
b1950430
AK		 2365static const MemoryRegionOps cirrus_linear_bitblt_io_ops = {
2366 .read = cirrus_linear_bitblt_read,
2367 .write = cirrus_linear_bitblt_write,
2368 .endianness = DEVICE_LITTLE_ENDIAN,
4e56f089
AK		 2369 .impl = {
2370 .min_access_size = 1,
2371 .max_access_size = 1,
2372 },
a5082316
FB		 2373};
2374
b1950430
AK		 2375static void map_linear_vram_bank(CirrusVGAState *s, unsigned bank)
2376{
7969d9ed
AK		 2377 MemoryRegion *mr = &s->cirrus_bank[bank];
2378 bool enabled = !(s->cirrus_srcptr != s->cirrus_srcptr_end)
4e12cd94
AK		 2379 && !((s->vga.sr[0x07] & 0x01) == 0)
2380 && !((s->vga.gr[0x0B] & 0x14) == 0x14)
7969d9ed
AK		 2381 && !(s->vga.gr[0x0B] & 0x02);
2382
2383 memory_region_set_enabled(mr, enabled);
2384 memory_region_set_alias_offset(mr, s->cirrus_bank_base[bank]);
b1950430 2385}
2bec46dc 2386
b1950430
AK		 2387static void map_linear_vram(CirrusVGAState *s)
2388{
4c08fd1e 2389 if (s->bustype == CIRRUS_BUSTYPE_PCI && !s->linear_vram) {
b1950430
AK		 2390 s->linear_vram = true;
2391 memory_region_add_subregion_overlap(&s->pci_bar, 0, &s->vga.vram, 1);
2392 }
2393 map_linear_vram_bank(s, 0);
2394 map_linear_vram_bank(s, 1);
2bec46dc
AL		 2395}
2396
2397static void unmap_linear_vram(CirrusVGAState *s)
2398{
4c08fd1e 2399 if (s->bustype == CIRRUS_BUSTYPE_PCI && s->linear_vram) {
b1950430
AK		 2400 s->linear_vram = false;
2401 memory_region_del_subregion(&s->pci_bar, &s->vga.vram);
4516e45f 2402 }
7969d9ed
AK		 2403 memory_region_set_enabled(&s->cirrus_bank[0], false);
2404 memory_region_set_enabled(&s->cirrus_bank[1], false);
2bec46dc
AL		 2405}
2406
8926b517
FB		 2407/* Compute the memory access functions */
2408static void cirrus_update_memory_access(CirrusVGAState *s)
2409{
2410 unsigned mode;
2411
64c048f4 2412 memory_region_transaction_begin();
4e12cd94 2413 if ((s->vga.sr[0x17] & 0x44) == 0x44) {
8926b517
FB		 2414 goto generic_io;
2415 } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2416 goto generic_io;
2417 } else {
4e12cd94 2418 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
8926b517 2419 goto generic_io;
4e12cd94 2420 } else if (s->vga.gr[0x0B] & 0x02) {
8926b517
FB		 2421 goto generic_io;
2422 }
3b46e624 2423
4e12cd94
AK		 2424 mode = s->vga.gr[0x05] & 0x7;
2425 if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) {
2bec46dc 2426 map_linear_vram(s);
8926b517
FB		 2427 } else {
2428 generic_io:
2bec46dc 2429 unmap_linear_vram(s);
8926b517
FB		 2430 }
2431 }
64c048f4 2432 memory_region_transaction_commit();
8926b517
FB		 2433}
2434
2435
e6e5ad80
FB		 2436/* I/O ports */
2437
c75e6d8e
JG		 2438static uint64_t cirrus_vga_ioport_read(void *opaque, hwaddr addr,
2439 unsigned size)
e6e5ad80 2440{
b6343073
JQ		 2441 CirrusVGAState *c = opaque;
2442 VGACommonState *s = &c->vga;
e6e5ad80
FB		 2443 int val, index;
2444
bd8f2f5d 2445 qemu_flush_coalesced_mmio_buffer();
c75e6d8e 2446 addr += 0x3b0;
bd8f2f5d 2447
b6343073 2448 if (vga_ioport_invalid(s, addr)) {
e6e5ad80
FB		 2449 val = 0xff;
2450 } else {
2451 switch (addr) {
2452 case 0x3c0:
b6343073
JQ		 2453 if (s->ar_flip_flop == 0) {
2454 val = s->ar_index;
e6e5ad80
FB		 2455 } else {
2456 val = 0;
2457 }
2458 break;
2459 case 0x3c1:
b6343073 2460 index = s->ar_index & 0x1f;
e6e5ad80 2461 if (index < 21)
b6343073 2462 val = s->ar[index];
e6e5ad80
FB		 2463 else
2464 val = 0;
2465 break;
2466 case 0x3c2:
b6343073 2467 val = s->st00;
e6e5ad80
FB		 2468 break;
2469 case 0x3c4:
b6343073 2470 val = s->sr_index;
e6e5ad80
FB		 2471 break;
2472 case 0x3c5:
8a82c322
JQ		 2473 val = cirrus_vga_read_sr(c);
2474 break;
e6e5ad80 2475#ifdef DEBUG_VGA_REG
b6343073 2476 printf("vga: read SR%x = 0x%02x\n", s->sr_index, val);
e6e5ad80
FB		 2477#endif
2478 break;
2479 case 0x3c6:
957c9db5 2480 val = cirrus_read_hidden_dac(c);
e6e5ad80
FB		 2481 break;
2482 case 0x3c7:
b6343073 2483 val = s->dac_state;
e6e5ad80 2484 break;
ae184e4a 2485 case 0x3c8:
b6343073
JQ		 2486 val = s->dac_write_index;
2487 c->cirrus_hidden_dac_lockindex = 0;
ae184e4a
FB		 2488 break;
2489 case 0x3c9:
5deaeee3
JQ		 2490 val = cirrus_vga_read_palette(c);
2491 break;
e6e5ad80 2492 case 0x3ca:
b6343073 2493 val = s->fcr;
e6e5ad80
FB		 2494 break;
2495 case 0x3cc:
b6343073 2496 val = s->msr;
e6e5ad80
FB		 2497 break;
2498 case 0x3ce:
b6343073 2499 val = s->gr_index;
e6e5ad80
FB		 2500 break;
2501 case 0x3cf:
f705db9d 2502 val = cirrus_vga_read_gr(c, s->gr_index);
e6e5ad80 2503#ifdef DEBUG_VGA_REG
b6343073 2504 printf("vga: read GR%x = 0x%02x\n", s->gr_index, val);
e6e5ad80
FB		 2505#endif
2506 break;
2507 case 0x3b4:
2508 case 0x3d4:
b6343073 2509 val = s->cr_index;
e6e5ad80
FB		 2510 break;
2511 case 0x3b5:
2512 case 0x3d5:
b863d514 2513 val = cirrus_vga_read_cr(c, s->cr_index);
e6e5ad80 2514#ifdef DEBUG_VGA_REG
b6343073 2515 printf("vga: read CR%x = 0x%02x\n", s->cr_index, val);
e6e5ad80
FB		 2516#endif
2517 break;
2518 case 0x3ba:
2519 case 0x3da:
2520 /* just toggle to fool polling */
b6343073
JQ		 2521 val = s->st01 = s->retrace(s);
2522 s->ar_flip_flop = 0;
e6e5ad80
FB		 2523 break;
2524 default:
2525 val = 0x00;
2526 break;
2527 }
2528 }
2529#if defined(DEBUG_VGA)
2530 printf("VGA: read addr=0x%04x data=0x%02x\n", addr, val);
2531#endif
2532 return val;
2533}
2534
c75e6d8e
JG		 2535static void cirrus_vga_ioport_write(void *opaque, hwaddr addr, uint64_t val,
2536 unsigned size)
e6e5ad80 2537{
b6343073
JQ		 2538 CirrusVGAState *c = opaque;
2539 VGACommonState *s = &c->vga;
e6e5ad80
FB		 2540 int index;
2541
bd8f2f5d 2542 qemu_flush_coalesced_mmio_buffer();
c75e6d8e 2543 addr += 0x3b0;
bd8f2f5d 2544
e6e5ad80 2545 /* check port range access depending on color/monochrome mode */
b6343073 2546 if (vga_ioport_invalid(s, addr)) {
e6e5ad80 2547 return;
25a18cbd 2548 }
e6e5ad80
FB		 2549#ifdef DEBUG_VGA
2550 printf("VGA: write addr=0x%04x data=0x%02x\n", addr, val);
2551#endif
2552
2553 switch (addr) {
2554 case 0x3c0:
b6343073 2555 if (s->ar_flip_flop == 0) {
e6e5ad80 2556 val &= 0x3f;
b6343073 2557 s->ar_index = val;
e6e5ad80 2558 } else {
b6343073 2559 index = s->ar_index & 0x1f;
e6e5ad80
FB		 2560 switch (index) {
2561 case 0x00 ... 0x0f:
b6343073 2562 s->ar[index] = val & 0x3f;
e6e5ad80
FB		 2563 break;
2564 case 0x10:
b6343073 2565 s->ar[index] = val & ~0x10;
e6e5ad80
FB		 2566 break;
2567 case 0x11:
b6343073 2568 s->ar[index] = val;
e6e5ad80
FB		 2569 break;
2570 case 0x12:
b6343073 2571 s->ar[index] = val & ~0xc0;
e6e5ad80
FB		 2572 break;
2573 case 0x13:
b6343073 2574 s->ar[index] = val & ~0xf0;
e6e5ad80
FB		 2575 break;
2576 case 0x14:
b6343073 2577 s->ar[index] = val & ~0xf0;
e6e5ad80
FB		 2578 break;
2579 default:
2580 break;
2581 }
2582 }
b6343073 2583 s->ar_flip_flop ^= 1;
e6e5ad80
FB		 2584 break;
2585 case 0x3c2:
b6343073
JQ		 2586 s->msr = val & ~0x10;
2587 s->update_retrace_info(s);
e6e5ad80
FB		 2588 break;
2589 case 0x3c4:
b6343073 2590 s->sr_index = val;
e6e5ad80
FB		 2591 break;
2592 case 0x3c5:
e6e5ad80 2593#ifdef DEBUG_VGA_REG
b6343073 2594 printf("vga: write SR%x = 0x%02x\n", s->sr_index, val);
e6e5ad80 2595#endif
31c63201
JQ		 2596 cirrus_vga_write_sr(c, val);
2597 break;
e6e5ad80
FB		 2598 break;
2599 case 0x3c6:
b6343073 2600 cirrus_write_hidden_dac(c, val);
e6e5ad80
FB		 2601 break;
2602 case 0x3c7:
b6343073
JQ		 2603 s->dac_read_index = val;
2604 s->dac_sub_index = 0;
2605 s->dac_state = 3;
e6e5ad80
FB		 2606 break;
2607 case 0x3c8:
b6343073
JQ		 2608 s->dac_write_index = val;
2609 s->dac_sub_index = 0;
2610 s->dac_state = 0;
e6e5ad80
FB		 2611 break;
2612 case 0x3c9:
86948bb1
JQ		 2613 cirrus_vga_write_palette(c, val);
2614 break;
e6e5ad80 2615 case 0x3ce:
b6343073 2616 s->gr_index = val;
e6e5ad80
FB		 2617 break;
2618 case 0x3cf:
e6e5ad80 2619#ifdef DEBUG_VGA_REG
b6343073 2620 printf("vga: write GR%x = 0x%02x\n", s->gr_index, val);
e6e5ad80 2621#endif
22286bc6 2622 cirrus_vga_write_gr(c, s->gr_index, val);
e6e5ad80
FB		 2623 break;
2624 case 0x3b4:
2625 case 0x3d4:
b6343073 2626 s->cr_index = val;
e6e5ad80
FB		 2627 break;
2628 case 0x3b5:
2629 case 0x3d5:
e6e5ad80 2630#ifdef DEBUG_VGA_REG
b6343073 2631 printf("vga: write CR%x = 0x%02x\n", s->cr_index, val);
e6e5ad80 2632#endif
4ec1ce04 2633 cirrus_vga_write_cr(c, val);
e6e5ad80
FB		 2634 break;
2635 case 0x3ba:
2636 case 0x3da:
b6343073 2637 s->fcr = val & 0x10;
e6e5ad80
FB		 2638 break;
2639 }
2640}
2641
e36f36e1
FB		 2642/***************************************
2643 *
2644 * memory-mapped I/O access
2645 *
2646 ***************************************/
2647
a8170e5e 2648static uint64_t cirrus_mmio_read(void *opaque, hwaddr addr,
1e04d4d6 2649 unsigned size)
e36f36e1 2650{
e05587e8 2651 CirrusVGAState *s = opaque;
e36f36e1 2652
e36f36e1
FB		 2653 if (addr >= 0x100) {
2654 return cirrus_mmio_blt_read(s, addr - 0x100);
2655 } else {
c75e6d8e 2656 return cirrus_vga_ioport_read(s, addr + 0x10, size);
e36f36e1
FB		 2657 }
2658}
2659
a8170e5e 2660static void cirrus_mmio_write(void *opaque, hwaddr addr,
1e04d4d6 2661 uint64_t val, unsigned size)
e36f36e1 2662{
e05587e8 2663 CirrusVGAState *s = opaque;
e36f36e1 2664
e36f36e1
FB		 2665 if (addr >= 0x100) {
2666 cirrus_mmio_blt_write(s, addr - 0x100, val);
2667 } else {
c75e6d8e 2668 cirrus_vga_ioport_write(s, addr + 0x10, val, size);
e36f36e1
FB		 2669 }
2670}
2671
b1950430
AK		 2672static const MemoryRegionOps cirrus_mmio_io_ops = {
2673 .read = cirrus_mmio_read,
2674 .write = cirrus_mmio_write,
2675 .endianness = DEVICE_LITTLE_ENDIAN,
1e04d4d6
AK		 2676 .impl = {
2677 .min_access_size = 1,
2678 .max_access_size = 1,
2679 },
e36f36e1
FB		 2680};
2681
2c6ab832
FB		 2682/* load/save state */
2683
e59fb374 2684static int cirrus_post_load(void *opaque, int version_id)
2c6ab832
FB		 2685{
2686 CirrusVGAState *s = opaque;
2687
4e12cd94
AK		 2688 s->vga.gr[0x00] = s->cirrus_shadow_gr0 & 0x0f;
2689 s->vga.gr[0x01] = s->cirrus_shadow_gr1 & 0x0f;
2c6ab832 2690
2bec46dc 2691 cirrus_update_memory_access(s);
2c6ab832 2692 /* force refresh */
4e12cd94 2693 s->vga.graphic_mode = -1;
2c6ab832
FB		 2694 cirrus_update_bank_ptr(s, 0);
2695 cirrus_update_bank_ptr(s, 1);
2696 return 0;
2697}
2698
7e72abc3
JQ		 2699static const VMStateDescription vmstate_cirrus_vga = {
2700 .name = "cirrus_vga",
2701 .version_id = 2,
2702 .minimum_version_id = 1,
2703 .minimum_version_id_old = 1,
2704 .post_load = cirrus_post_load,
2705 .fields = (VMStateField []) {
2706 VMSTATE_UINT32(vga.latch, CirrusVGAState),
2707 VMSTATE_UINT8(vga.sr_index, CirrusVGAState),
2708 VMSTATE_BUFFER(vga.sr, CirrusVGAState),
2709 VMSTATE_UINT8(vga.gr_index, CirrusVGAState),
2710 VMSTATE_UINT8(cirrus_shadow_gr0, CirrusVGAState),
2711 VMSTATE_UINT8(cirrus_shadow_gr1, CirrusVGAState),
2712 VMSTATE_BUFFER_START_MIDDLE(vga.gr, CirrusVGAState, 2),
2713 VMSTATE_UINT8(vga.ar_index, CirrusVGAState),
2714 VMSTATE_BUFFER(vga.ar, CirrusVGAState),
2715 VMSTATE_INT32(vga.ar_flip_flop, CirrusVGAState),
2716 VMSTATE_UINT8(vga.cr_index, CirrusVGAState),
2717 VMSTATE_BUFFER(vga.cr, CirrusVGAState),
2718 VMSTATE_UINT8(vga.msr, CirrusVGAState),
2719 VMSTATE_UINT8(vga.fcr, CirrusVGAState),
2720 VMSTATE_UINT8(vga.st00, CirrusVGAState),
2721 VMSTATE_UINT8(vga.st01, CirrusVGAState),
2722 VMSTATE_UINT8(vga.dac_state, CirrusVGAState),
2723 VMSTATE_UINT8(vga.dac_sub_index, CirrusVGAState),
2724 VMSTATE_UINT8(vga.dac_read_index, CirrusVGAState),
2725 VMSTATE_UINT8(vga.dac_write_index, CirrusVGAState),
2726 VMSTATE_BUFFER(vga.dac_cache, CirrusVGAState),
2727 VMSTATE_BUFFER(vga.palette, CirrusVGAState),
2728 VMSTATE_INT32(vga.bank_offset, CirrusVGAState),
2729 VMSTATE_UINT8(cirrus_hidden_dac_lockindex, CirrusVGAState),
2730 VMSTATE_UINT8(cirrus_hidden_dac_data, CirrusVGAState),
2731 VMSTATE_UINT32(hw_cursor_x, CirrusVGAState),
2732 VMSTATE_UINT32(hw_cursor_y, CirrusVGAState),
2733 /* XXX: we do not save the bitblt state - we assume we do not save
2734 the state when the blitter is active */
2735 VMSTATE_END_OF_LIST()
4f335feb 2736 }
7e72abc3 2737};
4f335feb 2738
7e72abc3
JQ		 2739static const VMStateDescription vmstate_pci_cirrus_vga = {
2740 .name = "cirrus_vga",
2741 .version_id = 2,
2742 .minimum_version_id = 2,
2743 .minimum_version_id_old = 2,
7e72abc3
JQ		 2744 .fields = (VMStateField []) {
2745 VMSTATE_PCI_DEVICE(dev, PCICirrusVGAState),
2746 VMSTATE_STRUCT(cirrus_vga, PCICirrusVGAState, 0,
2747 vmstate_cirrus_vga, CirrusVGAState),
2748 VMSTATE_END_OF_LIST()
2749 }
2750};
4f335feb 2751
e6e5ad80
FB		 2752/***************************************
2753 *
2754 * initialize
2755 *
2756 ***************************************/
2757
4abc796d 2758static void cirrus_reset(void *opaque)
e6e5ad80 2759{
4abc796d 2760 CirrusVGAState *s = opaque;
e6e5ad80 2761
03a3e7ba 2762 vga_common_reset(&s->vga);
ee50c6bc 2763 unmap_linear_vram(s);
4e12cd94 2764 s->vga.sr[0x06] = 0x0f;
4abc796d 2765 if (s->device_id == CIRRUS_ID_CLGD5446) {
78e127ef 2766 /* 4MB 64 bit memory config, always PCI */
4e12cd94
AK		 2767 s->vga.sr[0x1F] = 0x2d; // MemClock
2768 s->vga.gr[0x18] = 0x0f; // fastest memory configuration
2769 s->vga.sr[0x0f] = 0x98;
2770 s->vga.sr[0x17] = 0x20;
2771 s->vga.sr[0x15] = 0x04; /* memory size, 3=2MB, 4=4MB */
78e127ef 2772 } else {
4e12cd94
AK		 2773 s->vga.sr[0x1F] = 0x22; // MemClock
2774 s->vga.sr[0x0F] = CIRRUS_MEMSIZE_2M;
2775 s->vga.sr[0x17] = s->bustype;
2776 s->vga.sr[0x15] = 0x03; /* memory size, 3=2MB, 4=4MB */
78e127ef 2777 }
4e12cd94 2778 s->vga.cr[0x27] = s->device_id;
e6e5ad80
FB		 2779
2780 s->cirrus_hidden_dac_lockindex = 5;
2781 s->cirrus_hidden_dac_data = 0;
4abc796d
BS		 2782}
2783
b1950430
AK		 2784static const MemoryRegionOps cirrus_linear_io_ops = {
2785 .read = cirrus_linear_read,
2786 .write = cirrus_linear_write,
2787 .endianness = DEVICE_LITTLE_ENDIAN,
899adf81
AK		 2788 .impl = {
2789 .min_access_size = 1,
2790 .max_access_size = 1,
2791 },
b1950430
AK		 2792};
2793
c75e6d8e
JG		 2794static const MemoryRegionOps cirrus_vga_io_ops = {
2795 .read = cirrus_vga_ioport_read,
2796 .write = cirrus_vga_ioport_write,
2797 .endianness = DEVICE_LITTLE_ENDIAN,
2798 .impl = {
2799 .min_access_size = 1,
2800 .max_access_size = 1,
2801 },
2802};
2803
be20f9e9 2804static void cirrus_init_common(CirrusVGAState * s, int device_id, int is_pci,
c75e6d8e
JG		 2805 MemoryRegion *system_memory,
2806 MemoryRegion *system_io)
4abc796d
BS		 2807{
2808 int i;
2809 static int inited;
2810
2811 if (!inited) {
2812 inited = 1;
2813 for(i = 0;i < 256; i++)
2814 rop_to_index[i] = CIRRUS_ROP_NOP_INDEX; /* nop rop */
2815 rop_to_index[CIRRUS_ROP_0] = 0;
2816 rop_to_index[CIRRUS_ROP_SRC_AND_DST] = 1;
2817 rop_to_index[CIRRUS_ROP_NOP] = 2;
2818 rop_to_index[CIRRUS_ROP_SRC_AND_NOTDST] = 3;
2819 rop_to_index[CIRRUS_ROP_NOTDST] = 4;
2820 rop_to_index[CIRRUS_ROP_SRC] = 5;
2821 rop_to_index[CIRRUS_ROP_1] = 6;
2822 rop_to_index[CIRRUS_ROP_NOTSRC_AND_DST] = 7;
2823 rop_to_index[CIRRUS_ROP_SRC_XOR_DST] = 8;
2824 rop_to_index[CIRRUS_ROP_SRC_OR_DST] = 9;
2825 rop_to_index[CIRRUS_ROP_NOTSRC_OR_NOTDST] = 10;
2826 rop_to_index[CIRRUS_ROP_SRC_NOTXOR_DST] = 11;
2827 rop_to_index[CIRRUS_ROP_SRC_OR_NOTDST] = 12;
2828 rop_to_index[CIRRUS_ROP_NOTSRC] = 13;
2829 rop_to_index[CIRRUS_ROP_NOTSRC_OR_DST] = 14;
2830 rop_to_index[CIRRUS_ROP_NOTSRC_AND_NOTDST] = 15;
2831 s->device_id = device_id;
2832 if (is_pci)
2833 s->bustype = CIRRUS_BUSTYPE_PCI;
2834 else
2835 s->bustype = CIRRUS_BUSTYPE_ISA;
2836 }
2837
c75e6d8e
JG		 2838 /* Register ioport 0x3b0 - 0x3df */
2839 memory_region_init_io(&s->cirrus_vga_io, &cirrus_vga_io_ops, s,
2840 "cirrus-io", 0x30);
2841 memory_region_add_subregion(system_io, 0x3b0, &s->cirrus_vga_io);
4abc796d 2842
b1950430
AK		 2843 memory_region_init(&s->low_mem_container,
2844 "cirrus-lowmem-container",
2845 0x20000);
2846
2847 memory_region_init_io(&s->low_mem, &cirrus_vga_mem_ops, s,
2848 "cirrus-low-memory", 0x20000);
2849 memory_region_add_subregion(&s->low_mem_container, 0, &s->low_mem);
7969d9ed
AK		 2850 for (i = 0; i < 2; ++i) {
2851 static const char *names[] = { "vga.bank0", "vga.bank1" };
2852 MemoryRegion *bank = &s->cirrus_bank[i];
2853 memory_region_init_alias(bank, names[i], &s->vga.vram, 0, 0x8000);
2854 memory_region_set_enabled(bank, false);
2855 memory_region_add_subregion_overlap(&s->low_mem_container, i * 0x8000,
2856 bank, 1);
2857 }
be20f9e9 2858 memory_region_add_subregion_overlap(system_memory,
b1950430
AK		 2859 isa_mem_base + 0x000a0000,
2860 &s->low_mem_container,
2861 1);
2862 memory_region_set_coalescing(&s->low_mem);
2c6ab832 2863
fefe54e3 2864 /* I/O handler for LFB */
b1950430 2865 memory_region_init_io(&s->cirrus_linear_io, &cirrus_linear_io_ops, s,
19403a68
MT		 2866 "cirrus-linear-io", s->vga.vram_size_mb
2867 * 1024 * 1024);
bd8f2f5d 2868 memory_region_set_flush_coalesced(&s->cirrus_linear_io);
fefe54e3
AL		 2869
2870 /* I/O handler for LFB */
b1950430
AK		 2871 memory_region_init_io(&s->cirrus_linear_bitblt_io,
2872 &cirrus_linear_bitblt_io_ops,
2873 s,
2874 "cirrus-bitblt-mmio",
2875 0x400000);
bd8f2f5d 2876 memory_region_set_flush_coalesced(&s->cirrus_linear_bitblt_io);
fefe54e3
AL		 2877
2878 /* I/O handler for memory-mapped I/O */
b1950430
AK		 2879 memory_region_init_io(&s->cirrus_mmio_io, &cirrus_mmio_io_ops, s,
2880 "cirrus-mmio", CIRRUS_PNPMMIO_SIZE);
bd8f2f5d 2881 memory_region_set_flush_coalesced(&s->cirrus_mmio_io);
fefe54e3
AL		 2882
2883 s->real_vram_size =
2884 (s->device_id == CIRRUS_ID_CLGD5446) ? 4096 * 1024 : 2048 * 1024;
2885
4e12cd94 2886 /* XXX: s->vga.vram_size must be a power of two */
fefe54e3
AL		 2887 s->cirrus_addr_mask = s->real_vram_size - 1;
2888 s->linear_mmio_mask = s->real_vram_size - 256;
2889
4e12cd94
AK		 2890 s->vga.get_bpp = cirrus_get_bpp;
2891 s->vga.get_offsets = cirrus_get_offsets;
2892 s->vga.get_resolution = cirrus_get_resolution;
2893 s->vga.cursor_invalidate = cirrus_cursor_invalidate;
2894 s->vga.cursor_draw_line = cirrus_cursor_draw_line;
fefe54e3 2895
a08d4367 2896 qemu_register_reset(cirrus_reset, s);
e6e5ad80
FB		 2897}
2898
2899/***************************************
2900 *
2901 * ISA bus support
2902 *
2903 ***************************************/
2904
3d402831 2905static int vga_initfn(ISADevice *dev)
e6e5ad80 2906{
3d402831
BS		 2907 ISACirrusVGAState *d = DO_UPCAST(ISACirrusVGAState, dev, dev);
2908 VGACommonState *s = &d->cirrus_vga.vga;
2909
4a1e244e 2910 vga_common_init(s);
3d402831 2911 cirrus_init_common(&d->cirrus_vga, CIRRUS_ID_CLGD5430, 0,
c75e6d8e 2912 isa_address_space(dev), isa_address_space_io(dev));
aa2beaa1 2913 s->con = graphic_console_init(DEVICE(dev), s->hw_ops, s);
5245d57a 2914 rom_add_vga(VGABIOS_CIRRUS_FILENAME);
e6e5ad80 2915 /* XXX ISA-LFB support */
ad6d45fa 2916 /* FIXME not qdev yet */
3d402831
BS		 2917 return 0;
2918}
2919
19403a68
MT		 2920static Property isa_vga_cirrus_properties[] = {
2921 DEFINE_PROP_UINT32("vgamem_mb", struct ISACirrusVGAState,
2922 cirrus_vga.vga.vram_size_mb, 8),
2923 DEFINE_PROP_END_OF_LIST(),
2924};
2925
8f04ee08
AL		 2926static void isa_cirrus_vga_class_init(ObjectClass *klass, void *data)
2927{
2928 ISADeviceClass *k = ISA_DEVICE_CLASS(klass);
39bffca2 2929 DeviceClass *dc = DEVICE_CLASS(klass);
8f04ee08 2930
39bffca2
AL		 2931 dc->vmsd = &vmstate_cirrus_vga;
2932 k->init = vga_initfn;
19403a68 2933 dc->props = isa_vga_cirrus_properties;
8f04ee08
AL		 2934}
2935
8c43a6f0 2936static const TypeInfo isa_cirrus_vga_info = {
39bffca2
AL		 2937 .name = "isa-cirrus-vga",
2938 .parent = TYPE_ISA_DEVICE,
2939 .instance_size = sizeof(ISACirrusVGAState),
8f04ee08 2940 .class_init = isa_cirrus_vga_class_init,
3d402831
BS		 2941};
2942
e6e5ad80
FB		 2943/***************************************
2944 *
2945 * PCI bus support
2946 *
2947 ***************************************/
2948
81a322d4 2949static int pci_cirrus_vga_initfn(PCIDevice *dev)
a414c306
GH		 2950{
2951 PCICirrusVGAState *d = DO_UPCAST(PCICirrusVGAState, dev, dev);
2952 CirrusVGAState *s = &d->cirrus_vga;
40021f08
AL		 2953 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
2954 int16_t device_id = pc->device_id;
a414c306
GH		 2955
2956 /* setup VGA */
4a1e244e 2957 vga_common_init(&s->vga);
c75e6d8e
JG		 2958 cirrus_init_common(s, device_id, 1, pci_address_space(dev),
2959 pci_address_space_io(dev));
aa2beaa1 2960 s->vga.con = graphic_console_init(DEVICE(dev), s->vga.hw_ops, &s->vga);
a414c306
GH		 2961
2962 /* setup PCI */
a414c306 2963
b1950430
AK		 2964 memory_region_init(&s->pci_bar, "cirrus-pci-bar0", 0x2000000);
2965
2966 /* XXX: add byte swapping apertures */
2967 memory_region_add_subregion(&s->pci_bar, 0, &s->cirrus_linear_io);
2968 memory_region_add_subregion(&s->pci_bar, 0x1000000,
2969 &s->cirrus_linear_bitblt_io);
2970
a414c306
GH		 2971 /* setup memory space */
2972 /* memory #0 LFB */
2973 /* memory #1 memory-mapped I/O */
2974 /* XXX: s->vga.vram_size must be a power of two */
e824b2cc 2975 pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &s->pci_bar);
a414c306 2976 if (device_id == CIRRUS_ID_CLGD5446) {
e824b2cc 2977 pci_register_bar(&d->dev, 1, 0, &s->cirrus_mmio_io);
a414c306 2978 }
81a322d4 2979 return 0;
a414c306
GH		 2980}
2981
19403a68
MT		 2982static Property pci_vga_cirrus_properties[] = {
2983 DEFINE_PROP_UINT32("vgamem_mb", struct PCICirrusVGAState,
2984 cirrus_vga.vga.vram_size_mb, 8),
2985 DEFINE_PROP_END_OF_LIST(),
2986};
2987
40021f08
AL		 2988static void cirrus_vga_class_init(ObjectClass *klass, void *data)
2989{
39bffca2 2990 DeviceClass *dc = DEVICE_CLASS(klass);
40021f08
AL		 2991 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
2992
2993 k->no_hotplug = 1;
2994 k->init = pci_cirrus_vga_initfn;
2995 k->romfile = VGABIOS_CIRRUS_FILENAME;
2996 k->vendor_id = PCI_VENDOR_ID_CIRRUS;
2997 k->device_id = CIRRUS_ID_CLGD5446;
2998 k->class_id = PCI_CLASS_DISPLAY_VGA;
39bffca2
AL		 2999 dc->desc = "Cirrus CLGD 54xx VGA";
3000 dc->vmsd = &vmstate_pci_cirrus_vga;
19403a68 3001 dc->props = pci_vga_cirrus_properties;
40021f08
AL		 3002}
3003
8c43a6f0 3004static const TypeInfo cirrus_vga_info = {
39bffca2
AL		 3005 .name = "cirrus-vga",
3006 .parent = TYPE_PCI_DEVICE,
3007 .instance_size = sizeof(PCICirrusVGAState),
3008 .class_init = cirrus_vga_class_init,
a414c306 3009};
e6e5ad80 3010
83f7d43a 3011static void cirrus_vga_register_types(void)
a414c306 3012{
83f7d43a 3013 type_register_static(&isa_cirrus_vga_info);
39bffca2 3014 type_register_static(&cirrus_vga_info);
e6e5ad80 3015}
83f7d43a
AF		 3016
3017type_init(cirrus_vga_register_types)
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