]> Git Repo - qemu.git/blame - hw/cirrus_vga.c
projects / qemu.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
console: zap displaystate from dcl callbacks
[qemu.git] / hw / cirrus_vga.c
CommitLineData
e6e5ad80 1/*
aeb3c85f 2 * QEMU Cirrus CLGD 54xx VGA Emulator.
5fafdf24 3 *
e6e5ad80 4 * Copyright (c) 2004 Fabrice Bellard
aeb3c85f 5 * Copyright (c) 2004 Makoto Suzuki (suzu)
5fafdf24 6 *
e6e5ad80
FB		 7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
aeb3c85f
FB		 25/*
26 * Reference: Finn Thogersons' VGADOC4b
27 * available at http://home.worldonline.dk/~finth/
28 */
83c9f4ca
PB		 29#include "hw/hw.h"
30#include "hw/pci/pci.h"
28ecbaee 31#include "ui/console.h"
83c9f4ca
PB		 32#include "hw/vga_int.h"
33#include "hw/loader.h"
e6e5ad80 34
a5082316
FB		 35/*
36 * TODO:
ad81218e 37 * - destination write mask support not complete (bits 5..7)
a5082316
FB		 38 * - optimize linear mappings
39 * - optimize bitblt functions
40 */
41
e36f36e1 42//#define DEBUG_CIRRUS
a21ae81d 43//#define DEBUG_BITBLT
e36f36e1 44
e6e5ad80
FB		 45/***************************************
46 *
47 * definitions
48 *
49 ***************************************/
50
e6e5ad80
FB		 51// ID
52#define CIRRUS_ID_CLGD5422 (0x23<<2)
53#define CIRRUS_ID_CLGD5426 (0x24<<2)
54#define CIRRUS_ID_CLGD5424 (0x25<<2)
55#define CIRRUS_ID_CLGD5428 (0x26<<2)
56#define CIRRUS_ID_CLGD5430 (0x28<<2)
57#define CIRRUS_ID_CLGD5434 (0x2A<<2)
a21ae81d 58#define CIRRUS_ID_CLGD5436 (0x2B<<2)
e6e5ad80
FB		 59#define CIRRUS_ID_CLGD5446 (0x2E<<2)
60
61// sequencer 0x07
62#define CIRRUS_SR7_BPP_VGA 0x00
63#define CIRRUS_SR7_BPP_SVGA 0x01
64#define CIRRUS_SR7_BPP_MASK 0x0e
65#define CIRRUS_SR7_BPP_8 0x00
66#define CIRRUS_SR7_BPP_16_DOUBLEVCLK 0x02
67#define CIRRUS_SR7_BPP_24 0x04
68#define CIRRUS_SR7_BPP_16 0x06
69#define CIRRUS_SR7_BPP_32 0x08
70#define CIRRUS_SR7_ISAADDR_MASK 0xe0
71
72// sequencer 0x0f
73#define CIRRUS_MEMSIZE_512k 0x08
74#define CIRRUS_MEMSIZE_1M 0x10
75#define CIRRUS_MEMSIZE_2M 0x18
76#define CIRRUS_MEMFLAGS_BANKSWITCH 0x80 // bank switching is enabled.
77
78// sequencer 0x12
79#define CIRRUS_CURSOR_SHOW 0x01
80#define CIRRUS_CURSOR_HIDDENPEL 0x02
81#define CIRRUS_CURSOR_LARGE 0x04 // 64x64 if set, 32x32 if clear
82
83// sequencer 0x17
84#define CIRRUS_BUSTYPE_VLBFAST 0x10
85#define CIRRUS_BUSTYPE_PCI 0x20
86#define CIRRUS_BUSTYPE_VLBSLOW 0x30
87#define CIRRUS_BUSTYPE_ISA 0x38
88#define CIRRUS_MMIO_ENABLE 0x04
89#define CIRRUS_MMIO_USE_PCIADDR 0x40 // 0xb8000 if cleared.
90#define CIRRUS_MEMSIZEEXT_DOUBLE 0x80
91
92// control 0x0b
93#define CIRRUS_BANKING_DUAL 0x01
94#define CIRRUS_BANKING_GRANULARITY_16K 0x20 // set:16k, clear:4k
95
96// control 0x30
97#define CIRRUS_BLTMODE_BACKWARDS 0x01
98#define CIRRUS_BLTMODE_MEMSYSDEST 0x02
99#define CIRRUS_BLTMODE_MEMSYSSRC 0x04
100#define CIRRUS_BLTMODE_TRANSPARENTCOMP 0x08
101#define CIRRUS_BLTMODE_PATTERNCOPY 0x40
102#define CIRRUS_BLTMODE_COLOREXPAND 0x80
103#define CIRRUS_BLTMODE_PIXELWIDTHMASK 0x30
104#define CIRRUS_BLTMODE_PIXELWIDTH8 0x00
105#define CIRRUS_BLTMODE_PIXELWIDTH16 0x10
106#define CIRRUS_BLTMODE_PIXELWIDTH24 0x20
107#define CIRRUS_BLTMODE_PIXELWIDTH32 0x30
108
109// control 0x31
110#define CIRRUS_BLT_BUSY 0x01
111#define CIRRUS_BLT_START 0x02
112#define CIRRUS_BLT_RESET 0x04
113#define CIRRUS_BLT_FIFOUSED 0x10
a5082316 114#define CIRRUS_BLT_AUTOSTART 0x80
e6e5ad80
FB		 115
116// control 0x32
117#define CIRRUS_ROP_0 0x00
118#define CIRRUS_ROP_SRC_AND_DST 0x05
119#define CIRRUS_ROP_NOP 0x06
120#define CIRRUS_ROP_SRC_AND_NOTDST 0x09
121#define CIRRUS_ROP_NOTDST 0x0b
122#define CIRRUS_ROP_SRC 0x0d
123#define CIRRUS_ROP_1 0x0e
124#define CIRRUS_ROP_NOTSRC_AND_DST 0x50
125#define CIRRUS_ROP_SRC_XOR_DST 0x59
126#define CIRRUS_ROP_SRC_OR_DST 0x6d
127#define CIRRUS_ROP_NOTSRC_OR_NOTDST 0x90
128#define CIRRUS_ROP_SRC_NOTXOR_DST 0x95
129#define CIRRUS_ROP_SRC_OR_NOTDST 0xad
130#define CIRRUS_ROP_NOTSRC 0xd0
131#define CIRRUS_ROP_NOTSRC_OR_DST 0xd6
132#define CIRRUS_ROP_NOTSRC_AND_NOTDST 0xda
133
a5082316
FB		 134#define CIRRUS_ROP_NOP_INDEX 2
135#define CIRRUS_ROP_SRC_INDEX 5
136
a21ae81d 137// control 0x33
a5082316 138#define CIRRUS_BLTMODEEXT_SOLIDFILL 0x04
4c8732d7 139#define CIRRUS_BLTMODEEXT_COLOREXPINV 0x02
a5082316 140#define CIRRUS_BLTMODEEXT_DWORDGRANULARITY 0x01
a21ae81d 141
e6e5ad80
FB		 142// memory-mapped IO
143#define CIRRUS_MMIO_BLTBGCOLOR 0x00 // dword
144#define CIRRUS_MMIO_BLTFGCOLOR 0x04 // dword
145#define CIRRUS_MMIO_BLTWIDTH 0x08 // word
146#define CIRRUS_MMIO_BLTHEIGHT 0x0a // word
147#define CIRRUS_MMIO_BLTDESTPITCH 0x0c // word
148#define CIRRUS_MMIO_BLTSRCPITCH 0x0e // word
149#define CIRRUS_MMIO_BLTDESTADDR 0x10 // dword
150#define CIRRUS_MMIO_BLTSRCADDR 0x14 // dword
151#define CIRRUS_MMIO_BLTWRITEMASK 0x17 // byte
152#define CIRRUS_MMIO_BLTMODE 0x18 // byte
153#define CIRRUS_MMIO_BLTROP 0x1a // byte
154#define CIRRUS_MMIO_BLTMODEEXT 0x1b // byte
155#define CIRRUS_MMIO_BLTTRANSPARENTCOLOR 0x1c // word?
156#define CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK 0x20 // word?
157#define CIRRUS_MMIO_LINEARDRAW_START_X 0x24 // word
158#define CIRRUS_MMIO_LINEARDRAW_START_Y 0x26 // word
159#define CIRRUS_MMIO_LINEARDRAW_END_X 0x28 // word
160#define CIRRUS_MMIO_LINEARDRAW_END_Y 0x2a // word
161#define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_INC 0x2c // byte
162#define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ROLLOVER 0x2d // byte
163#define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_MASK 0x2e // byte
164#define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ACCUM 0x2f // byte
165#define CIRRUS_MMIO_BRESENHAM_K1 0x30 // word
166#define CIRRUS_MMIO_BRESENHAM_K3 0x32 // word
167#define CIRRUS_MMIO_BRESENHAM_ERROR 0x34 // word
168#define CIRRUS_MMIO_BRESENHAM_DELTA_MAJOR 0x36 // word
169#define CIRRUS_MMIO_BRESENHAM_DIRECTION 0x38 // byte
170#define CIRRUS_MMIO_LINEDRAW_MODE 0x39 // byte
171#define CIRRUS_MMIO_BLTSTATUS 0x40 // byte
172
a21ae81d 173#define CIRRUS_PNPMMIO_SIZE 0x1000
e6e5ad80 174
b2eb849d
AJ		 175#define BLTUNSAFE(s) \
176 ( \
177 ( /* check dst is within bounds */ \
b2b183c2 178 (s)->cirrus_blt_height * ABS((s)->cirrus_blt_dstpitch) \
b2eb849d 179 + ((s)->cirrus_blt_dstaddr & (s)->cirrus_addr_mask) > \
4e12cd94 180 (s)->vga.vram_size \
b2eb849d
AJ		 181 ) || \
182 ( /* check src is within bounds */ \
b2b183c2 183 (s)->cirrus_blt_height * ABS((s)->cirrus_blt_srcpitch) \
b2eb849d 184 + ((s)->cirrus_blt_srcaddr & (s)->cirrus_addr_mask) > \
4e12cd94 185 (s)->vga.vram_size \
b2eb849d
AJ		 186 ) \
187 )
188
a5082316
FB		 189struct CirrusVGAState;
190typedef void (*cirrus_bitblt_rop_t) (struct CirrusVGAState *s,
191 uint8_t * dst, const uint8_t * src,
e6e5ad80
FB		 192 int dstpitch, int srcpitch,
193 int bltwidth, int bltheight);
a5082316
FB		 194typedef void (*cirrus_fill_t)(struct CirrusVGAState *s,
195 uint8_t *dst, int dst_pitch, int width, int height);
e6e5ad80
FB		 196
197typedef struct CirrusVGAState {
4e12cd94 198 VGACommonState vga;
e6e5ad80 199
c75e6d8e 200 MemoryRegion cirrus_vga_io;
b1950430
AK		 201 MemoryRegion cirrus_linear_io;
202 MemoryRegion cirrus_linear_bitblt_io;
203 MemoryRegion cirrus_mmio_io;
204 MemoryRegion pci_bar;
205 bool linear_vram; /* vga.vram mapped over cirrus_linear_io */
206 MemoryRegion low_mem_container; /* container for 0xa0000-0xc0000 */
207 MemoryRegion low_mem; /* always mapped, overridden by: */
7969d9ed 208 MemoryRegion cirrus_bank[2]; /* aliases at 0xa0000-0xb0000 */
e6e5ad80 209 uint32_t cirrus_addr_mask;
78e127ef 210 uint32_t linear_mmio_mask;
e6e5ad80
FB		 211 uint8_t cirrus_shadow_gr0;
212 uint8_t cirrus_shadow_gr1;
213 uint8_t cirrus_hidden_dac_lockindex;
214 uint8_t cirrus_hidden_dac_data;
215 uint32_t cirrus_bank_base[2];
216 uint32_t cirrus_bank_limit[2];
217 uint8_t cirrus_hidden_palette[48];
a5082316
FB		 218 uint32_t hw_cursor_x;
219 uint32_t hw_cursor_y;
e6e5ad80
FB		 220 int cirrus_blt_pixelwidth;
221 int cirrus_blt_width;
222 int cirrus_blt_height;
223 int cirrus_blt_dstpitch;
224 int cirrus_blt_srcpitch;
a5082316
FB		 225 uint32_t cirrus_blt_fgcol;
226 uint32_t cirrus_blt_bgcol;
e6e5ad80
FB		 227 uint32_t cirrus_blt_dstaddr;
228 uint32_t cirrus_blt_srcaddr;
229 uint8_t cirrus_blt_mode;
a5082316 230 uint8_t cirrus_blt_modeext;
e6e5ad80 231 cirrus_bitblt_rop_t cirrus_rop;
a5082316 232#define CIRRUS_BLTBUFSIZE (2048 * 4) /* one line width */
e6e5ad80
FB		 233 uint8_t cirrus_bltbuf[CIRRUS_BLTBUFSIZE];
234 uint8_t *cirrus_srcptr;
235 uint8_t *cirrus_srcptr_end;
236 uint32_t cirrus_srccounter;
a5082316
FB		 237 /* hwcursor display state */
238 int last_hw_cursor_size;
239 int last_hw_cursor_x;
240 int last_hw_cursor_y;
241 int last_hw_cursor_y_start;
242 int last_hw_cursor_y_end;
78e127ef 243 int real_vram_size; /* XXX: suppress that */
4abc796d
BS		 244 int device_id;
245 int bustype;
e6e5ad80
FB		 246} CirrusVGAState;
247
248typedef struct PCICirrusVGAState {
249 PCIDevice dev;
250 CirrusVGAState cirrus_vga;
251} PCICirrusVGAState;
252
3d402831
BS		 253typedef struct ISACirrusVGAState {
254 ISADevice dev;
255 CirrusVGAState cirrus_vga;
256} ISACirrusVGAState;
257
a5082316 258static uint8_t rop_to_index[256];
3b46e624 259
e6e5ad80
FB		 260/***************************************
261 *
262 * prototypes.
263 *
264 ***************************************/
265
266
8926b517
FB		 267static void cirrus_bitblt_reset(CirrusVGAState *s);
268static void cirrus_update_memory_access(CirrusVGAState *s);
e6e5ad80
FB		 269
270/***************************************
271 *
272 * raster operations
273 *
274 ***************************************/
275
a5082316
FB		 276static void cirrus_bitblt_rop_nop(CirrusVGAState *s,
277 uint8_t *dst,const uint8_t *src,
278 int dstpitch,int srcpitch,
279 int bltwidth,int bltheight)
280{
e6e5ad80
FB		 281}
282
a5082316
FB		 283static void cirrus_bitblt_fill_nop(CirrusVGAState *s,
284 uint8_t *dst,
285 int dstpitch, int bltwidth,int bltheight)
e6e5ad80 286{
a5082316 287}
e6e5ad80 288
a5082316 289#define ROP_NAME 0
8c78881f 290#define ROP_FN(d, s) 0
83c9f4ca 291#include "hw/cirrus_vga_rop.h"
e6e5ad80 292
a5082316 293#define ROP_NAME src_and_dst
8c78881f 294#define ROP_FN(d, s) (s) & (d)
83c9f4ca 295#include "hw/cirrus_vga_rop.h"
e6e5ad80 296
a5082316 297#define ROP_NAME src_and_notdst
8c78881f 298#define ROP_FN(d, s) (s) & (~(d))
83c9f4ca 299#include "hw/cirrus_vga_rop.h"
e6e5ad80 300
a5082316 301#define ROP_NAME notdst
8c78881f 302#define ROP_FN(d, s) ~(d)
83c9f4ca 303#include "hw/cirrus_vga_rop.h"
e6e5ad80 304
a5082316 305#define ROP_NAME src
8c78881f 306#define ROP_FN(d, s) s
83c9f4ca 307#include "hw/cirrus_vga_rop.h"
e6e5ad80 308
a5082316 309#define ROP_NAME 1
8c78881f 310#define ROP_FN(d, s) ~0
83c9f4ca 311#include "hw/cirrus_vga_rop.h"
a5082316
FB		 312
313#define ROP_NAME notsrc_and_dst
8c78881f 314#define ROP_FN(d, s) (~(s)) & (d)
83c9f4ca 315#include "hw/cirrus_vga_rop.h"
a5082316
FB		 316
317#define ROP_NAME src_xor_dst
8c78881f 318#define ROP_FN(d, s) (s) ^ (d)
83c9f4ca 319#include "hw/cirrus_vga_rop.h"
a5082316
FB		 320
321#define ROP_NAME src_or_dst
8c78881f 322#define ROP_FN(d, s) (s) | (d)
83c9f4ca 323#include "hw/cirrus_vga_rop.h"
a5082316
FB		 324
325#define ROP_NAME notsrc_or_notdst
8c78881f 326#define ROP_FN(d, s) (~(s)) | (~(d))
83c9f4ca 327#include "hw/cirrus_vga_rop.h"
a5082316
FB		 328
329#define ROP_NAME src_notxor_dst
8c78881f 330#define ROP_FN(d, s) ~((s) ^ (d))
83c9f4ca 331#include "hw/cirrus_vga_rop.h"
e6e5ad80 332
a5082316 333#define ROP_NAME src_or_notdst
8c78881f 334#define ROP_FN(d, s) (s) | (~(d))
83c9f4ca 335#include "hw/cirrus_vga_rop.h"
a5082316
FB		 336
337#define ROP_NAME notsrc
8c78881f 338#define ROP_FN(d, s) (~(s))
83c9f4ca 339#include "hw/cirrus_vga_rop.h"
a5082316
FB		 340
341#define ROP_NAME notsrc_or_dst
8c78881f 342#define ROP_FN(d, s) (~(s)) | (d)
83c9f4ca 343#include "hw/cirrus_vga_rop.h"
a5082316
FB		 344
345#define ROP_NAME notsrc_and_notdst
8c78881f 346#define ROP_FN(d, s) (~(s)) & (~(d))
83c9f4ca 347#include "hw/cirrus_vga_rop.h"
a5082316
FB		 348
349static const cirrus_bitblt_rop_t cirrus_fwd_rop[16] = {
350 cirrus_bitblt_rop_fwd_0,
351 cirrus_bitblt_rop_fwd_src_and_dst,
352 cirrus_bitblt_rop_nop,
353 cirrus_bitblt_rop_fwd_src_and_notdst,
354 cirrus_bitblt_rop_fwd_notdst,
355 cirrus_bitblt_rop_fwd_src,
356 cirrus_bitblt_rop_fwd_1,
357 cirrus_bitblt_rop_fwd_notsrc_and_dst,
358 cirrus_bitblt_rop_fwd_src_xor_dst,
359 cirrus_bitblt_rop_fwd_src_or_dst,
360 cirrus_bitblt_rop_fwd_notsrc_or_notdst,
361 cirrus_bitblt_rop_fwd_src_notxor_dst,
362 cirrus_bitblt_rop_fwd_src_or_notdst,
363 cirrus_bitblt_rop_fwd_notsrc,
364 cirrus_bitblt_rop_fwd_notsrc_or_dst,
365 cirrus_bitblt_rop_fwd_notsrc_and_notdst,
366};
367
368static const cirrus_bitblt_rop_t cirrus_bkwd_rop[16] = {
369 cirrus_bitblt_rop_bkwd_0,
370 cirrus_bitblt_rop_bkwd_src_and_dst,
371 cirrus_bitblt_rop_nop,
372 cirrus_bitblt_rop_bkwd_src_and_notdst,
373 cirrus_bitblt_rop_bkwd_notdst,
374 cirrus_bitblt_rop_bkwd_src,
375 cirrus_bitblt_rop_bkwd_1,
376 cirrus_bitblt_rop_bkwd_notsrc_and_dst,
377 cirrus_bitblt_rop_bkwd_src_xor_dst,
378 cirrus_bitblt_rop_bkwd_src_or_dst,
379 cirrus_bitblt_rop_bkwd_notsrc_or_notdst,
380 cirrus_bitblt_rop_bkwd_src_notxor_dst,
381 cirrus_bitblt_rop_bkwd_src_or_notdst,
382 cirrus_bitblt_rop_bkwd_notsrc,
383 cirrus_bitblt_rop_bkwd_notsrc_or_dst,
384 cirrus_bitblt_rop_bkwd_notsrc_and_notdst,
385};
96cf2df8
TS		 386
387#define TRANSP_ROP(name) {\
388 name ## _8,\
389 name ## _16,\
390 }
391#define TRANSP_NOP(func) {\
392 func,\
393 func,\
394 }
395
396static const cirrus_bitblt_rop_t cirrus_fwd_transp_rop[16][2] = {
397 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_0),
398 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_and_dst),
399 TRANSP_NOP(cirrus_bitblt_rop_nop),
400 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_and_notdst),
401 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notdst),
402 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src),
403 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_1),
404 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_and_dst),
405 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_xor_dst),
406 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_or_dst),
407 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_or_notdst),
408 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_notxor_dst),
409 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_or_notdst),
410 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc),
411 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_or_dst),
412 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_and_notdst),
413};
414
415static const cirrus_bitblt_rop_t cirrus_bkwd_transp_rop[16][2] = {
416 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_0),
417 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_and_dst),
418 TRANSP_NOP(cirrus_bitblt_rop_nop),
419 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_and_notdst),
420 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notdst),
421 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src),
422 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_1),
423 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_and_dst),
424 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_xor_dst),
425 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_or_dst),
426 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_or_notdst),
427 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_notxor_dst),
428 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_or_notdst),
429 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc),
430 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_or_dst),
431 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_and_notdst),
432};
433
a5082316
FB		 434#define ROP2(name) {\
435 name ## _8,\
436 name ## _16,\
437 name ## _24,\
438 name ## _32,\
439 }
440
441#define ROP_NOP2(func) {\
442 func,\
443 func,\
444 func,\
445 func,\
446 }
447
e69390ce
FB		 448static const cirrus_bitblt_rop_t cirrus_patternfill[16][4] = {
449 ROP2(cirrus_patternfill_0),
450 ROP2(cirrus_patternfill_src_and_dst),
451 ROP_NOP2(cirrus_bitblt_rop_nop),
452 ROP2(cirrus_patternfill_src_and_notdst),
453 ROP2(cirrus_patternfill_notdst),
454 ROP2(cirrus_patternfill_src),
455 ROP2(cirrus_patternfill_1),
456 ROP2(cirrus_patternfill_notsrc_and_dst),
457 ROP2(cirrus_patternfill_src_xor_dst),
458 ROP2(cirrus_patternfill_src_or_dst),
459 ROP2(cirrus_patternfill_notsrc_or_notdst),
460 ROP2(cirrus_patternfill_src_notxor_dst),
461 ROP2(cirrus_patternfill_src_or_notdst),
462 ROP2(cirrus_patternfill_notsrc),
463 ROP2(cirrus_patternfill_notsrc_or_dst),
464 ROP2(cirrus_patternfill_notsrc_and_notdst),
465};
466
a5082316
FB		 467static const cirrus_bitblt_rop_t cirrus_colorexpand_transp[16][4] = {
468 ROP2(cirrus_colorexpand_transp_0),
469 ROP2(cirrus_colorexpand_transp_src_and_dst),
470 ROP_NOP2(cirrus_bitblt_rop_nop),
471 ROP2(cirrus_colorexpand_transp_src_and_notdst),
472 ROP2(cirrus_colorexpand_transp_notdst),
473 ROP2(cirrus_colorexpand_transp_src),
474 ROP2(cirrus_colorexpand_transp_1),
475 ROP2(cirrus_colorexpand_transp_notsrc_and_dst),
476 ROP2(cirrus_colorexpand_transp_src_xor_dst),
477 ROP2(cirrus_colorexpand_transp_src_or_dst),
478 ROP2(cirrus_colorexpand_transp_notsrc_or_notdst),
479 ROP2(cirrus_colorexpand_transp_src_notxor_dst),
480 ROP2(cirrus_colorexpand_transp_src_or_notdst),
481 ROP2(cirrus_colorexpand_transp_notsrc),
482 ROP2(cirrus_colorexpand_transp_notsrc_or_dst),
483 ROP2(cirrus_colorexpand_transp_notsrc_and_notdst),
484};
485
486static const cirrus_bitblt_rop_t cirrus_colorexpand[16][4] = {
487 ROP2(cirrus_colorexpand_0),
488 ROP2(cirrus_colorexpand_src_and_dst),
489 ROP_NOP2(cirrus_bitblt_rop_nop),
490 ROP2(cirrus_colorexpand_src_and_notdst),
491 ROP2(cirrus_colorexpand_notdst),
492 ROP2(cirrus_colorexpand_src),
493 ROP2(cirrus_colorexpand_1),
494 ROP2(cirrus_colorexpand_notsrc_and_dst),
495 ROP2(cirrus_colorexpand_src_xor_dst),
496 ROP2(cirrus_colorexpand_src_or_dst),
497 ROP2(cirrus_colorexpand_notsrc_or_notdst),
498 ROP2(cirrus_colorexpand_src_notxor_dst),
499 ROP2(cirrus_colorexpand_src_or_notdst),
500 ROP2(cirrus_colorexpand_notsrc),
501 ROP2(cirrus_colorexpand_notsrc_or_dst),
502 ROP2(cirrus_colorexpand_notsrc_and_notdst),
503};
504
b30d4608
FB		 505static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern_transp[16][4] = {
506 ROP2(cirrus_colorexpand_pattern_transp_0),
507 ROP2(cirrus_colorexpand_pattern_transp_src_and_dst),
508 ROP_NOP2(cirrus_bitblt_rop_nop),
509 ROP2(cirrus_colorexpand_pattern_transp_src_and_notdst),
510 ROP2(cirrus_colorexpand_pattern_transp_notdst),
511 ROP2(cirrus_colorexpand_pattern_transp_src),
512 ROP2(cirrus_colorexpand_pattern_transp_1),
513 ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_dst),
514 ROP2(cirrus_colorexpand_pattern_transp_src_xor_dst),
515 ROP2(cirrus_colorexpand_pattern_transp_src_or_dst),
516 ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_notdst),
517 ROP2(cirrus_colorexpand_pattern_transp_src_notxor_dst),
518 ROP2(cirrus_colorexpand_pattern_transp_src_or_notdst),
519 ROP2(cirrus_colorexpand_pattern_transp_notsrc),
520 ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_dst),
521 ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_notdst),
522};
523
524static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern[16][4] = {
525 ROP2(cirrus_colorexpand_pattern_0),
526 ROP2(cirrus_colorexpand_pattern_src_and_dst),
527 ROP_NOP2(cirrus_bitblt_rop_nop),
528 ROP2(cirrus_colorexpand_pattern_src_and_notdst),
529 ROP2(cirrus_colorexpand_pattern_notdst),
530 ROP2(cirrus_colorexpand_pattern_src),
531 ROP2(cirrus_colorexpand_pattern_1),
532 ROP2(cirrus_colorexpand_pattern_notsrc_and_dst),
533 ROP2(cirrus_colorexpand_pattern_src_xor_dst),
534 ROP2(cirrus_colorexpand_pattern_src_or_dst),
535 ROP2(cirrus_colorexpand_pattern_notsrc_or_notdst),
536 ROP2(cirrus_colorexpand_pattern_src_notxor_dst),
537 ROP2(cirrus_colorexpand_pattern_src_or_notdst),
538 ROP2(cirrus_colorexpand_pattern_notsrc),
539 ROP2(cirrus_colorexpand_pattern_notsrc_or_dst),
540 ROP2(cirrus_colorexpand_pattern_notsrc_and_notdst),
541};
542
a5082316
FB		 543static const cirrus_fill_t cirrus_fill[16][4] = {
544 ROP2(cirrus_fill_0),
545 ROP2(cirrus_fill_src_and_dst),
546 ROP_NOP2(cirrus_bitblt_fill_nop),
547 ROP2(cirrus_fill_src_and_notdst),
548 ROP2(cirrus_fill_notdst),
549 ROP2(cirrus_fill_src),
550 ROP2(cirrus_fill_1),
551 ROP2(cirrus_fill_notsrc_and_dst),
552 ROP2(cirrus_fill_src_xor_dst),
553 ROP2(cirrus_fill_src_or_dst),
554 ROP2(cirrus_fill_notsrc_or_notdst),
555 ROP2(cirrus_fill_src_notxor_dst),
556 ROP2(cirrus_fill_src_or_notdst),
557 ROP2(cirrus_fill_notsrc),
558 ROP2(cirrus_fill_notsrc_or_dst),
559 ROP2(cirrus_fill_notsrc_and_notdst),
560};
561
562static inline void cirrus_bitblt_fgcol(CirrusVGAState *s)
e6e5ad80 563{
a5082316
FB		 564 unsigned int color;
565 switch (s->cirrus_blt_pixelwidth) {
566 case 1:
567 s->cirrus_blt_fgcol = s->cirrus_shadow_gr1;
568 break;
569 case 2:
4e12cd94 570 color = s->cirrus_shadow_gr1 | (s->vga.gr[0x11] << 8);
a5082316
FB		 571 s->cirrus_blt_fgcol = le16_to_cpu(color);
572 break;
573 case 3:
5fafdf24 574 s->cirrus_blt_fgcol = s->cirrus_shadow_gr1 |
4e12cd94 575 (s->vga.gr[0x11] << 8) | (s->vga.gr[0x13] << 16);
a5082316
FB		 576 break;
577 default:
578 case 4:
4e12cd94
AK		 579 color = s->cirrus_shadow_gr1 | (s->vga.gr[0x11] << 8) |
580 (s->vga.gr[0x13] << 16) | (s->vga.gr[0x15] << 24);
a5082316
FB		 581 s->cirrus_blt_fgcol = le32_to_cpu(color);
582 break;
e6e5ad80
FB		 583 }
584}
585
a5082316 586static inline void cirrus_bitblt_bgcol(CirrusVGAState *s)
e6e5ad80 587{
a5082316 588 unsigned int color;
e6e5ad80
FB		 589 switch (s->cirrus_blt_pixelwidth) {
590 case 1:
a5082316
FB		 591 s->cirrus_blt_bgcol = s->cirrus_shadow_gr0;
592 break;
e6e5ad80 593 case 2:
4e12cd94 594 color = s->cirrus_shadow_gr0 | (s->vga.gr[0x10] << 8);
a5082316
FB		 595 s->cirrus_blt_bgcol = le16_to_cpu(color);
596 break;
e6e5ad80 597 case 3:
5fafdf24 598 s->cirrus_blt_bgcol = s->cirrus_shadow_gr0 |
4e12cd94 599 (s->vga.gr[0x10] << 8) | (s->vga.gr[0x12] << 16);
a5082316 600 break;
e6e5ad80 601 default:
a5082316 602 case 4:
4e12cd94
AK		 603 color = s->cirrus_shadow_gr0 | (s->vga.gr[0x10] << 8) |
604 (s->vga.gr[0x12] << 16) | (s->vga.gr[0x14] << 24);
a5082316
FB		 605 s->cirrus_blt_bgcol = le32_to_cpu(color);
606 break;
e6e5ad80
FB		 607 }
608}
609
610static void cirrus_invalidate_region(CirrusVGAState * s, int off_begin,
611 int off_pitch, int bytesperline,
612 int lines)
613{
614 int y;
615 int off_cur;
616 int off_cur_end;
617
618 for (y = 0; y < lines; y++) {
619 off_cur = off_begin;
b2eb849d 620 off_cur_end = (off_cur + bytesperline) & s->cirrus_addr_mask;
fd4aa979 621 memory_region_set_dirty(&s->vga.vram, off_cur, off_cur_end - off_cur);
e6e5ad80
FB		 622 off_begin += off_pitch;
623 }
624}
625
e6e5ad80
FB		 626static int cirrus_bitblt_common_patterncopy(CirrusVGAState * s,
627 const uint8_t * src)
628{
e6e5ad80 629 uint8_t *dst;
e6e5ad80 630
4e12cd94 631 dst = s->vga.vram_ptr + (s->cirrus_blt_dstaddr & s->cirrus_addr_mask);
b2eb849d
AJ		 632
633 if (BLTUNSAFE(s))
634 return 0;
635
e69390ce 636 (*s->cirrus_rop) (s, dst, src,
5fafdf24 637 s->cirrus_blt_dstpitch, 0,
e69390ce 638 s->cirrus_blt_width, s->cirrus_blt_height);
e6e5ad80 639 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
e69390ce
FB		 640 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
641 s->cirrus_blt_height);
e6e5ad80
FB		 642 return 1;
643}
644
a21ae81d
FB		 645/* fill */
646
a5082316 647static int cirrus_bitblt_solidfill(CirrusVGAState *s, int blt_rop)
a21ae81d 648{
a5082316 649 cirrus_fill_t rop_func;
a21ae81d 650
b2eb849d
AJ		 651 if (BLTUNSAFE(s))
652 return 0;
a5082316 653 rop_func = cirrus_fill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
4e12cd94 654 rop_func(s, s->vga.vram_ptr + (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
a5082316
FB		 655 s->cirrus_blt_dstpitch,
656 s->cirrus_blt_width, s->cirrus_blt_height);
a21ae81d
FB		 657 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
658 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
659 s->cirrus_blt_height);
660 cirrus_bitblt_reset(s);
661 return 1;
662}
663
e6e5ad80
FB		 664/***************************************
665 *
666 * bitblt (video-to-video)
667 *
668 ***************************************/
669
670static int cirrus_bitblt_videotovideo_patterncopy(CirrusVGAState * s)
671{
672 return cirrus_bitblt_common_patterncopy(s,
4e12cd94 673 s->vga.vram_ptr + ((s->cirrus_blt_srcaddr & ~7) &
b2eb849d 674 s->cirrus_addr_mask));
e6e5ad80
FB		 675}
676
24236869 677static void cirrus_do_copy(CirrusVGAState *s, int dst, int src, int w, int h)
e6e5ad80 678{
78935c4a
AJ		 679 int sx = 0, sy = 0;
680 int dx = 0, dy = 0;
681 int depth = 0;
24236869
FB		 682 int notify = 0;
683
92d675d1
AJ		 684 /* make sure to only copy if it's a plain copy ROP */
685 if (*s->cirrus_rop == cirrus_bitblt_rop_fwd_src ||
686 *s->cirrus_rop == cirrus_bitblt_rop_bkwd_src) {
24236869 687
92d675d1
AJ		 688 int width, height;
689
690 depth = s->vga.get_bpp(&s->vga) / 8;
691 s->vga.get_resolution(&s->vga, &width, &height);
692
693 /* extra x, y */
694 sx = (src % ABS(s->cirrus_blt_srcpitch)) / depth;
695 sy = (src / ABS(s->cirrus_blt_srcpitch));
696 dx = (dst % ABS(s->cirrus_blt_dstpitch)) / depth;
697 dy = (dst / ABS(s->cirrus_blt_dstpitch));
24236869 698
92d675d1
AJ		 699 /* normalize width */
700 w /= depth;
24236869 701
92d675d1
AJ		 702 /* if we're doing a backward copy, we have to adjust
703 our x/y to be the upper left corner (instead of the lower
704 right corner) */
705 if (s->cirrus_blt_dstpitch < 0) {
706 sx -= (s->cirrus_blt_width / depth) - 1;
707 dx -= (s->cirrus_blt_width / depth) - 1;
708 sy -= s->cirrus_blt_height - 1;
709 dy -= s->cirrus_blt_height - 1;
710 }
711
712 /* are we in the visible portion of memory? */
713 if (sx >= 0 && sy >= 0 && dx >= 0 && dy >= 0 &&
714 (sx + w) <= width && (sy + h) <= height &&
715 (dx + w) <= width && (dy + h) <= height) {
716 notify = 1;
717 }
718 }
24236869
FB		 719
720 /* we have to flush all pending changes so that the copy
721 is generated at the appropriate moment in time */
722 if (notify)
723 vga_hw_update();
724
4e12cd94 725 (*s->cirrus_rop) (s, s->vga.vram_ptr +
b2eb849d 726 (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
4e12cd94 727 s->vga.vram_ptr +
b2eb849d 728 (s->cirrus_blt_srcaddr & s->cirrus_addr_mask),
e6e5ad80
FB		 729 s->cirrus_blt_dstpitch, s->cirrus_blt_srcpitch,
730 s->cirrus_blt_width, s->cirrus_blt_height);
24236869
FB		 731
732 if (notify)
4e12cd94 733 qemu_console_copy(s->vga.ds,
38334f76
AZ		 734 sx, sy, dx, dy,
735 s->cirrus_blt_width / depth,
736 s->cirrus_blt_height);
24236869
FB		 737
738 /* we don't have to notify the display that this portion has
38334f76 739 changed since qemu_console_copy implies this */
24236869 740
31c05501
AL		 741 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
742 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
743 s->cirrus_blt_height);
24236869
FB		 744}
745
746static int cirrus_bitblt_videotovideo_copy(CirrusVGAState * s)
747{
65d35a09
AJ		 748 if (BLTUNSAFE(s))
749 return 0;
750
4e12cd94
AK		 751 cirrus_do_copy(s, s->cirrus_blt_dstaddr - s->vga.start_addr,
752 s->cirrus_blt_srcaddr - s->vga.start_addr,
7d957bd8 753 s->cirrus_blt_width, s->cirrus_blt_height);
24236869 754
e6e5ad80
FB		 755 return 1;
756}
757
758/***************************************
759 *
760 * bitblt (cpu-to-video)
761 *
762 ***************************************/
763
e6e5ad80
FB		 764static void cirrus_bitblt_cputovideo_next(CirrusVGAState * s)
765{
766 int copy_count;
a5082316 767 uint8_t *end_ptr;
3b46e624 768
e6e5ad80 769 if (s->cirrus_srccounter > 0) {
a5082316
FB		 770 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
771 cirrus_bitblt_common_patterncopy(s, s->cirrus_bltbuf);
772 the_end:
773 s->cirrus_srccounter = 0;
774 cirrus_bitblt_reset(s);
775 } else {
776 /* at least one scan line */
777 do {
4e12cd94 778 (*s->cirrus_rop)(s, s->vga.vram_ptr +
b2eb849d
AJ		 779 (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
780 s->cirrus_bltbuf, 0, 0, s->cirrus_blt_width, 1);
a5082316
FB		 781 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr, 0,
782 s->cirrus_blt_width, 1);
783 s->cirrus_blt_dstaddr += s->cirrus_blt_dstpitch;
784 s->cirrus_srccounter -= s->cirrus_blt_srcpitch;
785 if (s->cirrus_srccounter <= 0)
786 goto the_end;
66a0a2cb 787 /* more bytes than needed can be transferred because of
a5082316
FB		 788 word alignment, so we keep them for the next line */
789 /* XXX: keep alignment to speed up transfer */
790 end_ptr = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
791 copy_count = s->cirrus_srcptr_end - end_ptr;
792 memmove(s->cirrus_bltbuf, end_ptr, copy_count);
793 s->cirrus_srcptr = s->cirrus_bltbuf + copy_count;
794 s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
795 } while (s->cirrus_srcptr >= s->cirrus_srcptr_end);
796 }
e6e5ad80
FB		 797 }
798}
799
800/***************************************
801 *
802 * bitblt wrapper
803 *
804 ***************************************/
805
806static void cirrus_bitblt_reset(CirrusVGAState * s)
807{
f8b237af
AL		 808 int need_update;
809
4e12cd94 810 s->vga.gr[0x31] &=
e6e5ad80 811 ~(CIRRUS_BLT_START | CIRRUS_BLT_BUSY | CIRRUS_BLT_FIFOUSED);
f8b237af
AL		 812 need_update = s->cirrus_srcptr != &s->cirrus_bltbuf[0]
813 || s->cirrus_srcptr_end != &s->cirrus_bltbuf[0];
e6e5ad80
FB		 814 s->cirrus_srcptr = &s->cirrus_bltbuf[0];
815 s->cirrus_srcptr_end = &s->cirrus_bltbuf[0];
816 s->cirrus_srccounter = 0;
f8b237af
AL		 817 if (!need_update)
818 return;
8926b517 819 cirrus_update_memory_access(s);
e6e5ad80
FB		 820}
821
822static int cirrus_bitblt_cputovideo(CirrusVGAState * s)
823{
a5082316
FB		 824 int w;
825
e6e5ad80
FB		 826 s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_MEMSYSSRC;
827 s->cirrus_srcptr = &s->cirrus_bltbuf[0];
828 s->cirrus_srcptr_end = &s->cirrus_bltbuf[0];
829
830 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
831 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
a5082316 832 s->cirrus_blt_srcpitch = 8;
e6e5ad80 833 } else {
b30d4608 834 /* XXX: check for 24 bpp */
a5082316 835 s->cirrus_blt_srcpitch = 8 * 8 * s->cirrus_blt_pixelwidth;
e6e5ad80 836 }
a5082316 837 s->cirrus_srccounter = s->cirrus_blt_srcpitch;
e6e5ad80
FB		 838 } else {
839 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
a5082316 840 w = s->cirrus_blt_width / s->cirrus_blt_pixelwidth;
5fafdf24 841 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_DWORDGRANULARITY)
a5082316
FB		 842 s->cirrus_blt_srcpitch = ((w + 31) >> 5);
843 else
844 s->cirrus_blt_srcpitch = ((w + 7) >> 3);
e6e5ad80 845 } else {
c9c0eae8
FB		 846 /* always align input size to 32 bits */
847 s->cirrus_blt_srcpitch = (s->cirrus_blt_width + 3) & ~3;
e6e5ad80 848 }
a5082316 849 s->cirrus_srccounter = s->cirrus_blt_srcpitch * s->cirrus_blt_height;
e6e5ad80 850 }
a5082316
FB		 851 s->cirrus_srcptr = s->cirrus_bltbuf;
852 s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
8926b517 853 cirrus_update_memory_access(s);
e6e5ad80
FB		 854 return 1;
855}
856
857static int cirrus_bitblt_videotocpu(CirrusVGAState * s)
858{
859 /* XXX */
a5082316 860#ifdef DEBUG_BITBLT
e6e5ad80
FB		 861 printf("cirrus: bitblt (video to cpu) is not implemented yet\n");
862#endif
863 return 0;
864}
865
866static int cirrus_bitblt_videotovideo(CirrusVGAState * s)
867{
868 int ret;
869
870 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
871 ret = cirrus_bitblt_videotovideo_patterncopy(s);
872 } else {
873 ret = cirrus_bitblt_videotovideo_copy(s);
874 }
e6e5ad80
FB		 875 if (ret)
876 cirrus_bitblt_reset(s);
877 return ret;
878}
879
880static void cirrus_bitblt_start(CirrusVGAState * s)
881{
882 uint8_t blt_rop;
883
4e12cd94 884 s->vga.gr[0x31] |= CIRRUS_BLT_BUSY;
a5082316 885
4e12cd94
AK		 886 s->cirrus_blt_width = (s->vga.gr[0x20] | (s->vga.gr[0x21] << 8)) + 1;
887 s->cirrus_blt_height = (s->vga.gr[0x22] | (s->vga.gr[0x23] << 8)) + 1;
888 s->cirrus_blt_dstpitch = (s->vga.gr[0x24] | (s->vga.gr[0x25] << 8));
889 s->cirrus_blt_srcpitch = (s->vga.gr[0x26] | (s->vga.gr[0x27] << 8));
e6e5ad80 890 s->cirrus_blt_dstaddr =
4e12cd94 891 (s->vga.gr[0x28] | (s->vga.gr[0x29] << 8) | (s->vga.gr[0x2a] << 16));
e6e5ad80 892 s->cirrus_blt_srcaddr =
4e12cd94
AK		 893 (s->vga.gr[0x2c] | (s->vga.gr[0x2d] << 8) | (s->vga.gr[0x2e] << 16));
894 s->cirrus_blt_mode = s->vga.gr[0x30];
895 s->cirrus_blt_modeext = s->vga.gr[0x33];
896 blt_rop = s->vga.gr[0x32];
e6e5ad80 897
a21ae81d 898#ifdef DEBUG_BITBLT
0b74ed78 899 printf("rop=0x%02x mode=0x%02x modeext=0x%02x w=%d h=%d dpitch=%d spitch=%d daddr=0x%08x saddr=0x%08x writemask=0x%02x\n",
5fafdf24 900 blt_rop,
a21ae81d 901 s->cirrus_blt_mode,
a5082316 902 s->cirrus_blt_modeext,
a21ae81d
FB		 903 s->cirrus_blt_width,
904 s->cirrus_blt_height,
905 s->cirrus_blt_dstpitch,
906 s->cirrus_blt_srcpitch,
907 s->cirrus_blt_dstaddr,
a5082316 908 s->cirrus_blt_srcaddr,
4e12cd94 909 s->vga.gr[0x2f]);
a21ae81d
FB		 910#endif
911
e6e5ad80
FB		 912 switch (s->cirrus_blt_mode & CIRRUS_BLTMODE_PIXELWIDTHMASK) {
913 case CIRRUS_BLTMODE_PIXELWIDTH8:
914 s->cirrus_blt_pixelwidth = 1;
915 break;
916 case CIRRUS_BLTMODE_PIXELWIDTH16:
917 s->cirrus_blt_pixelwidth = 2;
918 break;
919 case CIRRUS_BLTMODE_PIXELWIDTH24:
920 s->cirrus_blt_pixelwidth = 3;
921 break;
922 case CIRRUS_BLTMODE_PIXELWIDTH32:
923 s->cirrus_blt_pixelwidth = 4;
924 break;
925 default:
a5082316 926#ifdef DEBUG_BITBLT
e6e5ad80
FB		 927 printf("cirrus: bitblt - pixel width is unknown\n");
928#endif
929 goto bitblt_ignore;
930 }
931 s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_PIXELWIDTHMASK;
932
933 if ((s->
934 cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSSRC |
935 CIRRUS_BLTMODE_MEMSYSDEST))
936 == (CIRRUS_BLTMODE_MEMSYSSRC | CIRRUS_BLTMODE_MEMSYSDEST)) {
a5082316 937#ifdef DEBUG_BITBLT
e6e5ad80
FB		 938 printf("cirrus: bitblt - memory-to-memory copy is requested\n");
939#endif
940 goto bitblt_ignore;
941 }
942
a5082316 943 if ((s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_SOLIDFILL) &&
5fafdf24 944 (s->cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSDEST |
a21ae81d 945 CIRRUS_BLTMODE_TRANSPARENTCOMP |
5fafdf24
TS		 946 CIRRUS_BLTMODE_PATTERNCOPY |
947 CIRRUS_BLTMODE_COLOREXPAND)) ==
a21ae81d 948 (CIRRUS_BLTMODE_PATTERNCOPY | CIRRUS_BLTMODE_COLOREXPAND)) {
a5082316
FB		 949 cirrus_bitblt_fgcol(s);
950 cirrus_bitblt_solidfill(s, blt_rop);
e6e5ad80 951 } else {
5fafdf24
TS		 952 if ((s->cirrus_blt_mode & (CIRRUS_BLTMODE_COLOREXPAND |
953 CIRRUS_BLTMODE_PATTERNCOPY)) ==
a5082316
FB		 954 CIRRUS_BLTMODE_COLOREXPAND) {
955
956 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
b30d4608 957 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV)
4c8732d7 958 cirrus_bitblt_bgcol(s);
b30d4608 959 else
4c8732d7 960 cirrus_bitblt_fgcol(s);
b30d4608 961 s->cirrus_rop = cirrus_colorexpand_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
a5082316
FB		 962 } else {
963 cirrus_bitblt_fgcol(s);
964 cirrus_bitblt_bgcol(s);
965 s->cirrus_rop = cirrus_colorexpand[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
966 }
e69390ce 967 } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
b30d4608
FB		 968 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
969 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
970 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV)
971 cirrus_bitblt_bgcol(s);
972 else
973 cirrus_bitblt_fgcol(s);
974 s->cirrus_rop = cirrus_colorexpand_pattern_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
975 } else {
976 cirrus_bitblt_fgcol(s);
977 cirrus_bitblt_bgcol(s);
978 s->cirrus_rop = cirrus_colorexpand_pattern[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
979 }
980 } else {
981 s->cirrus_rop = cirrus_patternfill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
982 }
a21ae81d 983 } else {
96cf2df8
TS		 984 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
985 if (s->cirrus_blt_pixelwidth > 2) {
986 printf("src transparent without colorexpand must be 8bpp or 16bpp\n");
987 goto bitblt_ignore;
988 }
989 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) {
990 s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch;
991 s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch;
992 s->cirrus_rop = cirrus_bkwd_transp_rop[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
993 } else {
994 s->cirrus_rop = cirrus_fwd_transp_rop[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
995 }
996 } else {
997 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) {
998 s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch;
999 s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch;
1000 s->cirrus_rop = cirrus_bkwd_rop[rop_to_index[blt_rop]];
1001 } else {
1002 s->cirrus_rop = cirrus_fwd_rop[rop_to_index[blt_rop]];
1003 }
1004 }
1005 }
a21ae81d
FB		 1006 // setup bitblt engine.
1007 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSSRC) {
1008 if (!cirrus_bitblt_cputovideo(s))
1009 goto bitblt_ignore;
1010 } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSDEST) {
1011 if (!cirrus_bitblt_videotocpu(s))
1012 goto bitblt_ignore;
1013 } else {
1014 if (!cirrus_bitblt_videotovideo(s))
1015 goto bitblt_ignore;
1016 }
e6e5ad80 1017 }
e6e5ad80
FB		 1018 return;
1019 bitblt_ignore:;
1020 cirrus_bitblt_reset(s);
1021}
1022
1023static void cirrus_write_bitblt(CirrusVGAState * s, unsigned reg_value)
1024{
1025 unsigned old_value;
1026
4e12cd94
AK		 1027 old_value = s->vga.gr[0x31];
1028 s->vga.gr[0x31] = reg_value;
e6e5ad80
FB		 1029
1030 if (((old_value & CIRRUS_BLT_RESET) != 0) &&
1031 ((reg_value & CIRRUS_BLT_RESET) == 0)) {
1032 cirrus_bitblt_reset(s);
1033 } else if (((old_value & CIRRUS_BLT_START) == 0) &&
1034 ((reg_value & CIRRUS_BLT_START) != 0)) {
e6e5ad80
FB		 1035 cirrus_bitblt_start(s);
1036 }
1037}
1038
1039
1040/***************************************
1041 *
1042 * basic parameters
1043 *
1044 ***************************************/
1045
a4a2f59c 1046static void cirrus_get_offsets(VGACommonState *s1,
83acc96b
FB		 1047 uint32_t *pline_offset,
1048 uint32_t *pstart_addr,
1049 uint32_t *pline_compare)
e6e5ad80 1050{
4e12cd94 1051 CirrusVGAState * s = container_of(s1, CirrusVGAState, vga);
83acc96b 1052 uint32_t start_addr, line_offset, line_compare;
e6e5ad80 1053
4e12cd94
AK		 1054 line_offset = s->vga.cr[0x13]
1055 | ((s->vga.cr[0x1b] & 0x10) << 4);
e6e5ad80
FB		 1056 line_offset <<= 3;
1057 *pline_offset = line_offset;
1058
4e12cd94
AK		 1059 start_addr = (s->vga.cr[0x0c] << 8)
1060 | s->vga.cr[0x0d]
1061 | ((s->vga.cr[0x1b] & 0x01) << 16)
1062 | ((s->vga.cr[0x1b] & 0x0c) << 15)
1063 | ((s->vga.cr[0x1d] & 0x80) << 12);
e6e5ad80 1064 *pstart_addr = start_addr;
83acc96b 1065
4e12cd94
AK		 1066 line_compare = s->vga.cr[0x18] |
1067 ((s->vga.cr[0x07] & 0x10) << 4) |
1068 ((s->vga.cr[0x09] & 0x40) << 3);
83acc96b 1069 *pline_compare = line_compare;
e6e5ad80
FB		 1070}
1071
1072static uint32_t cirrus_get_bpp16_depth(CirrusVGAState * s)
1073{
1074 uint32_t ret = 16;
1075
1076 switch (s->cirrus_hidden_dac_data & 0xf) {
1077 case 0:
1078 ret = 15;
1079 break; /* Sierra HiColor */
1080 case 1:
1081 ret = 16;
1082 break; /* XGA HiColor */
1083 default:
1084#ifdef DEBUG_CIRRUS
1085 printf("cirrus: invalid DAC value %x in 16bpp\n",
1086 (s->cirrus_hidden_dac_data & 0xf));
1087#endif
1088 ret = 15; /* XXX */
1089 break;
1090 }
1091 return ret;
1092}
1093
a4a2f59c 1094static int cirrus_get_bpp(VGACommonState *s1)
e6e5ad80 1095{
4e12cd94 1096 CirrusVGAState * s = container_of(s1, CirrusVGAState, vga);
e6e5ad80
FB		 1097 uint32_t ret = 8;
1098
4e12cd94 1099 if ((s->vga.sr[0x07] & 0x01) != 0) {
e6e5ad80 1100 /* Cirrus SVGA */
4e12cd94 1101 switch (s->vga.sr[0x07] & CIRRUS_SR7_BPP_MASK) {
e6e5ad80
FB		 1102 case CIRRUS_SR7_BPP_8:
1103 ret = 8;
1104 break;
1105 case CIRRUS_SR7_BPP_16_DOUBLEVCLK:
1106 ret = cirrus_get_bpp16_depth(s);
1107 break;
1108 case CIRRUS_SR7_BPP_24:
1109 ret = 24;
1110 break;
1111 case CIRRUS_SR7_BPP_16:
1112 ret = cirrus_get_bpp16_depth(s);
1113 break;
1114 case CIRRUS_SR7_BPP_32:
1115 ret = 32;
1116 break;
1117 default:
1118#ifdef DEBUG_CIRRUS
4e12cd94 1119 printf("cirrus: unknown bpp - sr7=%x\n", s->vga.sr[0x7]);
e6e5ad80
FB		 1120#endif
1121 ret = 8;
1122 break;
1123 }
1124 } else {
1125 /* VGA */
aeb3c85f 1126 ret = 0;
e6e5ad80
FB		 1127 }
1128
1129 return ret;
1130}
1131
a4a2f59c 1132static void cirrus_get_resolution(VGACommonState *s, int *pwidth, int *pheight)
78e127ef
FB		 1133{
1134 int width, height;
3b46e624 1135
78e127ef 1136 width = (s->cr[0x01] + 1) * 8;
5fafdf24
TS		 1137 height = s->cr[0x12] |
1138 ((s->cr[0x07] & 0x02) << 7) |
78e127ef
FB		 1139 ((s->cr[0x07] & 0x40) << 3);
1140 height = (height + 1);
1141 /* interlace support */
1142 if (s->cr[0x1a] & 0x01)
1143 height = height * 2;
1144 *pwidth = width;
1145 *pheight = height;
1146}
1147
e6e5ad80
FB		 1148/***************************************
1149 *
1150 * bank memory
1151 *
1152 ***************************************/
1153
1154static void cirrus_update_bank_ptr(CirrusVGAState * s, unsigned bank_index)
1155{
1156 unsigned offset;
1157 unsigned limit;
1158
4e12cd94
AK		 1159 if ((s->vga.gr[0x0b] & 0x01) != 0) /* dual bank */
1160 offset = s->vga.gr[0x09 + bank_index];
e6e5ad80 1161 else /* single bank */
4e12cd94 1162 offset = s->vga.gr[0x09];
e6e5ad80 1163
4e12cd94 1164 if ((s->vga.gr[0x0b] & 0x20) != 0)
e6e5ad80
FB		 1165 offset <<= 14;
1166 else
1167 offset <<= 12;
1168
e3a4e4b6 1169 if (s->real_vram_size <= offset)
e6e5ad80
FB		 1170 limit = 0;
1171 else
e3a4e4b6 1172 limit = s->real_vram_size - offset;
e6e5ad80 1173
4e12cd94 1174 if (((s->vga.gr[0x0b] & 0x01) == 0) && (bank_index != 0)) {
e6e5ad80
FB		 1175 if (limit > 0x8000) {
1176 offset += 0x8000;
1177 limit -= 0x8000;
1178 } else {
1179 limit = 0;
1180 }
1181 }
1182
1183 if (limit > 0) {
1184 s->cirrus_bank_base[bank_index] = offset;
1185 s->cirrus_bank_limit[bank_index] = limit;
1186 } else {
1187 s->cirrus_bank_base[bank_index] = 0;
1188 s->cirrus_bank_limit[bank_index] = 0;
1189 }
1190}
1191
1192/***************************************
1193 *
1194 * I/O access between 0x3c4-0x3c5
1195 *
1196 ***************************************/
1197
8a82c322 1198static int cirrus_vga_read_sr(CirrusVGAState * s)
e6e5ad80 1199{
8a82c322 1200 switch (s->vga.sr_index) {
e6e5ad80
FB		 1201 case 0x00: // Standard VGA
1202 case 0x01: // Standard VGA
1203 case 0x02: // Standard VGA
1204 case 0x03: // Standard VGA
1205 case 0x04: // Standard VGA
8a82c322 1206 return s->vga.sr[s->vga.sr_index];
e6e5ad80 1207 case 0x06: // Unlock Cirrus extensions
8a82c322 1208 return s->vga.sr[s->vga.sr_index];
e6e5ad80
FB		 1209 case 0x10:
1210 case 0x30:
1211 case 0x50:
1212 case 0x70: // Graphics Cursor X
1213 case 0x90:
1214 case 0xb0:
1215 case 0xd0:
1216 case 0xf0: // Graphics Cursor X
8a82c322 1217 return s->vga.sr[0x10];
e6e5ad80
FB		 1218 case 0x11:
1219 case 0x31:
1220 case 0x51:
1221 case 0x71: // Graphics Cursor Y
1222 case 0x91:
1223 case 0xb1:
1224 case 0xd1:
a5082316 1225 case 0xf1: // Graphics Cursor Y
8a82c322 1226 return s->vga.sr[0x11];
aeb3c85f
FB		 1227 case 0x05: // ???
1228 case 0x07: // Extended Sequencer Mode
1229 case 0x08: // EEPROM Control
1230 case 0x09: // Scratch Register 0
1231 case 0x0a: // Scratch Register 1
1232 case 0x0b: // VCLK 0
1233 case 0x0c: // VCLK 1
1234 case 0x0d: // VCLK 2
1235 case 0x0e: // VCLK 3
1236 case 0x0f: // DRAM Control
e6e5ad80
FB		 1237 case 0x12: // Graphics Cursor Attribute
1238 case 0x13: // Graphics Cursor Pattern Address
1239 case 0x14: // Scratch Register 2
1240 case 0x15: // Scratch Register 3
1241 case 0x16: // Performance Tuning Register
1242 case 0x17: // Configuration Readback and Extended Control
1243 case 0x18: // Signature Generator Control
1244 case 0x19: // Signal Generator Result
1245 case 0x1a: // Signal Generator Result
1246 case 0x1b: // VCLK 0 Denominator & Post
1247 case 0x1c: // VCLK 1 Denominator & Post
1248 case 0x1d: // VCLK 2 Denominator & Post
1249 case 0x1e: // VCLK 3 Denominator & Post
1250 case 0x1f: // BIOS Write Enable and MCLK select
1251#ifdef DEBUG_CIRRUS
8a82c322 1252 printf("cirrus: handled inport sr_index %02x\n", s->vga.sr_index);
e6e5ad80 1253#endif
8a82c322 1254 return s->vga.sr[s->vga.sr_index];
e6e5ad80
FB		 1255 default:
1256#ifdef DEBUG_CIRRUS
8a82c322 1257 printf("cirrus: inport sr_index %02x\n", s->vga.sr_index);
e6e5ad80 1258#endif
8a82c322 1259 return 0xff;
e6e5ad80
FB		 1260 break;
1261 }
e6e5ad80
FB		 1262}
1263
31c63201 1264static void cirrus_vga_write_sr(CirrusVGAState * s, uint32_t val)
e6e5ad80 1265{
31c63201 1266 switch (s->vga.sr_index) {
e6e5ad80
FB		 1267 case 0x00: // Standard VGA
1268 case 0x01: // Standard VGA
1269 case 0x02: // Standard VGA
1270 case 0x03: // Standard VGA
1271 case 0x04: // Standard VGA
31c63201
JQ		 1272 s->vga.sr[s->vga.sr_index] = val & sr_mask[s->vga.sr_index];
1273 if (s->vga.sr_index == 1)
1274 s->vga.update_retrace_info(&s->vga);
1275 break;
e6e5ad80 1276 case 0x06: // Unlock Cirrus extensions
31c63201
JQ		 1277 val &= 0x17;
1278 if (val == 0x12) {
1279 s->vga.sr[s->vga.sr_index] = 0x12;
e6e5ad80 1280 } else {
31c63201 1281 s->vga.sr[s->vga.sr_index] = 0x0f;
e6e5ad80
FB		 1282 }
1283 break;
1284 case 0x10:
1285 case 0x30:
1286 case 0x50:
1287 case 0x70: // Graphics Cursor X
1288 case 0x90:
1289 case 0xb0:
1290 case 0xd0:
1291 case 0xf0: // Graphics Cursor X
31c63201
JQ		 1292 s->vga.sr[0x10] = val;
1293 s->hw_cursor_x = (val << 3) | (s->vga.sr_index >> 5);
e6e5ad80
FB		 1294 break;
1295 case 0x11:
1296 case 0x31:
1297 case 0x51:
1298 case 0x71: // Graphics Cursor Y
1299 case 0x91:
1300 case 0xb1:
1301 case 0xd1:
1302 case 0xf1: // Graphics Cursor Y
31c63201
JQ		 1303 s->vga.sr[0x11] = val;
1304 s->hw_cursor_y = (val << 3) | (s->vga.sr_index >> 5);
e6e5ad80
FB		 1305 break;
1306 case 0x07: // Extended Sequencer Mode
2bec46dc 1307 cirrus_update_memory_access(s);
e6e5ad80
FB		 1308 case 0x08: // EEPROM Control
1309 case 0x09: // Scratch Register 0
1310 case 0x0a: // Scratch Register 1
1311 case 0x0b: // VCLK 0
1312 case 0x0c: // VCLK 1
1313 case 0x0d: // VCLK 2
1314 case 0x0e: // VCLK 3
1315 case 0x0f: // DRAM Control
1316 case 0x12: // Graphics Cursor Attribute
1317 case 0x13: // Graphics Cursor Pattern Address
1318 case 0x14: // Scratch Register 2
1319 case 0x15: // Scratch Register 3
1320 case 0x16: // Performance Tuning Register
e6e5ad80
FB		 1321 case 0x18: // Signature Generator Control
1322 case 0x19: // Signature Generator Result
1323 case 0x1a: // Signature Generator Result
1324 case 0x1b: // VCLK 0 Denominator & Post
1325 case 0x1c: // VCLK 1 Denominator & Post
1326 case 0x1d: // VCLK 2 Denominator & Post
1327 case 0x1e: // VCLK 3 Denominator & Post
1328 case 0x1f: // BIOS Write Enable and MCLK select
31c63201 1329 s->vga.sr[s->vga.sr_index] = val;
e6e5ad80
FB		 1330#ifdef DEBUG_CIRRUS
1331 printf("cirrus: handled outport sr_index %02x, sr_value %02x\n",
31c63201 1332 s->vga.sr_index, val);
e6e5ad80
FB		 1333#endif
1334 break;
8926b517 1335 case 0x17: // Configuration Readback and Extended Control
31c63201
JQ		 1336 s->vga.sr[s->vga.sr_index] = (s->vga.sr[s->vga.sr_index] & 0x38)
1337 | (val & 0xc7);
8926b517
FB		 1338 cirrus_update_memory_access(s);
1339 break;
e6e5ad80
FB		 1340 default:
1341#ifdef DEBUG_CIRRUS
31c63201
JQ		 1342 printf("cirrus: outport sr_index %02x, sr_value %02x\n",
1343 s->vga.sr_index, val);
e6e5ad80
FB		 1344#endif
1345 break;
1346 }
e6e5ad80
FB		 1347}
1348
1349/***************************************
1350 *
1351 * I/O access at 0x3c6
1352 *
1353 ***************************************/
1354
957c9db5 1355static int cirrus_read_hidden_dac(CirrusVGAState * s)
e6e5ad80 1356{
a21ae81d 1357 if (++s->cirrus_hidden_dac_lockindex == 5) {
957c9db5
JQ		 1358 s->cirrus_hidden_dac_lockindex = 0;
1359 return s->cirrus_hidden_dac_data;
e6e5ad80 1360 }
957c9db5 1361 return 0xff;
e6e5ad80
FB		 1362}
1363
1364static void cirrus_write_hidden_dac(CirrusVGAState * s, int reg_value)
1365{
1366 if (s->cirrus_hidden_dac_lockindex == 4) {
1367 s->cirrus_hidden_dac_data = reg_value;
a21ae81d 1368#if defined(DEBUG_CIRRUS)
e6e5ad80
FB		 1369 printf("cirrus: outport hidden DAC, value %02x\n", reg_value);
1370#endif
1371 }
1372 s->cirrus_hidden_dac_lockindex = 0;
1373}
1374
1375/***************************************
1376 *
1377 * I/O access at 0x3c9
1378 *
1379 ***************************************/
1380
5deaeee3 1381static int cirrus_vga_read_palette(CirrusVGAState * s)
e6e5ad80 1382{
5deaeee3
JQ		 1383 int val;
1384
1385 if ((s->vga.sr[0x12] & CIRRUS_CURSOR_HIDDENPEL)) {
1386 val = s->cirrus_hidden_palette[(s->vga.dac_read_index & 0x0f) * 3 +
1387 s->vga.dac_sub_index];
1388 } else {
1389 val = s->vga.palette[s->vga.dac_read_index * 3 + s->vga.dac_sub_index];
1390 }
4e12cd94
AK		 1391 if (++s->vga.dac_sub_index == 3) {
1392 s->vga.dac_sub_index = 0;
1393 s->vga.dac_read_index++;
e6e5ad80 1394 }
5deaeee3 1395 return val;
e6e5ad80
FB		 1396}
1397
86948bb1 1398static void cirrus_vga_write_palette(CirrusVGAState * s, int reg_value)
e6e5ad80 1399{
4e12cd94
AK		 1400 s->vga.dac_cache[s->vga.dac_sub_index] = reg_value;
1401 if (++s->vga.dac_sub_index == 3) {
86948bb1
JQ		 1402 if ((s->vga.sr[0x12] & CIRRUS_CURSOR_HIDDENPEL)) {
1403 memcpy(&s->cirrus_hidden_palette[(s->vga.dac_write_index & 0x0f) * 3],
1404 s->vga.dac_cache, 3);
1405 } else {
1406 memcpy(&s->vga.palette[s->vga.dac_write_index * 3], s->vga.dac_cache, 3);
1407 }
a5082316 1408 /* XXX update cursor */
4e12cd94
AK		 1409 s->vga.dac_sub_index = 0;
1410 s->vga.dac_write_index++;
e6e5ad80 1411 }
e6e5ad80
FB		 1412}
1413
1414/***************************************
1415 *
1416 * I/O access between 0x3ce-0x3cf
1417 *
1418 ***************************************/
1419
f705db9d 1420static int cirrus_vga_read_gr(CirrusVGAState * s, unsigned reg_index)
e6e5ad80
FB		 1421{
1422 switch (reg_index) {
aeb3c85f 1423 case 0x00: // Standard VGA, BGCOLOR 0x000000ff
f705db9d 1424 return s->cirrus_shadow_gr0;
aeb3c85f 1425 case 0x01: // Standard VGA, FGCOLOR 0x000000ff
f705db9d 1426 return s->cirrus_shadow_gr1;
e6e5ad80
FB		 1427 case 0x02: // Standard VGA
1428 case 0x03: // Standard VGA
1429 case 0x04: // Standard VGA
1430 case 0x06: // Standard VGA
1431 case 0x07: // Standard VGA
1432 case 0x08: // Standard VGA
f705db9d 1433 return s->vga.gr[s->vga.gr_index];
e6e5ad80
FB		 1434 case 0x05: // Standard VGA, Cirrus extended mode
1435 default:
1436 break;
1437 }
1438
1439 if (reg_index < 0x3a) {
f705db9d 1440 return s->vga.gr[reg_index];
e6e5ad80
FB		 1441 } else {
1442#ifdef DEBUG_CIRRUS
1443 printf("cirrus: inport gr_index %02x\n", reg_index);
1444#endif
f705db9d 1445 return 0xff;
e6e5ad80 1446 }
e6e5ad80
FB		 1447}
1448
22286bc6
JQ		 1449static void
1450cirrus_vga_write_gr(CirrusVGAState * s, unsigned reg_index, int reg_value)
e6e5ad80 1451{
a5082316
FB		 1452#if defined(DEBUG_BITBLT) && 0
1453 printf("gr%02x: %02x\n", reg_index, reg_value);
1454#endif
e6e5ad80
FB		 1455 switch (reg_index) {
1456 case 0x00: // Standard VGA, BGCOLOR 0x000000ff
f22f5b07 1457 s->vga.gr[reg_index] = reg_value & gr_mask[reg_index];
aeb3c85f 1458 s->cirrus_shadow_gr0 = reg_value;
22286bc6 1459 break;
e6e5ad80 1460 case 0x01: // Standard VGA, FGCOLOR 0x000000ff
f22f5b07 1461 s->vga.gr[reg_index] = reg_value & gr_mask[reg_index];
aeb3c85f 1462 s->cirrus_shadow_gr1 = reg_value;
22286bc6 1463 break;
e6e5ad80
FB		 1464 case 0x02: // Standard VGA
1465 case 0x03: // Standard VGA
1466 case 0x04: // Standard VGA
1467 case 0x06: // Standard VGA
1468 case 0x07: // Standard VGA
1469 case 0x08: // Standard VGA
22286bc6
JQ		 1470 s->vga.gr[reg_index] = reg_value & gr_mask[reg_index];
1471 break;
e6e5ad80 1472 case 0x05: // Standard VGA, Cirrus extended mode
4e12cd94 1473 s->vga.gr[reg_index] = reg_value & 0x7f;
8926b517 1474 cirrus_update_memory_access(s);
e6e5ad80
FB		 1475 break;
1476 case 0x09: // bank offset #0
1477 case 0x0A: // bank offset #1
4e12cd94 1478 s->vga.gr[reg_index] = reg_value;
8926b517
FB		 1479 cirrus_update_bank_ptr(s, 0);
1480 cirrus_update_bank_ptr(s, 1);
2bec46dc 1481 cirrus_update_memory_access(s);
8926b517 1482 break;
e6e5ad80 1483 case 0x0B:
4e12cd94 1484 s->vga.gr[reg_index] = reg_value;
e6e5ad80
FB		 1485 cirrus_update_bank_ptr(s, 0);
1486 cirrus_update_bank_ptr(s, 1);
8926b517 1487 cirrus_update_memory_access(s);
e6e5ad80
FB		 1488 break;
1489 case 0x10: // BGCOLOR 0x0000ff00
1490 case 0x11: // FGCOLOR 0x0000ff00
1491 case 0x12: // BGCOLOR 0x00ff0000
1492 case 0x13: // FGCOLOR 0x00ff0000
1493 case 0x14: // BGCOLOR 0xff000000
1494 case 0x15: // FGCOLOR 0xff000000
1495 case 0x20: // BLT WIDTH 0x0000ff
1496 case 0x22: // BLT HEIGHT 0x0000ff
1497 case 0x24: // BLT DEST PITCH 0x0000ff
1498 case 0x26: // BLT SRC PITCH 0x0000ff
1499 case 0x28: // BLT DEST ADDR 0x0000ff
1500 case 0x29: // BLT DEST ADDR 0x00ff00
1501 case 0x2c: // BLT SRC ADDR 0x0000ff
1502 case 0x2d: // BLT SRC ADDR 0x00ff00
a5082316 1503 case 0x2f: // BLT WRITEMASK
e6e5ad80
FB		 1504 case 0x30: // BLT MODE
1505 case 0x32: // RASTER OP
a21ae81d 1506 case 0x33: // BLT MODEEXT
e6e5ad80
FB		 1507 case 0x34: // BLT TRANSPARENT COLOR 0x00ff
1508 case 0x35: // BLT TRANSPARENT COLOR 0xff00
1509 case 0x38: // BLT TRANSPARENT COLOR MASK 0x00ff
1510 case 0x39: // BLT TRANSPARENT COLOR MASK 0xff00
4e12cd94 1511 s->vga.gr[reg_index] = reg_value;
e6e5ad80
FB		 1512 break;
1513 case 0x21: // BLT WIDTH 0x001f00
1514 case 0x23: // BLT HEIGHT 0x001f00
1515 case 0x25: // BLT DEST PITCH 0x001f00
1516 case 0x27: // BLT SRC PITCH 0x001f00
4e12cd94 1517 s->vga.gr[reg_index] = reg_value & 0x1f;
e6e5ad80
FB		 1518 break;
1519 case 0x2a: // BLT DEST ADDR 0x3f0000
4e12cd94 1520 s->vga.gr[reg_index] = reg_value & 0x3f;
a5082316 1521 /* if auto start mode, starts bit blt now */
4e12cd94 1522 if (s->vga.gr[0x31] & CIRRUS_BLT_AUTOSTART) {
a5082316
FB		 1523 cirrus_bitblt_start(s);
1524 }
1525 break;
e6e5ad80 1526 case 0x2e: // BLT SRC ADDR 0x3f0000
4e12cd94 1527 s->vga.gr[reg_index] = reg_value & 0x3f;
e6e5ad80
FB		 1528 break;
1529 case 0x31: // BLT STATUS/START
1530 cirrus_write_bitblt(s, reg_value);
1531 break;
1532 default:
1533#ifdef DEBUG_CIRRUS
1534 printf("cirrus: outport gr_index %02x, gr_value %02x\n", reg_index,
1535 reg_value);
1536#endif
1537 break;
1538 }
e6e5ad80
FB		 1539}
1540
1541/***************************************
1542 *
1543 * I/O access between 0x3d4-0x3d5
1544 *
1545 ***************************************/
1546
b863d514 1547static int cirrus_vga_read_cr(CirrusVGAState * s, unsigned reg_index)
e6e5ad80
FB		 1548{
1549 switch (reg_index) {
1550 case 0x00: // Standard VGA
1551 case 0x01: // Standard VGA
1552 case 0x02: // Standard VGA
1553 case 0x03: // Standard VGA
1554 case 0x04: // Standard VGA
1555 case 0x05: // Standard VGA
1556 case 0x06: // Standard VGA
1557 case 0x07: // Standard VGA
1558 case 0x08: // Standard VGA
1559 case 0x09: // Standard VGA
1560 case 0x0a: // Standard VGA
1561 case 0x0b: // Standard VGA
1562 case 0x0c: // Standard VGA
1563 case 0x0d: // Standard VGA
1564 case 0x0e: // Standard VGA
1565 case 0x0f: // Standard VGA
1566 case 0x10: // Standard VGA
1567 case 0x11: // Standard VGA
1568 case 0x12: // Standard VGA
1569 case 0x13: // Standard VGA
1570 case 0x14: // Standard VGA
1571 case 0x15: // Standard VGA
1572 case 0x16: // Standard VGA
1573 case 0x17: // Standard VGA
1574 case 0x18: // Standard VGA
b863d514 1575 return s->vga.cr[s->vga.cr_index];
ca896ef3 1576 case 0x24: // Attribute Controller Toggle Readback (R)
b863d514 1577 return (s->vga.ar_flip_flop << 7);
e6e5ad80
FB		 1578 case 0x19: // Interlace End
1579 case 0x1a: // Miscellaneous Control
1580 case 0x1b: // Extended Display Control
1581 case 0x1c: // Sync Adjust and Genlock
1582 case 0x1d: // Overlay Extended Control
1583 case 0x22: // Graphics Data Latches Readback (R)
e6e5ad80
FB		 1584 case 0x25: // Part Status
1585 case 0x27: // Part ID (R)
b863d514 1586 return s->vga.cr[s->vga.cr_index];
e6e5ad80 1587 case 0x26: // Attribute Controller Index Readback (R)
b863d514 1588 return s->vga.ar_index & 0x3f;
e6e5ad80
FB		 1589 break;
1590 default:
1591#ifdef DEBUG_CIRRUS
1592 printf("cirrus: inport cr_index %02x\n", reg_index);
e6e5ad80 1593#endif
b863d514 1594 return 0xff;
e6e5ad80 1595 }
e6e5ad80
FB		 1596}
1597
4ec1ce04 1598static void cirrus_vga_write_cr(CirrusVGAState * s, int reg_value)
e6e5ad80 1599{
4ec1ce04 1600 switch (s->vga.cr_index) {
e6e5ad80
FB		 1601 case 0x00: // Standard VGA
1602 case 0x01: // Standard VGA
1603 case 0x02: // Standard VGA
1604 case 0x03: // Standard VGA
1605 case 0x04: // Standard VGA
1606 case 0x05: // Standard VGA
1607 case 0x06: // Standard VGA
1608 case 0x07: // Standard VGA
1609 case 0x08: // Standard VGA
1610 case 0x09: // Standard VGA
1611 case 0x0a: // Standard VGA
1612 case 0x0b: // Standard VGA
1613 case 0x0c: // Standard VGA
1614 case 0x0d: // Standard VGA
1615 case 0x0e: // Standard VGA
1616 case 0x0f: // Standard VGA
1617 case 0x10: // Standard VGA
1618 case 0x11: // Standard VGA
1619 case 0x12: // Standard VGA
1620 case 0x13: // Standard VGA
1621 case 0x14: // Standard VGA
1622 case 0x15: // Standard VGA
1623 case 0x16: // Standard VGA
1624 case 0x17: // Standard VGA
1625 case 0x18: // Standard VGA
4ec1ce04
JQ		 1626 /* handle CR0-7 protection */
1627 if ((s->vga.cr[0x11] & 0x80) && s->vga.cr_index <= 7) {
1628 /* can always write bit 4 of CR7 */
1629 if (s->vga.cr_index == 7)
1630 s->vga.cr[7] = (s->vga.cr[7] & ~0x10) | (reg_value & 0x10);
1631 return;
1632 }
1633 s->vga.cr[s->vga.cr_index] = reg_value;
1634 switch(s->vga.cr_index) {
1635 case 0x00:
1636 case 0x04:
1637 case 0x05:
1638 case 0x06:
1639 case 0x07:
1640 case 0x11:
1641 case 0x17:
1642 s->vga.update_retrace_info(&s->vga);
1643 break;
1644 }
1645 break;
e6e5ad80
FB		 1646 case 0x19: // Interlace End
1647 case 0x1a: // Miscellaneous Control
1648 case 0x1b: // Extended Display Control
1649 case 0x1c: // Sync Adjust and Genlock
ae184e4a 1650 case 0x1d: // Overlay Extended Control
4ec1ce04 1651 s->vga.cr[s->vga.cr_index] = reg_value;
e6e5ad80
FB		 1652#ifdef DEBUG_CIRRUS
1653 printf("cirrus: handled outport cr_index %02x, cr_value %02x\n",
4ec1ce04 1654 s->vga.cr_index, reg_value);
e6e5ad80
FB		 1655#endif
1656 break;
1657 case 0x22: // Graphics Data Latches Readback (R)
1658 case 0x24: // Attribute Controller Toggle Readback (R)
1659 case 0x26: // Attribute Controller Index Readback (R)
1660 case 0x27: // Part ID (R)
1661 break;
e6e5ad80
FB		 1662 case 0x25: // Part Status
1663 default:
1664#ifdef DEBUG_CIRRUS
4ec1ce04
JQ		 1665 printf("cirrus: outport cr_index %02x, cr_value %02x\n",
1666 s->vga.cr_index, reg_value);
e6e5ad80
FB		 1667#endif
1668 break;
1669 }
e6e5ad80
FB		 1670}
1671
1672/***************************************
1673 *
1674 * memory-mapped I/O (bitblt)
1675 *
1676 ***************************************/
1677
1678static uint8_t cirrus_mmio_blt_read(CirrusVGAState * s, unsigned address)
1679{
1680 int value = 0xff;
1681
1682 switch (address) {
1683 case (CIRRUS_MMIO_BLTBGCOLOR + 0):
f705db9d 1684 value = cirrus_vga_read_gr(s, 0x00);
e6e5ad80
FB		 1685 break;
1686 case (CIRRUS_MMIO_BLTBGCOLOR + 1):
f705db9d 1687 value = cirrus_vga_read_gr(s, 0x10);
e6e5ad80
FB		 1688 break;
1689 case (CIRRUS_MMIO_BLTBGCOLOR + 2):
f705db9d 1690 value = cirrus_vga_read_gr(s, 0x12);
e6e5ad80
FB		 1691 break;
1692 case (CIRRUS_MMIO_BLTBGCOLOR + 3):
f705db9d 1693 value = cirrus_vga_read_gr(s, 0x14);
e6e5ad80
FB		 1694 break;
1695 case (CIRRUS_MMIO_BLTFGCOLOR + 0):
f705db9d 1696 value = cirrus_vga_read_gr(s, 0x01);
e6e5ad80
FB		 1697 break;
1698 case (CIRRUS_MMIO_BLTFGCOLOR + 1):
f705db9d 1699 value = cirrus_vga_read_gr(s, 0x11);
e6e5ad80
FB		 1700 break;
1701 case (CIRRUS_MMIO_BLTFGCOLOR + 2):
f705db9d 1702 value = cirrus_vga_read_gr(s, 0x13);
e6e5ad80
FB		 1703 break;
1704 case (CIRRUS_MMIO_BLTFGCOLOR + 3):
f705db9d 1705 value = cirrus_vga_read_gr(s, 0x15);
e6e5ad80
FB		 1706 break;
1707 case (CIRRUS_MMIO_BLTWIDTH + 0):
f705db9d 1708 value = cirrus_vga_read_gr(s, 0x20);
e6e5ad80
FB		 1709 break;
1710 case (CIRRUS_MMIO_BLTWIDTH + 1):
f705db9d 1711 value = cirrus_vga_read_gr(s, 0x21);
e6e5ad80
FB		 1712 break;
1713 case (CIRRUS_MMIO_BLTHEIGHT + 0):
f705db9d 1714 value = cirrus_vga_read_gr(s, 0x22);
e6e5ad80
FB		 1715 break;
1716 case (CIRRUS_MMIO_BLTHEIGHT + 1):
f705db9d 1717 value = cirrus_vga_read_gr(s, 0x23);
e6e5ad80
FB		 1718 break;
1719 case (CIRRUS_MMIO_BLTDESTPITCH + 0):
f705db9d 1720 value = cirrus_vga_read_gr(s, 0x24);
e6e5ad80
FB		 1721 break;
1722 case (CIRRUS_MMIO_BLTDESTPITCH + 1):
f705db9d 1723 value = cirrus_vga_read_gr(s, 0x25);
e6e5ad80
FB		 1724 break;
1725 case (CIRRUS_MMIO_BLTSRCPITCH + 0):
f705db9d 1726 value = cirrus_vga_read_gr(s, 0x26);
e6e5ad80
FB		 1727 break;
1728 case (CIRRUS_MMIO_BLTSRCPITCH + 1):
f705db9d 1729 value = cirrus_vga_read_gr(s, 0x27);
e6e5ad80
FB		 1730 break;
1731 case (CIRRUS_MMIO_BLTDESTADDR + 0):
f705db9d 1732 value = cirrus_vga_read_gr(s, 0x28);
e6e5ad80
FB		 1733 break;
1734 case (CIRRUS_MMIO_BLTDESTADDR + 1):
f705db9d 1735 value = cirrus_vga_read_gr(s, 0x29);
e6e5ad80
FB		 1736 break;
1737 case (CIRRUS_MMIO_BLTDESTADDR + 2):
f705db9d 1738 value = cirrus_vga_read_gr(s, 0x2a);
e6e5ad80
FB		 1739 break;
1740 case (CIRRUS_MMIO_BLTSRCADDR + 0):
f705db9d 1741 value = cirrus_vga_read_gr(s, 0x2c);
e6e5ad80
FB		 1742 break;
1743 case (CIRRUS_MMIO_BLTSRCADDR + 1):
f705db9d 1744 value = cirrus_vga_read_gr(s, 0x2d);
e6e5ad80
FB		 1745 break;
1746 case (CIRRUS_MMIO_BLTSRCADDR + 2):
f705db9d 1747 value = cirrus_vga_read_gr(s, 0x2e);
e6e5ad80
FB		 1748 break;
1749 case CIRRUS_MMIO_BLTWRITEMASK:
f705db9d 1750 value = cirrus_vga_read_gr(s, 0x2f);
e6e5ad80
FB		 1751 break;
1752 case CIRRUS_MMIO_BLTMODE:
f705db9d 1753 value = cirrus_vga_read_gr(s, 0x30);
e6e5ad80
FB		 1754 break;
1755 case CIRRUS_MMIO_BLTROP:
f705db9d 1756 value = cirrus_vga_read_gr(s, 0x32);
e6e5ad80 1757 break;
a21ae81d 1758 case CIRRUS_MMIO_BLTMODEEXT:
f705db9d 1759 value = cirrus_vga_read_gr(s, 0x33);
a21ae81d 1760 break;
e6e5ad80 1761 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0):
f705db9d 1762 value = cirrus_vga_read_gr(s, 0x34);
e6e5ad80
FB		 1763 break;
1764 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1):
f705db9d 1765 value = cirrus_vga_read_gr(s, 0x35);
e6e5ad80
FB		 1766 break;
1767 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0):
f705db9d 1768 value = cirrus_vga_read_gr(s, 0x38);
e6e5ad80
FB		 1769 break;
1770 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1):
f705db9d 1771 value = cirrus_vga_read_gr(s, 0x39);
e6e5ad80
FB		 1772 break;
1773 case CIRRUS_MMIO_BLTSTATUS:
f705db9d 1774 value = cirrus_vga_read_gr(s, 0x31);
e6e5ad80
FB		 1775 break;
1776 default:
1777#ifdef DEBUG_CIRRUS
1778 printf("cirrus: mmio read - address 0x%04x\n", address);
1779#endif
1780 break;
1781 }
1782
1783 return (uint8_t) value;
1784}
1785
1786static void cirrus_mmio_blt_write(CirrusVGAState * s, unsigned address,
1787 uint8_t value)
1788{
1789 switch (address) {
1790 case (CIRRUS_MMIO_BLTBGCOLOR + 0):
22286bc6 1791 cirrus_vga_write_gr(s, 0x00, value);
e6e5ad80
FB		 1792 break;
1793 case (CIRRUS_MMIO_BLTBGCOLOR + 1):
22286bc6 1794 cirrus_vga_write_gr(s, 0x10, value);
e6e5ad80
FB		 1795 break;
1796 case (CIRRUS_MMIO_BLTBGCOLOR + 2):
22286bc6 1797 cirrus_vga_write_gr(s, 0x12, value);
e6e5ad80
FB		 1798 break;
1799 case (CIRRUS_MMIO_BLTBGCOLOR + 3):
22286bc6 1800 cirrus_vga_write_gr(s, 0x14, value);
e6e5ad80
FB		 1801 break;
1802 case (CIRRUS_MMIO_BLTFGCOLOR + 0):
22286bc6 1803 cirrus_vga_write_gr(s, 0x01, value);
e6e5ad80
FB		 1804 break;
1805 case (CIRRUS_MMIO_BLTFGCOLOR + 1):
22286bc6 1806 cirrus_vga_write_gr(s, 0x11, value);
e6e5ad80
FB		 1807 break;
1808 case (CIRRUS_MMIO_BLTFGCOLOR + 2):
22286bc6 1809 cirrus_vga_write_gr(s, 0x13, value);
e6e5ad80
FB		 1810 break;
1811 case (CIRRUS_MMIO_BLTFGCOLOR + 3):
22286bc6 1812 cirrus_vga_write_gr(s, 0x15, value);
e6e5ad80
FB		 1813 break;
1814 case (CIRRUS_MMIO_BLTWIDTH + 0):
22286bc6 1815 cirrus_vga_write_gr(s, 0x20, value);
e6e5ad80
FB		 1816 break;
1817 case (CIRRUS_MMIO_BLTWIDTH + 1):
22286bc6 1818 cirrus_vga_write_gr(s, 0x21, value);
e6e5ad80
FB		 1819 break;
1820 case (CIRRUS_MMIO_BLTHEIGHT + 0):
22286bc6 1821 cirrus_vga_write_gr(s, 0x22, value);
e6e5ad80
FB		 1822 break;
1823 case (CIRRUS_MMIO_BLTHEIGHT + 1):
22286bc6 1824 cirrus_vga_write_gr(s, 0x23, value);
e6e5ad80
FB		 1825 break;
1826 case (CIRRUS_MMIO_BLTDESTPITCH + 0):
22286bc6 1827 cirrus_vga_write_gr(s, 0x24, value);
e6e5ad80
FB		 1828 break;
1829 case (CIRRUS_MMIO_BLTDESTPITCH + 1):
22286bc6 1830 cirrus_vga_write_gr(s, 0x25, value);
e6e5ad80
FB		 1831 break;
1832 case (CIRRUS_MMIO_BLTSRCPITCH + 0):
22286bc6 1833 cirrus_vga_write_gr(s, 0x26, value);
e6e5ad80
FB		 1834 break;
1835 case (CIRRUS_MMIO_BLTSRCPITCH + 1):
22286bc6 1836 cirrus_vga_write_gr(s, 0x27, value);
e6e5ad80
FB		 1837 break;
1838 case (CIRRUS_MMIO_BLTDESTADDR + 0):
22286bc6 1839 cirrus_vga_write_gr(s, 0x28, value);
e6e5ad80
FB		 1840 break;
1841 case (CIRRUS_MMIO_BLTDESTADDR + 1):
22286bc6 1842 cirrus_vga_write_gr(s, 0x29, value);
e6e5ad80
FB		 1843 break;
1844 case (CIRRUS_MMIO_BLTDESTADDR + 2):
22286bc6 1845 cirrus_vga_write_gr(s, 0x2a, value);
e6e5ad80
FB		 1846 break;
1847 case (CIRRUS_MMIO_BLTDESTADDR + 3):
1848 /* ignored */
1849 break;
1850 case (CIRRUS_MMIO_BLTSRCADDR + 0):
22286bc6 1851 cirrus_vga_write_gr(s, 0x2c, value);
e6e5ad80
FB		 1852 break;
1853 case (CIRRUS_MMIO_BLTSRCADDR + 1):
22286bc6 1854 cirrus_vga_write_gr(s, 0x2d, value);
e6e5ad80
FB		 1855 break;
1856 case (CIRRUS_MMIO_BLTSRCADDR + 2):
22286bc6 1857 cirrus_vga_write_gr(s, 0x2e, value);
e6e5ad80
FB		 1858 break;
1859 case CIRRUS_MMIO_BLTWRITEMASK:
22286bc6 1860 cirrus_vga_write_gr(s, 0x2f, value);
e6e5ad80
FB		 1861 break;
1862 case CIRRUS_MMIO_BLTMODE:
22286bc6 1863 cirrus_vga_write_gr(s, 0x30, value);
e6e5ad80
FB		 1864 break;
1865 case CIRRUS_MMIO_BLTROP:
22286bc6 1866 cirrus_vga_write_gr(s, 0x32, value);
e6e5ad80 1867 break;
a21ae81d 1868 case CIRRUS_MMIO_BLTMODEEXT:
22286bc6 1869 cirrus_vga_write_gr(s, 0x33, value);
a21ae81d 1870 break;
e6e5ad80 1871 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0):
22286bc6 1872 cirrus_vga_write_gr(s, 0x34, value);
e6e5ad80
FB		 1873 break;
1874 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1):
22286bc6 1875 cirrus_vga_write_gr(s, 0x35, value);
e6e5ad80
FB		 1876 break;
1877 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0):
22286bc6 1878 cirrus_vga_write_gr(s, 0x38, value);
e6e5ad80
FB		 1879 break;
1880 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1):
22286bc6 1881 cirrus_vga_write_gr(s, 0x39, value);
e6e5ad80
FB		 1882 break;
1883 case CIRRUS_MMIO_BLTSTATUS:
22286bc6 1884 cirrus_vga_write_gr(s, 0x31, value);
e6e5ad80
FB		 1885 break;
1886 default:
1887#ifdef DEBUG_CIRRUS
1888 printf("cirrus: mmio write - addr 0x%04x val 0x%02x (ignored)\n",
1889 address, value);
1890#endif
1891 break;
1892 }
1893}
1894
e6e5ad80
FB		 1895/***************************************
1896 *
1897 * write mode 4/5
1898 *
e6e5ad80
FB		 1899 ***************************************/
1900
1901static void cirrus_mem_writeb_mode4and5_8bpp(CirrusVGAState * s,
1902 unsigned mode,
1903 unsigned offset,
1904 uint32_t mem_value)
1905{
1906 int x;
1907 unsigned val = mem_value;
1908 uint8_t *dst;
1909
4e12cd94 1910 dst = s->vga.vram_ptr + (offset &= s->cirrus_addr_mask);
e6e5ad80
FB		 1911 for (x = 0; x < 8; x++) {
1912 if (val & 0x80) {
0b74ed78 1913 *dst = s->cirrus_shadow_gr1;
e6e5ad80 1914 } else if (mode == 5) {
0b74ed78 1915 *dst = s->cirrus_shadow_gr0;
e6e5ad80
FB		 1916 }
1917 val <<= 1;
0b74ed78 1918 dst++;
e6e5ad80 1919 }
fd4aa979 1920 memory_region_set_dirty(&s->vga.vram, offset, 8);
e6e5ad80
FB		 1921}
1922
1923static void cirrus_mem_writeb_mode4and5_16bpp(CirrusVGAState * s,
1924 unsigned mode,
1925 unsigned offset,
1926 uint32_t mem_value)
1927{
1928 int x;
1929 unsigned val = mem_value;
1930 uint8_t *dst;
1931
4e12cd94 1932 dst = s->vga.vram_ptr + (offset &= s->cirrus_addr_mask);
e6e5ad80
FB		 1933 for (x = 0; x < 8; x++) {
1934 if (val & 0x80) {
0b74ed78 1935 *dst = s->cirrus_shadow_gr1;
4e12cd94 1936 *(dst + 1) = s->vga.gr[0x11];
e6e5ad80 1937 } else if (mode == 5) {
0b74ed78 1938 *dst = s->cirrus_shadow_gr0;
4e12cd94 1939 *(dst + 1) = s->vga.gr[0x10];
e6e5ad80
FB		 1940 }
1941 val <<= 1;
0b74ed78 1942 dst += 2;
e6e5ad80 1943 }
fd4aa979 1944 memory_region_set_dirty(&s->vga.vram, offset, 16);
e6e5ad80
FB		 1945}
1946
1947/***************************************
1948 *
1949 * memory access between 0xa0000-0xbffff
1950 *
1951 ***************************************/
1952
a815b166 1953static uint64_t cirrus_vga_mem_read(void *opaque,
a8170e5e 1954 hwaddr addr,
a815b166 1955 uint32_t size)
e6e5ad80
FB		 1956{
1957 CirrusVGAState *s = opaque;
1958 unsigned bank_index;
1959 unsigned bank_offset;
1960 uint32_t val;
1961
4e12cd94 1962 if ((s->vga.sr[0x07] & 0x01) == 0) {
b2a5e761 1963 return vga_mem_readb(&s->vga, addr);
e6e5ad80
FB		 1964 }
1965
1966 if (addr < 0x10000) {
1967 /* XXX handle bitblt */
1968 /* video memory */
1969 bank_index = addr >> 15;
1970 bank_offset = addr & 0x7fff;
1971 if (bank_offset < s->cirrus_bank_limit[bank_index]) {
1972 bank_offset += s->cirrus_bank_base[bank_index];
4e12cd94 1973 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
e6e5ad80 1974 bank_offset <<= 4;
4e12cd94 1975 } else if (s->vga.gr[0x0B] & 0x02) {
e6e5ad80
FB		 1976 bank_offset <<= 3;
1977 }
1978 bank_offset &= s->cirrus_addr_mask;
4e12cd94 1979 val = *(s->vga.vram_ptr + bank_offset);
e6e5ad80
FB		 1980 } else
1981 val = 0xff;
1982 } else if (addr >= 0x18000 && addr < 0x18100) {
1983 /* memory-mapped I/O */
1984 val = 0xff;
4e12cd94 1985 if ((s->vga.sr[0x17] & 0x44) == 0x04) {
e6e5ad80
FB		 1986 val = cirrus_mmio_blt_read(s, addr & 0xff);
1987 }
1988 } else {
1989 val = 0xff;
1990#ifdef DEBUG_CIRRUS
0bf9e31a 1991 printf("cirrus: mem_readb " TARGET_FMT_plx "\n", addr);
e6e5ad80
FB		 1992#endif
1993 }
1994 return val;
1995}
1996
a815b166 1997static void cirrus_vga_mem_write(void *opaque,
a8170e5e 1998 hwaddr addr,
a815b166
AK		 1999 uint64_t mem_value,
2000 uint32_t size)
e6e5ad80
FB		 2001{
2002 CirrusVGAState *s = opaque;
2003 unsigned bank_index;
2004 unsigned bank_offset;
2005 unsigned mode;
2006
4e12cd94 2007 if ((s->vga.sr[0x07] & 0x01) == 0) {
b2a5e761 2008 vga_mem_writeb(&s->vga, addr, mem_value);
e6e5ad80
FB		 2009 return;
2010 }
2011
2012 if (addr < 0x10000) {
2013 if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2014 /* bitblt */
2015 *s->cirrus_srcptr++ = (uint8_t) mem_value;
a5082316 2016 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
e6e5ad80
FB		 2017 cirrus_bitblt_cputovideo_next(s);
2018 }
2019 } else {
2020 /* video memory */
2021 bank_index = addr >> 15;
2022 bank_offset = addr & 0x7fff;
2023 if (bank_offset < s->cirrus_bank_limit[bank_index]) {
2024 bank_offset += s->cirrus_bank_base[bank_index];
4e12cd94 2025 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
e6e5ad80 2026 bank_offset <<= 4;
4e12cd94 2027 } else if (s->vga.gr[0x0B] & 0x02) {
e6e5ad80
FB		 2028 bank_offset <<= 3;
2029 }
2030 bank_offset &= s->cirrus_addr_mask;
4e12cd94
AK		 2031 mode = s->vga.gr[0x05] & 0x7;
2032 if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) {
2033 *(s->vga.vram_ptr + bank_offset) = mem_value;
fd4aa979
BS		 2034 memory_region_set_dirty(&s->vga.vram, bank_offset,
2035 sizeof(mem_value));
e6e5ad80 2036 } else {
4e12cd94 2037 if ((s->vga.gr[0x0B] & 0x14) != 0x14) {
e6e5ad80
FB		 2038 cirrus_mem_writeb_mode4and5_8bpp(s, mode,
2039 bank_offset,
2040 mem_value);
2041 } else {
2042 cirrus_mem_writeb_mode4and5_16bpp(s, mode,
2043 bank_offset,
2044 mem_value);
2045 }
2046 }
2047 }
2048 }
2049 } else if (addr >= 0x18000 && addr < 0x18100) {
2050 /* memory-mapped I/O */
4e12cd94 2051 if ((s->vga.sr[0x17] & 0x44) == 0x04) {
e6e5ad80
FB		 2052 cirrus_mmio_blt_write(s, addr & 0xff, mem_value);
2053 }
2054 } else {
2055#ifdef DEBUG_CIRRUS
08406b03 2056 printf("cirrus: mem_writeb " TARGET_FMT_plx " value %02x\n", addr,
2057 mem_value);
e6e5ad80
FB		 2058#endif
2059 }
2060}
2061
b1950430
AK		 2062static const MemoryRegionOps cirrus_vga_mem_ops = {
2063 .read = cirrus_vga_mem_read,
2064 .write = cirrus_vga_mem_write,
2065 .endianness = DEVICE_LITTLE_ENDIAN,
a815b166
AK		 2066 .impl = {
2067 .min_access_size = 1,
2068 .max_access_size = 1,
2069 },
e6e5ad80
FB		 2070};
2071
a5082316
FB		 2072/***************************************
2073 *
2074 * hardware cursor
2075 *
2076 ***************************************/
2077
2078static inline void invalidate_cursor1(CirrusVGAState *s)
2079{
2080 if (s->last_hw_cursor_size) {
4e12cd94 2081 vga_invalidate_scanlines(&s->vga,
a5082316
FB		 2082 s->last_hw_cursor_y + s->last_hw_cursor_y_start,
2083 s->last_hw_cursor_y + s->last_hw_cursor_y_end);
2084 }
2085}
2086
2087static inline void cirrus_cursor_compute_yrange(CirrusVGAState *s)
2088{
2089 const uint8_t *src;
2090 uint32_t content;
2091 int y, y_min, y_max;
2092
4e12cd94
AK		 2093 src = s->vga.vram_ptr + s->real_vram_size - 16 * 1024;
2094 if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) {
2095 src += (s->vga.sr[0x13] & 0x3c) * 256;
a5082316
FB		 2096 y_min = 64;
2097 y_max = -1;
2098 for(y = 0; y < 64; y++) {
2099 content = ((uint32_t *)src)[0] |
2100 ((uint32_t *)src)[1] |
2101 ((uint32_t *)src)[2] |
2102 ((uint32_t *)src)[3];
2103 if (content) {
2104 if (y < y_min)
2105 y_min = y;
2106 if (y > y_max)
2107 y_max = y;
2108 }
2109 src += 16;
2110 }
2111 } else {
4e12cd94 2112 src += (s->vga.sr[0x13] & 0x3f) * 256;
a5082316
FB		 2113 y_min = 32;
2114 y_max = -1;
2115 for(y = 0; y < 32; y++) {
2116 content = ((uint32_t *)src)[0] |
2117 ((uint32_t *)(src + 128))[0];
2118 if (content) {
2119 if (y < y_min)
2120 y_min = y;
2121 if (y > y_max)
2122 y_max = y;
2123 }
2124 src += 4;
2125 }
2126 }
2127 if (y_min > y_max) {
2128 s->last_hw_cursor_y_start = 0;
2129 s->last_hw_cursor_y_end = 0;
2130 } else {
2131 s->last_hw_cursor_y_start = y_min;
2132 s->last_hw_cursor_y_end = y_max + 1;
2133 }
2134}
2135
2136/* NOTE: we do not currently handle the cursor bitmap change, so we
2137 update the cursor only if it moves. */
a4a2f59c 2138static void cirrus_cursor_invalidate(VGACommonState *s1)
a5082316 2139{
4e12cd94 2140 CirrusVGAState *s = container_of(s1, CirrusVGAState, vga);
a5082316
FB		 2141 int size;
2142
4e12cd94 2143 if (!(s->vga.sr[0x12] & CIRRUS_CURSOR_SHOW)) {
a5082316
FB		 2144 size = 0;
2145 } else {
4e12cd94 2146 if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE)
a5082316
FB		 2147 size = 64;
2148 else
2149 size = 32;
2150 }
2151 /* invalidate last cursor and new cursor if any change */
2152 if (s->last_hw_cursor_size != size ||
2153 s->last_hw_cursor_x != s->hw_cursor_x ||
2154 s->last_hw_cursor_y != s->hw_cursor_y) {
2155
2156 invalidate_cursor1(s);
3b46e624 2157
a5082316
FB		 2158 s->last_hw_cursor_size = size;
2159 s->last_hw_cursor_x = s->hw_cursor_x;
2160 s->last_hw_cursor_y = s->hw_cursor_y;
2161 /* compute the real cursor min and max y */
2162 cirrus_cursor_compute_yrange(s);
2163 invalidate_cursor1(s);
2164 }
2165}
2166
94d7b483 2167#define DEPTH 8
83c9f4ca 2168#include "hw/cirrus_vga_template.h"
94d7b483
BS		 2169
2170#define DEPTH 16
83c9f4ca 2171#include "hw/cirrus_vga_template.h"
94d7b483
BS		 2172
2173#define DEPTH 32
83c9f4ca 2174#include "hw/cirrus_vga_template.h"
94d7b483 2175
a4a2f59c 2176static void cirrus_cursor_draw_line(VGACommonState *s1, uint8_t *d1, int scr_y)
a5082316 2177{
4e12cd94 2178 CirrusVGAState *s = container_of(s1, CirrusVGAState, vga);
a5082316
FB		 2179 int w, h, bpp, x1, x2, poffset;
2180 unsigned int color0, color1;
2181 const uint8_t *palette, *src;
2182 uint32_t content;
3b46e624 2183
4e12cd94 2184 if (!(s->vga.sr[0x12] & CIRRUS_CURSOR_SHOW))
a5082316
FB		 2185 return;
2186 /* fast test to see if the cursor intersects with the scan line */
4e12cd94 2187 if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) {
a5082316
FB		 2188 h = 64;
2189 } else {
2190 h = 32;
2191 }
2192 if (scr_y < s->hw_cursor_y ||
2193 scr_y >= (s->hw_cursor_y + h))
2194 return;
3b46e624 2195
4e12cd94
AK		 2196 src = s->vga.vram_ptr + s->real_vram_size - 16 * 1024;
2197 if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) {
2198 src += (s->vga.sr[0x13] & 0x3c) * 256;
a5082316
FB		 2199 src += (scr_y - s->hw_cursor_y) * 16;
2200 poffset = 8;
2201 content = ((uint32_t *)src)[0] |
2202 ((uint32_t *)src)[1] |
2203 ((uint32_t *)src)[2] |
2204 ((uint32_t *)src)[3];
2205 } else {
4e12cd94 2206 src += (s->vga.sr[0x13] & 0x3f) * 256;
a5082316
FB		 2207 src += (scr_y - s->hw_cursor_y) * 4;
2208 poffset = 128;
2209 content = ((uint32_t *)src)[0] |
2210 ((uint32_t *)(src + 128))[0];
2211 }
2212 /* if nothing to draw, no need to continue */
2213 if (!content)
2214 return;
2215 w = h;
2216
2217 x1 = s->hw_cursor_x;
4e12cd94 2218 if (x1 >= s->vga.last_scr_width)
a5082316
FB		 2219 return;
2220 x2 = s->hw_cursor_x + w;
4e12cd94
AK		 2221 if (x2 > s->vga.last_scr_width)
2222 x2 = s->vga.last_scr_width;
a5082316
FB		 2223 w = x2 - x1;
2224 palette = s->cirrus_hidden_palette;
4e12cd94
AK		 2225 color0 = s->vga.rgb_to_pixel(c6_to_8(palette[0x0 * 3]),
2226 c6_to_8(palette[0x0 * 3 + 1]),
2227 c6_to_8(palette[0x0 * 3 + 2]));
2228 color1 = s->vga.rgb_to_pixel(c6_to_8(palette[0xf * 3]),
2229 c6_to_8(palette[0xf * 3 + 1]),
2230 c6_to_8(palette[0xf * 3 + 2]));
2231 bpp = ((ds_get_bits_per_pixel(s->vga.ds) + 7) >> 3);
a5082316 2232 d1 += x1 * bpp;
4e12cd94 2233 switch(ds_get_bits_per_pixel(s->vga.ds)) {
a5082316
FB		 2234 default:
2235 break;
2236 case 8:
2237 vga_draw_cursor_line_8(d1, src, poffset, w, color0, color1, 0xff);
2238 break;
2239 case 15:
2240 vga_draw_cursor_line_16(d1, src, poffset, w, color0, color1, 0x7fff);
2241 break;
2242 case 16:
2243 vga_draw_cursor_line_16(d1, src, poffset, w, color0, color1, 0xffff);
2244 break;
2245 case 32:
2246 vga_draw_cursor_line_32(d1, src, poffset, w, color0, color1, 0xffffff);
2247 break;
2248 }
2249}
2250
e6e5ad80
FB		 2251/***************************************
2252 *
2253 * LFB memory access
2254 *
2255 ***************************************/
2256
a8170e5e 2257static uint64_t cirrus_linear_read(void *opaque, hwaddr addr,
899adf81 2258 unsigned size)
e6e5ad80 2259{
e05587e8 2260 CirrusVGAState *s = opaque;
e6e5ad80
FB		 2261 uint32_t ret;
2262
e6e5ad80
FB		 2263 addr &= s->cirrus_addr_mask;
2264
4e12cd94 2265 if (((s->vga.sr[0x17] & 0x44) == 0x44) &&
78e127ef 2266 ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) {
e6e5ad80
FB		 2267 /* memory-mapped I/O */
2268 ret = cirrus_mmio_blt_read(s, addr & 0xff);
2269 } else if (0) {
2270 /* XXX handle bitblt */
2271 ret = 0xff;
2272 } else {
2273 /* video memory */
4e12cd94 2274 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
e6e5ad80 2275 addr <<= 4;
4e12cd94 2276 } else if (s->vga.gr[0x0B] & 0x02) {
e6e5ad80
FB		 2277 addr <<= 3;
2278 }
2279 addr &= s->cirrus_addr_mask;
4e12cd94 2280 ret = *(s->vga.vram_ptr + addr);
e6e5ad80
FB		 2281 }
2282
2283 return ret;
2284}
2285
a8170e5e 2286static void cirrus_linear_write(void *opaque, hwaddr addr,
899adf81 2287 uint64_t val, unsigned size)
e6e5ad80 2288{
e05587e8 2289 CirrusVGAState *s = opaque;
e6e5ad80
FB		 2290 unsigned mode;
2291
2292 addr &= s->cirrus_addr_mask;
3b46e624 2293
4e12cd94 2294 if (((s->vga.sr[0x17] & 0x44) == 0x44) &&
78e127ef 2295 ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) {
e6e5ad80
FB		 2296 /* memory-mapped I/O */
2297 cirrus_mmio_blt_write(s, addr & 0xff, val);
2298 } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2299 /* bitblt */
2300 *s->cirrus_srcptr++ = (uint8_t) val;
a5082316 2301 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
e6e5ad80
FB		 2302 cirrus_bitblt_cputovideo_next(s);
2303 }
2304 } else {
2305 /* video memory */
4e12cd94 2306 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
e6e5ad80 2307 addr <<= 4;
4e12cd94 2308 } else if (s->vga.gr[0x0B] & 0x02) {
e6e5ad80
FB		 2309 addr <<= 3;
2310 }
2311 addr &= s->cirrus_addr_mask;
2312
4e12cd94
AK		 2313 mode = s->vga.gr[0x05] & 0x7;
2314 if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) {
2315 *(s->vga.vram_ptr + addr) = (uint8_t) val;
fd4aa979 2316 memory_region_set_dirty(&s->vga.vram, addr, 1);
e6e5ad80 2317 } else {
4e12cd94 2318 if ((s->vga.gr[0x0B] & 0x14) != 0x14) {
e6e5ad80
FB		 2319 cirrus_mem_writeb_mode4and5_8bpp(s, mode, addr, val);
2320 } else {
2321 cirrus_mem_writeb_mode4and5_16bpp(s, mode, addr, val);
2322 }
2323 }
2324 }
2325}
2326
a5082316
FB		 2327/***************************************
2328 *
2329 * system to screen memory access
2330 *
2331 ***************************************/
2332
2333
4e56f089 2334static uint64_t cirrus_linear_bitblt_read(void *opaque,
a8170e5e 2335 hwaddr addr,
4e56f089 2336 unsigned size)
a5082316 2337{
4e56f089 2338 CirrusVGAState *s = opaque;
a5082316
FB		 2339 uint32_t ret;
2340
2341 /* XXX handle bitblt */
4e56f089 2342 (void)s;
a5082316
FB		 2343 ret = 0xff;
2344 return ret;
2345}
2346
4e56f089 2347static void cirrus_linear_bitblt_write(void *opaque,
a8170e5e 2348 hwaddr addr,
4e56f089
AK		 2349 uint64_t val,
2350 unsigned size)
a5082316 2351{
e05587e8 2352 CirrusVGAState *s = opaque;
a5082316
FB		 2353
2354 if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2355 /* bitblt */
2356 *s->cirrus_srcptr++ = (uint8_t) val;
2357 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
2358 cirrus_bitblt_cputovideo_next(s);
2359 }
2360 }
2361}
2362
b1950430
AK		 2363static const MemoryRegionOps cirrus_linear_bitblt_io_ops = {
2364 .read = cirrus_linear_bitblt_read,
2365 .write = cirrus_linear_bitblt_write,
2366 .endianness = DEVICE_LITTLE_ENDIAN,
4e56f089
AK		 2367 .impl = {
2368 .min_access_size = 1,
2369 .max_access_size = 1,
2370 },
a5082316
FB		 2371};
2372
b1950430
AK		 2373static void map_linear_vram_bank(CirrusVGAState *s, unsigned bank)
2374{
7969d9ed
AK		 2375 MemoryRegion *mr = &s->cirrus_bank[bank];
2376 bool enabled = !(s->cirrus_srcptr != s->cirrus_srcptr_end)
4e12cd94
AK		 2377 && !((s->vga.sr[0x07] & 0x01) == 0)
2378 && !((s->vga.gr[0x0B] & 0x14) == 0x14)
7969d9ed
AK		 2379 && !(s->vga.gr[0x0B] & 0x02);
2380
2381 memory_region_set_enabled(mr, enabled);
2382 memory_region_set_alias_offset(mr, s->cirrus_bank_base[bank]);
b1950430 2383}
2bec46dc 2384
b1950430
AK		 2385static void map_linear_vram(CirrusVGAState *s)
2386{
4c08fd1e 2387 if (s->bustype == CIRRUS_BUSTYPE_PCI && !s->linear_vram) {
b1950430
AK		 2388 s->linear_vram = true;
2389 memory_region_add_subregion_overlap(&s->pci_bar, 0, &s->vga.vram, 1);
2390 }
2391 map_linear_vram_bank(s, 0);
2392 map_linear_vram_bank(s, 1);
2bec46dc
AL		 2393}
2394
2395static void unmap_linear_vram(CirrusVGAState *s)
2396{
4c08fd1e 2397 if (s->bustype == CIRRUS_BUSTYPE_PCI && s->linear_vram) {
b1950430
AK		 2398 s->linear_vram = false;
2399 memory_region_del_subregion(&s->pci_bar, &s->vga.vram);
4516e45f 2400 }
7969d9ed
AK		 2401 memory_region_set_enabled(&s->cirrus_bank[0], false);
2402 memory_region_set_enabled(&s->cirrus_bank[1], false);
2bec46dc
AL		 2403}
2404
8926b517
FB		 2405/* Compute the memory access functions */
2406static void cirrus_update_memory_access(CirrusVGAState *s)
2407{
2408 unsigned mode;
2409
64c048f4 2410 memory_region_transaction_begin();
4e12cd94 2411 if ((s->vga.sr[0x17] & 0x44) == 0x44) {
8926b517
FB		 2412 goto generic_io;
2413 } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2414 goto generic_io;
2415 } else {
4e12cd94 2416 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
8926b517 2417 goto generic_io;
4e12cd94 2418 } else if (s->vga.gr[0x0B] & 0x02) {
8926b517
FB		 2419 goto generic_io;
2420 }
3b46e624 2421
4e12cd94
AK		 2422 mode = s->vga.gr[0x05] & 0x7;
2423 if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) {
2bec46dc 2424 map_linear_vram(s);
8926b517
FB		 2425 } else {
2426 generic_io:
2bec46dc 2427 unmap_linear_vram(s);
8926b517
FB		 2428 }
2429 }
64c048f4 2430 memory_region_transaction_commit();
8926b517
FB		 2431}
2432
2433
e6e5ad80
FB		 2434/* I/O ports */
2435
c75e6d8e
JG		 2436static uint64_t cirrus_vga_ioport_read(void *opaque, hwaddr addr,
2437 unsigned size)
e6e5ad80 2438{
b6343073
JQ		 2439 CirrusVGAState *c = opaque;
2440 VGACommonState *s = &c->vga;
e6e5ad80
FB		 2441 int val, index;
2442
bd8f2f5d 2443 qemu_flush_coalesced_mmio_buffer();
c75e6d8e 2444 addr += 0x3b0;
bd8f2f5d 2445
b6343073 2446 if (vga_ioport_invalid(s, addr)) {
e6e5ad80
FB		 2447 val = 0xff;
2448 } else {
2449 switch (addr) {
2450 case 0x3c0:
b6343073
JQ		 2451 if (s->ar_flip_flop == 0) {
2452 val = s->ar_index;
e6e5ad80
FB		 2453 } else {
2454 val = 0;
2455 }
2456 break;
2457 case 0x3c1:
b6343073 2458 index = s->ar_index & 0x1f;
e6e5ad80 2459 if (index < 21)
b6343073 2460 val = s->ar[index];
e6e5ad80
FB		 2461 else
2462 val = 0;
2463 break;
2464 case 0x3c2:
b6343073 2465 val = s->st00;
e6e5ad80
FB		 2466 break;
2467 case 0x3c4:
b6343073 2468 val = s->sr_index;
e6e5ad80
FB		 2469 break;
2470 case 0x3c5:
8a82c322
JQ		 2471 val = cirrus_vga_read_sr(c);
2472 break;
e6e5ad80 2473#ifdef DEBUG_VGA_REG
b6343073 2474 printf("vga: read SR%x = 0x%02x\n", s->sr_index, val);
e6e5ad80
FB		 2475#endif
2476 break;
2477 case 0x3c6:
957c9db5 2478 val = cirrus_read_hidden_dac(c);
e6e5ad80
FB		 2479 break;
2480 case 0x3c7:
b6343073 2481 val = s->dac_state;
e6e5ad80 2482 break;
ae184e4a 2483 case 0x3c8:
b6343073
JQ		 2484 val = s->dac_write_index;
2485 c->cirrus_hidden_dac_lockindex = 0;
ae184e4a
FB		 2486 break;
2487 case 0x3c9:
5deaeee3
JQ		 2488 val = cirrus_vga_read_palette(c);
2489 break;
e6e5ad80 2490 case 0x3ca:
b6343073 2491 val = s->fcr;
e6e5ad80
FB		 2492 break;
2493 case 0x3cc:
b6343073 2494 val = s->msr;
e6e5ad80
FB		 2495 break;
2496 case 0x3ce:
b6343073 2497 val = s->gr_index;
e6e5ad80
FB		 2498 break;
2499 case 0x3cf:
f705db9d 2500 val = cirrus_vga_read_gr(c, s->gr_index);
e6e5ad80 2501#ifdef DEBUG_VGA_REG
b6343073 2502 printf("vga: read GR%x = 0x%02x\n", s->gr_index, val);
e6e5ad80
FB		 2503#endif
2504 break;
2505 case 0x3b4:
2506 case 0x3d4:
b6343073 2507 val = s->cr_index;
e6e5ad80
FB		 2508 break;
2509 case 0x3b5:
2510 case 0x3d5:
b863d514 2511 val = cirrus_vga_read_cr(c, s->cr_index);
e6e5ad80 2512#ifdef DEBUG_VGA_REG
b6343073 2513 printf("vga: read CR%x = 0x%02x\n", s->cr_index, val);
e6e5ad80
FB		 2514#endif
2515 break;
2516 case 0x3ba:
2517 case 0x3da:
2518 /* just toggle to fool polling */
b6343073
JQ		 2519 val = s->st01 = s->retrace(s);
2520 s->ar_flip_flop = 0;
e6e5ad80
FB		 2521 break;
2522 default:
2523 val = 0x00;
2524 break;
2525 }
2526 }
2527#if defined(DEBUG_VGA)
2528 printf("VGA: read addr=0x%04x data=0x%02x\n", addr, val);
2529#endif
2530 return val;
2531}
2532
c75e6d8e
JG		 2533static void cirrus_vga_ioport_write(void *opaque, hwaddr addr, uint64_t val,
2534 unsigned size)
e6e5ad80 2535{
b6343073
JQ		 2536 CirrusVGAState *c = opaque;
2537 VGACommonState *s = &c->vga;
e6e5ad80
FB		 2538 int index;
2539
bd8f2f5d 2540 qemu_flush_coalesced_mmio_buffer();
c75e6d8e 2541 addr += 0x3b0;
bd8f2f5d 2542
e6e5ad80 2543 /* check port range access depending on color/monochrome mode */
b6343073 2544 if (vga_ioport_invalid(s, addr)) {
e6e5ad80 2545 return;
25a18cbd 2546 }
e6e5ad80
FB		 2547#ifdef DEBUG_VGA
2548 printf("VGA: write addr=0x%04x data=0x%02x\n", addr, val);
2549#endif
2550
2551 switch (addr) {
2552 case 0x3c0:
b6343073 2553 if (s->ar_flip_flop == 0) {
e6e5ad80 2554 val &= 0x3f;
b6343073 2555 s->ar_index = val;
e6e5ad80 2556 } else {
b6343073 2557 index = s->ar_index & 0x1f;
e6e5ad80
FB		 2558 switch (index) {
2559 case 0x00 ... 0x0f:
b6343073 2560 s->ar[index] = val & 0x3f;
e6e5ad80
FB		 2561 break;
2562 case 0x10:
b6343073 2563 s->ar[index] = val & ~0x10;
e6e5ad80
FB		 2564 break;
2565 case 0x11:
b6343073 2566 s->ar[index] = val;
e6e5ad80
FB		 2567 break;
2568 case 0x12:
b6343073 2569 s->ar[index] = val & ~0xc0;
e6e5ad80
FB		 2570 break;
2571 case 0x13:
b6343073 2572 s->ar[index] = val & ~0xf0;
e6e5ad80
FB		 2573 break;
2574 case 0x14:
b6343073 2575 s->ar[index] = val & ~0xf0;
e6e5ad80
FB		 2576 break;
2577 default:
2578 break;
2579 }
2580 }
b6343073 2581 s->ar_flip_flop ^= 1;
e6e5ad80
FB		 2582 break;
2583 case 0x3c2:
b6343073
JQ		 2584 s->msr = val & ~0x10;
2585 s->update_retrace_info(s);
e6e5ad80
FB		 2586 break;
2587 case 0x3c4:
b6343073 2588 s->sr_index = val;
e6e5ad80
FB		 2589 break;
2590 case 0x3c5:
e6e5ad80 2591#ifdef DEBUG_VGA_REG
b6343073 2592 printf("vga: write SR%x = 0x%02x\n", s->sr_index, val);
e6e5ad80 2593#endif
31c63201
JQ		 2594 cirrus_vga_write_sr(c, val);
2595 break;
e6e5ad80
FB		 2596 break;
2597 case 0x3c6:
b6343073 2598 cirrus_write_hidden_dac(c, val);
e6e5ad80
FB		 2599 break;
2600 case 0x3c7:
b6343073
JQ		 2601 s->dac_read_index = val;
2602 s->dac_sub_index = 0;
2603 s->dac_state = 3;
e6e5ad80
FB		 2604 break;
2605 case 0x3c8:
b6343073
JQ		 2606 s->dac_write_index = val;
2607 s->dac_sub_index = 0;
2608 s->dac_state = 0;
e6e5ad80
FB		 2609 break;
2610 case 0x3c9:
86948bb1
JQ		 2611 cirrus_vga_write_palette(c, val);
2612 break;
e6e5ad80 2613 case 0x3ce:
b6343073 2614 s->gr_index = val;
e6e5ad80
FB		 2615 break;
2616 case 0x3cf:
e6e5ad80 2617#ifdef DEBUG_VGA_REG
b6343073 2618 printf("vga: write GR%x = 0x%02x\n", s->gr_index, val);
e6e5ad80 2619#endif
22286bc6 2620 cirrus_vga_write_gr(c, s->gr_index, val);
e6e5ad80
FB		 2621 break;
2622 case 0x3b4:
2623 case 0x3d4:
b6343073 2624 s->cr_index = val;
e6e5ad80
FB		 2625 break;
2626 case 0x3b5:
2627 case 0x3d5:
e6e5ad80 2628#ifdef DEBUG_VGA_REG
b6343073 2629 printf("vga: write CR%x = 0x%02x\n", s->cr_index, val);
e6e5ad80 2630#endif
4ec1ce04 2631 cirrus_vga_write_cr(c, val);
e6e5ad80
FB		 2632 break;
2633 case 0x3ba:
2634 case 0x3da:
b6343073 2635 s->fcr = val & 0x10;
e6e5ad80
FB		 2636 break;
2637 }
2638}
2639
e36f36e1
FB		 2640/***************************************
2641 *
2642 * memory-mapped I/O access
2643 *
2644 ***************************************/
2645
a8170e5e 2646static uint64_t cirrus_mmio_read(void *opaque, hwaddr addr,
1e04d4d6 2647 unsigned size)
e36f36e1 2648{
e05587e8 2649 CirrusVGAState *s = opaque;
e36f36e1 2650
e36f36e1
FB		 2651 if (addr >= 0x100) {
2652 return cirrus_mmio_blt_read(s, addr - 0x100);
2653 } else {
c75e6d8e 2654 return cirrus_vga_ioport_read(s, addr + 0x10, size);
e36f36e1
FB		 2655 }
2656}
2657
a8170e5e 2658static void cirrus_mmio_write(void *opaque, hwaddr addr,
1e04d4d6 2659 uint64_t val, unsigned size)
e36f36e1 2660{
e05587e8 2661 CirrusVGAState *s = opaque;
e36f36e1 2662
e36f36e1
FB		 2663 if (addr >= 0x100) {
2664 cirrus_mmio_blt_write(s, addr - 0x100, val);
2665 } else {
c75e6d8e 2666 cirrus_vga_ioport_write(s, addr + 0x10, val, size);
e36f36e1
FB		 2667 }
2668}
2669
b1950430
AK		 2670static const MemoryRegionOps cirrus_mmio_io_ops = {
2671 .read = cirrus_mmio_read,
2672 .write = cirrus_mmio_write,
2673 .endianness = DEVICE_LITTLE_ENDIAN,
1e04d4d6
AK		 2674 .impl = {
2675 .min_access_size = 1,
2676 .max_access_size = 1,
2677 },
e36f36e1
FB		 2678};
2679
2c6ab832
FB		 2680/* load/save state */
2681
e59fb374 2682static int cirrus_post_load(void *opaque, int version_id)
2c6ab832
FB		 2683{
2684 CirrusVGAState *s = opaque;
2685
4e12cd94
AK		 2686 s->vga.gr[0x00] = s->cirrus_shadow_gr0 & 0x0f;
2687 s->vga.gr[0x01] = s->cirrus_shadow_gr1 & 0x0f;
2c6ab832 2688
2bec46dc 2689 cirrus_update_memory_access(s);
2c6ab832 2690 /* force refresh */
4e12cd94 2691 s->vga.graphic_mode = -1;
2c6ab832
FB		 2692 cirrus_update_bank_ptr(s, 0);
2693 cirrus_update_bank_ptr(s, 1);
2694 return 0;
2695}
2696
7e72abc3
JQ		 2697static const VMStateDescription vmstate_cirrus_vga = {
2698 .name = "cirrus_vga",
2699 .version_id = 2,
2700 .minimum_version_id = 1,
2701 .minimum_version_id_old = 1,
2702 .post_load = cirrus_post_load,
2703 .fields = (VMStateField []) {
2704 VMSTATE_UINT32(vga.latch, CirrusVGAState),
2705 VMSTATE_UINT8(vga.sr_index, CirrusVGAState),
2706 VMSTATE_BUFFER(vga.sr, CirrusVGAState),
2707 VMSTATE_UINT8(vga.gr_index, CirrusVGAState),
2708 VMSTATE_UINT8(cirrus_shadow_gr0, CirrusVGAState),
2709 VMSTATE_UINT8(cirrus_shadow_gr1, CirrusVGAState),
2710 VMSTATE_BUFFER_START_MIDDLE(vga.gr, CirrusVGAState, 2),
2711 VMSTATE_UINT8(vga.ar_index, CirrusVGAState),
2712 VMSTATE_BUFFER(vga.ar, CirrusVGAState),
2713 VMSTATE_INT32(vga.ar_flip_flop, CirrusVGAState),
2714 VMSTATE_UINT8(vga.cr_index, CirrusVGAState),
2715 VMSTATE_BUFFER(vga.cr, CirrusVGAState),
2716 VMSTATE_UINT8(vga.msr, CirrusVGAState),
2717 VMSTATE_UINT8(vga.fcr, CirrusVGAState),
2718 VMSTATE_UINT8(vga.st00, CirrusVGAState),
2719 VMSTATE_UINT8(vga.st01, CirrusVGAState),
2720 VMSTATE_UINT8(vga.dac_state, CirrusVGAState),
2721 VMSTATE_UINT8(vga.dac_sub_index, CirrusVGAState),
2722 VMSTATE_UINT8(vga.dac_read_index, CirrusVGAState),
2723 VMSTATE_UINT8(vga.dac_write_index, CirrusVGAState),
2724 VMSTATE_BUFFER(vga.dac_cache, CirrusVGAState),
2725 VMSTATE_BUFFER(vga.palette, CirrusVGAState),
2726 VMSTATE_INT32(vga.bank_offset, CirrusVGAState),
2727 VMSTATE_UINT8(cirrus_hidden_dac_lockindex, CirrusVGAState),
2728 VMSTATE_UINT8(cirrus_hidden_dac_data, CirrusVGAState),
2729 VMSTATE_UINT32(hw_cursor_x, CirrusVGAState),
2730 VMSTATE_UINT32(hw_cursor_y, CirrusVGAState),
2731 /* XXX: we do not save the bitblt state - we assume we do not save
2732 the state when the blitter is active */
2733 VMSTATE_END_OF_LIST()
4f335feb 2734 }
7e72abc3 2735};
4f335feb 2736
7e72abc3
JQ		 2737static const VMStateDescription vmstate_pci_cirrus_vga = {
2738 .name = "cirrus_vga",
2739 .version_id = 2,
2740 .minimum_version_id = 2,
2741 .minimum_version_id_old = 2,
7e72abc3
JQ		 2742 .fields = (VMStateField []) {
2743 VMSTATE_PCI_DEVICE(dev, PCICirrusVGAState),
2744 VMSTATE_STRUCT(cirrus_vga, PCICirrusVGAState, 0,
2745 vmstate_cirrus_vga, CirrusVGAState),
2746 VMSTATE_END_OF_LIST()
2747 }
2748};
4f335feb 2749
e6e5ad80
FB		 2750/***************************************
2751 *
2752 * initialize
2753 *
2754 ***************************************/
2755
4abc796d 2756static void cirrus_reset(void *opaque)
e6e5ad80 2757{
4abc796d 2758 CirrusVGAState *s = opaque;
e6e5ad80 2759
03a3e7ba 2760 vga_common_reset(&s->vga);
ee50c6bc 2761 unmap_linear_vram(s);
4e12cd94 2762 s->vga.sr[0x06] = 0x0f;
4abc796d 2763 if (s->device_id == CIRRUS_ID_CLGD5446) {
78e127ef 2764 /* 4MB 64 bit memory config, always PCI */
4e12cd94
AK		 2765 s->vga.sr[0x1F] = 0x2d; // MemClock
2766 s->vga.gr[0x18] = 0x0f; // fastest memory configuration
2767 s->vga.sr[0x0f] = 0x98;
2768 s->vga.sr[0x17] = 0x20;
2769 s->vga.sr[0x15] = 0x04; /* memory size, 3=2MB, 4=4MB */
78e127ef 2770 } else {
4e12cd94
AK		 2771 s->vga.sr[0x1F] = 0x22; // MemClock
2772 s->vga.sr[0x0F] = CIRRUS_MEMSIZE_2M;
2773 s->vga.sr[0x17] = s->bustype;
2774 s->vga.sr[0x15] = 0x03; /* memory size, 3=2MB, 4=4MB */
78e127ef 2775 }
4e12cd94 2776 s->vga.cr[0x27] = s->device_id;
e6e5ad80
FB		 2777
2778 s->cirrus_hidden_dac_lockindex = 5;
2779 s->cirrus_hidden_dac_data = 0;
4abc796d
BS		 2780}
2781
b1950430
AK		 2782static const MemoryRegionOps cirrus_linear_io_ops = {
2783 .read = cirrus_linear_read,
2784 .write = cirrus_linear_write,
2785 .endianness = DEVICE_LITTLE_ENDIAN,
899adf81
AK		 2786 .impl = {
2787 .min_access_size = 1,
2788 .max_access_size = 1,
2789 },
b1950430
AK		 2790};
2791
c75e6d8e
JG		 2792static const MemoryRegionOps cirrus_vga_io_ops = {
2793 .read = cirrus_vga_ioport_read,
2794 .write = cirrus_vga_ioport_write,
2795 .endianness = DEVICE_LITTLE_ENDIAN,
2796 .impl = {
2797 .min_access_size = 1,
2798 .max_access_size = 1,
2799 },
2800};
2801
be20f9e9 2802static void cirrus_init_common(CirrusVGAState * s, int device_id, int is_pci,
c75e6d8e
JG		 2803 MemoryRegion *system_memory,
2804 MemoryRegion *system_io)
4abc796d
BS		 2805{
2806 int i;
2807 static int inited;
2808
2809 if (!inited) {
2810 inited = 1;
2811 for(i = 0;i < 256; i++)
2812 rop_to_index[i] = CIRRUS_ROP_NOP_INDEX; /* nop rop */
2813 rop_to_index[CIRRUS_ROP_0] = 0;
2814 rop_to_index[CIRRUS_ROP_SRC_AND_DST] = 1;
2815 rop_to_index[CIRRUS_ROP_NOP] = 2;
2816 rop_to_index[CIRRUS_ROP_SRC_AND_NOTDST] = 3;
2817 rop_to_index[CIRRUS_ROP_NOTDST] = 4;
2818 rop_to_index[CIRRUS_ROP_SRC] = 5;
2819 rop_to_index[CIRRUS_ROP_1] = 6;
2820 rop_to_index[CIRRUS_ROP_NOTSRC_AND_DST] = 7;
2821 rop_to_index[CIRRUS_ROP_SRC_XOR_DST] = 8;
2822 rop_to_index[CIRRUS_ROP_SRC_OR_DST] = 9;
2823 rop_to_index[CIRRUS_ROP_NOTSRC_OR_NOTDST] = 10;
2824 rop_to_index[CIRRUS_ROP_SRC_NOTXOR_DST] = 11;
2825 rop_to_index[CIRRUS_ROP_SRC_OR_NOTDST] = 12;
2826 rop_to_index[CIRRUS_ROP_NOTSRC] = 13;
2827 rop_to_index[CIRRUS_ROP_NOTSRC_OR_DST] = 14;
2828 rop_to_index[CIRRUS_ROP_NOTSRC_AND_NOTDST] = 15;
2829 s->device_id = device_id;
2830 if (is_pci)
2831 s->bustype = CIRRUS_BUSTYPE_PCI;
2832 else
2833 s->bustype = CIRRUS_BUSTYPE_ISA;
2834 }
2835
c75e6d8e
JG		 2836 /* Register ioport 0x3b0 - 0x3df */
2837 memory_region_init_io(&s->cirrus_vga_io, &cirrus_vga_io_ops, s,
2838 "cirrus-io", 0x30);
2839 memory_region_add_subregion(system_io, 0x3b0, &s->cirrus_vga_io);
4abc796d 2840
b1950430
AK		 2841 memory_region_init(&s->low_mem_container,
2842 "cirrus-lowmem-container",
2843 0x20000);
2844
2845 memory_region_init_io(&s->low_mem, &cirrus_vga_mem_ops, s,
2846 "cirrus-low-memory", 0x20000);
2847 memory_region_add_subregion(&s->low_mem_container, 0, &s->low_mem);
7969d9ed
AK		 2848 for (i = 0; i < 2; ++i) {
2849 static const char *names[] = { "vga.bank0", "vga.bank1" };
2850 MemoryRegion *bank = &s->cirrus_bank[i];
2851 memory_region_init_alias(bank, names[i], &s->vga.vram, 0, 0x8000);
2852 memory_region_set_enabled(bank, false);
2853 memory_region_add_subregion_overlap(&s->low_mem_container, i * 0x8000,
2854 bank, 1);
2855 }
be20f9e9 2856 memory_region_add_subregion_overlap(system_memory,
b1950430
AK		 2857 isa_mem_base + 0x000a0000,
2858 &s->low_mem_container,
2859 1);
2860 memory_region_set_coalescing(&s->low_mem);
2c6ab832 2861
fefe54e3 2862 /* I/O handler for LFB */
b1950430 2863 memory_region_init_io(&s->cirrus_linear_io, &cirrus_linear_io_ops, s,
19403a68
MT		 2864 "cirrus-linear-io", s->vga.vram_size_mb
2865 * 1024 * 1024);
bd8f2f5d 2866 memory_region_set_flush_coalesced(&s->cirrus_linear_io);
fefe54e3
AL		 2867
2868 /* I/O handler for LFB */
b1950430
AK		 2869 memory_region_init_io(&s->cirrus_linear_bitblt_io,
2870 &cirrus_linear_bitblt_io_ops,
2871 s,
2872 "cirrus-bitblt-mmio",
2873 0x400000);
bd8f2f5d 2874 memory_region_set_flush_coalesced(&s->cirrus_linear_bitblt_io);
fefe54e3
AL		 2875
2876 /* I/O handler for memory-mapped I/O */
b1950430
AK		 2877 memory_region_init_io(&s->cirrus_mmio_io, &cirrus_mmio_io_ops, s,
2878 "cirrus-mmio", CIRRUS_PNPMMIO_SIZE);
bd8f2f5d 2879 memory_region_set_flush_coalesced(&s->cirrus_mmio_io);
fefe54e3
AL		 2880
2881 s->real_vram_size =
2882 (s->device_id == CIRRUS_ID_CLGD5446) ? 4096 * 1024 : 2048 * 1024;
2883
4e12cd94 2884 /* XXX: s->vga.vram_size must be a power of two */
fefe54e3
AL		 2885 s->cirrus_addr_mask = s->real_vram_size - 1;
2886 s->linear_mmio_mask = s->real_vram_size - 256;
2887
4e12cd94
AK		 2888 s->vga.get_bpp = cirrus_get_bpp;
2889 s->vga.get_offsets = cirrus_get_offsets;
2890 s->vga.get_resolution = cirrus_get_resolution;
2891 s->vga.cursor_invalidate = cirrus_cursor_invalidate;
2892 s->vga.cursor_draw_line = cirrus_cursor_draw_line;
fefe54e3 2893
a08d4367 2894 qemu_register_reset(cirrus_reset, s);
e6e5ad80
FB		 2895}
2896
2897/***************************************
2898 *
2899 * ISA bus support
2900 *
2901 ***************************************/
2902
3d402831 2903static int vga_initfn(ISADevice *dev)
e6e5ad80 2904{
3d402831
BS		 2905 ISACirrusVGAState *d = DO_UPCAST(ISACirrusVGAState, dev, dev);
2906 VGACommonState *s = &d->cirrus_vga.vga;
2907
4a1e244e 2908 vga_common_init(s);
3d402831 2909 cirrus_init_common(&d->cirrus_vga, CIRRUS_ID_CLGD5430, 0,
c75e6d8e 2910 isa_address_space(dev), isa_address_space_io(dev));
3d402831
BS		 2911 s->ds = graphic_console_init(s->update, s->invalidate,
2912 s->screen_dump, s->text_update,
2913 s);
5245d57a 2914 rom_add_vga(VGABIOS_CIRRUS_FILENAME);
e6e5ad80 2915 /* XXX ISA-LFB support */
ad6d45fa 2916 /* FIXME not qdev yet */
3d402831
BS		 2917 return 0;
2918}
2919
19403a68
MT		 2920static Property isa_vga_cirrus_properties[] = {
2921 DEFINE_PROP_UINT32("vgamem_mb", struct ISACirrusVGAState,
2922 cirrus_vga.vga.vram_size_mb, 8),
2923 DEFINE_PROP_END_OF_LIST(),
2924};
2925
8f04ee08
AL		 2926static void isa_cirrus_vga_class_init(ObjectClass *klass, void *data)
2927{
2928 ISADeviceClass *k = ISA_DEVICE_CLASS(klass);
39bffca2 2929 DeviceClass *dc = DEVICE_CLASS(klass);
8f04ee08 2930
39bffca2
AL		 2931 dc->vmsd = &vmstate_cirrus_vga;
2932 k->init = vga_initfn;
19403a68 2933 dc->props = isa_vga_cirrus_properties;
8f04ee08
AL		 2934}
2935
8c43a6f0 2936static const TypeInfo isa_cirrus_vga_info = {
39bffca2
AL		 2937 .name = "isa-cirrus-vga",
2938 .parent = TYPE_ISA_DEVICE,
2939 .instance_size = sizeof(ISACirrusVGAState),
8f04ee08 2940 .class_init = isa_cirrus_vga_class_init,
3d402831
BS		 2941};
2942
e6e5ad80
FB		 2943/***************************************
2944 *
2945 * PCI bus support
2946 *
2947 ***************************************/
2948
81a322d4 2949static int pci_cirrus_vga_initfn(PCIDevice *dev)
a414c306
GH		 2950{
2951 PCICirrusVGAState *d = DO_UPCAST(PCICirrusVGAState, dev, dev);
2952 CirrusVGAState *s = &d->cirrus_vga;
40021f08
AL		 2953 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
2954 int16_t device_id = pc->device_id;
a414c306
GH		 2955
2956 /* setup VGA */
4a1e244e 2957 vga_common_init(&s->vga);
c75e6d8e
JG		 2958 cirrus_init_common(s, device_id, 1, pci_address_space(dev),
2959 pci_address_space_io(dev));
a414c306
GH		 2960 s->vga.ds = graphic_console_init(s->vga.update, s->vga.invalidate,
2961 s->vga.screen_dump, s->vga.text_update,
2962 &s->vga);
2963
2964 /* setup PCI */
a414c306 2965
b1950430
AK		 2966 memory_region_init(&s->pci_bar, "cirrus-pci-bar0", 0x2000000);
2967
2968 /* XXX: add byte swapping apertures */
2969 memory_region_add_subregion(&s->pci_bar, 0, &s->cirrus_linear_io);
2970 memory_region_add_subregion(&s->pci_bar, 0x1000000,
2971 &s->cirrus_linear_bitblt_io);
2972
a414c306
GH		 2973 /* setup memory space */
2974 /* memory #0 LFB */
2975 /* memory #1 memory-mapped I/O */
2976 /* XXX: s->vga.vram_size must be a power of two */
e824b2cc 2977 pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &s->pci_bar);
a414c306 2978 if (device_id == CIRRUS_ID_CLGD5446) {
e824b2cc 2979 pci_register_bar(&d->dev, 1, 0, &s->cirrus_mmio_io);
a414c306 2980 }
81a322d4 2981 return 0;
a414c306
GH		 2982}
2983
19403a68
MT		 2984static Property pci_vga_cirrus_properties[] = {
2985 DEFINE_PROP_UINT32("vgamem_mb", struct PCICirrusVGAState,
2986 cirrus_vga.vga.vram_size_mb, 8),
2987 DEFINE_PROP_END_OF_LIST(),
2988};
2989
40021f08
AL		 2990static void cirrus_vga_class_init(ObjectClass *klass, void *data)
2991{
39bffca2 2992 DeviceClass *dc = DEVICE_CLASS(klass);
40021f08
AL		 2993 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
2994
2995 k->no_hotplug = 1;
2996 k->init = pci_cirrus_vga_initfn;
2997 k->romfile = VGABIOS_CIRRUS_FILENAME;
2998 k->vendor_id = PCI_VENDOR_ID_CIRRUS;
2999 k->device_id = CIRRUS_ID_CLGD5446;
3000 k->class_id = PCI_CLASS_DISPLAY_VGA;
39bffca2
AL		 3001 dc->desc = "Cirrus CLGD 54xx VGA";
3002 dc->vmsd = &vmstate_pci_cirrus_vga;
19403a68 3003 dc->props = pci_vga_cirrus_properties;
40021f08
AL		 3004}
3005
8c43a6f0 3006static const TypeInfo cirrus_vga_info = {
39bffca2
AL		 3007 .name = "cirrus-vga",
3008 .parent = TYPE_PCI_DEVICE,
3009 .instance_size = sizeof(PCICirrusVGAState),
3010 .class_init = cirrus_vga_class_init,
a414c306 3011};
e6e5ad80 3012
83f7d43a 3013static void cirrus_vga_register_types(void)
a414c306 3014{
83f7d43a 3015 type_register_static(&isa_cirrus_vga_info);
39bffca2 3016 type_register_static(&cirrus_vga_info);
e6e5ad80 3017}
83f7d43a
AF		 3018
3019type_init(cirrus_vga_register_types)
Empty description
This page took 1.094147 seconds and 4 git commands to generate.