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Update ARM non-rt sigframe layout.
[qemu.git] / hw / cirrus_vga.c
CommitLineData
e6e5ad80 1/*
aeb3c85f 2 * QEMU Cirrus CLGD 54xx VGA Emulator.
5fafdf24 3 *
e6e5ad80 4 * Copyright (c) 2004 Fabrice Bellard
aeb3c85f 5 * Copyright (c) 2004 Makoto Suzuki (suzu)
5fafdf24 6 *
e6e5ad80
FB		 7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
aeb3c85f
FB		 25/*
26 * Reference: Finn Thogersons' VGADOC4b
27 * available at http://home.worldonline.dk/~finth/
28 */
87ecb68b
PB		 29#include "hw.h"
30#include "pc.h"
31#include "pci.h"
32#include "console.h"
e6e5ad80
FB		 33#include "vga_int.h"
34
a5082316
FB		 35/*
36 * TODO:
ad81218e 37 * - destination write mask support not complete (bits 5..7)
a5082316
FB		 38 * - optimize linear mappings
39 * - optimize bitblt functions
40 */
41
e36f36e1 42//#define DEBUG_CIRRUS
a21ae81d 43//#define DEBUG_BITBLT
e36f36e1 44
e6e5ad80
FB		 45/***************************************
46 *
47 * definitions
48 *
49 ***************************************/
50
51#define qemu_MIN(a,b) ((a) < (b) ? (a) : (b))
52
53// ID
54#define CIRRUS_ID_CLGD5422 (0x23<<2)
55#define CIRRUS_ID_CLGD5426 (0x24<<2)
56#define CIRRUS_ID_CLGD5424 (0x25<<2)
57#define CIRRUS_ID_CLGD5428 (0x26<<2)
58#define CIRRUS_ID_CLGD5430 (0x28<<2)
59#define CIRRUS_ID_CLGD5434 (0x2A<<2)
a21ae81d 60#define CIRRUS_ID_CLGD5436 (0x2B<<2)
e6e5ad80
FB		 61#define CIRRUS_ID_CLGD5446 (0x2E<<2)
62
63// sequencer 0x07
64#define CIRRUS_SR7_BPP_VGA 0x00
65#define CIRRUS_SR7_BPP_SVGA 0x01
66#define CIRRUS_SR7_BPP_MASK 0x0e
67#define CIRRUS_SR7_BPP_8 0x00
68#define CIRRUS_SR7_BPP_16_DOUBLEVCLK 0x02
69#define CIRRUS_SR7_BPP_24 0x04
70#define CIRRUS_SR7_BPP_16 0x06
71#define CIRRUS_SR7_BPP_32 0x08
72#define CIRRUS_SR7_ISAADDR_MASK 0xe0
73
74// sequencer 0x0f
75#define CIRRUS_MEMSIZE_512k 0x08
76#define CIRRUS_MEMSIZE_1M 0x10
77#define CIRRUS_MEMSIZE_2M 0x18
78#define CIRRUS_MEMFLAGS_BANKSWITCH 0x80 // bank switching is enabled.
79
80// sequencer 0x12
81#define CIRRUS_CURSOR_SHOW 0x01
82#define CIRRUS_CURSOR_HIDDENPEL 0x02
83#define CIRRUS_CURSOR_LARGE 0x04 // 64x64 if set, 32x32 if clear
84
85// sequencer 0x17
86#define CIRRUS_BUSTYPE_VLBFAST 0x10
87#define CIRRUS_BUSTYPE_PCI 0x20
88#define CIRRUS_BUSTYPE_VLBSLOW 0x30
89#define CIRRUS_BUSTYPE_ISA 0x38
90#define CIRRUS_MMIO_ENABLE 0x04
91#define CIRRUS_MMIO_USE_PCIADDR 0x40 // 0xb8000 if cleared.
92#define CIRRUS_MEMSIZEEXT_DOUBLE 0x80
93
94// control 0x0b
95#define CIRRUS_BANKING_DUAL 0x01
96#define CIRRUS_BANKING_GRANULARITY_16K 0x20 // set:16k, clear:4k
97
98// control 0x30
99#define CIRRUS_BLTMODE_BACKWARDS 0x01
100#define CIRRUS_BLTMODE_MEMSYSDEST 0x02
101#define CIRRUS_BLTMODE_MEMSYSSRC 0x04
102#define CIRRUS_BLTMODE_TRANSPARENTCOMP 0x08
103#define CIRRUS_BLTMODE_PATTERNCOPY 0x40
104#define CIRRUS_BLTMODE_COLOREXPAND 0x80
105#define CIRRUS_BLTMODE_PIXELWIDTHMASK 0x30
106#define CIRRUS_BLTMODE_PIXELWIDTH8 0x00
107#define CIRRUS_BLTMODE_PIXELWIDTH16 0x10
108#define CIRRUS_BLTMODE_PIXELWIDTH24 0x20
109#define CIRRUS_BLTMODE_PIXELWIDTH32 0x30
110
111// control 0x31
112#define CIRRUS_BLT_BUSY 0x01
113#define CIRRUS_BLT_START 0x02
114#define CIRRUS_BLT_RESET 0x04
115#define CIRRUS_BLT_FIFOUSED 0x10
a5082316 116#define CIRRUS_BLT_AUTOSTART 0x80
e6e5ad80
FB		 117
118// control 0x32
119#define CIRRUS_ROP_0 0x00
120#define CIRRUS_ROP_SRC_AND_DST 0x05
121#define CIRRUS_ROP_NOP 0x06
122#define CIRRUS_ROP_SRC_AND_NOTDST 0x09
123#define CIRRUS_ROP_NOTDST 0x0b
124#define CIRRUS_ROP_SRC 0x0d
125#define CIRRUS_ROP_1 0x0e
126#define CIRRUS_ROP_NOTSRC_AND_DST 0x50
127#define CIRRUS_ROP_SRC_XOR_DST 0x59
128#define CIRRUS_ROP_SRC_OR_DST 0x6d
129#define CIRRUS_ROP_NOTSRC_OR_NOTDST 0x90
130#define CIRRUS_ROP_SRC_NOTXOR_DST 0x95
131#define CIRRUS_ROP_SRC_OR_NOTDST 0xad
132#define CIRRUS_ROP_NOTSRC 0xd0
133#define CIRRUS_ROP_NOTSRC_OR_DST 0xd6
134#define CIRRUS_ROP_NOTSRC_AND_NOTDST 0xda
135
a5082316
FB		 136#define CIRRUS_ROP_NOP_INDEX 2
137#define CIRRUS_ROP_SRC_INDEX 5
138
a21ae81d 139// control 0x33
a5082316 140#define CIRRUS_BLTMODEEXT_SOLIDFILL 0x04
4c8732d7 141#define CIRRUS_BLTMODEEXT_COLOREXPINV 0x02
a5082316 142#define CIRRUS_BLTMODEEXT_DWORDGRANULARITY 0x01
a21ae81d 143
e6e5ad80
FB		 144// memory-mapped IO
145#define CIRRUS_MMIO_BLTBGCOLOR 0x00 // dword
146#define CIRRUS_MMIO_BLTFGCOLOR 0x04 // dword
147#define CIRRUS_MMIO_BLTWIDTH 0x08 // word
148#define CIRRUS_MMIO_BLTHEIGHT 0x0a // word
149#define CIRRUS_MMIO_BLTDESTPITCH 0x0c // word
150#define CIRRUS_MMIO_BLTSRCPITCH 0x0e // word
151#define CIRRUS_MMIO_BLTDESTADDR 0x10 // dword
152#define CIRRUS_MMIO_BLTSRCADDR 0x14 // dword
153#define CIRRUS_MMIO_BLTWRITEMASK 0x17 // byte
154#define CIRRUS_MMIO_BLTMODE 0x18 // byte
155#define CIRRUS_MMIO_BLTROP 0x1a // byte
156#define CIRRUS_MMIO_BLTMODEEXT 0x1b // byte
157#define CIRRUS_MMIO_BLTTRANSPARENTCOLOR 0x1c // word?
158#define CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK 0x20 // word?
159#define CIRRUS_MMIO_LINEARDRAW_START_X 0x24 // word
160#define CIRRUS_MMIO_LINEARDRAW_START_Y 0x26 // word
161#define CIRRUS_MMIO_LINEARDRAW_END_X 0x28 // word
162#define CIRRUS_MMIO_LINEARDRAW_END_Y 0x2a // word
163#define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_INC 0x2c // byte
164#define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ROLLOVER 0x2d // byte
165#define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_MASK 0x2e // byte
166#define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ACCUM 0x2f // byte
167#define CIRRUS_MMIO_BRESENHAM_K1 0x30 // word
168#define CIRRUS_MMIO_BRESENHAM_K3 0x32 // word
169#define CIRRUS_MMIO_BRESENHAM_ERROR 0x34 // word
170#define CIRRUS_MMIO_BRESENHAM_DELTA_MAJOR 0x36 // word
171#define CIRRUS_MMIO_BRESENHAM_DIRECTION 0x38 // byte
172#define CIRRUS_MMIO_LINEDRAW_MODE 0x39 // byte
173#define CIRRUS_MMIO_BLTSTATUS 0x40 // byte
174
175// PCI 0x00: vendor, 0x02: device
176#define PCI_VENDOR_CIRRUS 0x1013
e6e5ad80
FB		 177#define PCI_DEVICE_CLGD5462 0x00d0
178#define PCI_DEVICE_CLGD5465 0x00d6
a21ae81d 179
e6e5ad80
FB		 180// PCI 0x04: command(word), 0x06(word): status
181#define PCI_COMMAND_IOACCESS 0x0001
182#define PCI_COMMAND_MEMACCESS 0x0002
183#define PCI_COMMAND_BUSMASTER 0x0004
184#define PCI_COMMAND_SPECIALCYCLE 0x0008
185#define PCI_COMMAND_MEMWRITEINVALID 0x0010
186#define PCI_COMMAND_PALETTESNOOPING 0x0020
187#define PCI_COMMAND_PARITYDETECTION 0x0040
188#define PCI_COMMAND_ADDRESSDATASTEPPING 0x0080
189#define PCI_COMMAND_SERR 0x0100
190#define PCI_COMMAND_BACKTOBACKTRANS 0x0200
191// PCI 0x08, 0xff000000 (0x09-0x0b:class,0x08:rev)
192#define PCI_CLASS_BASE_DISPLAY 0x03
193// PCI 0x08, 0x00ff0000
194#define PCI_CLASS_SUB_VGA 0x00
195// PCI 0x0c, 0x00ff0000 (0x0c:cacheline,0x0d:latency,0x0e:headertype,0x0f:Built-in self test)
196#define PCI_CLASS_HEADERTYPE_00h 0x00
197// 0x10-0x3f (headertype 00h)
198// PCI 0x10,0x14,0x18,0x1c,0x20,0x24: base address mapping registers
199// 0x10: MEMBASE, 0x14: IOBASE(hard-coded in XFree86 3.x)
200#define PCI_MAP_MEM 0x0
201#define PCI_MAP_IO 0x1
202#define PCI_MAP_MEM_ADDR_MASK (~0xf)
203#define PCI_MAP_IO_ADDR_MASK (~0x3)
204#define PCI_MAP_MEMFLAGS_32BIT 0x0
205#define PCI_MAP_MEMFLAGS_32BIT_1M 0x1
206#define PCI_MAP_MEMFLAGS_64BIT 0x4
207#define PCI_MAP_MEMFLAGS_CACHEABLE 0x8
208// PCI 0x28: cardbus CIS pointer
209// PCI 0x2c: subsystem vendor id, 0x2e: subsystem id
210// PCI 0x30: expansion ROM base address
211#define PCI_ROMBIOS_ENABLED 0x1
212// PCI 0x34: 0xffffff00=reserved, 0x000000ff=capabilities pointer
213// PCI 0x38: reserved
214// PCI 0x3c: 0x3c=int-line, 0x3d=int-pin, 0x3e=min-gnt, 0x3f=maax-lat
215
a21ae81d 216#define CIRRUS_PNPMMIO_SIZE 0x1000
e6e5ad80
FB		 217
218
219/* I/O and memory hook */
220#define CIRRUS_HOOK_NOT_HANDLED 0
221#define CIRRUS_HOOK_HANDLED 1
222
b2eb849d
AJ		 223#define BLTUNSAFE(s) \
224 ( \
225 ( /* check dst is within bounds */ \
226 (s)->cirrus_blt_height * (s)->cirrus_blt_dstpitch \
227 + ((s)->cirrus_blt_dstaddr & (s)->cirrus_addr_mask) > \
228 (s)->vram_size \
229 ) || \
230 ( /* check src is within bounds */ \
231 (s)->cirrus_blt_height * (s)->cirrus_blt_srcpitch \
232 + ((s)->cirrus_blt_srcaddr & (s)->cirrus_addr_mask) > \
233 (s)->vram_size \
234 ) \
235 )
236
a5082316
FB		 237struct CirrusVGAState;
238typedef void (*cirrus_bitblt_rop_t) (struct CirrusVGAState *s,
239 uint8_t * dst, const uint8_t * src,
e6e5ad80
FB		 240 int dstpitch, int srcpitch,
241 int bltwidth, int bltheight);
a5082316
FB		 242typedef void (*cirrus_fill_t)(struct CirrusVGAState *s,
243 uint8_t *dst, int dst_pitch, int width, int height);
e6e5ad80
FB		 244
245typedef struct CirrusVGAState {
4e3e9d0b 246 VGA_STATE_COMMON
e6e5ad80
FB		 247
248 int cirrus_linear_io_addr;
a5082316 249 int cirrus_linear_bitblt_io_addr;
e6e5ad80
FB		 250 int cirrus_mmio_io_addr;
251 uint32_t cirrus_addr_mask;
78e127ef 252 uint32_t linear_mmio_mask;
e6e5ad80
FB		 253 uint8_t cirrus_shadow_gr0;
254 uint8_t cirrus_shadow_gr1;
255 uint8_t cirrus_hidden_dac_lockindex;
256 uint8_t cirrus_hidden_dac_data;
257 uint32_t cirrus_bank_base[2];
258 uint32_t cirrus_bank_limit[2];
259 uint8_t cirrus_hidden_palette[48];
a5082316
FB		 260 uint32_t hw_cursor_x;
261 uint32_t hw_cursor_y;
e6e5ad80
FB		 262 int cirrus_blt_pixelwidth;
263 int cirrus_blt_width;
264 int cirrus_blt_height;
265 int cirrus_blt_dstpitch;
266 int cirrus_blt_srcpitch;
a5082316
FB		 267 uint32_t cirrus_blt_fgcol;
268 uint32_t cirrus_blt_bgcol;
e6e5ad80
FB		 269 uint32_t cirrus_blt_dstaddr;
270 uint32_t cirrus_blt_srcaddr;
271 uint8_t cirrus_blt_mode;
a5082316 272 uint8_t cirrus_blt_modeext;
e6e5ad80 273 cirrus_bitblt_rop_t cirrus_rop;
a5082316 274#define CIRRUS_BLTBUFSIZE (2048 * 4) /* one line width */
e6e5ad80
FB		 275 uint8_t cirrus_bltbuf[CIRRUS_BLTBUFSIZE];
276 uint8_t *cirrus_srcptr;
277 uint8_t *cirrus_srcptr_end;
278 uint32_t cirrus_srccounter;
a5082316
FB		 279 /* hwcursor display state */
280 int last_hw_cursor_size;
281 int last_hw_cursor_x;
282 int last_hw_cursor_y;
283 int last_hw_cursor_y_start;
284 int last_hw_cursor_y_end;
78e127ef 285 int real_vram_size; /* XXX: suppress that */
8926b517 286 CPUWriteMemoryFunc **cirrus_linear_write;
e6e5ad80
FB		 287} CirrusVGAState;
288
289typedef struct PCICirrusVGAState {
290 PCIDevice dev;
291 CirrusVGAState cirrus_vga;
292} PCICirrusVGAState;
293
a5082316 294static uint8_t rop_to_index[256];
3b46e624 295
e6e5ad80
FB		 296/***************************************
297 *
298 * prototypes.
299 *
300 ***************************************/
301
302
8926b517
FB		 303static void cirrus_bitblt_reset(CirrusVGAState *s);
304static void cirrus_update_memory_access(CirrusVGAState *s);
e6e5ad80
FB		 305
306/***************************************
307 *
308 * raster operations
309 *
310 ***************************************/
311
a5082316
FB		 312static void cirrus_bitblt_rop_nop(CirrusVGAState *s,
313 uint8_t *dst,const uint8_t *src,
314 int dstpitch,int srcpitch,
315 int bltwidth,int bltheight)
316{
e6e5ad80
FB		 317}
318
a5082316
FB		 319static void cirrus_bitblt_fill_nop(CirrusVGAState *s,
320 uint8_t *dst,
321 int dstpitch, int bltwidth,int bltheight)
e6e5ad80 322{
a5082316 323}
e6e5ad80 324
a5082316
FB		 325#define ROP_NAME 0
326#define ROP_OP(d, s) d = 0
327#include "cirrus_vga_rop.h"
e6e5ad80 328
a5082316
FB		 329#define ROP_NAME src_and_dst
330#define ROP_OP(d, s) d = (s) & (d)
331#include "cirrus_vga_rop.h"
e6e5ad80 332
a5082316
FB		 333#define ROP_NAME src_and_notdst
334#define ROP_OP(d, s) d = (s) & (~(d))
335#include "cirrus_vga_rop.h"
e6e5ad80 336
a5082316
FB		 337#define ROP_NAME notdst
338#define ROP_OP(d, s) d = ~(d)
339#include "cirrus_vga_rop.h"
e6e5ad80 340
a5082316
FB		 341#define ROP_NAME src
342#define ROP_OP(d, s) d = s
343#include "cirrus_vga_rop.h"
e6e5ad80 344
a5082316 345#define ROP_NAME 1
4c8732d7 346#define ROP_OP(d, s) d = ~0
a5082316
FB		 347#include "cirrus_vga_rop.h"
348
349#define ROP_NAME notsrc_and_dst
350#define ROP_OP(d, s) d = (~(s)) & (d)
351#include "cirrus_vga_rop.h"
352
353#define ROP_NAME src_xor_dst
354#define ROP_OP(d, s) d = (s) ^ (d)
355#include "cirrus_vga_rop.h"
356
357#define ROP_NAME src_or_dst
358#define ROP_OP(d, s) d = (s) | (d)
359#include "cirrus_vga_rop.h"
360
361#define ROP_NAME notsrc_or_notdst
362#define ROP_OP(d, s) d = (~(s)) | (~(d))
363#include "cirrus_vga_rop.h"
364
365#define ROP_NAME src_notxor_dst
366#define ROP_OP(d, s) d = ~((s) ^ (d))
367#include "cirrus_vga_rop.h"
e6e5ad80 368
a5082316
FB		 369#define ROP_NAME src_or_notdst
370#define ROP_OP(d, s) d = (s) | (~(d))
371#include "cirrus_vga_rop.h"
372
373#define ROP_NAME notsrc
374#define ROP_OP(d, s) d = (~(s))
375#include "cirrus_vga_rop.h"
376
377#define ROP_NAME notsrc_or_dst
378#define ROP_OP(d, s) d = (~(s)) | (d)
379#include "cirrus_vga_rop.h"
380
381#define ROP_NAME notsrc_and_notdst
382#define ROP_OP(d, s) d = (~(s)) & (~(d))
383#include "cirrus_vga_rop.h"
384
385static const cirrus_bitblt_rop_t cirrus_fwd_rop[16] = {
386 cirrus_bitblt_rop_fwd_0,
387 cirrus_bitblt_rop_fwd_src_and_dst,
388 cirrus_bitblt_rop_nop,
389 cirrus_bitblt_rop_fwd_src_and_notdst,
390 cirrus_bitblt_rop_fwd_notdst,
391 cirrus_bitblt_rop_fwd_src,
392 cirrus_bitblt_rop_fwd_1,
393 cirrus_bitblt_rop_fwd_notsrc_and_dst,
394 cirrus_bitblt_rop_fwd_src_xor_dst,
395 cirrus_bitblt_rop_fwd_src_or_dst,
396 cirrus_bitblt_rop_fwd_notsrc_or_notdst,
397 cirrus_bitblt_rop_fwd_src_notxor_dst,
398 cirrus_bitblt_rop_fwd_src_or_notdst,
399 cirrus_bitblt_rop_fwd_notsrc,
400 cirrus_bitblt_rop_fwd_notsrc_or_dst,
401 cirrus_bitblt_rop_fwd_notsrc_and_notdst,
402};
403
404static const cirrus_bitblt_rop_t cirrus_bkwd_rop[16] = {
405 cirrus_bitblt_rop_bkwd_0,
406 cirrus_bitblt_rop_bkwd_src_and_dst,
407 cirrus_bitblt_rop_nop,
408 cirrus_bitblt_rop_bkwd_src_and_notdst,
409 cirrus_bitblt_rop_bkwd_notdst,
410 cirrus_bitblt_rop_bkwd_src,
411 cirrus_bitblt_rop_bkwd_1,
412 cirrus_bitblt_rop_bkwd_notsrc_and_dst,
413 cirrus_bitblt_rop_bkwd_src_xor_dst,
414 cirrus_bitblt_rop_bkwd_src_or_dst,
415 cirrus_bitblt_rop_bkwd_notsrc_or_notdst,
416 cirrus_bitblt_rop_bkwd_src_notxor_dst,
417 cirrus_bitblt_rop_bkwd_src_or_notdst,
418 cirrus_bitblt_rop_bkwd_notsrc,
419 cirrus_bitblt_rop_bkwd_notsrc_or_dst,
420 cirrus_bitblt_rop_bkwd_notsrc_and_notdst,
421};
96cf2df8
TS		 422
423#define TRANSP_ROP(name) {\
424 name ## _8,\
425 name ## _16,\
426 }
427#define TRANSP_NOP(func) {\
428 func,\
429 func,\
430 }
431
432static const cirrus_bitblt_rop_t cirrus_fwd_transp_rop[16][2] = {
433 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_0),
434 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_and_dst),
435 TRANSP_NOP(cirrus_bitblt_rop_nop),
436 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_and_notdst),
437 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notdst),
438 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src),
439 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_1),
440 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_and_dst),
441 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_xor_dst),
442 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_or_dst),
443 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_or_notdst),
444 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_notxor_dst),
445 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_or_notdst),
446 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc),
447 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_or_dst),
448 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_and_notdst),
449};
450
451static const cirrus_bitblt_rop_t cirrus_bkwd_transp_rop[16][2] = {
452 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_0),
453 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_and_dst),
454 TRANSP_NOP(cirrus_bitblt_rop_nop),
455 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_and_notdst),
456 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notdst),
457 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src),
458 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_1),
459 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_and_dst),
460 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_xor_dst),
461 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_or_dst),
462 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_or_notdst),
463 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_notxor_dst),
464 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_or_notdst),
465 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc),
466 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_or_dst),
467 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_and_notdst),
468};
469
a5082316
FB		 470#define ROP2(name) {\
471 name ## _8,\
472 name ## _16,\
473 name ## _24,\
474 name ## _32,\
475 }
476
477#define ROP_NOP2(func) {\
478 func,\
479 func,\
480 func,\
481 func,\
482 }
483
e69390ce
FB		 484static const cirrus_bitblt_rop_t cirrus_patternfill[16][4] = {
485 ROP2(cirrus_patternfill_0),
486 ROP2(cirrus_patternfill_src_and_dst),
487 ROP_NOP2(cirrus_bitblt_rop_nop),
488 ROP2(cirrus_patternfill_src_and_notdst),
489 ROP2(cirrus_patternfill_notdst),
490 ROP2(cirrus_patternfill_src),
491 ROP2(cirrus_patternfill_1),
492 ROP2(cirrus_patternfill_notsrc_and_dst),
493 ROP2(cirrus_patternfill_src_xor_dst),
494 ROP2(cirrus_patternfill_src_or_dst),
495 ROP2(cirrus_patternfill_notsrc_or_notdst),
496 ROP2(cirrus_patternfill_src_notxor_dst),
497 ROP2(cirrus_patternfill_src_or_notdst),
498 ROP2(cirrus_patternfill_notsrc),
499 ROP2(cirrus_patternfill_notsrc_or_dst),
500 ROP2(cirrus_patternfill_notsrc_and_notdst),
501};
502
a5082316
FB		 503static const cirrus_bitblt_rop_t cirrus_colorexpand_transp[16][4] = {
504 ROP2(cirrus_colorexpand_transp_0),
505 ROP2(cirrus_colorexpand_transp_src_and_dst),
506 ROP_NOP2(cirrus_bitblt_rop_nop),
507 ROP2(cirrus_colorexpand_transp_src_and_notdst),
508 ROP2(cirrus_colorexpand_transp_notdst),
509 ROP2(cirrus_colorexpand_transp_src),
510 ROP2(cirrus_colorexpand_transp_1),
511 ROP2(cirrus_colorexpand_transp_notsrc_and_dst),
512 ROP2(cirrus_colorexpand_transp_src_xor_dst),
513 ROP2(cirrus_colorexpand_transp_src_or_dst),
514 ROP2(cirrus_colorexpand_transp_notsrc_or_notdst),
515 ROP2(cirrus_colorexpand_transp_src_notxor_dst),
516 ROP2(cirrus_colorexpand_transp_src_or_notdst),
517 ROP2(cirrus_colorexpand_transp_notsrc),
518 ROP2(cirrus_colorexpand_transp_notsrc_or_dst),
519 ROP2(cirrus_colorexpand_transp_notsrc_and_notdst),
520};
521
522static const cirrus_bitblt_rop_t cirrus_colorexpand[16][4] = {
523 ROP2(cirrus_colorexpand_0),
524 ROP2(cirrus_colorexpand_src_and_dst),
525 ROP_NOP2(cirrus_bitblt_rop_nop),
526 ROP2(cirrus_colorexpand_src_and_notdst),
527 ROP2(cirrus_colorexpand_notdst),
528 ROP2(cirrus_colorexpand_src),
529 ROP2(cirrus_colorexpand_1),
530 ROP2(cirrus_colorexpand_notsrc_and_dst),
531 ROP2(cirrus_colorexpand_src_xor_dst),
532 ROP2(cirrus_colorexpand_src_or_dst),
533 ROP2(cirrus_colorexpand_notsrc_or_notdst),
534 ROP2(cirrus_colorexpand_src_notxor_dst),
535 ROP2(cirrus_colorexpand_src_or_notdst),
536 ROP2(cirrus_colorexpand_notsrc),
537 ROP2(cirrus_colorexpand_notsrc_or_dst),
538 ROP2(cirrus_colorexpand_notsrc_and_notdst),
539};
540
b30d4608
FB		 541static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern_transp[16][4] = {
542 ROP2(cirrus_colorexpand_pattern_transp_0),
543 ROP2(cirrus_colorexpand_pattern_transp_src_and_dst),
544 ROP_NOP2(cirrus_bitblt_rop_nop),
545 ROP2(cirrus_colorexpand_pattern_transp_src_and_notdst),
546 ROP2(cirrus_colorexpand_pattern_transp_notdst),
547 ROP2(cirrus_colorexpand_pattern_transp_src),
548 ROP2(cirrus_colorexpand_pattern_transp_1),
549 ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_dst),
550 ROP2(cirrus_colorexpand_pattern_transp_src_xor_dst),
551 ROP2(cirrus_colorexpand_pattern_transp_src_or_dst),
552 ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_notdst),
553 ROP2(cirrus_colorexpand_pattern_transp_src_notxor_dst),
554 ROP2(cirrus_colorexpand_pattern_transp_src_or_notdst),
555 ROP2(cirrus_colorexpand_pattern_transp_notsrc),
556 ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_dst),
557 ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_notdst),
558};
559
560static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern[16][4] = {
561 ROP2(cirrus_colorexpand_pattern_0),
562 ROP2(cirrus_colorexpand_pattern_src_and_dst),
563 ROP_NOP2(cirrus_bitblt_rop_nop),
564 ROP2(cirrus_colorexpand_pattern_src_and_notdst),
565 ROP2(cirrus_colorexpand_pattern_notdst),
566 ROP2(cirrus_colorexpand_pattern_src),
567 ROP2(cirrus_colorexpand_pattern_1),
568 ROP2(cirrus_colorexpand_pattern_notsrc_and_dst),
569 ROP2(cirrus_colorexpand_pattern_src_xor_dst),
570 ROP2(cirrus_colorexpand_pattern_src_or_dst),
571 ROP2(cirrus_colorexpand_pattern_notsrc_or_notdst),
572 ROP2(cirrus_colorexpand_pattern_src_notxor_dst),
573 ROP2(cirrus_colorexpand_pattern_src_or_notdst),
574 ROP2(cirrus_colorexpand_pattern_notsrc),
575 ROP2(cirrus_colorexpand_pattern_notsrc_or_dst),
576 ROP2(cirrus_colorexpand_pattern_notsrc_and_notdst),
577};
578
a5082316
FB		 579static const cirrus_fill_t cirrus_fill[16][4] = {
580 ROP2(cirrus_fill_0),
581 ROP2(cirrus_fill_src_and_dst),
582 ROP_NOP2(cirrus_bitblt_fill_nop),
583 ROP2(cirrus_fill_src_and_notdst),
584 ROP2(cirrus_fill_notdst),
585 ROP2(cirrus_fill_src),
586 ROP2(cirrus_fill_1),
587 ROP2(cirrus_fill_notsrc_and_dst),
588 ROP2(cirrus_fill_src_xor_dst),
589 ROP2(cirrus_fill_src_or_dst),
590 ROP2(cirrus_fill_notsrc_or_notdst),
591 ROP2(cirrus_fill_src_notxor_dst),
592 ROP2(cirrus_fill_src_or_notdst),
593 ROP2(cirrus_fill_notsrc),
594 ROP2(cirrus_fill_notsrc_or_dst),
595 ROP2(cirrus_fill_notsrc_and_notdst),
596};
597
598static inline void cirrus_bitblt_fgcol(CirrusVGAState *s)
e6e5ad80 599{
a5082316
FB		 600 unsigned int color;
601 switch (s->cirrus_blt_pixelwidth) {
602 case 1:
603 s->cirrus_blt_fgcol = s->cirrus_shadow_gr1;
604 break;
605 case 2:
606 color = s->cirrus_shadow_gr1 | (s->gr[0x11] << 8);
607 s->cirrus_blt_fgcol = le16_to_cpu(color);
608 break;
609 case 3:
5fafdf24 610 s->cirrus_blt_fgcol = s->cirrus_shadow_gr1 |
a5082316
FB		 611 (s->gr[0x11] << 8) | (s->gr[0x13] << 16);
612 break;
613 default:
614 case 4:
615 color = s->cirrus_shadow_gr1 | (s->gr[0x11] << 8) |
616 (s->gr[0x13] << 16) | (s->gr[0x15] << 24);
617 s->cirrus_blt_fgcol = le32_to_cpu(color);
618 break;
e6e5ad80
FB		 619 }
620}
621
a5082316 622static inline void cirrus_bitblt_bgcol(CirrusVGAState *s)
e6e5ad80 623{
a5082316 624 unsigned int color;
e6e5ad80
FB		 625 switch (s->cirrus_blt_pixelwidth) {
626 case 1:
a5082316
FB		 627 s->cirrus_blt_bgcol = s->cirrus_shadow_gr0;
628 break;
e6e5ad80 629 case 2:
a5082316
FB		 630 color = s->cirrus_shadow_gr0 | (s->gr[0x10] << 8);
631 s->cirrus_blt_bgcol = le16_to_cpu(color);
632 break;
e6e5ad80 633 case 3:
5fafdf24 634 s->cirrus_blt_bgcol = s->cirrus_shadow_gr0 |
a5082316
FB		 635 (s->gr[0x10] << 8) | (s->gr[0x12] << 16);
636 break;
e6e5ad80 637 default:
a5082316
FB		 638 case 4:
639 color = s->cirrus_shadow_gr0 | (s->gr[0x10] << 8) |
640 (s->gr[0x12] << 16) | (s->gr[0x14] << 24);
641 s->cirrus_blt_bgcol = le32_to_cpu(color);
642 break;
e6e5ad80
FB		 643 }
644}
645
646static void cirrus_invalidate_region(CirrusVGAState * s, int off_begin,
647 int off_pitch, int bytesperline,
648 int lines)
649{
650 int y;
651 int off_cur;
652 int off_cur_end;
653
654 for (y = 0; y < lines; y++) {
655 off_cur = off_begin;
b2eb849d 656 off_cur_end = (off_cur + bytesperline) & s->cirrus_addr_mask;
e6e5ad80
FB		 657 off_cur &= TARGET_PAGE_MASK;
658 while (off_cur < off_cur_end) {
659 cpu_physical_memory_set_dirty(s->vram_offset + off_cur);
660 off_cur += TARGET_PAGE_SIZE;
661 }
662 off_begin += off_pitch;
663 }
664}
665
e6e5ad80
FB		 666static int cirrus_bitblt_common_patterncopy(CirrusVGAState * s,
667 const uint8_t * src)
668{
e6e5ad80 669 uint8_t *dst;
e6e5ad80 670
b2eb849d
AJ		 671 dst = s->vram_ptr + (s->cirrus_blt_dstaddr & s->cirrus_addr_mask);
672
673 if (BLTUNSAFE(s))
674 return 0;
675
e69390ce 676 (*s->cirrus_rop) (s, dst, src,
5fafdf24 677 s->cirrus_blt_dstpitch, 0,
e69390ce 678 s->cirrus_blt_width, s->cirrus_blt_height);
e6e5ad80 679 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
e69390ce
FB		 680 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
681 s->cirrus_blt_height);
e6e5ad80
FB		 682 return 1;
683}
684
a21ae81d
FB		 685/* fill */
686
a5082316 687static int cirrus_bitblt_solidfill(CirrusVGAState *s, int blt_rop)
a21ae81d 688{
a5082316 689 cirrus_fill_t rop_func;
a21ae81d 690
b2eb849d
AJ		 691 if (BLTUNSAFE(s))
692 return 0;
a5082316 693 rop_func = cirrus_fill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
b2eb849d 694 rop_func(s, s->vram_ptr + (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
a5082316
FB		 695 s->cirrus_blt_dstpitch,
696 s->cirrus_blt_width, s->cirrus_blt_height);
a21ae81d
FB		 697 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
698 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
699 s->cirrus_blt_height);
700 cirrus_bitblt_reset(s);
701 return 1;
702}
703
e6e5ad80
FB		 704/***************************************
705 *
706 * bitblt (video-to-video)
707 *
708 ***************************************/
709
710static int cirrus_bitblt_videotovideo_patterncopy(CirrusVGAState * s)
711{
712 return cirrus_bitblt_common_patterncopy(s,
b2eb849d
AJ		 713 s->vram_ptr + ((s->cirrus_blt_srcaddr & ~7) &
714 s->cirrus_addr_mask));
e6e5ad80
FB		 715}
716
24236869 717static void cirrus_do_copy(CirrusVGAState *s, int dst, int src, int w, int h)
e6e5ad80 718{
24236869
FB		 719 int sx, sy;
720 int dx, dy;
721 int width, height;
722 int depth;
723 int notify = 0;
724
725 depth = s->get_bpp((VGAState *)s) / 8;
726 s->get_resolution((VGAState *)s, &width, &height);
727
728 /* extra x, y */
729 sx = (src % (width * depth)) / depth;
730 sy = (src / (width * depth));
731 dx = (dst % (width *depth)) / depth;
732 dy = (dst / (width * depth));
733
734 /* normalize width */
735 w /= depth;
736
737 /* if we're doing a backward copy, we have to adjust
738 our x/y to be the upper left corner (instead of the lower
739 right corner) */
740 if (s->cirrus_blt_dstpitch < 0) {
741 sx -= (s->cirrus_blt_width / depth) - 1;
742 dx -= (s->cirrus_blt_width / depth) - 1;
743 sy -= s->cirrus_blt_height - 1;
744 dy -= s->cirrus_blt_height - 1;
745 }
746
747 /* are we in the visible portion of memory? */
748 if (sx >= 0 && sy >= 0 && dx >= 0 && dy >= 0 &&
749 (sx + w) <= width && (sy + h) <= height &&
750 (dx + w) <= width && (dy + h) <= height) {
751 notify = 1;
752 }
753
754 /* make to sure only copy if it's a plain copy ROP */
755 if (*s->cirrus_rop != cirrus_bitblt_rop_fwd_src &&
756 *s->cirrus_rop != cirrus_bitblt_rop_bkwd_src)
757 notify = 0;
758
759 /* we have to flush all pending changes so that the copy
760 is generated at the appropriate moment in time */
761 if (notify)
762 vga_hw_update();
763
b2eb849d
AJ		 764 (*s->cirrus_rop) (s, s->vram_ptr +
765 (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
766 s->vram_ptr +
767 (s->cirrus_blt_srcaddr & s->cirrus_addr_mask),
e6e5ad80
FB		 768 s->cirrus_blt_dstpitch, s->cirrus_blt_srcpitch,
769 s->cirrus_blt_width, s->cirrus_blt_height);
24236869
FB		 770
771 if (notify)
772 s->ds->dpy_copy(s->ds,
773 sx, sy, dx, dy,
774 s->cirrus_blt_width / depth,
775 s->cirrus_blt_height);
776
777 /* we don't have to notify the display that this portion has
778 changed since dpy_copy implies this */
779
780 if (!notify)
781 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
782 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
783 s->cirrus_blt_height);
784}
785
786static int cirrus_bitblt_videotovideo_copy(CirrusVGAState * s)
787{
788 if (s->ds->dpy_copy) {
789 cirrus_do_copy(s, s->cirrus_blt_dstaddr - s->start_addr,
790 s->cirrus_blt_srcaddr - s->start_addr,
791 s->cirrus_blt_width, s->cirrus_blt_height);
792 } else {
b2eb849d
AJ		 793
794 if (BLTUNSAFE(s))
795 return 0;
796
797 (*s->cirrus_rop) (s, s->vram_ptr +
798 (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
799 s->vram_ptr +
800 (s->cirrus_blt_srcaddr & s->cirrus_addr_mask),
24236869
FB		 801 s->cirrus_blt_dstpitch, s->cirrus_blt_srcpitch,
802 s->cirrus_blt_width, s->cirrus_blt_height);
803
804 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
805 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
806 s->cirrus_blt_height);
807 }
808
e6e5ad80
FB		 809 return 1;
810}
811
812/***************************************
813 *
814 * bitblt (cpu-to-video)
815 *
816 ***************************************/
817
e6e5ad80
FB		 818static void cirrus_bitblt_cputovideo_next(CirrusVGAState * s)
819{
820 int copy_count;
a5082316 821 uint8_t *end_ptr;
3b46e624 822
e6e5ad80 823 if (s->cirrus_srccounter > 0) {
a5082316
FB		 824 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
825 cirrus_bitblt_common_patterncopy(s, s->cirrus_bltbuf);
826 the_end:
827 s->cirrus_srccounter = 0;
828 cirrus_bitblt_reset(s);
829 } else {
830 /* at least one scan line */
831 do {
b2eb849d
AJ		 832 (*s->cirrus_rop)(s, s->vram_ptr +
833 (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
834 s->cirrus_bltbuf, 0, 0, s->cirrus_blt_width, 1);
a5082316
FB		 835 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr, 0,
836 s->cirrus_blt_width, 1);
837 s->cirrus_blt_dstaddr += s->cirrus_blt_dstpitch;
838 s->cirrus_srccounter -= s->cirrus_blt_srcpitch;
839 if (s->cirrus_srccounter <= 0)
840 goto the_end;
841 /* more bytes than needed can be transfered because of
842 word alignment, so we keep them for the next line */
843 /* XXX: keep alignment to speed up transfer */
844 end_ptr = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
845 copy_count = s->cirrus_srcptr_end - end_ptr;
846 memmove(s->cirrus_bltbuf, end_ptr, copy_count);
847 s->cirrus_srcptr = s->cirrus_bltbuf + copy_count;
848 s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
849 } while (s->cirrus_srcptr >= s->cirrus_srcptr_end);
850 }
e6e5ad80
FB		 851 }
852}
853
854/***************************************
855 *
856 * bitblt wrapper
857 *
858 ***************************************/
859
860static void cirrus_bitblt_reset(CirrusVGAState * s)
861{
862 s->gr[0x31] &=
863 ~(CIRRUS_BLT_START | CIRRUS_BLT_BUSY | CIRRUS_BLT_FIFOUSED);
864 s->cirrus_srcptr = &s->cirrus_bltbuf[0];
865 s->cirrus_srcptr_end = &s->cirrus_bltbuf[0];
866 s->cirrus_srccounter = 0;
8926b517 867 cirrus_update_memory_access(s);
e6e5ad80
FB		 868}
869
870static int cirrus_bitblt_cputovideo(CirrusVGAState * s)
871{
a5082316
FB		 872 int w;
873
e6e5ad80
FB		 874 s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_MEMSYSSRC;
875 s->cirrus_srcptr = &s->cirrus_bltbuf[0];
876 s->cirrus_srcptr_end = &s->cirrus_bltbuf[0];
877
878 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
879 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
a5082316 880 s->cirrus_blt_srcpitch = 8;
e6e5ad80 881 } else {
b30d4608 882 /* XXX: check for 24 bpp */
a5082316 883 s->cirrus_blt_srcpitch = 8 * 8 * s->cirrus_blt_pixelwidth;
e6e5ad80 884 }
a5082316 885 s->cirrus_srccounter = s->cirrus_blt_srcpitch;
e6e5ad80
FB		 886 } else {
887 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
a5082316 888 w = s->cirrus_blt_width / s->cirrus_blt_pixelwidth;
5fafdf24 889 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_DWORDGRANULARITY)
a5082316
FB		 890 s->cirrus_blt_srcpitch = ((w + 31) >> 5);
891 else
892 s->cirrus_blt_srcpitch = ((w + 7) >> 3);
e6e5ad80 893 } else {
c9c0eae8
FB		 894 /* always align input size to 32 bits */
895 s->cirrus_blt_srcpitch = (s->cirrus_blt_width + 3) & ~3;
e6e5ad80 896 }
a5082316 897 s->cirrus_srccounter = s->cirrus_blt_srcpitch * s->cirrus_blt_height;
e6e5ad80 898 }
a5082316
FB		 899 s->cirrus_srcptr = s->cirrus_bltbuf;
900 s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
8926b517 901 cirrus_update_memory_access(s);
e6e5ad80
FB		 902 return 1;
903}
904
905static int cirrus_bitblt_videotocpu(CirrusVGAState * s)
906{
907 /* XXX */
a5082316 908#ifdef DEBUG_BITBLT
e6e5ad80
FB		 909 printf("cirrus: bitblt (video to cpu) is not implemented yet\n");
910#endif
911 return 0;
912}
913
914static int cirrus_bitblt_videotovideo(CirrusVGAState * s)
915{
916 int ret;
917
918 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
919 ret = cirrus_bitblt_videotovideo_patterncopy(s);
920 } else {
921 ret = cirrus_bitblt_videotovideo_copy(s);
922 }
e6e5ad80
FB		 923 if (ret)
924 cirrus_bitblt_reset(s);
925 return ret;
926}
927
928static void cirrus_bitblt_start(CirrusVGAState * s)
929{
930 uint8_t blt_rop;
931
a5082316
FB		 932 s->gr[0x31] |= CIRRUS_BLT_BUSY;
933
e6e5ad80
FB		 934 s->cirrus_blt_width = (s->gr[0x20] | (s->gr[0x21] << 8)) + 1;
935 s->cirrus_blt_height = (s->gr[0x22] | (s->gr[0x23] << 8)) + 1;
936 s->cirrus_blt_dstpitch = (s->gr[0x24] | (s->gr[0x25] << 8));
937 s->cirrus_blt_srcpitch = (s->gr[0x26] | (s->gr[0x27] << 8));
938 s->cirrus_blt_dstaddr =
939 (s->gr[0x28] | (s->gr[0x29] << 8) | (s->gr[0x2a] << 16));
940 s->cirrus_blt_srcaddr =
941 (s->gr[0x2c] | (s->gr[0x2d] << 8) | (s->gr[0x2e] << 16));
942 s->cirrus_blt_mode = s->gr[0x30];
a5082316 943 s->cirrus_blt_modeext = s->gr[0x33];
e6e5ad80
FB		 944 blt_rop = s->gr[0x32];
945
a21ae81d 946#ifdef DEBUG_BITBLT
0b74ed78 947 printf("rop=0x%02x mode=0x%02x modeext=0x%02x w=%d h=%d dpitch=%d spitch=%d daddr=0x%08x saddr=0x%08x writemask=0x%02x\n",
5fafdf24 948 blt_rop,
a21ae81d 949 s->cirrus_blt_mode,
a5082316 950 s->cirrus_blt_modeext,
a21ae81d
FB		 951 s->cirrus_blt_width,
952 s->cirrus_blt_height,
953 s->cirrus_blt_dstpitch,
954 s->cirrus_blt_srcpitch,
955 s->cirrus_blt_dstaddr,
a5082316 956 s->cirrus_blt_srcaddr,
e3a4e4b6 957 s->gr[0x2f]);
a21ae81d
FB		 958#endif
959
e6e5ad80
FB		 960 switch (s->cirrus_blt_mode & CIRRUS_BLTMODE_PIXELWIDTHMASK) {
961 case CIRRUS_BLTMODE_PIXELWIDTH8:
962 s->cirrus_blt_pixelwidth = 1;
963 break;
964 case CIRRUS_BLTMODE_PIXELWIDTH16:
965 s->cirrus_blt_pixelwidth = 2;
966 break;
967 case CIRRUS_BLTMODE_PIXELWIDTH24:
968 s->cirrus_blt_pixelwidth = 3;
969 break;
970 case CIRRUS_BLTMODE_PIXELWIDTH32:
971 s->cirrus_blt_pixelwidth = 4;
972 break;
973 default:
a5082316 974#ifdef DEBUG_BITBLT
e6e5ad80
FB		 975 printf("cirrus: bitblt - pixel width is unknown\n");
976#endif
977 goto bitblt_ignore;
978 }
979 s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_PIXELWIDTHMASK;
980
981 if ((s->
982 cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSSRC |
983 CIRRUS_BLTMODE_MEMSYSDEST))
984 == (CIRRUS_BLTMODE_MEMSYSSRC | CIRRUS_BLTMODE_MEMSYSDEST)) {
a5082316 985#ifdef DEBUG_BITBLT
e6e5ad80
FB		 986 printf("cirrus: bitblt - memory-to-memory copy is requested\n");
987#endif
988 goto bitblt_ignore;
989 }
990
a5082316 991 if ((s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_SOLIDFILL) &&
5fafdf24 992 (s->cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSDEST |
a21ae81d 993 CIRRUS_BLTMODE_TRANSPARENTCOMP |
5fafdf24
TS		 994 CIRRUS_BLTMODE_PATTERNCOPY |
995 CIRRUS_BLTMODE_COLOREXPAND)) ==
a21ae81d 996 (CIRRUS_BLTMODE_PATTERNCOPY | CIRRUS_BLTMODE_COLOREXPAND)) {
a5082316
FB		 997 cirrus_bitblt_fgcol(s);
998 cirrus_bitblt_solidfill(s, blt_rop);
e6e5ad80 999 } else {
5fafdf24
TS		 1000 if ((s->cirrus_blt_mode & (CIRRUS_BLTMODE_COLOREXPAND |
1001 CIRRUS_BLTMODE_PATTERNCOPY)) ==
a5082316
FB		 1002 CIRRUS_BLTMODE_COLOREXPAND) {
1003
1004 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
b30d4608 1005 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV)
4c8732d7 1006 cirrus_bitblt_bgcol(s);
b30d4608 1007 else
4c8732d7 1008 cirrus_bitblt_fgcol(s);
b30d4608 1009 s->cirrus_rop = cirrus_colorexpand_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
a5082316
FB		 1010 } else {
1011 cirrus_bitblt_fgcol(s);
1012 cirrus_bitblt_bgcol(s);
1013 s->cirrus_rop = cirrus_colorexpand[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1014 }
e69390ce 1015 } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
b30d4608
FB		 1016 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
1017 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
1018 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV)
1019 cirrus_bitblt_bgcol(s);
1020 else
1021 cirrus_bitblt_fgcol(s);
1022 s->cirrus_rop = cirrus_colorexpand_pattern_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1023 } else {
1024 cirrus_bitblt_fgcol(s);
1025 cirrus_bitblt_bgcol(s);
1026 s->cirrus_rop = cirrus_colorexpand_pattern[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1027 }
1028 } else {
1029 s->cirrus_rop = cirrus_patternfill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1030 }
a21ae81d 1031 } else {
96cf2df8
TS		 1032 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
1033 if (s->cirrus_blt_pixelwidth > 2) {
1034 printf("src transparent without colorexpand must be 8bpp or 16bpp\n");
1035 goto bitblt_ignore;
1036 }
1037 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) {
1038 s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch;
1039 s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch;
1040 s->cirrus_rop = cirrus_bkwd_transp_rop[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1041 } else {
1042 s->cirrus_rop = cirrus_fwd_transp_rop[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1043 }
1044 } else {
1045 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) {
1046 s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch;
1047 s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch;
1048 s->cirrus_rop = cirrus_bkwd_rop[rop_to_index[blt_rop]];
1049 } else {
1050 s->cirrus_rop = cirrus_fwd_rop[rop_to_index[blt_rop]];
1051 }
1052 }
1053 }
a21ae81d
FB		 1054 // setup bitblt engine.
1055 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSSRC) {
1056 if (!cirrus_bitblt_cputovideo(s))
1057 goto bitblt_ignore;
1058 } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSDEST) {
1059 if (!cirrus_bitblt_videotocpu(s))
1060 goto bitblt_ignore;
1061 } else {
1062 if (!cirrus_bitblt_videotovideo(s))
1063 goto bitblt_ignore;
1064 }
e6e5ad80 1065 }
e6e5ad80
FB		 1066 return;
1067 bitblt_ignore:;
1068 cirrus_bitblt_reset(s);
1069}
1070
1071static void cirrus_write_bitblt(CirrusVGAState * s, unsigned reg_value)
1072{
1073 unsigned old_value;
1074
1075 old_value = s->gr[0x31];
1076 s->gr[0x31] = reg_value;
1077
1078 if (((old_value & CIRRUS_BLT_RESET) != 0) &&
1079 ((reg_value & CIRRUS_BLT_RESET) == 0)) {
1080 cirrus_bitblt_reset(s);
1081 } else if (((old_value & CIRRUS_BLT_START) == 0) &&
1082 ((reg_value & CIRRUS_BLT_START) != 0)) {
e6e5ad80
FB		 1083 cirrus_bitblt_start(s);
1084 }
1085}
1086
1087
1088/***************************************
1089 *
1090 * basic parameters
1091 *
1092 ***************************************/
1093
5fafdf24 1094static void cirrus_get_offsets(VGAState *s1,
83acc96b
FB		 1095 uint32_t *pline_offset,
1096 uint32_t *pstart_addr,
1097 uint32_t *pline_compare)
e6e5ad80
FB		 1098{
1099 CirrusVGAState * s = (CirrusVGAState *)s1;
83acc96b 1100 uint32_t start_addr, line_offset, line_compare;
e6e5ad80
FB		 1101
1102 line_offset = s->cr[0x13]
e36f36e1 1103 | ((s->cr[0x1b] & 0x10) << 4);
e6e5ad80
FB		 1104 line_offset <<= 3;
1105 *pline_offset = line_offset;
1106
1107 start_addr = (s->cr[0x0c] << 8)
1108 | s->cr[0x0d]
1109 | ((s->cr[0x1b] & 0x01) << 16)
1110 | ((s->cr[0x1b] & 0x0c) << 15)
1111 | ((s->cr[0x1d] & 0x80) << 12);
1112 *pstart_addr = start_addr;
83acc96b 1113
5fafdf24 1114 line_compare = s->cr[0x18] |
83acc96b
FB		 1115 ((s->cr[0x07] & 0x10) << 4) |
1116 ((s->cr[0x09] & 0x40) << 3);
1117 *pline_compare = line_compare;
e6e5ad80
FB		 1118}
1119
1120static uint32_t cirrus_get_bpp16_depth(CirrusVGAState * s)
1121{
1122 uint32_t ret = 16;
1123
1124 switch (s->cirrus_hidden_dac_data & 0xf) {
1125 case 0:
1126 ret = 15;
1127 break; /* Sierra HiColor */
1128 case 1:
1129 ret = 16;
1130 break; /* XGA HiColor */
1131 default:
1132#ifdef DEBUG_CIRRUS
1133 printf("cirrus: invalid DAC value %x in 16bpp\n",
1134 (s->cirrus_hidden_dac_data & 0xf));
1135#endif
1136 ret = 15; /* XXX */
1137 break;
1138 }
1139 return ret;
1140}
1141
1142static int cirrus_get_bpp(VGAState *s1)
1143{
1144 CirrusVGAState * s = (CirrusVGAState *)s1;
1145 uint32_t ret = 8;
1146
1147 if ((s->sr[0x07] & 0x01) != 0) {
1148 /* Cirrus SVGA */
1149 switch (s->sr[0x07] & CIRRUS_SR7_BPP_MASK) {
1150 case CIRRUS_SR7_BPP_8:
1151 ret = 8;
1152 break;
1153 case CIRRUS_SR7_BPP_16_DOUBLEVCLK:
1154 ret = cirrus_get_bpp16_depth(s);
1155 break;
1156 case CIRRUS_SR7_BPP_24:
1157 ret = 24;
1158 break;
1159 case CIRRUS_SR7_BPP_16:
1160 ret = cirrus_get_bpp16_depth(s);
1161 break;
1162 case CIRRUS_SR7_BPP_32:
1163 ret = 32;
1164 break;
1165 default:
1166#ifdef DEBUG_CIRRUS
1167 printf("cirrus: unknown bpp - sr7=%x\n", s->sr[0x7]);
1168#endif
1169 ret = 8;
1170 break;
1171 }
1172 } else {
1173 /* VGA */
aeb3c85f 1174 ret = 0;
e6e5ad80
FB		 1175 }
1176
1177 return ret;
1178}
1179
78e127ef
FB		 1180static void cirrus_get_resolution(VGAState *s, int *pwidth, int *pheight)
1181{
1182 int width, height;
3b46e624 1183
78e127ef 1184 width = (s->cr[0x01] + 1) * 8;
5fafdf24
TS		 1185 height = s->cr[0x12] |
1186 ((s->cr[0x07] & 0x02) << 7) |
78e127ef
FB		 1187 ((s->cr[0x07] & 0x40) << 3);
1188 height = (height + 1);
1189 /* interlace support */
1190 if (s->cr[0x1a] & 0x01)
1191 height = height * 2;
1192 *pwidth = width;
1193 *pheight = height;
1194}
1195
e6e5ad80
FB		 1196/***************************************
1197 *
1198 * bank memory
1199 *
1200 ***************************************/
1201
1202static void cirrus_update_bank_ptr(CirrusVGAState * s, unsigned bank_index)
1203{
1204 unsigned offset;
1205 unsigned limit;
1206
1207 if ((s->gr[0x0b] & 0x01) != 0) /* dual bank */
1208 offset = s->gr[0x09 + bank_index];
1209 else /* single bank */
1210 offset = s->gr[0x09];
1211
1212 if ((s->gr[0x0b] & 0x20) != 0)
1213 offset <<= 14;
1214 else
1215 offset <<= 12;
1216
e3a4e4b6 1217 if (s->real_vram_size <= offset)
e6e5ad80
FB		 1218 limit = 0;
1219 else
e3a4e4b6 1220 limit = s->real_vram_size - offset;
e6e5ad80
FB		 1221
1222 if (((s->gr[0x0b] & 0x01) == 0) && (bank_index != 0)) {
1223 if (limit > 0x8000) {
1224 offset += 0x8000;
1225 limit -= 0x8000;
1226 } else {
1227 limit = 0;
1228 }
1229 }
1230
1231 if (limit > 0) {
1232 s->cirrus_bank_base[bank_index] = offset;
1233 s->cirrus_bank_limit[bank_index] = limit;
1234 } else {
1235 s->cirrus_bank_base[bank_index] = 0;
1236 s->cirrus_bank_limit[bank_index] = 0;
1237 }
1238}
1239
1240/***************************************
1241 *
1242 * I/O access between 0x3c4-0x3c5
1243 *
1244 ***************************************/
1245
1246static int
1247cirrus_hook_read_sr(CirrusVGAState * s, unsigned reg_index, int *reg_value)
1248{
1249 switch (reg_index) {
1250 case 0x00: // Standard VGA
1251 case 0x01: // Standard VGA
1252 case 0x02: // Standard VGA
1253 case 0x03: // Standard VGA
1254 case 0x04: // Standard VGA
1255 return CIRRUS_HOOK_NOT_HANDLED;
1256 case 0x06: // Unlock Cirrus extensions
1257 *reg_value = s->sr[reg_index];
1258 break;
e6e5ad80
FB		 1259 case 0x10:
1260 case 0x30:
1261 case 0x50:
1262 case 0x70: // Graphics Cursor X
1263 case 0x90:
1264 case 0xb0:
1265 case 0xd0:
1266 case 0xf0: // Graphics Cursor X
aeb3c85f
FB		 1267 *reg_value = s->sr[0x10];
1268 break;
e6e5ad80
FB		 1269 case 0x11:
1270 case 0x31:
1271 case 0x51:
1272 case 0x71: // Graphics Cursor Y
1273 case 0x91:
1274 case 0xb1:
1275 case 0xd1:
a5082316 1276 case 0xf1: // Graphics Cursor Y
aeb3c85f
FB		 1277 *reg_value = s->sr[0x11];
1278 break;
1279 case 0x05: // ???
1280 case 0x07: // Extended Sequencer Mode
1281 case 0x08: // EEPROM Control
1282 case 0x09: // Scratch Register 0
1283 case 0x0a: // Scratch Register 1
1284 case 0x0b: // VCLK 0
1285 case 0x0c: // VCLK 1
1286 case 0x0d: // VCLK 2
1287 case 0x0e: // VCLK 3
1288 case 0x0f: // DRAM Control
e6e5ad80
FB		 1289 case 0x12: // Graphics Cursor Attribute
1290 case 0x13: // Graphics Cursor Pattern Address
1291 case 0x14: // Scratch Register 2
1292 case 0x15: // Scratch Register 3
1293 case 0x16: // Performance Tuning Register
1294 case 0x17: // Configuration Readback and Extended Control
1295 case 0x18: // Signature Generator Control
1296 case 0x19: // Signal Generator Result
1297 case 0x1a: // Signal Generator Result
1298 case 0x1b: // VCLK 0 Denominator & Post
1299 case 0x1c: // VCLK 1 Denominator & Post
1300 case 0x1d: // VCLK 2 Denominator & Post
1301 case 0x1e: // VCLK 3 Denominator & Post
1302 case 0x1f: // BIOS Write Enable and MCLK select
1303#ifdef DEBUG_CIRRUS
1304 printf("cirrus: handled inport sr_index %02x\n", reg_index);
1305#endif
1306 *reg_value = s->sr[reg_index];
1307 break;
1308 default:
1309#ifdef DEBUG_CIRRUS
1310 printf("cirrus: inport sr_index %02x\n", reg_index);
1311#endif
1312 *reg_value = 0xff;
1313 break;
1314 }
1315
1316 return CIRRUS_HOOK_HANDLED;
1317}
1318
1319static int
1320cirrus_hook_write_sr(CirrusVGAState * s, unsigned reg_index, int reg_value)
1321{
1322 switch (reg_index) {
1323 case 0x00: // Standard VGA
1324 case 0x01: // Standard VGA
1325 case 0x02: // Standard VGA
1326 case 0x03: // Standard VGA
1327 case 0x04: // Standard VGA
1328 return CIRRUS_HOOK_NOT_HANDLED;
1329 case 0x06: // Unlock Cirrus extensions
1330 reg_value &= 0x17;
1331 if (reg_value == 0x12) {
1332 s->sr[reg_index] = 0x12;
1333 } else {
1334 s->sr[reg_index] = 0x0f;
1335 }
1336 break;
1337 case 0x10:
1338 case 0x30:
1339 case 0x50:
1340 case 0x70: // Graphics Cursor X
1341 case 0x90:
1342 case 0xb0:
1343 case 0xd0:
1344 case 0xf0: // Graphics Cursor X
1345 s->sr[0x10] = reg_value;
a5082316 1346 s->hw_cursor_x = (reg_value << 3) | (reg_index >> 5);
e6e5ad80
FB		 1347 break;
1348 case 0x11:
1349 case 0x31:
1350 case 0x51:
1351 case 0x71: // Graphics Cursor Y
1352 case 0x91:
1353 case 0xb1:
1354 case 0xd1:
1355 case 0xf1: // Graphics Cursor Y
1356 s->sr[0x11] = reg_value;
a5082316 1357 s->hw_cursor_y = (reg_value << 3) | (reg_index >> 5);
e6e5ad80
FB		 1358 break;
1359 case 0x07: // Extended Sequencer Mode
1360 case 0x08: // EEPROM Control
1361 case 0x09: // Scratch Register 0
1362 case 0x0a: // Scratch Register 1
1363 case 0x0b: // VCLK 0
1364 case 0x0c: // VCLK 1
1365 case 0x0d: // VCLK 2
1366 case 0x0e: // VCLK 3
1367 case 0x0f: // DRAM Control
1368 case 0x12: // Graphics Cursor Attribute
1369 case 0x13: // Graphics Cursor Pattern Address
1370 case 0x14: // Scratch Register 2
1371 case 0x15: // Scratch Register 3
1372 case 0x16: // Performance Tuning Register
e6e5ad80
FB		 1373 case 0x18: // Signature Generator Control
1374 case 0x19: // Signature Generator Result
1375 case 0x1a: // Signature Generator Result
1376 case 0x1b: // VCLK 0 Denominator & Post
1377 case 0x1c: // VCLK 1 Denominator & Post
1378 case 0x1d: // VCLK 2 Denominator & Post
1379 case 0x1e: // VCLK 3 Denominator & Post
1380 case 0x1f: // BIOS Write Enable and MCLK select
1381 s->sr[reg_index] = reg_value;
1382#ifdef DEBUG_CIRRUS
1383 printf("cirrus: handled outport sr_index %02x, sr_value %02x\n",
1384 reg_index, reg_value);
1385#endif
1386 break;
8926b517 1387 case 0x17: // Configuration Readback and Extended Control
e3a4e4b6 1388 s->sr[reg_index] = (s->sr[reg_index] & 0x38) | (reg_value & 0xc7);
8926b517
FB		 1389 cirrus_update_memory_access(s);
1390 break;
e6e5ad80
FB		 1391 default:
1392#ifdef DEBUG_CIRRUS
1393 printf("cirrus: outport sr_index %02x, sr_value %02x\n", reg_index,
1394 reg_value);
1395#endif
1396 break;
1397 }
1398
1399 return CIRRUS_HOOK_HANDLED;
1400}
1401
1402/***************************************
1403 *
1404 * I/O access at 0x3c6
1405 *
1406 ***************************************/
1407
1408static void cirrus_read_hidden_dac(CirrusVGAState * s, int *reg_value)
1409{
1410 *reg_value = 0xff;
a21ae81d
FB		 1411 if (++s->cirrus_hidden_dac_lockindex == 5) {
1412 *reg_value = s->cirrus_hidden_dac_data;
1413 s->cirrus_hidden_dac_lockindex = 0;
e6e5ad80
FB		 1414 }
1415}
1416
1417static void cirrus_write_hidden_dac(CirrusVGAState * s, int reg_value)
1418{
1419 if (s->cirrus_hidden_dac_lockindex == 4) {
1420 s->cirrus_hidden_dac_data = reg_value;
a21ae81d 1421#if defined(DEBUG_CIRRUS)
e6e5ad80
FB		 1422 printf("cirrus: outport hidden DAC, value %02x\n", reg_value);
1423#endif
1424 }
1425 s->cirrus_hidden_dac_lockindex = 0;
1426}
1427
1428/***************************************
1429 *
1430 * I/O access at 0x3c9
1431 *
1432 ***************************************/
1433
1434static int cirrus_hook_read_palette(CirrusVGAState * s, int *reg_value)
1435{
1436 if (!(s->sr[0x12] & CIRRUS_CURSOR_HIDDENPEL))
1437 return CIRRUS_HOOK_NOT_HANDLED;
a5082316
FB		 1438 *reg_value =
1439 s->cirrus_hidden_palette[(s->dac_read_index & 0x0f) * 3 +
1440 s->dac_sub_index];
e6e5ad80
FB		 1441 if (++s->dac_sub_index == 3) {
1442 s->dac_sub_index = 0;
1443 s->dac_read_index++;
1444 }
1445 return CIRRUS_HOOK_HANDLED;
1446}
1447
1448static int cirrus_hook_write_palette(CirrusVGAState * s, int reg_value)
1449{
1450 if (!(s->sr[0x12] & CIRRUS_CURSOR_HIDDENPEL))
1451 return CIRRUS_HOOK_NOT_HANDLED;
1452 s->dac_cache[s->dac_sub_index] = reg_value;
1453 if (++s->dac_sub_index == 3) {
a5082316
FB		 1454 memcpy(&s->cirrus_hidden_palette[(s->dac_write_index & 0x0f) * 3],
1455 s->dac_cache, 3);
1456 /* XXX update cursor */
e6e5ad80
FB		 1457 s->dac_sub_index = 0;
1458 s->dac_write_index++;
1459 }
1460 return CIRRUS_HOOK_HANDLED;
1461}
1462
1463/***************************************
1464 *
1465 * I/O access between 0x3ce-0x3cf
1466 *
1467 ***************************************/
1468
1469static int
1470cirrus_hook_read_gr(CirrusVGAState * s, unsigned reg_index, int *reg_value)
1471{
1472 switch (reg_index) {
aeb3c85f
FB		 1473 case 0x00: // Standard VGA, BGCOLOR 0x000000ff
1474 *reg_value = s->cirrus_shadow_gr0;
1475 return CIRRUS_HOOK_HANDLED;
1476 case 0x01: // Standard VGA, FGCOLOR 0x000000ff
1477 *reg_value = s->cirrus_shadow_gr1;
1478 return CIRRUS_HOOK_HANDLED;
e6e5ad80
FB		 1479 case 0x02: // Standard VGA
1480 case 0x03: // Standard VGA
1481 case 0x04: // Standard VGA
1482 case 0x06: // Standard VGA
1483 case 0x07: // Standard VGA
1484 case 0x08: // Standard VGA
1485 return CIRRUS_HOOK_NOT_HANDLED;
1486 case 0x05: // Standard VGA, Cirrus extended mode
1487 default:
1488 break;
1489 }
1490
1491 if (reg_index < 0x3a) {
1492 *reg_value = s->gr[reg_index];
1493 } else {
1494#ifdef DEBUG_CIRRUS
1495 printf("cirrus: inport gr_index %02x\n", reg_index);
1496#endif
1497 *reg_value = 0xff;
1498 }
1499
1500 return CIRRUS_HOOK_HANDLED;
1501}
1502
1503static int
1504cirrus_hook_write_gr(CirrusVGAState * s, unsigned reg_index, int reg_value)
1505{
a5082316
FB		 1506#if defined(DEBUG_BITBLT) && 0
1507 printf("gr%02x: %02x\n", reg_index, reg_value);
1508#endif
e6e5ad80
FB		 1509 switch (reg_index) {
1510 case 0x00: // Standard VGA, BGCOLOR 0x000000ff
aeb3c85f 1511 s->cirrus_shadow_gr0 = reg_value;
e6e5ad80
FB		 1512 return CIRRUS_HOOK_NOT_HANDLED;
1513 case 0x01: // Standard VGA, FGCOLOR 0x000000ff
aeb3c85f 1514 s->cirrus_shadow_gr1 = reg_value;
e6e5ad80
FB		 1515 return CIRRUS_HOOK_NOT_HANDLED;
1516 case 0x02: // Standard VGA
1517 case 0x03: // Standard VGA
1518 case 0x04: // Standard VGA
1519 case 0x06: // Standard VGA
1520 case 0x07: // Standard VGA
1521 case 0x08: // Standard VGA
1522 return CIRRUS_HOOK_NOT_HANDLED;
1523 case 0x05: // Standard VGA, Cirrus extended mode
1524 s->gr[reg_index] = reg_value & 0x7f;
8926b517 1525 cirrus_update_memory_access(s);
e6e5ad80
FB		 1526 break;
1527 case 0x09: // bank offset #0
1528 case 0x0A: // bank offset #1
8926b517
FB		 1529 s->gr[reg_index] = reg_value;
1530 cirrus_update_bank_ptr(s, 0);
1531 cirrus_update_bank_ptr(s, 1);
1532 break;
e6e5ad80
FB		 1533 case 0x0B:
1534 s->gr[reg_index] = reg_value;
1535 cirrus_update_bank_ptr(s, 0);
1536 cirrus_update_bank_ptr(s, 1);
8926b517 1537 cirrus_update_memory_access(s);
e6e5ad80
FB		 1538 break;
1539 case 0x10: // BGCOLOR 0x0000ff00
1540 case 0x11: // FGCOLOR 0x0000ff00
1541 case 0x12: // BGCOLOR 0x00ff0000
1542 case 0x13: // FGCOLOR 0x00ff0000
1543 case 0x14: // BGCOLOR 0xff000000
1544 case 0x15: // FGCOLOR 0xff000000
1545 case 0x20: // BLT WIDTH 0x0000ff
1546 case 0x22: // BLT HEIGHT 0x0000ff
1547 case 0x24: // BLT DEST PITCH 0x0000ff
1548 case 0x26: // BLT SRC PITCH 0x0000ff
1549 case 0x28: // BLT DEST ADDR 0x0000ff
1550 case 0x29: // BLT DEST ADDR 0x00ff00
1551 case 0x2c: // BLT SRC ADDR 0x0000ff
1552 case 0x2d: // BLT SRC ADDR 0x00ff00
a5082316 1553 case 0x2f: // BLT WRITEMASK
e6e5ad80
FB		 1554 case 0x30: // BLT MODE
1555 case 0x32: // RASTER OP
a21ae81d 1556 case 0x33: // BLT MODEEXT
e6e5ad80
FB		 1557 case 0x34: // BLT TRANSPARENT COLOR 0x00ff
1558 case 0x35: // BLT TRANSPARENT COLOR 0xff00
1559 case 0x38: // BLT TRANSPARENT COLOR MASK 0x00ff
1560 case 0x39: // BLT TRANSPARENT COLOR MASK 0xff00
1561 s->gr[reg_index] = reg_value;
1562 break;
1563 case 0x21: // BLT WIDTH 0x001f00
1564 case 0x23: // BLT HEIGHT 0x001f00
1565 case 0x25: // BLT DEST PITCH 0x001f00
1566 case 0x27: // BLT SRC PITCH 0x001f00
1567 s->gr[reg_index] = reg_value & 0x1f;
1568 break;
1569 case 0x2a: // BLT DEST ADDR 0x3f0000
a5082316
FB		 1570 s->gr[reg_index] = reg_value & 0x3f;
1571 /* if auto start mode, starts bit blt now */
1572 if (s->gr[0x31] & CIRRUS_BLT_AUTOSTART) {
1573 cirrus_bitblt_start(s);
1574 }
1575 break;
e6e5ad80
FB		 1576 case 0x2e: // BLT SRC ADDR 0x3f0000
1577 s->gr[reg_index] = reg_value & 0x3f;
1578 break;
1579 case 0x31: // BLT STATUS/START
1580 cirrus_write_bitblt(s, reg_value);
1581 break;
1582 default:
1583#ifdef DEBUG_CIRRUS
1584 printf("cirrus: outport gr_index %02x, gr_value %02x\n", reg_index,
1585 reg_value);
1586#endif
1587 break;
1588 }
1589
1590 return CIRRUS_HOOK_HANDLED;
1591}
1592
1593/***************************************
1594 *
1595 * I/O access between 0x3d4-0x3d5
1596 *
1597 ***************************************/
1598
1599static int
1600cirrus_hook_read_cr(CirrusVGAState * s, unsigned reg_index, int *reg_value)
1601{
1602 switch (reg_index) {
1603 case 0x00: // Standard VGA
1604 case 0x01: // Standard VGA
1605 case 0x02: // Standard VGA
1606 case 0x03: // Standard VGA
1607 case 0x04: // Standard VGA
1608 case 0x05: // Standard VGA
1609 case 0x06: // Standard VGA
1610 case 0x07: // Standard VGA
1611 case 0x08: // Standard VGA
1612 case 0x09: // Standard VGA
1613 case 0x0a: // Standard VGA
1614 case 0x0b: // Standard VGA
1615 case 0x0c: // Standard VGA
1616 case 0x0d: // Standard VGA
1617 case 0x0e: // Standard VGA
1618 case 0x0f: // Standard VGA
1619 case 0x10: // Standard VGA
1620 case 0x11: // Standard VGA
1621 case 0x12: // Standard VGA
1622 case 0x13: // Standard VGA
1623 case 0x14: // Standard VGA
1624 case 0x15: // Standard VGA
1625 case 0x16: // Standard VGA
1626 case 0x17: // Standard VGA
1627 case 0x18: // Standard VGA
1628 return CIRRUS_HOOK_NOT_HANDLED;
1629 case 0x19: // Interlace End
1630 case 0x1a: // Miscellaneous Control
1631 case 0x1b: // Extended Display Control
1632 case 0x1c: // Sync Adjust and Genlock
1633 case 0x1d: // Overlay Extended Control
1634 case 0x22: // Graphics Data Latches Readback (R)
1635 case 0x24: // Attribute Controller Toggle Readback (R)
1636 case 0x25: // Part Status
1637 case 0x27: // Part ID (R)
1638 *reg_value = s->cr[reg_index];
1639 break;
1640 case 0x26: // Attribute Controller Index Readback (R)
1641 *reg_value = s->ar_index & 0x3f;
1642 break;
1643 default:
1644#ifdef DEBUG_CIRRUS
1645 printf("cirrus: inport cr_index %02x\n", reg_index);
1646 *reg_value = 0xff;
1647#endif
1648 break;
1649 }
1650
1651 return CIRRUS_HOOK_HANDLED;
1652}
1653
1654static int
1655cirrus_hook_write_cr(CirrusVGAState * s, unsigned reg_index, int reg_value)
1656{
1657 switch (reg_index) {
1658 case 0x00: // Standard VGA
1659 case 0x01: // Standard VGA
1660 case 0x02: // Standard VGA
1661 case 0x03: // Standard VGA
1662 case 0x04: // Standard VGA
1663 case 0x05: // Standard VGA
1664 case 0x06: // Standard VGA
1665 case 0x07: // Standard VGA
1666 case 0x08: // Standard VGA
1667 case 0x09: // Standard VGA
1668 case 0x0a: // Standard VGA
1669 case 0x0b: // Standard VGA
1670 case 0x0c: // Standard VGA
1671 case 0x0d: // Standard VGA
1672 case 0x0e: // Standard VGA
1673 case 0x0f: // Standard VGA
1674 case 0x10: // Standard VGA
1675 case 0x11: // Standard VGA
1676 case 0x12: // Standard VGA
1677 case 0x13: // Standard VGA
1678 case 0x14: // Standard VGA
1679 case 0x15: // Standard VGA
1680 case 0x16: // Standard VGA
1681 case 0x17: // Standard VGA
1682 case 0x18: // Standard VGA
1683 return CIRRUS_HOOK_NOT_HANDLED;
1684 case 0x19: // Interlace End
1685 case 0x1a: // Miscellaneous Control
1686 case 0x1b: // Extended Display Control
1687 case 0x1c: // Sync Adjust and Genlock
ae184e4a 1688 case 0x1d: // Overlay Extended Control
e6e5ad80
FB		 1689 s->cr[reg_index] = reg_value;
1690#ifdef DEBUG_CIRRUS
1691 printf("cirrus: handled outport cr_index %02x, cr_value %02x\n",
1692 reg_index, reg_value);
1693#endif
1694 break;
1695 case 0x22: // Graphics Data Latches Readback (R)
1696 case 0x24: // Attribute Controller Toggle Readback (R)
1697 case 0x26: // Attribute Controller Index Readback (R)
1698 case 0x27: // Part ID (R)
1699 break;
e6e5ad80
FB		 1700 case 0x25: // Part Status
1701 default:
1702#ifdef DEBUG_CIRRUS
1703 printf("cirrus: outport cr_index %02x, cr_value %02x\n", reg_index,
1704 reg_value);
1705#endif
1706 break;
1707 }
1708
1709 return CIRRUS_HOOK_HANDLED;
1710}
1711
1712/***************************************
1713 *
1714 * memory-mapped I/O (bitblt)
1715 *
1716 ***************************************/
1717
1718static uint8_t cirrus_mmio_blt_read(CirrusVGAState * s, unsigned address)
1719{
1720 int value = 0xff;
1721
1722 switch (address) {
1723 case (CIRRUS_MMIO_BLTBGCOLOR + 0):
1724 cirrus_hook_read_gr(s, 0x00, &value);
1725 break;
1726 case (CIRRUS_MMIO_BLTBGCOLOR + 1):
1727 cirrus_hook_read_gr(s, 0x10, &value);
1728 break;
1729 case (CIRRUS_MMIO_BLTBGCOLOR + 2):
1730 cirrus_hook_read_gr(s, 0x12, &value);
1731 break;
1732 case (CIRRUS_MMIO_BLTBGCOLOR + 3):
1733 cirrus_hook_read_gr(s, 0x14, &value);
1734 break;
1735 case (CIRRUS_MMIO_BLTFGCOLOR + 0):
1736 cirrus_hook_read_gr(s, 0x01, &value);
1737 break;
1738 case (CIRRUS_MMIO_BLTFGCOLOR + 1):
1739 cirrus_hook_read_gr(s, 0x11, &value);
1740 break;
1741 case (CIRRUS_MMIO_BLTFGCOLOR + 2):
1742 cirrus_hook_read_gr(s, 0x13, &value);
1743 break;
1744 case (CIRRUS_MMIO_BLTFGCOLOR + 3):
1745 cirrus_hook_read_gr(s, 0x15, &value);
1746 break;
1747 case (CIRRUS_MMIO_BLTWIDTH + 0):
1748 cirrus_hook_read_gr(s, 0x20, &value);
1749 break;
1750 case (CIRRUS_MMIO_BLTWIDTH + 1):
1751 cirrus_hook_read_gr(s, 0x21, &value);
1752 break;
1753 case (CIRRUS_MMIO_BLTHEIGHT + 0):
1754 cirrus_hook_read_gr(s, 0x22, &value);
1755 break;
1756 case (CIRRUS_MMIO_BLTHEIGHT + 1):
1757 cirrus_hook_read_gr(s, 0x23, &value);
1758 break;
1759 case (CIRRUS_MMIO_BLTDESTPITCH + 0):
1760 cirrus_hook_read_gr(s, 0x24, &value);
1761 break;
1762 case (CIRRUS_MMIO_BLTDESTPITCH + 1):
1763 cirrus_hook_read_gr(s, 0x25, &value);
1764 break;
1765 case (CIRRUS_MMIO_BLTSRCPITCH + 0):
1766 cirrus_hook_read_gr(s, 0x26, &value);
1767 break;
1768 case (CIRRUS_MMIO_BLTSRCPITCH + 1):
1769 cirrus_hook_read_gr(s, 0x27, &value);
1770 break;
1771 case (CIRRUS_MMIO_BLTDESTADDR + 0):
1772 cirrus_hook_read_gr(s, 0x28, &value);
1773 break;
1774 case (CIRRUS_MMIO_BLTDESTADDR + 1):
1775 cirrus_hook_read_gr(s, 0x29, &value);
1776 break;
1777 case (CIRRUS_MMIO_BLTDESTADDR + 2):
1778 cirrus_hook_read_gr(s, 0x2a, &value);
1779 break;
1780 case (CIRRUS_MMIO_BLTSRCADDR + 0):
1781 cirrus_hook_read_gr(s, 0x2c, &value);
1782 break;
1783 case (CIRRUS_MMIO_BLTSRCADDR + 1):
1784 cirrus_hook_read_gr(s, 0x2d, &value);
1785 break;
1786 case (CIRRUS_MMIO_BLTSRCADDR + 2):
1787 cirrus_hook_read_gr(s, 0x2e, &value);
1788 break;
1789 case CIRRUS_MMIO_BLTWRITEMASK:
1790 cirrus_hook_read_gr(s, 0x2f, &value);
1791 break;
1792 case CIRRUS_MMIO_BLTMODE:
1793 cirrus_hook_read_gr(s, 0x30, &value);
1794 break;
1795 case CIRRUS_MMIO_BLTROP:
1796 cirrus_hook_read_gr(s, 0x32, &value);
1797 break;
a21ae81d
FB		 1798 case CIRRUS_MMIO_BLTMODEEXT:
1799 cirrus_hook_read_gr(s, 0x33, &value);
1800 break;
e6e5ad80
FB		 1801 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0):
1802 cirrus_hook_read_gr(s, 0x34, &value);
1803 break;
1804 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1):
1805 cirrus_hook_read_gr(s, 0x35, &value);
1806 break;
1807 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0):
1808 cirrus_hook_read_gr(s, 0x38, &value);
1809 break;
1810 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1):
1811 cirrus_hook_read_gr(s, 0x39, &value);
1812 break;
1813 case CIRRUS_MMIO_BLTSTATUS:
1814 cirrus_hook_read_gr(s, 0x31, &value);
1815 break;
1816 default:
1817#ifdef DEBUG_CIRRUS
1818 printf("cirrus: mmio read - address 0x%04x\n", address);
1819#endif
1820 break;
1821 }
1822
1823 return (uint8_t) value;
1824}
1825
1826static void cirrus_mmio_blt_write(CirrusVGAState * s, unsigned address,
1827 uint8_t value)
1828{
1829 switch (address) {
1830 case (CIRRUS_MMIO_BLTBGCOLOR + 0):
1831 cirrus_hook_write_gr(s, 0x00, value);
1832 break;
1833 case (CIRRUS_MMIO_BLTBGCOLOR + 1):
1834 cirrus_hook_write_gr(s, 0x10, value);
1835 break;
1836 case (CIRRUS_MMIO_BLTBGCOLOR + 2):
1837 cirrus_hook_write_gr(s, 0x12, value);
1838 break;
1839 case (CIRRUS_MMIO_BLTBGCOLOR + 3):
1840 cirrus_hook_write_gr(s, 0x14, value);
1841 break;
1842 case (CIRRUS_MMIO_BLTFGCOLOR + 0):
1843 cirrus_hook_write_gr(s, 0x01, value);
1844 break;
1845 case (CIRRUS_MMIO_BLTFGCOLOR + 1):
1846 cirrus_hook_write_gr(s, 0x11, value);
1847 break;
1848 case (CIRRUS_MMIO_BLTFGCOLOR + 2):
1849 cirrus_hook_write_gr(s, 0x13, value);
1850 break;
1851 case (CIRRUS_MMIO_BLTFGCOLOR + 3):
1852 cirrus_hook_write_gr(s, 0x15, value);
1853 break;
1854 case (CIRRUS_MMIO_BLTWIDTH + 0):
1855 cirrus_hook_write_gr(s, 0x20, value);
1856 break;
1857 case (CIRRUS_MMIO_BLTWIDTH + 1):
1858 cirrus_hook_write_gr(s, 0x21, value);
1859 break;
1860 case (CIRRUS_MMIO_BLTHEIGHT + 0):
1861 cirrus_hook_write_gr(s, 0x22, value);
1862 break;
1863 case (CIRRUS_MMIO_BLTHEIGHT + 1):
1864 cirrus_hook_write_gr(s, 0x23, value);
1865 break;
1866 case (CIRRUS_MMIO_BLTDESTPITCH + 0):
1867 cirrus_hook_write_gr(s, 0x24, value);
1868 break;
1869 case (CIRRUS_MMIO_BLTDESTPITCH + 1):
1870 cirrus_hook_write_gr(s, 0x25, value);
1871 break;
1872 case (CIRRUS_MMIO_BLTSRCPITCH + 0):
1873 cirrus_hook_write_gr(s, 0x26, value);
1874 break;
1875 case (CIRRUS_MMIO_BLTSRCPITCH + 1):
1876 cirrus_hook_write_gr(s, 0x27, value);
1877 break;
1878 case (CIRRUS_MMIO_BLTDESTADDR + 0):
1879 cirrus_hook_write_gr(s, 0x28, value);
1880 break;
1881 case (CIRRUS_MMIO_BLTDESTADDR + 1):
1882 cirrus_hook_write_gr(s, 0x29, value);
1883 break;
1884 case (CIRRUS_MMIO_BLTDESTADDR + 2):
1885 cirrus_hook_write_gr(s, 0x2a, value);
1886 break;
1887 case (CIRRUS_MMIO_BLTDESTADDR + 3):
1888 /* ignored */
1889 break;
1890 case (CIRRUS_MMIO_BLTSRCADDR + 0):
1891 cirrus_hook_write_gr(s, 0x2c, value);
1892 break;
1893 case (CIRRUS_MMIO_BLTSRCADDR + 1):
1894 cirrus_hook_write_gr(s, 0x2d, value);
1895 break;
1896 case (CIRRUS_MMIO_BLTSRCADDR + 2):
1897 cirrus_hook_write_gr(s, 0x2e, value);
1898 break;
1899 case CIRRUS_MMIO_BLTWRITEMASK:
1900 cirrus_hook_write_gr(s, 0x2f, value);
1901 break;
1902 case CIRRUS_MMIO_BLTMODE:
1903 cirrus_hook_write_gr(s, 0x30, value);
1904 break;
1905 case CIRRUS_MMIO_BLTROP:
1906 cirrus_hook_write_gr(s, 0x32, value);
1907 break;
a21ae81d
FB		 1908 case CIRRUS_MMIO_BLTMODEEXT:
1909 cirrus_hook_write_gr(s, 0x33, value);
1910 break;
e6e5ad80
FB		 1911 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0):
1912 cirrus_hook_write_gr(s, 0x34, value);
1913 break;
1914 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1):
1915 cirrus_hook_write_gr(s, 0x35, value);
1916 break;
1917 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0):
1918 cirrus_hook_write_gr(s, 0x38, value);
1919 break;
1920 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1):
1921 cirrus_hook_write_gr(s, 0x39, value);
1922 break;
1923 case CIRRUS_MMIO_BLTSTATUS:
1924 cirrus_hook_write_gr(s, 0x31, value);
1925 break;
1926 default:
1927#ifdef DEBUG_CIRRUS
1928 printf("cirrus: mmio write - addr 0x%04x val 0x%02x (ignored)\n",
1929 address, value);
1930#endif
1931 break;
1932 }
1933}
1934
e6e5ad80
FB		 1935/***************************************
1936 *
1937 * write mode 4/5
1938 *
1939 * assume TARGET_PAGE_SIZE >= 16
1940 *
1941 ***************************************/
1942
1943static void cirrus_mem_writeb_mode4and5_8bpp(CirrusVGAState * s,
1944 unsigned mode,
1945 unsigned offset,
1946 uint32_t mem_value)
1947{
1948 int x;
1949 unsigned val = mem_value;
1950 uint8_t *dst;
1951
b2eb849d 1952 dst = s->vram_ptr + (offset &= s->cirrus_addr_mask);
e6e5ad80
FB		 1953 for (x = 0; x < 8; x++) {
1954 if (val & 0x80) {
0b74ed78 1955 *dst = s->cirrus_shadow_gr1;
e6e5ad80 1956 } else if (mode == 5) {
0b74ed78 1957 *dst = s->cirrus_shadow_gr0;
e6e5ad80
FB		 1958 }
1959 val <<= 1;
0b74ed78 1960 dst++;
e6e5ad80
FB		 1961 }
1962 cpu_physical_memory_set_dirty(s->vram_offset + offset);
1963 cpu_physical_memory_set_dirty(s->vram_offset + offset + 7);
1964}
1965
1966static void cirrus_mem_writeb_mode4and5_16bpp(CirrusVGAState * s,
1967 unsigned mode,
1968 unsigned offset,
1969 uint32_t mem_value)
1970{
1971 int x;
1972 unsigned val = mem_value;
1973 uint8_t *dst;
1974
b2eb849d 1975 dst = s->vram_ptr + (offset &= s->cirrus_addr_mask);
e6e5ad80
FB		 1976 for (x = 0; x < 8; x++) {
1977 if (val & 0x80) {
0b74ed78
FB		 1978 *dst = s->cirrus_shadow_gr1;
1979 *(dst + 1) = s->gr[0x11];
e6e5ad80 1980 } else if (mode == 5) {
0b74ed78
FB		 1981 *dst = s->cirrus_shadow_gr0;
1982 *(dst + 1) = s->gr[0x10];
e6e5ad80
FB		 1983 }
1984 val <<= 1;
0b74ed78 1985 dst += 2;
e6e5ad80
FB		 1986 }
1987 cpu_physical_memory_set_dirty(s->vram_offset + offset);
1988 cpu_physical_memory_set_dirty(s->vram_offset + offset + 15);
1989}
1990
1991/***************************************
1992 *
1993 * memory access between 0xa0000-0xbffff
1994 *
1995 ***************************************/
1996
1997static uint32_t cirrus_vga_mem_readb(void *opaque, target_phys_addr_t addr)
1998{
1999 CirrusVGAState *s = opaque;
2000 unsigned bank_index;
2001 unsigned bank_offset;
2002 uint32_t val;
2003
2004 if ((s->sr[0x07] & 0x01) == 0) {
2005 return vga_mem_readb(s, addr);
2006 }
2007
aeb3c85f
FB		 2008 addr &= 0x1ffff;
2009
e6e5ad80
FB		 2010 if (addr < 0x10000) {
2011 /* XXX handle bitblt */
2012 /* video memory */
2013 bank_index = addr >> 15;
2014 bank_offset = addr & 0x7fff;
2015 if (bank_offset < s->cirrus_bank_limit[bank_index]) {
2016 bank_offset += s->cirrus_bank_base[bank_index];
2017 if ((s->gr[0x0B] & 0x14) == 0x14) {
2018 bank_offset <<= 4;
2019 } else if (s->gr[0x0B] & 0x02) {
2020 bank_offset <<= 3;
2021 }
2022 bank_offset &= s->cirrus_addr_mask;
2023 val = *(s->vram_ptr + bank_offset);
2024 } else
2025 val = 0xff;
2026 } else if (addr >= 0x18000 && addr < 0x18100) {
2027 /* memory-mapped I/O */
2028 val = 0xff;
2029 if ((s->sr[0x17] & 0x44) == 0x04) {
2030 val = cirrus_mmio_blt_read(s, addr & 0xff);
2031 }
2032 } else {
2033 val = 0xff;
2034#ifdef DEBUG_CIRRUS
2035 printf("cirrus: mem_readb %06x\n", addr);
2036#endif
2037 }
2038 return val;
2039}
2040
2041static uint32_t cirrus_vga_mem_readw(void *opaque, target_phys_addr_t addr)
2042{
2043 uint32_t v;
2044#ifdef TARGET_WORDS_BIGENDIAN
2045 v = cirrus_vga_mem_readb(opaque, addr) << 8;
2046 v |= cirrus_vga_mem_readb(opaque, addr + 1);
2047#else
2048 v = cirrus_vga_mem_readb(opaque, addr);
2049 v |= cirrus_vga_mem_readb(opaque, addr + 1) << 8;
2050#endif
2051 return v;
2052}
2053
2054static uint32_t cirrus_vga_mem_readl(void *opaque, target_phys_addr_t addr)
2055{
2056 uint32_t v;
2057#ifdef TARGET_WORDS_BIGENDIAN
2058 v = cirrus_vga_mem_readb(opaque, addr) << 24;
2059 v |= cirrus_vga_mem_readb(opaque, addr + 1) << 16;
2060 v |= cirrus_vga_mem_readb(opaque, addr + 2) << 8;
2061 v |= cirrus_vga_mem_readb(opaque, addr + 3);
2062#else
2063 v = cirrus_vga_mem_readb(opaque, addr);
2064 v |= cirrus_vga_mem_readb(opaque, addr + 1) << 8;
2065 v |= cirrus_vga_mem_readb(opaque, addr + 2) << 16;
2066 v |= cirrus_vga_mem_readb(opaque, addr + 3) << 24;
2067#endif
2068 return v;
2069}
2070
5fafdf24 2071static void cirrus_vga_mem_writeb(void *opaque, target_phys_addr_t addr,
e6e5ad80
FB		 2072 uint32_t mem_value)
2073{
2074 CirrusVGAState *s = opaque;
2075 unsigned bank_index;
2076 unsigned bank_offset;
2077 unsigned mode;
2078
2079 if ((s->sr[0x07] & 0x01) == 0) {
2080 vga_mem_writeb(s, addr, mem_value);
2081 return;
2082 }
2083
aeb3c85f
FB		 2084 addr &= 0x1ffff;
2085
e6e5ad80
FB		 2086 if (addr < 0x10000) {
2087 if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2088 /* bitblt */
2089 *s->cirrus_srcptr++ = (uint8_t) mem_value;
a5082316 2090 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
e6e5ad80
FB		 2091 cirrus_bitblt_cputovideo_next(s);
2092 }
2093 } else {
2094 /* video memory */
2095 bank_index = addr >> 15;
2096 bank_offset = addr & 0x7fff;
2097 if (bank_offset < s->cirrus_bank_limit[bank_index]) {
2098 bank_offset += s->cirrus_bank_base[bank_index];
2099 if ((s->gr[0x0B] & 0x14) == 0x14) {
2100 bank_offset <<= 4;
2101 } else if (s->gr[0x0B] & 0x02) {
2102 bank_offset <<= 3;
2103 }
2104 bank_offset &= s->cirrus_addr_mask;
2105 mode = s->gr[0x05] & 0x7;
2106 if (mode < 4 || mode > 5 || ((s->gr[0x0B] & 0x4) == 0)) {
2107 *(s->vram_ptr + bank_offset) = mem_value;
2108 cpu_physical_memory_set_dirty(s->vram_offset +
2109 bank_offset);
2110 } else {
2111 if ((s->gr[0x0B] & 0x14) != 0x14) {
2112 cirrus_mem_writeb_mode4and5_8bpp(s, mode,
2113 bank_offset,
2114 mem_value);
2115 } else {
2116 cirrus_mem_writeb_mode4and5_16bpp(s, mode,
2117 bank_offset,
2118 mem_value);
2119 }
2120 }
2121 }
2122 }
2123 } else if (addr >= 0x18000 && addr < 0x18100) {
2124 /* memory-mapped I/O */
2125 if ((s->sr[0x17] & 0x44) == 0x04) {
2126 cirrus_mmio_blt_write(s, addr & 0xff, mem_value);
2127 }
2128 } else {
2129#ifdef DEBUG_CIRRUS
2130 printf("cirrus: mem_writeb %06x value %02x\n", addr, mem_value);
2131#endif
2132 }
2133}
2134
2135static void cirrus_vga_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
2136{
2137#ifdef TARGET_WORDS_BIGENDIAN
2138 cirrus_vga_mem_writeb(opaque, addr, (val >> 8) & 0xff);
2139 cirrus_vga_mem_writeb(opaque, addr + 1, val & 0xff);
2140#else
2141 cirrus_vga_mem_writeb(opaque, addr, val & 0xff);
2142 cirrus_vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2143#endif
2144}
2145
2146static void cirrus_vga_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
2147{
2148#ifdef TARGET_WORDS_BIGENDIAN
2149 cirrus_vga_mem_writeb(opaque, addr, (val >> 24) & 0xff);
2150 cirrus_vga_mem_writeb(opaque, addr + 1, (val >> 16) & 0xff);
2151 cirrus_vga_mem_writeb(opaque, addr + 2, (val >> 8) & 0xff);
2152 cirrus_vga_mem_writeb(opaque, addr + 3, val & 0xff);
2153#else
2154 cirrus_vga_mem_writeb(opaque, addr, val & 0xff);
2155 cirrus_vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2156 cirrus_vga_mem_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2157 cirrus_vga_mem_writeb(opaque, addr + 3, (val >> 24) & 0xff);
2158#endif
2159}
2160
2161static CPUReadMemoryFunc *cirrus_vga_mem_read[3] = {
2162 cirrus_vga_mem_readb,
2163 cirrus_vga_mem_readw,
2164 cirrus_vga_mem_readl,
2165};
2166
2167static CPUWriteMemoryFunc *cirrus_vga_mem_write[3] = {
2168 cirrus_vga_mem_writeb,
2169 cirrus_vga_mem_writew,
2170 cirrus_vga_mem_writel,
2171};
2172
a5082316
FB		 2173/***************************************
2174 *
2175 * hardware cursor
2176 *
2177 ***************************************/
2178
2179static inline void invalidate_cursor1(CirrusVGAState *s)
2180{
2181 if (s->last_hw_cursor_size) {
5fafdf24 2182 vga_invalidate_scanlines((VGAState *)s,
a5082316
FB		 2183 s->last_hw_cursor_y + s->last_hw_cursor_y_start,
2184 s->last_hw_cursor_y + s->last_hw_cursor_y_end);
2185 }
2186}
2187
2188static inline void cirrus_cursor_compute_yrange(CirrusVGAState *s)
2189{
2190 const uint8_t *src;
2191 uint32_t content;
2192 int y, y_min, y_max;
2193
78e127ef 2194 src = s->vram_ptr + s->real_vram_size - 16 * 1024;
a5082316
FB		 2195 if (s->sr[0x12] & CIRRUS_CURSOR_LARGE) {
2196 src += (s->sr[0x13] & 0x3c) * 256;
2197 y_min = 64;
2198 y_max = -1;
2199 for(y = 0; y < 64; y++) {
2200 content = ((uint32_t *)src)[0] |
2201 ((uint32_t *)src)[1] |
2202 ((uint32_t *)src)[2] |
2203 ((uint32_t *)src)[3];
2204 if (content) {
2205 if (y < y_min)
2206 y_min = y;
2207 if (y > y_max)
2208 y_max = y;
2209 }
2210 src += 16;
2211 }
2212 } else {
2213 src += (s->sr[0x13] & 0x3f) * 256;
2214 y_min = 32;
2215 y_max = -1;
2216 for(y = 0; y < 32; y++) {
2217 content = ((uint32_t *)src)[0] |
2218 ((uint32_t *)(src + 128))[0];
2219 if (content) {
2220 if (y < y_min)
2221 y_min = y;
2222 if (y > y_max)
2223 y_max = y;
2224 }
2225 src += 4;
2226 }
2227 }
2228 if (y_min > y_max) {
2229 s->last_hw_cursor_y_start = 0;
2230 s->last_hw_cursor_y_end = 0;
2231 } else {
2232 s->last_hw_cursor_y_start = y_min;
2233 s->last_hw_cursor_y_end = y_max + 1;
2234 }
2235}
2236
2237/* NOTE: we do not currently handle the cursor bitmap change, so we
2238 update the cursor only if it moves. */
2239static void cirrus_cursor_invalidate(VGAState *s1)
2240{
2241 CirrusVGAState *s = (CirrusVGAState *)s1;
2242 int size;
2243
2244 if (!s->sr[0x12] & CIRRUS_CURSOR_SHOW) {
2245 size = 0;
2246 } else {
2247 if (s->sr[0x12] & CIRRUS_CURSOR_LARGE)
2248 size = 64;
2249 else
2250 size = 32;
2251 }
2252 /* invalidate last cursor and new cursor if any change */
2253 if (s->last_hw_cursor_size != size ||
2254 s->last_hw_cursor_x != s->hw_cursor_x ||
2255 s->last_hw_cursor_y != s->hw_cursor_y) {
2256
2257 invalidate_cursor1(s);
3b46e624 2258
a5082316
FB		 2259 s->last_hw_cursor_size = size;
2260 s->last_hw_cursor_x = s->hw_cursor_x;
2261 s->last_hw_cursor_y = s->hw_cursor_y;
2262 /* compute the real cursor min and max y */
2263 cirrus_cursor_compute_yrange(s);
2264 invalidate_cursor1(s);
2265 }
2266}
2267
2268static void cirrus_cursor_draw_line(VGAState *s1, uint8_t *d1, int scr_y)
2269{
2270 CirrusVGAState *s = (CirrusVGAState *)s1;
2271 int w, h, bpp, x1, x2, poffset;
2272 unsigned int color0, color1;
2273 const uint8_t *palette, *src;
2274 uint32_t content;
3b46e624 2275
5fafdf24 2276 if (!(s->sr[0x12] & CIRRUS_CURSOR_SHOW))
a5082316
FB		 2277 return;
2278 /* fast test to see if the cursor intersects with the scan line */
2279 if (s->sr[0x12] & CIRRUS_CURSOR_LARGE) {
2280 h = 64;
2281 } else {
2282 h = 32;
2283 }
2284 if (scr_y < s->hw_cursor_y ||
2285 scr_y >= (s->hw_cursor_y + h))
2286 return;
3b46e624 2287
78e127ef 2288 src = s->vram_ptr + s->real_vram_size - 16 * 1024;
a5082316
FB		 2289 if (s->sr[0x12] & CIRRUS_CURSOR_LARGE) {
2290 src += (s->sr[0x13] & 0x3c) * 256;
2291 src += (scr_y - s->hw_cursor_y) * 16;
2292 poffset = 8;
2293 content = ((uint32_t *)src)[0] |
2294 ((uint32_t *)src)[1] |
2295 ((uint32_t *)src)[2] |
2296 ((uint32_t *)src)[3];
2297 } else {
2298 src += (s->sr[0x13] & 0x3f) * 256;
2299 src += (scr_y - s->hw_cursor_y) * 4;
2300 poffset = 128;
2301 content = ((uint32_t *)src)[0] |
2302 ((uint32_t *)(src + 128))[0];
2303 }
2304 /* if nothing to draw, no need to continue */
2305 if (!content)
2306 return;
2307 w = h;
2308
2309 x1 = s->hw_cursor_x;
2310 if (x1 >= s->last_scr_width)
2311 return;
2312 x2 = s->hw_cursor_x + w;
2313 if (x2 > s->last_scr_width)
2314 x2 = s->last_scr_width;
2315 w = x2 - x1;
2316 palette = s->cirrus_hidden_palette;
5fafdf24
TS		 2317 color0 = s->rgb_to_pixel(c6_to_8(palette[0x0 * 3]),
2318 c6_to_8(palette[0x0 * 3 + 1]),
a5082316 2319 c6_to_8(palette[0x0 * 3 + 2]));
5fafdf24
TS		 2320 color1 = s->rgb_to_pixel(c6_to_8(palette[0xf * 3]),
2321 c6_to_8(palette[0xf * 3 + 1]),
a5082316
FB		 2322 c6_to_8(palette[0xf * 3 + 2]));
2323 bpp = ((s->ds->depth + 7) >> 3);
2324 d1 += x1 * bpp;
2325 switch(s->ds->depth) {
2326 default:
2327 break;
2328 case 8:
2329 vga_draw_cursor_line_8(d1, src, poffset, w, color0, color1, 0xff);
2330 break;
2331 case 15:
2332 vga_draw_cursor_line_16(d1, src, poffset, w, color0, color1, 0x7fff);
2333 break;
2334 case 16:
2335 vga_draw_cursor_line_16(d1, src, poffset, w, color0, color1, 0xffff);
2336 break;
2337 case 32:
2338 vga_draw_cursor_line_32(d1, src, poffset, w, color0, color1, 0xffffff);
2339 break;
2340 }
2341}
2342
e6e5ad80
FB		 2343/***************************************
2344 *
2345 * LFB memory access
2346 *
2347 ***************************************/
2348
2349static uint32_t cirrus_linear_readb(void *opaque, target_phys_addr_t addr)
2350{
2351 CirrusVGAState *s = (CirrusVGAState *) opaque;
2352 uint32_t ret;
2353
e6e5ad80
FB		 2354 addr &= s->cirrus_addr_mask;
2355
5fafdf24 2356 if (((s->sr[0x17] & 0x44) == 0x44) &&
78e127ef 2357 ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) {
e6e5ad80
FB		 2358 /* memory-mapped I/O */
2359 ret = cirrus_mmio_blt_read(s, addr & 0xff);
2360 } else if (0) {
2361 /* XXX handle bitblt */
2362 ret = 0xff;
2363 } else {
2364 /* video memory */
2365 if ((s->gr[0x0B] & 0x14) == 0x14) {
2366 addr <<= 4;
2367 } else if (s->gr[0x0B] & 0x02) {
2368 addr <<= 3;
2369 }
2370 addr &= s->cirrus_addr_mask;
2371 ret = *(s->vram_ptr + addr);
2372 }
2373
2374 return ret;
2375}
2376
2377static uint32_t cirrus_linear_readw(void *opaque, target_phys_addr_t addr)
2378{
2379 uint32_t v;
2380#ifdef TARGET_WORDS_BIGENDIAN
2381 v = cirrus_linear_readb(opaque, addr) << 8;
2382 v |= cirrus_linear_readb(opaque, addr + 1);
2383#else
2384 v = cirrus_linear_readb(opaque, addr);
2385 v |= cirrus_linear_readb(opaque, addr + 1) << 8;
2386#endif
2387 return v;
2388}
2389
2390static uint32_t cirrus_linear_readl(void *opaque, target_phys_addr_t addr)
2391{
2392 uint32_t v;
2393#ifdef TARGET_WORDS_BIGENDIAN
2394 v = cirrus_linear_readb(opaque, addr) << 24;
2395 v |= cirrus_linear_readb(opaque, addr + 1) << 16;
2396 v |= cirrus_linear_readb(opaque, addr + 2) << 8;
2397 v |= cirrus_linear_readb(opaque, addr + 3);
2398#else
2399 v = cirrus_linear_readb(opaque, addr);
2400 v |= cirrus_linear_readb(opaque, addr + 1) << 8;
2401 v |= cirrus_linear_readb(opaque, addr + 2) << 16;
2402 v |= cirrus_linear_readb(opaque, addr + 3) << 24;
2403#endif
2404 return v;
2405}
2406
2407static void cirrus_linear_writeb(void *opaque, target_phys_addr_t addr,
2408 uint32_t val)
2409{
2410 CirrusVGAState *s = (CirrusVGAState *) opaque;
2411 unsigned mode;
2412
2413 addr &= s->cirrus_addr_mask;
3b46e624 2414
5fafdf24 2415 if (((s->sr[0x17] & 0x44) == 0x44) &&
78e127ef 2416 ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) {
e6e5ad80
FB		 2417 /* memory-mapped I/O */
2418 cirrus_mmio_blt_write(s, addr & 0xff, val);
2419 } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2420 /* bitblt */
2421 *s->cirrus_srcptr++ = (uint8_t) val;
a5082316 2422 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
e6e5ad80
FB		 2423 cirrus_bitblt_cputovideo_next(s);
2424 }
2425 } else {
2426 /* video memory */
2427 if ((s->gr[0x0B] & 0x14) == 0x14) {
2428 addr <<= 4;
2429 } else if (s->gr[0x0B] & 0x02) {
2430 addr <<= 3;
2431 }
2432 addr &= s->cirrus_addr_mask;
2433
2434 mode = s->gr[0x05] & 0x7;
2435 if (mode < 4 || mode > 5 || ((s->gr[0x0B] & 0x4) == 0)) {
2436 *(s->vram_ptr + addr) = (uint8_t) val;
2437 cpu_physical_memory_set_dirty(s->vram_offset + addr);
2438 } else {
2439 if ((s->gr[0x0B] & 0x14) != 0x14) {
2440 cirrus_mem_writeb_mode4and5_8bpp(s, mode, addr, val);
2441 } else {
2442 cirrus_mem_writeb_mode4and5_16bpp(s, mode, addr, val);
2443 }
2444 }
2445 }
2446}
2447
2448static void cirrus_linear_writew(void *opaque, target_phys_addr_t addr,
2449 uint32_t val)
2450{
2451#ifdef TARGET_WORDS_BIGENDIAN
2452 cirrus_linear_writeb(opaque, addr, (val >> 8) & 0xff);
2453 cirrus_linear_writeb(opaque, addr + 1, val & 0xff);
2454#else
2455 cirrus_linear_writeb(opaque, addr, val & 0xff);
2456 cirrus_linear_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2457#endif
2458}
2459
2460static void cirrus_linear_writel(void *opaque, target_phys_addr_t addr,
2461 uint32_t val)
2462{
2463#ifdef TARGET_WORDS_BIGENDIAN
2464 cirrus_linear_writeb(opaque, addr, (val >> 24) & 0xff);
2465 cirrus_linear_writeb(opaque, addr + 1, (val >> 16) & 0xff);
2466 cirrus_linear_writeb(opaque, addr + 2, (val >> 8) & 0xff);
2467 cirrus_linear_writeb(opaque, addr + 3, val & 0xff);
2468#else
2469 cirrus_linear_writeb(opaque, addr, val & 0xff);
2470 cirrus_linear_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2471 cirrus_linear_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2472 cirrus_linear_writeb(opaque, addr + 3, (val >> 24) & 0xff);
2473#endif
2474}
2475
2476
2477static CPUReadMemoryFunc *cirrus_linear_read[3] = {
2478 cirrus_linear_readb,
2479 cirrus_linear_readw,
2480 cirrus_linear_readl,
2481};
2482
2483static CPUWriteMemoryFunc *cirrus_linear_write[3] = {
2484 cirrus_linear_writeb,
2485 cirrus_linear_writew,
2486 cirrus_linear_writel,
2487};
2488
8926b517
FB		 2489static void cirrus_linear_mem_writeb(void *opaque, target_phys_addr_t addr,
2490 uint32_t val)
2491{
2492 CirrusVGAState *s = (CirrusVGAState *) opaque;
2493
2494 addr &= s->cirrus_addr_mask;
2495 *(s->vram_ptr + addr) = val;
2496 cpu_physical_memory_set_dirty(s->vram_offset + addr);
2497}
2498
2499static void cirrus_linear_mem_writew(void *opaque, target_phys_addr_t addr,
2500 uint32_t val)
2501{
2502 CirrusVGAState *s = (CirrusVGAState *) opaque;
2503
2504 addr &= s->cirrus_addr_mask;
2505 cpu_to_le16w((uint16_t *)(s->vram_ptr + addr), val);
2506 cpu_physical_memory_set_dirty(s->vram_offset + addr);
2507}
2508
2509static void cirrus_linear_mem_writel(void *opaque, target_phys_addr_t addr,
2510 uint32_t val)
2511{
2512 CirrusVGAState *s = (CirrusVGAState *) opaque;
2513
2514 addr &= s->cirrus_addr_mask;
2515 cpu_to_le32w((uint32_t *)(s->vram_ptr + addr), val);
2516 cpu_physical_memory_set_dirty(s->vram_offset + addr);
2517}
2518
a5082316
FB		 2519/***************************************
2520 *
2521 * system to screen memory access
2522 *
2523 ***************************************/
2524
2525
2526static uint32_t cirrus_linear_bitblt_readb(void *opaque, target_phys_addr_t addr)
2527{
2528 uint32_t ret;
2529
2530 /* XXX handle bitblt */
2531 ret = 0xff;
2532 return ret;
2533}
2534
2535static uint32_t cirrus_linear_bitblt_readw(void *opaque, target_phys_addr_t addr)
2536{
2537 uint32_t v;
2538#ifdef TARGET_WORDS_BIGENDIAN
2539 v = cirrus_linear_bitblt_readb(opaque, addr) << 8;
2540 v |= cirrus_linear_bitblt_readb(opaque, addr + 1);
2541#else
2542 v = cirrus_linear_bitblt_readb(opaque, addr);
2543 v |= cirrus_linear_bitblt_readb(opaque, addr + 1) << 8;
2544#endif
2545 return v;
2546}
2547
2548static uint32_t cirrus_linear_bitblt_readl(void *opaque, target_phys_addr_t addr)
2549{
2550 uint32_t v;
2551#ifdef TARGET_WORDS_BIGENDIAN
2552 v = cirrus_linear_bitblt_readb(opaque, addr) << 24;
2553 v |= cirrus_linear_bitblt_readb(opaque, addr + 1) << 16;
2554 v |= cirrus_linear_bitblt_readb(opaque, addr + 2) << 8;
2555 v |= cirrus_linear_bitblt_readb(opaque, addr + 3);
2556#else
2557 v = cirrus_linear_bitblt_readb(opaque, addr);
2558 v |= cirrus_linear_bitblt_readb(opaque, addr + 1) << 8;
2559 v |= cirrus_linear_bitblt_readb(opaque, addr + 2) << 16;
2560 v |= cirrus_linear_bitblt_readb(opaque, addr + 3) << 24;
2561#endif
2562 return v;
2563}
2564
2565static void cirrus_linear_bitblt_writeb(void *opaque, target_phys_addr_t addr,
2566 uint32_t val)
2567{
2568 CirrusVGAState *s = (CirrusVGAState *) opaque;
2569
2570 if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2571 /* bitblt */
2572 *s->cirrus_srcptr++ = (uint8_t) val;
2573 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
2574 cirrus_bitblt_cputovideo_next(s);
2575 }
2576 }
2577}
2578
2579static void cirrus_linear_bitblt_writew(void *opaque, target_phys_addr_t addr,
2580 uint32_t val)
2581{
2582#ifdef TARGET_WORDS_BIGENDIAN
2583 cirrus_linear_bitblt_writeb(opaque, addr, (val >> 8) & 0xff);
2584 cirrus_linear_bitblt_writeb(opaque, addr + 1, val & 0xff);
2585#else
2586 cirrus_linear_bitblt_writeb(opaque, addr, val & 0xff);
2587 cirrus_linear_bitblt_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2588#endif
2589}
2590
2591static void cirrus_linear_bitblt_writel(void *opaque, target_phys_addr_t addr,
2592 uint32_t val)
2593{
2594#ifdef TARGET_WORDS_BIGENDIAN
2595 cirrus_linear_bitblt_writeb(opaque, addr, (val >> 24) & 0xff);
2596 cirrus_linear_bitblt_writeb(opaque, addr + 1, (val >> 16) & 0xff);
2597 cirrus_linear_bitblt_writeb(opaque, addr + 2, (val >> 8) & 0xff);
2598 cirrus_linear_bitblt_writeb(opaque, addr + 3, val & 0xff);
2599#else
2600 cirrus_linear_bitblt_writeb(opaque, addr, val & 0xff);
2601 cirrus_linear_bitblt_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2602 cirrus_linear_bitblt_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2603 cirrus_linear_bitblt_writeb(opaque, addr + 3, (val >> 24) & 0xff);
2604#endif
2605}
2606
2607
2608static CPUReadMemoryFunc *cirrus_linear_bitblt_read[3] = {
2609 cirrus_linear_bitblt_readb,
2610 cirrus_linear_bitblt_readw,
2611 cirrus_linear_bitblt_readl,
2612};
2613
2614static CPUWriteMemoryFunc *cirrus_linear_bitblt_write[3] = {
2615 cirrus_linear_bitblt_writeb,
2616 cirrus_linear_bitblt_writew,
2617 cirrus_linear_bitblt_writel,
2618};
2619
8926b517
FB		 2620/* Compute the memory access functions */
2621static void cirrus_update_memory_access(CirrusVGAState *s)
2622{
2623 unsigned mode;
2624
2625 if ((s->sr[0x17] & 0x44) == 0x44) {
2626 goto generic_io;
2627 } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2628 goto generic_io;
2629 } else {
2630 if ((s->gr[0x0B] & 0x14) == 0x14) {
2631 goto generic_io;
2632 } else if (s->gr[0x0B] & 0x02) {
2633 goto generic_io;
2634 }
3b46e624 2635
8926b517
FB		 2636 mode = s->gr[0x05] & 0x7;
2637 if (mode < 4 || mode > 5 || ((s->gr[0x0B] & 0x4) == 0)) {
2638 s->cirrus_linear_write[0] = cirrus_linear_mem_writeb;
2639 s->cirrus_linear_write[1] = cirrus_linear_mem_writew;
2640 s->cirrus_linear_write[2] = cirrus_linear_mem_writel;
2641 } else {
2642 generic_io:
2643 s->cirrus_linear_write[0] = cirrus_linear_writeb;
2644 s->cirrus_linear_write[1] = cirrus_linear_writew;
2645 s->cirrus_linear_write[2] = cirrus_linear_writel;
2646 }
2647 }
2648}
2649
2650
e6e5ad80
FB		 2651/* I/O ports */
2652
2653static uint32_t vga_ioport_read(void *opaque, uint32_t addr)
2654{
2655 CirrusVGAState *s = opaque;
2656 int val, index;
2657
2658 /* check port range access depending on color/monochrome mode */
2659 if ((addr >= 0x3b0 && addr <= 0x3bf && (s->msr & MSR_COLOR_EMULATION))
2660 || (addr >= 0x3d0 && addr <= 0x3df
2661 && !(s->msr & MSR_COLOR_EMULATION))) {
2662 val = 0xff;
2663 } else {
2664 switch (addr) {
2665 case 0x3c0:
2666 if (s->ar_flip_flop == 0) {
2667 val = s->ar_index;
2668 } else {
2669 val = 0;
2670 }
2671 break;
2672 case 0x3c1:
2673 index = s->ar_index & 0x1f;
2674 if (index < 21)
2675 val = s->ar[index];
2676 else
2677 val = 0;
2678 break;
2679 case 0x3c2:
2680 val = s->st00;
2681 break;
2682 case 0x3c4:
2683 val = s->sr_index;
2684 break;
2685 case 0x3c5:
2686 if (cirrus_hook_read_sr(s, s->sr_index, &val))
2687 break;
2688 val = s->sr[s->sr_index];
2689#ifdef DEBUG_VGA_REG
2690 printf("vga: read SR%x = 0x%02x\n", s->sr_index, val);
2691#endif
2692 break;
2693 case 0x3c6:
2694 cirrus_read_hidden_dac(s, &val);
2695 break;
2696 case 0x3c7:
2697 val = s->dac_state;
2698 break;
ae184e4a
FB		 2699 case 0x3c8:
2700 val = s->dac_write_index;
2701 s->cirrus_hidden_dac_lockindex = 0;
2702 break;
2703 case 0x3c9:
e6e5ad80
FB		 2704 if (cirrus_hook_read_palette(s, &val))
2705 break;
2706 val = s->palette[s->dac_read_index * 3 + s->dac_sub_index];
2707 if (++s->dac_sub_index == 3) {
2708 s->dac_sub_index = 0;
2709 s->dac_read_index++;
2710 }
2711 break;
2712 case 0x3ca:
2713 val = s->fcr;
2714 break;
2715 case 0x3cc:
2716 val = s->msr;
2717 break;
2718 case 0x3ce:
2719 val = s->gr_index;
2720 break;
2721 case 0x3cf:
2722 if (cirrus_hook_read_gr(s, s->gr_index, &val))
2723 break;
2724 val = s->gr[s->gr_index];
2725#ifdef DEBUG_VGA_REG
2726 printf("vga: read GR%x = 0x%02x\n", s->gr_index, val);
2727#endif
2728 break;
2729 case 0x3b4:
2730 case 0x3d4:
2731 val = s->cr_index;
2732 break;
2733 case 0x3b5:
2734 case 0x3d5:
2735 if (cirrus_hook_read_cr(s, s->cr_index, &val))
2736 break;
2737 val = s->cr[s->cr_index];
2738#ifdef DEBUG_VGA_REG
2739 printf("vga: read CR%x = 0x%02x\n", s->cr_index, val);
e6e5ad80
FB		 2740#endif
2741 break;
2742 case 0x3ba:
2743 case 0x3da:
2744 /* just toggle to fool polling */
2745 s->st01 ^= ST01_V_RETRACE | ST01_DISP_ENABLE;
2746 val = s->st01;
2747 s->ar_flip_flop = 0;
2748 break;
2749 default:
2750 val = 0x00;
2751 break;
2752 }
2753 }
2754#if defined(DEBUG_VGA)
2755 printf("VGA: read addr=0x%04x data=0x%02x\n", addr, val);
2756#endif
2757 return val;
2758}
2759
2760static void vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
2761{
2762 CirrusVGAState *s = opaque;
2763 int index;
2764
2765 /* check port range access depending on color/monochrome mode */
2766 if ((addr >= 0x3b0 && addr <= 0x3bf && (s->msr & MSR_COLOR_EMULATION))
2767 || (addr >= 0x3d0 && addr <= 0x3df
2768 && !(s->msr & MSR_COLOR_EMULATION)))
2769 return;
2770
2771#ifdef DEBUG_VGA
2772 printf("VGA: write addr=0x%04x data=0x%02x\n", addr, val);
2773#endif
2774
2775 switch (addr) {
2776 case 0x3c0:
2777 if (s->ar_flip_flop == 0) {
2778 val &= 0x3f;
2779 s->ar_index = val;
2780 } else {
2781 index = s->ar_index & 0x1f;
2782 switch (index) {
2783 case 0x00 ... 0x0f:
2784 s->ar[index] = val & 0x3f;
2785 break;
2786 case 0x10:
2787 s->ar[index] = val & ~0x10;
2788 break;
2789 case 0x11:
2790 s->ar[index] = val;
2791 break;
2792 case 0x12:
2793 s->ar[index] = val & ~0xc0;
2794 break;
2795 case 0x13:
2796 s->ar[index] = val & ~0xf0;
2797 break;
2798 case 0x14:
2799 s->ar[index] = val & ~0xf0;
2800 break;
2801 default:
2802 break;
2803 }
2804 }
2805 s->ar_flip_flop ^= 1;
2806 break;
2807 case 0x3c2:
2808 s->msr = val & ~0x10;
2809 break;
2810 case 0x3c4:
2811 s->sr_index = val;
2812 break;
2813 case 0x3c5:
2814 if (cirrus_hook_write_sr(s, s->sr_index, val))
2815 break;
2816#ifdef DEBUG_VGA_REG
2817 printf("vga: write SR%x = 0x%02x\n", s->sr_index, val);
2818#endif
2819 s->sr[s->sr_index] = val & sr_mask[s->sr_index];
2820 break;
2821 case 0x3c6:
2822 cirrus_write_hidden_dac(s, val);
2823 break;
2824 case 0x3c7:
2825 s->dac_read_index = val;
2826 s->dac_sub_index = 0;
2827 s->dac_state = 3;
2828 break;
2829 case 0x3c8:
2830 s->dac_write_index = val;
2831 s->dac_sub_index = 0;
2832 s->dac_state = 0;
2833 break;
2834 case 0x3c9:
2835 if (cirrus_hook_write_palette(s, val))
2836 break;
2837 s->dac_cache[s->dac_sub_index] = val;
2838 if (++s->dac_sub_index == 3) {
2839 memcpy(&s->palette[s->dac_write_index * 3], s->dac_cache, 3);
2840 s->dac_sub_index = 0;
2841 s->dac_write_index++;
2842 }
2843 break;
2844 case 0x3ce:
2845 s->gr_index = val;
2846 break;
2847 case 0x3cf:
2848 if (cirrus_hook_write_gr(s, s->gr_index, val))
2849 break;
2850#ifdef DEBUG_VGA_REG
2851 printf("vga: write GR%x = 0x%02x\n", s->gr_index, val);
2852#endif
2853 s->gr[s->gr_index] = val & gr_mask[s->gr_index];
2854 break;
2855 case 0x3b4:
2856 case 0x3d4:
2857 s->cr_index = val;
2858 break;
2859 case 0x3b5:
2860 case 0x3d5:
2861 if (cirrus_hook_write_cr(s, s->cr_index, val))
2862 break;
2863#ifdef DEBUG_VGA_REG
2864 printf("vga: write CR%x = 0x%02x\n", s->cr_index, val);
2865#endif
2866 /* handle CR0-7 protection */
9bb34eac 2867 if ((s->cr[0x11] & 0x80) && s->cr_index <= 7) {
e6e5ad80
FB		 2868 /* can always write bit 4 of CR7 */
2869 if (s->cr_index == 7)
2870 s->cr[7] = (s->cr[7] & ~0x10) | (val & 0x10);
2871 return;
2872 }
2873 switch (s->cr_index) {
2874 case 0x01: /* horizontal display end */
2875 case 0x07:
2876 case 0x09:
2877 case 0x0c:
2878 case 0x0d:
e91c8a77 2879 case 0x12: /* vertical display end */
e6e5ad80
FB		 2880 s->cr[s->cr_index] = val;
2881 break;
2882
2883 default:
2884 s->cr[s->cr_index] = val;
2885 break;
2886 }
2887 break;
2888 case 0x3ba:
2889 case 0x3da:
2890 s->fcr = val & 0x10;
2891 break;
2892 }
2893}
2894
e36f36e1
FB		 2895/***************************************
2896 *
2897 * memory-mapped I/O access
2898 *
2899 ***************************************/
2900
2901static uint32_t cirrus_mmio_readb(void *opaque, target_phys_addr_t addr)
2902{
2903 CirrusVGAState *s = (CirrusVGAState *) opaque;
2904
2905 addr &= CIRRUS_PNPMMIO_SIZE - 1;
2906
2907 if (addr >= 0x100) {
2908 return cirrus_mmio_blt_read(s, addr - 0x100);
2909 } else {
2910 return vga_ioport_read(s, addr + 0x3c0);
2911 }
2912}
2913
2914static uint32_t cirrus_mmio_readw(void *opaque, target_phys_addr_t addr)
2915{
2916 uint32_t v;
2917#ifdef TARGET_WORDS_BIGENDIAN
2918 v = cirrus_mmio_readb(opaque, addr) << 8;
2919 v |= cirrus_mmio_readb(opaque, addr + 1);
2920#else
2921 v = cirrus_mmio_readb(opaque, addr);
2922 v |= cirrus_mmio_readb(opaque, addr + 1) << 8;
2923#endif
2924 return v;
2925}
2926
2927static uint32_t cirrus_mmio_readl(void *opaque, target_phys_addr_t addr)
2928{
2929 uint32_t v;
2930#ifdef TARGET_WORDS_BIGENDIAN
2931 v = cirrus_mmio_readb(opaque, addr) << 24;
2932 v |= cirrus_mmio_readb(opaque, addr + 1) << 16;
2933 v |= cirrus_mmio_readb(opaque, addr + 2) << 8;
2934 v |= cirrus_mmio_readb(opaque, addr + 3);
2935#else
2936 v = cirrus_mmio_readb(opaque, addr);
2937 v |= cirrus_mmio_readb(opaque, addr + 1) << 8;
2938 v |= cirrus_mmio_readb(opaque, addr + 2) << 16;
2939 v |= cirrus_mmio_readb(opaque, addr + 3) << 24;
2940#endif
2941 return v;
2942}
2943
2944static void cirrus_mmio_writeb(void *opaque, target_phys_addr_t addr,
2945 uint32_t val)
2946{
2947 CirrusVGAState *s = (CirrusVGAState *) opaque;
2948
2949 addr &= CIRRUS_PNPMMIO_SIZE - 1;
2950
2951 if (addr >= 0x100) {
2952 cirrus_mmio_blt_write(s, addr - 0x100, val);
2953 } else {
2954 vga_ioport_write(s, addr + 0x3c0, val);
2955 }
2956}
2957
2958static void cirrus_mmio_writew(void *opaque, target_phys_addr_t addr,
2959 uint32_t val)
2960{
2961#ifdef TARGET_WORDS_BIGENDIAN
2962 cirrus_mmio_writeb(opaque, addr, (val >> 8) & 0xff);
2963 cirrus_mmio_writeb(opaque, addr + 1, val & 0xff);
2964#else
2965 cirrus_mmio_writeb(opaque, addr, val & 0xff);
2966 cirrus_mmio_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2967#endif
2968}
2969
2970static void cirrus_mmio_writel(void *opaque, target_phys_addr_t addr,
2971 uint32_t val)
2972{
2973#ifdef TARGET_WORDS_BIGENDIAN
2974 cirrus_mmio_writeb(opaque, addr, (val >> 24) & 0xff);
2975 cirrus_mmio_writeb(opaque, addr + 1, (val >> 16) & 0xff);
2976 cirrus_mmio_writeb(opaque, addr + 2, (val >> 8) & 0xff);
2977 cirrus_mmio_writeb(opaque, addr + 3, val & 0xff);
2978#else
2979 cirrus_mmio_writeb(opaque, addr, val & 0xff);
2980 cirrus_mmio_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2981 cirrus_mmio_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2982 cirrus_mmio_writeb(opaque, addr + 3, (val >> 24) & 0xff);
2983#endif
2984}
2985
2986
2987static CPUReadMemoryFunc *cirrus_mmio_read[3] = {
2988 cirrus_mmio_readb,
2989 cirrus_mmio_readw,
2990 cirrus_mmio_readl,
2991};
2992
2993static CPUWriteMemoryFunc *cirrus_mmio_write[3] = {
2994 cirrus_mmio_writeb,
2995 cirrus_mmio_writew,
2996 cirrus_mmio_writel,
2997};
2998
2c6ab832
FB		 2999/* load/save state */
3000
3001static void cirrus_vga_save(QEMUFile *f, void *opaque)
3002{
3003 CirrusVGAState *s = opaque;
3004
d2269f6f
FB		 3005 if (s->pci_dev)
3006 pci_device_save(s->pci_dev, f);
3007
2c6ab832
FB		 3008 qemu_put_be32s(f, &s->latch);
3009 qemu_put_8s(f, &s->sr_index);
3010 qemu_put_buffer(f, s->sr, 256);
3011 qemu_put_8s(f, &s->gr_index);
3012 qemu_put_8s(f, &s->cirrus_shadow_gr0);
3013 qemu_put_8s(f, &s->cirrus_shadow_gr1);
3014 qemu_put_buffer(f, s->gr + 2, 254);
3015 qemu_put_8s(f, &s->ar_index);
3016 qemu_put_buffer(f, s->ar, 21);
bee8d684 3017 qemu_put_be32(f, s->ar_flip_flop);
2c6ab832
FB		 3018 qemu_put_8s(f, &s->cr_index);
3019 qemu_put_buffer(f, s->cr, 256);
3020 qemu_put_8s(f, &s->msr);
3021 qemu_put_8s(f, &s->fcr);
3022 qemu_put_8s(f, &s->st00);
3023 qemu_put_8s(f, &s->st01);
3024
3025 qemu_put_8s(f, &s->dac_state);
3026 qemu_put_8s(f, &s->dac_sub_index);
3027 qemu_put_8s(f, &s->dac_read_index);
3028 qemu_put_8s(f, &s->dac_write_index);
3029 qemu_put_buffer(f, s->dac_cache, 3);
3030 qemu_put_buffer(f, s->palette, 768);
3031
bee8d684 3032 qemu_put_be32(f, s->bank_offset);
2c6ab832
FB		 3033
3034 qemu_put_8s(f, &s->cirrus_hidden_dac_lockindex);
3035 qemu_put_8s(f, &s->cirrus_hidden_dac_data);
3036
3037 qemu_put_be32s(f, &s->hw_cursor_x);
3038 qemu_put_be32s(f, &s->hw_cursor_y);
3039 /* XXX: we do not save the bitblt state - we assume we do not save
3040 the state when the blitter is active */
3041}
3042
3043static int cirrus_vga_load(QEMUFile *f, void *opaque, int version_id)
3044{
3045 CirrusVGAState *s = opaque;
d2269f6f 3046 int ret;
2c6ab832 3047
d2269f6f 3048 if (version_id > 2)
2c6ab832
FB		 3049 return -EINVAL;
3050
d2269f6f
FB		 3051 if (s->pci_dev && version_id >= 2) {
3052 ret = pci_device_load(s->pci_dev, f);
3053 if (ret < 0)
3054 return ret;
3055 }
3056
2c6ab832
FB		 3057 qemu_get_be32s(f, &s->latch);
3058 qemu_get_8s(f, &s->sr_index);
3059 qemu_get_buffer(f, s->sr, 256);
3060 qemu_get_8s(f, &s->gr_index);
3061 qemu_get_8s(f, &s->cirrus_shadow_gr0);
3062 qemu_get_8s(f, &s->cirrus_shadow_gr1);
3063 s->gr[0x00] = s->cirrus_shadow_gr0 & 0x0f;
3064 s->gr[0x01] = s->cirrus_shadow_gr1 & 0x0f;
3065 qemu_get_buffer(f, s->gr + 2, 254);
3066 qemu_get_8s(f, &s->ar_index);
3067 qemu_get_buffer(f, s->ar, 21);
bee8d684 3068 s->ar_flip_flop=qemu_get_be32(f);
2c6ab832
FB		 3069 qemu_get_8s(f, &s->cr_index);
3070 qemu_get_buffer(f, s->cr, 256);
3071 qemu_get_8s(f, &s->msr);
3072 qemu_get_8s(f, &s->fcr);
3073 qemu_get_8s(f, &s->st00);
3074 qemu_get_8s(f, &s->st01);
3075
3076 qemu_get_8s(f, &s->dac_state);
3077 qemu_get_8s(f, &s->dac_sub_index);
3078 qemu_get_8s(f, &s->dac_read_index);
3079 qemu_get_8s(f, &s->dac_write_index);
3080 qemu_get_buffer(f, s->dac_cache, 3);
3081 qemu_get_buffer(f, s->palette, 768);
3082
bee8d684 3083 s->bank_offset=qemu_get_be32(f);
2c6ab832
FB		 3084
3085 qemu_get_8s(f, &s->cirrus_hidden_dac_lockindex);
3086 qemu_get_8s(f, &s->cirrus_hidden_dac_data);
3087
3088 qemu_get_be32s(f, &s->hw_cursor_x);
3089 qemu_get_be32s(f, &s->hw_cursor_y);
3090
3091 /* force refresh */
3092 s->graphic_mode = -1;
3093 cirrus_update_bank_ptr(s, 0);
3094 cirrus_update_bank_ptr(s, 1);
3095 return 0;
3096}
3097
e6e5ad80
FB		 3098/***************************************
3099 *
3100 * initialize
3101 *
3102 ***************************************/
3103
78e127ef 3104static void cirrus_init_common(CirrusVGAState * s, int device_id, int is_pci)
e6e5ad80 3105{
a5082316
FB		 3106 int vga_io_memory, i;
3107 static int inited;
3108
3109 if (!inited) {
3110 inited = 1;
3111 for(i = 0;i < 256; i++)
3112 rop_to_index[i] = CIRRUS_ROP_NOP_INDEX; /* nop rop */
3113 rop_to_index[CIRRUS_ROP_0] = 0;
3114 rop_to_index[CIRRUS_ROP_SRC_AND_DST] = 1;
3115 rop_to_index[CIRRUS_ROP_NOP] = 2;
3116 rop_to_index[CIRRUS_ROP_SRC_AND_NOTDST] = 3;
3117 rop_to_index[CIRRUS_ROP_NOTDST] = 4;
3118 rop_to_index[CIRRUS_ROP_SRC] = 5;
3119 rop_to_index[CIRRUS_ROP_1] = 6;
3120 rop_to_index[CIRRUS_ROP_NOTSRC_AND_DST] = 7;
3121 rop_to_index[CIRRUS_ROP_SRC_XOR_DST] = 8;
3122 rop_to_index[CIRRUS_ROP_SRC_OR_DST] = 9;
3123 rop_to_index[CIRRUS_ROP_NOTSRC_OR_NOTDST] = 10;
3124 rop_to_index[CIRRUS_ROP_SRC_NOTXOR_DST] = 11;
3125 rop_to_index[CIRRUS_ROP_SRC_OR_NOTDST] = 12;
3126 rop_to_index[CIRRUS_ROP_NOTSRC] = 13;
3127 rop_to_index[CIRRUS_ROP_NOTSRC_OR_DST] = 14;
3128 rop_to_index[CIRRUS_ROP_NOTSRC_AND_NOTDST] = 15;
3129 }
e6e5ad80
FB		 3130
3131 register_ioport_write(0x3c0, 16, 1, vga_ioport_write, s);
3132
3133 register_ioport_write(0x3b4, 2, 1, vga_ioport_write, s);
3134 register_ioport_write(0x3d4, 2, 1, vga_ioport_write, s);
3135 register_ioport_write(0x3ba, 1, 1, vga_ioport_write, s);
3136 register_ioport_write(0x3da, 1, 1, vga_ioport_write, s);
3137
3138 register_ioport_read(0x3c0, 16, 1, vga_ioport_read, s);
3139
3140 register_ioport_read(0x3b4, 2, 1, vga_ioport_read, s);
3141 register_ioport_read(0x3d4, 2, 1, vga_ioport_read, s);
3142 register_ioport_read(0x3ba, 1, 1, vga_ioport_read, s);
3143 register_ioport_read(0x3da, 1, 1, vga_ioport_read, s);
3144
5fafdf24 3145 vga_io_memory = cpu_register_io_memory(0, cirrus_vga_mem_read,
e6e5ad80 3146 cirrus_vga_mem_write, s);
5fafdf24 3147 cpu_register_physical_memory(isa_mem_base + 0x000a0000, 0x20000,
e6e5ad80
FB		 3148 vga_io_memory);
3149
3150 s->sr[0x06] = 0x0f;
78e127ef
FB		 3151 if (device_id == CIRRUS_ID_CLGD5446) {
3152 /* 4MB 64 bit memory config, always PCI */
b30d4608
FB		 3153 s->sr[0x1F] = 0x2d; // MemClock
3154 s->gr[0x18] = 0x0f; // fastest memory configuration
78e127ef
FB		 3155#if 1
3156 s->sr[0x0f] = 0x98;
3157 s->sr[0x17] = 0x20;
3158 s->sr[0x15] = 0x04; /* memory size, 3=2MB, 4=4MB */
3159 s->real_vram_size = 4096 * 1024;
3160#else
3161 s->sr[0x0f] = 0x18;
3162 s->sr[0x17] = 0x20;
3163 s->sr[0x15] = 0x03; /* memory size, 3=2MB, 4=4MB */
3164 s->real_vram_size = 2048 * 1024;
3165#endif
3166 } else {
b30d4608 3167 s->sr[0x1F] = 0x22; // MemClock
78e127ef 3168 s->sr[0x0F] = CIRRUS_MEMSIZE_2M;
5fafdf24 3169 if (is_pci)
78e127ef
FB		 3170 s->sr[0x17] = CIRRUS_BUSTYPE_PCI;
3171 else
3172 s->sr[0x17] = CIRRUS_BUSTYPE_ISA;
3173 s->real_vram_size = 2048 * 1024;
3174 s->sr[0x15] = 0x03; /* memory size, 3=2MB, 4=4MB */
3175 }
20ba3ae1 3176 s->cr[0x27] = device_id;
e6e5ad80 3177
78e127ef
FB		 3178 /* Win2K seems to assume that the pattern buffer is at 0xff
3179 initially ! */
3180 memset(s->vram_ptr, 0xff, s->real_vram_size);
3181
e6e5ad80
FB		 3182 s->cirrus_hidden_dac_lockindex = 5;
3183 s->cirrus_hidden_dac_data = 0;
3184
3185 /* I/O handler for LFB */
3186 s->cirrus_linear_io_addr =
3187 cpu_register_io_memory(0, cirrus_linear_read, cirrus_linear_write,
3188 s);
8926b517
FB		 3189 s->cirrus_linear_write = cpu_get_io_memory_write(s->cirrus_linear_io_addr);
3190
a5082316
FB		 3191 /* I/O handler for LFB */
3192 s->cirrus_linear_bitblt_io_addr =
3193 cpu_register_io_memory(0, cirrus_linear_bitblt_read, cirrus_linear_bitblt_write,
3194 s);
3195
e6e5ad80
FB		 3196 /* I/O handler for memory-mapped I/O */
3197 s->cirrus_mmio_io_addr =
3198 cpu_register_io_memory(0, cirrus_mmio_read, cirrus_mmio_write, s);
3199
3200 /* XXX: s->vram_size must be a power of two */
78e127ef
FB		 3201 s->cirrus_addr_mask = s->real_vram_size - 1;
3202 s->linear_mmio_mask = s->real_vram_size - 256;
e6e5ad80
FB		 3203
3204 s->get_bpp = cirrus_get_bpp;
3205 s->get_offsets = cirrus_get_offsets;
78e127ef 3206 s->get_resolution = cirrus_get_resolution;
a5082316
FB		 3207 s->cursor_invalidate = cirrus_cursor_invalidate;
3208 s->cursor_draw_line = cirrus_cursor_draw_line;
2c6ab832 3209
d2269f6f 3210 register_savevm("cirrus_vga", 0, 2, cirrus_vga_save, cirrus_vga_load, s);
e6e5ad80
FB		 3211}
3212
3213/***************************************
3214 *
3215 * ISA bus support
3216 *
3217 ***************************************/
3218
5fafdf24 3219void isa_cirrus_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
e6e5ad80
FB		 3220 unsigned long vga_ram_offset, int vga_ram_size)
3221{
3222 CirrusVGAState *s;
3223
3224 s = qemu_mallocz(sizeof(CirrusVGAState));
3b46e624 3225
5fafdf24 3226 vga_common_init((VGAState *)s,
e6e5ad80 3227 ds, vga_ram_base, vga_ram_offset, vga_ram_size);
78e127ef 3228 cirrus_init_common(s, CIRRUS_ID_CLGD5430, 0);
e6e5ad80
FB		 3229 /* XXX ISA-LFB support */
3230}
3231
3232/***************************************
3233 *
3234 * PCI bus support
3235 *
3236 ***************************************/
3237
3238static void cirrus_pci_lfb_map(PCIDevice *d, int region_num,
3239 uint32_t addr, uint32_t size, int type)
3240{
3241 CirrusVGAState *s = &((PCICirrusVGAState *)d)->cirrus_vga;
3242
a5082316 3243 /* XXX: add byte swapping apertures */
e6e5ad80
FB		 3244 cpu_register_physical_memory(addr, s->vram_size,
3245 s->cirrus_linear_io_addr);
a5082316
FB		 3246 cpu_register_physical_memory(addr + 0x1000000, 0x400000,
3247 s->cirrus_linear_bitblt_io_addr);
e6e5ad80
FB		 3248}
3249
3250static void cirrus_pci_mmio_map(PCIDevice *d, int region_num,
3251 uint32_t addr, uint32_t size, int type)
3252{
3253 CirrusVGAState *s = &((PCICirrusVGAState *)d)->cirrus_vga;
3254
3255 cpu_register_physical_memory(addr, CIRRUS_PNPMMIO_SIZE,
3256 s->cirrus_mmio_io_addr);
3257}
3258
5fafdf24 3259void pci_cirrus_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
e6e5ad80
FB		 3260 unsigned long vga_ram_offset, int vga_ram_size)
3261{
3262 PCICirrusVGAState *d;
3263 uint8_t *pci_conf;
3264 CirrusVGAState *s;
20ba3ae1 3265 int device_id;
3b46e624 3266
20ba3ae1 3267 device_id = CIRRUS_ID_CLGD5446;
e6e5ad80
FB		 3268
3269 /* setup PCI configuration registers */
5fafdf24
TS		 3270 d = (PCICirrusVGAState *)pci_register_device(bus, "Cirrus VGA",
3271 sizeof(PCICirrusVGAState),
46e50e9d 3272 -1, NULL, NULL);
e6e5ad80
FB		 3273 pci_conf = d->dev.config;
3274 pci_conf[0x00] = (uint8_t) (PCI_VENDOR_CIRRUS & 0xff);
3275 pci_conf[0x01] = (uint8_t) (PCI_VENDOR_CIRRUS >> 8);
20ba3ae1
FB		 3276 pci_conf[0x02] = (uint8_t) (device_id & 0xff);
3277 pci_conf[0x03] = (uint8_t) (device_id >> 8);
e6e5ad80
FB		 3278 pci_conf[0x04] = PCI_COMMAND_IOACCESS | PCI_COMMAND_MEMACCESS;
3279 pci_conf[0x0a] = PCI_CLASS_SUB_VGA;
3280 pci_conf[0x0b] = PCI_CLASS_BASE_DISPLAY;
3281 pci_conf[0x0e] = PCI_CLASS_HEADERTYPE_00h;
3282
3283 /* setup VGA */
3284 s = &d->cirrus_vga;
5fafdf24 3285 vga_common_init((VGAState *)s,
e6e5ad80 3286 ds, vga_ram_base, vga_ram_offset, vga_ram_size);
78e127ef 3287 cirrus_init_common(s, device_id, 1);
d34cab9f 3288
4d3b6f6e
AZ		 3289 graphic_console_init(s->ds, s->update, s->invalidate, s->screen_dump,
3290 s->text_update, s);
d34cab9f 3291
d2269f6f 3292 s->pci_dev = (PCIDevice *)d;
e6e5ad80
FB		 3293
3294 /* setup memory space */
3295 /* memory #0 LFB */
3296 /* memory #1 memory-mapped I/O */
3297 /* XXX: s->vram_size must be a power of two */
a5082316 3298 pci_register_io_region((PCIDevice *)d, 0, 0x2000000,
a21ae81d 3299 PCI_ADDRESS_SPACE_MEM_PREFETCH, cirrus_pci_lfb_map);
20ba3ae1 3300 if (device_id == CIRRUS_ID_CLGD5446) {
a21ae81d
FB		 3301 pci_register_io_region((PCIDevice *)d, 1, CIRRUS_PNPMMIO_SIZE,
3302 PCI_ADDRESS_SPACE_MEM, cirrus_pci_mmio_map);
3303 }
e6e5ad80
FB		 3304 /* XXX: ROM BIOS */
3305}
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