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cirrus: simplify bitblt BAR access functions
[qemu.git] / hw / cirrus_vga.c
CommitLineData
e6e5ad80 1/*
aeb3c85f 2 * QEMU Cirrus CLGD 54xx VGA Emulator.
5fafdf24 3 *
e6e5ad80 4 * Copyright (c) 2004 Fabrice Bellard
aeb3c85f 5 * Copyright (c) 2004 Makoto Suzuki (suzu)
5fafdf24 6 *
e6e5ad80
FB		 7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
aeb3c85f
FB		 25/*
26 * Reference: Finn Thogersons' VGADOC4b
27 * available at http://home.worldonline.dk/~finth/
28 */
87ecb68b
PB		 29#include "hw.h"
30#include "pc.h"
31#include "pci.h"
32#include "console.h"
e6e5ad80 33#include "vga_int.h"
5245d57a 34#include "loader.h"
b1950430 35#include "exec-memory.h"
e6e5ad80 36
a5082316
FB		 37/*
38 * TODO:
ad81218e 39 * - destination write mask support not complete (bits 5..7)
a5082316
FB		 40 * - optimize linear mappings
41 * - optimize bitblt functions
42 */
43
e36f36e1 44//#define DEBUG_CIRRUS
a21ae81d 45//#define DEBUG_BITBLT
e36f36e1 46
e6e5ad80
FB		 47/***************************************
48 *
49 * definitions
50 *
51 ***************************************/
52
e6e5ad80
FB		 53// ID
54#define CIRRUS_ID_CLGD5422 (0x23<<2)
55#define CIRRUS_ID_CLGD5426 (0x24<<2)
56#define CIRRUS_ID_CLGD5424 (0x25<<2)
57#define CIRRUS_ID_CLGD5428 (0x26<<2)
58#define CIRRUS_ID_CLGD5430 (0x28<<2)
59#define CIRRUS_ID_CLGD5434 (0x2A<<2)
a21ae81d 60#define CIRRUS_ID_CLGD5436 (0x2B<<2)
e6e5ad80
FB		 61#define CIRRUS_ID_CLGD5446 (0x2E<<2)
62
63// sequencer 0x07
64#define CIRRUS_SR7_BPP_VGA 0x00
65#define CIRRUS_SR7_BPP_SVGA 0x01
66#define CIRRUS_SR7_BPP_MASK 0x0e
67#define CIRRUS_SR7_BPP_8 0x00
68#define CIRRUS_SR7_BPP_16_DOUBLEVCLK 0x02
69#define CIRRUS_SR7_BPP_24 0x04
70#define CIRRUS_SR7_BPP_16 0x06
71#define CIRRUS_SR7_BPP_32 0x08
72#define CIRRUS_SR7_ISAADDR_MASK 0xe0
73
74// sequencer 0x0f
75#define CIRRUS_MEMSIZE_512k 0x08
76#define CIRRUS_MEMSIZE_1M 0x10
77#define CIRRUS_MEMSIZE_2M 0x18
78#define CIRRUS_MEMFLAGS_BANKSWITCH 0x80 // bank switching is enabled.
79
80// sequencer 0x12
81#define CIRRUS_CURSOR_SHOW 0x01
82#define CIRRUS_CURSOR_HIDDENPEL 0x02
83#define CIRRUS_CURSOR_LARGE 0x04 // 64x64 if set, 32x32 if clear
84
85// sequencer 0x17
86#define CIRRUS_BUSTYPE_VLBFAST 0x10
87#define CIRRUS_BUSTYPE_PCI 0x20
88#define CIRRUS_BUSTYPE_VLBSLOW 0x30
89#define CIRRUS_BUSTYPE_ISA 0x38
90#define CIRRUS_MMIO_ENABLE 0x04
91#define CIRRUS_MMIO_USE_PCIADDR 0x40 // 0xb8000 if cleared.
92#define CIRRUS_MEMSIZEEXT_DOUBLE 0x80
93
94// control 0x0b
95#define CIRRUS_BANKING_DUAL 0x01
96#define CIRRUS_BANKING_GRANULARITY_16K 0x20 // set:16k, clear:4k
97
98// control 0x30
99#define CIRRUS_BLTMODE_BACKWARDS 0x01
100#define CIRRUS_BLTMODE_MEMSYSDEST 0x02
101#define CIRRUS_BLTMODE_MEMSYSSRC 0x04
102#define CIRRUS_BLTMODE_TRANSPARENTCOMP 0x08
103#define CIRRUS_BLTMODE_PATTERNCOPY 0x40
104#define CIRRUS_BLTMODE_COLOREXPAND 0x80
105#define CIRRUS_BLTMODE_PIXELWIDTHMASK 0x30
106#define CIRRUS_BLTMODE_PIXELWIDTH8 0x00
107#define CIRRUS_BLTMODE_PIXELWIDTH16 0x10
108#define CIRRUS_BLTMODE_PIXELWIDTH24 0x20
109#define CIRRUS_BLTMODE_PIXELWIDTH32 0x30
110
111// control 0x31
112#define CIRRUS_BLT_BUSY 0x01
113#define CIRRUS_BLT_START 0x02
114#define CIRRUS_BLT_RESET 0x04
115#define CIRRUS_BLT_FIFOUSED 0x10
a5082316 116#define CIRRUS_BLT_AUTOSTART 0x80
e6e5ad80
FB		 117
118// control 0x32
119#define CIRRUS_ROP_0 0x00
120#define CIRRUS_ROP_SRC_AND_DST 0x05
121#define CIRRUS_ROP_NOP 0x06
122#define CIRRUS_ROP_SRC_AND_NOTDST 0x09
123#define CIRRUS_ROP_NOTDST 0x0b
124#define CIRRUS_ROP_SRC 0x0d
125#define CIRRUS_ROP_1 0x0e
126#define CIRRUS_ROP_NOTSRC_AND_DST 0x50
127#define CIRRUS_ROP_SRC_XOR_DST 0x59
128#define CIRRUS_ROP_SRC_OR_DST 0x6d
129#define CIRRUS_ROP_NOTSRC_OR_NOTDST 0x90
130#define CIRRUS_ROP_SRC_NOTXOR_DST 0x95
131#define CIRRUS_ROP_SRC_OR_NOTDST 0xad
132#define CIRRUS_ROP_NOTSRC 0xd0
133#define CIRRUS_ROP_NOTSRC_OR_DST 0xd6
134#define CIRRUS_ROP_NOTSRC_AND_NOTDST 0xda
135
a5082316
FB		 136#define CIRRUS_ROP_NOP_INDEX 2
137#define CIRRUS_ROP_SRC_INDEX 5
138
a21ae81d 139// control 0x33
a5082316 140#define CIRRUS_BLTMODEEXT_SOLIDFILL 0x04
4c8732d7 141#define CIRRUS_BLTMODEEXT_COLOREXPINV 0x02
a5082316 142#define CIRRUS_BLTMODEEXT_DWORDGRANULARITY 0x01
a21ae81d 143
e6e5ad80
FB		 144// memory-mapped IO
145#define CIRRUS_MMIO_BLTBGCOLOR 0x00 // dword
146#define CIRRUS_MMIO_BLTFGCOLOR 0x04 // dword
147#define CIRRUS_MMIO_BLTWIDTH 0x08 // word
148#define CIRRUS_MMIO_BLTHEIGHT 0x0a // word
149#define CIRRUS_MMIO_BLTDESTPITCH 0x0c // word
150#define CIRRUS_MMIO_BLTSRCPITCH 0x0e // word
151#define CIRRUS_MMIO_BLTDESTADDR 0x10 // dword
152#define CIRRUS_MMIO_BLTSRCADDR 0x14 // dword
153#define CIRRUS_MMIO_BLTWRITEMASK 0x17 // byte
154#define CIRRUS_MMIO_BLTMODE 0x18 // byte
155#define CIRRUS_MMIO_BLTROP 0x1a // byte
156#define CIRRUS_MMIO_BLTMODEEXT 0x1b // byte
157#define CIRRUS_MMIO_BLTTRANSPARENTCOLOR 0x1c // word?
158#define CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK 0x20 // word?
159#define CIRRUS_MMIO_LINEARDRAW_START_X 0x24 // word
160#define CIRRUS_MMIO_LINEARDRAW_START_Y 0x26 // word
161#define CIRRUS_MMIO_LINEARDRAW_END_X 0x28 // word
162#define CIRRUS_MMIO_LINEARDRAW_END_Y 0x2a // word
163#define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_INC 0x2c // byte
164#define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ROLLOVER 0x2d // byte
165#define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_MASK 0x2e // byte
166#define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ACCUM 0x2f // byte
167#define CIRRUS_MMIO_BRESENHAM_K1 0x30 // word
168#define CIRRUS_MMIO_BRESENHAM_K3 0x32 // word
169#define CIRRUS_MMIO_BRESENHAM_ERROR 0x34 // word
170#define CIRRUS_MMIO_BRESENHAM_DELTA_MAJOR 0x36 // word
171#define CIRRUS_MMIO_BRESENHAM_DIRECTION 0x38 // byte
172#define CIRRUS_MMIO_LINEDRAW_MODE 0x39 // byte
173#define CIRRUS_MMIO_BLTSTATUS 0x40 // byte
174
a21ae81d 175#define CIRRUS_PNPMMIO_SIZE 0x1000
e6e5ad80 176
b2b183c2
AL		 177#define ABS(a) ((signed)(a) > 0 ? a : -a)
178
b2eb849d
AJ		 179#define BLTUNSAFE(s) \
180 ( \
181 ( /* check dst is within bounds */ \
b2b183c2 182 (s)->cirrus_blt_height * ABS((s)->cirrus_blt_dstpitch) \
b2eb849d 183 + ((s)->cirrus_blt_dstaddr & (s)->cirrus_addr_mask) > \
4e12cd94 184 (s)->vga.vram_size \
b2eb849d
AJ		 185 ) || \
186 ( /* check src is within bounds */ \
b2b183c2 187 (s)->cirrus_blt_height * ABS((s)->cirrus_blt_srcpitch) \
b2eb849d 188 + ((s)->cirrus_blt_srcaddr & (s)->cirrus_addr_mask) > \
4e12cd94 189 (s)->vga.vram_size \
b2eb849d
AJ		 190 ) \
191 )
192
a5082316
FB		 193struct CirrusVGAState;
194typedef void (*cirrus_bitblt_rop_t) (struct CirrusVGAState *s,
195 uint8_t * dst, const uint8_t * src,
e6e5ad80
FB		 196 int dstpitch, int srcpitch,
197 int bltwidth, int bltheight);
a5082316
FB		 198typedef void (*cirrus_fill_t)(struct CirrusVGAState *s,
199 uint8_t *dst, int dst_pitch, int width, int height);
e6e5ad80
FB		 200
201typedef struct CirrusVGAState {
4e12cd94 202 VGACommonState vga;
e6e5ad80 203
b1950430
AK		 204 MemoryRegion cirrus_linear_io;
205 MemoryRegion cirrus_linear_bitblt_io;
206 MemoryRegion cirrus_mmio_io;
207 MemoryRegion pci_bar;
208 bool linear_vram; /* vga.vram mapped over cirrus_linear_io */
209 MemoryRegion low_mem_container; /* container for 0xa0000-0xc0000 */
210 MemoryRegion low_mem; /* always mapped, overridden by: */
211 MemoryRegion *cirrus_bank[2]; /* aliases at 0xa0000-0xb0000 */
e6e5ad80 212 uint32_t cirrus_addr_mask;
78e127ef 213 uint32_t linear_mmio_mask;
e6e5ad80
FB		 214 uint8_t cirrus_shadow_gr0;
215 uint8_t cirrus_shadow_gr1;
216 uint8_t cirrus_hidden_dac_lockindex;
217 uint8_t cirrus_hidden_dac_data;
218 uint32_t cirrus_bank_base[2];
219 uint32_t cirrus_bank_limit[2];
220 uint8_t cirrus_hidden_palette[48];
a5082316
FB		 221 uint32_t hw_cursor_x;
222 uint32_t hw_cursor_y;
e6e5ad80
FB		 223 int cirrus_blt_pixelwidth;
224 int cirrus_blt_width;
225 int cirrus_blt_height;
226 int cirrus_blt_dstpitch;
227 int cirrus_blt_srcpitch;
a5082316
FB		 228 uint32_t cirrus_blt_fgcol;
229 uint32_t cirrus_blt_bgcol;
e6e5ad80
FB		 230 uint32_t cirrus_blt_dstaddr;
231 uint32_t cirrus_blt_srcaddr;
232 uint8_t cirrus_blt_mode;
a5082316 233 uint8_t cirrus_blt_modeext;
e6e5ad80 234 cirrus_bitblt_rop_t cirrus_rop;
a5082316 235#define CIRRUS_BLTBUFSIZE (2048 * 4) /* one line width */
e6e5ad80
FB		 236 uint8_t cirrus_bltbuf[CIRRUS_BLTBUFSIZE];
237 uint8_t *cirrus_srcptr;
238 uint8_t *cirrus_srcptr_end;
239 uint32_t cirrus_srccounter;
a5082316
FB		 240 /* hwcursor display state */
241 int last_hw_cursor_size;
242 int last_hw_cursor_x;
243 int last_hw_cursor_y;
244 int last_hw_cursor_y_start;
245 int last_hw_cursor_y_end;
78e127ef 246 int real_vram_size; /* XXX: suppress that */
4abc796d
BS		 247 int device_id;
248 int bustype;
e6e5ad80
FB		 249} CirrusVGAState;
250
251typedef struct PCICirrusVGAState {
252 PCIDevice dev;
253 CirrusVGAState cirrus_vga;
254} PCICirrusVGAState;
255
a5082316 256static uint8_t rop_to_index[256];
3b46e624 257
e6e5ad80
FB		 258/***************************************
259 *
260 * prototypes.
261 *
262 ***************************************/
263
264
8926b517
FB		 265static void cirrus_bitblt_reset(CirrusVGAState *s);
266static void cirrus_update_memory_access(CirrusVGAState *s);
e6e5ad80
FB		 267
268/***************************************
269 *
270 * raster operations
271 *
272 ***************************************/
273
a5082316
FB		 274static void cirrus_bitblt_rop_nop(CirrusVGAState *s,
275 uint8_t *dst,const uint8_t *src,
276 int dstpitch,int srcpitch,
277 int bltwidth,int bltheight)
278{
e6e5ad80
FB		 279}
280
a5082316
FB		 281static void cirrus_bitblt_fill_nop(CirrusVGAState *s,
282 uint8_t *dst,
283 int dstpitch, int bltwidth,int bltheight)
e6e5ad80 284{
a5082316 285}
e6e5ad80 286
a5082316 287#define ROP_NAME 0
8c78881f 288#define ROP_FN(d, s) 0
a5082316 289#include "cirrus_vga_rop.h"
e6e5ad80 290
a5082316 291#define ROP_NAME src_and_dst
8c78881f 292#define ROP_FN(d, s) (s) & (d)
a5082316 293#include "cirrus_vga_rop.h"
e6e5ad80 294
a5082316 295#define ROP_NAME src_and_notdst
8c78881f 296#define ROP_FN(d, s) (s) & (~(d))
a5082316 297#include "cirrus_vga_rop.h"
e6e5ad80 298
a5082316 299#define ROP_NAME notdst
8c78881f 300#define ROP_FN(d, s) ~(d)
a5082316 301#include "cirrus_vga_rop.h"
e6e5ad80 302
a5082316 303#define ROP_NAME src
8c78881f 304#define ROP_FN(d, s) s
a5082316 305#include "cirrus_vga_rop.h"
e6e5ad80 306
a5082316 307#define ROP_NAME 1
8c78881f 308#define ROP_FN(d, s) ~0
a5082316
FB		 309#include "cirrus_vga_rop.h"
310
311#define ROP_NAME notsrc_and_dst
8c78881f 312#define ROP_FN(d, s) (~(s)) & (d)
a5082316
FB		 313#include "cirrus_vga_rop.h"
314
315#define ROP_NAME src_xor_dst
8c78881f 316#define ROP_FN(d, s) (s) ^ (d)
a5082316
FB		 317#include "cirrus_vga_rop.h"
318
319#define ROP_NAME src_or_dst
8c78881f 320#define ROP_FN(d, s) (s) | (d)
a5082316
FB		 321#include "cirrus_vga_rop.h"
322
323#define ROP_NAME notsrc_or_notdst
8c78881f 324#define ROP_FN(d, s) (~(s)) | (~(d))
a5082316
FB		 325#include "cirrus_vga_rop.h"
326
327#define ROP_NAME src_notxor_dst
8c78881f 328#define ROP_FN(d, s) ~((s) ^ (d))
a5082316 329#include "cirrus_vga_rop.h"
e6e5ad80 330
a5082316 331#define ROP_NAME src_or_notdst
8c78881f 332#define ROP_FN(d, s) (s) | (~(d))
a5082316
FB		 333#include "cirrus_vga_rop.h"
334
335#define ROP_NAME notsrc
8c78881f 336#define ROP_FN(d, s) (~(s))
a5082316
FB		 337#include "cirrus_vga_rop.h"
338
339#define ROP_NAME notsrc_or_dst
8c78881f 340#define ROP_FN(d, s) (~(s)) | (d)
a5082316
FB		 341#include "cirrus_vga_rop.h"
342
343#define ROP_NAME notsrc_and_notdst
8c78881f 344#define ROP_FN(d, s) (~(s)) & (~(d))
a5082316
FB		 345#include "cirrus_vga_rop.h"
346
347static const cirrus_bitblt_rop_t cirrus_fwd_rop[16] = {
348 cirrus_bitblt_rop_fwd_0,
349 cirrus_bitblt_rop_fwd_src_and_dst,
350 cirrus_bitblt_rop_nop,
351 cirrus_bitblt_rop_fwd_src_and_notdst,
352 cirrus_bitblt_rop_fwd_notdst,
353 cirrus_bitblt_rop_fwd_src,
354 cirrus_bitblt_rop_fwd_1,
355 cirrus_bitblt_rop_fwd_notsrc_and_dst,
356 cirrus_bitblt_rop_fwd_src_xor_dst,
357 cirrus_bitblt_rop_fwd_src_or_dst,
358 cirrus_bitblt_rop_fwd_notsrc_or_notdst,
359 cirrus_bitblt_rop_fwd_src_notxor_dst,
360 cirrus_bitblt_rop_fwd_src_or_notdst,
361 cirrus_bitblt_rop_fwd_notsrc,
362 cirrus_bitblt_rop_fwd_notsrc_or_dst,
363 cirrus_bitblt_rop_fwd_notsrc_and_notdst,
364};
365
366static const cirrus_bitblt_rop_t cirrus_bkwd_rop[16] = {
367 cirrus_bitblt_rop_bkwd_0,
368 cirrus_bitblt_rop_bkwd_src_and_dst,
369 cirrus_bitblt_rop_nop,
370 cirrus_bitblt_rop_bkwd_src_and_notdst,
371 cirrus_bitblt_rop_bkwd_notdst,
372 cirrus_bitblt_rop_bkwd_src,
373 cirrus_bitblt_rop_bkwd_1,
374 cirrus_bitblt_rop_bkwd_notsrc_and_dst,
375 cirrus_bitblt_rop_bkwd_src_xor_dst,
376 cirrus_bitblt_rop_bkwd_src_or_dst,
377 cirrus_bitblt_rop_bkwd_notsrc_or_notdst,
378 cirrus_bitblt_rop_bkwd_src_notxor_dst,
379 cirrus_bitblt_rop_bkwd_src_or_notdst,
380 cirrus_bitblt_rop_bkwd_notsrc,
381 cirrus_bitblt_rop_bkwd_notsrc_or_dst,
382 cirrus_bitblt_rop_bkwd_notsrc_and_notdst,
383};
96cf2df8
TS		 384
385#define TRANSP_ROP(name) {\
386 name ## _8,\
387 name ## _16,\
388 }
389#define TRANSP_NOP(func) {\
390 func,\
391 func,\
392 }
393
394static const cirrus_bitblt_rop_t cirrus_fwd_transp_rop[16][2] = {
395 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_0),
396 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_and_dst),
397 TRANSP_NOP(cirrus_bitblt_rop_nop),
398 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_and_notdst),
399 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notdst),
400 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src),
401 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_1),
402 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_and_dst),
403 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_xor_dst),
404 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_or_dst),
405 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_or_notdst),
406 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_notxor_dst),
407 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_or_notdst),
408 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc),
409 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_or_dst),
410 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_and_notdst),
411};
412
413static const cirrus_bitblt_rop_t cirrus_bkwd_transp_rop[16][2] = {
414 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_0),
415 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_and_dst),
416 TRANSP_NOP(cirrus_bitblt_rop_nop),
417 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_and_notdst),
418 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notdst),
419 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src),
420 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_1),
421 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_and_dst),
422 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_xor_dst),
423 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_or_dst),
424 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_or_notdst),
425 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_notxor_dst),
426 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_or_notdst),
427 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc),
428 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_or_dst),
429 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_and_notdst),
430};
431
a5082316
FB		 432#define ROP2(name) {\
433 name ## _8,\
434 name ## _16,\
435 name ## _24,\
436 name ## _32,\
437 }
438
439#define ROP_NOP2(func) {\
440 func,\
441 func,\
442 func,\
443 func,\
444 }
445
e69390ce
FB		 446static const cirrus_bitblt_rop_t cirrus_patternfill[16][4] = {
447 ROP2(cirrus_patternfill_0),
448 ROP2(cirrus_patternfill_src_and_dst),
449 ROP_NOP2(cirrus_bitblt_rop_nop),
450 ROP2(cirrus_patternfill_src_and_notdst),
451 ROP2(cirrus_patternfill_notdst),
452 ROP2(cirrus_patternfill_src),
453 ROP2(cirrus_patternfill_1),
454 ROP2(cirrus_patternfill_notsrc_and_dst),
455 ROP2(cirrus_patternfill_src_xor_dst),
456 ROP2(cirrus_patternfill_src_or_dst),
457 ROP2(cirrus_patternfill_notsrc_or_notdst),
458 ROP2(cirrus_patternfill_src_notxor_dst),
459 ROP2(cirrus_patternfill_src_or_notdst),
460 ROP2(cirrus_patternfill_notsrc),
461 ROP2(cirrus_patternfill_notsrc_or_dst),
462 ROP2(cirrus_patternfill_notsrc_and_notdst),
463};
464
a5082316
FB		 465static const cirrus_bitblt_rop_t cirrus_colorexpand_transp[16][4] = {
466 ROP2(cirrus_colorexpand_transp_0),
467 ROP2(cirrus_colorexpand_transp_src_and_dst),
468 ROP_NOP2(cirrus_bitblt_rop_nop),
469 ROP2(cirrus_colorexpand_transp_src_and_notdst),
470 ROP2(cirrus_colorexpand_transp_notdst),
471 ROP2(cirrus_colorexpand_transp_src),
472 ROP2(cirrus_colorexpand_transp_1),
473 ROP2(cirrus_colorexpand_transp_notsrc_and_dst),
474 ROP2(cirrus_colorexpand_transp_src_xor_dst),
475 ROP2(cirrus_colorexpand_transp_src_or_dst),
476 ROP2(cirrus_colorexpand_transp_notsrc_or_notdst),
477 ROP2(cirrus_colorexpand_transp_src_notxor_dst),
478 ROP2(cirrus_colorexpand_transp_src_or_notdst),
479 ROP2(cirrus_colorexpand_transp_notsrc),
480 ROP2(cirrus_colorexpand_transp_notsrc_or_dst),
481 ROP2(cirrus_colorexpand_transp_notsrc_and_notdst),
482};
483
484static const cirrus_bitblt_rop_t cirrus_colorexpand[16][4] = {
485 ROP2(cirrus_colorexpand_0),
486 ROP2(cirrus_colorexpand_src_and_dst),
487 ROP_NOP2(cirrus_bitblt_rop_nop),
488 ROP2(cirrus_colorexpand_src_and_notdst),
489 ROP2(cirrus_colorexpand_notdst),
490 ROP2(cirrus_colorexpand_src),
491 ROP2(cirrus_colorexpand_1),
492 ROP2(cirrus_colorexpand_notsrc_and_dst),
493 ROP2(cirrus_colorexpand_src_xor_dst),
494 ROP2(cirrus_colorexpand_src_or_dst),
495 ROP2(cirrus_colorexpand_notsrc_or_notdst),
496 ROP2(cirrus_colorexpand_src_notxor_dst),
497 ROP2(cirrus_colorexpand_src_or_notdst),
498 ROP2(cirrus_colorexpand_notsrc),
499 ROP2(cirrus_colorexpand_notsrc_or_dst),
500 ROP2(cirrus_colorexpand_notsrc_and_notdst),
501};
502
b30d4608
FB		 503static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern_transp[16][4] = {
504 ROP2(cirrus_colorexpand_pattern_transp_0),
505 ROP2(cirrus_colorexpand_pattern_transp_src_and_dst),
506 ROP_NOP2(cirrus_bitblt_rop_nop),
507 ROP2(cirrus_colorexpand_pattern_transp_src_and_notdst),
508 ROP2(cirrus_colorexpand_pattern_transp_notdst),
509 ROP2(cirrus_colorexpand_pattern_transp_src),
510 ROP2(cirrus_colorexpand_pattern_transp_1),
511 ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_dst),
512 ROP2(cirrus_colorexpand_pattern_transp_src_xor_dst),
513 ROP2(cirrus_colorexpand_pattern_transp_src_or_dst),
514 ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_notdst),
515 ROP2(cirrus_colorexpand_pattern_transp_src_notxor_dst),
516 ROP2(cirrus_colorexpand_pattern_transp_src_or_notdst),
517 ROP2(cirrus_colorexpand_pattern_transp_notsrc),
518 ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_dst),
519 ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_notdst),
520};
521
522static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern[16][4] = {
523 ROP2(cirrus_colorexpand_pattern_0),
524 ROP2(cirrus_colorexpand_pattern_src_and_dst),
525 ROP_NOP2(cirrus_bitblt_rop_nop),
526 ROP2(cirrus_colorexpand_pattern_src_and_notdst),
527 ROP2(cirrus_colorexpand_pattern_notdst),
528 ROP2(cirrus_colorexpand_pattern_src),
529 ROP2(cirrus_colorexpand_pattern_1),
530 ROP2(cirrus_colorexpand_pattern_notsrc_and_dst),
531 ROP2(cirrus_colorexpand_pattern_src_xor_dst),
532 ROP2(cirrus_colorexpand_pattern_src_or_dst),
533 ROP2(cirrus_colorexpand_pattern_notsrc_or_notdst),
534 ROP2(cirrus_colorexpand_pattern_src_notxor_dst),
535 ROP2(cirrus_colorexpand_pattern_src_or_notdst),
536 ROP2(cirrus_colorexpand_pattern_notsrc),
537 ROP2(cirrus_colorexpand_pattern_notsrc_or_dst),
538 ROP2(cirrus_colorexpand_pattern_notsrc_and_notdst),
539};
540
a5082316
FB		 541static const cirrus_fill_t cirrus_fill[16][4] = {
542 ROP2(cirrus_fill_0),
543 ROP2(cirrus_fill_src_and_dst),
544 ROP_NOP2(cirrus_bitblt_fill_nop),
545 ROP2(cirrus_fill_src_and_notdst),
546 ROP2(cirrus_fill_notdst),
547 ROP2(cirrus_fill_src),
548 ROP2(cirrus_fill_1),
549 ROP2(cirrus_fill_notsrc_and_dst),
550 ROP2(cirrus_fill_src_xor_dst),
551 ROP2(cirrus_fill_src_or_dst),
552 ROP2(cirrus_fill_notsrc_or_notdst),
553 ROP2(cirrus_fill_src_notxor_dst),
554 ROP2(cirrus_fill_src_or_notdst),
555 ROP2(cirrus_fill_notsrc),
556 ROP2(cirrus_fill_notsrc_or_dst),
557 ROP2(cirrus_fill_notsrc_and_notdst),
558};
559
560static inline void cirrus_bitblt_fgcol(CirrusVGAState *s)
e6e5ad80 561{
a5082316
FB		 562 unsigned int color;
563 switch (s->cirrus_blt_pixelwidth) {
564 case 1:
565 s->cirrus_blt_fgcol = s->cirrus_shadow_gr1;
566 break;
567 case 2:
4e12cd94 568 color = s->cirrus_shadow_gr1 | (s->vga.gr[0x11] << 8);
a5082316
FB		 569 s->cirrus_blt_fgcol = le16_to_cpu(color);
570 break;
571 case 3:
5fafdf24 572 s->cirrus_blt_fgcol = s->cirrus_shadow_gr1 |
4e12cd94 573 (s->vga.gr[0x11] << 8) | (s->vga.gr[0x13] << 16);
a5082316
FB		 574 break;
575 default:
576 case 4:
4e12cd94
AK		 577 color = s->cirrus_shadow_gr1 | (s->vga.gr[0x11] << 8) |
578 (s->vga.gr[0x13] << 16) | (s->vga.gr[0x15] << 24);
a5082316
FB		 579 s->cirrus_blt_fgcol = le32_to_cpu(color);
580 break;
e6e5ad80
FB		 581 }
582}
583
a5082316 584static inline void cirrus_bitblt_bgcol(CirrusVGAState *s)
e6e5ad80 585{
a5082316 586 unsigned int color;
e6e5ad80
FB		 587 switch (s->cirrus_blt_pixelwidth) {
588 case 1:
a5082316
FB		 589 s->cirrus_blt_bgcol = s->cirrus_shadow_gr0;
590 break;
e6e5ad80 591 case 2:
4e12cd94 592 color = s->cirrus_shadow_gr0 | (s->vga.gr[0x10] << 8);
a5082316
FB		 593 s->cirrus_blt_bgcol = le16_to_cpu(color);
594 break;
e6e5ad80 595 case 3:
5fafdf24 596 s->cirrus_blt_bgcol = s->cirrus_shadow_gr0 |
4e12cd94 597 (s->vga.gr[0x10] << 8) | (s->vga.gr[0x12] << 16);
a5082316 598 break;
e6e5ad80 599 default:
a5082316 600 case 4:
4e12cd94
AK		 601 color = s->cirrus_shadow_gr0 | (s->vga.gr[0x10] << 8) |
602 (s->vga.gr[0x12] << 16) | (s->vga.gr[0x14] << 24);
a5082316
FB		 603 s->cirrus_blt_bgcol = le32_to_cpu(color);
604 break;
e6e5ad80
FB		 605 }
606}
607
608static void cirrus_invalidate_region(CirrusVGAState * s, int off_begin,
609 int off_pitch, int bytesperline,
610 int lines)
611{
612 int y;
613 int off_cur;
614 int off_cur_end;
615
616 for (y = 0; y < lines; y++) {
617 off_cur = off_begin;
b2eb849d 618 off_cur_end = (off_cur + bytesperline) & s->cirrus_addr_mask;
e6e5ad80
FB		 619 off_cur &= TARGET_PAGE_MASK;
620 while (off_cur < off_cur_end) {
b1950430 621 memory_region_set_dirty(&s->vga.vram, off_cur);
e6e5ad80
FB		 622 off_cur += TARGET_PAGE_SIZE;
623 }
624 off_begin += off_pitch;
625 }
626}
627
e6e5ad80
FB		 628static int cirrus_bitblt_common_patterncopy(CirrusVGAState * s,
629 const uint8_t * src)
630{
e6e5ad80 631 uint8_t *dst;
e6e5ad80 632
4e12cd94 633 dst = s->vga.vram_ptr + (s->cirrus_blt_dstaddr & s->cirrus_addr_mask);
b2eb849d
AJ		 634
635 if (BLTUNSAFE(s))
636 return 0;
637
e69390ce 638 (*s->cirrus_rop) (s, dst, src,
5fafdf24 639 s->cirrus_blt_dstpitch, 0,
e69390ce 640 s->cirrus_blt_width, s->cirrus_blt_height);
e6e5ad80 641 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
e69390ce
FB		 642 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
643 s->cirrus_blt_height);
e6e5ad80
FB		 644 return 1;
645}
646
a21ae81d
FB		 647/* fill */
648
a5082316 649static int cirrus_bitblt_solidfill(CirrusVGAState *s, int blt_rop)
a21ae81d 650{
a5082316 651 cirrus_fill_t rop_func;
a21ae81d 652
b2eb849d
AJ		 653 if (BLTUNSAFE(s))
654 return 0;
a5082316 655 rop_func = cirrus_fill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
4e12cd94 656 rop_func(s, s->vga.vram_ptr + (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
a5082316
FB		 657 s->cirrus_blt_dstpitch,
658 s->cirrus_blt_width, s->cirrus_blt_height);
a21ae81d
FB		 659 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
660 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
661 s->cirrus_blt_height);
662 cirrus_bitblt_reset(s);
663 return 1;
664}
665
e6e5ad80
FB		 666/***************************************
667 *
668 * bitblt (video-to-video)
669 *
670 ***************************************/
671
672static int cirrus_bitblt_videotovideo_patterncopy(CirrusVGAState * s)
673{
674 return cirrus_bitblt_common_patterncopy(s,
4e12cd94 675 s->vga.vram_ptr + ((s->cirrus_blt_srcaddr & ~7) &
b2eb849d 676 s->cirrus_addr_mask));
e6e5ad80
FB		 677}
678
24236869 679static void cirrus_do_copy(CirrusVGAState *s, int dst, int src, int w, int h)
e6e5ad80 680{
78935c4a
AJ		 681 int sx = 0, sy = 0;
682 int dx = 0, dy = 0;
683 int depth = 0;
24236869
FB		 684 int notify = 0;
685
92d675d1
AJ		 686 /* make sure to only copy if it's a plain copy ROP */
687 if (*s->cirrus_rop == cirrus_bitblt_rop_fwd_src ||
688 *s->cirrus_rop == cirrus_bitblt_rop_bkwd_src) {
24236869 689
92d675d1
AJ		 690 int width, height;
691
692 depth = s->vga.get_bpp(&s->vga) / 8;
693 s->vga.get_resolution(&s->vga, &width, &height);
694
695 /* extra x, y */
696 sx = (src % ABS(s->cirrus_blt_srcpitch)) / depth;
697 sy = (src / ABS(s->cirrus_blt_srcpitch));
698 dx = (dst % ABS(s->cirrus_blt_dstpitch)) / depth;
699 dy = (dst / ABS(s->cirrus_blt_dstpitch));
24236869 700
92d675d1
AJ		 701 /* normalize width */
702 w /= depth;
24236869 703
92d675d1
AJ		 704 /* if we're doing a backward copy, we have to adjust
705 our x/y to be the upper left corner (instead of the lower
706 right corner) */
707 if (s->cirrus_blt_dstpitch < 0) {
708 sx -= (s->cirrus_blt_width / depth) - 1;
709 dx -= (s->cirrus_blt_width / depth) - 1;
710 sy -= s->cirrus_blt_height - 1;
711 dy -= s->cirrus_blt_height - 1;
712 }
713
714 /* are we in the visible portion of memory? */
715 if (sx >= 0 && sy >= 0 && dx >= 0 && dy >= 0 &&
716 (sx + w) <= width && (sy + h) <= height &&
717 (dx + w) <= width && (dy + h) <= height) {
718 notify = 1;
719 }
720 }
24236869
FB		 721
722 /* we have to flush all pending changes so that the copy
723 is generated at the appropriate moment in time */
724 if (notify)
725 vga_hw_update();
726
4e12cd94 727 (*s->cirrus_rop) (s, s->vga.vram_ptr +
b2eb849d 728 (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
4e12cd94 729 s->vga.vram_ptr +
b2eb849d 730 (s->cirrus_blt_srcaddr & s->cirrus_addr_mask),
e6e5ad80
FB		 731 s->cirrus_blt_dstpitch, s->cirrus_blt_srcpitch,
732 s->cirrus_blt_width, s->cirrus_blt_height);
24236869
FB		 733
734 if (notify)
4e12cd94 735 qemu_console_copy(s->vga.ds,
38334f76
AZ		 736 sx, sy, dx, dy,
737 s->cirrus_blt_width / depth,
738 s->cirrus_blt_height);
24236869
FB		 739
740 /* we don't have to notify the display that this portion has
38334f76 741 changed since qemu_console_copy implies this */
24236869 742
31c05501
AL		 743 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
744 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
745 s->cirrus_blt_height);
24236869
FB		 746}
747
748static int cirrus_bitblt_videotovideo_copy(CirrusVGAState * s)
749{
65d35a09
AJ		 750 if (BLTUNSAFE(s))
751 return 0;
752
4e12cd94
AK		 753 cirrus_do_copy(s, s->cirrus_blt_dstaddr - s->vga.start_addr,
754 s->cirrus_blt_srcaddr - s->vga.start_addr,
7d957bd8 755 s->cirrus_blt_width, s->cirrus_blt_height);
24236869 756
e6e5ad80
FB		 757 return 1;
758}
759
760/***************************************
761 *
762 * bitblt (cpu-to-video)
763 *
764 ***************************************/
765
e6e5ad80
FB		 766static void cirrus_bitblt_cputovideo_next(CirrusVGAState * s)
767{
768 int copy_count;
a5082316 769 uint8_t *end_ptr;
3b46e624 770
e6e5ad80 771 if (s->cirrus_srccounter > 0) {
a5082316
FB		 772 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
773 cirrus_bitblt_common_patterncopy(s, s->cirrus_bltbuf);
774 the_end:
775 s->cirrus_srccounter = 0;
776 cirrus_bitblt_reset(s);
777 } else {
778 /* at least one scan line */
779 do {
4e12cd94 780 (*s->cirrus_rop)(s, s->vga.vram_ptr +
b2eb849d
AJ		 781 (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
782 s->cirrus_bltbuf, 0, 0, s->cirrus_blt_width, 1);
a5082316
FB		 783 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr, 0,
784 s->cirrus_blt_width, 1);
785 s->cirrus_blt_dstaddr += s->cirrus_blt_dstpitch;
786 s->cirrus_srccounter -= s->cirrus_blt_srcpitch;
787 if (s->cirrus_srccounter <= 0)
788 goto the_end;
789 /* more bytes than needed can be transfered because of
790 word alignment, so we keep them for the next line */
791 /* XXX: keep alignment to speed up transfer */
792 end_ptr = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
793 copy_count = s->cirrus_srcptr_end - end_ptr;
794 memmove(s->cirrus_bltbuf, end_ptr, copy_count);
795 s->cirrus_srcptr = s->cirrus_bltbuf + copy_count;
796 s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
797 } while (s->cirrus_srcptr >= s->cirrus_srcptr_end);
798 }
e6e5ad80
FB		 799 }
800}
801
802/***************************************
803 *
804 * bitblt wrapper
805 *
806 ***************************************/
807
808static void cirrus_bitblt_reset(CirrusVGAState * s)
809{
f8b237af
AL		 810 int need_update;
811
4e12cd94 812 s->vga.gr[0x31] &=
e6e5ad80 813 ~(CIRRUS_BLT_START | CIRRUS_BLT_BUSY | CIRRUS_BLT_FIFOUSED);
f8b237af
AL		 814 need_update = s->cirrus_srcptr != &s->cirrus_bltbuf[0]
815 || s->cirrus_srcptr_end != &s->cirrus_bltbuf[0];
e6e5ad80
FB		 816 s->cirrus_srcptr = &s->cirrus_bltbuf[0];
817 s->cirrus_srcptr_end = &s->cirrus_bltbuf[0];
818 s->cirrus_srccounter = 0;
f8b237af
AL		 819 if (!need_update)
820 return;
8926b517 821 cirrus_update_memory_access(s);
e6e5ad80
FB		 822}
823
824static int cirrus_bitblt_cputovideo(CirrusVGAState * s)
825{
a5082316
FB		 826 int w;
827
e6e5ad80
FB		 828 s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_MEMSYSSRC;
829 s->cirrus_srcptr = &s->cirrus_bltbuf[0];
830 s->cirrus_srcptr_end = &s->cirrus_bltbuf[0];
831
832 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
833 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
a5082316 834 s->cirrus_blt_srcpitch = 8;
e6e5ad80 835 } else {
b30d4608 836 /* XXX: check for 24 bpp */
a5082316 837 s->cirrus_blt_srcpitch = 8 * 8 * s->cirrus_blt_pixelwidth;
e6e5ad80 838 }
a5082316 839 s->cirrus_srccounter = s->cirrus_blt_srcpitch;
e6e5ad80
FB		 840 } else {
841 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
a5082316 842 w = s->cirrus_blt_width / s->cirrus_blt_pixelwidth;
5fafdf24 843 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_DWORDGRANULARITY)
a5082316
FB		 844 s->cirrus_blt_srcpitch = ((w + 31) >> 5);
845 else
846 s->cirrus_blt_srcpitch = ((w + 7) >> 3);
e6e5ad80 847 } else {
c9c0eae8
FB		 848 /* always align input size to 32 bits */
849 s->cirrus_blt_srcpitch = (s->cirrus_blt_width + 3) & ~3;
e6e5ad80 850 }
a5082316 851 s->cirrus_srccounter = s->cirrus_blt_srcpitch * s->cirrus_blt_height;
e6e5ad80 852 }
a5082316
FB		 853 s->cirrus_srcptr = s->cirrus_bltbuf;
854 s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
8926b517 855 cirrus_update_memory_access(s);
e6e5ad80
FB		 856 return 1;
857}
858
859static int cirrus_bitblt_videotocpu(CirrusVGAState * s)
860{
861 /* XXX */
a5082316 862#ifdef DEBUG_BITBLT
e6e5ad80
FB		 863 printf("cirrus: bitblt (video to cpu) is not implemented yet\n");
864#endif
865 return 0;
866}
867
868static int cirrus_bitblt_videotovideo(CirrusVGAState * s)
869{
870 int ret;
871
872 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
873 ret = cirrus_bitblt_videotovideo_patterncopy(s);
874 } else {
875 ret = cirrus_bitblt_videotovideo_copy(s);
876 }
e6e5ad80
FB		 877 if (ret)
878 cirrus_bitblt_reset(s);
879 return ret;
880}
881
882static void cirrus_bitblt_start(CirrusVGAState * s)
883{
884 uint8_t blt_rop;
885
4e12cd94 886 s->vga.gr[0x31] |= CIRRUS_BLT_BUSY;
a5082316 887
4e12cd94
AK		 888 s->cirrus_blt_width = (s->vga.gr[0x20] | (s->vga.gr[0x21] << 8)) + 1;
889 s->cirrus_blt_height = (s->vga.gr[0x22] | (s->vga.gr[0x23] << 8)) + 1;
890 s->cirrus_blt_dstpitch = (s->vga.gr[0x24] | (s->vga.gr[0x25] << 8));
891 s->cirrus_blt_srcpitch = (s->vga.gr[0x26] | (s->vga.gr[0x27] << 8));
e6e5ad80 892 s->cirrus_blt_dstaddr =
4e12cd94 893 (s->vga.gr[0x28] | (s->vga.gr[0x29] << 8) | (s->vga.gr[0x2a] << 16));
e6e5ad80 894 s->cirrus_blt_srcaddr =
4e12cd94
AK		 895 (s->vga.gr[0x2c] | (s->vga.gr[0x2d] << 8) | (s->vga.gr[0x2e] << 16));
896 s->cirrus_blt_mode = s->vga.gr[0x30];
897 s->cirrus_blt_modeext = s->vga.gr[0x33];
898 blt_rop = s->vga.gr[0x32];
e6e5ad80 899
a21ae81d 900#ifdef DEBUG_BITBLT
0b74ed78 901 printf("rop=0x%02x mode=0x%02x modeext=0x%02x w=%d h=%d dpitch=%d spitch=%d daddr=0x%08x saddr=0x%08x writemask=0x%02x\n",
5fafdf24 902 blt_rop,
a21ae81d 903 s->cirrus_blt_mode,
a5082316 904 s->cirrus_blt_modeext,
a21ae81d
FB		 905 s->cirrus_blt_width,
906 s->cirrus_blt_height,
907 s->cirrus_blt_dstpitch,
908 s->cirrus_blt_srcpitch,
909 s->cirrus_blt_dstaddr,
a5082316 910 s->cirrus_blt_srcaddr,
4e12cd94 911 s->vga.gr[0x2f]);
a21ae81d
FB		 912#endif
913
e6e5ad80
FB		 914 switch (s->cirrus_blt_mode & CIRRUS_BLTMODE_PIXELWIDTHMASK) {
915 case CIRRUS_BLTMODE_PIXELWIDTH8:
916 s->cirrus_blt_pixelwidth = 1;
917 break;
918 case CIRRUS_BLTMODE_PIXELWIDTH16:
919 s->cirrus_blt_pixelwidth = 2;
920 break;
921 case CIRRUS_BLTMODE_PIXELWIDTH24:
922 s->cirrus_blt_pixelwidth = 3;
923 break;
924 case CIRRUS_BLTMODE_PIXELWIDTH32:
925 s->cirrus_blt_pixelwidth = 4;
926 break;
927 default:
a5082316 928#ifdef DEBUG_BITBLT
e6e5ad80
FB		 929 printf("cirrus: bitblt - pixel width is unknown\n");
930#endif
931 goto bitblt_ignore;
932 }
933 s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_PIXELWIDTHMASK;
934
935 if ((s->
936 cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSSRC |
937 CIRRUS_BLTMODE_MEMSYSDEST))
938 == (CIRRUS_BLTMODE_MEMSYSSRC | CIRRUS_BLTMODE_MEMSYSDEST)) {
a5082316 939#ifdef DEBUG_BITBLT
e6e5ad80
FB		 940 printf("cirrus: bitblt - memory-to-memory copy is requested\n");
941#endif
942 goto bitblt_ignore;
943 }
944
a5082316 945 if ((s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_SOLIDFILL) &&
5fafdf24 946 (s->cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSDEST |
a21ae81d 947 CIRRUS_BLTMODE_TRANSPARENTCOMP |
5fafdf24
TS		 948 CIRRUS_BLTMODE_PATTERNCOPY |
949 CIRRUS_BLTMODE_COLOREXPAND)) ==
a21ae81d 950 (CIRRUS_BLTMODE_PATTERNCOPY | CIRRUS_BLTMODE_COLOREXPAND)) {
a5082316
FB		 951 cirrus_bitblt_fgcol(s);
952 cirrus_bitblt_solidfill(s, blt_rop);
e6e5ad80 953 } else {
5fafdf24
TS		 954 if ((s->cirrus_blt_mode & (CIRRUS_BLTMODE_COLOREXPAND |
955 CIRRUS_BLTMODE_PATTERNCOPY)) ==
a5082316
FB		 956 CIRRUS_BLTMODE_COLOREXPAND) {
957
958 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
b30d4608 959 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV)
4c8732d7 960 cirrus_bitblt_bgcol(s);
b30d4608 961 else
4c8732d7 962 cirrus_bitblt_fgcol(s);
b30d4608 963 s->cirrus_rop = cirrus_colorexpand_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
a5082316
FB		 964 } else {
965 cirrus_bitblt_fgcol(s);
966 cirrus_bitblt_bgcol(s);
967 s->cirrus_rop = cirrus_colorexpand[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
968 }
e69390ce 969 } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
b30d4608
FB		 970 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
971 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
972 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV)
973 cirrus_bitblt_bgcol(s);
974 else
975 cirrus_bitblt_fgcol(s);
976 s->cirrus_rop = cirrus_colorexpand_pattern_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
977 } else {
978 cirrus_bitblt_fgcol(s);
979 cirrus_bitblt_bgcol(s);
980 s->cirrus_rop = cirrus_colorexpand_pattern[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
981 }
982 } else {
983 s->cirrus_rop = cirrus_patternfill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
984 }
a21ae81d 985 } else {
96cf2df8
TS		 986 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
987 if (s->cirrus_blt_pixelwidth > 2) {
988 printf("src transparent without colorexpand must be 8bpp or 16bpp\n");
989 goto bitblt_ignore;
990 }
991 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) {
992 s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch;
993 s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch;
994 s->cirrus_rop = cirrus_bkwd_transp_rop[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
995 } else {
996 s->cirrus_rop = cirrus_fwd_transp_rop[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
997 }
998 } else {
999 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) {
1000 s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch;
1001 s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch;
1002 s->cirrus_rop = cirrus_bkwd_rop[rop_to_index[blt_rop]];
1003 } else {
1004 s->cirrus_rop = cirrus_fwd_rop[rop_to_index[blt_rop]];
1005 }
1006 }
1007 }
a21ae81d
FB		 1008 // setup bitblt engine.
1009 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSSRC) {
1010 if (!cirrus_bitblt_cputovideo(s))
1011 goto bitblt_ignore;
1012 } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSDEST) {
1013 if (!cirrus_bitblt_videotocpu(s))
1014 goto bitblt_ignore;
1015 } else {
1016 if (!cirrus_bitblt_videotovideo(s))
1017 goto bitblt_ignore;
1018 }
e6e5ad80 1019 }
e6e5ad80
FB		 1020 return;
1021 bitblt_ignore:;
1022 cirrus_bitblt_reset(s);
1023}
1024
1025static void cirrus_write_bitblt(CirrusVGAState * s, unsigned reg_value)
1026{
1027 unsigned old_value;
1028
4e12cd94
AK		 1029 old_value = s->vga.gr[0x31];
1030 s->vga.gr[0x31] = reg_value;
e6e5ad80
FB		 1031
1032 if (((old_value & CIRRUS_BLT_RESET) != 0) &&
1033 ((reg_value & CIRRUS_BLT_RESET) == 0)) {
1034 cirrus_bitblt_reset(s);
1035 } else if (((old_value & CIRRUS_BLT_START) == 0) &&
1036 ((reg_value & CIRRUS_BLT_START) != 0)) {
e6e5ad80
FB		 1037 cirrus_bitblt_start(s);
1038 }
1039}
1040
1041
1042/***************************************
1043 *
1044 * basic parameters
1045 *
1046 ***************************************/
1047
a4a2f59c 1048static void cirrus_get_offsets(VGACommonState *s1,
83acc96b
FB		 1049 uint32_t *pline_offset,
1050 uint32_t *pstart_addr,
1051 uint32_t *pline_compare)
e6e5ad80 1052{
4e12cd94 1053 CirrusVGAState * s = container_of(s1, CirrusVGAState, vga);
83acc96b 1054 uint32_t start_addr, line_offset, line_compare;
e6e5ad80 1055
4e12cd94
AK		 1056 line_offset = s->vga.cr[0x13]
1057 | ((s->vga.cr[0x1b] & 0x10) << 4);
e6e5ad80
FB		 1058 line_offset <<= 3;
1059 *pline_offset = line_offset;
1060
4e12cd94
AK		 1061 start_addr = (s->vga.cr[0x0c] << 8)
1062 | s->vga.cr[0x0d]
1063 | ((s->vga.cr[0x1b] & 0x01) << 16)
1064 | ((s->vga.cr[0x1b] & 0x0c) << 15)
1065 | ((s->vga.cr[0x1d] & 0x80) << 12);
e6e5ad80 1066 *pstart_addr = start_addr;
83acc96b 1067
4e12cd94
AK		 1068 line_compare = s->vga.cr[0x18] |
1069 ((s->vga.cr[0x07] & 0x10) << 4) |
1070 ((s->vga.cr[0x09] & 0x40) << 3);
83acc96b 1071 *pline_compare = line_compare;
e6e5ad80
FB		 1072}
1073
1074static uint32_t cirrus_get_bpp16_depth(CirrusVGAState * s)
1075{
1076 uint32_t ret = 16;
1077
1078 switch (s->cirrus_hidden_dac_data & 0xf) {
1079 case 0:
1080 ret = 15;
1081 break; /* Sierra HiColor */
1082 case 1:
1083 ret = 16;
1084 break; /* XGA HiColor */
1085 default:
1086#ifdef DEBUG_CIRRUS
1087 printf("cirrus: invalid DAC value %x in 16bpp\n",
1088 (s->cirrus_hidden_dac_data & 0xf));
1089#endif
1090 ret = 15; /* XXX */
1091 break;
1092 }
1093 return ret;
1094}
1095
a4a2f59c 1096static int cirrus_get_bpp(VGACommonState *s1)
e6e5ad80 1097{
4e12cd94 1098 CirrusVGAState * s = container_of(s1, CirrusVGAState, vga);
e6e5ad80
FB		 1099 uint32_t ret = 8;
1100
4e12cd94 1101 if ((s->vga.sr[0x07] & 0x01) != 0) {
e6e5ad80 1102 /* Cirrus SVGA */
4e12cd94 1103 switch (s->vga.sr[0x07] & CIRRUS_SR7_BPP_MASK) {
e6e5ad80
FB		 1104 case CIRRUS_SR7_BPP_8:
1105 ret = 8;
1106 break;
1107 case CIRRUS_SR7_BPP_16_DOUBLEVCLK:
1108 ret = cirrus_get_bpp16_depth(s);
1109 break;
1110 case CIRRUS_SR7_BPP_24:
1111 ret = 24;
1112 break;
1113 case CIRRUS_SR7_BPP_16:
1114 ret = cirrus_get_bpp16_depth(s);
1115 break;
1116 case CIRRUS_SR7_BPP_32:
1117 ret = 32;
1118 break;
1119 default:
1120#ifdef DEBUG_CIRRUS
4e12cd94 1121 printf("cirrus: unknown bpp - sr7=%x\n", s->vga.sr[0x7]);
e6e5ad80
FB		 1122#endif
1123 ret = 8;
1124 break;
1125 }
1126 } else {
1127 /* VGA */
aeb3c85f 1128 ret = 0;
e6e5ad80
FB		 1129 }
1130
1131 return ret;
1132}
1133
a4a2f59c 1134static void cirrus_get_resolution(VGACommonState *s, int *pwidth, int *pheight)
78e127ef
FB		 1135{
1136 int width, height;
3b46e624 1137
78e127ef 1138 width = (s->cr[0x01] + 1) * 8;
5fafdf24
TS		 1139 height = s->cr[0x12] |
1140 ((s->cr[0x07] & 0x02) << 7) |
78e127ef
FB		 1141 ((s->cr[0x07] & 0x40) << 3);
1142 height = (height + 1);
1143 /* interlace support */
1144 if (s->cr[0x1a] & 0x01)
1145 height = height * 2;
1146 *pwidth = width;
1147 *pheight = height;
1148}
1149
e6e5ad80
FB		 1150/***************************************
1151 *
1152 * bank memory
1153 *
1154 ***************************************/
1155
1156static void cirrus_update_bank_ptr(CirrusVGAState * s, unsigned bank_index)
1157{
1158 unsigned offset;
1159 unsigned limit;
1160
4e12cd94
AK		 1161 if ((s->vga.gr[0x0b] & 0x01) != 0) /* dual bank */
1162 offset = s->vga.gr[0x09 + bank_index];
e6e5ad80 1163 else /* single bank */
4e12cd94 1164 offset = s->vga.gr[0x09];
e6e5ad80 1165
4e12cd94 1166 if ((s->vga.gr[0x0b] & 0x20) != 0)
e6e5ad80
FB		 1167 offset <<= 14;
1168 else
1169 offset <<= 12;
1170
e3a4e4b6 1171 if (s->real_vram_size <= offset)
e6e5ad80
FB		 1172 limit = 0;
1173 else
e3a4e4b6 1174 limit = s->real_vram_size - offset;
e6e5ad80 1175
4e12cd94 1176 if (((s->vga.gr[0x0b] & 0x01) == 0) && (bank_index != 0)) {
e6e5ad80
FB		 1177 if (limit > 0x8000) {
1178 offset += 0x8000;
1179 limit -= 0x8000;
1180 } else {
1181 limit = 0;
1182 }
1183 }
1184
1185 if (limit > 0) {
1186 s->cirrus_bank_base[bank_index] = offset;
1187 s->cirrus_bank_limit[bank_index] = limit;
1188 } else {
1189 s->cirrus_bank_base[bank_index] = 0;
1190 s->cirrus_bank_limit[bank_index] = 0;
1191 }
1192}
1193
1194/***************************************
1195 *
1196 * I/O access between 0x3c4-0x3c5
1197 *
1198 ***************************************/
1199
8a82c322 1200static int cirrus_vga_read_sr(CirrusVGAState * s)
e6e5ad80 1201{
8a82c322 1202 switch (s->vga.sr_index) {
e6e5ad80
FB		 1203 case 0x00: // Standard VGA
1204 case 0x01: // Standard VGA
1205 case 0x02: // Standard VGA
1206 case 0x03: // Standard VGA
1207 case 0x04: // Standard VGA
8a82c322 1208 return s->vga.sr[s->vga.sr_index];
e6e5ad80 1209 case 0x06: // Unlock Cirrus extensions
8a82c322 1210 return s->vga.sr[s->vga.sr_index];
e6e5ad80
FB		 1211 case 0x10:
1212 case 0x30:
1213 case 0x50:
1214 case 0x70: // Graphics Cursor X
1215 case 0x90:
1216 case 0xb0:
1217 case 0xd0:
1218 case 0xf0: // Graphics Cursor X
8a82c322 1219 return s->vga.sr[0x10];
e6e5ad80
FB		 1220 case 0x11:
1221 case 0x31:
1222 case 0x51:
1223 case 0x71: // Graphics Cursor Y
1224 case 0x91:
1225 case 0xb1:
1226 case 0xd1:
a5082316 1227 case 0xf1: // Graphics Cursor Y
8a82c322 1228 return s->vga.sr[0x11];
aeb3c85f
FB		 1229 case 0x05: // ???
1230 case 0x07: // Extended Sequencer Mode
1231 case 0x08: // EEPROM Control
1232 case 0x09: // Scratch Register 0
1233 case 0x0a: // Scratch Register 1
1234 case 0x0b: // VCLK 0
1235 case 0x0c: // VCLK 1
1236 case 0x0d: // VCLK 2
1237 case 0x0e: // VCLK 3
1238 case 0x0f: // DRAM Control
e6e5ad80
FB		 1239 case 0x12: // Graphics Cursor Attribute
1240 case 0x13: // Graphics Cursor Pattern Address
1241 case 0x14: // Scratch Register 2
1242 case 0x15: // Scratch Register 3
1243 case 0x16: // Performance Tuning Register
1244 case 0x17: // Configuration Readback and Extended Control
1245 case 0x18: // Signature Generator Control
1246 case 0x19: // Signal Generator Result
1247 case 0x1a: // Signal Generator Result
1248 case 0x1b: // VCLK 0 Denominator & Post
1249 case 0x1c: // VCLK 1 Denominator & Post
1250 case 0x1d: // VCLK 2 Denominator & Post
1251 case 0x1e: // VCLK 3 Denominator & Post
1252 case 0x1f: // BIOS Write Enable and MCLK select
1253#ifdef DEBUG_CIRRUS
8a82c322 1254 printf("cirrus: handled inport sr_index %02x\n", s->vga.sr_index);
e6e5ad80 1255#endif
8a82c322 1256 return s->vga.sr[s->vga.sr_index];
e6e5ad80
FB		 1257 default:
1258#ifdef DEBUG_CIRRUS
8a82c322 1259 printf("cirrus: inport sr_index %02x\n", s->vga.sr_index);
e6e5ad80 1260#endif
8a82c322 1261 return 0xff;
e6e5ad80
FB		 1262 break;
1263 }
e6e5ad80
FB		 1264}
1265
31c63201 1266static void cirrus_vga_write_sr(CirrusVGAState * s, uint32_t val)
e6e5ad80 1267{
31c63201 1268 switch (s->vga.sr_index) {
e6e5ad80
FB		 1269 case 0x00: // Standard VGA
1270 case 0x01: // Standard VGA
1271 case 0x02: // Standard VGA
1272 case 0x03: // Standard VGA
1273 case 0x04: // Standard VGA
31c63201
JQ		 1274 s->vga.sr[s->vga.sr_index] = val & sr_mask[s->vga.sr_index];
1275 if (s->vga.sr_index == 1)
1276 s->vga.update_retrace_info(&s->vga);
1277 break;
e6e5ad80 1278 case 0x06: // Unlock Cirrus extensions
31c63201
JQ		 1279 val &= 0x17;
1280 if (val == 0x12) {
1281 s->vga.sr[s->vga.sr_index] = 0x12;
e6e5ad80 1282 } else {
31c63201 1283 s->vga.sr[s->vga.sr_index] = 0x0f;
e6e5ad80
FB		 1284 }
1285 break;
1286 case 0x10:
1287 case 0x30:
1288 case 0x50:
1289 case 0x70: // Graphics Cursor X
1290 case 0x90:
1291 case 0xb0:
1292 case 0xd0:
1293 case 0xf0: // Graphics Cursor X
31c63201
JQ		 1294 s->vga.sr[0x10] = val;
1295 s->hw_cursor_x = (val << 3) | (s->vga.sr_index >> 5);
e6e5ad80
FB		 1296 break;
1297 case 0x11:
1298 case 0x31:
1299 case 0x51:
1300 case 0x71: // Graphics Cursor Y
1301 case 0x91:
1302 case 0xb1:
1303 case 0xd1:
1304 case 0xf1: // Graphics Cursor Y
31c63201
JQ		 1305 s->vga.sr[0x11] = val;
1306 s->hw_cursor_y = (val << 3) | (s->vga.sr_index >> 5);
e6e5ad80
FB		 1307 break;
1308 case 0x07: // Extended Sequencer Mode
2bec46dc 1309 cirrus_update_memory_access(s);
e6e5ad80
FB		 1310 case 0x08: // EEPROM Control
1311 case 0x09: // Scratch Register 0
1312 case 0x0a: // Scratch Register 1
1313 case 0x0b: // VCLK 0
1314 case 0x0c: // VCLK 1
1315 case 0x0d: // VCLK 2
1316 case 0x0e: // VCLK 3
1317 case 0x0f: // DRAM Control
1318 case 0x12: // Graphics Cursor Attribute
1319 case 0x13: // Graphics Cursor Pattern Address
1320 case 0x14: // Scratch Register 2
1321 case 0x15: // Scratch Register 3
1322 case 0x16: // Performance Tuning Register
e6e5ad80
FB		 1323 case 0x18: // Signature Generator Control
1324 case 0x19: // Signature Generator Result
1325 case 0x1a: // Signature Generator Result
1326 case 0x1b: // VCLK 0 Denominator & Post
1327 case 0x1c: // VCLK 1 Denominator & Post
1328 case 0x1d: // VCLK 2 Denominator & Post
1329 case 0x1e: // VCLK 3 Denominator & Post
1330 case 0x1f: // BIOS Write Enable and MCLK select
31c63201 1331 s->vga.sr[s->vga.sr_index] = val;
e6e5ad80
FB		 1332#ifdef DEBUG_CIRRUS
1333 printf("cirrus: handled outport sr_index %02x, sr_value %02x\n",
31c63201 1334 s->vga.sr_index, val);
e6e5ad80
FB		 1335#endif
1336 break;
8926b517 1337 case 0x17: // Configuration Readback and Extended Control
31c63201
JQ		 1338 s->vga.sr[s->vga.sr_index] = (s->vga.sr[s->vga.sr_index] & 0x38)
1339 | (val & 0xc7);
8926b517
FB		 1340 cirrus_update_memory_access(s);
1341 break;
e6e5ad80
FB		 1342 default:
1343#ifdef DEBUG_CIRRUS
31c63201
JQ		 1344 printf("cirrus: outport sr_index %02x, sr_value %02x\n",
1345 s->vga.sr_index, val);
e6e5ad80
FB		 1346#endif
1347 break;
1348 }
e6e5ad80
FB		 1349}
1350
1351/***************************************
1352 *
1353 * I/O access at 0x3c6
1354 *
1355 ***************************************/
1356
957c9db5 1357static int cirrus_read_hidden_dac(CirrusVGAState * s)
e6e5ad80 1358{
a21ae81d 1359 if (++s->cirrus_hidden_dac_lockindex == 5) {
957c9db5
JQ		 1360 s->cirrus_hidden_dac_lockindex = 0;
1361 return s->cirrus_hidden_dac_data;
e6e5ad80 1362 }
957c9db5 1363 return 0xff;
e6e5ad80
FB		 1364}
1365
1366static void cirrus_write_hidden_dac(CirrusVGAState * s, int reg_value)
1367{
1368 if (s->cirrus_hidden_dac_lockindex == 4) {
1369 s->cirrus_hidden_dac_data = reg_value;
a21ae81d 1370#if defined(DEBUG_CIRRUS)
e6e5ad80
FB		 1371 printf("cirrus: outport hidden DAC, value %02x\n", reg_value);
1372#endif
1373 }
1374 s->cirrus_hidden_dac_lockindex = 0;
1375}
1376
1377/***************************************
1378 *
1379 * I/O access at 0x3c9
1380 *
1381 ***************************************/
1382
5deaeee3 1383static int cirrus_vga_read_palette(CirrusVGAState * s)
e6e5ad80 1384{
5deaeee3
JQ		 1385 int val;
1386
1387 if ((s->vga.sr[0x12] & CIRRUS_CURSOR_HIDDENPEL)) {
1388 val = s->cirrus_hidden_palette[(s->vga.dac_read_index & 0x0f) * 3 +
1389 s->vga.dac_sub_index];
1390 } else {
1391 val = s->vga.palette[s->vga.dac_read_index * 3 + s->vga.dac_sub_index];
1392 }
4e12cd94
AK		 1393 if (++s->vga.dac_sub_index == 3) {
1394 s->vga.dac_sub_index = 0;
1395 s->vga.dac_read_index++;
e6e5ad80 1396 }
5deaeee3 1397 return val;
e6e5ad80
FB		 1398}
1399
86948bb1 1400static void cirrus_vga_write_palette(CirrusVGAState * s, int reg_value)
e6e5ad80 1401{
4e12cd94
AK		 1402 s->vga.dac_cache[s->vga.dac_sub_index] = reg_value;
1403 if (++s->vga.dac_sub_index == 3) {
86948bb1
JQ		 1404 if ((s->vga.sr[0x12] & CIRRUS_CURSOR_HIDDENPEL)) {
1405 memcpy(&s->cirrus_hidden_palette[(s->vga.dac_write_index & 0x0f) * 3],
1406 s->vga.dac_cache, 3);
1407 } else {
1408 memcpy(&s->vga.palette[s->vga.dac_write_index * 3], s->vga.dac_cache, 3);
1409 }
a5082316 1410 /* XXX update cursor */
4e12cd94
AK		 1411 s->vga.dac_sub_index = 0;
1412 s->vga.dac_write_index++;
e6e5ad80 1413 }
e6e5ad80
FB		 1414}
1415
1416/***************************************
1417 *
1418 * I/O access between 0x3ce-0x3cf
1419 *
1420 ***************************************/
1421
f705db9d 1422static int cirrus_vga_read_gr(CirrusVGAState * s, unsigned reg_index)
e6e5ad80
FB		 1423{
1424 switch (reg_index) {
aeb3c85f 1425 case 0x00: // Standard VGA, BGCOLOR 0x000000ff
f705db9d 1426 return s->cirrus_shadow_gr0;
aeb3c85f 1427 case 0x01: // Standard VGA, FGCOLOR 0x000000ff
f705db9d 1428 return s->cirrus_shadow_gr1;
e6e5ad80
FB		 1429 case 0x02: // Standard VGA
1430 case 0x03: // Standard VGA
1431 case 0x04: // Standard VGA
1432 case 0x06: // Standard VGA
1433 case 0x07: // Standard VGA
1434 case 0x08: // Standard VGA
f705db9d 1435 return s->vga.gr[s->vga.gr_index];
e6e5ad80
FB		 1436 case 0x05: // Standard VGA, Cirrus extended mode
1437 default:
1438 break;
1439 }
1440
1441 if (reg_index < 0x3a) {
f705db9d 1442 return s->vga.gr[reg_index];
e6e5ad80
FB		 1443 } else {
1444#ifdef DEBUG_CIRRUS
1445 printf("cirrus: inport gr_index %02x\n", reg_index);
1446#endif
f705db9d 1447 return 0xff;
e6e5ad80 1448 }
e6e5ad80
FB		 1449}
1450
22286bc6
JQ		 1451static void
1452cirrus_vga_write_gr(CirrusVGAState * s, unsigned reg_index, int reg_value)
e6e5ad80 1453{
a5082316
FB		 1454#if defined(DEBUG_BITBLT) && 0
1455 printf("gr%02x: %02x\n", reg_index, reg_value);
1456#endif
e6e5ad80
FB		 1457 switch (reg_index) {
1458 case 0x00: // Standard VGA, BGCOLOR 0x000000ff
f22f5b07 1459 s->vga.gr[reg_index] = reg_value & gr_mask[reg_index];
aeb3c85f 1460 s->cirrus_shadow_gr0 = reg_value;
22286bc6 1461 break;
e6e5ad80 1462 case 0x01: // Standard VGA, FGCOLOR 0x000000ff
f22f5b07 1463 s->vga.gr[reg_index] = reg_value & gr_mask[reg_index];
aeb3c85f 1464 s->cirrus_shadow_gr1 = reg_value;
22286bc6 1465 break;
e6e5ad80
FB		 1466 case 0x02: // Standard VGA
1467 case 0x03: // Standard VGA
1468 case 0x04: // Standard VGA
1469 case 0x06: // Standard VGA
1470 case 0x07: // Standard VGA
1471 case 0x08: // Standard VGA
22286bc6
JQ		 1472 s->vga.gr[reg_index] = reg_value & gr_mask[reg_index];
1473 break;
e6e5ad80 1474 case 0x05: // Standard VGA, Cirrus extended mode
4e12cd94 1475 s->vga.gr[reg_index] = reg_value & 0x7f;
8926b517 1476 cirrus_update_memory_access(s);
e6e5ad80
FB		 1477 break;
1478 case 0x09: // bank offset #0
1479 case 0x0A: // bank offset #1
4e12cd94 1480 s->vga.gr[reg_index] = reg_value;
8926b517
FB		 1481 cirrus_update_bank_ptr(s, 0);
1482 cirrus_update_bank_ptr(s, 1);
2bec46dc 1483 cirrus_update_memory_access(s);
8926b517 1484 break;
e6e5ad80 1485 case 0x0B:
4e12cd94 1486 s->vga.gr[reg_index] = reg_value;
e6e5ad80
FB		 1487 cirrus_update_bank_ptr(s, 0);
1488 cirrus_update_bank_ptr(s, 1);
8926b517 1489 cirrus_update_memory_access(s);
e6e5ad80
FB		 1490 break;
1491 case 0x10: // BGCOLOR 0x0000ff00
1492 case 0x11: // FGCOLOR 0x0000ff00
1493 case 0x12: // BGCOLOR 0x00ff0000
1494 case 0x13: // FGCOLOR 0x00ff0000
1495 case 0x14: // BGCOLOR 0xff000000
1496 case 0x15: // FGCOLOR 0xff000000
1497 case 0x20: // BLT WIDTH 0x0000ff
1498 case 0x22: // BLT HEIGHT 0x0000ff
1499 case 0x24: // BLT DEST PITCH 0x0000ff
1500 case 0x26: // BLT SRC PITCH 0x0000ff
1501 case 0x28: // BLT DEST ADDR 0x0000ff
1502 case 0x29: // BLT DEST ADDR 0x00ff00
1503 case 0x2c: // BLT SRC ADDR 0x0000ff
1504 case 0x2d: // BLT SRC ADDR 0x00ff00
a5082316 1505 case 0x2f: // BLT WRITEMASK
e6e5ad80
FB		 1506 case 0x30: // BLT MODE
1507 case 0x32: // RASTER OP
a21ae81d 1508 case 0x33: // BLT MODEEXT
e6e5ad80
FB		 1509 case 0x34: // BLT TRANSPARENT COLOR 0x00ff
1510 case 0x35: // BLT TRANSPARENT COLOR 0xff00
1511 case 0x38: // BLT TRANSPARENT COLOR MASK 0x00ff
1512 case 0x39: // BLT TRANSPARENT COLOR MASK 0xff00
4e12cd94 1513 s->vga.gr[reg_index] = reg_value;
e6e5ad80
FB		 1514 break;
1515 case 0x21: // BLT WIDTH 0x001f00
1516 case 0x23: // BLT HEIGHT 0x001f00
1517 case 0x25: // BLT DEST PITCH 0x001f00
1518 case 0x27: // BLT SRC PITCH 0x001f00
4e12cd94 1519 s->vga.gr[reg_index] = reg_value & 0x1f;
e6e5ad80
FB		 1520 break;
1521 case 0x2a: // BLT DEST ADDR 0x3f0000
4e12cd94 1522 s->vga.gr[reg_index] = reg_value & 0x3f;
a5082316 1523 /* if auto start mode, starts bit blt now */
4e12cd94 1524 if (s->vga.gr[0x31] & CIRRUS_BLT_AUTOSTART) {
a5082316
FB		 1525 cirrus_bitblt_start(s);
1526 }
1527 break;
e6e5ad80 1528 case 0x2e: // BLT SRC ADDR 0x3f0000
4e12cd94 1529 s->vga.gr[reg_index] = reg_value & 0x3f;
e6e5ad80
FB		 1530 break;
1531 case 0x31: // BLT STATUS/START
1532 cirrus_write_bitblt(s, reg_value);
1533 break;
1534 default:
1535#ifdef DEBUG_CIRRUS
1536 printf("cirrus: outport gr_index %02x, gr_value %02x\n", reg_index,
1537 reg_value);
1538#endif
1539 break;
1540 }
e6e5ad80
FB		 1541}
1542
1543/***************************************
1544 *
1545 * I/O access between 0x3d4-0x3d5
1546 *
1547 ***************************************/
1548
b863d514 1549static int cirrus_vga_read_cr(CirrusVGAState * s, unsigned reg_index)
e6e5ad80
FB		 1550{
1551 switch (reg_index) {
1552 case 0x00: // Standard VGA
1553 case 0x01: // Standard VGA
1554 case 0x02: // Standard VGA
1555 case 0x03: // Standard VGA
1556 case 0x04: // Standard VGA
1557 case 0x05: // Standard VGA
1558 case 0x06: // Standard VGA
1559 case 0x07: // Standard VGA
1560 case 0x08: // Standard VGA
1561 case 0x09: // Standard VGA
1562 case 0x0a: // Standard VGA
1563 case 0x0b: // Standard VGA
1564 case 0x0c: // Standard VGA
1565 case 0x0d: // Standard VGA
1566 case 0x0e: // Standard VGA
1567 case 0x0f: // Standard VGA
1568 case 0x10: // Standard VGA
1569 case 0x11: // Standard VGA
1570 case 0x12: // Standard VGA
1571 case 0x13: // Standard VGA
1572 case 0x14: // Standard VGA
1573 case 0x15: // Standard VGA
1574 case 0x16: // Standard VGA
1575 case 0x17: // Standard VGA
1576 case 0x18: // Standard VGA
b863d514 1577 return s->vga.cr[s->vga.cr_index];
ca896ef3 1578 case 0x24: // Attribute Controller Toggle Readback (R)
b863d514 1579 return (s->vga.ar_flip_flop << 7);
e6e5ad80
FB		 1580 case 0x19: // Interlace End
1581 case 0x1a: // Miscellaneous Control
1582 case 0x1b: // Extended Display Control
1583 case 0x1c: // Sync Adjust and Genlock
1584 case 0x1d: // Overlay Extended Control
1585 case 0x22: // Graphics Data Latches Readback (R)
e6e5ad80
FB		 1586 case 0x25: // Part Status
1587 case 0x27: // Part ID (R)
b863d514 1588 return s->vga.cr[s->vga.cr_index];
e6e5ad80 1589 case 0x26: // Attribute Controller Index Readback (R)
b863d514 1590 return s->vga.ar_index & 0x3f;
e6e5ad80
FB		 1591 break;
1592 default:
1593#ifdef DEBUG_CIRRUS
1594 printf("cirrus: inport cr_index %02x\n", reg_index);
e6e5ad80 1595#endif
b863d514 1596 return 0xff;
e6e5ad80 1597 }
e6e5ad80
FB		 1598}
1599
4ec1ce04 1600static void cirrus_vga_write_cr(CirrusVGAState * s, int reg_value)
e6e5ad80 1601{
4ec1ce04 1602 switch (s->vga.cr_index) {
e6e5ad80
FB		 1603 case 0x00: // Standard VGA
1604 case 0x01: // Standard VGA
1605 case 0x02: // Standard VGA
1606 case 0x03: // Standard VGA
1607 case 0x04: // Standard VGA
1608 case 0x05: // Standard VGA
1609 case 0x06: // Standard VGA
1610 case 0x07: // Standard VGA
1611 case 0x08: // Standard VGA
1612 case 0x09: // Standard VGA
1613 case 0x0a: // Standard VGA
1614 case 0x0b: // Standard VGA
1615 case 0x0c: // Standard VGA
1616 case 0x0d: // Standard VGA
1617 case 0x0e: // Standard VGA
1618 case 0x0f: // Standard VGA
1619 case 0x10: // Standard VGA
1620 case 0x11: // Standard VGA
1621 case 0x12: // Standard VGA
1622 case 0x13: // Standard VGA
1623 case 0x14: // Standard VGA
1624 case 0x15: // Standard VGA
1625 case 0x16: // Standard VGA
1626 case 0x17: // Standard VGA
1627 case 0x18: // Standard VGA
4ec1ce04
JQ		 1628 /* handle CR0-7 protection */
1629 if ((s->vga.cr[0x11] & 0x80) && s->vga.cr_index <= 7) {
1630 /* can always write bit 4 of CR7 */
1631 if (s->vga.cr_index == 7)
1632 s->vga.cr[7] = (s->vga.cr[7] & ~0x10) | (reg_value & 0x10);
1633 return;
1634 }
1635 s->vga.cr[s->vga.cr_index] = reg_value;
1636 switch(s->vga.cr_index) {
1637 case 0x00:
1638 case 0x04:
1639 case 0x05:
1640 case 0x06:
1641 case 0x07:
1642 case 0x11:
1643 case 0x17:
1644 s->vga.update_retrace_info(&s->vga);
1645 break;
1646 }
1647 break;
e6e5ad80
FB		 1648 case 0x19: // Interlace End
1649 case 0x1a: // Miscellaneous Control
1650 case 0x1b: // Extended Display Control
1651 case 0x1c: // Sync Adjust and Genlock
ae184e4a 1652 case 0x1d: // Overlay Extended Control
4ec1ce04 1653 s->vga.cr[s->vga.cr_index] = reg_value;
e6e5ad80
FB		 1654#ifdef DEBUG_CIRRUS
1655 printf("cirrus: handled outport cr_index %02x, cr_value %02x\n",
4ec1ce04 1656 s->vga.cr_index, reg_value);
e6e5ad80
FB		 1657#endif
1658 break;
1659 case 0x22: // Graphics Data Latches Readback (R)
1660 case 0x24: // Attribute Controller Toggle Readback (R)
1661 case 0x26: // Attribute Controller Index Readback (R)
1662 case 0x27: // Part ID (R)
1663 break;
e6e5ad80
FB		 1664 case 0x25: // Part Status
1665 default:
1666#ifdef DEBUG_CIRRUS
4ec1ce04
JQ		 1667 printf("cirrus: outport cr_index %02x, cr_value %02x\n",
1668 s->vga.cr_index, reg_value);
e6e5ad80
FB		 1669#endif
1670 break;
1671 }
e6e5ad80
FB		 1672}
1673
1674/***************************************
1675 *
1676 * memory-mapped I/O (bitblt)
1677 *
1678 ***************************************/
1679
1680static uint8_t cirrus_mmio_blt_read(CirrusVGAState * s, unsigned address)
1681{
1682 int value = 0xff;
1683
1684 switch (address) {
1685 case (CIRRUS_MMIO_BLTBGCOLOR + 0):
f705db9d 1686 value = cirrus_vga_read_gr(s, 0x00);
e6e5ad80
FB		 1687 break;
1688 case (CIRRUS_MMIO_BLTBGCOLOR + 1):
f705db9d 1689 value = cirrus_vga_read_gr(s, 0x10);
e6e5ad80
FB		 1690 break;
1691 case (CIRRUS_MMIO_BLTBGCOLOR + 2):
f705db9d 1692 value = cirrus_vga_read_gr(s, 0x12);
e6e5ad80
FB		 1693 break;
1694 case (CIRRUS_MMIO_BLTBGCOLOR + 3):
f705db9d 1695 value = cirrus_vga_read_gr(s, 0x14);
e6e5ad80
FB		 1696 break;
1697 case (CIRRUS_MMIO_BLTFGCOLOR + 0):
f705db9d 1698 value = cirrus_vga_read_gr(s, 0x01);
e6e5ad80
FB		 1699 break;
1700 case (CIRRUS_MMIO_BLTFGCOLOR + 1):
f705db9d 1701 value = cirrus_vga_read_gr(s, 0x11);
e6e5ad80
FB		 1702 break;
1703 case (CIRRUS_MMIO_BLTFGCOLOR + 2):
f705db9d 1704 value = cirrus_vga_read_gr(s, 0x13);
e6e5ad80
FB		 1705 break;
1706 case (CIRRUS_MMIO_BLTFGCOLOR + 3):
f705db9d 1707 value = cirrus_vga_read_gr(s, 0x15);
e6e5ad80
FB		 1708 break;
1709 case (CIRRUS_MMIO_BLTWIDTH + 0):
f705db9d 1710 value = cirrus_vga_read_gr(s, 0x20);
e6e5ad80
FB		 1711 break;
1712 case (CIRRUS_MMIO_BLTWIDTH + 1):
f705db9d 1713 value = cirrus_vga_read_gr(s, 0x21);
e6e5ad80
FB		 1714 break;
1715 case (CIRRUS_MMIO_BLTHEIGHT + 0):
f705db9d 1716 value = cirrus_vga_read_gr(s, 0x22);
e6e5ad80
FB		 1717 break;
1718 case (CIRRUS_MMIO_BLTHEIGHT + 1):
f705db9d 1719 value = cirrus_vga_read_gr(s, 0x23);
e6e5ad80
FB		 1720 break;
1721 case (CIRRUS_MMIO_BLTDESTPITCH + 0):
f705db9d 1722 value = cirrus_vga_read_gr(s, 0x24);
e6e5ad80
FB		 1723 break;
1724 case (CIRRUS_MMIO_BLTDESTPITCH + 1):
f705db9d 1725 value = cirrus_vga_read_gr(s, 0x25);
e6e5ad80
FB		 1726 break;
1727 case (CIRRUS_MMIO_BLTSRCPITCH + 0):
f705db9d 1728 value = cirrus_vga_read_gr(s, 0x26);
e6e5ad80
FB		 1729 break;
1730 case (CIRRUS_MMIO_BLTSRCPITCH + 1):
f705db9d 1731 value = cirrus_vga_read_gr(s, 0x27);
e6e5ad80
FB		 1732 break;
1733 case (CIRRUS_MMIO_BLTDESTADDR + 0):
f705db9d 1734 value = cirrus_vga_read_gr(s, 0x28);
e6e5ad80
FB		 1735 break;
1736 case (CIRRUS_MMIO_BLTDESTADDR + 1):
f705db9d 1737 value = cirrus_vga_read_gr(s, 0x29);
e6e5ad80
FB		 1738 break;
1739 case (CIRRUS_MMIO_BLTDESTADDR + 2):
f705db9d 1740 value = cirrus_vga_read_gr(s, 0x2a);
e6e5ad80
FB		 1741 break;
1742 case (CIRRUS_MMIO_BLTSRCADDR + 0):
f705db9d 1743 value = cirrus_vga_read_gr(s, 0x2c);
e6e5ad80
FB		 1744 break;
1745 case (CIRRUS_MMIO_BLTSRCADDR + 1):
f705db9d 1746 value = cirrus_vga_read_gr(s, 0x2d);
e6e5ad80
FB		 1747 break;
1748 case (CIRRUS_MMIO_BLTSRCADDR + 2):
f705db9d 1749 value = cirrus_vga_read_gr(s, 0x2e);
e6e5ad80
FB		 1750 break;
1751 case CIRRUS_MMIO_BLTWRITEMASK:
f705db9d 1752 value = cirrus_vga_read_gr(s, 0x2f);
e6e5ad80
FB		 1753 break;
1754 case CIRRUS_MMIO_BLTMODE:
f705db9d 1755 value = cirrus_vga_read_gr(s, 0x30);
e6e5ad80
FB		 1756 break;
1757 case CIRRUS_MMIO_BLTROP:
f705db9d 1758 value = cirrus_vga_read_gr(s, 0x32);
e6e5ad80 1759 break;
a21ae81d 1760 case CIRRUS_MMIO_BLTMODEEXT:
f705db9d 1761 value = cirrus_vga_read_gr(s, 0x33);
a21ae81d 1762 break;
e6e5ad80 1763 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0):
f705db9d 1764 value = cirrus_vga_read_gr(s, 0x34);
e6e5ad80
FB		 1765 break;
1766 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1):
f705db9d 1767 value = cirrus_vga_read_gr(s, 0x35);
e6e5ad80
FB		 1768 break;
1769 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0):
f705db9d 1770 value = cirrus_vga_read_gr(s, 0x38);
e6e5ad80
FB		 1771 break;
1772 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1):
f705db9d 1773 value = cirrus_vga_read_gr(s, 0x39);
e6e5ad80
FB		 1774 break;
1775 case CIRRUS_MMIO_BLTSTATUS:
f705db9d 1776 value = cirrus_vga_read_gr(s, 0x31);
e6e5ad80
FB		 1777 break;
1778 default:
1779#ifdef DEBUG_CIRRUS
1780 printf("cirrus: mmio read - address 0x%04x\n", address);
1781#endif
1782 break;
1783 }
1784
1785 return (uint8_t) value;
1786}
1787
1788static void cirrus_mmio_blt_write(CirrusVGAState * s, unsigned address,
1789 uint8_t value)
1790{
1791 switch (address) {
1792 case (CIRRUS_MMIO_BLTBGCOLOR + 0):
22286bc6 1793 cirrus_vga_write_gr(s, 0x00, value);
e6e5ad80
FB		 1794 break;
1795 case (CIRRUS_MMIO_BLTBGCOLOR + 1):
22286bc6 1796 cirrus_vga_write_gr(s, 0x10, value);
e6e5ad80
FB		 1797 break;
1798 case (CIRRUS_MMIO_BLTBGCOLOR + 2):
22286bc6 1799 cirrus_vga_write_gr(s, 0x12, value);
e6e5ad80
FB		 1800 break;
1801 case (CIRRUS_MMIO_BLTBGCOLOR + 3):
22286bc6 1802 cirrus_vga_write_gr(s, 0x14, value);
e6e5ad80
FB		 1803 break;
1804 case (CIRRUS_MMIO_BLTFGCOLOR + 0):
22286bc6 1805 cirrus_vga_write_gr(s, 0x01, value);
e6e5ad80
FB		 1806 break;
1807 case (CIRRUS_MMIO_BLTFGCOLOR + 1):
22286bc6 1808 cirrus_vga_write_gr(s, 0x11, value);
e6e5ad80
FB		 1809 break;
1810 case (CIRRUS_MMIO_BLTFGCOLOR + 2):
22286bc6 1811 cirrus_vga_write_gr(s, 0x13, value);
e6e5ad80
FB		 1812 break;
1813 case (CIRRUS_MMIO_BLTFGCOLOR + 3):
22286bc6 1814 cirrus_vga_write_gr(s, 0x15, value);
e6e5ad80
FB		 1815 break;
1816 case (CIRRUS_MMIO_BLTWIDTH + 0):
22286bc6 1817 cirrus_vga_write_gr(s, 0x20, value);
e6e5ad80
FB		 1818 break;
1819 case (CIRRUS_MMIO_BLTWIDTH + 1):
22286bc6 1820 cirrus_vga_write_gr(s, 0x21, value);
e6e5ad80
FB		 1821 break;
1822 case (CIRRUS_MMIO_BLTHEIGHT + 0):
22286bc6 1823 cirrus_vga_write_gr(s, 0x22, value);
e6e5ad80
FB		 1824 break;
1825 case (CIRRUS_MMIO_BLTHEIGHT + 1):
22286bc6 1826 cirrus_vga_write_gr(s, 0x23, value);
e6e5ad80
FB		 1827 break;
1828 case (CIRRUS_MMIO_BLTDESTPITCH + 0):
22286bc6 1829 cirrus_vga_write_gr(s, 0x24, value);
e6e5ad80
FB		 1830 break;
1831 case (CIRRUS_MMIO_BLTDESTPITCH + 1):
22286bc6 1832 cirrus_vga_write_gr(s, 0x25, value);
e6e5ad80
FB		 1833 break;
1834 case (CIRRUS_MMIO_BLTSRCPITCH + 0):
22286bc6 1835 cirrus_vga_write_gr(s, 0x26, value);
e6e5ad80
FB		 1836 break;
1837 case (CIRRUS_MMIO_BLTSRCPITCH + 1):
22286bc6 1838 cirrus_vga_write_gr(s, 0x27, value);
e6e5ad80
FB		 1839 break;
1840 case (CIRRUS_MMIO_BLTDESTADDR + 0):
22286bc6 1841 cirrus_vga_write_gr(s, 0x28, value);
e6e5ad80
FB		 1842 break;
1843 case (CIRRUS_MMIO_BLTDESTADDR + 1):
22286bc6 1844 cirrus_vga_write_gr(s, 0x29, value);
e6e5ad80
FB		 1845 break;
1846 case (CIRRUS_MMIO_BLTDESTADDR + 2):
22286bc6 1847 cirrus_vga_write_gr(s, 0x2a, value);
e6e5ad80
FB		 1848 break;
1849 case (CIRRUS_MMIO_BLTDESTADDR + 3):
1850 /* ignored */
1851 break;
1852 case (CIRRUS_MMIO_BLTSRCADDR + 0):
22286bc6 1853 cirrus_vga_write_gr(s, 0x2c, value);
e6e5ad80
FB		 1854 break;
1855 case (CIRRUS_MMIO_BLTSRCADDR + 1):
22286bc6 1856 cirrus_vga_write_gr(s, 0x2d, value);
e6e5ad80
FB		 1857 break;
1858 case (CIRRUS_MMIO_BLTSRCADDR + 2):
22286bc6 1859 cirrus_vga_write_gr(s, 0x2e, value);
e6e5ad80
FB		 1860 break;
1861 case CIRRUS_MMIO_BLTWRITEMASK:
22286bc6 1862 cirrus_vga_write_gr(s, 0x2f, value);
e6e5ad80
FB		 1863 break;
1864 case CIRRUS_MMIO_BLTMODE:
22286bc6 1865 cirrus_vga_write_gr(s, 0x30, value);
e6e5ad80
FB		 1866 break;
1867 case CIRRUS_MMIO_BLTROP:
22286bc6 1868 cirrus_vga_write_gr(s, 0x32, value);
e6e5ad80 1869 break;
a21ae81d 1870 case CIRRUS_MMIO_BLTMODEEXT:
22286bc6 1871 cirrus_vga_write_gr(s, 0x33, value);
a21ae81d 1872 break;
e6e5ad80 1873 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0):
22286bc6 1874 cirrus_vga_write_gr(s, 0x34, value);
e6e5ad80
FB		 1875 break;
1876 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1):
22286bc6 1877 cirrus_vga_write_gr(s, 0x35, value);
e6e5ad80
FB		 1878 break;
1879 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0):
22286bc6 1880 cirrus_vga_write_gr(s, 0x38, value);
e6e5ad80
FB		 1881 break;
1882 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1):
22286bc6 1883 cirrus_vga_write_gr(s, 0x39, value);
e6e5ad80
FB		 1884 break;
1885 case CIRRUS_MMIO_BLTSTATUS:
22286bc6 1886 cirrus_vga_write_gr(s, 0x31, value);
e6e5ad80
FB		 1887 break;
1888 default:
1889#ifdef DEBUG_CIRRUS
1890 printf("cirrus: mmio write - addr 0x%04x val 0x%02x (ignored)\n",
1891 address, value);
1892#endif
1893 break;
1894 }
1895}
1896
e6e5ad80
FB		 1897/***************************************
1898 *
1899 * write mode 4/5
1900 *
1901 * assume TARGET_PAGE_SIZE >= 16
1902 *
1903 ***************************************/
1904
1905static void cirrus_mem_writeb_mode4and5_8bpp(CirrusVGAState * s,
1906 unsigned mode,
1907 unsigned offset,
1908 uint32_t mem_value)
1909{
1910 int x;
1911 unsigned val = mem_value;
1912 uint8_t *dst;
1913
4e12cd94 1914 dst = s->vga.vram_ptr + (offset &= s->cirrus_addr_mask);
e6e5ad80
FB		 1915 for (x = 0; x < 8; x++) {
1916 if (val & 0x80) {
0b74ed78 1917 *dst = s->cirrus_shadow_gr1;
e6e5ad80 1918 } else if (mode == 5) {
0b74ed78 1919 *dst = s->cirrus_shadow_gr0;
e6e5ad80
FB		 1920 }
1921 val <<= 1;
0b74ed78 1922 dst++;
e6e5ad80 1923 }
b1950430
AK		 1924 memory_region_set_dirty(&s->vga.vram, offset);
1925 memory_region_set_dirty(&s->vga.vram, offset + 7);
e6e5ad80
FB		 1926}
1927
1928static void cirrus_mem_writeb_mode4and5_16bpp(CirrusVGAState * s,
1929 unsigned mode,
1930 unsigned offset,
1931 uint32_t mem_value)
1932{
1933 int x;
1934 unsigned val = mem_value;
1935 uint8_t *dst;
1936
4e12cd94 1937 dst = s->vga.vram_ptr + (offset &= s->cirrus_addr_mask);
e6e5ad80
FB		 1938 for (x = 0; x < 8; x++) {
1939 if (val & 0x80) {
0b74ed78 1940 *dst = s->cirrus_shadow_gr1;
4e12cd94 1941 *(dst + 1) = s->vga.gr[0x11];
e6e5ad80 1942 } else if (mode == 5) {
0b74ed78 1943 *dst = s->cirrus_shadow_gr0;
4e12cd94 1944 *(dst + 1) = s->vga.gr[0x10];
e6e5ad80
FB		 1945 }
1946 val <<= 1;
0b74ed78 1947 dst += 2;
e6e5ad80 1948 }
b1950430
AK		 1949 memory_region_set_dirty(&s->vga.vram, offset);
1950 memory_region_set_dirty(&s->vga.vram, offset + 15);
e6e5ad80
FB		 1951}
1952
1953/***************************************
1954 *
1955 * memory access between 0xa0000-0xbffff
1956 *
1957 ***************************************/
1958
c227f099 1959static uint32_t cirrus_vga_mem_readb(void *opaque, target_phys_addr_t addr)
e6e5ad80
FB		 1960{
1961 CirrusVGAState *s = opaque;
1962 unsigned bank_index;
1963 unsigned bank_offset;
1964 uint32_t val;
1965
4e12cd94 1966 if ((s->vga.sr[0x07] & 0x01) == 0) {
e6e5ad80
FB		 1967 return vga_mem_readb(s, addr);
1968 }
1969
aeb3c85f
FB		 1970 addr &= 0x1ffff;
1971
e6e5ad80
FB		 1972 if (addr < 0x10000) {
1973 /* XXX handle bitblt */
1974 /* video memory */
1975 bank_index = addr >> 15;
1976 bank_offset = addr & 0x7fff;
1977 if (bank_offset < s->cirrus_bank_limit[bank_index]) {
1978 bank_offset += s->cirrus_bank_base[bank_index];
4e12cd94 1979 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
e6e5ad80 1980 bank_offset <<= 4;
4e12cd94 1981 } else if (s->vga.gr[0x0B] & 0x02) {
e6e5ad80
FB		 1982 bank_offset <<= 3;
1983 }
1984 bank_offset &= s->cirrus_addr_mask;
4e12cd94 1985 val = *(s->vga.vram_ptr + bank_offset);
e6e5ad80
FB		 1986 } else
1987 val = 0xff;
1988 } else if (addr >= 0x18000 && addr < 0x18100) {
1989 /* memory-mapped I/O */
1990 val = 0xff;
4e12cd94 1991 if ((s->vga.sr[0x17] & 0x44) == 0x04) {
e6e5ad80
FB		 1992 val = cirrus_mmio_blt_read(s, addr & 0xff);
1993 }
1994 } else {
1995 val = 0xff;
1996#ifdef DEBUG_CIRRUS
0bf9e31a 1997 printf("cirrus: mem_readb " TARGET_FMT_plx "\n", addr);
e6e5ad80
FB		 1998#endif
1999 }
2000 return val;
2001}
2002
c227f099 2003static uint32_t cirrus_vga_mem_readw(void *opaque, target_phys_addr_t addr)
e6e5ad80
FB		 2004{
2005 uint32_t v;
3fbb33d0 2006
e6e5ad80
FB		 2007 v = cirrus_vga_mem_readb(opaque, addr);
2008 v |= cirrus_vga_mem_readb(opaque, addr + 1) << 8;
e6e5ad80
FB		 2009 return v;
2010}
2011
c227f099 2012static uint32_t cirrus_vga_mem_readl(void *opaque, target_phys_addr_t addr)
e6e5ad80
FB		 2013{
2014 uint32_t v;
3fbb33d0 2015
e6e5ad80
FB		 2016 v = cirrus_vga_mem_readb(opaque, addr);
2017 v |= cirrus_vga_mem_readb(opaque, addr + 1) << 8;
2018 v |= cirrus_vga_mem_readb(opaque, addr + 2) << 16;
2019 v |= cirrus_vga_mem_readb(opaque, addr + 3) << 24;
e6e5ad80
FB		 2020 return v;
2021}
2022
c227f099 2023static void cirrus_vga_mem_writeb(void *opaque, target_phys_addr_t addr,
e6e5ad80
FB		 2024 uint32_t mem_value)
2025{
2026 CirrusVGAState *s = opaque;
2027 unsigned bank_index;
2028 unsigned bank_offset;
2029 unsigned mode;
2030
4e12cd94 2031 if ((s->vga.sr[0x07] & 0x01) == 0) {
e6e5ad80
FB		 2032 vga_mem_writeb(s, addr, mem_value);
2033 return;
2034 }
2035
aeb3c85f
FB		 2036 addr &= 0x1ffff;
2037
e6e5ad80
FB		 2038 if (addr < 0x10000) {
2039 if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2040 /* bitblt */
2041 *s->cirrus_srcptr++ = (uint8_t) mem_value;
a5082316 2042 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
e6e5ad80
FB		 2043 cirrus_bitblt_cputovideo_next(s);
2044 }
2045 } else {
2046 /* video memory */
2047 bank_index = addr >> 15;
2048 bank_offset = addr & 0x7fff;
2049 if (bank_offset < s->cirrus_bank_limit[bank_index]) {
2050 bank_offset += s->cirrus_bank_base[bank_index];
4e12cd94 2051 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
e6e5ad80 2052 bank_offset <<= 4;
4e12cd94 2053 } else if (s->vga.gr[0x0B] & 0x02) {
e6e5ad80
FB		 2054 bank_offset <<= 3;
2055 }
2056 bank_offset &= s->cirrus_addr_mask;
4e12cd94
AK		 2057 mode = s->vga.gr[0x05] & 0x7;
2058 if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) {
2059 *(s->vga.vram_ptr + bank_offset) = mem_value;
b1950430 2060 memory_region_set_dirty(&s->vga.vram, bank_offset);
e6e5ad80 2061 } else {
4e12cd94 2062 if ((s->vga.gr[0x0B] & 0x14) != 0x14) {
e6e5ad80
FB		 2063 cirrus_mem_writeb_mode4and5_8bpp(s, mode,
2064 bank_offset,
2065 mem_value);
2066 } else {
2067 cirrus_mem_writeb_mode4and5_16bpp(s, mode,
2068 bank_offset,
2069 mem_value);
2070 }
2071 }
2072 }
2073 }
2074 } else if (addr >= 0x18000 && addr < 0x18100) {
2075 /* memory-mapped I/O */
4e12cd94 2076 if ((s->vga.sr[0x17] & 0x44) == 0x04) {
e6e5ad80
FB		 2077 cirrus_mmio_blt_write(s, addr & 0xff, mem_value);
2078 }
2079 } else {
2080#ifdef DEBUG_CIRRUS
0bf9e31a
BS		 2081 printf("cirrus: mem_writeb " TARGET_FMT_plx " value %02x\n", addr,
2082 mem_value);
e6e5ad80
FB		 2083#endif
2084 }
2085}
2086
c227f099 2087static void cirrus_vga_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
e6e5ad80 2088{
e6e5ad80
FB		 2089 cirrus_vga_mem_writeb(opaque, addr, val & 0xff);
2090 cirrus_vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
e6e5ad80
FB		 2091}
2092
c227f099 2093static void cirrus_vga_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
e6e5ad80 2094{
e6e5ad80
FB		 2095 cirrus_vga_mem_writeb(opaque, addr, val & 0xff);
2096 cirrus_vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2097 cirrus_vga_mem_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2098 cirrus_vga_mem_writeb(opaque, addr + 3, (val >> 24) & 0xff);
e6e5ad80
FB		 2099}
2100
b1950430
AK		 2101static uint64_t cirrus_vga_mem_read(void *opaque,
2102 target_phys_addr_t addr,
2103 uint32_t size)
2104{
2105 CirrusVGAState *s = opaque;
2106
2107 switch (size) {
2108 case 1: return cirrus_vga_mem_readb(s, addr);
2109 case 2: return cirrus_vga_mem_readw(s, addr);
2110 case 4: return cirrus_vga_mem_readl(s, addr);
2111 default: abort();
2112 }
2113}
2114
2115static void cirrus_vga_mem_write(void *opaque, target_phys_addr_t addr,
2116 uint64_t data, unsigned size)
2117{
2118 CirrusVGAState *s = opaque;
2119
2120 switch (size) {
2121 case 1: return cirrus_vga_mem_writeb(s, addr, data);
2122 case 2: return cirrus_vga_mem_writew(s, addr, data);
2123 case 4: return cirrus_vga_mem_writel(s, addr, data);
2124 default: abort();
2125 }
e6e5ad80
FB		 2126};
2127
b1950430
AK		 2128static const MemoryRegionOps cirrus_vga_mem_ops = {
2129 .read = cirrus_vga_mem_read,
2130 .write = cirrus_vga_mem_write,
2131 .endianness = DEVICE_LITTLE_ENDIAN,
e6e5ad80
FB		 2132};
2133
a5082316
FB		 2134/***************************************
2135 *
2136 * hardware cursor
2137 *
2138 ***************************************/
2139
2140static inline void invalidate_cursor1(CirrusVGAState *s)
2141{
2142 if (s->last_hw_cursor_size) {
4e12cd94 2143 vga_invalidate_scanlines(&s->vga,
a5082316
FB		 2144 s->last_hw_cursor_y + s->last_hw_cursor_y_start,
2145 s->last_hw_cursor_y + s->last_hw_cursor_y_end);
2146 }
2147}
2148
2149static inline void cirrus_cursor_compute_yrange(CirrusVGAState *s)
2150{
2151 const uint8_t *src;
2152 uint32_t content;
2153 int y, y_min, y_max;
2154
4e12cd94
AK		 2155 src = s->vga.vram_ptr + s->real_vram_size - 16 * 1024;
2156 if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) {
2157 src += (s->vga.sr[0x13] & 0x3c) * 256;
a5082316
FB		 2158 y_min = 64;
2159 y_max = -1;
2160 for(y = 0; y < 64; y++) {
2161 content = ((uint32_t *)src)[0] |
2162 ((uint32_t *)src)[1] |
2163 ((uint32_t *)src)[2] |
2164 ((uint32_t *)src)[3];
2165 if (content) {
2166 if (y < y_min)
2167 y_min = y;
2168 if (y > y_max)
2169 y_max = y;
2170 }
2171 src += 16;
2172 }
2173 } else {
4e12cd94 2174 src += (s->vga.sr[0x13] & 0x3f) * 256;
a5082316
FB		 2175 y_min = 32;
2176 y_max = -1;
2177 for(y = 0; y < 32; y++) {
2178 content = ((uint32_t *)src)[0] |
2179 ((uint32_t *)(src + 128))[0];
2180 if (content) {
2181 if (y < y_min)
2182 y_min = y;
2183 if (y > y_max)
2184 y_max = y;
2185 }
2186 src += 4;
2187 }
2188 }
2189 if (y_min > y_max) {
2190 s->last_hw_cursor_y_start = 0;
2191 s->last_hw_cursor_y_end = 0;
2192 } else {
2193 s->last_hw_cursor_y_start = y_min;
2194 s->last_hw_cursor_y_end = y_max + 1;
2195 }
2196}
2197
2198/* NOTE: we do not currently handle the cursor bitmap change, so we
2199 update the cursor only if it moves. */
a4a2f59c 2200static void cirrus_cursor_invalidate(VGACommonState *s1)
a5082316 2201{
4e12cd94 2202 CirrusVGAState *s = container_of(s1, CirrusVGAState, vga);
a5082316
FB		 2203 int size;
2204
4e12cd94 2205 if (!(s->vga.sr[0x12] & CIRRUS_CURSOR_SHOW)) {
a5082316
FB		 2206 size = 0;
2207 } else {
4e12cd94 2208 if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE)
a5082316
FB		 2209 size = 64;
2210 else
2211 size = 32;
2212 }
2213 /* invalidate last cursor and new cursor if any change */
2214 if (s->last_hw_cursor_size != size ||
2215 s->last_hw_cursor_x != s->hw_cursor_x ||
2216 s->last_hw_cursor_y != s->hw_cursor_y) {
2217
2218 invalidate_cursor1(s);
3b46e624 2219
a5082316
FB		 2220 s->last_hw_cursor_size = size;
2221 s->last_hw_cursor_x = s->hw_cursor_x;
2222 s->last_hw_cursor_y = s->hw_cursor_y;
2223 /* compute the real cursor min and max y */
2224 cirrus_cursor_compute_yrange(s);
2225 invalidate_cursor1(s);
2226 }
2227}
2228
a4a2f59c 2229static void cirrus_cursor_draw_line(VGACommonState *s1, uint8_t *d1, int scr_y)
a5082316 2230{
4e12cd94 2231 CirrusVGAState *s = container_of(s1, CirrusVGAState, vga);
a5082316
FB		 2232 int w, h, bpp, x1, x2, poffset;
2233 unsigned int color0, color1;
2234 const uint8_t *palette, *src;
2235 uint32_t content;
3b46e624 2236
4e12cd94 2237 if (!(s->vga.sr[0x12] & CIRRUS_CURSOR_SHOW))
a5082316
FB		 2238 return;
2239 /* fast test to see if the cursor intersects with the scan line */
4e12cd94 2240 if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) {
a5082316
FB		 2241 h = 64;
2242 } else {
2243 h = 32;
2244 }
2245 if (scr_y < s->hw_cursor_y ||
2246 scr_y >= (s->hw_cursor_y + h))
2247 return;
3b46e624 2248
4e12cd94
AK		 2249 src = s->vga.vram_ptr + s->real_vram_size - 16 * 1024;
2250 if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) {
2251 src += (s->vga.sr[0x13] & 0x3c) * 256;
a5082316
FB		 2252 src += (scr_y - s->hw_cursor_y) * 16;
2253 poffset = 8;
2254 content = ((uint32_t *)src)[0] |
2255 ((uint32_t *)src)[1] |
2256 ((uint32_t *)src)[2] |
2257 ((uint32_t *)src)[3];
2258 } else {
4e12cd94 2259 src += (s->vga.sr[0x13] & 0x3f) * 256;
a5082316
FB		 2260 src += (scr_y - s->hw_cursor_y) * 4;
2261 poffset = 128;
2262 content = ((uint32_t *)src)[0] |
2263 ((uint32_t *)(src + 128))[0];
2264 }
2265 /* if nothing to draw, no need to continue */
2266 if (!content)
2267 return;
2268 w = h;
2269
2270 x1 = s->hw_cursor_x;
4e12cd94 2271 if (x1 >= s->vga.last_scr_width)
a5082316
FB		 2272 return;
2273 x2 = s->hw_cursor_x + w;
4e12cd94
AK		 2274 if (x2 > s->vga.last_scr_width)
2275 x2 = s->vga.last_scr_width;
a5082316
FB		 2276 w = x2 - x1;
2277 palette = s->cirrus_hidden_palette;
4e12cd94
AK		 2278 color0 = s->vga.rgb_to_pixel(c6_to_8(palette[0x0 * 3]),
2279 c6_to_8(palette[0x0 * 3 + 1]),
2280 c6_to_8(palette[0x0 * 3 + 2]));
2281 color1 = s->vga.rgb_to_pixel(c6_to_8(palette[0xf * 3]),
2282 c6_to_8(palette[0xf * 3 + 1]),
2283 c6_to_8(palette[0xf * 3 + 2]));
2284 bpp = ((ds_get_bits_per_pixel(s->vga.ds) + 7) >> 3);
a5082316 2285 d1 += x1 * bpp;
4e12cd94 2286 switch(ds_get_bits_per_pixel(s->vga.ds)) {
a5082316
FB		 2287 default:
2288 break;
2289 case 8:
2290 vga_draw_cursor_line_8(d1, src, poffset, w, color0, color1, 0xff);
2291 break;
2292 case 15:
2293 vga_draw_cursor_line_16(d1, src, poffset, w, color0, color1, 0x7fff);
2294 break;
2295 case 16:
2296 vga_draw_cursor_line_16(d1, src, poffset, w, color0, color1, 0xffff);
2297 break;
2298 case 32:
2299 vga_draw_cursor_line_32(d1, src, poffset, w, color0, color1, 0xffffff);
2300 break;
2301 }
2302}
2303
e6e5ad80
FB		 2304/***************************************
2305 *
2306 * LFB memory access
2307 *
2308 ***************************************/
2309
c227f099 2310static uint32_t cirrus_linear_readb(void *opaque, target_phys_addr_t addr)
e6e5ad80 2311{
e05587e8 2312 CirrusVGAState *s = opaque;
e6e5ad80
FB		 2313 uint32_t ret;
2314
e6e5ad80
FB		 2315 addr &= s->cirrus_addr_mask;
2316
4e12cd94 2317 if (((s->vga.sr[0x17] & 0x44) == 0x44) &&
78e127ef 2318 ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) {
e6e5ad80
FB		 2319 /* memory-mapped I/O */
2320 ret = cirrus_mmio_blt_read(s, addr & 0xff);
2321 } else if (0) {
2322 /* XXX handle bitblt */
2323 ret = 0xff;
2324 } else {
2325 /* video memory */
4e12cd94 2326 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
e6e5ad80 2327 addr <<= 4;
4e12cd94 2328 } else if (s->vga.gr[0x0B] & 0x02) {
e6e5ad80
FB		 2329 addr <<= 3;
2330 }
2331 addr &= s->cirrus_addr_mask;
4e12cd94 2332 ret = *(s->vga.vram_ptr + addr);
e6e5ad80
FB		 2333 }
2334
2335 return ret;
2336}
2337
c227f099 2338static uint32_t cirrus_linear_readw(void *opaque, target_phys_addr_t addr)
e6e5ad80
FB		 2339{
2340 uint32_t v;
3fbb33d0 2341
e6e5ad80
FB		 2342 v = cirrus_linear_readb(opaque, addr);
2343 v |= cirrus_linear_readb(opaque, addr + 1) << 8;
e6e5ad80
FB		 2344 return v;
2345}
2346
c227f099 2347static uint32_t cirrus_linear_readl(void *opaque, target_phys_addr_t addr)
e6e5ad80
FB		 2348{
2349 uint32_t v;
3fbb33d0 2350
e6e5ad80
FB		 2351 v = cirrus_linear_readb(opaque, addr);
2352 v |= cirrus_linear_readb(opaque, addr + 1) << 8;
2353 v |= cirrus_linear_readb(opaque, addr + 2) << 16;
2354 v |= cirrus_linear_readb(opaque, addr + 3) << 24;
e6e5ad80
FB		 2355 return v;
2356}
2357
c227f099 2358static void cirrus_linear_writeb(void *opaque, target_phys_addr_t addr,
e6e5ad80
FB		 2359 uint32_t val)
2360{
e05587e8 2361 CirrusVGAState *s = opaque;
e6e5ad80
FB		 2362 unsigned mode;
2363
2364 addr &= s->cirrus_addr_mask;
3b46e624 2365
4e12cd94 2366 if (((s->vga.sr[0x17] & 0x44) == 0x44) &&
78e127ef 2367 ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) {
e6e5ad80
FB		 2368 /* memory-mapped I/O */
2369 cirrus_mmio_blt_write(s, addr & 0xff, val);
2370 } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2371 /* bitblt */
2372 *s->cirrus_srcptr++ = (uint8_t) val;
a5082316 2373 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
e6e5ad80
FB		 2374 cirrus_bitblt_cputovideo_next(s);
2375 }
2376 } else {
2377 /* video memory */
4e12cd94 2378 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
e6e5ad80 2379 addr <<= 4;
4e12cd94 2380 } else if (s->vga.gr[0x0B] & 0x02) {
e6e5ad80
FB		 2381 addr <<= 3;
2382 }
2383 addr &= s->cirrus_addr_mask;
2384
4e12cd94
AK		 2385 mode = s->vga.gr[0x05] & 0x7;
2386 if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) {
2387 *(s->vga.vram_ptr + addr) = (uint8_t) val;
b1950430 2388 memory_region_set_dirty(&s->vga.vram, addr);
e6e5ad80 2389 } else {
4e12cd94 2390 if ((s->vga.gr[0x0B] & 0x14) != 0x14) {
e6e5ad80
FB		 2391 cirrus_mem_writeb_mode4and5_8bpp(s, mode, addr, val);
2392 } else {
2393 cirrus_mem_writeb_mode4and5_16bpp(s, mode, addr, val);
2394 }
2395 }
2396 }
2397}
2398
c227f099 2399static void cirrus_linear_writew(void *opaque, target_phys_addr_t addr,
e6e5ad80
FB		 2400 uint32_t val)
2401{
e6e5ad80
FB		 2402 cirrus_linear_writeb(opaque, addr, val & 0xff);
2403 cirrus_linear_writeb(opaque, addr + 1, (val >> 8) & 0xff);
e6e5ad80
FB		 2404}
2405
c227f099 2406static void cirrus_linear_writel(void *opaque, target_phys_addr_t addr,
e6e5ad80
FB		 2407 uint32_t val)
2408{
e6e5ad80
FB		 2409 cirrus_linear_writeb(opaque, addr, val & 0xff);
2410 cirrus_linear_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2411 cirrus_linear_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2412 cirrus_linear_writeb(opaque, addr + 3, (val >> 24) & 0xff);
e6e5ad80
FB		 2413}
2414
2415
b1950430
AK		 2416static uint64_t cirrus_linear_read(void *opaque, target_phys_addr_t addr,
2417 unsigned size)
2418{
2419 CirrusVGAState *s = opaque;
e6e5ad80 2420
b1950430
AK		 2421 switch (size) {
2422 case 1: return cirrus_linear_readb(s, addr);
2423 case 2: return cirrus_linear_readw(s, addr);
2424 case 4: return cirrus_linear_readl(s, addr);
2425 default: abort();
2426 }
2427}
2428
2429static void cirrus_linear_write(void *opaque, target_phys_addr_t addr,
2430 uint64_t data, unsigned size)
2431{
2432 CirrusVGAState *s = opaque;
2433
2434 switch (size) {
2435 case 1: return cirrus_linear_writeb(s, addr, data);
2436 case 2: return cirrus_linear_writew(s, addr, data);
2437 case 4: return cirrus_linear_writel(s, addr, data);
2438 default: abort();
2439 }
2440}
e6e5ad80 2441
a5082316
FB		 2442/***************************************
2443 *
2444 * system to screen memory access
2445 *
2446 ***************************************/
2447
2448
4e56f089
AK		 2449static uint64_t cirrus_linear_bitblt_read(void *opaque,
2450 target_phys_addr_t addr,
2451 unsigned size)
a5082316 2452{
4e56f089 2453 CirrusVGAState *s = opaque;
a5082316
FB		 2454 uint32_t ret;
2455
2456 /* XXX handle bitblt */
4e56f089 2457 (void)s;
a5082316
FB		 2458 ret = 0xff;
2459 return ret;
2460}
2461
4e56f089
AK		 2462static void cirrus_linear_bitblt_write(void *opaque,
2463 target_phys_addr_t addr,
2464 uint64_t val,
2465 unsigned size)
a5082316 2466{
e05587e8 2467 CirrusVGAState *s = opaque;
a5082316
FB		 2468
2469 if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2470 /* bitblt */
2471 *s->cirrus_srcptr++ = (uint8_t) val;
2472 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
2473 cirrus_bitblt_cputovideo_next(s);
2474 }
2475 }
2476}
2477
b1950430
AK		 2478static const MemoryRegionOps cirrus_linear_bitblt_io_ops = {
2479 .read = cirrus_linear_bitblt_read,
2480 .write = cirrus_linear_bitblt_write,
2481 .endianness = DEVICE_LITTLE_ENDIAN,
4e56f089
AK		 2482 .impl = {
2483 .min_access_size = 1,
2484 .max_access_size = 1,
2485 },
a5082316
FB		 2486};
2487
b1950430 2488static void unmap_bank(CirrusVGAState *s, unsigned bank)
2bec46dc 2489{
b1950430
AK		 2490 if (s->cirrus_bank[bank]) {
2491 memory_region_del_subregion(&s->low_mem_container,
2492 s->cirrus_bank[bank]);
2493 memory_region_destroy(s->cirrus_bank[bank]);
2494 qemu_free(s->cirrus_bank[bank]);
2495 s->cirrus_bank[bank] = NULL;
2bec46dc 2496 }
b1950430 2497}
2bec46dc 2498
b1950430
AK		 2499static void map_linear_vram_bank(CirrusVGAState *s, unsigned bank)
2500{
2501 MemoryRegion *mr;
2502 static const char *names[] = { "vga.bank0", "vga.bank1" };
2bec46dc
AL		 2503
2504 if (!(s->cirrus_srcptr != s->cirrus_srcptr_end)
4e12cd94
AK		 2505 && !((s->vga.sr[0x07] & 0x01) == 0)
2506 && !((s->vga.gr[0x0B] & 0x14) == 0x14)
2507 && !(s->vga.gr[0x0B] & 0x02)) {
2bec46dc 2508
b1950430
AK		 2509 mr = qemu_malloc(sizeof(*mr));
2510 memory_region_init_alias(mr, names[bank], &s->vga.vram,
2511 s->cirrus_bank_base[bank], 0x8000);
2512 memory_region_add_subregion_overlap(
2513 &s->low_mem_container,
2514 0x8000 * bank,
2515 mr,
2516 1);
2517 unmap_bank(s, bank);
2518 s->cirrus_bank[bank] = mr;
2519 } else {
2520 unmap_bank(s, bank);
2bec46dc 2521 }
b1950430 2522}
2bec46dc 2523
b1950430
AK		 2524static void map_linear_vram(CirrusVGAState *s)
2525{
2526 if (!s->linear_vram) {
2527 s->linear_vram = true;
2528 memory_region_add_subregion_overlap(&s->pci_bar, 0, &s->vga.vram, 1);
2529 }
2530 map_linear_vram_bank(s, 0);
2531 map_linear_vram_bank(s, 1);
2bec46dc
AL		 2532}
2533
2534static void unmap_linear_vram(CirrusVGAState *s)
2535{
b1950430
AK		 2536 if (s->linear_vram) {
2537 s->linear_vram = false;
2538 memory_region_del_subregion(&s->pci_bar, &s->vga.vram);
4516e45f 2539 }
b1950430
AK		 2540 unmap_bank(s, 0);
2541 unmap_bank(s, 1);
2bec46dc
AL		 2542}
2543
8926b517
FB		 2544/* Compute the memory access functions */
2545static void cirrus_update_memory_access(CirrusVGAState *s)
2546{
2547 unsigned mode;
2548
4e12cd94 2549 if ((s->vga.sr[0x17] & 0x44) == 0x44) {
8926b517
FB		 2550 goto generic_io;
2551 } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2552 goto generic_io;
2553 } else {
4e12cd94 2554 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
8926b517 2555 goto generic_io;
4e12cd94 2556 } else if (s->vga.gr[0x0B] & 0x02) {
8926b517
FB		 2557 goto generic_io;
2558 }
3b46e624 2559
4e12cd94
AK		 2560 mode = s->vga.gr[0x05] & 0x7;
2561 if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) {
2bec46dc 2562 map_linear_vram(s);
8926b517
FB		 2563 } else {
2564 generic_io:
2bec46dc 2565 unmap_linear_vram(s);
8926b517
FB		 2566 }
2567 }
2568}
2569
2570
e6e5ad80
FB		 2571/* I/O ports */
2572
0ceac75b 2573static uint32_t cirrus_vga_ioport_read(void *opaque, uint32_t addr)
e6e5ad80 2574{
b6343073
JQ		 2575 CirrusVGAState *c = opaque;
2576 VGACommonState *s = &c->vga;
e6e5ad80
FB		 2577 int val, index;
2578
b6343073 2579 if (vga_ioport_invalid(s, addr)) {
e6e5ad80
FB		 2580 val = 0xff;
2581 } else {
2582 switch (addr) {
2583 case 0x3c0:
b6343073
JQ		 2584 if (s->ar_flip_flop == 0) {
2585 val = s->ar_index;
e6e5ad80
FB		 2586 } else {
2587 val = 0;
2588 }
2589 break;
2590 case 0x3c1:
b6343073 2591 index = s->ar_index & 0x1f;
e6e5ad80 2592 if (index < 21)
b6343073 2593 val = s->ar[index];
e6e5ad80
FB		 2594 else
2595 val = 0;
2596 break;
2597 case 0x3c2:
b6343073 2598 val = s->st00;
e6e5ad80
FB		 2599 break;
2600 case 0x3c4:
b6343073 2601 val = s->sr_index;
e6e5ad80
FB		 2602 break;
2603 case 0x3c5:
8a82c322
JQ		 2604 val = cirrus_vga_read_sr(c);
2605 break;
e6e5ad80 2606#ifdef DEBUG_VGA_REG
b6343073 2607 printf("vga: read SR%x = 0x%02x\n", s->sr_index, val);
e6e5ad80
FB		 2608#endif
2609 break;
2610 case 0x3c6:
957c9db5 2611 val = cirrus_read_hidden_dac(c);
e6e5ad80
FB		 2612 break;
2613 case 0x3c7:
b6343073 2614 val = s->dac_state;
e6e5ad80 2615 break;
ae184e4a 2616 case 0x3c8:
b6343073
JQ		 2617 val = s->dac_write_index;
2618 c->cirrus_hidden_dac_lockindex = 0;
ae184e4a
FB		 2619 break;
2620 case 0x3c9:
5deaeee3
JQ		 2621 val = cirrus_vga_read_palette(c);
2622 break;
e6e5ad80 2623 case 0x3ca:
b6343073 2624 val = s->fcr;
e6e5ad80
FB		 2625 break;
2626 case 0x3cc:
b6343073 2627 val = s->msr;
e6e5ad80
FB		 2628 break;
2629 case 0x3ce:
b6343073 2630 val = s->gr_index;
e6e5ad80
FB		 2631 break;
2632 case 0x3cf:
f705db9d 2633 val = cirrus_vga_read_gr(c, s->gr_index);
e6e5ad80 2634#ifdef DEBUG_VGA_REG
b6343073 2635 printf("vga: read GR%x = 0x%02x\n", s->gr_index, val);
e6e5ad80
FB		 2636#endif
2637 break;
2638 case 0x3b4:
2639 case 0x3d4:
b6343073 2640 val = s->cr_index;
e6e5ad80
FB		 2641 break;
2642 case 0x3b5:
2643 case 0x3d5:
b863d514 2644 val = cirrus_vga_read_cr(c, s->cr_index);
e6e5ad80 2645#ifdef DEBUG_VGA_REG
b6343073 2646 printf("vga: read CR%x = 0x%02x\n", s->cr_index, val);
e6e5ad80
FB		 2647#endif
2648 break;
2649 case 0x3ba:
2650 case 0x3da:
2651 /* just toggle to fool polling */
b6343073
JQ		 2652 val = s->st01 = s->retrace(s);
2653 s->ar_flip_flop = 0;
e6e5ad80
FB		 2654 break;
2655 default:
2656 val = 0x00;
2657 break;
2658 }
2659 }
2660#if defined(DEBUG_VGA)
2661 printf("VGA: read addr=0x%04x data=0x%02x\n", addr, val);
2662#endif
2663 return val;
2664}
2665
0ceac75b 2666static void cirrus_vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
e6e5ad80 2667{
b6343073
JQ		 2668 CirrusVGAState *c = opaque;
2669 VGACommonState *s = &c->vga;
e6e5ad80
FB		 2670 int index;
2671
2672 /* check port range access depending on color/monochrome mode */
b6343073 2673 if (vga_ioport_invalid(s, addr)) {
e6e5ad80 2674 return;
25a18cbd 2675 }
e6e5ad80
FB		 2676#ifdef DEBUG_VGA
2677 printf("VGA: write addr=0x%04x data=0x%02x\n", addr, val);
2678#endif
2679
2680 switch (addr) {
2681 case 0x3c0:
b6343073 2682 if (s->ar_flip_flop == 0) {
e6e5ad80 2683 val &= 0x3f;
b6343073 2684 s->ar_index = val;
e6e5ad80 2685 } else {
b6343073 2686 index = s->ar_index & 0x1f;
e6e5ad80
FB		 2687 switch (index) {
2688 case 0x00 ... 0x0f:
b6343073 2689 s->ar[index] = val & 0x3f;
e6e5ad80
FB		 2690 break;
2691 case 0x10:
b6343073 2692 s->ar[index] = val & ~0x10;
e6e5ad80
FB		 2693 break;
2694 case 0x11:
b6343073 2695 s->ar[index] = val;
e6e5ad80
FB		 2696 break;
2697 case 0x12:
b6343073 2698 s->ar[index] = val & ~0xc0;
e6e5ad80
FB		 2699 break;
2700 case 0x13:
b6343073 2701 s->ar[index] = val & ~0xf0;
e6e5ad80
FB		 2702 break;
2703 case 0x14:
b6343073 2704 s->ar[index] = val & ~0xf0;
e6e5ad80
FB		 2705 break;
2706 default:
2707 break;
2708 }
2709 }
b6343073 2710 s->ar_flip_flop ^= 1;
e6e5ad80
FB		 2711 break;
2712 case 0x3c2:
b6343073
JQ		 2713 s->msr = val & ~0x10;
2714 s->update_retrace_info(s);
e6e5ad80
FB		 2715 break;
2716 case 0x3c4:
b6343073 2717 s->sr_index = val;
e6e5ad80
FB		 2718 break;
2719 case 0x3c5:
e6e5ad80 2720#ifdef DEBUG_VGA_REG
b6343073 2721 printf("vga: write SR%x = 0x%02x\n", s->sr_index, val);
e6e5ad80 2722#endif
31c63201
JQ		 2723 cirrus_vga_write_sr(c, val);
2724 break;
e6e5ad80
FB		 2725 break;
2726 case 0x3c6:
b6343073 2727 cirrus_write_hidden_dac(c, val);
e6e5ad80
FB		 2728 break;
2729 case 0x3c7:
b6343073
JQ		 2730 s->dac_read_index = val;
2731 s->dac_sub_index = 0;
2732 s->dac_state = 3;
e6e5ad80
FB		 2733 break;
2734 case 0x3c8:
b6343073
JQ		 2735 s->dac_write_index = val;
2736 s->dac_sub_index = 0;
2737 s->dac_state = 0;
e6e5ad80
FB		 2738 break;
2739 case 0x3c9:
86948bb1
JQ		 2740 cirrus_vga_write_palette(c, val);
2741 break;
e6e5ad80 2742 case 0x3ce:
b6343073 2743 s->gr_index = val;
e6e5ad80
FB		 2744 break;
2745 case 0x3cf:
e6e5ad80 2746#ifdef DEBUG_VGA_REG
b6343073 2747 printf("vga: write GR%x = 0x%02x\n", s->gr_index, val);
e6e5ad80 2748#endif
22286bc6 2749 cirrus_vga_write_gr(c, s->gr_index, val);
e6e5ad80
FB		 2750 break;
2751 case 0x3b4:
2752 case 0x3d4:
b6343073 2753 s->cr_index = val;
e6e5ad80
FB		 2754 break;
2755 case 0x3b5:
2756 case 0x3d5:
e6e5ad80 2757#ifdef DEBUG_VGA_REG
b6343073 2758 printf("vga: write CR%x = 0x%02x\n", s->cr_index, val);
e6e5ad80 2759#endif
4ec1ce04 2760 cirrus_vga_write_cr(c, val);
e6e5ad80
FB		 2761 break;
2762 case 0x3ba:
2763 case 0x3da:
b6343073 2764 s->fcr = val & 0x10;
e6e5ad80
FB		 2765 break;
2766 }
2767}
2768
e36f36e1
FB		 2769/***************************************
2770 *
2771 * memory-mapped I/O access
2772 *
2773 ***************************************/
2774
1e04d4d6
AK		 2775static uint64_t cirrus_mmio_read(void *opaque, target_phys_addr_t addr,
2776 unsigned size)
e36f36e1 2777{
e05587e8 2778 CirrusVGAState *s = opaque;
e36f36e1 2779
e36f36e1
FB		 2780 if (addr >= 0x100) {
2781 return cirrus_mmio_blt_read(s, addr - 0x100);
2782 } else {
0ceac75b 2783 return cirrus_vga_ioport_read(s, addr + 0x3c0);
e36f36e1
FB		 2784 }
2785}
2786
1e04d4d6
AK		 2787static void cirrus_mmio_write(void *opaque, target_phys_addr_t addr,
2788 uint64_t val, unsigned size)
e36f36e1 2789{
e05587e8 2790 CirrusVGAState *s = opaque;
e36f36e1 2791
e36f36e1
FB		 2792 if (addr >= 0x100) {
2793 cirrus_mmio_blt_write(s, addr - 0x100, val);
2794 } else {
0ceac75b 2795 cirrus_vga_ioport_write(s, addr + 0x3c0, val);
e36f36e1
FB		 2796 }
2797}
2798
b1950430
AK		 2799static const MemoryRegionOps cirrus_mmio_io_ops = {
2800 .read = cirrus_mmio_read,
2801 .write = cirrus_mmio_write,
2802 .endianness = DEVICE_LITTLE_ENDIAN,
1e04d4d6
AK		 2803 .impl = {
2804 .min_access_size = 1,
2805 .max_access_size = 1,
2806 },
e36f36e1
FB		 2807};
2808
2c6ab832
FB		 2809/* load/save state */
2810
e59fb374 2811static int cirrus_post_load(void *opaque, int version_id)
2c6ab832
FB		 2812{
2813 CirrusVGAState *s = opaque;
2814
4e12cd94
AK		 2815 s->vga.gr[0x00] = s->cirrus_shadow_gr0 & 0x0f;
2816 s->vga.gr[0x01] = s->cirrus_shadow_gr1 & 0x0f;
2c6ab832 2817
2bec46dc 2818 cirrus_update_memory_access(s);
2c6ab832 2819 /* force refresh */
4e12cd94 2820 s->vga.graphic_mode = -1;
2c6ab832
FB		 2821 cirrus_update_bank_ptr(s, 0);
2822 cirrus_update_bank_ptr(s, 1);
2823 return 0;
2824}
2825
7e72abc3
JQ		 2826static const VMStateDescription vmstate_cirrus_vga = {
2827 .name = "cirrus_vga",
2828 .version_id = 2,
2829 .minimum_version_id = 1,
2830 .minimum_version_id_old = 1,
2831 .post_load = cirrus_post_load,
2832 .fields = (VMStateField []) {
2833 VMSTATE_UINT32(vga.latch, CirrusVGAState),
2834 VMSTATE_UINT8(vga.sr_index, CirrusVGAState),
2835 VMSTATE_BUFFER(vga.sr, CirrusVGAState),
2836 VMSTATE_UINT8(vga.gr_index, CirrusVGAState),
2837 VMSTATE_UINT8(cirrus_shadow_gr0, CirrusVGAState),
2838 VMSTATE_UINT8(cirrus_shadow_gr1, CirrusVGAState),
2839 VMSTATE_BUFFER_START_MIDDLE(vga.gr, CirrusVGAState, 2),
2840 VMSTATE_UINT8(vga.ar_index, CirrusVGAState),
2841 VMSTATE_BUFFER(vga.ar, CirrusVGAState),
2842 VMSTATE_INT32(vga.ar_flip_flop, CirrusVGAState),
2843 VMSTATE_UINT8(vga.cr_index, CirrusVGAState),
2844 VMSTATE_BUFFER(vga.cr, CirrusVGAState),
2845 VMSTATE_UINT8(vga.msr, CirrusVGAState),
2846 VMSTATE_UINT8(vga.fcr, CirrusVGAState),
2847 VMSTATE_UINT8(vga.st00, CirrusVGAState),
2848 VMSTATE_UINT8(vga.st01, CirrusVGAState),
2849 VMSTATE_UINT8(vga.dac_state, CirrusVGAState),
2850 VMSTATE_UINT8(vga.dac_sub_index, CirrusVGAState),
2851 VMSTATE_UINT8(vga.dac_read_index, CirrusVGAState),
2852 VMSTATE_UINT8(vga.dac_write_index, CirrusVGAState),
2853 VMSTATE_BUFFER(vga.dac_cache, CirrusVGAState),
2854 VMSTATE_BUFFER(vga.palette, CirrusVGAState),
2855 VMSTATE_INT32(vga.bank_offset, CirrusVGAState),
2856 VMSTATE_UINT8(cirrus_hidden_dac_lockindex, CirrusVGAState),
2857 VMSTATE_UINT8(cirrus_hidden_dac_data, CirrusVGAState),
2858 VMSTATE_UINT32(hw_cursor_x, CirrusVGAState),
2859 VMSTATE_UINT32(hw_cursor_y, CirrusVGAState),
2860 /* XXX: we do not save the bitblt state - we assume we do not save
2861 the state when the blitter is active */
2862 VMSTATE_END_OF_LIST()
4f335feb 2863 }
7e72abc3 2864};
4f335feb 2865
7e72abc3
JQ		 2866static const VMStateDescription vmstate_pci_cirrus_vga = {
2867 .name = "cirrus_vga",
2868 .version_id = 2,
2869 .minimum_version_id = 2,
2870 .minimum_version_id_old = 2,
7e72abc3
JQ		 2871 .fields = (VMStateField []) {
2872 VMSTATE_PCI_DEVICE(dev, PCICirrusVGAState),
2873 VMSTATE_STRUCT(cirrus_vga, PCICirrusVGAState, 0,
2874 vmstate_cirrus_vga, CirrusVGAState),
2875 VMSTATE_END_OF_LIST()
2876 }
2877};
4f335feb 2878
e6e5ad80
FB		 2879/***************************************
2880 *
2881 * initialize
2882 *
2883 ***************************************/
2884
4abc796d 2885static void cirrus_reset(void *opaque)
e6e5ad80 2886{
4abc796d 2887 CirrusVGAState *s = opaque;
e6e5ad80 2888
03a3e7ba 2889 vga_common_reset(&s->vga);
ee50c6bc 2890 unmap_linear_vram(s);
4e12cd94 2891 s->vga.sr[0x06] = 0x0f;
4abc796d 2892 if (s->device_id == CIRRUS_ID_CLGD5446) {
78e127ef 2893 /* 4MB 64 bit memory config, always PCI */
4e12cd94
AK		 2894 s->vga.sr[0x1F] = 0x2d; // MemClock
2895 s->vga.gr[0x18] = 0x0f; // fastest memory configuration
2896 s->vga.sr[0x0f] = 0x98;
2897 s->vga.sr[0x17] = 0x20;
2898 s->vga.sr[0x15] = 0x04; /* memory size, 3=2MB, 4=4MB */
78e127ef 2899 } else {
4e12cd94
AK		 2900 s->vga.sr[0x1F] = 0x22; // MemClock
2901 s->vga.sr[0x0F] = CIRRUS_MEMSIZE_2M;
2902 s->vga.sr[0x17] = s->bustype;
2903 s->vga.sr[0x15] = 0x03; /* memory size, 3=2MB, 4=4MB */
78e127ef 2904 }
4e12cd94 2905 s->vga.cr[0x27] = s->device_id;
e6e5ad80 2906
78e127ef
FB		 2907 /* Win2K seems to assume that the pattern buffer is at 0xff
2908 initially ! */
4e12cd94 2909 memset(s->vga.vram_ptr, 0xff, s->real_vram_size);
78e127ef 2910
e6e5ad80
FB		 2911 s->cirrus_hidden_dac_lockindex = 5;
2912 s->cirrus_hidden_dac_data = 0;
4abc796d
BS		 2913}
2914
b1950430
AK		 2915static const MemoryRegionOps cirrus_linear_io_ops = {
2916 .read = cirrus_linear_read,
2917 .write = cirrus_linear_write,
2918 .endianness = DEVICE_LITTLE_ENDIAN,
2919};
2920
4abc796d
BS		 2921static void cirrus_init_common(CirrusVGAState * s, int device_id, int is_pci)
2922{
2923 int i;
2924 static int inited;
2925
2926 if (!inited) {
2927 inited = 1;
2928 for(i = 0;i < 256; i++)
2929 rop_to_index[i] = CIRRUS_ROP_NOP_INDEX; /* nop rop */
2930 rop_to_index[CIRRUS_ROP_0] = 0;
2931 rop_to_index[CIRRUS_ROP_SRC_AND_DST] = 1;
2932 rop_to_index[CIRRUS_ROP_NOP] = 2;
2933 rop_to_index[CIRRUS_ROP_SRC_AND_NOTDST] = 3;
2934 rop_to_index[CIRRUS_ROP_NOTDST] = 4;
2935 rop_to_index[CIRRUS_ROP_SRC] = 5;
2936 rop_to_index[CIRRUS_ROP_1] = 6;
2937 rop_to_index[CIRRUS_ROP_NOTSRC_AND_DST] = 7;
2938 rop_to_index[CIRRUS_ROP_SRC_XOR_DST] = 8;
2939 rop_to_index[CIRRUS_ROP_SRC_OR_DST] = 9;
2940 rop_to_index[CIRRUS_ROP_NOTSRC_OR_NOTDST] = 10;
2941 rop_to_index[CIRRUS_ROP_SRC_NOTXOR_DST] = 11;
2942 rop_to_index[CIRRUS_ROP_SRC_OR_NOTDST] = 12;
2943 rop_to_index[CIRRUS_ROP_NOTSRC] = 13;
2944 rop_to_index[CIRRUS_ROP_NOTSRC_OR_DST] = 14;
2945 rop_to_index[CIRRUS_ROP_NOTSRC_AND_NOTDST] = 15;
2946 s->device_id = device_id;
2947 if (is_pci)
2948 s->bustype = CIRRUS_BUSTYPE_PCI;
2949 else
2950 s->bustype = CIRRUS_BUSTYPE_ISA;
2951 }
2952
0ceac75b 2953 register_ioport_write(0x3c0, 16, 1, cirrus_vga_ioport_write, s);
4abc796d 2954
0ceac75b
JQ		 2955 register_ioport_write(0x3b4, 2, 1, cirrus_vga_ioport_write, s);
2956 register_ioport_write(0x3d4, 2, 1, cirrus_vga_ioport_write, s);
2957 register_ioport_write(0x3ba, 1, 1, cirrus_vga_ioport_write, s);
2958 register_ioport_write(0x3da, 1, 1, cirrus_vga_ioport_write, s);
4abc796d 2959
0ceac75b 2960 register_ioport_read(0x3c0, 16, 1, cirrus_vga_ioport_read, s);
4abc796d 2961
0ceac75b
JQ		 2962 register_ioport_read(0x3b4, 2, 1, cirrus_vga_ioport_read, s);
2963 register_ioport_read(0x3d4, 2, 1, cirrus_vga_ioport_read, s);
2964 register_ioport_read(0x3ba, 1, 1, cirrus_vga_ioport_read, s);
2965 register_ioport_read(0x3da, 1, 1, cirrus_vga_ioport_read, s);
4abc796d 2966
b1950430
AK		 2967 memory_region_init(&s->low_mem_container,
2968 "cirrus-lowmem-container",
2969 0x20000);
2970
2971 memory_region_init_io(&s->low_mem, &cirrus_vga_mem_ops, s,
2972 "cirrus-low-memory", 0x20000);
2973 memory_region_add_subregion(&s->low_mem_container, 0, &s->low_mem);
2974 memory_region_add_subregion_overlap(get_system_memory(),
2975 isa_mem_base + 0x000a0000,
2976 &s->low_mem_container,
2977 1);
2978 memory_region_set_coalescing(&s->low_mem);
2c6ab832 2979
fefe54e3 2980 /* I/O handler for LFB */
b1950430
AK		 2981 memory_region_init_io(&s->cirrus_linear_io, &cirrus_linear_io_ops, s,
2982 "cirrus-linear-io", VGA_RAM_SIZE);
fefe54e3
AL		 2983
2984 /* I/O handler for LFB */
b1950430
AK		 2985 memory_region_init_io(&s->cirrus_linear_bitblt_io,
2986 &cirrus_linear_bitblt_io_ops,
2987 s,
2988 "cirrus-bitblt-mmio",
2989 0x400000);
fefe54e3
AL		 2990
2991 /* I/O handler for memory-mapped I/O */
b1950430
AK		 2992 memory_region_init_io(&s->cirrus_mmio_io, &cirrus_mmio_io_ops, s,
2993 "cirrus-mmio", CIRRUS_PNPMMIO_SIZE);
fefe54e3
AL		 2994
2995 s->real_vram_size =
2996 (s->device_id == CIRRUS_ID_CLGD5446) ? 4096 * 1024 : 2048 * 1024;
2997
4e12cd94 2998 /* XXX: s->vga.vram_size must be a power of two */
fefe54e3
AL		 2999 s->cirrus_addr_mask = s->real_vram_size - 1;
3000 s->linear_mmio_mask = s->real_vram_size - 256;
3001
4e12cd94
AK		 3002 s->vga.get_bpp = cirrus_get_bpp;
3003 s->vga.get_offsets = cirrus_get_offsets;
3004 s->vga.get_resolution = cirrus_get_resolution;
3005 s->vga.cursor_invalidate = cirrus_cursor_invalidate;
3006 s->vga.cursor_draw_line = cirrus_cursor_draw_line;
fefe54e3 3007
a08d4367 3008 qemu_register_reset(cirrus_reset, s);
e6e5ad80
FB		 3009}
3010
3011/***************************************
3012 *
3013 * ISA bus support
3014 *
3015 ***************************************/
3016
fbe1b595 3017void isa_cirrus_vga_init(void)
e6e5ad80
FB		 3018{
3019 CirrusVGAState *s;
3020
3021 s = qemu_mallocz(sizeof(CirrusVGAState));
3b46e624 3022
fbe1b595 3023 vga_common_init(&s->vga, VGA_RAM_SIZE);
78e127ef 3024 cirrus_init_common(s, CIRRUS_ID_CLGD5430, 0);
4e12cd94
AK		 3025 s->vga.ds = graphic_console_init(s->vga.update, s->vga.invalidate,
3026 s->vga.screen_dump, s->vga.text_update,
3027 &s->vga);
0be71e32 3028 vmstate_register(NULL, 0, &vmstate_cirrus_vga, s);
5245d57a 3029 rom_add_vga(VGABIOS_CIRRUS_FILENAME);
e6e5ad80
FB		 3030 /* XXX ISA-LFB support */
3031}
3032
3033/***************************************
3034 *
3035 * PCI bus support
3036 *
3037 ***************************************/
3038
81a322d4 3039static int pci_cirrus_vga_initfn(PCIDevice *dev)
a414c306
GH		 3040{
3041 PCICirrusVGAState *d = DO_UPCAST(PCICirrusVGAState, dev, dev);
3042 CirrusVGAState *s = &d->cirrus_vga;
5b96d8f9
IY		 3043 PCIDeviceInfo *info = DO_UPCAST(PCIDeviceInfo, qdev, dev->qdev.info);
3044 int16_t device_id = info->device_id;
a414c306
GH		 3045
3046 /* setup VGA */
3047 vga_common_init(&s->vga, VGA_RAM_SIZE);
3048 cirrus_init_common(s, device_id, 1);
a414c306
GH		 3049 s->vga.ds = graphic_console_init(s->vga.update, s->vga.invalidate,
3050 s->vga.screen_dump, s->vga.text_update,
3051 &s->vga);
3052
3053 /* setup PCI */
a414c306 3054
b1950430
AK		 3055 memory_region_init(&s->pci_bar, "cirrus-pci-bar0", 0x2000000);
3056
3057 /* XXX: add byte swapping apertures */
3058 memory_region_add_subregion(&s->pci_bar, 0, &s->cirrus_linear_io);
3059 memory_region_add_subregion(&s->pci_bar, 0x1000000,
3060 &s->cirrus_linear_bitblt_io);
3061
a414c306
GH		 3062 /* setup memory space */
3063 /* memory #0 LFB */
3064 /* memory #1 memory-mapped I/O */
3065 /* XXX: s->vga.vram_size must be a power of two */
b1950430
AK		 3066 pci_register_bar_region(&d->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH,
3067 &s->pci_bar);
a414c306 3068 if (device_id == CIRRUS_ID_CLGD5446) {
b1950430 3069 pci_register_bar_region(&d->dev, 1, 0, &s->cirrus_mmio_io);
a414c306 3070 }
81a322d4 3071 return 0;
a414c306
GH		 3072}
3073
fbe1b595 3074void pci_cirrus_vga_init(PCIBus *bus)
e6e5ad80 3075{
556cd098 3076 pci_create_simple(bus, -1, "cirrus-vga");
a414c306 3077}
d34cab9f 3078
a414c306 3079static PCIDeviceInfo cirrus_vga_info = {
556cd098
MA		 3080 .qdev.name = "cirrus-vga",
3081 .qdev.desc = "Cirrus CLGD 54xx VGA",
a414c306 3082 .qdev.size = sizeof(PCICirrusVGAState),
be73cfe2 3083 .qdev.vmsd = &vmstate_pci_cirrus_vga,
be92bbf7 3084 .no_hotplug = 1,
a414c306 3085 .init = pci_cirrus_vga_initfn,
8c52c8f3 3086 .romfile = VGABIOS_CIRRUS_FILENAME,
5b96d8f9
IY		 3087 .vendor_id = PCI_VENDOR_ID_CIRRUS,
3088 .device_id = CIRRUS_ID_CLGD5446,
3089 .class_id = PCI_CLASS_DISPLAY_VGA,
a414c306 3090};
e6e5ad80 3091
a414c306
GH		 3092static void cirrus_vga_register(void)
3093{
3094 pci_qdev_register(&cirrus_vga_info);
e6e5ad80 3095}
a414c306 3096device_init(cirrus_vga_register);
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