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[qemu.git] / hw / display / qxl.c
CommitLineData
a19cbfb3
GH		 1/*
2 * Copyright (C) 2010 Red Hat, Inc.
3 *
4 * written by Yaniv Kamay, Izik Eidus, Gerd Hoffmann
5 * maintained by Gerd Hoffmann <[email protected]>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 or
10 * (at your option) version 3 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, see <http://www.gnu.org/licenses/>.
19 */
20
47df5154 21#include "qemu/osdep.h"
f0353b0d 22#include "qemu/units.h"
a639ab04
AL		 23#include <zlib.h>
24
e688df6b 25#include "qapi/error.h"
a19cbfb3 26#include "qemu-common.h"
1de7afc9
PB		 27#include "qemu/timer.h"
28#include "qemu/queue.h"
5444e768 29#include "qemu/atomic.h"
9c17d615 30#include "sysemu/sysemu.h"
795c40b8 31#include "migration/blocker.h"
c480bb7d 32#include "trace.h"
a19cbfb3 33
47b43a1f 34#include "qxl.h"
a19cbfb3 35
0b81c478
AL		 36/*
37 * NOTE: SPICE_RING_PROD_ITEM accesses memory on the pci bar and as
38 * such can be changed by the guest, so to avoid a guest trigerrable
0a530548 39 * abort we just qxl_set_guest_bug and set the return to NULL. Still
0b81c478
AL		 40 * it may happen as a result of emulator bug as well.
41 */
a19cbfb3 42#undef SPICE_RING_PROD_ITEM
0b81c478 43#define SPICE_RING_PROD_ITEM(qxl, r, ret) { \
a19cbfb3 44 uint32_t prod = (r)->prod & SPICE_RING_INDEX_MASK(r); \
bc5f92e5 45 if (prod >= ARRAY_SIZE((r)->items)) { \
0a530548 46 qxl_set_guest_bug(qxl, "SPICE_RING_PROD_ITEM indices mismatch " \
bc5f92e5 47 "%u >= %zu", prod, ARRAY_SIZE((r)->items)); \
0b81c478
AL		 48 ret = NULL; \
49 } else { \
bc5f92e5 50 ret = &(r)->items[prod].el; \
a19cbfb3 51 } \
a19cbfb3
GH		 52 }
53
54#undef SPICE_RING_CONS_ITEM
0b81c478 55#define SPICE_RING_CONS_ITEM(qxl, r, ret) { \
a19cbfb3 56 uint32_t cons = (r)->cons & SPICE_RING_INDEX_MASK(r); \
bc5f92e5 57 if (cons >= ARRAY_SIZE((r)->items)) { \
0a530548 58 qxl_set_guest_bug(qxl, "SPICE_RING_CONS_ITEM indices mismatch " \
bc5f92e5 59 "%u >= %zu", cons, ARRAY_SIZE((r)->items)); \
0b81c478
AL		 60 ret = NULL; \
61 } else { \
bc5f92e5 62 ret = &(r)->items[cons].el; \
a19cbfb3 63 } \
a19cbfb3
GH		 64 }
65
66#undef ALIGN
67#define ALIGN(a, b) (((a) + ((b) - 1)) & ~((b) - 1))
68
69#define PIXEL_SIZE 0.2936875 //1280x1024 is 14.8" x 11.9"
70
71#define QXL_MODE(_x, _y, _b, _o) \
72 { .x_res = _x, \
73 .y_res = _y, \
74 .bits = _b, \
75 .stride = (_x) * (_b) / 8, \
76 .x_mili = PIXEL_SIZE * (_x), \
77 .y_mili = PIXEL_SIZE * (_y), \
78 .orientation = _o, \
79 }
80
81#define QXL_MODE_16_32(x_res, y_res, orientation) \
82 QXL_MODE(x_res, y_res, 16, orientation), \
83 QXL_MODE(x_res, y_res, 32, orientation)
84
85#define QXL_MODE_EX(x_res, y_res) \
86 QXL_MODE_16_32(x_res, y_res, 0), \
038c1879 87 QXL_MODE_16_32(x_res, y_res, 1)
a19cbfb3
GH		 88
89static QXLMode qxl_modes[] = {
90 QXL_MODE_EX(640, 480),
91 QXL_MODE_EX(800, 480),
92 QXL_MODE_EX(800, 600),
93 QXL_MODE_EX(832, 624),
94 QXL_MODE_EX(960, 640),
95 QXL_MODE_EX(1024, 600),
96 QXL_MODE_EX(1024, 768),
97 QXL_MODE_EX(1152, 864),
98 QXL_MODE_EX(1152, 870),
99 QXL_MODE_EX(1280, 720),
100 QXL_MODE_EX(1280, 760),
101 QXL_MODE_EX(1280, 768),
102 QXL_MODE_EX(1280, 800),
103 QXL_MODE_EX(1280, 960),
104 QXL_MODE_EX(1280, 1024),
105 QXL_MODE_EX(1360, 768),
106 QXL_MODE_EX(1366, 768),
107 QXL_MODE_EX(1400, 1050),
108 QXL_MODE_EX(1440, 900),
109 QXL_MODE_EX(1600, 900),
110 QXL_MODE_EX(1600, 1200),
111 QXL_MODE_EX(1680, 1050),
112 QXL_MODE_EX(1920, 1080),
a19cbfb3
GH		 113 /* these modes need more than 8 MB video memory */
114 QXL_MODE_EX(1920, 1200),
115 QXL_MODE_EX(1920, 1440),
5c74fb27 116 QXL_MODE_EX(2000, 2000),
a19cbfb3 117 QXL_MODE_EX(2048, 1536),
5c74fb27 118 QXL_MODE_EX(2048, 2048),
a19cbfb3
GH		 119 QXL_MODE_EX(2560, 1440),
120 QXL_MODE_EX(2560, 1600),
a19cbfb3
GH		 121 /* these modes need more than 16 MB video memory */
122 QXL_MODE_EX(2560, 2048),
123 QXL_MODE_EX(2800, 2100),
124 QXL_MODE_EX(3200, 2400),
03d9825d 125 /* these modes need more than 32 MB video memory */
d4bcb199
GH		 126 QXL_MODE_EX(3840, 2160), /* 4k mainstream */
127 QXL_MODE_EX(4096, 2160), /* 4k */
03d9825d 128 /* these modes need more than 64 MB video memory */
d4bcb199 129 QXL_MODE_EX(7680, 4320), /* 8k mainstream */
03d9825d 130 /* these modes need more than 128 MB video memory */
d4bcb199 131 QXL_MODE_EX(8192, 4320), /* 8k */
a19cbfb3
GH		 132};
133
a19cbfb3 134static void qxl_send_events(PCIQXLDevice *d, uint32_t events);
5ff4e36c 135static int qxl_destroy_primary(PCIQXLDevice *d, qxl_async_io async);
a19cbfb3
GH		 136static void qxl_reset_memslots(PCIQXLDevice *d);
137static void qxl_reset_surfaces(PCIQXLDevice *d);
138static void qxl_ring_set_dirty(PCIQXLDevice *qxl);
139
15162335
GH		 140static void qxl_hw_update(void *opaque);
141
0a530548 142void qxl_set_guest_bug(PCIQXLDevice *qxl, const char *msg, ...)
2bce0400 143{
917ae08c 144 trace_qxl_set_guest_bug(qxl->id);
2bce0400 145 qxl_send_events(qxl, QXL_INTERRUPT_ERROR);
087e6a42 146 qxl->guest_bug = 1;
2bce0400 147 if (qxl->guestdebug) {
7635392c
AL		 148 va_list ap;
149 va_start(ap, msg);
150 fprintf(stderr, "qxl-%d: guest bug: ", qxl->id);
151 vfprintf(stderr, msg, ap);
152 fprintf(stderr, "\n");
153 va_end(ap);
2bce0400
GH		 154 }
155}
156
087e6a42
AL		 157static void qxl_clear_guest_bug(PCIQXLDevice *qxl)
158{
159 qxl->guest_bug = 0;
160}
aee32bf3
GH		 161
162void qxl_spice_update_area(PCIQXLDevice *qxl, uint32_t surface_id,
163 struct QXLRect *area, struct QXLRect *dirty_rects,
164 uint32_t num_dirty_rects,
5ff4e36c 165 uint32_t clear_dirty_region,
2e1a98c9 166 qxl_async_io async, struct QXLCookie *cookie)
aee32bf3 167{
c480bb7d
AL		 168 trace_qxl_spice_update_area(qxl->id, surface_id, area->left, area->right,
169 area->top, area->bottom);
170 trace_qxl_spice_update_area_rest(qxl->id, num_dirty_rects,
171 clear_dirty_region);
5ff4e36c 172 if (async == QXL_SYNC) {
26defe81 173 spice_qxl_update_area(&qxl->ssd.qxl, surface_id, area,
5ff4e36c
AL		 174 dirty_rects, num_dirty_rects, clear_dirty_region);
175 } else {
2e1a98c9 176 assert(cookie != NULL);
5ff4e36c 177 spice_qxl_update_area_async(&qxl->ssd.qxl, surface_id, area,
5dba0d45 178 clear_dirty_region, (uintptr_t)cookie);
5ff4e36c 179 }
aee32bf3
GH		 180}
181
5ff4e36c
AL		 182static void qxl_spice_destroy_surface_wait_complete(PCIQXLDevice *qxl,
183 uint32_t id)
aee32bf3 184{
c480bb7d 185 trace_qxl_spice_destroy_surface_wait_complete(qxl->id, id);
14898cf6 186 qemu_mutex_lock(&qxl->track_lock);
14898cf6
GH		 187 qxl->guest_surfaces.cmds[id] = 0;
188 qxl->guest_surfaces.count--;
189 qemu_mutex_unlock(&qxl->track_lock);
aee32bf3
GH		 190}
191
5ff4e36c
AL		 192static void qxl_spice_destroy_surface_wait(PCIQXLDevice *qxl, uint32_t id,
193 qxl_async_io async)
194{
2e1a98c9
AL		 195 QXLCookie *cookie;
196
c480bb7d 197 trace_qxl_spice_destroy_surface_wait(qxl->id, id, async);
5ff4e36c 198 if (async) {
2e1a98c9
AL		 199 cookie = qxl_cookie_new(QXL_COOKIE_TYPE_IO,
200 QXL_IO_DESTROY_SURFACE_ASYNC);
201 cookie->u.surface_id = id;
5dba0d45 202 spice_qxl_destroy_surface_async(&qxl->ssd.qxl, id, (uintptr_t)cookie);
5ff4e36c 203 } else {
26defe81 204 spice_qxl_destroy_surface_wait(&qxl->ssd.qxl, id);
753b8b0d 205 qxl_spice_destroy_surface_wait_complete(qxl, id);
5ff4e36c
AL		 206 }
207}
208
3e16b9c5
AL		 209static void qxl_spice_flush_surfaces_async(PCIQXLDevice *qxl)
210{
c480bb7d
AL		 211 trace_qxl_spice_flush_surfaces_async(qxl->id, qxl->guest_surfaces.count,
212 qxl->num_free_res);
2e1a98c9 213 spice_qxl_flush_surfaces_async(&qxl->ssd.qxl,
5dba0d45
PM		 214 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO,
215 QXL_IO_FLUSH_SURFACES_ASYNC));
3e16b9c5 216}
3e16b9c5 217
aee32bf3
GH		 218void qxl_spice_loadvm_commands(PCIQXLDevice *qxl, struct QXLCommandExt *ext,
219 uint32_t count)
220{
c480bb7d 221 trace_qxl_spice_loadvm_commands(qxl->id, ext, count);
26defe81 222 spice_qxl_loadvm_commands(&qxl->ssd.qxl, ext, count);
aee32bf3
GH		 223}
224
225void qxl_spice_oom(PCIQXLDevice *qxl)
226{
c480bb7d 227 trace_qxl_spice_oom(qxl->id);
26defe81 228 spice_qxl_oom(&qxl->ssd.qxl);
aee32bf3
GH		 229}
230
231void qxl_spice_reset_memslots(PCIQXLDevice *qxl)
232{
c480bb7d 233 trace_qxl_spice_reset_memslots(qxl->id);
26defe81 234 spice_qxl_reset_memslots(&qxl->ssd.qxl);
aee32bf3
GH		 235}
236
5ff4e36c 237static void qxl_spice_destroy_surfaces_complete(PCIQXLDevice *qxl)
aee32bf3 238{
c480bb7d 239 trace_qxl_spice_destroy_surfaces_complete(qxl->id);
14898cf6 240 qemu_mutex_lock(&qxl->track_lock);
ddd8fdc7 241 memset(qxl->guest_surfaces.cmds, 0,
8bb9f51c 242 sizeof(qxl->guest_surfaces.cmds[0]) * qxl->ssd.num_surfaces);
14898cf6
GH		 243 qxl->guest_surfaces.count = 0;
244 qemu_mutex_unlock(&qxl->track_lock);
aee32bf3
GH		 245}
246
5ff4e36c
AL		 247static void qxl_spice_destroy_surfaces(PCIQXLDevice *qxl, qxl_async_io async)
248{
c480bb7d 249 trace_qxl_spice_destroy_surfaces(qxl->id, async);
5ff4e36c 250 if (async) {
2e1a98c9 251 spice_qxl_destroy_surfaces_async(&qxl->ssd.qxl,
5dba0d45
PM		 252 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO,
253 QXL_IO_DESTROY_ALL_SURFACES_ASYNC));
5ff4e36c 254 } else {
26defe81 255 spice_qxl_destroy_surfaces(&qxl->ssd.qxl);
5ff4e36c
AL		 256 qxl_spice_destroy_surfaces_complete(qxl);
257 }
258}
259
020af1c4
AL		 260static void qxl_spice_monitors_config_async(PCIQXLDevice *qxl, int replay)
261{
979f7ef8
GH		 262 QXLMonitorsConfig *cfg;
263
020af1c4 264 trace_qxl_spice_monitors_config(qxl->id);
020af1c4
AL		 265 if (replay) {
266 /*
267 * don't use QXL_COOKIE_TYPE_IO:
268 * - we are not running yet (post_load), we will assert
269 * in send_events
270 * - this is not a guest io, but a reply, so async_io isn't set.
271 */
272 spice_qxl_monitors_config_async(&qxl->ssd.qxl,
273 qxl->guest_monitors_config,
274 MEMSLOT_GROUP_GUEST,
275 (uintptr_t)qxl_cookie_new(
276 QXL_COOKIE_TYPE_POST_LOAD_MONITORS_CONFIG,
277 0));
278 } else {
567161fd
FZ		 279#if SPICE_SERVER_VERSION >= 0x000c06 /* release 0.12.6 */
280 if (qxl->max_outputs) {
a52b2cbf 281 spice_qxl_set_max_monitors(&qxl->ssd.qxl, qxl->max_outputs);
567161fd
FZ		 282 }
283#endif
020af1c4
AL		 284 qxl->guest_monitors_config = qxl->ram->monitors_config;
285 spice_qxl_monitors_config_async(&qxl->ssd.qxl,
286 qxl->ram->monitors_config,
287 MEMSLOT_GROUP_GUEST,
288 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO,
289 QXL_IO_MONITORS_CONFIG_ASYNC));
290 }
979f7ef8
GH		 291
292 cfg = qxl_phys2virt(qxl, qxl->guest_monitors_config, MEMSLOT_GROUP_GUEST);
2f99f80c 293 if (cfg != NULL && cfg->count == 1) {
979f7ef8
GH		 294 qxl->guest_primary.resized = 1;
295 qxl->guest_head0_width = cfg->heads[0].width;
296 qxl->guest_head0_height = cfg->heads[0].height;
297 } else {
298 qxl->guest_head0_width = 0;
299 qxl->guest_head0_height = 0;
300 }
020af1c4
AL		 301}
302
aee32bf3
GH		 303void qxl_spice_reset_image_cache(PCIQXLDevice *qxl)
304{
c480bb7d 305 trace_qxl_spice_reset_image_cache(qxl->id);
26defe81 306 spice_qxl_reset_image_cache(&qxl->ssd.qxl);
aee32bf3
GH		 307}
308
309void qxl_spice_reset_cursor(PCIQXLDevice *qxl)
310{
c480bb7d 311 trace_qxl_spice_reset_cursor(qxl->id);
26defe81 312 spice_qxl_reset_cursor(&qxl->ssd.qxl);
30f6da66
YH		 313 qemu_mutex_lock(&qxl->track_lock);
314 qxl->guest_cursor = 0;
315 qemu_mutex_unlock(&qxl->track_lock);
958c2bce
GH		 316 if (qxl->ssd.cursor) {
317 cursor_put(qxl->ssd.cursor);
318 }
319 qxl->ssd.cursor = cursor_builtin_hidden();
aee32bf3
GH		 320}
321
6f663d7b
GH		 322static uint32_t qxl_crc32(const uint8_t *p, unsigned len)
323{
324 /*
325 * zlib xors the seed with 0xffffffff, and xors the result
326 * again with 0xffffffff; Both are not done with linux's crc32,
327 * which we want to be compatible with, so undo that.
328 */
329 return crc32(0xffffffff, p, len) ^ 0xffffffff;
330}
331
a19cbfb3
GH		 332static ram_addr_t qxl_rom_size(void)
333{
df45892c
MT		 334#define QXL_REQUIRED_SZ (sizeof(QXLRom) + sizeof(QXLModes) + sizeof(qxl_modes))
335#define QXL_ROM_SZ 8192
13d1fd44 336
df45892c
MT		 337 QEMU_BUILD_BUG_ON(QXL_REQUIRED_SZ > QXL_ROM_SZ);
338 return QXL_ROM_SZ;
a19cbfb3
GH		 339}
340
341static void init_qxl_rom(PCIQXLDevice *d)
342{
b1950430 343 QXLRom *rom = memory_region_get_ram_ptr(&d->rom_bar);
a19cbfb3
GH		 344 QXLModes *modes = (QXLModes *)(rom + 1);
345 uint32_t ram_header_size;
346 uint32_t surface0_area_size;
347 uint32_t num_pages;
13d1fd44
AL		 348 uint32_t fb;
349 int i, n;
a19cbfb3
GH		 350
351 memset(rom, 0, d->rom_size);
352
353 rom->magic = cpu_to_le32(QXL_ROM_MAGIC);
354 rom->id = cpu_to_le32(d->id);
355 rom->log_level = cpu_to_le32(d->guestdebug);
356 rom->modes_offset = cpu_to_le32(sizeof(QXLRom));
357
358 rom->slot_gen_bits = MEMSLOT_GENERATION_BITS;
359 rom->slot_id_bits = MEMSLOT_SLOT_BITS;
360 rom->slots_start = 1;
361 rom->slots_end = NUM_MEMSLOTS - 1;
ddd8fdc7 362 rom->n_surfaces = cpu_to_le32(d->ssd.num_surfaces);
a19cbfb3 363
13d1fd44 364 for (i = 0, n = 0; i < ARRAY_SIZE(qxl_modes); i++) {
a19cbfb3 365 fb = qxl_modes[i].y_res * qxl_modes[i].stride;
13d1fd44
AL		 366 if (fb > d->vgamem_size) {
367 continue;
a19cbfb3 368 }
13d1fd44
AL		 369 modes->modes[n].id = cpu_to_le32(i);
370 modes->modes[n].x_res = cpu_to_le32(qxl_modes[i].x_res);
371 modes->modes[n].y_res = cpu_to_le32(qxl_modes[i].y_res);
372 modes->modes[n].bits = cpu_to_le32(qxl_modes[i].bits);
373 modes->modes[n].stride = cpu_to_le32(qxl_modes[i].stride);
374 modes->modes[n].x_mili = cpu_to_le32(qxl_modes[i].x_mili);
375 modes->modes[n].y_mili = cpu_to_le32(qxl_modes[i].y_mili);
376 modes->modes[n].orientation = cpu_to_le32(qxl_modes[i].orientation);
377 n++;
378 }
379 modes->n_modes = cpu_to_le32(n);
a19cbfb3
GH		 380
381 ram_header_size = ALIGN(sizeof(QXLRam), 4096);
13d1fd44 382 surface0_area_size = ALIGN(d->vgamem_size, 4096);
a19cbfb3
GH		 383 num_pages = d->vga.vram_size;
384 num_pages -= ram_header_size;
385 num_pages -= surface0_area_size;
9efc2d8d 386 num_pages = num_pages / QXL_PAGE_SIZE;
a19cbfb3 387
876d5163
RK		 388 assert(ram_header_size + surface0_area_size <= d->vga.vram_size);
389
a19cbfb3
GH		 390 rom->draw_area_offset = cpu_to_le32(0);
391 rom->surface0_area_size = cpu_to_le32(surface0_area_size);
392 rom->pages_offset = cpu_to_le32(surface0_area_size);
393 rom->num_pages = cpu_to_le32(num_pages);
394 rom->ram_header_offset = cpu_to_le32(d->vga.vram_size - ram_header_size);
395
6f663d7b
GH		 396 if (d->xres && d->yres) {
397 /* needs linux kernel 4.12+ to work */
398 rom->client_monitors_config.count = 1;
399 rom->client_monitors_config.heads[0].left = 0;
400 rom->client_monitors_config.heads[0].top = 0;
401 rom->client_monitors_config.heads[0].right = cpu_to_le32(d->xres);
402 rom->client_monitors_config.heads[0].bottom = cpu_to_le32(d->yres);
403 rom->client_monitors_config_crc = qxl_crc32(
404 (const uint8_t *)&rom->client_monitors_config,
405 sizeof(rom->client_monitors_config));
406 }
407
a19cbfb3
GH		 408 d->shadow_rom = *rom;
409 d->rom = rom;
410 d->modes = modes;
411}
412
413static void init_qxl_ram(PCIQXLDevice *d)
414{
415 uint8_t *buf;
416 uint64_t *item;
417
418 buf = d->vga.vram_ptr;
419 d->ram = (QXLRam *)(buf + le32_to_cpu(d->shadow_rom.ram_header_offset));
420 d->ram->magic = cpu_to_le32(QXL_RAM_MAGIC);
421 d->ram->int_pending = cpu_to_le32(0);
422 d->ram->int_mask = cpu_to_le32(0);
9f0f352d 423 d->ram->update_surface = 0;
329f97fc 424 d->ram->monitors_config = 0;
a19cbfb3
GH		 425 SPICE_RING_INIT(&d->ram->cmd_ring);
426 SPICE_RING_INIT(&d->ram->cursor_ring);
427 SPICE_RING_INIT(&d->ram->release_ring);
0b81c478
AL		 428 SPICE_RING_PROD_ITEM(d, &d->ram->release_ring, item);
429 assert(item);
a19cbfb3
GH		 430 *item = 0;
431 qxl_ring_set_dirty(d);
432}
433
434/* can be called from spice server thread context */
b1950430 435static void qxl_set_dirty(MemoryRegion *mr, ram_addr_t addr, ram_addr_t end)
a19cbfb3 436{
fd4aa979 437 memory_region_set_dirty(mr, addr, end - addr);
a19cbfb3
GH		 438}
439
440static void qxl_rom_set_dirty(PCIQXLDevice *qxl)
441{
b1950430 442 qxl_set_dirty(&qxl->rom_bar, 0, qxl->rom_size);
a19cbfb3
GH		 443}
444
445/* called from spice server thread context only */
446static void qxl_ram_set_dirty(PCIQXLDevice *qxl, void *ptr)
447{
a19cbfb3
GH		 448 void *base = qxl->vga.vram_ptr;
449 intptr_t offset;
450
451 offset = ptr - base;
a19cbfb3 452 assert(offset < qxl->vga.vram_size);
b0297b4a 453 qxl_set_dirty(&qxl->vga.vram, offset, offset + 3);
a19cbfb3
GH		 454}
455
456/* can be called from spice server thread context */
457static void qxl_ring_set_dirty(PCIQXLDevice *qxl)
458{
b1950430
AK		 459 ram_addr_t addr = qxl->shadow_rom.ram_header_offset;
460 ram_addr_t end = qxl->vga.vram_size;
461 qxl_set_dirty(&qxl->vga.vram, addr, end);
a19cbfb3
GH		 462}
463
464/*
465 * keep track of some command state, for savevm/loadvm.
466 * called from spice server thread context only
467 */
fae2afb1 468static int qxl_track_command(PCIQXLDevice *qxl, struct QXLCommandExt *ext)
a19cbfb3
GH		 469{
470 switch (le32_to_cpu(ext->cmd.type)) {
471 case QXL_CMD_SURFACE:
472 {
473 QXLSurfaceCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id);
fae2afb1
AL		 474
475 if (!cmd) {
476 return 1;
477 }
a19cbfb3 478 uint32_t id = le32_to_cpu(cmd->surface_id);
47eddfbf 479
ddd8fdc7 480 if (id >= qxl->ssd.num_surfaces) {
0a530548 481 qxl_set_guest_bug(qxl, "QXL_CMD_SURFACE id %d >= %d", id,
ddd8fdc7 482 qxl->ssd.num_surfaces);
47eddfbf
AL		 483 return 1;
484 }
48f4ba67
AL		 485 if (cmd->type == QXL_SURFACE_CMD_CREATE &&
486 (cmd->u.surface_create.stride & 0x03) != 0) {
487 qxl_set_guest_bug(qxl, "QXL_CMD_SURFACE stride = %d %% 4 != 0\n",
488 cmd->u.surface_create.stride);
489 return 1;
490 }
14898cf6 491 qemu_mutex_lock(&qxl->track_lock);
a19cbfb3
GH		 492 if (cmd->type == QXL_SURFACE_CMD_CREATE) {
493 qxl->guest_surfaces.cmds[id] = ext->cmd.data;
494 qxl->guest_surfaces.count++;
495 if (qxl->guest_surfaces.max < qxl->guest_surfaces.count)
496 qxl->guest_surfaces.max = qxl->guest_surfaces.count;
497 }
498 if (cmd->type == QXL_SURFACE_CMD_DESTROY) {
499 qxl->guest_surfaces.cmds[id] = 0;
500 qxl->guest_surfaces.count--;
501 }
14898cf6 502 qemu_mutex_unlock(&qxl->track_lock);
a19cbfb3
GH		 503 break;
504 }
505 case QXL_CMD_CURSOR:
506 {
507 QXLCursorCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id);
fae2afb1
AL		 508
509 if (!cmd) {
510 return 1;
511 }
a19cbfb3 512 if (cmd->type == QXL_CURSOR_SET) {
30f6da66 513 qemu_mutex_lock(&qxl->track_lock);
a19cbfb3 514 qxl->guest_cursor = ext->cmd.data;
30f6da66 515 qemu_mutex_unlock(&qxl->track_lock);
a19cbfb3 516 }
dbb5fb8d
GH		 517 if (cmd->type == QXL_CURSOR_HIDE) {
518 qemu_mutex_lock(&qxl->track_lock);
519 qxl->guest_cursor = 0;
520 qemu_mutex_unlock(&qxl->track_lock);
521 }
a19cbfb3
GH		 522 break;
523 }
524 }
fae2afb1 525 return 0;
a19cbfb3
GH		 526}
527
528/* spice display interface callbacks */
529
530static void interface_attach_worker(QXLInstance *sin, QXLWorker *qxl_worker)
531{
532 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
533
c480bb7d 534 trace_qxl_interface_attach_worker(qxl->id);
a19cbfb3
GH		 535}
536
537static void interface_set_compression_level(QXLInstance *sin, int level)
538{
539 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
540
c480bb7d 541 trace_qxl_interface_set_compression_level(qxl->id, level);
a19cbfb3
GH		 542 qxl->shadow_rom.compression_level = cpu_to_le32(level);
543 qxl->rom->compression_level = cpu_to_le32(level);
544 qxl_rom_set_dirty(qxl);
545}
546
015e02f8 547#if SPICE_NEEDS_SET_MM_TIME
a19cbfb3
GH		 548static void interface_set_mm_time(QXLInstance *sin, uint32_t mm_time)
549{
550 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
551
641381c1
GH		 552 if (!qemu_spice_display_is_running(&qxl->ssd)) {
553 return;
554 }
555
c480bb7d 556 trace_qxl_interface_set_mm_time(qxl->id, mm_time);
a19cbfb3
GH		 557 qxl->shadow_rom.mm_clock = cpu_to_le32(mm_time);
558 qxl->rom->mm_clock = cpu_to_le32(mm_time);
559 qxl_rom_set_dirty(qxl);
560}
015e02f8 561#endif
a19cbfb3
GH		 562
563static void interface_get_init_info(QXLInstance *sin, QXLDevInitInfo *info)
564{
565 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
566
c480bb7d 567 trace_qxl_interface_get_init_info(qxl->id);
a19cbfb3
GH		 568 info->memslot_gen_bits = MEMSLOT_GENERATION_BITS;
569 info->memslot_id_bits = MEMSLOT_SLOT_BITS;
570 info->num_memslots = NUM_MEMSLOTS;
571 info->num_memslots_groups = NUM_MEMSLOTS_GROUPS;
572 info->internal_groupslot_id = 0;
9efc2d8d
GH		 573 info->qxl_ram_size =
574 le32_to_cpu(qxl->shadow_rom.num_pages) << QXL_PAGE_BITS;
ddd8fdc7 575 info->n_surfaces = qxl->ssd.num_surfaces;
a19cbfb3
GH		 576}
577
5b77870c
AL		 578static const char *qxl_mode_to_string(int mode)
579{
580 switch (mode) {
581 case QXL_MODE_COMPAT:
582 return "compat";
583 case QXL_MODE_NATIVE:
584 return "native";
585 case QXL_MODE_UNDEFINED:
586 return "undefined";
587 case QXL_MODE_VGA:
588 return "vga";
589 }
590 return "INVALID";
591}
592
8b92e298
AL		 593static const char *io_port_to_string(uint32_t io_port)
594{
595 if (io_port >= QXL_IO_RANGE_SIZE) {
596 return "out of range";
597 }
598 static const char *io_port_to_string[QXL_IO_RANGE_SIZE + 1] = {
599 [QXL_IO_NOTIFY_CMD] = "QXL_IO_NOTIFY_CMD",
600 [QXL_IO_NOTIFY_CURSOR] = "QXL_IO_NOTIFY_CURSOR",
601 [QXL_IO_UPDATE_AREA] = "QXL_IO_UPDATE_AREA",
602 [QXL_IO_UPDATE_IRQ] = "QXL_IO_UPDATE_IRQ",
603 [QXL_IO_NOTIFY_OOM] = "QXL_IO_NOTIFY_OOM",
604 [QXL_IO_RESET] = "QXL_IO_RESET",
605 [QXL_IO_SET_MODE] = "QXL_IO_SET_MODE",
606 [QXL_IO_LOG] = "QXL_IO_LOG",
607 [QXL_IO_MEMSLOT_ADD] = "QXL_IO_MEMSLOT_ADD",
608 [QXL_IO_MEMSLOT_DEL] = "QXL_IO_MEMSLOT_DEL",
609 [QXL_IO_DETACH_PRIMARY] = "QXL_IO_DETACH_PRIMARY",
610 [QXL_IO_ATTACH_PRIMARY] = "QXL_IO_ATTACH_PRIMARY",
611 [QXL_IO_CREATE_PRIMARY] = "QXL_IO_CREATE_PRIMARY",
612 [QXL_IO_DESTROY_PRIMARY] = "QXL_IO_DESTROY_PRIMARY",
613 [QXL_IO_DESTROY_SURFACE_WAIT] = "QXL_IO_DESTROY_SURFACE_WAIT",
614 [QXL_IO_DESTROY_ALL_SURFACES] = "QXL_IO_DESTROY_ALL_SURFACES",
8b92e298
AL		 615 [QXL_IO_UPDATE_AREA_ASYNC] = "QXL_IO_UPDATE_AREA_ASYNC",
616 [QXL_IO_MEMSLOT_ADD_ASYNC] = "QXL_IO_MEMSLOT_ADD_ASYNC",
617 [QXL_IO_CREATE_PRIMARY_ASYNC] = "QXL_IO_CREATE_PRIMARY_ASYNC",
618 [QXL_IO_DESTROY_PRIMARY_ASYNC] = "QXL_IO_DESTROY_PRIMARY_ASYNC",
619 [QXL_IO_DESTROY_SURFACE_ASYNC] = "QXL_IO_DESTROY_SURFACE_ASYNC",
620 [QXL_IO_DESTROY_ALL_SURFACES_ASYNC]
621 = "QXL_IO_DESTROY_ALL_SURFACES_ASYNC",
622 [QXL_IO_FLUSH_SURFACES_ASYNC] = "QXL_IO_FLUSH_SURFACES_ASYNC",
623 [QXL_IO_FLUSH_RELEASE] = "QXL_IO_FLUSH_RELEASE",
020af1c4 624 [QXL_IO_MONITORS_CONFIG_ASYNC] = "QXL_IO_MONITORS_CONFIG_ASYNC",
8b92e298
AL		 625 };
626 return io_port_to_string[io_port];
627}
628
a19cbfb3
GH		 629/* called from spice server thread context only */
630static int interface_get_command(QXLInstance *sin, struct QXLCommandExt *ext)
631{
632 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
633 SimpleSpiceUpdate *update;
634 QXLCommandRing *ring;
635 QXLCommand *cmd;
e0c64d08 636 int notify, ret;
a19cbfb3 637
c480bb7d
AL		 638 trace_qxl_ring_command_check(qxl->id, qxl_mode_to_string(qxl->mode));
639
a19cbfb3
GH		 640 switch (qxl->mode) {
641 case QXL_MODE_VGA:
e0c64d08
GH		 642 ret = false;
643 qemu_mutex_lock(&qxl->ssd.lock);
b1af98ba
GH		 644 update = QTAILQ_FIRST(&qxl->ssd.updates);
645 if (update != NULL) {
646 QTAILQ_REMOVE(&qxl->ssd.updates, update, next);
e0c64d08
GH		 647 *ext = update->ext;
648 ret = true;
a19cbfb3 649 }
e0c64d08 650 qemu_mutex_unlock(&qxl->ssd.lock);
212496c9 651 if (ret) {
c480bb7d 652 trace_qxl_ring_command_get(qxl->id, qxl_mode_to_string(qxl->mode));
212496c9
AL		 653 qxl_log_command(qxl, "vga", ext);
654 }
e0c64d08 655 return ret;
a19cbfb3
GH		 656 case QXL_MODE_COMPAT:
657 case QXL_MODE_NATIVE:
658 case QXL_MODE_UNDEFINED:
a19cbfb3 659 ring = &qxl->ram->cmd_ring;
087e6a42 660 if (qxl->guest_bug || SPICE_RING_IS_EMPTY(ring)) {
a19cbfb3
GH		 661 return false;
662 }
0b81c478
AL		 663 SPICE_RING_CONS_ITEM(qxl, ring, cmd);
664 if (!cmd) {
665 return false;
666 }
a19cbfb3
GH		 667 ext->cmd = *cmd;
668 ext->group_id = MEMSLOT_GROUP_GUEST;
669 ext->flags = qxl->cmdflags;
670 SPICE_RING_POP(ring, notify);
671 qxl_ring_set_dirty(qxl);
672 if (notify) {
673 qxl_send_events(qxl, QXL_INTERRUPT_DISPLAY);
674 }
675 qxl->guest_primary.commands++;
676 qxl_track_command(qxl, ext);
677 qxl_log_command(qxl, "cmd", ext);
86dbcdd9
GH		 678 {
679 /*
680 * Windows 8 drivers place qxl commands in the vram
681 * (instead of the ram) bar. We can't live migrate such a
682 * guest, so add a migration blocker in case we detect
683 * this, to avoid triggering the assert in pre_save().
684 *
685 * https://cgit.freedesktop.org/spice/win32/qxl-wddm-dod/commit/?id=f6e099db39e7d0787f294d5fd0dce328b5210faa
686 */
687 void *msg = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id);
688 if (msg != NULL && (
689 msg < (void *)qxl->vga.vram_ptr ||
690 msg > ((void *)qxl->vga.vram_ptr + qxl->vga.vram_size))) {
691 if (!qxl->migration_blocker) {
692 Error *local_err = NULL;
693 error_setg(&qxl->migration_blocker,
694 "qxl: guest bug: command not in ram bar");
695 migrate_add_blocker(qxl->migration_blocker, &local_err);
696 if (local_err) {
697 error_report_err(local_err);
698 }
699 }
700 }
701 }
0b81c478 702 trace_qxl_ring_command_get(qxl->id, qxl_mode_to_string(qxl->mode));
a19cbfb3
GH		 703 return true;
704 default:
705 return false;
706 }
707}
708
709/* called from spice server thread context only */
710static int interface_req_cmd_notification(QXLInstance *sin)
711{
712 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
713 int wait = 1;
714
c480bb7d 715 trace_qxl_ring_command_req_notification(qxl->id);
a19cbfb3
GH		 716 switch (qxl->mode) {
717 case QXL_MODE_COMPAT:
718 case QXL_MODE_NATIVE:
719 case QXL_MODE_UNDEFINED:
720 SPICE_RING_CONS_WAIT(&qxl->ram->cmd_ring, wait);
721 qxl_ring_set_dirty(qxl);
722 break;
723 default:
724 /* nothing */
725 break;
726 }
727 return wait;
728}
729
730/* called from spice server thread context only */
731static inline void qxl_push_free_res(PCIQXLDevice *d, int flush)
732{
733 QXLReleaseRing *ring = &d->ram->release_ring;
734 uint64_t *item;
735 int notify;
736
737#define QXL_FREE_BUNCH_SIZE 32
738
739 if (ring->prod - ring->cons + 1 == ring->num_items) {
740 /* ring full -- can't push */
741 return;
742 }
743 if (!flush && d->oom_running) {
744 /* collect everything from oom handler before pushing */
745 return;
746 }
747 if (!flush && d->num_free_res < QXL_FREE_BUNCH_SIZE) {
748 /* collect a bit more before pushing */
749 return;
750 }
751
752 SPICE_RING_PUSH(ring, notify);
c480bb7d
AL		 753 trace_qxl_ring_res_push(d->id, qxl_mode_to_string(d->mode),
754 d->guest_surfaces.count, d->num_free_res,
755 d->last_release, notify ? "yes" : "no");
756 trace_qxl_ring_res_push_rest(d->id, ring->prod - ring->cons,
757 ring->num_items, ring->prod, ring->cons);
a19cbfb3
GH		 758 if (notify) {
759 qxl_send_events(d, QXL_INTERRUPT_DISPLAY);
760 }
0b81c478
AL		 761 SPICE_RING_PROD_ITEM(d, ring, item);
762 if (!item) {
763 return;
764 }
a19cbfb3
GH		 765 *item = 0;
766 d->num_free_res = 0;
767 d->last_release = NULL;
768 qxl_ring_set_dirty(d);
769}
770
771/* called from spice server thread context only */
772static void interface_release_resource(QXLInstance *sin,
c9f88ce3 773 QXLReleaseInfoExt ext)
a19cbfb3
GH		 774{
775 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
776 QXLReleaseRing *ring;
777 uint64_t *item, id;
778
779 if (ext.group_id == MEMSLOT_GROUP_HOST) {
780 /* host group -> vga mode update request */
e8e23b7d 781 QXLCommandExt *cmdext = (void *)(intptr_t)(ext.info->id);
5643fc01
GH		 782 SimpleSpiceUpdate *update;
783 g_assert(cmdext->cmd.type == QXL_CMD_DRAW);
784 update = container_of(cmdext, SimpleSpiceUpdate, ext);
785 qemu_spice_destroy_update(&qxl->ssd, update);
a19cbfb3
GH		 786 return;
787 }
788
789 /*
790 * ext->info points into guest-visible memory
791 * pci bar 0, $command.release_info
792 */
793 ring = &qxl->ram->release_ring;
0b81c478
AL		 794 SPICE_RING_PROD_ITEM(qxl, ring, item);
795 if (!item) {
796 return;
797 }
a19cbfb3
GH		 798 if (*item == 0) {
799 /* stick head into the ring */
800 id = ext.info->id;
801 ext.info->next = 0;
802 qxl_ram_set_dirty(qxl, &ext.info->next);
803 *item = id;
804 qxl_ring_set_dirty(qxl);
805 } else {
806 /* append item to the list */
807 qxl->last_release->next = ext.info->id;
808 qxl_ram_set_dirty(qxl, &qxl->last_release->next);
809 ext.info->next = 0;
810 qxl_ram_set_dirty(qxl, &ext.info->next);
811 }
812 qxl->last_release = ext.info;
813 qxl->num_free_res++;
c480bb7d 814 trace_qxl_ring_res_put(qxl->id, qxl->num_free_res);
a19cbfb3
GH		 815 qxl_push_free_res(qxl, 0);
816}
817
818/* called from spice server thread context only */
819static int interface_get_cursor_command(QXLInstance *sin, struct QXLCommandExt *ext)
820{
821 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
822 QXLCursorRing *ring;
823 QXLCommand *cmd;
824 int notify;
825
c480bb7d
AL		 826 trace_qxl_ring_cursor_check(qxl->id, qxl_mode_to_string(qxl->mode));
827
a19cbfb3
GH		 828 switch (qxl->mode) {
829 case QXL_MODE_COMPAT:
830 case QXL_MODE_NATIVE:
831 case QXL_MODE_UNDEFINED:
832 ring = &qxl->ram->cursor_ring;
833 if (SPICE_RING_IS_EMPTY(ring)) {
834 return false;
835 }
0b81c478
AL		 836 SPICE_RING_CONS_ITEM(qxl, ring, cmd);
837 if (!cmd) {
838 return false;
839 }
a19cbfb3
GH		 840 ext->cmd = *cmd;
841 ext->group_id = MEMSLOT_GROUP_GUEST;
842 ext->flags = qxl->cmdflags;
843 SPICE_RING_POP(ring, notify);
844 qxl_ring_set_dirty(qxl);
845 if (notify) {
846 qxl_send_events(qxl, QXL_INTERRUPT_CURSOR);
847 }
848 qxl->guest_primary.commands++;
849 qxl_track_command(qxl, ext);
850 qxl_log_command(qxl, "csr", ext);
60e94e43 851 if (qxl->have_vga) {
a19cbfb3
GH		 852 qxl_render_cursor(qxl, ext);
853 }
c480bb7d 854 trace_qxl_ring_cursor_get(qxl->id, qxl_mode_to_string(qxl->mode));
a19cbfb3
GH		 855 return true;
856 default:
857 return false;
858 }
859}
860
861/* called from spice server thread context only */
862static int interface_req_cursor_notification(QXLInstance *sin)
863{
864 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
865 int wait = 1;
866
c480bb7d 867 trace_qxl_ring_cursor_req_notification(qxl->id);
a19cbfb3
GH		 868 switch (qxl->mode) {
869 case QXL_MODE_COMPAT:
870 case QXL_MODE_NATIVE:
871 case QXL_MODE_UNDEFINED:
872 SPICE_RING_CONS_WAIT(&qxl->ram->cursor_ring, wait);
873 qxl_ring_set_dirty(qxl);
874 break;
875 default:
876 /* nothing */
877 break;
878 }
879 return wait;
880}
881
882/* called from spice server thread context */
883static void interface_notify_update(QXLInstance *sin, uint32_t update_id)
884{
baeae407
AL		 885 /*
886 * Called by spice-server as a result of a QXL_CMD_UPDATE which is not in
887 * use by xf86-video-qxl and is defined out in the qxl windows driver.
888 * Probably was at some earlier version that is prior to git start (2009),
889 * and is still guest trigerrable.
890 */
891 fprintf(stderr, "%s: deprecated\n", __func__);
a19cbfb3
GH		 892}
893
894/* called from spice server thread context only */
895static int interface_flush_resources(QXLInstance *sin)
896{
897 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
898 int ret;
899
a19cbfb3
GH		 900 ret = qxl->num_free_res;
901 if (ret) {
902 qxl_push_free_res(qxl, 1);
903 }
904 return ret;
905}
906
5ff4e36c
AL		 907static void qxl_create_guest_primary_complete(PCIQXLDevice *d);
908
5ff4e36c 909/* called from spice server thread context only */
2e1a98c9 910static void interface_async_complete_io(PCIQXLDevice *qxl, QXLCookie *cookie)
5ff4e36c 911{
5ff4e36c
AL		 912 uint32_t current_async;
913
914 qemu_mutex_lock(&qxl->async_lock);
915 current_async = qxl->current_async;
916 qxl->current_async = QXL_UNDEFINED_IO;
917 qemu_mutex_unlock(&qxl->async_lock);
918
c480bb7d 919 trace_qxl_interface_async_complete_io(qxl->id, current_async, cookie);
2e1a98c9
AL		 920 if (!cookie) {
921 fprintf(stderr, "qxl: %s: error, cookie is NULL\n", __func__);
922 return;
923 }
924 if (cookie && current_async != cookie->io) {
925 fprintf(stderr,
2fce7edf
AL		 926 "qxl: %s: error: current_async = %d != %"
927 PRId64 " = cookie->io\n", __func__, current_async, cookie->io);
2e1a98c9 928 }
5ff4e36c 929 switch (current_async) {
81fb6f15
AL		 930 case QXL_IO_MEMSLOT_ADD_ASYNC:
931 case QXL_IO_DESTROY_PRIMARY_ASYNC:
932 case QXL_IO_UPDATE_AREA_ASYNC:
933 case QXL_IO_FLUSH_SURFACES_ASYNC:
020af1c4 934 case QXL_IO_MONITORS_CONFIG_ASYNC:
81fb6f15 935 break;
5ff4e36c
AL		 936 case QXL_IO_CREATE_PRIMARY_ASYNC:
937 qxl_create_guest_primary_complete(qxl);
938 break;
939 case QXL_IO_DESTROY_ALL_SURFACES_ASYNC:
940 qxl_spice_destroy_surfaces_complete(qxl);
941 break;
942 case QXL_IO_DESTROY_SURFACE_ASYNC:
2e1a98c9 943 qxl_spice_destroy_surface_wait_complete(qxl, cookie->u.surface_id);
5ff4e36c 944 break;
81fb6f15
AL		 945 default:
946 fprintf(stderr, "qxl: %s: unexpected current_async %d\n", __func__,
947 current_async);
5ff4e36c
AL		 948 }
949 qxl_send_events(qxl, QXL_INTERRUPT_IO_CMD);
950}
951
81fb6f15
AL		 952/* called from spice server thread context only */
953static void interface_update_area_complete(QXLInstance *sin,
954 uint32_t surface_id,
955 QXLRect *dirty, uint32_t num_updated_rects)
956{
957 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
958 int i;
959 int qxl_i;
960
961 qemu_mutex_lock(&qxl->ssd.lock);
2f5ae772
GH		 962 if (surface_id != 0 || !num_updated_rects ||
963 !qxl->render_update_cookie_num) {
81fb6f15
AL		 964 qemu_mutex_unlock(&qxl->ssd.lock);
965 return;
966 }
c480bb7d
AL		 967 trace_qxl_interface_update_area_complete(qxl->id, surface_id, dirty->left,
968 dirty->right, dirty->top, dirty->bottom);
969 trace_qxl_interface_update_area_complete_rest(qxl->id, num_updated_rects);
81fb6f15
AL		 970 if (qxl->num_dirty_rects + num_updated_rects > QXL_NUM_DIRTY_RECTS) {
971 /*
972 * overflow - treat this as a full update. Not expected to be common.
973 */
c480bb7d
AL		 974 trace_qxl_interface_update_area_complete_overflow(qxl->id,
975 QXL_NUM_DIRTY_RECTS);
81fb6f15
AL		 976 qxl->guest_primary.resized = 1;
977 }
978 if (qxl->guest_primary.resized) {
979 /*
980 * Don't bother copying or scheduling the bh since we will flip
981 * the whole area anyway on completion of the update_area async call
982 */
983 qemu_mutex_unlock(&qxl->ssd.lock);
984 return;
985 }
986 qxl_i = qxl->num_dirty_rects;
987 for (i = 0; i < num_updated_rects; i++) {
988 qxl->dirty[qxl_i++] = dirty[i];
989 }
990 qxl->num_dirty_rects += num_updated_rects;
c480bb7d
AL		 991 trace_qxl_interface_update_area_complete_schedule_bh(qxl->id,
992 qxl->num_dirty_rects);
81fb6f15
AL		 993 qemu_bh_schedule(qxl->update_area_bh);
994 qemu_mutex_unlock(&qxl->ssd.lock);
995}
996
2e1a98c9
AL		 997/* called from spice server thread context only */
998static void interface_async_complete(QXLInstance *sin, uint64_t cookie_token)
999{
1000 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
5dba0d45 1001 QXLCookie *cookie = (QXLCookie *)(uintptr_t)cookie_token;
2e1a98c9
AL		 1002
1003 switch (cookie->type) {
1004 case QXL_COOKIE_TYPE_IO:
1005 interface_async_complete_io(qxl, cookie);
81fb6f15
AL		 1006 g_free(cookie);
1007 break;
1008 case QXL_COOKIE_TYPE_RENDER_UPDATE_AREA:
1009 qxl_render_update_area_done(qxl, cookie);
2e1a98c9 1010 break;
020af1c4
AL		 1011 case QXL_COOKIE_TYPE_POST_LOAD_MONITORS_CONFIG:
1012 break;
2e1a98c9
AL		 1013 default:
1014 fprintf(stderr, "qxl: %s: unexpected cookie type %d\n",
1015 __func__, cookie->type);
81fb6f15 1016 g_free(cookie);
2e1a98c9 1017 }
2e1a98c9
AL		 1018}
1019
c10018d6
SSP		 1020/* called from spice server thread context only */
1021static void interface_set_client_capabilities(QXLInstance *sin,
1022 uint8_t client_present,
1023 uint8_t caps[58])
1024{
1025 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
1026
e0ac6097
AL		 1027 if (qxl->revision < 4) {
1028 trace_qxl_set_client_capabilities_unsupported_by_revision(qxl->id,
1029 qxl->revision);
1030 return;
1031 }
1032
ab902981
HG		 1033 if (runstate_check(RUN_STATE_INMIGRATE) ||
1034 runstate_check(RUN_STATE_POSTMIGRATE)) {
1035 return;
1036 }
1037
c10018d6 1038 qxl->shadow_rom.client_present = client_present;
08688af0
MA		 1039 memcpy(qxl->shadow_rom.client_capabilities, caps,
1040 sizeof(qxl->shadow_rom.client_capabilities));
c10018d6 1041 qxl->rom->client_present = client_present;
08688af0
MA		 1042 memcpy(qxl->rom->client_capabilities, caps,
1043 sizeof(qxl->rom->client_capabilities));
c10018d6
SSP		 1044 qxl_rom_set_dirty(qxl);
1045
1046 qxl_send_events(qxl, QXL_INTERRUPT_CLIENT);
1047}
1048
6c756502
CF		 1049static bool qxl_rom_monitors_config_changed(QXLRom *rom,
1050 VDAgentMonitorsConfig *monitors_config,
1051 unsigned int max_outputs)
1052{
1053 int i;
1054 unsigned int monitors_count;
1055
1056 monitors_count = MIN(monitors_config->num_of_monitors, max_outputs);
1057
1058 if (rom->client_monitors_config.count != monitors_count) {
1059 return true;
1060 }
1061
1062 for (i = 0 ; i < rom->client_monitors_config.count ; ++i) {
1063 VDAgentMonConfig *monitor = &monitors_config->monitors[i];
1064 QXLURect *rect = &rom->client_monitors_config.heads[i];
1065 /* monitor->depth ignored */
1066 if ((rect->left != monitor->x) ||
1067 (rect->top != monitor->y) ||
1068 (rect->right != monitor->x + monitor->width) ||
1069 (rect->bottom != monitor->y + monitor->height)) {
1070 return true;
1071 }
1072 }
1073
1074 return false;
1075}
1076
a639ab04
AL		 1077/* called from main context only */
1078static int interface_client_monitors_config(QXLInstance *sin,
1079 VDAgentMonitorsConfig *monitors_config)
1080{
1081 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
1082 QXLRom *rom = memory_region_get_ram_ptr(&qxl->rom_bar);
1083 int i;
567161fd 1084 unsigned max_outputs = ARRAY_SIZE(rom->client_monitors_config.heads);
6c756502 1085 bool config_changed = false;
a639ab04 1086
e0ac6097
AL		 1087 if (qxl->revision < 4) {
1088 trace_qxl_client_monitors_config_unsupported_by_device(qxl->id,
1089 qxl->revision);
1090 return 0;
1091 }
a639ab04
AL		 1092 /*
1093 * Older windows drivers set int_mask to 0 when their ISR is called,
1094 * then later set it to ~0. So it doesn't relate to the actual interrupts
1095 * handled. However, they are old, so clearly they don't support this
1096 * interrupt
1097 */
1098 if (qxl->ram->int_mask == 0 || qxl->ram->int_mask == ~0 ||
1099 !(qxl->ram->int_mask & QXL_INTERRUPT_CLIENT_MONITORS_CONFIG)) {
1100 trace_qxl_client_monitors_config_unsupported_by_guest(qxl->id,
1101 qxl->ram->int_mask,
1102 monitors_config);
1103 return 0;
1104 }
1105 if (!monitors_config) {
1106 return 1;
1107 }
567161fd
FZ		 1108
1109#if SPICE_SERVER_VERSION >= 0x000c06 /* release 0.12.6 */
1110 /* limit number of outputs based on setting limit */
1111 if (qxl->max_outputs && qxl->max_outputs <= max_outputs) {
1112 max_outputs = qxl->max_outputs;
1113 }
1114#endif
1115
6c756502
CF		 1116 config_changed = qxl_rom_monitors_config_changed(rom,
1117 monitors_config,
1118 max_outputs);
1119
a639ab04
AL		 1120 memset(&rom->client_monitors_config, 0,
1121 sizeof(rom->client_monitors_config));
1122 rom->client_monitors_config.count = monitors_config->num_of_monitors;
1123 /* monitors_config->flags ignored */
567161fd 1124 if (rom->client_monitors_config.count >= max_outputs) {
a639ab04
AL		 1125 trace_qxl_client_monitors_config_capped(qxl->id,
1126 monitors_config->num_of_monitors,
567161fd
FZ		 1127 max_outputs);
1128 rom->client_monitors_config.count = max_outputs;
a639ab04
AL		 1129 }
1130 for (i = 0 ; i < rom->client_monitors_config.count ; ++i) {
1131 VDAgentMonConfig *monitor = &monitors_config->monitors[i];
1132 QXLURect *rect = &rom->client_monitors_config.heads[i];
1133 /* monitor->depth ignored */
1134 rect->left = monitor->x;
1135 rect->top = monitor->y;
1136 rect->right = monitor->x + monitor->width;
1137 rect->bottom = monitor->y + monitor->height;
1138 }
1139 rom->client_monitors_config_crc = qxl_crc32(
1140 (const uint8_t *)&rom->client_monitors_config,
1141 sizeof(rom->client_monitors_config));
1142 trace_qxl_client_monitors_config_crc(qxl->id,
1143 sizeof(rom->client_monitors_config),
1144 rom->client_monitors_config_crc);
1145
1146 trace_qxl_interrupt_client_monitors_config(qxl->id,
1147 rom->client_monitors_config.count,
1148 rom->client_monitors_config.heads);
6c756502
CF		 1149 if (config_changed) {
1150 qxl_send_events(qxl, QXL_INTERRUPT_CLIENT_MONITORS_CONFIG);
1151 }
a639ab04
AL		 1152 return 1;
1153}
a639ab04 1154
a19cbfb3
GH		 1155static const QXLInterface qxl_interface = {
1156 .base.type = SPICE_INTERFACE_QXL,
1157 .base.description = "qxl gpu",
1158 .base.major_version = SPICE_INTERFACE_QXL_MAJOR,
1159 .base.minor_version = SPICE_INTERFACE_QXL_MINOR,
1160
1161 .attache_worker = interface_attach_worker,
1162 .set_compression_level = interface_set_compression_level,
015e02f8 1163#if SPICE_NEEDS_SET_MM_TIME
a19cbfb3 1164 .set_mm_time = interface_set_mm_time,
015e02f8 1165#endif
a19cbfb3
GH		 1166 .get_init_info = interface_get_init_info,
1167
1168 /* the callbacks below are called from spice server thread context */
1169 .get_command = interface_get_command,
1170 .req_cmd_notification = interface_req_cmd_notification,
1171 .release_resource = interface_release_resource,
1172 .get_cursor_command = interface_get_cursor_command,
1173 .req_cursor_notification = interface_req_cursor_notification,
1174 .notify_update = interface_notify_update,
1175 .flush_resources = interface_flush_resources,
5ff4e36c 1176 .async_complete = interface_async_complete,
81fb6f15 1177 .update_area_complete = interface_update_area_complete,
c10018d6 1178 .set_client_capabilities = interface_set_client_capabilities,
a639ab04 1179 .client_monitors_config = interface_client_monitors_config,
a19cbfb3
GH		 1180};
1181
15162335
GH		 1182static const GraphicHwOps qxl_ops = {
1183 .gfx_update = qxl_hw_update,
1184};
1185
a19cbfb3
GH		 1186static void qxl_enter_vga_mode(PCIQXLDevice *d)
1187{
1188 if (d->mode == QXL_MODE_VGA) {
1189 return;
1190 }
c480bb7d 1191 trace_qxl_enter_vga_mode(d->id);
0a2b5e3a 1192 spice_qxl_driver_unload(&d->ssd.qxl);
15162335 1193 graphic_console_set_hwops(d->ssd.dcl.con, d->vga.hw_ops, &d->vga);
3dcadce5 1194 update_displaychangelistener(&d->ssd.dcl, GUI_REFRESH_INTERVAL_DEFAULT);
a19cbfb3
GH		 1195 qemu_spice_create_host_primary(&d->ssd);
1196 d->mode = QXL_MODE_VGA;
a703d3ae 1197 qemu_spice_display_switch(&d->ssd, d->ssd.ds);
0f7bfd81 1198 vga_dirty_log_start(&d->vga);
1dbfa005 1199 graphic_hw_update(d->vga.con);
a19cbfb3
GH		 1200}
1201
1202static void qxl_exit_vga_mode(PCIQXLDevice *d)
1203{
1204 if (d->mode != QXL_MODE_VGA) {
1205 return;
1206 }
c480bb7d 1207 trace_qxl_exit_vga_mode(d->id);
15162335 1208 graphic_console_set_hwops(d->ssd.dcl.con, &qxl_ops, d);
3dcadce5 1209 update_displaychangelistener(&d->ssd.dcl, GUI_REFRESH_INTERVAL_IDLE);
0f7bfd81 1210 vga_dirty_log_stop(&d->vga);
5ff4e36c 1211 qxl_destroy_primary(d, QXL_SYNC);
a19cbfb3
GH		 1212}
1213
40010aea 1214static void qxl_update_irq(PCIQXLDevice *d)
a19cbfb3
GH		 1215{
1216 uint32_t pending = le32_to_cpu(d->ram->int_pending);
1217 uint32_t mask = le32_to_cpu(d->ram->int_mask);
1218 int level = !!(pending & mask);
9e64f8a3 1219 pci_set_irq(&d->pci, level);
a19cbfb3
GH		 1220 qxl_ring_set_dirty(d);
1221}
1222
a19cbfb3
GH		 1223static void qxl_check_state(PCIQXLDevice *d)
1224{
1225 QXLRam *ram = d->ram;
71d388d4 1226 int spice_display_running = qemu_spice_display_is_running(&d->ssd);
a19cbfb3 1227
71d388d4
YH		 1228 assert(!spice_display_running || SPICE_RING_IS_EMPTY(&ram->cmd_ring));
1229 assert(!spice_display_running || SPICE_RING_IS_EMPTY(&ram->cursor_ring));
a19cbfb3
GH		 1230}
1231
1232static void qxl_reset_state(PCIQXLDevice *d)
1233{
a19cbfb3
GH		 1234 QXLRom *rom = d->rom;
1235
be48e995 1236 qxl_check_state(d);
a19cbfb3
GH		 1237 d->shadow_rom.update_id = cpu_to_le32(0);
1238 *rom = d->shadow_rom;
1239 qxl_rom_set_dirty(d);
1240 init_qxl_ram(d);
1241 d->num_free_res = 0;
1242 d->last_release = NULL;
1243 memset(&d->ssd.dirty, 0, sizeof(d->ssd.dirty));
f06b8521 1244 qxl_update_irq(d);
a19cbfb3
GH		 1245}
1246
1247static void qxl_soft_reset(PCIQXLDevice *d)
1248{
c480bb7d 1249 trace_qxl_soft_reset(d->id);
a19cbfb3 1250 qxl_check_state(d);
087e6a42 1251 qxl_clear_guest_bug(d);
05fa1c74 1252 qemu_mutex_lock(&d->async_lock);
a5f68c22 1253 d->current_async = QXL_UNDEFINED_IO;
05fa1c74 1254 qemu_mutex_unlock(&d->async_lock);
a19cbfb3 1255
60e94e43 1256 if (d->have_vga) {
a19cbfb3
GH		 1257 qxl_enter_vga_mode(d);
1258 } else {
1259 d->mode = QXL_MODE_UNDEFINED;
1260 }
1261}
1262
1263static void qxl_hard_reset(PCIQXLDevice *d, int loadvm)
1264{
75c70e37
GH		 1265 bool startstop = qemu_spice_display_is_running(&d->ssd);
1266
c480bb7d 1267 trace_qxl_hard_reset(d->id, loadvm);
a19cbfb3 1268
75c70e37
GH		 1269 if (startstop) {
1270 qemu_spice_display_stop();
1271 }
1272
aee32bf3
GH		 1273 qxl_spice_reset_cursor(d);
1274 qxl_spice_reset_image_cache(d);
a19cbfb3
GH		 1275 qxl_reset_surfaces(d);
1276 qxl_reset_memslots(d);
1277
1278 /* pre loadvm reset must not touch QXLRam. This lives in
1279 * device memory, is migrated together with RAM and thus
1280 * already loaded at this point */
1281 if (!loadvm) {
1282 qxl_reset_state(d);
1283 }
1284 qemu_spice_create_host_memslot(&d->ssd);
1285 qxl_soft_reset(d);
75c70e37 1286
86dbcdd9
GH		 1287 if (d->migration_blocker) {
1288 migrate_del_blocker(d->migration_blocker);
1289 error_free(d->migration_blocker);
1290 d->migration_blocker = NULL;
1291 }
1292
75c70e37
GH		 1293 if (startstop) {
1294 qemu_spice_display_start();
1295 }
a19cbfb3
GH		 1296}
1297
1298static void qxl_reset_handler(DeviceState *dev)
1299{
c69f6c7d 1300 PCIQXLDevice *d = PCI_QXL(PCI_DEVICE(dev));
c480bb7d 1301
a19cbfb3
GH		 1302 qxl_hard_reset(d, 0);
1303}
1304
1305static void qxl_vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
1306{
1307 VGACommonState *vga = opaque;
1308 PCIQXLDevice *qxl = container_of(vga, PCIQXLDevice, vga);
1309
c480bb7d 1310 trace_qxl_io_write_vga(qxl->id, qxl_mode_to_string(qxl->mode), addr, val);
a19cbfb3 1311 if (qxl->mode != QXL_MODE_VGA) {
5ff4e36c 1312 qxl_destroy_primary(qxl, QXL_SYNC);
a19cbfb3
GH		 1313 qxl_soft_reset(qxl);
1314 }
1315 vga_ioport_write(opaque, addr, val);
1316}
1317
f67ab77a
GH		 1318static const MemoryRegionPortio qxl_vga_portio_list[] = {
1319 { 0x04, 2, 1, .read = vga_ioport_read,
1320 .write = qxl_vga_ioport_write }, /* 3b4 */
1321 { 0x0a, 1, 1, .read = vga_ioport_read,
1322 .write = qxl_vga_ioport_write }, /* 3ba */
1323 { 0x10, 16, 1, .read = vga_ioport_read,
1324 .write = qxl_vga_ioport_write }, /* 3c0 */
1325 { 0x24, 2, 1, .read = vga_ioport_read,
1326 .write = qxl_vga_ioport_write }, /* 3d4 */
1327 { 0x2a, 1, 1, .read = vga_ioport_read,
1328 .write = qxl_vga_ioport_write }, /* 3da */
1329 PORTIO_END_OF_LIST(),
1330};
1331
e954ea28
AL		 1332static int qxl_add_memslot(PCIQXLDevice *d, uint32_t slot_id, uint64_t delta,
1333 qxl_async_io async)
a19cbfb3
GH		 1334{
1335 static const int regions[] = {
1336 QXL_RAM_RANGE_INDEX,
1337 QXL_VRAM_RANGE_INDEX,
6f2b175a 1338 QXL_VRAM64_RANGE_INDEX,
a19cbfb3
GH		 1339 };
1340 uint64_t guest_start;
1341 uint64_t guest_end;
1342 int pci_region;
1343 pcibus_t pci_start;
1344 pcibus_t pci_end;
3cb5158f 1345 MemoryRegion *mr;
a19cbfb3
GH		 1346 intptr_t virt_start;
1347 QXLDevMemSlot memslot;
1348 int i;
1349
1350 guest_start = le64_to_cpu(d->guest_slots[slot_id].slot.mem_start);
1351 guest_end = le64_to_cpu(d->guest_slots[slot_id].slot.mem_end);
1352
c480bb7d 1353 trace_qxl_memslot_add_guest(d->id, slot_id, guest_start, guest_end);
a19cbfb3 1354
e954ea28 1355 if (slot_id >= NUM_MEMSLOTS) {
0a530548 1356 qxl_set_guest_bug(d, "%s: slot_id >= NUM_MEMSLOTS %d >= %d", __func__,
e954ea28
AL		 1357 slot_id, NUM_MEMSLOTS);
1358 return 1;
1359 }
1360 if (guest_start > guest_end) {
0a530548 1361 qxl_set_guest_bug(d, "%s: guest_start > guest_end 0x%" PRIx64
e954ea28
AL		 1362 " > 0x%" PRIx64, __func__, guest_start, guest_end);
1363 return 1;
1364 }
a19cbfb3
GH		 1365
1366 for (i = 0; i < ARRAY_SIZE(regions); i++) {
1367 pci_region = regions[i];
1368 pci_start = d->pci.io_regions[pci_region].addr;
1369 pci_end = pci_start + d->pci.io_regions[pci_region].size;
1370 /* mapped? */
1371 if (pci_start == -1) {
1372 continue;
1373 }
1374 /* start address in range ? */
1375 if (guest_start < pci_start || guest_start > pci_end) {
1376 continue;
1377 }
1378 /* end address in range ? */
1379 if (guest_end > pci_end) {
1380 continue;
1381 }
1382 /* passed */
1383 break;
1384 }
e954ea28 1385 if (i == ARRAY_SIZE(regions)) {
0a530548 1386 qxl_set_guest_bug(d, "%s: finished loop without match", __func__);
e954ea28
AL		 1387 return 1;
1388 }
a19cbfb3
GH		 1389
1390 switch (pci_region) {
1391 case QXL_RAM_RANGE_INDEX:
3cb5158f 1392 mr = &d->vga.vram;
a19cbfb3
GH		 1393 break;
1394 case QXL_VRAM_RANGE_INDEX:
6f2b175a 1395 case 4 /* vram 64bit */:
3cb5158f 1396 mr = &d->vram_bar;
a19cbfb3
GH		 1397 break;
1398 default:
1399 /* should not happen */
0a530548 1400 qxl_set_guest_bug(d, "%s: pci_region = %d", __func__, pci_region);
e954ea28 1401 return 1;
a19cbfb3
GH		 1402 }
1403
3cb5158f 1404 virt_start = (intptr_t)memory_region_get_ram_ptr(mr);
a19cbfb3
GH		 1405 memslot.slot_id = slot_id;
1406 memslot.slot_group_id = MEMSLOT_GROUP_GUEST; /* guest group */
1407 memslot.virt_start = virt_start + (guest_start - pci_start);
1408 memslot.virt_end = virt_start + (guest_end - pci_start);
1409 memslot.addr_delta = memslot.virt_start - delta;
1410 memslot.generation = d->rom->slot_generation = 0;
1411 qxl_rom_set_dirty(d);
1412
5ff4e36c 1413 qemu_spice_add_memslot(&d->ssd, &memslot, async);
3cb5158f
GH		 1414 d->guest_slots[slot_id].mr = mr;
1415 d->guest_slots[slot_id].offset = memslot.virt_start - virt_start;
a19cbfb3
GH		 1416 d->guest_slots[slot_id].size = memslot.virt_end - memslot.virt_start;
1417 d->guest_slots[slot_id].delta = delta;
1418 d->guest_slots[slot_id].active = 1;
e954ea28 1419 return 0;
a19cbfb3
GH		 1420}
1421
1422static void qxl_del_memslot(PCIQXLDevice *d, uint32_t slot_id)
1423{
5c59d118 1424 qemu_spice_del_memslot(&d->ssd, MEMSLOT_GROUP_HOST, slot_id);
a19cbfb3
GH		 1425 d->guest_slots[slot_id].active = 0;
1426}
1427
1428static void qxl_reset_memslots(PCIQXLDevice *d)
1429{
aee32bf3 1430 qxl_spice_reset_memslots(d);
a19cbfb3
GH		 1431 memset(&d->guest_slots, 0, sizeof(d->guest_slots));
1432}
1433
1434static void qxl_reset_surfaces(PCIQXLDevice *d)
1435{
c480bb7d 1436 trace_qxl_reset_surfaces(d->id);
a19cbfb3 1437 d->mode = QXL_MODE_UNDEFINED;
5ff4e36c 1438 qxl_spice_destroy_surfaces(d, QXL_SYNC);
a19cbfb3
GH		 1439}
1440
e25139b3 1441/* can be also called from spice server thread context */
726bdf65
GH		 1442static bool qxl_get_check_slot_offset(PCIQXLDevice *qxl, QXLPHYSICAL pqxl,
1443 uint32_t *s, uint64_t *o)
a19cbfb3
GH		 1444{
1445 uint64_t phys = le64_to_cpu(pqxl);
1446 uint32_t slot = (phys >> (64 - 8)) & 0xff;
1447 uint64_t offset = phys & 0xffffffffffff;
1448
726bdf65
GH		 1449 if (slot >= NUM_MEMSLOTS) {
1450 qxl_set_guest_bug(qxl, "slot too large %d >= %d", slot,
1451 NUM_MEMSLOTS);
1452 return false;
1453 }
1454 if (!qxl->guest_slots[slot].active) {
1455 qxl_set_guest_bug(qxl, "inactive slot %d\n", slot);
1456 return false;
1457 }
1458 if (offset < qxl->guest_slots[slot].delta) {
1459 qxl_set_guest_bug(qxl,
0a530548 1460 "slot %d offset %"PRIu64" < delta %"PRIu64"\n",
4b635c59 1461 slot, offset, qxl->guest_slots[slot].delta);
726bdf65
GH		 1462 return false;
1463 }
1464 offset -= qxl->guest_slots[slot].delta;
1465 if (offset > qxl->guest_slots[slot].size) {
1466 qxl_set_guest_bug(qxl,
0a530548 1467 "slot %d offset %"PRIu64" > size %"PRIu64"\n",
4b635c59 1468 slot, offset, qxl->guest_slots[slot].size);
726bdf65
GH		 1469 return false;
1470 }
1471
1472 *s = slot;
1473 *o = offset;
1474 return true;
1475}
1476
1477/* can be also called from spice server thread context */
1478void *qxl_phys2virt(PCIQXLDevice *qxl, QXLPHYSICAL pqxl, int group_id)
1479{
1480 uint64_t offset;
1481 uint32_t slot;
3cb5158f 1482 void *ptr;
726bdf65
GH		 1483
1484 switch (group_id) {
1485 case MEMSLOT_GROUP_HOST:
1486 offset = le64_to_cpu(pqxl) & 0xffffffffffff;
1487 return (void *)(intptr_t)offset;
1488 case MEMSLOT_GROUP_GUEST:
1489 if (!qxl_get_check_slot_offset(qxl, pqxl, &slot, &offset)) {
4b635c59
AL		 1490 return NULL;
1491 }
3cb5158f
GH		 1492 ptr = memory_region_get_ram_ptr(qxl->guest_slots[slot].mr);
1493 ptr += qxl->guest_slots[slot].offset;
1494 ptr += offset;
1495 return ptr;
a19cbfb3 1496 }
4b635c59 1497 return NULL;
a19cbfb3
GH		 1498}
1499
5ff4e36c
AL		 1500static void qxl_create_guest_primary_complete(PCIQXLDevice *qxl)
1501{
1502 /* for local rendering */
1503 qxl_render_resize(qxl);
1504}
1505
1506static void qxl_create_guest_primary(PCIQXLDevice *qxl, int loadvm,
1507 qxl_async_io async)
a19cbfb3
GH		 1508{
1509 QXLDevSurfaceCreate surface;
1510 QXLSurfaceCreate *sc = &qxl->guest_primary.surface;
3761abb1 1511 uint32_t requested_height = le32_to_cpu(sc->height);
13d1fd44
AL		 1512 int requested_stride = le32_to_cpu(sc->stride);
1513
3761abb1
AL		 1514 if (requested_stride == INT32_MIN ||
1515 abs(requested_stride) * (uint64_t)requested_height
1516 > qxl->vgamem_size) {
1517 qxl_set_guest_bug(qxl, "%s: requested primary larger than framebuffer"
1518 " stride %d x height %" PRIu32 " > %" PRIu32,
1519 __func__, requested_stride, requested_height,
1520 qxl->vgamem_size);
13d1fd44
AL		 1521 return;
1522 }
a19cbfb3 1523
ddf9f4b7 1524 if (qxl->mode == QXL_MODE_NATIVE) {
0a530548 1525 qxl_set_guest_bug(qxl, "%s: nop since already in QXL_MODE_NATIVE",
ddf9f4b7
AL		 1526 __func__);
1527 }
a19cbfb3
GH		 1528 qxl_exit_vga_mode(qxl);
1529
a19cbfb3
GH		 1530 surface.format = le32_to_cpu(sc->format);
1531 surface.height = le32_to_cpu(sc->height);
1532 surface.mem = le64_to_cpu(sc->mem);
1533 surface.position = le32_to_cpu(sc->position);
1534 surface.stride = le32_to_cpu(sc->stride);
1535 surface.width = le32_to_cpu(sc->width);
1536 surface.type = le32_to_cpu(sc->type);
1537 surface.flags = le32_to_cpu(sc->flags);
c480bb7d
AL		 1538 trace_qxl_create_guest_primary(qxl->id, sc->width, sc->height, sc->mem,
1539 sc->format, sc->position);
1540 trace_qxl_create_guest_primary_rest(qxl->id, sc->stride, sc->type,
1541 sc->flags);
a19cbfb3 1542
48f4ba67
AL		 1543 if ((surface.stride & 0x3) != 0) {
1544 qxl_set_guest_bug(qxl, "primary surface stride = %d %% 4 != 0",
1545 surface.stride);
1546 return;
1547 }
1548
a19cbfb3
GH		 1549 surface.mouse_mode = true;
1550 surface.group_id = MEMSLOT_GROUP_GUEST;
1551 if (loadvm) {
1552 surface.flags |= QXL_SURF_FLAG_KEEP_DATA;
1553 }
1554
1555 qxl->mode = QXL_MODE_NATIVE;
1556 qxl->cmdflags = 0;
5ff4e36c 1557 qemu_spice_create_primary_surface(&qxl->ssd, 0, &surface, async);
a19cbfb3 1558
5ff4e36c
AL		 1559 if (async == QXL_SYNC) {
1560 qxl_create_guest_primary_complete(qxl);
1561 }
a19cbfb3
GH		 1562}
1563
5ff4e36c
AL		 1564/* return 1 if surface destoy was initiated (in QXL_ASYNC case) or
1565 * done (in QXL_SYNC case), 0 otherwise. */
1566static int qxl_destroy_primary(PCIQXLDevice *d, qxl_async_io async)
a19cbfb3
GH		 1567{
1568 if (d->mode == QXL_MODE_UNDEFINED) {
5ff4e36c 1569 return 0;
a19cbfb3 1570 }
c480bb7d 1571 trace_qxl_destroy_primary(d->id);
a19cbfb3 1572 d->mode = QXL_MODE_UNDEFINED;
5ff4e36c 1573 qemu_spice_destroy_primary_surface(&d->ssd, 0, async);
30f6da66 1574 qxl_spice_reset_cursor(d);
5ff4e36c 1575 return 1;
a19cbfb3
GH		 1576}
1577
9c70434f 1578static void qxl_set_mode(PCIQXLDevice *d, unsigned int modenr, int loadvm)
a19cbfb3
GH		 1579{
1580 pcibus_t start = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr;
1581 pcibus_t end = d->pci.io_regions[QXL_RAM_RANGE_INDEX].size + start;
1582 QXLMode *mode = d->modes->modes + modenr;
1583 uint64_t devmem = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr;
1584 QXLMemSlot slot = {
1585 .mem_start = start,
1586 .mem_end = end
1587 };
9c70434f
GH		 1588
1589 if (modenr >= d->modes->n_modes) {
1590 qxl_set_guest_bug(d, "mode number out of range");
1591 return;
1592 }
1593
a19cbfb3
GH		 1594 QXLSurfaceCreate surface = {
1595 .width = mode->x_res,
1596 .height = mode->y_res,
1597 .stride = -mode->x_res * 4,
1598 .format = SPICE_SURFACE_FMT_32_xRGB,
1599 .flags = loadvm ? QXL_SURF_FLAG_KEEP_DATA : 0,
1600 .mouse_mode = true,
1601 .mem = devmem + d->shadow_rom.draw_area_offset,
1602 };
1603
c480bb7d
AL		 1604 trace_qxl_set_mode(d->id, modenr, mode->x_res, mode->y_res, mode->bits,
1605 devmem);
a19cbfb3
GH		 1606 if (!loadvm) {
1607 qxl_hard_reset(d, 0);
1608 }
1609
1610 d->guest_slots[0].slot = slot;
e954ea28 1611 assert(qxl_add_memslot(d, 0, devmem, QXL_SYNC) == 0);
a19cbfb3
GH		 1612
1613 d->guest_primary.surface = surface;
5ff4e36c 1614 qxl_create_guest_primary(d, 0, QXL_SYNC);
a19cbfb3
GH		 1615
1616 d->mode = QXL_MODE_COMPAT;
1617 d->cmdflags = QXL_COMMAND_FLAG_COMPAT;
a19cbfb3
GH		 1618 if (mode->bits == 16) {
1619 d->cmdflags |= QXL_COMMAND_FLAG_COMPAT_16BPP;
1620 }
a19cbfb3
GH		 1621 d->shadow_rom.mode = cpu_to_le32(modenr);
1622 d->rom->mode = cpu_to_le32(modenr);
1623 qxl_rom_set_dirty(d);
1624}
1625
a8170e5e 1626static void ioport_write(void *opaque, hwaddr addr,
b1950430 1627 uint64_t val, unsigned size)
a19cbfb3
GH		 1628{
1629 PCIQXLDevice *d = opaque;
b1950430 1630 uint32_t io_port = addr;
5ff4e36c 1631 qxl_async_io async = QXL_SYNC;
5ff4e36c 1632 uint32_t orig_io_port = io_port;
a19cbfb3 1633
d96aafca 1634 if (d->guest_bug && io_port != QXL_IO_RESET) {
087e6a42
AL		 1635 return;
1636 }
1637
020af1c4 1638 if (d->revision <= QXL_REVISION_STABLE_V10 &&
ffe01e59 1639 io_port > QXL_IO_FLUSH_RELEASE) {
020af1c4
AL		 1640 qxl_set_guest_bug(d, "unsupported io %d for revision %d\n",
1641 io_port, d->revision);
1642 return;
1643 }
1644
a19cbfb3
GH		 1645 switch (io_port) {
1646 case QXL_IO_RESET:
1647 case QXL_IO_SET_MODE:
1648 case QXL_IO_MEMSLOT_ADD:
1649 case QXL_IO_MEMSLOT_DEL:
1650 case QXL_IO_CREATE_PRIMARY:
81144d1a 1651 case QXL_IO_UPDATE_IRQ:
a3d14054 1652 case QXL_IO_LOG:
5ff4e36c
AL		 1653 case QXL_IO_MEMSLOT_ADD_ASYNC:
1654 case QXL_IO_CREATE_PRIMARY_ASYNC:
a19cbfb3
GH		 1655 break;
1656 default:
e21a298a 1657 if (d->mode != QXL_MODE_VGA) {
a19cbfb3 1658 break;
e21a298a 1659 }
c480bb7d 1660 trace_qxl_io_unexpected_vga_mode(d->id,
917ae08c 1661 addr, val, io_port_to_string(io_port));
5ff4e36c
AL		 1662 /* be nice to buggy guest drivers */
1663 if (io_port >= QXL_IO_UPDATE_AREA_ASYNC &&
020af1c4 1664 io_port < QXL_IO_RANGE_SIZE) {
5ff4e36c
AL		 1665 qxl_send_events(d, QXL_INTERRUPT_IO_CMD);
1666 }
a19cbfb3
GH		 1667 return;
1668 }
1669
5ff4e36c
AL		 1670 /* we change the io_port to avoid ifdeffery in the main switch */
1671 orig_io_port = io_port;
1672 switch (io_port) {
1673 case QXL_IO_UPDATE_AREA_ASYNC:
1674 io_port = QXL_IO_UPDATE_AREA;
1675 goto async_common;
1676 case QXL_IO_MEMSLOT_ADD_ASYNC:
1677 io_port = QXL_IO_MEMSLOT_ADD;
1678 goto async_common;
1679 case QXL_IO_CREATE_PRIMARY_ASYNC:
1680 io_port = QXL_IO_CREATE_PRIMARY;
1681 goto async_common;
1682 case QXL_IO_DESTROY_PRIMARY_ASYNC:
1683 io_port = QXL_IO_DESTROY_PRIMARY;
1684 goto async_common;
1685 case QXL_IO_DESTROY_SURFACE_ASYNC:
1686 io_port = QXL_IO_DESTROY_SURFACE_WAIT;
1687 goto async_common;
1688 case QXL_IO_DESTROY_ALL_SURFACES_ASYNC:
1689 io_port = QXL_IO_DESTROY_ALL_SURFACES;
3e16b9c5
AL		 1690 goto async_common;
1691 case QXL_IO_FLUSH_SURFACES_ASYNC:
020af1c4 1692 case QXL_IO_MONITORS_CONFIG_ASYNC:
5ff4e36c
AL		 1693async_common:
1694 async = QXL_ASYNC;
1695 qemu_mutex_lock(&d->async_lock);
1696 if (d->current_async != QXL_UNDEFINED_IO) {
0a530548 1697 qxl_set_guest_bug(d, "%d async started before last (%d) complete",
5ff4e36c
AL		 1698 io_port, d->current_async);
1699 qemu_mutex_unlock(&d->async_lock);
1700 return;
1701 }
1702 d->current_async = orig_io_port;
1703 qemu_mutex_unlock(&d->async_lock);
5ff4e36c
AL		 1704 break;
1705 default:
1706 break;
1707 }
18b20385
GH		 1708 trace_qxl_io_write(d->id, qxl_mode_to_string(d->mode),
1709 addr, io_port_to_string(addr),
1710 val, size, async);
5ff4e36c 1711
a19cbfb3
GH		 1712 switch (io_port) {
1713 case QXL_IO_UPDATE_AREA:
1714 {
81fb6f15 1715 QXLCookie *cookie = NULL;
a19cbfb3 1716 QXLRect update = d->ram->update_area;
81fb6f15 1717
ddd8fdc7 1718 if (d->ram->update_surface > d->ssd.num_surfaces) {
511b13e2
AL		 1719 qxl_set_guest_bug(d, "QXL_IO_UPDATE_AREA: invalid surface id %d\n",
1720 d->ram->update_surface);
36a03e0b 1721 break;
511b13e2 1722 }
36a03e0b
MT		 1723 if (update.left >= update.right || update.top >= update.bottom ||
1724 update.left < 0 || update.top < 0) {
511b13e2
AL		 1725 qxl_set_guest_bug(d,
1726 "QXL_IO_UPDATE_AREA: invalid area (%ux%u)x(%ux%u)\n",
1727 update.left, update.top, update.right, update.bottom);
9e5a25f1
MAL		 1728 if (update.left == update.right || update.top == update.bottom) {
1729 /* old drivers may provide empty area, keep going */
1730 qxl_clear_guest_bug(d);
1731 goto cancel_async;
1732 }
ccc2960d
DH		 1733 break;
1734 }
81fb6f15
AL		 1735 if (async == QXL_ASYNC) {
1736 cookie = qxl_cookie_new(QXL_COOKIE_TYPE_IO,
1737 QXL_IO_UPDATE_AREA_ASYNC);
1738 cookie->u.area = update;
1739 }
aee32bf3 1740 qxl_spice_update_area(d, d->ram->update_surface,
81fb6f15
AL		 1741 cookie ? &cookie->u.area : &update,
1742 NULL, 0, 0, async, cookie);
a19cbfb3
GH		 1743 break;
1744 }
1745 case QXL_IO_NOTIFY_CMD:
5c59d118 1746 qemu_spice_wakeup(&d->ssd);
a19cbfb3
GH		 1747 break;
1748 case QXL_IO_NOTIFY_CURSOR:
5c59d118 1749 qemu_spice_wakeup(&d->ssd);
a19cbfb3
GH		 1750 break;
1751 case QXL_IO_UPDATE_IRQ:
40010aea 1752 qxl_update_irq(d);
a19cbfb3
GH		 1753 break;
1754 case QXL_IO_NOTIFY_OOM:
a19cbfb3
GH		 1755 if (!SPICE_RING_IS_EMPTY(&d->ram->release_ring)) {
1756 break;
1757 }
1758 d->oom_running = 1;
aee32bf3 1759 qxl_spice_oom(d);
a19cbfb3
GH		 1760 d->oom_running = 0;
1761 break;
1762 case QXL_IO_SET_MODE:
a19cbfb3
GH		 1763 qxl_set_mode(d, val, 0);
1764 break;
1765 case QXL_IO_LOG:
00f42697
DB		 1766 if (TRACE_QXL_IO_LOG_ENABLED || d->guestdebug) {
1767 /* We cannot trust the guest to NUL terminate d->ram->log_buf */
1768 char *log_buf = g_strndup((const char *)d->ram->log_buf,
1769 sizeof(d->ram->log_buf));
1770 trace_qxl_io_log(d->id, log_buf);
1771 if (d->guestdebug) {
1772 fprintf(stderr, "qxl/guest-%d: %" PRId64 ": %s", d->id,
1773 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), log_buf);
1774 }
1775 g_free(log_buf);
a19cbfb3
GH		 1776 }
1777 break;
1778 case QXL_IO_RESET:
a19cbfb3
GH		 1779 qxl_hard_reset(d, 0);
1780 break;
1781 case QXL_IO_MEMSLOT_ADD:
2bce0400 1782 if (val >= NUM_MEMSLOTS) {
0a530548 1783 qxl_set_guest_bug(d, "QXL_IO_MEMSLOT_ADD: val out of range");
2bce0400
GH		 1784 break;
1785 }
1786 if (d->guest_slots[val].active) {
0a530548
AL		 1787 qxl_set_guest_bug(d,
1788 "QXL_IO_MEMSLOT_ADD: memory slot already active");
2bce0400
GH		 1789 break;
1790 }
a19cbfb3 1791 d->guest_slots[val].slot = d->ram->mem_slot;
5ff4e36c 1792 qxl_add_memslot(d, val, 0, async);
a19cbfb3
GH		 1793 break;
1794 case QXL_IO_MEMSLOT_DEL:
2bce0400 1795 if (val >= NUM_MEMSLOTS) {
0a530548 1796 qxl_set_guest_bug(d, "QXL_IO_MEMSLOT_DEL: val out of range");
2bce0400
GH		 1797 break;
1798 }
a19cbfb3
GH		 1799 qxl_del_memslot(d, val);
1800 break;
1801 case QXL_IO_CREATE_PRIMARY:
2bce0400 1802 if (val != 0) {
0a530548 1803 qxl_set_guest_bug(d, "QXL_IO_CREATE_PRIMARY (async=%d): val != 0",
5ff4e36c
AL		 1804 async);
1805 goto cancel_async;
2bce0400 1806 }
a19cbfb3 1807 d->guest_primary.surface = d->ram->create_surface;
5ff4e36c 1808 qxl_create_guest_primary(d, 0, async);
a19cbfb3
GH		 1809 break;
1810 case QXL_IO_DESTROY_PRIMARY:
2bce0400 1811 if (val != 0) {
0a530548 1812 qxl_set_guest_bug(d, "QXL_IO_DESTROY_PRIMARY (async=%d): val != 0",
5ff4e36c
AL		 1813 async);
1814 goto cancel_async;
1815 }
5ff4e36c 1816 if (!qxl_destroy_primary(d, async)) {
c480bb7d
AL		 1817 trace_qxl_io_destroy_primary_ignored(d->id,
1818 qxl_mode_to_string(d->mode));
5ff4e36c 1819 goto cancel_async;
2bce0400 1820 }
a19cbfb3
GH		 1821 break;
1822 case QXL_IO_DESTROY_SURFACE_WAIT:
ddd8fdc7 1823 if (val >= d->ssd.num_surfaces) {
0a530548 1824 qxl_set_guest_bug(d, "QXL_IO_DESTROY_SURFACE (async=%d):"
5f8daf2e 1825 "%" PRIu64 " >= NUM_SURFACES", async, val);
5ff4e36c
AL		 1826 goto cancel_async;
1827 }
1828 qxl_spice_destroy_surface_wait(d, val, async);
a19cbfb3 1829 break;
3e16b9c5
AL		 1830 case QXL_IO_FLUSH_RELEASE: {
1831 QXLReleaseRing *ring = &d->ram->release_ring;
1832 if (ring->prod - ring->cons + 1 == ring->num_items) {
1833 fprintf(stderr,
1834 "ERROR: no flush, full release ring [p%d,%dc]\n",
1835 ring->prod, ring->cons);
1836 }
1837 qxl_push_free_res(d, 1 /* flush */);
3e16b9c5
AL		 1838 break;
1839 }
1840 case QXL_IO_FLUSH_SURFACES_ASYNC:
3e16b9c5
AL		 1841 qxl_spice_flush_surfaces_async(d);
1842 break;
a19cbfb3 1843 case QXL_IO_DESTROY_ALL_SURFACES:
5ff4e36c
AL		 1844 d->mode = QXL_MODE_UNDEFINED;
1845 qxl_spice_destroy_surfaces(d, async);
a19cbfb3 1846 break;
020af1c4
AL		 1847 case QXL_IO_MONITORS_CONFIG_ASYNC:
1848 qxl_spice_monitors_config_async(d, 0);
1849 break;
a19cbfb3 1850 default:
0a530548 1851 qxl_set_guest_bug(d, "%s: unexpected ioport=0x%x\n", __func__, io_port);
a19cbfb3 1852 }
5ff4e36c
AL		 1853 return;
1854cancel_async:
5ff4e36c
AL		 1855 if (async) {
1856 qxl_send_events(d, QXL_INTERRUPT_IO_CMD);
1857 qemu_mutex_lock(&d->async_lock);
1858 d->current_async = QXL_UNDEFINED_IO;
1859 qemu_mutex_unlock(&d->async_lock);
1860 }
a19cbfb3
GH		 1861}
1862
a8170e5e 1863static uint64_t ioport_read(void *opaque, hwaddr addr,
b1950430 1864 unsigned size)
a19cbfb3 1865{
917ae08c 1866 PCIQXLDevice *qxl = opaque;
a19cbfb3 1867
917ae08c 1868 trace_qxl_io_read_unexpected(qxl->id);
a19cbfb3
GH		 1869 return 0xff;
1870}
1871
b1950430
AK		 1872static const MemoryRegionOps qxl_io_ops = {
1873 .read = ioport_read,
1874 .write = ioport_write,
1875 .valid = {
1876 .min_access_size = 1,
1877 .max_access_size = 1,
1878 },
1879};
a19cbfb3 1880
4a46c99c 1881static void qxl_update_irq_bh(void *opaque)
a19cbfb3
GH		 1882{
1883 PCIQXLDevice *d = opaque;
40010aea 1884 qxl_update_irq(d);
a19cbfb3
GH		 1885}
1886
a19cbfb3
GH		 1887static void qxl_send_events(PCIQXLDevice *d, uint32_t events)
1888{
1889 uint32_t old_pending;
1890 uint32_t le_events = cpu_to_le32(events);
1891
917ae08c 1892 trace_qxl_send_events(d->id, events);
511aefb0
AL		 1893 if (!qemu_spice_display_is_running(&d->ssd)) {
1894 /* spice-server tracks guest running state and should not do this */
1895 fprintf(stderr, "%s: spice-server bug: guest stopped, ignoring\n",
1896 __func__);
1897 trace_qxl_send_events_vm_stopped(d->id, events);
1898 return;
1899 }
5a358b39
PM		 1900 /*
1901 * Older versions of Spice forgot to define the QXLRam struct
1902 * with the '__aligned__(4)' attribute. clang 7 and newer will
1903 * thus warn that atomic_fetch_or(&d->ram->int_pending, ...)
1904 * might be a misaligned atomic access, and will generate an
1905 * out-of-line call for it, which results in a link error since
1906 * we don't currently link against libatomic.
1907 *
1908 * In fact we set up d->ram in init_qxl_ram() so it always starts
1909 * at a 4K boundary, so we know that &d->ram->int_pending is
1910 * naturally aligned for a uint32_t. Newer Spice versions
1911 * (with Spice commit beda5ec7a6848be20c0cac2a9a8ef2a41e8069c1)
1912 * will fix the bug directly. To deal with older versions,
1913 * we tell the compiler to assume the address really is aligned.
1914 * Any compiler which cares about the misalignment will have
1915 * __builtin_assume_aligned.
1916 */
1917#ifdef HAS_ASSUME_ALIGNED
1918#define ALIGNED_UINT32_PTR(P) ((uint32_t *)__builtin_assume_aligned(P, 4))
1919#else
1920#define ALIGNED_UINT32_PTR(P) ((uint32_t *)P)
1921#endif
1922
1923 old_pending = atomic_fetch_or(ALIGNED_UINT32_PTR(&d->ram->int_pending),
1924 le_events);
a19cbfb3
GH		 1925 if ((old_pending & le_events) == le_events) {
1926 return;
1927 }
4a46c99c 1928 qemu_bh_schedule(d->update_irq);
a19cbfb3
GH		 1929}
1930
1931/* graphics console */
1932
1933static void qxl_hw_update(void *opaque)
1934{
1935 PCIQXLDevice *qxl = opaque;
a19cbfb3 1936
15162335 1937 qxl_render_update(qxl);
a19cbfb3
GH		 1938}
1939
1331eab2
GH		 1940static void qxl_dirty_one_surface(PCIQXLDevice *qxl, QXLPHYSICAL pqxl,
1941 uint32_t height, int32_t stride)
1942{
e0127d2e
GH		 1943 uint64_t offset, size;
1944 uint32_t slot;
1331eab2
GH		 1945 bool rc;
1946
1947 rc = qxl_get_check_slot_offset(qxl, pqxl, &slot, &offset);
1948 assert(rc == true);
e0127d2e
GH		 1949 size = (uint64_t)height * abs(stride);
1950 trace_qxl_surfaces_dirty(qxl->id, offset, size);
1331eab2 1951 qxl_set_dirty(qxl->guest_slots[slot].mr,
e0127d2e
GH		 1952 qxl->guest_slots[slot].offset + offset,
1953 qxl->guest_slots[slot].offset + offset + size);
1331eab2
GH		 1954}
1955
e25139b3
YH		 1956static void qxl_dirty_surfaces(PCIQXLDevice *qxl)
1957{
e25139b3
YH		 1958 int i;
1959
2aa9e85c 1960 if (qxl->mode != QXL_MODE_NATIVE && qxl->mode != QXL_MODE_COMPAT) {
e25139b3
YH		 1961 return;
1962 }
1963
1964 /* dirty the primary surface */
1331eab2
GH		 1965 qxl_dirty_one_surface(qxl, qxl->guest_primary.surface.mem,
1966 qxl->guest_primary.surface.height,
1967 qxl->guest_primary.surface.stride);
e25139b3
YH		 1968
1969 /* dirty the off-screen surfaces */
ddd8fdc7 1970 for (i = 0; i < qxl->ssd.num_surfaces; i++) {
e25139b3 1971 QXLSurfaceCmd *cmd;
e25139b3
YH		 1972
1973 if (qxl->guest_surfaces.cmds[i] == 0) {
1974 continue;
1975 }
1976
1977 cmd = qxl_phys2virt(qxl, qxl->guest_surfaces.cmds[i],
1978 MEMSLOT_GROUP_GUEST);
fae2afb1 1979 assert(cmd);
e25139b3 1980 assert(cmd->type == QXL_SURFACE_CMD_CREATE);
1331eab2
GH		 1981 qxl_dirty_one_surface(qxl, cmd->u.surface_create.data,
1982 cmd->u.surface_create.height,
1983 cmd->u.surface_create.stride);
e25139b3
YH		 1984 }
1985}
1986
1dfb4dd9
LC		 1987static void qxl_vm_change_state_handler(void *opaque, int running,
1988 RunState state)
a19cbfb3
GH		 1989{
1990 PCIQXLDevice *qxl = opaque;
a19cbfb3 1991
efbf2950
YH		 1992 if (running) {
1993 /*
1994 * if qxl_send_events was called from spice server context before
40010aea 1995 * migration ended, qxl_update_irq for these events might not have been
efbf2950
YH		 1996 * called
1997 */
40010aea 1998 qxl_update_irq(qxl);
e25139b3
YH		 1999 } else {
2000 /* make sure surfaces are saved before migration */
2001 qxl_dirty_surfaces(qxl);
a19cbfb3
GH		 2002 }
2003}
2004
2005/* display change listener */
2006
7c20b4a3 2007static void display_update(DisplayChangeListener *dcl,
7c20b4a3 2008 int x, int y, int w, int h)
a19cbfb3 2009{
c6c06853
GH		 2010 PCIQXLDevice *qxl = container_of(dcl, PCIQXLDevice, ssd.dcl);
2011
2012 if (qxl->mode == QXL_MODE_VGA) {
2013 qemu_spice_display_update(&qxl->ssd, x, y, w, h);
a19cbfb3
GH		 2014 }
2015}
2016
c12aeb86 2017static void display_switch(DisplayChangeListener *dcl,
c12aeb86 2018 struct DisplaySurface *surface)
a19cbfb3 2019{
c6c06853
GH		 2020 PCIQXLDevice *qxl = container_of(dcl, PCIQXLDevice, ssd.dcl);
2021
71874c17 2022 qxl->ssd.ds = surface;
c6c06853 2023 if (qxl->mode == QXL_MODE_VGA) {
c12aeb86 2024 qemu_spice_display_switch(&qxl->ssd, surface);
a19cbfb3
GH		 2025 }
2026}
2027
bc2ed970 2028static void display_refresh(DisplayChangeListener *dcl)
a19cbfb3 2029{
c6c06853
GH		 2030 PCIQXLDevice *qxl = container_of(dcl, PCIQXLDevice, ssd.dcl);
2031
2032 if (qxl->mode == QXL_MODE_VGA) {
2033 qemu_spice_display_refresh(&qxl->ssd);
a19cbfb3
GH		 2034 }
2035}
2036
7c20b4a3
GH		 2037static DisplayChangeListenerOps display_listener_ops = {
2038 .dpy_name = "spice/qxl",
a93a4a22 2039 .dpy_gfx_update = display_update,
c12aeb86 2040 .dpy_gfx_switch = display_switch,
7c20b4a3 2041 .dpy_refresh = display_refresh,
a19cbfb3
GH		 2042};
2043
13d1fd44 2044static void qxl_init_ramsize(PCIQXLDevice *qxl)
a974192c 2045{
13d1fd44
AL		 2046 /* vga mode framebuffer / primary surface (bar 0, first part) */
2047 if (qxl->vgamem_size_mb < 8) {
2048 qxl->vgamem_size_mb = 8;
2049 }
876d5163
RK		 2050 /* XXX: we round vgamem_size_mb up to a nearest power of two and it must be
2051 * less than vga_common_init()'s maximum on qxl->vga.vram_size (512 now).
2052 */
2053 if (qxl->vgamem_size_mb > 256) {
2054 qxl->vgamem_size_mb = 256;
2055 }
f0353b0d 2056 qxl->vgamem_size = qxl->vgamem_size_mb * MiB;
13d1fd44
AL		 2057
2058 /* vga ram (bar 0, total) */
017438ee 2059 if (qxl->ram_size_mb != -1) {
f0353b0d 2060 qxl->vga.vram_size = qxl->ram_size_mb * MiB;
017438ee 2061 }
13d1fd44
AL		 2062 if (qxl->vga.vram_size < qxl->vgamem_size * 2) {
2063 qxl->vga.vram_size = qxl->vgamem_size * 2;
a974192c
GH		 2064 }
2065
6f2b175a
GH		 2066 /* vram32 (surfaces, 32bit, bar 1) */
2067 if (qxl->vram32_size_mb != -1) {
f0353b0d 2068 qxl->vram32_size = qxl->vram32_size_mb * MiB;
6f2b175a
GH		 2069 }
2070 if (qxl->vram32_size < 4096) {
2071 qxl->vram32_size = 4096;
2072 }
2073
2074 /* vram (surfaces, 64bit, bar 4+5) */
017438ee 2075 if (qxl->vram_size_mb != -1) {
f0353b0d 2076 qxl->vram_size = (uint64_t)qxl->vram_size_mb * MiB;
017438ee 2077 }
6f2b175a
GH		 2078 if (qxl->vram_size < qxl->vram32_size) {
2079 qxl->vram_size = qxl->vram32_size;
a974192c 2080 }
6f2b175a 2081
a974192c 2082 if (qxl->revision == 1) {
6f2b175a 2083 qxl->vram32_size = 4096;
a974192c
GH		 2084 qxl->vram_size = 4096;
2085 }
bb7443f6
RK		 2086 qxl->vgamem_size = pow2ceil(qxl->vgamem_size);
2087 qxl->vga.vram_size = pow2ceil(qxl->vga.vram_size);
2088 qxl->vram32_size = pow2ceil(qxl->vram32_size);
2089 qxl->vram_size = pow2ceil(qxl->vram_size);
a974192c
GH		 2090}
2091
042a24db 2092static void qxl_realize_common(PCIQXLDevice *qxl, Error **errp)
a19cbfb3
GH		 2093{
2094 uint8_t* config = qxl->pci.config;
a19cbfb3
GH		 2095 uint32_t pci_device_rev;
2096 uint32_t io_size;
2097
47025a01 2098 qemu_spice_display_init_common(&qxl->ssd);
a19cbfb3 2099 qxl->mode = QXL_MODE_UNDEFINED;
a19cbfb3 2100 qxl->num_memslots = NUM_MEMSLOTS;
14898cf6 2101 qemu_mutex_init(&qxl->track_lock);
5ff4e36c
AL		 2102 qemu_mutex_init(&qxl->async_lock);
2103 qxl->current_async = QXL_UNDEFINED_IO;
087e6a42 2104 qxl->guest_bug = 0;
a19cbfb3
GH		 2105
2106 switch (qxl->revision) {
2107 case 1: /* spice 0.4 -- qxl-1 */
a19cbfb3 2108 pci_device_rev = QXL_REVISION_STABLE_V04;
3f6297b9 2109 io_size = 8;
a19cbfb3
GH		 2110 break;
2111 case 2: /* spice 0.6 -- qxl-2 */
a19cbfb3 2112 pci_device_rev = QXL_REVISION_STABLE_V06;
3f6297b9 2113 io_size = 16;
a19cbfb3 2114 break;
9197a7c8 2115 case 3: /* qxl-3 */
020af1c4
AL		 2116 pci_device_rev = QXL_REVISION_STABLE_V10;
2117 io_size = 32; /* PCI region size must be pow2 */
2118 break;
020af1c4
AL		 2119 case 4: /* qxl-4 */
2120 pci_device_rev = QXL_REVISION_STABLE_V12;
bb7443f6 2121 io_size = pow2ceil(QXL_IO_RANGE_SIZE);
9197a7c8 2122 break;
36839d35 2123 default:
042a24db
MA		 2124 error_setg(errp, "Invalid revision %d for qxl device (max %d)",
2125 qxl->revision, QXL_DEFAULT_REVISION);
2126 return;
a19cbfb3
GH		 2127 }
2128
a19cbfb3
GH		 2129 pci_set_byte(&config[PCI_REVISION_ID], pci_device_rev);
2130 pci_set_byte(&config[PCI_INTERRUPT_PIN], 1);
2131
2132 qxl->rom_size = qxl_rom_size();
ce66d778 2133 memory_region_init_ram(&qxl->rom_bar, OBJECT(qxl), "qxl.vrom",
f8ed85ac 2134 qxl->rom_size, &error_fatal);
a19cbfb3
GH		 2135 init_qxl_rom(qxl);
2136 init_qxl_ram(qxl);
2137
ddd8fdc7 2138 qxl->guest_surfaces.cmds = g_new0(QXLPHYSICAL, qxl->ssd.num_surfaces);
ce66d778 2139 memory_region_init_ram(&qxl->vram_bar, OBJECT(qxl), "qxl.vram",
f8ed85ac 2140 qxl->vram_size, &error_fatal);
3eadad55
PB		 2141 memory_region_init_alias(&qxl->vram32_bar, OBJECT(qxl), "qxl.vram32",
2142 &qxl->vram_bar, 0, qxl->vram32_size);
a19cbfb3 2143
3eadad55 2144 memory_region_init_io(&qxl->io_bar, OBJECT(qxl), &qxl_io_ops, qxl,
b1950430 2145 "qxl-ioports", io_size);
60e94e43 2146 if (qxl->have_vga) {
b1950430
AK		 2147 vga_dirty_log_start(&qxl->vga);
2148 }
bd8f2f5d 2149 memory_region_set_flush_coalesced(&qxl->io_bar);
b1950430
AK		 2150
2151
e824b2cc
AK		 2152 pci_register_bar(&qxl->pci, QXL_IO_RANGE_INDEX,
2153 PCI_BASE_ADDRESS_SPACE_IO, &qxl->io_bar);
a19cbfb3 2154
e824b2cc
AK		 2155 pci_register_bar(&qxl->pci, QXL_ROM_RANGE_INDEX,
2156 PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->rom_bar);
a19cbfb3 2157
e824b2cc
AK		 2158 pci_register_bar(&qxl->pci, QXL_RAM_RANGE_INDEX,
2159 PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->vga.vram);
a19cbfb3 2160
e824b2cc 2161 pci_register_bar(&qxl->pci, QXL_VRAM_RANGE_INDEX,
6f2b175a
GH		 2162 PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->vram32_bar);
2163
2164 if (qxl->vram32_size < qxl->vram_size) {
2165 /*
2166 * Make the 64bit vram bar show up only in case it is
2167 * configured to be larger than the 32bit vram bar.
2168 */
2169 pci_register_bar(&qxl->pci, QXL_VRAM64_RANGE_INDEX,
2170 PCI_BASE_ADDRESS_SPACE_MEMORY |
2171 PCI_BASE_ADDRESS_MEM_TYPE_64 |
2172 PCI_BASE_ADDRESS_MEM_PREFETCH,
2173 &qxl->vram_bar);
2174 }
2175
2176 /* print pci bar details */
f0353b0d 2177 dprint(qxl, 1, "ram/%s: %" PRId64 " MB [region 0]\n",
60e94e43 2178 qxl->have_vga ? "pri" : "sec", qxl->vga.vram_size / MiB);
f0353b0d
PMD		 2179 dprint(qxl, 1, "vram/32: %" PRIx64 " MB [region 1]\n",
2180 qxl->vram32_size / MiB);
2181 dprint(qxl, 1, "vram/64: %" PRIx64 " MB %s\n",
2182 qxl->vram_size / MiB,
6f2b175a 2183 qxl->vram32_size < qxl->vram_size ? "[region 4]" : "[unmapped]");
a19cbfb3
GH		 2184
2185 qxl->ssd.qxl.base.sif = &qxl_interface.base;
9fa03286 2186 if (qemu_spice_add_display_interface(&qxl->ssd.qxl, qxl->vga.con) != 0) {
042a24db
MA		 2187 error_setg(errp, "qxl interface %d.%d not supported by spice-server",
2188 SPICE_INTERFACE_QXL_MAJOR, SPICE_INTERFACE_QXL_MINOR);
2189 return;
e25a0651 2190 }
a19cbfb3
GH		 2191 qemu_add_vm_change_state_handler(qxl_vm_change_state_handler, qxl);
2192
4a46c99c 2193 qxl->update_irq = qemu_bh_new(qxl_update_irq_bh, qxl);
a19cbfb3
GH		 2194 qxl_reset_state(qxl);
2195
81fb6f15 2196 qxl->update_area_bh = qemu_bh_new(qxl_render_update_area_bh, qxl);
0b2824e5 2197 qxl->ssd.cursor_bh = qemu_bh_new(qemu_spice_cursor_refresh_bh, &qxl->ssd);
a19cbfb3
GH		 2198}
2199
042a24db 2200static void qxl_realize_primary(PCIDevice *dev, Error **errp)
a19cbfb3 2201{
c69f6c7d 2202 PCIQXLDevice *qxl = PCI_QXL(dev);
a19cbfb3 2203 VGACommonState *vga = &qxl->vga;
042a24db 2204 Error *local_err = NULL;
a19cbfb3 2205
13d1fd44 2206 qxl_init_ramsize(qxl);
54a85d46 2207 vga->vbe_size = qxl->vgamem_size;
f0353b0d 2208 vga->vram_size_mb = qxl->vga.vram_size / MiB;
1fcfdc43 2209 vga_common_init(vga, OBJECT(dev));
712f0cc7
PB		 2210 vga_init(vga, OBJECT(dev),
2211 pci_address_space(dev), pci_address_space_io(dev), false);
848696bf 2212 portio_list_init(&qxl->vga_port_list, OBJECT(dev), qxl_vga_portio_list,
db10ca90 2213 vga, "vga");
848696bf
KB		 2214 portio_list_set_flush_coalesced(&qxl->vga_port_list);
2215 portio_list_add(&qxl->vga_port_list, pci_address_space_io(dev), 0x3b0);
60e94e43 2216 qxl->have_vga = true;
a19cbfb3 2217
5643706a 2218 vga->con = graphic_console_init(DEVICE(dev), 0, &qxl_ops, qxl);
60e94e43
GH		 2219 qxl->id = qemu_console_get_index(vga->con); /* == channel_id */
2220 if (qxl->id != 0) {
2221 error_setg(errp, "primary qxl-vga device must be console 0 "
2222 "(first display device on the command line)");
2223 return;
2224 }
a19cbfb3 2225
042a24db
MA		 2226 qxl_realize_common(qxl, &local_err);
2227 if (local_err) {
2228 error_propagate(errp, local_err);
2229 return;
bdd4df33
GH		 2230 }
2231
7c20b4a3 2232 qxl->ssd.dcl.ops = &display_listener_ops;
284d1c6b 2233 qxl->ssd.dcl.con = vga->con;
5209089f 2234 register_displaychangelistener(&qxl->ssd.dcl);
a19cbfb3
GH		 2235}
2236
042a24db 2237static void qxl_realize_secondary(PCIDevice *dev, Error **errp)
a19cbfb3 2238{
c69f6c7d 2239 PCIQXLDevice *qxl = PCI_QXL(dev);
a19cbfb3 2240
13d1fd44 2241 qxl_init_ramsize(qxl);
ce66d778 2242 memory_region_init_ram(&qxl->vga.vram, OBJECT(dev), "qxl.vgavram",
f8ed85ac 2243 qxl->vga.vram_size, &error_fatal);
b1950430 2244 qxl->vga.vram_ptr = memory_region_get_ram_ptr(&qxl->vga.vram);
5643706a 2245 qxl->vga.con = graphic_console_init(DEVICE(dev), 0, &qxl_ops, qxl);
60e94e43 2246 qxl->id = qemu_console_get_index(qxl->vga.con); /* == channel_id */
a19cbfb3 2247
042a24db 2248 qxl_realize_common(qxl, errp);
a19cbfb3
GH		 2249}
2250
44b1ff31 2251static int qxl_pre_save(void *opaque)
a19cbfb3
GH		 2252{
2253 PCIQXLDevice* d = opaque;
2254 uint8_t *ram_start = d->vga.vram_ptr;
2255
c480bb7d 2256 trace_qxl_pre_save(d->id);
a19cbfb3
GH		 2257 if (d->last_release == NULL) {
2258 d->last_release_offset = 0;
2259 } else {
2260 d->last_release_offset = (uint8_t *)d->last_release - ram_start;
2261 }
2262 assert(d->last_release_offset < d->vga.vram_size);
44b1ff31
DDAG		 2263
2264 return 0;
a19cbfb3
GH		 2265}
2266
2267static int qxl_pre_load(void *opaque)
2268{
2269 PCIQXLDevice* d = opaque;
2270
c480bb7d 2271 trace_qxl_pre_load(d->id);
a19cbfb3
GH		 2272 qxl_hard_reset(d, 1);
2273 qxl_exit_vga_mode(d);
a19cbfb3
GH		 2274 return 0;
2275}
2276
54825d2e
AL		 2277static void qxl_create_memslots(PCIQXLDevice *d)
2278{
2279 int i;
2280
2281 for (i = 0; i < NUM_MEMSLOTS; i++) {
2282 if (!d->guest_slots[i].active) {
2283 continue;
2284 }
54825d2e
AL		 2285 qxl_add_memslot(d, i, 0, QXL_SYNC);
2286 }
2287}
2288
a19cbfb3
GH		 2289static int qxl_post_load(void *opaque, int version)
2290{
2291 PCIQXLDevice* d = opaque;
2292 uint8_t *ram_start = d->vga.vram_ptr;
2293 QXLCommandExt *cmds;
54825d2e 2294 int in, out, newmode;
a19cbfb3 2295
a19cbfb3
GH		 2296 assert(d->last_release_offset < d->vga.vram_size);
2297 if (d->last_release_offset == 0) {
2298 d->last_release = NULL;
2299 } else {
2300 d->last_release = (QXLReleaseInfo *)(ram_start + d->last_release_offset);
2301 }
2302
2303 d->modes = (QXLModes*)((uint8_t*)d->rom + d->rom->modes_offset);
2304
c480bb7d 2305 trace_qxl_post_load(d->id, qxl_mode_to_string(d->mode));
a19cbfb3
GH		 2306 newmode = d->mode;
2307 d->mode = QXL_MODE_UNDEFINED;
54825d2e 2308
a19cbfb3
GH		 2309 switch (newmode) {
2310 case QXL_MODE_UNDEFINED:
fa98efe9 2311 qxl_create_memslots(d);
a19cbfb3
GH		 2312 break;
2313 case QXL_MODE_VGA:
54825d2e 2314 qxl_create_memslots(d);
a19cbfb3
GH		 2315 qxl_enter_vga_mode(d);
2316 break;
2317 case QXL_MODE_NATIVE:
54825d2e 2318 qxl_create_memslots(d);
5ff4e36c 2319 qxl_create_guest_primary(d, 1, QXL_SYNC);
a19cbfb3
GH		 2320
2321 /* replay surface-create and cursor-set commands */
9de68637 2322 cmds = g_new0(QXLCommandExt, d->ssd.num_surfaces + 1);
ddd8fdc7 2323 for (in = 0, out = 0; in < d->ssd.num_surfaces; in++) {
a19cbfb3
GH		 2324 if (d->guest_surfaces.cmds[in] == 0) {
2325 continue;
2326 }
2327 cmds[out].cmd.data = d->guest_surfaces.cmds[in];
2328 cmds[out].cmd.type = QXL_CMD_SURFACE;
2329 cmds[out].group_id = MEMSLOT_GROUP_GUEST;
2330 out++;
2331 }
30f6da66
YH		 2332 if (d->guest_cursor) {
2333 cmds[out].cmd.data = d->guest_cursor;
2334 cmds[out].cmd.type = QXL_CMD_CURSOR;
2335 cmds[out].group_id = MEMSLOT_GROUP_GUEST;
2336 out++;
2337 }
aee32bf3 2338 qxl_spice_loadvm_commands(d, cmds, out);
7267c094 2339 g_free(cmds);
020af1c4
AL		 2340 if (d->guest_monitors_config) {
2341 qxl_spice_monitors_config_async(d, 1);
2342 }
a19cbfb3
GH		 2343 break;
2344 case QXL_MODE_COMPAT:
54825d2e
AL		 2345 /* note: no need to call qxl_create_memslots, qxl_set_mode
2346 * creates the mem slot. */
a19cbfb3
GH		 2347 qxl_set_mode(d, d->shadow_rom.mode, 1);
2348 break;
2349 }
a19cbfb3
GH		 2350 return 0;
2351}
2352
b67737a6 2353#define QXL_SAVE_VERSION 21
a19cbfb3 2354
020af1c4
AL		 2355static bool qxl_monitors_config_needed(void *opaque)
2356{
2357 PCIQXLDevice *qxl = opaque;
2358
2359 return qxl->guest_monitors_config != 0;
2360}
2361
2362
a19cbfb3
GH		 2363static VMStateDescription qxl_memslot = {
2364 .name = "qxl-memslot",
2365 .version_id = QXL_SAVE_VERSION,
2366 .minimum_version_id = QXL_SAVE_VERSION,
2367 .fields = (VMStateField[]) {
2368 VMSTATE_UINT64(slot.mem_start, struct guest_slots),
2369 VMSTATE_UINT64(slot.mem_end, struct guest_slots),
2370 VMSTATE_UINT32(active, struct guest_slots),
2371 VMSTATE_END_OF_LIST()
2372 }
2373};
2374
2375static VMStateDescription qxl_surface = {
2376 .name = "qxl-surface",
2377 .version_id = QXL_SAVE_VERSION,
2378 .minimum_version_id = QXL_SAVE_VERSION,
2379 .fields = (VMStateField[]) {
2380 VMSTATE_UINT32(width, QXLSurfaceCreate),
2381 VMSTATE_UINT32(height, QXLSurfaceCreate),
2382 VMSTATE_INT32(stride, QXLSurfaceCreate),
2383 VMSTATE_UINT32(format, QXLSurfaceCreate),
2384 VMSTATE_UINT32(position, QXLSurfaceCreate),
2385 VMSTATE_UINT32(mouse_mode, QXLSurfaceCreate),
2386 VMSTATE_UINT32(flags, QXLSurfaceCreate),
2387 VMSTATE_UINT32(type, QXLSurfaceCreate),
2388 VMSTATE_UINT64(mem, QXLSurfaceCreate),
2389 VMSTATE_END_OF_LIST()
2390 }
2391};
2392
020af1c4
AL		 2393static VMStateDescription qxl_vmstate_monitors_config = {
2394 .name = "qxl/monitors-config",
2395 .version_id = 1,
2396 .minimum_version_id = 1,
5cd8cada 2397 .needed = qxl_monitors_config_needed,
020af1c4
AL		 2398 .fields = (VMStateField[]) {
2399 VMSTATE_UINT64(guest_monitors_config, PCIQXLDevice),
2400 VMSTATE_END_OF_LIST()
2401 },
2402};
2403
a19cbfb3
GH		 2404static VMStateDescription qxl_vmstate = {
2405 .name = "qxl",
2406 .version_id = QXL_SAVE_VERSION,
2407 .minimum_version_id = QXL_SAVE_VERSION,
2408 .pre_save = qxl_pre_save,
2409 .pre_load = qxl_pre_load,
2410 .post_load = qxl_post_load,
020af1c4 2411 .fields = (VMStateField[]) {
a19cbfb3
GH		 2412 VMSTATE_PCI_DEVICE(pci, PCIQXLDevice),
2413 VMSTATE_STRUCT(vga, PCIQXLDevice, 0, vmstate_vga_common, VGACommonState),
2414 VMSTATE_UINT32(shadow_rom.mode, PCIQXLDevice),
2415 VMSTATE_UINT32(num_free_res, PCIQXLDevice),
2416 VMSTATE_UINT32(last_release_offset, PCIQXLDevice),
2417 VMSTATE_UINT32(mode, PCIQXLDevice),
2418 VMSTATE_UINT32(ssd.unique, PCIQXLDevice),
d2164ad3 2419 VMSTATE_INT32_EQUAL(num_memslots, PCIQXLDevice, NULL),
b67737a6
GH		 2420 VMSTATE_STRUCT_ARRAY(guest_slots, PCIQXLDevice, NUM_MEMSLOTS, 0,
2421 qxl_memslot, struct guest_slots),
2422 VMSTATE_STRUCT(guest_primary.surface, PCIQXLDevice, 0,
2423 qxl_surface, QXLSurfaceCreate),
d2164ad3 2424 VMSTATE_INT32_EQUAL(ssd.num_surfaces, PCIQXLDevice, NULL),
ddd8fdc7
GH		 2425 VMSTATE_VARRAY_INT32(guest_surfaces.cmds, PCIQXLDevice,
2426 ssd.num_surfaces, 0,
2427 vmstate_info_uint64, uint64_t),
b67737a6 2428 VMSTATE_UINT64(guest_cursor, PCIQXLDevice),
a19cbfb3
GH		 2429 VMSTATE_END_OF_LIST()
2430 },
5cd8cada
JQ		 2431 .subsections = (const VMStateDescription*[]) {
2432 &qxl_vmstate_monitors_config,
2433 NULL
020af1c4 2434 }
a19cbfb3
GH		 2435};
2436
78e60ba5 2437static Property qxl_properties[] = {
f0353b0d
PMD		 2438 DEFINE_PROP_UINT32("ram_size", PCIQXLDevice, vga.vram_size, 64 * MiB),
2439 DEFINE_PROP_UINT64("vram_size", PCIQXLDevice, vram32_size, 64 * MiB),
78e60ba5
GH		 2440 DEFINE_PROP_UINT32("revision", PCIQXLDevice, revision,
2441 QXL_DEFAULT_REVISION),
2442 DEFINE_PROP_UINT32("debug", PCIQXLDevice, debug, 0),
2443 DEFINE_PROP_UINT32("guestdebug", PCIQXLDevice, guestdebug, 0),
2444 DEFINE_PROP_UINT32("cmdlog", PCIQXLDevice, cmdlog, 0),
017438ee 2445 DEFINE_PROP_UINT32("ram_size_mb", PCIQXLDevice, ram_size_mb, -1),
79ce3567
AL		 2446 DEFINE_PROP_UINT32("vram_size_mb", PCIQXLDevice, vram32_size_mb, -1),
2447 DEFINE_PROP_UINT32("vram64_size_mb", PCIQXLDevice, vram_size_mb, -1),
9e56edcf 2448 DEFINE_PROP_UINT32("vgamem_mb", PCIQXLDevice, vgamem_size_mb, 16),
ddd8fdc7 2449 DEFINE_PROP_INT32("surfaces", PCIQXLDevice, ssd.num_surfaces, 1024),
567161fd
FZ		 2450#if SPICE_SERVER_VERSION >= 0x000c06 /* release 0.12.6 */
2451 DEFINE_PROP_UINT16("max_outputs", PCIQXLDevice, max_outputs, 0),
2452#endif
6f663d7b
GH		 2453 DEFINE_PROP_UINT32("xres", PCIQXLDevice, xres, 0),
2454 DEFINE_PROP_UINT32("yres", PCIQXLDevice, yres, 0),
1fcfdc43 2455 DEFINE_PROP_BOOL("global-vmstate", PCIQXLDevice, vga.global_vmstate, false),
78e60ba5
GH		 2456 DEFINE_PROP_END_OF_LIST(),
2457};
2458
c69f6c7d 2459static void qxl_pci_class_init(ObjectClass *klass, void *data)
40021f08 2460{
39bffca2 2461 DeviceClass *dc = DEVICE_CLASS(klass);
40021f08
AL		 2462 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
2463
40021f08
AL		 2464 k->vendor_id = REDHAT_PCI_VENDOR_ID;
2465 k->device_id = QXL_DEVICE_ID_STABLE;
125ee0ed 2466 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
39bffca2
AL		 2467 dc->reset = qxl_reset_handler;
2468 dc->vmsd = &qxl_vmstate;
2469 dc->props = qxl_properties;
c69f6c7d
GA		 2470}
2471
2472static const TypeInfo qxl_pci_type_info = {
2473 .name = TYPE_PCI_QXL,
2474 .parent = TYPE_PCI_DEVICE,
2475 .instance_size = sizeof(PCIQXLDevice),
2476 .abstract = true,
2477 .class_init = qxl_pci_class_init,
fd3b02c8
EH		 2478 .interfaces = (InterfaceInfo[]) {
2479 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
2480 { },
2481 },
c69f6c7d
GA		 2482};
2483
2484static void qxl_primary_class_init(ObjectClass *klass, void *data)
2485{
2486 DeviceClass *dc = DEVICE_CLASS(klass);
2487 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
2488
2489 k->realize = qxl_realize_primary;
2490 k->romfile = "vgabios-qxl.bin";
2491 k->class_id = PCI_CLASS_DISPLAY_VGA;
2492 dc->desc = "Spice QXL GPU (primary, vga compatible)";
2897ae02 2493 dc->hotpluggable = false;
40021f08
AL		 2494}
2495
8c43a6f0 2496static const TypeInfo qxl_primary_info = {
39bffca2 2497 .name = "qxl-vga",
c69f6c7d 2498 .parent = TYPE_PCI_QXL,
39bffca2 2499 .class_init = qxl_primary_class_init,
a19cbfb3
GH		 2500};
2501
40021f08
AL		 2502static void qxl_secondary_class_init(ObjectClass *klass, void *data)
2503{
39bffca2 2504 DeviceClass *dc = DEVICE_CLASS(klass);
40021f08
AL		 2505 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
2506
042a24db 2507 k->realize = qxl_realize_secondary;
40021f08 2508 k->class_id = PCI_CLASS_DISPLAY_OTHER;
39bffca2 2509 dc->desc = "Spice QXL GPU (secondary)";
40021f08
AL		 2510}
2511
8c43a6f0 2512static const TypeInfo qxl_secondary_info = {
39bffca2 2513 .name = "qxl",
c69f6c7d 2514 .parent = TYPE_PCI_QXL,
39bffca2 2515 .class_init = qxl_secondary_class_init,
a19cbfb3
GH		 2516};
2517
83f7d43a 2518static void qxl_register_types(void)
a19cbfb3 2519{
c69f6c7d 2520 type_register_static(&qxl_pci_type_info);
39bffca2
AL		 2521 type_register_static(&qxl_primary_info);
2522 type_register_static(&qxl_secondary_info);
a19cbfb3
GH		 2523}
2524
83f7d43a 2525type_init(qxl_register_types)
Empty description
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