[qemu.git] / hw / dma / xilinx_axidma.c

/*
 * QEMU model of Xilinx AXI-DMA block.
 *
 * Copyright (c) 2011 Edgar E. Iglesias.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

#include "qemu/osdep.h"
#include "hw/sysbus.h"
#include "qemu/timer.h"
#include "hw/ptimer.h"
#include "qemu/log.h"
#include "qemu/main-loop.h"

#include "hw/stream.h"

#define D(x)

#define TYPE_XILINX_AXI_DMA "xlnx.axi-dma"
#define TYPE_XILINX_AXI_DMA_DATA_STREAM "xilinx-axi-dma-data-stream"
#define TYPE_XILINX_AXI_DMA_CONTROL_STREAM "xilinx-axi-dma-control-stream"

#define XILINX_AXI_DMA(obj) \
     OBJECT_CHECK(XilinxAXIDMA, (obj), TYPE_XILINX_AXI_DMA)

#define XILINX_AXI_DMA_DATA_STREAM(obj) \
     OBJECT_CHECK(XilinxAXIDMAStreamSlave, (obj),\
     TYPE_XILINX_AXI_DMA_DATA_STREAM)

#define XILINX_AXI_DMA_CONTROL_STREAM(obj) \
     OBJECT_CHECK(XilinxAXIDMAStreamSlave, (obj),\
     TYPE_XILINX_AXI_DMA_CONTROL_STREAM)

#define R_DMACR             (0x00 / 4)
#define R_DMASR             (0x04 / 4)
#define R_CURDESC           (0x08 / 4)
#define R_TAILDESC          (0x10 / 4)
#define R_MAX               (0x30 / 4)

#define CONTROL_PAYLOAD_WORDS 5
#define CONTROL_PAYLOAD_SIZE (CONTROL_PAYLOAD_WORDS * (sizeof(uint32_t)))

typedef struct XilinxAXIDMA XilinxAXIDMA;
typedef struct XilinxAXIDMAStreamSlave XilinxAXIDMAStreamSlave;

enum {
    DMACR_RUNSTOP = 1,
    DMACR_TAILPTR_MODE = 2,
    DMACR_RESET = 4
};

enum {
    DMASR_HALTED = 1,
    DMASR_IDLE  = 2,
    DMASR_IOC_IRQ  = 1 << 12,
    DMASR_DLY_IRQ  = 1 << 13,

    DMASR_IRQ_MASK = 7 << 12
};

struct SDesc {
    uint64_t nxtdesc;
    uint64_t buffer_address;
    uint64_t reserved;
    uint32_t control;
    uint32_t status;
    uint8_t app[CONTROL_PAYLOAD_SIZE];
};

enum {
    SDESC_CTRL_EOF = (1 << 26),
    SDESC_CTRL_SOF = (1 << 27),

    SDESC_CTRL_LEN_MASK = (1 << 23) - 1
};

enum {
    SDESC_STATUS_EOF = (1 << 26),
    SDESC_STATUS_SOF_BIT = 27,
    SDESC_STATUS_SOF = (1 << SDESC_STATUS_SOF_BIT),
    SDESC_STATUS_COMPLETE = (1 << 31)
};

struct Stream {
    QEMUBH *bh;
    ptimer_state *ptimer;
    qemu_irq irq;

    int nr;

    struct SDesc desc;
    int pos;
    unsigned int complete_cnt;
    uint32_t regs[R_MAX];
    uint8_t app[20];
};

struct XilinxAXIDMAStreamSlave {
    Object parent;

    struct XilinxAXIDMA *dma;
};

struct XilinxAXIDMA {
    SysBusDevice busdev;
    MemoryRegion iomem;
    uint32_t freqhz;
    StreamSlave *tx_data_dev;
    StreamSlave *tx_control_dev;
    XilinxAXIDMAStreamSlave rx_data_dev;
    XilinxAXIDMAStreamSlave rx_control_dev;

    struct Stream streams[2];

    StreamCanPushNotifyFn notify;
    void *notify_opaque;
};

/*
 * Helper calls to extract info from descriptors and other trivial
 * state from regs.
 */
static inline int stream_desc_sof(struct SDesc *d)
{
    return d->control & SDESC_CTRL_SOF;
}

static inline int stream_desc_eof(struct SDesc *d)
{
    return d->control & SDESC_CTRL_EOF;
}

static inline int stream_resetting(struct Stream *s)
{
    return !!(s->regs[R_DMACR] & DMACR_RESET);
}

static inline int stream_running(struct Stream *s)
{
    return s->regs[R_DMACR] & DMACR_RUNSTOP;
}

static inline int stream_idle(struct Stream *s)
{
    return !!(s->regs[R_DMASR] & DMASR_IDLE);
}

static void stream_reset(struct Stream *s)
{
    s->regs[R_DMASR] = DMASR_HALTED;  /* starts up halted.  */
    s->regs[R_DMACR] = 1 << 16; /* Starts with one in compl threshold.  */
}

/* Map an offset addr into a channel index.  */
static inline int streamid_from_addr(hwaddr addr)
{
    int sid;

    sid = addr / (0x30);
    sid &= 1;
    return sid;
}

static void stream_desc_load(struct Stream *s, hwaddr addr)
{
    struct SDesc *d = &s->desc;

    cpu_physical_memory_read(addr, d, sizeof *d);

    /* Convert from LE into host endianness.  */
    d->buffer_address = le64_to_cpu(d->buffer_address);
    d->nxtdesc = le64_to_cpu(d->nxtdesc);
    d->control = le32_to_cpu(d->control);
    d->status = le32_to_cpu(d->status);
}

static void stream_desc_store(struct Stream *s, hwaddr addr)
{
    struct SDesc *d = &s->desc;

    /* Convert from host endianness into LE.  */
    d->buffer_address = cpu_to_le64(d->buffer_address);
    d->nxtdesc = cpu_to_le64(d->nxtdesc);
    d->control = cpu_to_le32(d->control);
    d->status = cpu_to_le32(d->status);
    cpu_physical_memory_write(addr, d, sizeof *d);
}

static void stream_update_irq(struct Stream *s)
{
    unsigned int pending, mask, irq;

    pending = s->regs[R_DMASR] & DMASR_IRQ_MASK;
    mask = s->regs[R_DMACR] & DMASR_IRQ_MASK;

    irq = pending & mask;

    qemu_set_irq(s->irq, !!irq);
}

static void stream_reload_complete_cnt(struct Stream *s)
{
    unsigned int comp_th;
    comp_th = (s->regs[R_DMACR] >> 16) & 0xff;
    s->complete_cnt = comp_th;
}

static void timer_hit(void *opaque)
{
    struct Stream *s = opaque;

    stream_reload_complete_cnt(s);
    s->regs[R_DMASR] |= DMASR_DLY_IRQ;
    stream_update_irq(s);
}

static void stream_complete(struct Stream *s)
{
    unsigned int comp_delay;

    /* Start the delayed timer.  */
    comp_delay = s->regs[R_DMACR] >> 24;
    if (comp_delay) {
        ptimer_stop(s->ptimer);
        ptimer_set_count(s->ptimer, comp_delay);
        ptimer_run(s->ptimer, 1);
    }

    s->complete_cnt--;
    if (s->complete_cnt == 0) {
        /* Raise the IOC irq.  */
        s->regs[R_DMASR] |= DMASR_IOC_IRQ;
        stream_reload_complete_cnt(s);
    }
}

static void stream_process_mem2s(struct Stream *s, StreamSlave *tx_data_dev,
                                 StreamSlave *tx_control_dev)
{
    uint32_t prev_d;
    unsigned char txbuf[16 * 1024];
    unsigned int txlen;

    if (!stream_running(s) || stream_idle(s)) {
        return;
    }

    while (1) {
        stream_desc_load(s, s->regs[R_CURDESC]);

        if (s->desc.status & SDESC_STATUS_COMPLETE) {
            s->regs[R_DMASR] |= DMASR_HALTED;
            break;
        }

        if (stream_desc_sof(&s->desc)) {
            s->pos = 0;
            stream_push(tx_control_dev, s->desc.app, sizeof(s->desc.app));
        }

        txlen = s->desc.control & SDESC_CTRL_LEN_MASK;
        if ((txlen + s->pos) > sizeof txbuf) {
            hw_error("%s: too small internal txbuf! %d\n", __func__,
                     txlen + s->pos);
        }

        cpu_physical_memory_read(s->desc.buffer_address,
                                 txbuf + s->pos, txlen);
        s->pos += txlen;

        if (stream_desc_eof(&s->desc)) {
            stream_push(tx_data_dev, txbuf, s->pos);
            s->pos = 0;
            stream_complete(s);
        }

        /* Update the descriptor.  */
        s->desc.status = txlen | SDESC_STATUS_COMPLETE;
        stream_desc_store(s, s->regs[R_CURDESC]);

        /* Advance.  */
        prev_d = s->regs[R_CURDESC];
        s->regs[R_CURDESC] = s->desc.nxtdesc;
        if (prev_d == s->regs[R_TAILDESC]) {
            s->regs[R_DMASR] |= DMASR_IDLE;
            break;
        }
    }
}

static size_t stream_process_s2mem(struct Stream *s, unsigned char *buf,
                                   size_t len)
{
    uint32_t prev_d;
    unsigned int rxlen;
    size_t pos = 0;
    int sof = 1;

    if (!stream_running(s) || stream_idle(s)) {
        return 0;
    }

    while (len) {
        stream_desc_load(s, s->regs[R_CURDESC]);

        if (s->desc.status & SDESC_STATUS_COMPLETE) {
            s->regs[R_DMASR] |= DMASR_HALTED;
            break;
        }

        rxlen = s->desc.control & SDESC_CTRL_LEN_MASK;
        if (rxlen > len) {
            /* It fits.  */
            rxlen = len;
        }

        cpu_physical_memory_write(s->desc.buffer_address, buf + pos, rxlen);
        len -= rxlen;
        pos += rxlen;

        /* Update the descriptor.  */
        if (!len) {
            stream_complete(s);
            memcpy(s->desc.app, s->app, sizeof(s->desc.app));
            s->desc.status |= SDESC_STATUS_EOF;
        }

        s->desc.status |= sof << SDESC_STATUS_SOF_BIT;
        s->desc.status |= SDESC_STATUS_COMPLETE;
        stream_desc_store(s, s->regs[R_CURDESC]);
        sof = 0;

        /* Advance.  */
        prev_d = s->regs[R_CURDESC];
        s->regs[R_CURDESC] = s->desc.nxtdesc;
        if (prev_d == s->regs[R_TAILDESC]) {
            s->regs[R_DMASR] |= DMASR_IDLE;
            break;
        }
    }

    return pos;
}

static void xilinx_axidma_reset(DeviceState *dev)
{
    int i;
    XilinxAXIDMA *s = XILINX_AXI_DMA(dev);

    for (i = 0; i < 2; i++) {
        stream_reset(&s->streams[i]);
    }
}

static size_t
xilinx_axidma_control_stream_push(StreamSlave *obj, unsigned char *buf,
                                  size_t len)
{
    XilinxAXIDMAStreamSlave *cs = XILINX_AXI_DMA_CONTROL_STREAM(obj);
    struct Stream *s = &cs->dma->streams[1];

    if (len != CONTROL_PAYLOAD_SIZE) {
        hw_error("AXI DMA requires %d byte control stream payload\n",
                 (int)CONTROL_PAYLOAD_SIZE);
    }

    memcpy(s->app, buf, len);
    return len;
}

static bool
xilinx_axidma_data_stream_can_push(StreamSlave *obj,
                                   StreamCanPushNotifyFn notify,
                                   void *notify_opaque)
{
    XilinxAXIDMAStreamSlave *ds = XILINX_AXI_DMA_DATA_STREAM(obj);
    struct Stream *s = &ds->dma->streams[1];

    if (!stream_running(s) || stream_idle(s)) {
        ds->dma->notify = notify;
        ds->dma->notify_opaque = notify_opaque;
        return false;
    }

    return true;
}

static size_t
xilinx_axidma_data_stream_push(StreamSlave *obj, unsigned char *buf, size_t len)
{
    XilinxAXIDMAStreamSlave *ds = XILINX_AXI_DMA_DATA_STREAM(obj);
    struct Stream *s = &ds->dma->streams[1];
    size_t ret;

    ret = stream_process_s2mem(s, buf, len);
    stream_update_irq(s);
    return ret;
}

static uint64_t axidma_read(void *opaque, hwaddr addr,
                            unsigned size)
{
    XilinxAXIDMA *d = opaque;
    struct Stream *s;
    uint32_t r = 0;
    int sid;

    sid = streamid_from_addr(addr);
    s = &d->streams[sid];

    addr = addr % 0x30;
    addr >>= 2;
    switch (addr) {
        case R_DMACR:
            /* Simulate one cycles reset delay.  */
            s->regs[addr] &= ~DMACR_RESET;
            r = s->regs[addr];
            break;
        case R_DMASR:
            s->regs[addr] &= 0xffff;
            s->regs[addr] |= (s->complete_cnt & 0xff) << 16;
            s->regs[addr] |= (ptimer_get_count(s->ptimer) & 0xff) << 24;
            r = s->regs[addr];
            break;
        default:
            r = s->regs[addr];
            D(qemu_log("%s ch=%d addr=" TARGET_FMT_plx " v=%x\n",
                           __func__, sid, addr * 4, r));
            break;
    }
    return r;

}

static void axidma_write(void *opaque, hwaddr addr,
                         uint64_t value, unsigned size)
{
    XilinxAXIDMA *d = opaque;
    struct Stream *s;
    int sid;

    sid = streamid_from_addr(addr);
    s = &d->streams[sid];

    addr = addr % 0x30;
    addr >>= 2;
    switch (addr) {
        case R_DMACR:
            /* Tailptr mode is always on.  */
            value |= DMACR_TAILPTR_MODE;
            /* Remember our previous reset state.  */
            value |= (s->regs[addr] & DMACR_RESET);
            s->regs[addr] = value;

            if (value & DMACR_RESET) {
                stream_reset(s);
            }

            if ((value & 1) && !stream_resetting(s)) {
                /* Start processing.  */
                s->regs[R_DMASR] &= ~(DMASR_HALTED | DMASR_IDLE);
            }
            stream_reload_complete_cnt(s);
            break;

        case R_DMASR:
            /* Mask away write to clear irq lines.  */
            value &= ~(value & DMASR_IRQ_MASK);
            s->regs[addr] = value;
            break;

        case R_TAILDESC:
            s->regs[addr] = value;
            s->regs[R_DMASR] &= ~DMASR_IDLE; /* Not idle.  */
            if (!sid) {
                stream_process_mem2s(s, d->tx_data_dev, d->tx_control_dev);
            }
            break;
        default:
            D(qemu_log("%s: ch=%d addr=" TARGET_FMT_plx " v=%x\n",
                  __func__, sid, addr * 4, (unsigned)value));
            s->regs[addr] = value;
            break;
    }
    if (sid == 1 && d->notify) {
        StreamCanPushNotifyFn notifytmp = d->notify;
        d->notify = NULL;
        notifytmp(d->notify_opaque);
    }
    stream_update_irq(s);
}

static const MemoryRegionOps axidma_ops = {
    .read = axidma_read,
    .write = axidma_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

static void xilinx_axidma_realize(DeviceState *dev, Error **errp)
{
    XilinxAXIDMA *s = XILINX_AXI_DMA(dev);
    XilinxAXIDMAStreamSlave *ds = XILINX_AXI_DMA_DATA_STREAM(&s->rx_data_dev);
    XilinxAXIDMAStreamSlave *cs = XILINX_AXI_DMA_CONTROL_STREAM(
                                                            &s->rx_control_dev);
    Error *local_err = NULL;

    object_property_add_link(OBJECT(ds), "dma", TYPE_XILINX_AXI_DMA,
                             (Object **)&ds->dma,
                             object_property_allow_set_link,
                             OBJ_PROP_LINK_UNREF_ON_RELEASE,
                             &local_err);
    object_property_add_link(OBJECT(cs), "dma", TYPE_XILINX_AXI_DMA,
                             (Object **)&cs->dma,
                             object_property_allow_set_link,
                             OBJ_PROP_LINK_UNREF_ON_RELEASE,
                             &local_err);
    if (local_err) {
        goto xilinx_axidma_realize_fail;
    }
    object_property_set_link(OBJECT(ds), OBJECT(s), "dma", &local_err);
    object_property_set_link(OBJECT(cs), OBJECT(s), "dma", &local_err);
    if (local_err) {
        goto xilinx_axidma_realize_fail;
    }

    int i;

    for (i = 0; i < 2; i++) {
        struct Stream *st = &s->streams[i];

        st->nr = i;
        st->bh = qemu_bh_new(timer_hit, st);
        st->ptimer = ptimer_init(st->bh);
        ptimer_set_freq(st->ptimer, s->freqhz);
    }
    return;

xilinx_axidma_realize_fail:
    if (!*errp) {
        *errp = local_err;
    }
}

static void xilinx_axidma_init(Object *obj)
{
    XilinxAXIDMA *s = XILINX_AXI_DMA(obj);
    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);

    object_property_add_link(obj, "axistream-connected", TYPE_STREAM_SLAVE,
                             (Object **)&s->tx_data_dev,
                             qdev_prop_allow_set_link_before_realize,
                             OBJ_PROP_LINK_UNREF_ON_RELEASE,
                             &error_abort);
    object_property_add_link(obj, "axistream-control-connected",
                             TYPE_STREAM_SLAVE,
                             (Object **)&s->tx_control_dev,
                             qdev_prop_allow_set_link_before_realize,
                             OBJ_PROP_LINK_UNREF_ON_RELEASE,
                             &error_abort);

    object_initialize(&s->rx_data_dev, sizeof(s->rx_data_dev),
                      TYPE_XILINX_AXI_DMA_DATA_STREAM);
    object_initialize(&s->rx_control_dev, sizeof(s->rx_control_dev),
                      TYPE_XILINX_AXI_DMA_CONTROL_STREAM);
    object_property_add_child(OBJECT(s), "axistream-connected-target",
                              (Object *)&s->rx_data_dev, &error_abort);
    object_property_add_child(OBJECT(s), "axistream-control-connected-target",
                              (Object *)&s->rx_control_dev, &error_abort);

    sysbus_init_irq(sbd, &s->streams[0].irq);
    sysbus_init_irq(sbd, &s->streams[1].irq);

    memory_region_init_io(&s->iomem, obj, &axidma_ops, s,
                          "xlnx.axi-dma", R_MAX * 4 * 2);
    sysbus_init_mmio(sbd, &s->iomem);
}

static Property axidma_properties[] = {
    DEFINE_PROP_UINT32("freqhz", XilinxAXIDMA, freqhz, 50000000),
    DEFINE_PROP_END_OF_LIST(),
};

static void axidma_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);

    dc->realize = xilinx_axidma_realize,
    dc->reset = xilinx_axidma_reset;
    dc->props = axidma_properties;
}

static StreamSlaveClass xilinx_axidma_data_stream_class = {
    .push = xilinx_axidma_data_stream_push,
    .can_push = xilinx_axidma_data_stream_can_push,
};

static StreamSlaveClass xilinx_axidma_control_stream_class = {
    .push = xilinx_axidma_control_stream_push,
};

static void xilinx_axidma_stream_class_init(ObjectClass *klass, void *data)
{
    StreamSlaveClass *ssc = STREAM_SLAVE_CLASS(klass);

    ssc->push = ((StreamSlaveClass *)data)->push;
    ssc->can_push = ((StreamSlaveClass *)data)->can_push;
}

static const TypeInfo axidma_info = {
    .name          = TYPE_XILINX_AXI_DMA,
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(XilinxAXIDMA),
    .class_init    = axidma_class_init,
    .instance_init = xilinx_axidma_init,
};

static const TypeInfo xilinx_axidma_data_stream_info = {
    .name          = TYPE_XILINX_AXI_DMA_DATA_STREAM,
    .parent        = TYPE_OBJECT,
    .instance_size = sizeof(struct XilinxAXIDMAStreamSlave),
    .class_init    = xilinx_axidma_stream_class_init,
    .class_data    = &xilinx_axidma_data_stream_class,
    .interfaces = (InterfaceInfo[]) {
        { TYPE_STREAM_SLAVE },
        { }
    }
};

static const TypeInfo xilinx_axidma_control_stream_info = {
    .name          = TYPE_XILINX_AXI_DMA_CONTROL_STREAM,
    .parent        = TYPE_OBJECT,
    .instance_size = sizeof(struct XilinxAXIDMAStreamSlave),
    .class_init    = xilinx_axidma_stream_class_init,
    .class_data    = &xilinx_axidma_control_stream_class,
    .interfaces = (InterfaceInfo[]) {
        { TYPE_STREAM_SLAVE },
        { }
    }
};

static void xilinx_axidma_register_types(void)
{
    type_register_static(&axidma_info);
    type_register_static(&xilinx_axidma_data_stream_info);
    type_register_static(&xilinx_axidma_control_stream_info);
}

type_init(xilinx_axidma_register_types)
Commit	Line	Data
93f1e401 EI	1	/*
	2	* QEMU model of Xilinx AXI-DMA block.
	3	*
	4	* Copyright (c) 2011 Edgar E. Iglesias.
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
	24
17b7f2db	25	#include "qemu/osdep.h"
83c9f4ca	26	#include "hw/sysbus.h"
1de7afc9	27	#include "qemu/timer.h"
83c9f4ca	28	#include "hw/ptimer.h"
1de7afc9	29	#include "qemu/log.h"
6a1751b7	30	#include "qemu/main-loop.h"
93f1e401	31
83c9f4ca	32	#include "hw/stream.h"
93f1e401 EI	33
	34	#define D(x)
	35
cbde584f	36	#define TYPE_XILINX_AXI_DMA "xlnx.axi-dma"
e1500e35	37	#define TYPE_XILINX_AXI_DMA_DATA_STREAM "xilinx-axi-dma-data-stream"
42bb9c91	38	#define TYPE_XILINX_AXI_DMA_CONTROL_STREAM "xilinx-axi-dma-control-stream"
cbde584f PC	39
	40	#define XILINX_AXI_DMA(obj) \
	41	OBJECT_CHECK(XilinxAXIDMA, (obj), TYPE_XILINX_AXI_DMA)
	42
e1500e35 PC	43	#define XILINX_AXI_DMA_DATA_STREAM(obj) \
	44	OBJECT_CHECK(XilinxAXIDMAStreamSlave, (obj),\
	45	TYPE_XILINX_AXI_DMA_DATA_STREAM)
	46
42bb9c91 PC	47	#define XILINX_AXI_DMA_CONTROL_STREAM(obj) \
	48	OBJECT_CHECK(XilinxAXIDMAStreamSlave, (obj),\
	49	TYPE_XILINX_AXI_DMA_CONTROL_STREAM)
	50
93f1e401 EI	51	#define R_DMACR (0x00 / 4)
	52	#define R_DMASR (0x04 / 4)
	53	#define R_CURDESC (0x08 / 4)
	54	#define R_TAILDESC (0x10 / 4)
	55	#define R_MAX (0x30 / 4)
	56
42bb9c91 PC	57	#define CONTROL_PAYLOAD_WORDS 5
	58	#define CONTROL_PAYLOAD_SIZE (CONTROL_PAYLOAD_WORDS * (sizeof(uint32_t)))
	59
42e8a283	60	typedef struct XilinxAXIDMA XilinxAXIDMA;
e1500e35	61	typedef struct XilinxAXIDMAStreamSlave XilinxAXIDMAStreamSlave;
42e8a283	62
93f1e401 EI	63	enum {
	64	DMACR_RUNSTOP = 1,
	65	DMACR_TAILPTR_MODE = 2,
	66	DMACR_RESET = 4
	67	};
	68
	69	enum {
	70	DMASR_HALTED = 1,
	71	DMASR_IDLE = 2,
	72	DMASR_IOC_IRQ = 1 << 12,
	73	DMASR_DLY_IRQ = 1 << 13,
	74
	75	DMASR_IRQ_MASK = 7 << 12
	76	};
	77
	78	struct SDesc {
	79	uint64_t nxtdesc;
	80	uint64_t buffer_address;
	81	uint64_t reserved;
	82	uint32_t control;
	83	uint32_t status;
42bb9c91	84	uint8_t app[CONTROL_PAYLOAD_SIZE];
93f1e401 EI	85	};
	86
	87	enum {
	88	SDESC_CTRL_EOF = (1 << 26),
	89	SDESC_CTRL_SOF = (1 << 27),
	90
	91	SDESC_CTRL_LEN_MASK = (1 << 23) - 1
	92	};
	93
	94	enum {
	95	SDESC_STATUS_EOF = (1 << 26),
	96	SDESC_STATUS_SOF_BIT = 27,
	97	SDESC_STATUS_SOF = (1 << SDESC_STATUS_SOF_BIT),
	98	SDESC_STATUS_COMPLETE = (1 << 31)
	99	};
	100
669b4983	101	struct Stream {
93f1e401 EI	102	QEMUBH *bh;
	103	ptimer_state *ptimer;
	104	qemu_irq irq;
	105
	106	int nr;
	107
	108	struct SDesc desc;
	109	int pos;
	110	unsigned int complete_cnt;
	111	uint32_t regs[R_MAX];
42bb9c91	112	uint8_t app[20];
93f1e401 EI	113	};
93f1e401 EI	114
e1500e35 PC	115	struct XilinxAXIDMAStreamSlave {
	116	Object parent;
	117
	118	struct XilinxAXIDMA *dma;
	119	};
	120
93f1e401 EI	121	struct XilinxAXIDMA {
93f1e401 EI	122	SysBusDevice busdev;
f810bc4a	123	MemoryRegion iomem;
93f1e401	124	uint32_t freqhz;
42bb9c91 PC	125	StreamSlave *tx_data_dev;
42bb9c91 PC	126	StreamSlave *tx_control_dev;
e1500e35	127	XilinxAXIDMAStreamSlave rx_data_dev;
42bb9c91	128	XilinxAXIDMAStreamSlave rx_control_dev;
93f1e401	129
669b4983	130	struct Stream streams[2];
3630ae95 PC	131
	132	StreamCanPushNotifyFn notify;
	133	void *notify_opaque;
93f1e401 EI	134	};
	135
	136	/*
67cc32eb	137	* Helper calls to extract info from descriptors and other trivial
93f1e401 EI	138	* state from regs.
	139	*/
	140	static inline int stream_desc_sof(struct SDesc *d)
	141	{
	142	return d->control & SDESC_CTRL_SOF;
	143	}
	144
	145	static inline int stream_desc_eof(struct SDesc *d)
	146	{
	147	return d->control & SDESC_CTRL_EOF;
	148	}
	149
669b4983	150	static inline int stream_resetting(struct Stream *s)
93f1e401 EI	151	{
	152	return !!(s->regs[R_DMACR] & DMACR_RESET);
	153	}
	154
669b4983	155	static inline int stream_running(struct Stream *s)
93f1e401 EI	156	{
	157	return s->regs[R_DMACR] & DMACR_RUNSTOP;
	158	}
	159
669b4983	160	static inline int stream_idle(struct Stream *s)
93f1e401 EI	161	{
	162	return !!(s->regs[R_DMASR] & DMASR_IDLE);
	163	}
	164
669b4983	165	static void stream_reset(struct Stream *s)
93f1e401 EI	166	{
93f1e401 EI	167	s->regs[R_DMASR] = DMASR_HALTED; /* starts up halted. */
0d50d616	168	s->regs[R_DMACR] = 1 << 16; /* Starts with one in compl threshold. */
93f1e401 EI	169	}
93f1e401 EI	170
0d50d616	171	/* Map an offset addr into a channel index. */
a8170e5e	172	static inline int streamid_from_addr(hwaddr addr)
93f1e401 EI	173	{
	174	int sid;
	175
	176	sid = addr / (0x30);
	177	sid &= 1;
	178	return sid;
	179	}
	180
a8170e5e	181	static void stream_desc_load(struct Stream *s, hwaddr addr)
93f1e401 EI	182	{
93f1e401 EI	183	struct SDesc *d = &s->desc;
93f1e401	184
e1fe50dc	185	cpu_physical_memory_read(addr, d, sizeof *d);
93f1e401 EI	186
	187	/* Convert from LE into host endianness. */
	188	d->buffer_address = le64_to_cpu(d->buffer_address);
	189	d->nxtdesc = le64_to_cpu(d->nxtdesc);
	190	d->control = le32_to_cpu(d->control);
	191	d->status = le32_to_cpu(d->status);
93f1e401 EI	192	}
93f1e401 EI	193
a8170e5e	194	static void stream_desc_store(struct Stream *s, hwaddr addr)
93f1e401 EI	195	{
93f1e401 EI	196	struct SDesc *d = &s->desc;
93f1e401 EI	197
	198	/* Convert from host endianness into LE. */
	199	d->buffer_address = cpu_to_le64(d->buffer_address);
	200	d->nxtdesc = cpu_to_le64(d->nxtdesc);
	201	d->control = cpu_to_le32(d->control);
	202	d->status = cpu_to_le32(d->status);
e1fe50dc	203	cpu_physical_memory_write(addr, d, sizeof *d);
93f1e401 EI	204	}
93f1e401 EI	205
669b4983	206	static void stream_update_irq(struct Stream *s)
93f1e401 EI	207	{
	208	unsigned int pending, mask, irq;
	209
	210	pending = s->regs[R_DMASR] & DMASR_IRQ_MASK;
	211	mask = s->regs[R_DMACR] & DMASR_IRQ_MASK;
	212
	213	irq = pending & mask;
	214
	215	qemu_set_irq(s->irq, !!irq);
	216	}
	217
669b4983	218	static void stream_reload_complete_cnt(struct Stream *s)
93f1e401 EI	219	{
	220	unsigned int comp_th;
	221	comp_th = (s->regs[R_DMACR] >> 16) & 0xff;
	222	s->complete_cnt = comp_th;
	223	}
	224
	225	static void timer_hit(void *opaque)
	226	{
669b4983	227	struct Stream *s = opaque;
93f1e401 EI	228
	229	stream_reload_complete_cnt(s);
	230	s->regs[R_DMASR] \|= DMASR_DLY_IRQ;
	231	stream_update_irq(s);
	232	}
	233
669b4983	234	static void stream_complete(struct Stream *s)
93f1e401 EI	235	{
	236	unsigned int comp_delay;
	237
	238	/* Start the delayed timer. */
	239	comp_delay = s->regs[R_DMACR] >> 24;
	240	if (comp_delay) {
	241	ptimer_stop(s->ptimer);
	242	ptimer_set_count(s->ptimer, comp_delay);
	243	ptimer_run(s->ptimer, 1);
	244	}
	245
	246	s->complete_cnt--;
	247	if (s->complete_cnt == 0) {
	248	/* Raise the IOC irq. */
	249	s->regs[R_DMASR] \|= DMASR_IOC_IRQ;
	250	stream_reload_complete_cnt(s);
	251	}
	252	}
	253
42bb9c91 PC	254	static void stream_process_mem2s(struct Stream s, StreamSlave tx_data_dev,
42bb9c91 PC	255	StreamSlave *tx_control_dev)
93f1e401 EI	256	{
	257	uint32_t prev_d;
	258	unsigned char txbuf[16 * 1024];
	259	unsigned int txlen;
93f1e401 EI	260
	261	if (!stream_running(s) \|\| stream_idle(s)) {
	262	return;
	263	}
	264
	265	while (1) {
	266	stream_desc_load(s, s->regs[R_CURDESC]);
	267
	268	if (s->desc.status & SDESC_STATUS_COMPLETE) {
210914e2	269	s->regs[R_DMASR] \|= DMASR_HALTED;
93f1e401 EI	270	break;
	271	}
	272
	273	if (stream_desc_sof(&s->desc)) {
	274	s->pos = 0;
42bb9c91	275	stream_push(tx_control_dev, s->desc.app, sizeof(s->desc.app));
93f1e401 EI	276	}
	277
	278	txlen = s->desc.control & SDESC_CTRL_LEN_MASK;
	279	if ((txlen + s->pos) > sizeof txbuf) {
	280	hw_error("%s: too small internal txbuf! %d\n", __func__,
	281	txlen + s->pos);
	282	}
	283
	284	cpu_physical_memory_read(s->desc.buffer_address,
	285	txbuf + s->pos, txlen);
	286	s->pos += txlen;
	287
	288	if (stream_desc_eof(&s->desc)) {
42bb9c91	289	stream_push(tx_data_dev, txbuf, s->pos);
93f1e401 EI	290	s->pos = 0;
	291	stream_complete(s);
	292	}
	293
	294	/* Update the descriptor. */
	295	s->desc.status = txlen \| SDESC_STATUS_COMPLETE;
	296	stream_desc_store(s, s->regs[R_CURDESC]);
	297
	298	/* Advance. */
	299	prev_d = s->regs[R_CURDESC];
	300	s->regs[R_CURDESC] = s->desc.nxtdesc;
	301	if (prev_d == s->regs[R_TAILDESC]) {
	302	s->regs[R_DMASR] \|= DMASR_IDLE;
	303	break;
	304	}
	305	}
	306	}
	307
3630ae95	308	static size_t stream_process_s2mem(struct Stream s, unsigned char buf,
42bb9c91	309	size_t len)
93f1e401 EI	310	{
	311	uint32_t prev_d;
	312	unsigned int rxlen;
3630ae95	313	size_t pos = 0;
93f1e401 EI	314	int sof = 1;
	315
	316	if (!stream_running(s) \|\| stream_idle(s)) {
3630ae95	317	return 0;
93f1e401 EI	318	}
	319
	320	while (len) {
	321	stream_desc_load(s, s->regs[R_CURDESC]);
	322
	323	if (s->desc.status & SDESC_STATUS_COMPLETE) {
210914e2	324	s->regs[R_DMASR] \|= DMASR_HALTED;
93f1e401 EI	325	break;
	326	}
	327
	328	rxlen = s->desc.control & SDESC_CTRL_LEN_MASK;
	329	if (rxlen > len) {
	330	/* It fits. */
	331	rxlen = len;
	332	}
	333
	334	cpu_physical_memory_write(s->desc.buffer_address, buf + pos, rxlen);
	335	len -= rxlen;
	336	pos += rxlen;
	337
	338	/* Update the descriptor. */
	339	if (!len) {
93f1e401	340	stream_complete(s);
42bb9c91	341	memcpy(s->desc.app, s->app, sizeof(s->desc.app));
93f1e401 EI	342	s->desc.status \|= SDESC_STATUS_EOF;
	343	}
	344
	345	s->desc.status \|= sof << SDESC_STATUS_SOF_BIT;
	346	s->desc.status \|= SDESC_STATUS_COMPLETE;
	347	stream_desc_store(s, s->regs[R_CURDESC]);
	348	sof = 0;
	349
	350	/* Advance. */
	351	prev_d = s->regs[R_CURDESC];
	352	s->regs[R_CURDESC] = s->desc.nxtdesc;
	353	if (prev_d == s->regs[R_TAILDESC]) {
	354	s->regs[R_DMASR] \|= DMASR_IDLE;
	355	break;
	356	}
	357	}
3630ae95 PC	358
3630ae95 PC	359	return pos;
93f1e401 EI	360	}
93f1e401 EI	361
897374db PC	362	static void xilinx_axidma_reset(DeviceState *dev)
	363	{
	364	int i;
	365	XilinxAXIDMA *s = XILINX_AXI_DMA(dev);
	366
	367	for (i = 0; i < 2; i++) {
	368	stream_reset(&s->streams[i]);
	369	}
	370	}
	371
42bb9c91 PC	372	static size_t
	373	xilinx_axidma_control_stream_push(StreamSlave obj, unsigned char buf,
	374	size_t len)
	375	{
	376	XilinxAXIDMAStreamSlave *cs = XILINX_AXI_DMA_CONTROL_STREAM(obj);
	377	struct Stream *s = &cs->dma->streams[1];
	378
	379	if (len != CONTROL_PAYLOAD_SIZE) {
	380	hw_error("AXI DMA requires %d byte control stream payload\n",
	381	(int)CONTROL_PAYLOAD_SIZE);
	382	}
	383
	384	memcpy(s->app, buf, len);
	385	return len;
	386	}
	387
3630ae95 PC	388	static bool
	389	xilinx_axidma_data_stream_can_push(StreamSlave *obj,
	390	StreamCanPushNotifyFn notify,
	391	void *notify_opaque)
	392	{
	393	XilinxAXIDMAStreamSlave *ds = XILINX_AXI_DMA_DATA_STREAM(obj);
	394	struct Stream *s = &ds->dma->streams[1];
	395
	396	if (!stream_running(s) \|\| stream_idle(s)) {
	397	ds->dma->notify = notify;
	398	ds->dma->notify_opaque = notify_opaque;
	399	return false;
	400	}
	401
	402	return true;
	403	}
	404
35e60bfd	405	static size_t
42bb9c91	406	xilinx_axidma_data_stream_push(StreamSlave obj, unsigned char buf, size_t len)
93f1e401	407	{
e1500e35 PC	408	XilinxAXIDMAStreamSlave *ds = XILINX_AXI_DMA_DATA_STREAM(obj);
e1500e35 PC	409	struct Stream *s = &ds->dma->streams[1];
3630ae95	410	size_t ret;
93f1e401	411
42bb9c91	412	ret = stream_process_s2mem(s, buf, len);
93f1e401	413	stream_update_irq(s);
3630ae95	414	return ret;
93f1e401 EI	415	}
93f1e401 EI	416
a8170e5e	417	static uint64_t axidma_read(void *opaque, hwaddr addr,
f810bc4a	418	unsigned size)
93f1e401	419	{
42e8a283	420	XilinxAXIDMA *d = opaque;
669b4983	421	struct Stream *s;
93f1e401 EI	422	uint32_t r = 0;
	423	int sid;
	424
	425	sid = streamid_from_addr(addr);
	426	s = &d->streams[sid];
	427
	428	addr = addr % 0x30;
	429	addr >>= 2;
	430	switch (addr) {
	431	case R_DMACR:
	432	/* Simulate one cycles reset delay. */
	433	s->regs[addr] &= ~DMACR_RESET;
	434	r = s->regs[addr];
	435	break;
	436	case R_DMASR:
	437	s->regs[addr] &= 0xffff;
	438	s->regs[addr] \|= (s->complete_cnt & 0xff) << 16;
	439	s->regs[addr] \|= (ptimer_get_count(s->ptimer) & 0xff) << 24;
	440	r = s->regs[addr];
	441	break;
	442	default:
	443	r = s->regs[addr];
	444	D(qemu_log("%s ch=%d addr=" TARGET_FMT_plx " v=%x\n",
	445	__func__, sid, addr * 4, r));
	446	break;
	447	}
	448	return r;
	449
	450	}
	451
a8170e5e	452	static void axidma_write(void *opaque, hwaddr addr,
f810bc4a	453	uint64_t value, unsigned size)
93f1e401	454	{
42e8a283	455	XilinxAXIDMA *d = opaque;
669b4983	456	struct Stream *s;
93f1e401 EI	457	int sid;
	458
	459	sid = streamid_from_addr(addr);
	460	s = &d->streams[sid];
	461
	462	addr = addr % 0x30;
	463	addr >>= 2;
	464	switch (addr) {
	465	case R_DMACR:
	466	/* Tailptr mode is always on. */
	467	value \|= DMACR_TAILPTR_MODE;
	468	/* Remember our previous reset state. */
	469	value \|= (s->regs[addr] & DMACR_RESET);
	470	s->regs[addr] = value;
	471
	472	if (value & DMACR_RESET) {
	473	stream_reset(s);
	474	}
	475
	476	if ((value & 1) && !stream_resetting(s)) {
	477	/* Start processing. */
	478	s->regs[R_DMASR] &= ~(DMASR_HALTED \| DMASR_IDLE);
	479	}
	480	stream_reload_complete_cnt(s);
	481	break;
	482
	483	case R_DMASR:
	484	/* Mask away write to clear irq lines. */
	485	value &= ~(value & DMASR_IRQ_MASK);
	486	s->regs[addr] = value;
	487	break;
	488
	489	case R_TAILDESC:
	490	s->regs[addr] = value;
	491	s->regs[R_DMASR] &= ~DMASR_IDLE; /* Not idle. */
	492	if (!sid) {
42bb9c91	493	stream_process_mem2s(s, d->tx_data_dev, d->tx_control_dev);
93f1e401 EI	494	}
	495	break;
	496	default:
	497	D(qemu_log("%s: ch=%d addr=" TARGET_FMT_plx " v=%x\n",
74cef80c	498	__func__, sid, addr * 4, (unsigned)value));
93f1e401 EI	499	s->regs[addr] = value;
	500	break;
	501	}
3630ae95	502	if (sid == 1 && d->notify) {
4f293bd6	503	StreamCanPushNotifyFn notifytmp = d->notify;
3630ae95	504	d->notify = NULL;
4f293bd6	505	notifytmp(d->notify_opaque);
3630ae95	506	}
93f1e401 EI	507	stream_update_irq(s);
	508	}
	509
f810bc4a AK	510	static const MemoryRegionOps axidma_ops = {
	511	.read = axidma_read,
	512	.write = axidma_write,
	513	.endianness = DEVICE_NATIVE_ENDIAN,
93f1e401 EI	514	};
93f1e401 EI	515
e6543663	516	static void xilinx_axidma_realize(DeviceState dev, Error *errp)
93f1e401	517	{
cbde584f	518	XilinxAXIDMA *s = XILINX_AXI_DMA(dev);
e1500e35	519	XilinxAXIDMAStreamSlave *ds = XILINX_AXI_DMA_DATA_STREAM(&s->rx_data_dev);
42bb9c91 PC	520	XilinxAXIDMAStreamSlave *cs = XILINX_AXI_DMA_CONTROL_STREAM(
42bb9c91 PC	521	&s->rx_control_dev);
2f719f19	522	Error *local_err = NULL;
e1500e35 PC	523
e1500e35 PC	524	object_property_add_link(OBJECT(ds), "dma", TYPE_XILINX_AXI_DMA,
9561fda8	525	(Object **)&ds->dma,
39f72ef9	526	object_property_allow_set_link,
9561fda8	527	OBJ_PROP_LINK_UNREF_ON_RELEASE,
2f719f19	528	&local_err);
42bb9c91	529	object_property_add_link(OBJECT(cs), "dma", TYPE_XILINX_AXI_DMA,
9561fda8	530	(Object **)&cs->dma,
39f72ef9	531	object_property_allow_set_link,
9561fda8	532	OBJ_PROP_LINK_UNREF_ON_RELEASE,
2f719f19 MA	533	&local_err);
2f719f19 MA	534	if (local_err) {
e1500e35 PC	535	goto xilinx_axidma_realize_fail;
e1500e35 PC	536	}
2f719f19 MA	537	object_property_set_link(OBJECT(ds), OBJECT(s), "dma", &local_err);
	538	object_property_set_link(OBJECT(cs), OBJECT(s), "dma", &local_err);
	539	if (local_err) {
e1500e35 PC	540	goto xilinx_axidma_realize_fail;
	541	}
	542
93f1e401 EI	543	int i;
93f1e401 EI	544
93f1e401	545	for (i = 0; i < 2; i++) {
6a07a695 PC	546	struct Stream *st = &s->streams[i];
	547
	548	st->nr = i;
	549	st->bh = qemu_bh_new(timer_hit, st);
	550	st->ptimer = ptimer_init(st->bh);
	551	ptimer_set_freq(st->ptimer, s->freqhz);
93f1e401	552	}
e1500e35 PC	553	return;
	554
	555	xilinx_axidma_realize_fail:
	556	if (!*errp) {
2f719f19	557	*errp = local_err;
e1500e35	558	}
93f1e401 EI	559	}
93f1e401 EI	560
e6543663	561	static void xilinx_axidma_init(Object *obj)
669b4983	562	{
cbde584f	563	XilinxAXIDMA *s = XILINX_AXI_DMA(obj);
e6543663	564	SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
669b4983 PC	565
669b4983 PC	566	object_property_add_link(obj, "axistream-connected", TYPE_STREAM_SLAVE,
9561fda8	567	(Object **)&s->tx_data_dev,
39f72ef9	568	qdev_prop_allow_set_link_before_realize,
9561fda8 SH	569	OBJ_PROP_LINK_UNREF_ON_RELEASE,
9561fda8 SH	570	&error_abort);
42bb9c91 PC	571	object_property_add_link(obj, "axistream-control-connected",
42bb9c91 PC	572	TYPE_STREAM_SLAVE,
9561fda8	573	(Object **)&s->tx_control_dev,
39f72ef9	574	qdev_prop_allow_set_link_before_realize,
9561fda8 SH	575	OBJ_PROP_LINK_UNREF_ON_RELEASE,
9561fda8 SH	576	&error_abort);
e6543663	577
213f0c4f AF	578	object_initialize(&s->rx_data_dev, sizeof(s->rx_data_dev),
	579	TYPE_XILINX_AXI_DMA_DATA_STREAM);
	580	object_initialize(&s->rx_control_dev, sizeof(s->rx_control_dev),
	581	TYPE_XILINX_AXI_DMA_CONTROL_STREAM);
e1500e35	582	object_property_add_child(OBJECT(s), "axistream-connected-target",
5433a0a8	583	(Object *)&s->rx_data_dev, &error_abort);
42bb9c91	584	object_property_add_child(OBJECT(s), "axistream-control-connected-target",
5433a0a8	585	(Object *)&s->rx_control_dev, &error_abort);
e1500e35	586
e6543663 PC	587	sysbus_init_irq(sbd, &s->streams[0].irq);
	588	sysbus_init_irq(sbd, &s->streams[1].irq);
	589
3eadad55	590	memory_region_init_io(&s->iomem, obj, &axidma_ops, s,
e6543663 PC	591	"xlnx.axi-dma", R_MAX * 4 * 2);
e6543663 PC	592	sysbus_init_mmio(sbd, &s->iomem);
669b4983 PC	593	}
669b4983 PC	594
999e12bb	595	static Property axidma_properties[] = {
42e8a283	596	DEFINE_PROP_UINT32("freqhz", XilinxAXIDMA, freqhz, 50000000),
999e12bb AL	597	DEFINE_PROP_END_OF_LIST(),
	598	};
	599
	600	static void axidma_class_init(ObjectClass klass, void data)
	601	{
39bffca2	602	DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb	603
e6543663	604	dc->realize = xilinx_axidma_realize,
897374db	605	dc->reset = xilinx_axidma_reset;
39bffca2	606	dc->props = axidma_properties;
e1500e35 PC	607	}
e1500e35 PC	608
3630ae95 PC	609	static StreamSlaveClass xilinx_axidma_data_stream_class = {
	610	.push = xilinx_axidma_data_stream_push,
	611	.can_push = xilinx_axidma_data_stream_can_push,
	612	};
	613
42bb9c91 PC	614	static StreamSlaveClass xilinx_axidma_control_stream_class = {
	615	.push = xilinx_axidma_control_stream_push,
	616	};
	617
e1500e35 PC	618	static void xilinx_axidma_stream_class_init(ObjectClass klass, void data)
	619	{
	620	StreamSlaveClass *ssc = STREAM_SLAVE_CLASS(klass);
	621
3630ae95 PC	622	ssc->push = ((StreamSlaveClass *)data)->push;
3630ae95 PC	623	ssc->can_push = ((StreamSlaveClass *)data)->can_push;
999e12bb AL	624	}
999e12bb AL	625
8c43a6f0	626	static const TypeInfo axidma_info = {
cbde584f	627	.name = TYPE_XILINX_AXI_DMA,
39bffca2	628	.parent = TYPE_SYS_BUS_DEVICE,
42e8a283	629	.instance_size = sizeof(XilinxAXIDMA),
39bffca2	630	.class_init = axidma_class_init,
e6543663	631	.instance_init = xilinx_axidma_init,
e1500e35 PC	632	};
	633
	634	static const TypeInfo xilinx_axidma_data_stream_info = {
	635	.name = TYPE_XILINX_AXI_DMA_DATA_STREAM,
	636	.parent = TYPE_OBJECT,
	637	.instance_size = sizeof(struct XilinxAXIDMAStreamSlave),
	638	.class_init = xilinx_axidma_stream_class_init,
3630ae95	639	.class_data = &xilinx_axidma_data_stream_class,
669b4983 PC	640	.interfaces = (InterfaceInfo[]) {
	641	{ TYPE_STREAM_SLAVE },
	642	{ }
	643	}
93f1e401 EI	644	};
93f1e401 EI	645
42bb9c91 PC	646	static const TypeInfo xilinx_axidma_control_stream_info = {
	647	.name = TYPE_XILINX_AXI_DMA_CONTROL_STREAM,
	648	.parent = TYPE_OBJECT,
	649	.instance_size = sizeof(struct XilinxAXIDMAStreamSlave),
	650	.class_init = xilinx_axidma_stream_class_init,
	651	.class_data = &xilinx_axidma_control_stream_class,
	652	.interfaces = (InterfaceInfo[]) {
	653	{ TYPE_STREAM_SLAVE },
	654	{ }
	655	}
	656	};
	657
83f7d43a	658	static void xilinx_axidma_register_types(void)
93f1e401	659	{
39bffca2	660	type_register_static(&axidma_info);
e1500e35	661	type_register_static(&xilinx_axidma_data_stream_info);
42bb9c91	662	type_register_static(&xilinx_axidma_control_stream_info);
93f1e401 EI	663	}
93f1e401 EI	664
83f7d43a	665	type_init(xilinx_axidma_register_types)