[qemu.git] / hw / dma / xilinx_axidma.c

/*
 * QEMU model of Xilinx AXI-DMA block.
 *
 * Copyright (c) 2011 Edgar E. Iglesias.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

#include "hw/sysbus.h"
#include "qemu/timer.h"
#include "hw/ptimer.h"
#include "qemu/log.h"
#include "hw/qdev-addr.h"
#include "qapi/qmp/qerror.h"

#include "hw/stream.h"

#define D(x)

#define TYPE_XILINX_AXI_DMA "xlnx.axi-dma"

#define XILINX_AXI_DMA(obj) \
     OBJECT_CHECK(XilinxAXIDMA, (obj), TYPE_XILINX_AXI_DMA)

#define R_DMACR             (0x00 / 4)
#define R_DMASR             (0x04 / 4)
#define R_CURDESC           (0x08 / 4)
#define R_TAILDESC          (0x10 / 4)
#define R_MAX               (0x30 / 4)

typedef struct XilinxAXIDMA XilinxAXIDMA;

enum {
    DMACR_RUNSTOP = 1,
    DMACR_TAILPTR_MODE = 2,
    DMACR_RESET = 4
};

enum {
    DMASR_HALTED = 1,
    DMASR_IDLE  = 2,
    DMASR_IOC_IRQ  = 1 << 12,
    DMASR_DLY_IRQ  = 1 << 13,

    DMASR_IRQ_MASK = 7 << 12
};

struct SDesc {
    uint64_t nxtdesc;
    uint64_t buffer_address;
    uint64_t reserved;
    uint32_t control;
    uint32_t status;
    uint32_t app[6];
};

enum {
    SDESC_CTRL_EOF = (1 << 26),
    SDESC_CTRL_SOF = (1 << 27),

    SDESC_CTRL_LEN_MASK = (1 << 23) - 1
};

enum {
    SDESC_STATUS_EOF = (1 << 26),
    SDESC_STATUS_SOF_BIT = 27,
    SDESC_STATUS_SOF = (1 << SDESC_STATUS_SOF_BIT),
    SDESC_STATUS_COMPLETE = (1 << 31)
};

struct Stream {
    QEMUBH *bh;
    ptimer_state *ptimer;
    qemu_irq irq;

    int nr;

    struct SDesc desc;
    int pos;
    unsigned int complete_cnt;
    uint32_t regs[R_MAX];
};

struct XilinxAXIDMA {
    SysBusDevice busdev;
    MemoryRegion iomem;
    uint32_t freqhz;
    StreamSlave *tx_dev;

    struct Stream streams[2];
};

/*
 * Helper calls to extract info from desriptors and other trivial
 * state from regs.
 */
static inline int stream_desc_sof(struct SDesc *d)
{
    return d->control & SDESC_CTRL_SOF;
}

static inline int stream_desc_eof(struct SDesc *d)
{
    return d->control & SDESC_CTRL_EOF;
}

static inline int stream_resetting(struct Stream *s)
{
    return !!(s->regs[R_DMACR] & DMACR_RESET);
}

static inline int stream_running(struct Stream *s)
{
    return s->regs[R_DMACR] & DMACR_RUNSTOP;
}

static inline int stream_halted(struct Stream *s)
{
    return s->regs[R_DMASR] & DMASR_HALTED;
}

static inline int stream_idle(struct Stream *s)
{
    return !!(s->regs[R_DMASR] & DMASR_IDLE);
}

static void stream_reset(struct Stream *s)
{
    s->regs[R_DMASR] = DMASR_HALTED;  /* starts up halted.  */
    s->regs[R_DMACR] = 1 << 16; /* Starts with one in compl threshold.  */
}

/* Map an offset addr into a channel index.  */
static inline int streamid_from_addr(hwaddr addr)
{
    int sid;

    sid = addr / (0x30);
    sid &= 1;
    return sid;
}

#ifdef DEBUG_ENET
static void stream_desc_show(struct SDesc *d)
{
    qemu_log("buffer_addr  = " PRIx64 "\n", d->buffer_address);
    qemu_log("nxtdesc      = " PRIx64 "\n", d->nxtdesc);
    qemu_log("control      = %x\n", d->control);
    qemu_log("status       = %x\n", d->status);
}
#endif

static void stream_desc_load(struct Stream *s, hwaddr addr)
{
    struct SDesc *d = &s->desc;
    int i;

    cpu_physical_memory_read(addr, (void *) d, sizeof *d);

    /* Convert from LE into host endianness.  */
    d->buffer_address = le64_to_cpu(d->buffer_address);
    d->nxtdesc = le64_to_cpu(d->nxtdesc);
    d->control = le32_to_cpu(d->control);
    d->status = le32_to_cpu(d->status);
    for (i = 0; i < ARRAY_SIZE(d->app); i++) {
        d->app[i] = le32_to_cpu(d->app[i]);
    }
}

static void stream_desc_store(struct Stream *s, hwaddr addr)
{
    struct SDesc *d = &s->desc;
    int i;

    /* Convert from host endianness into LE.  */
    d->buffer_address = cpu_to_le64(d->buffer_address);
    d->nxtdesc = cpu_to_le64(d->nxtdesc);
    d->control = cpu_to_le32(d->control);
    d->status = cpu_to_le32(d->status);
    for (i = 0; i < ARRAY_SIZE(d->app); i++) {
        d->app[i] = cpu_to_le32(d->app[i]);
    }
    cpu_physical_memory_write(addr, (void *) d, sizeof *d);
}

static void stream_update_irq(struct Stream *s)
{
    unsigned int pending, mask, irq;

    pending = s->regs[R_DMASR] & DMASR_IRQ_MASK;
    mask = s->regs[R_DMACR] & DMASR_IRQ_MASK;

    irq = pending & mask;

    qemu_set_irq(s->irq, !!irq);
}

static void stream_reload_complete_cnt(struct Stream *s)
{
    unsigned int comp_th;
    comp_th = (s->regs[R_DMACR] >> 16) & 0xff;
    s->complete_cnt = comp_th;
}

static void timer_hit(void *opaque)
{
    struct Stream *s = opaque;

    stream_reload_complete_cnt(s);
    s->regs[R_DMASR] |= DMASR_DLY_IRQ;
    stream_update_irq(s);
}

static void stream_complete(struct Stream *s)
{
    unsigned int comp_delay;

    /* Start the delayed timer.  */
    comp_delay = s->regs[R_DMACR] >> 24;
    if (comp_delay) {
        ptimer_stop(s->ptimer);
        ptimer_set_count(s->ptimer, comp_delay);
        ptimer_run(s->ptimer, 1);
    }

    s->complete_cnt--;
    if (s->complete_cnt == 0) {
        /* Raise the IOC irq.  */
        s->regs[R_DMASR] |= DMASR_IOC_IRQ;
        stream_reload_complete_cnt(s);
    }
}

static void stream_process_mem2s(struct Stream *s,
                                 StreamSlave *tx_dev)
{
    uint32_t prev_d;
    unsigned char txbuf[16 * 1024];
    unsigned int txlen;
    uint32_t app[6];

    if (!stream_running(s) || stream_idle(s)) {
        return;
    }

    while (1) {
        stream_desc_load(s, s->regs[R_CURDESC]);

        if (s->desc.status & SDESC_STATUS_COMPLETE) {
            s->regs[R_DMASR] |= DMASR_IDLE;
            break;
        }

        if (stream_desc_sof(&s->desc)) {
            s->pos = 0;
            memcpy(app, s->desc.app, sizeof app);
        }

        txlen = s->desc.control & SDESC_CTRL_LEN_MASK;
        if ((txlen + s->pos) > sizeof txbuf) {
            hw_error("%s: too small internal txbuf! %d\n", __func__,
                     txlen + s->pos);
        }

        cpu_physical_memory_read(s->desc.buffer_address,
                                 txbuf + s->pos, txlen);
        s->pos += txlen;

        if (stream_desc_eof(&s->desc)) {
            stream_push(tx_dev, txbuf, s->pos, app);
            s->pos = 0;
            stream_complete(s);
        }

        /* Update the descriptor.  */
        s->desc.status = txlen | SDESC_STATUS_COMPLETE;
        stream_desc_store(s, s->regs[R_CURDESC]);

        /* Advance.  */
        prev_d = s->regs[R_CURDESC];
        s->regs[R_CURDESC] = s->desc.nxtdesc;
        if (prev_d == s->regs[R_TAILDESC]) {
            s->regs[R_DMASR] |= DMASR_IDLE;
            break;
        }
    }
}

static void stream_process_s2mem(struct Stream *s,
                                 unsigned char *buf, size_t len, uint32_t *app)
{
    uint32_t prev_d;
    unsigned int rxlen;
    int pos = 0;
    int sof = 1;

    if (!stream_running(s) || stream_idle(s)) {
        return;
    }

    while (len) {
        stream_desc_load(s, s->regs[R_CURDESC]);

        if (s->desc.status & SDESC_STATUS_COMPLETE) {
            s->regs[R_DMASR] |= DMASR_IDLE;
            break;
        }

        rxlen = s->desc.control & SDESC_CTRL_LEN_MASK;
        if (rxlen > len) {
            /* It fits.  */
            rxlen = len;
        }

        cpu_physical_memory_write(s->desc.buffer_address, buf + pos, rxlen);
        len -= rxlen;
        pos += rxlen;

        /* Update the descriptor.  */
        if (!len) {
            int i;

            stream_complete(s);
            for (i = 0; i < 5; i++) {
                s->desc.app[i] = app[i];
            }
            s->desc.status |= SDESC_STATUS_EOF;
        }

        s->desc.status |= sof << SDESC_STATUS_SOF_BIT;
        s->desc.status |= SDESC_STATUS_COMPLETE;
        stream_desc_store(s, s->regs[R_CURDESC]);
        sof = 0;

        /* Advance.  */
        prev_d = s->regs[R_CURDESC];
        s->regs[R_CURDESC] = s->desc.nxtdesc;
        if (prev_d == s->regs[R_TAILDESC]) {
            s->regs[R_DMASR] |= DMASR_IDLE;
            break;
        }
    }
}

static void xilinx_axidma_reset(DeviceState *dev)
{
    int i;
    XilinxAXIDMA *s = XILINX_AXI_DMA(dev);

    for (i = 0; i < 2; i++) {
        stream_reset(&s->streams[i]);
    }
}

static void
axidma_push(StreamSlave *obj, unsigned char *buf, size_t len, uint32_t *app)
{
    XilinxAXIDMA *d = XILINX_AXI_DMA(obj);
    struct Stream *s = &d->streams[1];

    if (!app) {
        hw_error("No stream app data!\n");
    }
    stream_process_s2mem(s, buf, len, app);
    stream_update_irq(s);
}

static uint64_t axidma_read(void *opaque, hwaddr addr,
                            unsigned size)
{
    XilinxAXIDMA *d = opaque;
    struct Stream *s;
    uint32_t r = 0;
    int sid;

    sid = streamid_from_addr(addr);
    s = &d->streams[sid];

    addr = addr % 0x30;
    addr >>= 2;
    switch (addr) {
        case R_DMACR:
            /* Simulate one cycles reset delay.  */
            s->regs[addr] &= ~DMACR_RESET;
            r = s->regs[addr];
            break;
        case R_DMASR:
            s->regs[addr] &= 0xffff;
            s->regs[addr] |= (s->complete_cnt & 0xff) << 16;
            s->regs[addr] |= (ptimer_get_count(s->ptimer) & 0xff) << 24;
            r = s->regs[addr];
            break;
        default:
            r = s->regs[addr];
            D(qemu_log("%s ch=%d addr=" TARGET_FMT_plx " v=%x\n",
                           __func__, sid, addr * 4, r));
            break;
    }
    return r;

}

static void axidma_write(void *opaque, hwaddr addr,
                         uint64_t value, unsigned size)
{
    XilinxAXIDMA *d = opaque;
    struct Stream *s;
    int sid;

    sid = streamid_from_addr(addr);
    s = &d->streams[sid];

    addr = addr % 0x30;
    addr >>= 2;
    switch (addr) {
        case R_DMACR:
            /* Tailptr mode is always on.  */
            value |= DMACR_TAILPTR_MODE;
            /* Remember our previous reset state.  */
            value |= (s->regs[addr] & DMACR_RESET);
            s->regs[addr] = value;

            if (value & DMACR_RESET) {
                stream_reset(s);
            }

            if ((value & 1) && !stream_resetting(s)) {
                /* Start processing.  */
                s->regs[R_DMASR] &= ~(DMASR_HALTED | DMASR_IDLE);
            }
            stream_reload_complete_cnt(s);
            break;

        case R_DMASR:
            /* Mask away write to clear irq lines.  */
            value &= ~(value & DMASR_IRQ_MASK);
            s->regs[addr] = value;
            break;

        case R_TAILDESC:
            s->regs[addr] = value;
            s->regs[R_DMASR] &= ~DMASR_IDLE; /* Not idle.  */
            if (!sid) {
                stream_process_mem2s(s, d->tx_dev);
            }
            break;
        default:
            D(qemu_log("%s: ch=%d addr=" TARGET_FMT_plx " v=%x\n",
                  __func__, sid, addr * 4, (unsigned)value));
            s->regs[addr] = value;
            break;
    }
    stream_update_irq(s);
}

static const MemoryRegionOps axidma_ops = {
    .read = axidma_read,
    .write = axidma_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

static void xilinx_axidma_realize(DeviceState *dev, Error **errp)
{
    XilinxAXIDMA *s = XILINX_AXI_DMA(dev);
    int i;

    for (i = 0; i < 2; i++) {
        s->streams[i].nr = i;
        s->streams[i].bh = qemu_bh_new(timer_hit, &s->streams[i]);
        s->streams[i].ptimer = ptimer_init(s->streams[i].bh);
        ptimer_set_freq(s->streams[i].ptimer, s->freqhz);
    }
}

static void xilinx_axidma_init(Object *obj)
{
    XilinxAXIDMA *s = XILINX_AXI_DMA(obj);
    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);

    object_property_add_link(obj, "axistream-connected", TYPE_STREAM_SLAVE,
                             (Object **) &s->tx_dev, NULL);

    sysbus_init_irq(sbd, &s->streams[0].irq);
    sysbus_init_irq(sbd, &s->streams[1].irq);

    memory_region_init_io(&s->iomem, &axidma_ops, s,
                          "xlnx.axi-dma", R_MAX * 4 * 2);
    sysbus_init_mmio(sbd, &s->iomem);
}

static Property axidma_properties[] = {
    DEFINE_PROP_UINT32("freqhz", XilinxAXIDMA, freqhz, 50000000),
    DEFINE_PROP_END_OF_LIST(),
};

static void axidma_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    StreamSlaveClass *ssc = STREAM_SLAVE_CLASS(klass);

    dc->realize = xilinx_axidma_realize,
    dc->reset = xilinx_axidma_reset;
    dc->props = axidma_properties;
    ssc->push = axidma_push;
}

static const TypeInfo axidma_info = {
    .name          = TYPE_XILINX_AXI_DMA,
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(XilinxAXIDMA),
    .class_init    = axidma_class_init,
    .instance_init = xilinx_axidma_init,
    .interfaces = (InterfaceInfo[]) {
        { TYPE_STREAM_SLAVE },
        { }
    }
};

static void xilinx_axidma_register_types(void)
{
    type_register_static(&axidma_info);
}

type_init(xilinx_axidma_register_types)
Commit	Line	Data
93f1e401 EI	1	/*
	2	* QEMU model of Xilinx AXI-DMA block.
	3	*
	4	* Copyright (c) 2011 Edgar E. Iglesias.
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
	24
83c9f4ca	25	#include "hw/sysbus.h"
1de7afc9	26	#include "qemu/timer.h"
83c9f4ca	27	#include "hw/ptimer.h"
1de7afc9	28	#include "qemu/log.h"
83c9f4ca	29	#include "hw/qdev-addr.h"
e6543663	30	#include "qapi/qmp/qerror.h"
93f1e401	31
83c9f4ca	32	#include "hw/stream.h"
93f1e401 EI	33
	34	#define D(x)
	35
cbde584f PC	36	#define TYPE_XILINX_AXI_DMA "xlnx.axi-dma"
	37
	38	#define XILINX_AXI_DMA(obj) \
	39	OBJECT_CHECK(XilinxAXIDMA, (obj), TYPE_XILINX_AXI_DMA)
	40
93f1e401 EI	41	#define R_DMACR (0x00 / 4)
	42	#define R_DMASR (0x04 / 4)
	43	#define R_CURDESC (0x08 / 4)
	44	#define R_TAILDESC (0x10 / 4)
	45	#define R_MAX (0x30 / 4)
	46
42e8a283 PC	47	typedef struct XilinxAXIDMA XilinxAXIDMA;
42e8a283 PC	48
93f1e401 EI	49	enum {
	50	DMACR_RUNSTOP = 1,
	51	DMACR_TAILPTR_MODE = 2,
	52	DMACR_RESET = 4
	53	};
	54
	55	enum {
	56	DMASR_HALTED = 1,
	57	DMASR_IDLE = 2,
	58	DMASR_IOC_IRQ = 1 << 12,
	59	DMASR_DLY_IRQ = 1 << 13,
	60
	61	DMASR_IRQ_MASK = 7 << 12
	62	};
	63
	64	struct SDesc {
	65	uint64_t nxtdesc;
	66	uint64_t buffer_address;
	67	uint64_t reserved;
	68	uint32_t control;
	69	uint32_t status;
	70	uint32_t app[6];
	71	};
	72
	73	enum {
	74	SDESC_CTRL_EOF = (1 << 26),
	75	SDESC_CTRL_SOF = (1 << 27),
	76
	77	SDESC_CTRL_LEN_MASK = (1 << 23) - 1
	78	};
	79
	80	enum {
	81	SDESC_STATUS_EOF = (1 << 26),
	82	SDESC_STATUS_SOF_BIT = 27,
	83	SDESC_STATUS_SOF = (1 << SDESC_STATUS_SOF_BIT),
	84	SDESC_STATUS_COMPLETE = (1 << 31)
	85	};
	86
669b4983	87	struct Stream {
93f1e401 EI	88	QEMUBH *bh;
	89	ptimer_state *ptimer;
	90	qemu_irq irq;
	91
	92	int nr;
	93
	94	struct SDesc desc;
	95	int pos;
	96	unsigned int complete_cnt;
	97	uint32_t regs[R_MAX];
	98	};
	99
	100	struct XilinxAXIDMA {
	101	SysBusDevice busdev;
f810bc4a	102	MemoryRegion iomem;
93f1e401	103	uint32_t freqhz;
669b4983	104	StreamSlave *tx_dev;
93f1e401	105
669b4983	106	struct Stream streams[2];
93f1e401 EI	107	};
	108
	109	/*
	110	* Helper calls to extract info from desriptors and other trivial
	111	* state from regs.
	112	*/
	113	static inline int stream_desc_sof(struct SDesc *d)
	114	{
	115	return d->control & SDESC_CTRL_SOF;
	116	}
	117
	118	static inline int stream_desc_eof(struct SDesc *d)
	119	{
	120	return d->control & SDESC_CTRL_EOF;
	121	}
	122
669b4983	123	static inline int stream_resetting(struct Stream *s)
93f1e401 EI	124	{
	125	return !!(s->regs[R_DMACR] & DMACR_RESET);
	126	}
	127
669b4983	128	static inline int stream_running(struct Stream *s)
93f1e401 EI	129	{
	130	return s->regs[R_DMACR] & DMACR_RUNSTOP;
	131	}
	132
669b4983	133	static inline int stream_halted(struct Stream *s)
93f1e401 EI	134	{
	135	return s->regs[R_DMASR] & DMASR_HALTED;
	136	}
	137
669b4983	138	static inline int stream_idle(struct Stream *s)
93f1e401 EI	139	{
	140	return !!(s->regs[R_DMASR] & DMASR_IDLE);
	141	}
	142
669b4983	143	static void stream_reset(struct Stream *s)
93f1e401 EI	144	{
93f1e401 EI	145	s->regs[R_DMASR] = DMASR_HALTED; /* starts up halted. */
0d50d616	146	s->regs[R_DMACR] = 1 << 16; /* Starts with one in compl threshold. */
93f1e401 EI	147	}
93f1e401 EI	148
0d50d616	149	/* Map an offset addr into a channel index. */
a8170e5e	150	static inline int streamid_from_addr(hwaddr addr)
93f1e401 EI	151	{
	152	int sid;
	153
	154	sid = addr / (0x30);
	155	sid &= 1;
	156	return sid;
	157	}
	158
	159	#ifdef DEBUG_ENET
	160	static void stream_desc_show(struct SDesc *d)
	161	{
	162	qemu_log("buffer_addr = " PRIx64 "\n", d->buffer_address);
	163	qemu_log("nxtdesc = " PRIx64 "\n", d->nxtdesc);
	164	qemu_log("control = %x\n", d->control);
	165	qemu_log("status = %x\n", d->status);
	166	}
	167	#endif
	168
a8170e5e	169	static void stream_desc_load(struct Stream *s, hwaddr addr)
93f1e401 EI	170	{
	171	struct SDesc *d = &s->desc;
	172	int i;
	173
	174	cpu_physical_memory_read(addr, (void ) d, sizeof d);
	175
	176	/* Convert from LE into host endianness. */
	177	d->buffer_address = le64_to_cpu(d->buffer_address);
	178	d->nxtdesc = le64_to_cpu(d->nxtdesc);
	179	d->control = le32_to_cpu(d->control);
	180	d->status = le32_to_cpu(d->status);
	181	for (i = 0; i < ARRAY_SIZE(d->app); i++) {
	182	d->app[i] = le32_to_cpu(d->app[i]);
	183	}
	184	}
	185
a8170e5e	186	static void stream_desc_store(struct Stream *s, hwaddr addr)
93f1e401 EI	187	{
	188	struct SDesc *d = &s->desc;
	189	int i;
	190
	191	/* Convert from host endianness into LE. */
	192	d->buffer_address = cpu_to_le64(d->buffer_address);
	193	d->nxtdesc = cpu_to_le64(d->nxtdesc);
	194	d->control = cpu_to_le32(d->control);
	195	d->status = cpu_to_le32(d->status);
	196	for (i = 0; i < ARRAY_SIZE(d->app); i++) {
	197	d->app[i] = cpu_to_le32(d->app[i]);
	198	}
	199	cpu_physical_memory_write(addr, (void ) d, sizeof d);
	200	}
	201
669b4983	202	static void stream_update_irq(struct Stream *s)
93f1e401 EI	203	{
	204	unsigned int pending, mask, irq;
	205
	206	pending = s->regs[R_DMASR] & DMASR_IRQ_MASK;
	207	mask = s->regs[R_DMACR] & DMASR_IRQ_MASK;
	208
	209	irq = pending & mask;
	210
	211	qemu_set_irq(s->irq, !!irq);
	212	}
	213
669b4983	214	static void stream_reload_complete_cnt(struct Stream *s)
93f1e401 EI	215	{
	216	unsigned int comp_th;
	217	comp_th = (s->regs[R_DMACR] >> 16) & 0xff;
	218	s->complete_cnt = comp_th;
	219	}
	220
	221	static void timer_hit(void *opaque)
	222	{
669b4983	223	struct Stream *s = opaque;
93f1e401 EI	224
	225	stream_reload_complete_cnt(s);
	226	s->regs[R_DMASR] \|= DMASR_DLY_IRQ;
	227	stream_update_irq(s);
	228	}
	229
669b4983	230	static void stream_complete(struct Stream *s)
93f1e401 EI	231	{
	232	unsigned int comp_delay;
	233
	234	/* Start the delayed timer. */
	235	comp_delay = s->regs[R_DMACR] >> 24;
	236	if (comp_delay) {
	237	ptimer_stop(s->ptimer);
	238	ptimer_set_count(s->ptimer, comp_delay);
	239	ptimer_run(s->ptimer, 1);
	240	}
	241
	242	s->complete_cnt--;
	243	if (s->complete_cnt == 0) {
	244	/* Raise the IOC irq. */
	245	s->regs[R_DMASR] \|= DMASR_IOC_IRQ;
	246	stream_reload_complete_cnt(s);
	247	}
	248	}
	249
669b4983 PC	250	static void stream_process_mem2s(struct Stream *s,
669b4983 PC	251	StreamSlave *tx_dev)
93f1e401 EI	252	{
	253	uint32_t prev_d;
	254	unsigned char txbuf[16 * 1024];
	255	unsigned int txlen;
	256	uint32_t app[6];
	257
	258	if (!stream_running(s) \|\| stream_idle(s)) {
	259	return;
	260	}
	261
	262	while (1) {
	263	stream_desc_load(s, s->regs[R_CURDESC]);
	264
	265	if (s->desc.status & SDESC_STATUS_COMPLETE) {
	266	s->regs[R_DMASR] \|= DMASR_IDLE;
	267	break;
	268	}
	269
	270	if (stream_desc_sof(&s->desc)) {
	271	s->pos = 0;
	272	memcpy(app, s->desc.app, sizeof app);
	273	}
	274
	275	txlen = s->desc.control & SDESC_CTRL_LEN_MASK;
	276	if ((txlen + s->pos) > sizeof txbuf) {
	277	hw_error("%s: too small internal txbuf! %d\n", __func__,
	278	txlen + s->pos);
	279	}
	280
	281	cpu_physical_memory_read(s->desc.buffer_address,
	282	txbuf + s->pos, txlen);
	283	s->pos += txlen;
	284
	285	if (stream_desc_eof(&s->desc)) {
669b4983	286	stream_push(tx_dev, txbuf, s->pos, app);
93f1e401 EI	287	s->pos = 0;
	288	stream_complete(s);
	289	}
	290
	291	/* Update the descriptor. */
	292	s->desc.status = txlen \| SDESC_STATUS_COMPLETE;
	293	stream_desc_store(s, s->regs[R_CURDESC]);
	294
	295	/* Advance. */
	296	prev_d = s->regs[R_CURDESC];
	297	s->regs[R_CURDESC] = s->desc.nxtdesc;
	298	if (prev_d == s->regs[R_TAILDESC]) {
	299	s->regs[R_DMASR] \|= DMASR_IDLE;
	300	break;
	301	}
	302	}
	303	}
	304
669b4983	305	static void stream_process_s2mem(struct Stream *s,
93f1e401 EI	306	unsigned char buf, size_t len, uint32_t app)
	307	{
	308	uint32_t prev_d;
	309	unsigned int rxlen;
	310	int pos = 0;
	311	int sof = 1;
	312
	313	if (!stream_running(s) \|\| stream_idle(s)) {
	314	return;
	315	}
	316
	317	while (len) {
	318	stream_desc_load(s, s->regs[R_CURDESC]);
	319
	320	if (s->desc.status & SDESC_STATUS_COMPLETE) {
	321	s->regs[R_DMASR] \|= DMASR_IDLE;
	322	break;
	323	}
	324
	325	rxlen = s->desc.control & SDESC_CTRL_LEN_MASK;
	326	if (rxlen > len) {
	327	/* It fits. */
	328	rxlen = len;
	329	}
	330
	331	cpu_physical_memory_write(s->desc.buffer_address, buf + pos, rxlen);
	332	len -= rxlen;
	333	pos += rxlen;
	334
	335	/* Update the descriptor. */
	336	if (!len) {
	337	int i;
	338
	339	stream_complete(s);
	340	for (i = 0; i < 5; i++) {
	341	s->desc.app[i] = app[i];
	342	}
	343	s->desc.status \|= SDESC_STATUS_EOF;
	344	}
	345
	346	s->desc.status \|= sof << SDESC_STATUS_SOF_BIT;
	347	s->desc.status \|= SDESC_STATUS_COMPLETE;
	348	stream_desc_store(s, s->regs[R_CURDESC]);
	349	sof = 0;
	350
	351	/* Advance. */
	352	prev_d = s->regs[R_CURDESC];
	353	s->regs[R_CURDESC] = s->desc.nxtdesc;
	354	if (prev_d == s->regs[R_TAILDESC]) {
	355	s->regs[R_DMASR] \|= DMASR_IDLE;
	356	break;
	357	}
	358	}
	359	}
	360
897374db PC	361	static void xilinx_axidma_reset(DeviceState *dev)
	362	{
	363	int i;
	364	XilinxAXIDMA *s = XILINX_AXI_DMA(dev);
	365
	366	for (i = 0; i < 2; i++) {
	367	stream_reset(&s->streams[i]);
	368	}
	369	}
	370
669b4983 PC	371	static void
669b4983 PC	372	axidma_push(StreamSlave obj, unsigned char buf, size_t len, uint32_t *app)
93f1e401	373	{
cbde584f	374	XilinxAXIDMA *d = XILINX_AXI_DMA(obj);
669b4983	375	struct Stream *s = &d->streams[1];
93f1e401 EI	376
	377	if (!app) {
	378	hw_error("No stream app data!\n");
	379	}
	380	stream_process_s2mem(s, buf, len, app);
	381	stream_update_irq(s);
	382	}
	383
a8170e5e	384	static uint64_t axidma_read(void *opaque, hwaddr addr,
f810bc4a	385	unsigned size)
93f1e401	386	{
42e8a283	387	XilinxAXIDMA *d = opaque;
669b4983	388	struct Stream *s;
93f1e401 EI	389	uint32_t r = 0;
	390	int sid;
	391
	392	sid = streamid_from_addr(addr);
	393	s = &d->streams[sid];
	394
	395	addr = addr % 0x30;
	396	addr >>= 2;
	397	switch (addr) {
	398	case R_DMACR:
	399	/* Simulate one cycles reset delay. */
	400	s->regs[addr] &= ~DMACR_RESET;
	401	r = s->regs[addr];
	402	break;
	403	case R_DMASR:
	404	s->regs[addr] &= 0xffff;
	405	s->regs[addr] \|= (s->complete_cnt & 0xff) << 16;
	406	s->regs[addr] \|= (ptimer_get_count(s->ptimer) & 0xff) << 24;
	407	r = s->regs[addr];
	408	break;
	409	default:
	410	r = s->regs[addr];
	411	D(qemu_log("%s ch=%d addr=" TARGET_FMT_plx " v=%x\n",
	412	__func__, sid, addr * 4, r));
	413	break;
	414	}
	415	return r;
	416
	417	}
	418
a8170e5e	419	static void axidma_write(void *opaque, hwaddr addr,
f810bc4a	420	uint64_t value, unsigned size)
93f1e401	421	{
42e8a283	422	XilinxAXIDMA *d = opaque;
669b4983	423	struct Stream *s;
93f1e401 EI	424	int sid;
	425
	426	sid = streamid_from_addr(addr);
	427	s = &d->streams[sid];
	428
	429	addr = addr % 0x30;
	430	addr >>= 2;
	431	switch (addr) {
	432	case R_DMACR:
	433	/* Tailptr mode is always on. */
	434	value \|= DMACR_TAILPTR_MODE;
	435	/* Remember our previous reset state. */
	436	value \|= (s->regs[addr] & DMACR_RESET);
	437	s->regs[addr] = value;
	438
	439	if (value & DMACR_RESET) {
	440	stream_reset(s);
	441	}
	442
	443	if ((value & 1) && !stream_resetting(s)) {
	444	/* Start processing. */
	445	s->regs[R_DMASR] &= ~(DMASR_HALTED \| DMASR_IDLE);
	446	}
	447	stream_reload_complete_cnt(s);
	448	break;
	449
	450	case R_DMASR:
	451	/* Mask away write to clear irq lines. */
	452	value &= ~(value & DMASR_IRQ_MASK);
	453	s->regs[addr] = value;
	454	break;
	455
	456	case R_TAILDESC:
	457	s->regs[addr] = value;
	458	s->regs[R_DMASR] &= ~DMASR_IDLE; /* Not idle. */
	459	if (!sid) {
669b4983	460	stream_process_mem2s(s, d->tx_dev);
93f1e401 EI	461	}
	462	break;
	463	default:
	464	D(qemu_log("%s: ch=%d addr=" TARGET_FMT_plx " v=%x\n",
74cef80c	465	__func__, sid, addr * 4, (unsigned)value));
93f1e401 EI	466	s->regs[addr] = value;
	467	break;
	468	}
	469	stream_update_irq(s);
	470	}
	471
f810bc4a AK	472	static const MemoryRegionOps axidma_ops = {
	473	.read = axidma_read,
	474	.write = axidma_write,
	475	.endianness = DEVICE_NATIVE_ENDIAN,
93f1e401 EI	476	};
93f1e401 EI	477
e6543663	478	static void xilinx_axidma_realize(DeviceState dev, Error *errp)
93f1e401	479	{
cbde584f	480	XilinxAXIDMA *s = XILINX_AXI_DMA(dev);
93f1e401 EI	481	int i;
93f1e401 EI	482
93f1e401	483	for (i = 0; i < 2; i++) {
93f1e401 EI	484	s->streams[i].nr = i;
	485	s->streams[i].bh = qemu_bh_new(timer_hit, &s->streams[i]);
	486	s->streams[i].ptimer = ptimer_init(s->streams[i].bh);
	487	ptimer_set_freq(s->streams[i].ptimer, s->freqhz);
	488	}
93f1e401 EI	489	}
93f1e401 EI	490
e6543663	491	static void xilinx_axidma_init(Object *obj)
669b4983	492	{
cbde584f	493	XilinxAXIDMA *s = XILINX_AXI_DMA(obj);
e6543663	494	SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
669b4983 PC	495
	496	object_property_add_link(obj, "axistream-connected", TYPE_STREAM_SLAVE,
	497	(Object **) &s->tx_dev, NULL);
e6543663 PC	498
	499	sysbus_init_irq(sbd, &s->streams[0].irq);
	500	sysbus_init_irq(sbd, &s->streams[1].irq);
	501
	502	memory_region_init_io(&s->iomem, &axidma_ops, s,
	503	"xlnx.axi-dma", R_MAX * 4 * 2);
	504	sysbus_init_mmio(sbd, &s->iomem);
669b4983 PC	505	}
669b4983 PC	506
999e12bb	507	static Property axidma_properties[] = {
42e8a283	508	DEFINE_PROP_UINT32("freqhz", XilinxAXIDMA, freqhz, 50000000),
999e12bb AL	509	DEFINE_PROP_END_OF_LIST(),
	510	};
	511
	512	static void axidma_class_init(ObjectClass klass, void data)
	513	{
39bffca2	514	DeviceClass *dc = DEVICE_CLASS(klass);
669b4983	515	StreamSlaveClass *ssc = STREAM_SLAVE_CLASS(klass);
999e12bb	516
e6543663	517	dc->realize = xilinx_axidma_realize,
897374db	518	dc->reset = xilinx_axidma_reset;
39bffca2	519	dc->props = axidma_properties;
669b4983	520	ssc->push = axidma_push;
999e12bb AL	521	}
999e12bb AL	522
8c43a6f0	523	static const TypeInfo axidma_info = {
cbde584f	524	.name = TYPE_XILINX_AXI_DMA,
39bffca2	525	.parent = TYPE_SYS_BUS_DEVICE,
42e8a283	526	.instance_size = sizeof(XilinxAXIDMA),
39bffca2	527	.class_init = axidma_class_init,
e6543663	528	.instance_init = xilinx_axidma_init,
669b4983 PC	529	.interfaces = (InterfaceInfo[]) {
	530	{ TYPE_STREAM_SLAVE },
	531	{ }
	532	}
93f1e401 EI	533	};
93f1e401 EI	534
83f7d43a	535	static void xilinx_axidma_register_types(void)
93f1e401	536	{
39bffca2	537	type_register_static(&axidma_info);
93f1e401 EI	538	}
93f1e401 EI	539
83f7d43a	540	type_init(xilinx_axidma_register_types)