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Merge remote-tracking branch 'remotes/riku/tags/pull-linux-user-20150616' into staging
[qemu.git] / hw / display / qxl.c
CommitLineData
a19cbfb3
GH		 1/*
2 * Copyright (C) 2010 Red Hat, Inc.
3 *
4 * written by Yaniv Kamay, Izik Eidus, Gerd Hoffmann
5 * maintained by Gerd Hoffmann <[email protected]>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 or
10 * (at your option) version 3 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, see <http://www.gnu.org/licenses/>.
19 */
20
a639ab04 21#include <zlib.h>
3761abb1 22#include <stdint.h>
a639ab04 23
a19cbfb3 24#include "qemu-common.h"
1de7afc9
PB		 25#include "qemu/timer.h"
26#include "qemu/queue.h"
5444e768 27#include "qemu/atomic.h"
83c9089e 28#include "monitor/monitor.h"
9c17d615 29#include "sysemu/sysemu.h"
c480bb7d 30#include "trace.h"
a19cbfb3 31
47b43a1f 32#include "qxl.h"
a19cbfb3 33
0b81c478
AL		 34/*
35 * NOTE: SPICE_RING_PROD_ITEM accesses memory on the pci bar and as
36 * such can be changed by the guest, so to avoid a guest trigerrable
0a530548 37 * abort we just qxl_set_guest_bug and set the return to NULL. Still
0b81c478
AL		 38 * it may happen as a result of emulator bug as well.
39 */
a19cbfb3 40#undef SPICE_RING_PROD_ITEM
0b81c478 41#define SPICE_RING_PROD_ITEM(qxl, r, ret) { \
a19cbfb3 42 uint32_t prod = (r)->prod & SPICE_RING_INDEX_MASK(r); \
bc5f92e5 43 if (prod >= ARRAY_SIZE((r)->items)) { \
0a530548 44 qxl_set_guest_bug(qxl, "SPICE_RING_PROD_ITEM indices mismatch " \
bc5f92e5 45 "%u >= %zu", prod, ARRAY_SIZE((r)->items)); \
0b81c478
AL		 46 ret = NULL; \
47 } else { \
bc5f92e5 48 ret = &(r)->items[prod].el; \
a19cbfb3 49 } \
a19cbfb3
GH		 50 }
51
52#undef SPICE_RING_CONS_ITEM
0b81c478 53#define SPICE_RING_CONS_ITEM(qxl, r, ret) { \
a19cbfb3 54 uint32_t cons = (r)->cons & SPICE_RING_INDEX_MASK(r); \
bc5f92e5 55 if (cons >= ARRAY_SIZE((r)->items)) { \
0a530548 56 qxl_set_guest_bug(qxl, "SPICE_RING_CONS_ITEM indices mismatch " \
bc5f92e5 57 "%u >= %zu", cons, ARRAY_SIZE((r)->items)); \
0b81c478
AL		 58 ret = NULL; \
59 } else { \
bc5f92e5 60 ret = &(r)->items[cons].el; \
a19cbfb3 61 } \
a19cbfb3
GH		 62 }
63
64#undef ALIGN
65#define ALIGN(a, b) (((a) + ((b) - 1)) & ~((b) - 1))
66
67#define PIXEL_SIZE 0.2936875 //1280x1024 is 14.8" x 11.9"
68
69#define QXL_MODE(_x, _y, _b, _o) \
70 { .x_res = _x, \
71 .y_res = _y, \
72 .bits = _b, \
73 .stride = (_x) * (_b) / 8, \
74 .x_mili = PIXEL_SIZE * (_x), \
75 .y_mili = PIXEL_SIZE * (_y), \
76 .orientation = _o, \
77 }
78
79#define QXL_MODE_16_32(x_res, y_res, orientation) \
80 QXL_MODE(x_res, y_res, 16, orientation), \
81 QXL_MODE(x_res, y_res, 32, orientation)
82
83#define QXL_MODE_EX(x_res, y_res) \
84 QXL_MODE_16_32(x_res, y_res, 0), \
038c1879 85 QXL_MODE_16_32(x_res, y_res, 1)
a19cbfb3
GH		 86
87static QXLMode qxl_modes[] = {
88 QXL_MODE_EX(640, 480),
89 QXL_MODE_EX(800, 480),
90 QXL_MODE_EX(800, 600),
91 QXL_MODE_EX(832, 624),
92 QXL_MODE_EX(960, 640),
93 QXL_MODE_EX(1024, 600),
94 QXL_MODE_EX(1024, 768),
95 QXL_MODE_EX(1152, 864),
96 QXL_MODE_EX(1152, 870),
97 QXL_MODE_EX(1280, 720),
98 QXL_MODE_EX(1280, 760),
99 QXL_MODE_EX(1280, 768),
100 QXL_MODE_EX(1280, 800),
101 QXL_MODE_EX(1280, 960),
102 QXL_MODE_EX(1280, 1024),
103 QXL_MODE_EX(1360, 768),
104 QXL_MODE_EX(1366, 768),
105 QXL_MODE_EX(1400, 1050),
106 QXL_MODE_EX(1440, 900),
107 QXL_MODE_EX(1600, 900),
108 QXL_MODE_EX(1600, 1200),
109 QXL_MODE_EX(1680, 1050),
110 QXL_MODE_EX(1920, 1080),
a19cbfb3
GH		 111 /* these modes need more than 8 MB video memory */
112 QXL_MODE_EX(1920, 1200),
113 QXL_MODE_EX(1920, 1440),
5c74fb27 114 QXL_MODE_EX(2000, 2000),
a19cbfb3 115 QXL_MODE_EX(2048, 1536),
5c74fb27 116 QXL_MODE_EX(2048, 2048),
a19cbfb3
GH		 117 QXL_MODE_EX(2560, 1440),
118 QXL_MODE_EX(2560, 1600),
a19cbfb3
GH		 119 /* these modes need more than 16 MB video memory */
120 QXL_MODE_EX(2560, 2048),
121 QXL_MODE_EX(2800, 2100),
122 QXL_MODE_EX(3200, 2400),
03d9825d 123 /* these modes need more than 32 MB video memory */
d4bcb199
GH		 124 QXL_MODE_EX(3840, 2160), /* 4k mainstream */
125 QXL_MODE_EX(4096, 2160), /* 4k */
03d9825d 126 /* these modes need more than 64 MB video memory */
d4bcb199 127 QXL_MODE_EX(7680, 4320), /* 8k mainstream */
03d9825d 128 /* these modes need more than 128 MB video memory */
d4bcb199 129 QXL_MODE_EX(8192, 4320), /* 8k */
a19cbfb3
GH		 130};
131
a19cbfb3 132static void qxl_send_events(PCIQXLDevice *d, uint32_t events);
5ff4e36c 133static int qxl_destroy_primary(PCIQXLDevice *d, qxl_async_io async);
a19cbfb3
GH		 134static void qxl_reset_memslots(PCIQXLDevice *d);
135static void qxl_reset_surfaces(PCIQXLDevice *d);
136static void qxl_ring_set_dirty(PCIQXLDevice *qxl);
137
15162335
GH		 138static void qxl_hw_update(void *opaque);
139
0a530548 140void qxl_set_guest_bug(PCIQXLDevice *qxl, const char *msg, ...)
2bce0400 141{
917ae08c 142 trace_qxl_set_guest_bug(qxl->id);
2bce0400 143 qxl_send_events(qxl, QXL_INTERRUPT_ERROR);
087e6a42 144 qxl->guest_bug = 1;
2bce0400 145 if (qxl->guestdebug) {
7635392c
AL		 146 va_list ap;
147 va_start(ap, msg);
148 fprintf(stderr, "qxl-%d: guest bug: ", qxl->id);
149 vfprintf(stderr, msg, ap);
150 fprintf(stderr, "\n");
151 va_end(ap);
2bce0400
GH		 152 }
153}
154
087e6a42
AL		 155static void qxl_clear_guest_bug(PCIQXLDevice *qxl)
156{
157 qxl->guest_bug = 0;
158}
aee32bf3
GH		 159
160void qxl_spice_update_area(PCIQXLDevice *qxl, uint32_t surface_id,
161 struct QXLRect *area, struct QXLRect *dirty_rects,
162 uint32_t num_dirty_rects,
5ff4e36c 163 uint32_t clear_dirty_region,
2e1a98c9 164 qxl_async_io async, struct QXLCookie *cookie)
aee32bf3 165{
c480bb7d
AL		 166 trace_qxl_spice_update_area(qxl->id, surface_id, area->left, area->right,
167 area->top, area->bottom);
168 trace_qxl_spice_update_area_rest(qxl->id, num_dirty_rects,
169 clear_dirty_region);
5ff4e36c 170 if (async == QXL_SYNC) {
26defe81 171 spice_qxl_update_area(&qxl->ssd.qxl, surface_id, area,
5ff4e36c
AL		 172 dirty_rects, num_dirty_rects, clear_dirty_region);
173 } else {
2e1a98c9 174 assert(cookie != NULL);
5ff4e36c 175 spice_qxl_update_area_async(&qxl->ssd.qxl, surface_id, area,
5dba0d45 176 clear_dirty_region, (uintptr_t)cookie);
5ff4e36c 177 }
aee32bf3
GH		 178}
179
5ff4e36c
AL		 180static void qxl_spice_destroy_surface_wait_complete(PCIQXLDevice *qxl,
181 uint32_t id)
aee32bf3 182{
c480bb7d 183 trace_qxl_spice_destroy_surface_wait_complete(qxl->id, id);
14898cf6 184 qemu_mutex_lock(&qxl->track_lock);
14898cf6
GH		 185 qxl->guest_surfaces.cmds[id] = 0;
186 qxl->guest_surfaces.count--;
187 qemu_mutex_unlock(&qxl->track_lock);
aee32bf3
GH		 188}
189
5ff4e36c
AL		 190static void qxl_spice_destroy_surface_wait(PCIQXLDevice *qxl, uint32_t id,
191 qxl_async_io async)
192{
2e1a98c9
AL		 193 QXLCookie *cookie;
194
c480bb7d 195 trace_qxl_spice_destroy_surface_wait(qxl->id, id, async);
5ff4e36c 196 if (async) {
2e1a98c9
AL		 197 cookie = qxl_cookie_new(QXL_COOKIE_TYPE_IO,
198 QXL_IO_DESTROY_SURFACE_ASYNC);
199 cookie->u.surface_id = id;
5dba0d45 200 spice_qxl_destroy_surface_async(&qxl->ssd.qxl, id, (uintptr_t)cookie);
5ff4e36c 201 } else {
26defe81 202 spice_qxl_destroy_surface_wait(&qxl->ssd.qxl, id);
753b8b0d 203 qxl_spice_destroy_surface_wait_complete(qxl, id);
5ff4e36c
AL		 204 }
205}
206
3e16b9c5
AL		 207static void qxl_spice_flush_surfaces_async(PCIQXLDevice *qxl)
208{
c480bb7d
AL		 209 trace_qxl_spice_flush_surfaces_async(qxl->id, qxl->guest_surfaces.count,
210 qxl->num_free_res);
2e1a98c9 211 spice_qxl_flush_surfaces_async(&qxl->ssd.qxl,
5dba0d45
PM		 212 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO,
213 QXL_IO_FLUSH_SURFACES_ASYNC));
3e16b9c5 214}
3e16b9c5 215
aee32bf3
GH		 216void qxl_spice_loadvm_commands(PCIQXLDevice *qxl, struct QXLCommandExt *ext,
217 uint32_t count)
218{
c480bb7d 219 trace_qxl_spice_loadvm_commands(qxl->id, ext, count);
26defe81 220 spice_qxl_loadvm_commands(&qxl->ssd.qxl, ext, count);
aee32bf3
GH		 221}
222
223void qxl_spice_oom(PCIQXLDevice *qxl)
224{
c480bb7d 225 trace_qxl_spice_oom(qxl->id);
26defe81 226 spice_qxl_oom(&qxl->ssd.qxl);
aee32bf3
GH		 227}
228
229void qxl_spice_reset_memslots(PCIQXLDevice *qxl)
230{
c480bb7d 231 trace_qxl_spice_reset_memslots(qxl->id);
26defe81 232 spice_qxl_reset_memslots(&qxl->ssd.qxl);
aee32bf3
GH		 233}
234
5ff4e36c 235static void qxl_spice_destroy_surfaces_complete(PCIQXLDevice *qxl)
aee32bf3 236{
c480bb7d 237 trace_qxl_spice_destroy_surfaces_complete(qxl->id);
14898cf6 238 qemu_mutex_lock(&qxl->track_lock);
ddd8fdc7 239 memset(qxl->guest_surfaces.cmds, 0,
8bb9f51c 240 sizeof(qxl->guest_surfaces.cmds[0]) * qxl->ssd.num_surfaces);
14898cf6
GH		 241 qxl->guest_surfaces.count = 0;
242 qemu_mutex_unlock(&qxl->track_lock);
aee32bf3
GH		 243}
244
5ff4e36c
AL		 245static void qxl_spice_destroy_surfaces(PCIQXLDevice *qxl, qxl_async_io async)
246{
c480bb7d 247 trace_qxl_spice_destroy_surfaces(qxl->id, async);
5ff4e36c 248 if (async) {
2e1a98c9 249 spice_qxl_destroy_surfaces_async(&qxl->ssd.qxl,
5dba0d45
PM		 250 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO,
251 QXL_IO_DESTROY_ALL_SURFACES_ASYNC));
5ff4e36c 252 } else {
26defe81 253 spice_qxl_destroy_surfaces(&qxl->ssd.qxl);
5ff4e36c
AL		 254 qxl_spice_destroy_surfaces_complete(qxl);
255 }
256}
257
020af1c4
AL		 258static void qxl_spice_monitors_config_async(PCIQXLDevice *qxl, int replay)
259{
260 trace_qxl_spice_monitors_config(qxl->id);
020af1c4
AL		 261 if (replay) {
262 /*
263 * don't use QXL_COOKIE_TYPE_IO:
264 * - we are not running yet (post_load), we will assert
265 * in send_events
266 * - this is not a guest io, but a reply, so async_io isn't set.
267 */
268 spice_qxl_monitors_config_async(&qxl->ssd.qxl,
269 qxl->guest_monitors_config,
270 MEMSLOT_GROUP_GUEST,
271 (uintptr_t)qxl_cookie_new(
272 QXL_COOKIE_TYPE_POST_LOAD_MONITORS_CONFIG,
273 0));
274 } else {
275 qxl->guest_monitors_config = qxl->ram->monitors_config;
276 spice_qxl_monitors_config_async(&qxl->ssd.qxl,
277 qxl->ram->monitors_config,
278 MEMSLOT_GROUP_GUEST,
279 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO,
280 QXL_IO_MONITORS_CONFIG_ASYNC));
281 }
020af1c4
AL		 282}
283
aee32bf3
GH		 284void qxl_spice_reset_image_cache(PCIQXLDevice *qxl)
285{
c480bb7d 286 trace_qxl_spice_reset_image_cache(qxl->id);
26defe81 287 spice_qxl_reset_image_cache(&qxl->ssd.qxl);
aee32bf3
GH		 288}
289
290void qxl_spice_reset_cursor(PCIQXLDevice *qxl)
291{
c480bb7d 292 trace_qxl_spice_reset_cursor(qxl->id);
26defe81 293 spice_qxl_reset_cursor(&qxl->ssd.qxl);
30f6da66
YH		 294 qemu_mutex_lock(&qxl->track_lock);
295 qxl->guest_cursor = 0;
296 qemu_mutex_unlock(&qxl->track_lock);
958c2bce
GH		 297 if (qxl->ssd.cursor) {
298 cursor_put(qxl->ssd.cursor);
299 }
300 qxl->ssd.cursor = cursor_builtin_hidden();
aee32bf3
GH		 301}
302
a19cbfb3
GH		 303static ram_addr_t qxl_rom_size(void)
304{
038c1879
AL		 305 uint32_t required_rom_size = sizeof(QXLRom) + sizeof(QXLModes) +
306 sizeof(qxl_modes);
307 uint32_t rom_size = 8192; /* two pages */
13d1fd44 308
60b3b2a5 309 QEMU_BUILD_BUG_ON(required_rom_size > rom_size);
a19cbfb3
GH		 310 return rom_size;
311}
312
313static void init_qxl_rom(PCIQXLDevice *d)
314{
b1950430 315 QXLRom *rom = memory_region_get_ram_ptr(&d->rom_bar);
a19cbfb3
GH		 316 QXLModes *modes = (QXLModes *)(rom + 1);
317 uint32_t ram_header_size;
318 uint32_t surface0_area_size;
319 uint32_t num_pages;
13d1fd44
AL		 320 uint32_t fb;
321 int i, n;
a19cbfb3
GH		 322
323 memset(rom, 0, d->rom_size);
324
325 rom->magic = cpu_to_le32(QXL_ROM_MAGIC);
326 rom->id = cpu_to_le32(d->id);
327 rom->log_level = cpu_to_le32(d->guestdebug);
328 rom->modes_offset = cpu_to_le32(sizeof(QXLRom));
329
330 rom->slot_gen_bits = MEMSLOT_GENERATION_BITS;
331 rom->slot_id_bits = MEMSLOT_SLOT_BITS;
332 rom->slots_start = 1;
333 rom->slots_end = NUM_MEMSLOTS - 1;
ddd8fdc7 334 rom->n_surfaces = cpu_to_le32(d->ssd.num_surfaces);
a19cbfb3 335
13d1fd44 336 for (i = 0, n = 0; i < ARRAY_SIZE(qxl_modes); i++) {
a19cbfb3 337 fb = qxl_modes[i].y_res * qxl_modes[i].stride;
13d1fd44
AL		 338 if (fb > d->vgamem_size) {
339 continue;
a19cbfb3 340 }
13d1fd44
AL		 341 modes->modes[n].id = cpu_to_le32(i);
342 modes->modes[n].x_res = cpu_to_le32(qxl_modes[i].x_res);
343 modes->modes[n].y_res = cpu_to_le32(qxl_modes[i].y_res);
344 modes->modes[n].bits = cpu_to_le32(qxl_modes[i].bits);
345 modes->modes[n].stride = cpu_to_le32(qxl_modes[i].stride);
346 modes->modes[n].x_mili = cpu_to_le32(qxl_modes[i].x_mili);
347 modes->modes[n].y_mili = cpu_to_le32(qxl_modes[i].y_mili);
348 modes->modes[n].orientation = cpu_to_le32(qxl_modes[i].orientation);
349 n++;
350 }
351 modes->n_modes = cpu_to_le32(n);
a19cbfb3
GH		 352
353 ram_header_size = ALIGN(sizeof(QXLRam), 4096);
13d1fd44 354 surface0_area_size = ALIGN(d->vgamem_size, 4096);
a19cbfb3
GH		 355 num_pages = d->vga.vram_size;
356 num_pages -= ram_header_size;
357 num_pages -= surface0_area_size;
9efc2d8d 358 num_pages = num_pages / QXL_PAGE_SIZE;
a19cbfb3 359
876d5163
RK		 360 assert(ram_header_size + surface0_area_size <= d->vga.vram_size);
361
a19cbfb3
GH		 362 rom->draw_area_offset = cpu_to_le32(0);
363 rom->surface0_area_size = cpu_to_le32(surface0_area_size);
364 rom->pages_offset = cpu_to_le32(surface0_area_size);
365 rom->num_pages = cpu_to_le32(num_pages);
366 rom->ram_header_offset = cpu_to_le32(d->vga.vram_size - ram_header_size);
367
368 d->shadow_rom = *rom;
369 d->rom = rom;
370 d->modes = modes;
371}
372
373static void init_qxl_ram(PCIQXLDevice *d)
374{
375 uint8_t *buf;
376 uint64_t *item;
377
378 buf = d->vga.vram_ptr;
379 d->ram = (QXLRam *)(buf + le32_to_cpu(d->shadow_rom.ram_header_offset));
380 d->ram->magic = cpu_to_le32(QXL_RAM_MAGIC);
381 d->ram->int_pending = cpu_to_le32(0);
382 d->ram->int_mask = cpu_to_le32(0);
9f0f352d 383 d->ram->update_surface = 0;
329f97fc 384 d->ram->monitors_config = 0;
a19cbfb3
GH		 385 SPICE_RING_INIT(&d->ram->cmd_ring);
386 SPICE_RING_INIT(&d->ram->cursor_ring);
387 SPICE_RING_INIT(&d->ram->release_ring);
0b81c478
AL		 388 SPICE_RING_PROD_ITEM(d, &d->ram->release_ring, item);
389 assert(item);
a19cbfb3
GH		 390 *item = 0;
391 qxl_ring_set_dirty(d);
392}
393
394/* can be called from spice server thread context */
b1950430 395static void qxl_set_dirty(MemoryRegion *mr, ram_addr_t addr, ram_addr_t end)
a19cbfb3 396{
fd4aa979 397 memory_region_set_dirty(mr, addr, end - addr);
a19cbfb3
GH		 398}
399
400static void qxl_rom_set_dirty(PCIQXLDevice *qxl)
401{
b1950430 402 qxl_set_dirty(&qxl->rom_bar, 0, qxl->rom_size);
a19cbfb3
GH		 403}
404
405/* called from spice server thread context only */
406static void qxl_ram_set_dirty(PCIQXLDevice *qxl, void *ptr)
407{
a19cbfb3
GH		 408 void *base = qxl->vga.vram_ptr;
409 intptr_t offset;
410
411 offset = ptr - base;
a19cbfb3 412 assert(offset < qxl->vga.vram_size);
b0297b4a 413 qxl_set_dirty(&qxl->vga.vram, offset, offset + 3);
a19cbfb3
GH		 414}
415
416/* can be called from spice server thread context */
417static void qxl_ring_set_dirty(PCIQXLDevice *qxl)
418{
b1950430
AK		 419 ram_addr_t addr = qxl->shadow_rom.ram_header_offset;
420 ram_addr_t end = qxl->vga.vram_size;
421 qxl_set_dirty(&qxl->vga.vram, addr, end);
a19cbfb3
GH		 422}
423
424/*
425 * keep track of some command state, for savevm/loadvm.
426 * called from spice server thread context only
427 */
fae2afb1 428static int qxl_track_command(PCIQXLDevice *qxl, struct QXLCommandExt *ext)
a19cbfb3
GH		 429{
430 switch (le32_to_cpu(ext->cmd.type)) {
431 case QXL_CMD_SURFACE:
432 {
433 QXLSurfaceCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id);
fae2afb1
AL		 434
435 if (!cmd) {
436 return 1;
437 }
a19cbfb3 438 uint32_t id = le32_to_cpu(cmd->surface_id);
47eddfbf 439
ddd8fdc7 440 if (id >= qxl->ssd.num_surfaces) {
0a530548 441 qxl_set_guest_bug(qxl, "QXL_CMD_SURFACE id %d >= %d", id,
ddd8fdc7 442 qxl->ssd.num_surfaces);
47eddfbf
AL		 443 return 1;
444 }
48f4ba67
AL		 445 if (cmd->type == QXL_SURFACE_CMD_CREATE &&
446 (cmd->u.surface_create.stride & 0x03) != 0) {
447 qxl_set_guest_bug(qxl, "QXL_CMD_SURFACE stride = %d %% 4 != 0\n",
448 cmd->u.surface_create.stride);
449 return 1;
450 }
14898cf6 451 qemu_mutex_lock(&qxl->track_lock);
a19cbfb3
GH		 452 if (cmd->type == QXL_SURFACE_CMD_CREATE) {
453 qxl->guest_surfaces.cmds[id] = ext->cmd.data;
454 qxl->guest_surfaces.count++;
455 if (qxl->guest_surfaces.max < qxl->guest_surfaces.count)
456 qxl->guest_surfaces.max = qxl->guest_surfaces.count;
457 }
458 if (cmd->type == QXL_SURFACE_CMD_DESTROY) {
459 qxl->guest_surfaces.cmds[id] = 0;
460 qxl->guest_surfaces.count--;
461 }
14898cf6 462 qemu_mutex_unlock(&qxl->track_lock);
a19cbfb3
GH		 463 break;
464 }
465 case QXL_CMD_CURSOR:
466 {
467 QXLCursorCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id);
fae2afb1
AL		 468
469 if (!cmd) {
470 return 1;
471 }
a19cbfb3 472 if (cmd->type == QXL_CURSOR_SET) {
30f6da66 473 qemu_mutex_lock(&qxl->track_lock);
a19cbfb3 474 qxl->guest_cursor = ext->cmd.data;
30f6da66 475 qemu_mutex_unlock(&qxl->track_lock);
a19cbfb3
GH		 476 }
477 break;
478 }
479 }
fae2afb1 480 return 0;
a19cbfb3
GH		 481}
482
483/* spice display interface callbacks */
484
485static void interface_attach_worker(QXLInstance *sin, QXLWorker *qxl_worker)
486{
487 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
488
c480bb7d 489 trace_qxl_interface_attach_worker(qxl->id);
a19cbfb3
GH		 490 qxl->ssd.worker = qxl_worker;
491}
492
493static void interface_set_compression_level(QXLInstance *sin, int level)
494{
495 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
496
c480bb7d 497 trace_qxl_interface_set_compression_level(qxl->id, level);
a19cbfb3
GH		 498 qxl->shadow_rom.compression_level = cpu_to_le32(level);
499 qxl->rom->compression_level = cpu_to_le32(level);
500 qxl_rom_set_dirty(qxl);
501}
502
503static void interface_set_mm_time(QXLInstance *sin, uint32_t mm_time)
504{
505 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
506
641381c1
GH		 507 if (!qemu_spice_display_is_running(&qxl->ssd)) {
508 return;
509 }
510
c480bb7d 511 trace_qxl_interface_set_mm_time(qxl->id, mm_time);
a19cbfb3
GH		 512 qxl->shadow_rom.mm_clock = cpu_to_le32(mm_time);
513 qxl->rom->mm_clock = cpu_to_le32(mm_time);
514 qxl_rom_set_dirty(qxl);
515}
516
517static void interface_get_init_info(QXLInstance *sin, QXLDevInitInfo *info)
518{
519 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
520
c480bb7d 521 trace_qxl_interface_get_init_info(qxl->id);
a19cbfb3
GH		 522 info->memslot_gen_bits = MEMSLOT_GENERATION_BITS;
523 info->memslot_id_bits = MEMSLOT_SLOT_BITS;
524 info->num_memslots = NUM_MEMSLOTS;
525 info->num_memslots_groups = NUM_MEMSLOTS_GROUPS;
526 info->internal_groupslot_id = 0;
9efc2d8d
GH		 527 info->qxl_ram_size =
528 le32_to_cpu(qxl->shadow_rom.num_pages) << QXL_PAGE_BITS;
ddd8fdc7 529 info->n_surfaces = qxl->ssd.num_surfaces;
a19cbfb3
GH		 530}
531
5b77870c
AL		 532static const char *qxl_mode_to_string(int mode)
533{
534 switch (mode) {
535 case QXL_MODE_COMPAT:
536 return "compat";
537 case QXL_MODE_NATIVE:
538 return "native";
539 case QXL_MODE_UNDEFINED:
540 return "undefined";
541 case QXL_MODE_VGA:
542 return "vga";
543 }
544 return "INVALID";
545}
546
8b92e298
AL		 547static const char *io_port_to_string(uint32_t io_port)
548{
549 if (io_port >= QXL_IO_RANGE_SIZE) {
550 return "out of range";
551 }
552 static const char *io_port_to_string[QXL_IO_RANGE_SIZE + 1] = {
553 [QXL_IO_NOTIFY_CMD] = "QXL_IO_NOTIFY_CMD",
554 [QXL_IO_NOTIFY_CURSOR] = "QXL_IO_NOTIFY_CURSOR",
555 [QXL_IO_UPDATE_AREA] = "QXL_IO_UPDATE_AREA",
556 [QXL_IO_UPDATE_IRQ] = "QXL_IO_UPDATE_IRQ",
557 [QXL_IO_NOTIFY_OOM] = "QXL_IO_NOTIFY_OOM",
558 [QXL_IO_RESET] = "QXL_IO_RESET",
559 [QXL_IO_SET_MODE] = "QXL_IO_SET_MODE",
560 [QXL_IO_LOG] = "QXL_IO_LOG",
561 [QXL_IO_MEMSLOT_ADD] = "QXL_IO_MEMSLOT_ADD",
562 [QXL_IO_MEMSLOT_DEL] = "QXL_IO_MEMSLOT_DEL",
563 [QXL_IO_DETACH_PRIMARY] = "QXL_IO_DETACH_PRIMARY",
564 [QXL_IO_ATTACH_PRIMARY] = "QXL_IO_ATTACH_PRIMARY",
565 [QXL_IO_CREATE_PRIMARY] = "QXL_IO_CREATE_PRIMARY",
566 [QXL_IO_DESTROY_PRIMARY] = "QXL_IO_DESTROY_PRIMARY",
567 [QXL_IO_DESTROY_SURFACE_WAIT] = "QXL_IO_DESTROY_SURFACE_WAIT",
568 [QXL_IO_DESTROY_ALL_SURFACES] = "QXL_IO_DESTROY_ALL_SURFACES",
8b92e298
AL		 569 [QXL_IO_UPDATE_AREA_ASYNC] = "QXL_IO_UPDATE_AREA_ASYNC",
570 [QXL_IO_MEMSLOT_ADD_ASYNC] = "QXL_IO_MEMSLOT_ADD_ASYNC",
571 [QXL_IO_CREATE_PRIMARY_ASYNC] = "QXL_IO_CREATE_PRIMARY_ASYNC",
572 [QXL_IO_DESTROY_PRIMARY_ASYNC] = "QXL_IO_DESTROY_PRIMARY_ASYNC",
573 [QXL_IO_DESTROY_SURFACE_ASYNC] = "QXL_IO_DESTROY_SURFACE_ASYNC",
574 [QXL_IO_DESTROY_ALL_SURFACES_ASYNC]
575 = "QXL_IO_DESTROY_ALL_SURFACES_ASYNC",
576 [QXL_IO_FLUSH_SURFACES_ASYNC] = "QXL_IO_FLUSH_SURFACES_ASYNC",
577 [QXL_IO_FLUSH_RELEASE] = "QXL_IO_FLUSH_RELEASE",
020af1c4 578 [QXL_IO_MONITORS_CONFIG_ASYNC] = "QXL_IO_MONITORS_CONFIG_ASYNC",
8b92e298
AL		 579 };
580 return io_port_to_string[io_port];
581}
582
a19cbfb3
GH		 583/* called from spice server thread context only */
584static int interface_get_command(QXLInstance *sin, struct QXLCommandExt *ext)
585{
586 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
587 SimpleSpiceUpdate *update;
588 QXLCommandRing *ring;
589 QXLCommand *cmd;
e0c64d08 590 int notify, ret;
a19cbfb3 591
c480bb7d
AL		 592 trace_qxl_ring_command_check(qxl->id, qxl_mode_to_string(qxl->mode));
593
a19cbfb3
GH		 594 switch (qxl->mode) {
595 case QXL_MODE_VGA:
e0c64d08
GH		 596 ret = false;
597 qemu_mutex_lock(&qxl->ssd.lock);
b1af98ba
GH		 598 update = QTAILQ_FIRST(&qxl->ssd.updates);
599 if (update != NULL) {
600 QTAILQ_REMOVE(&qxl->ssd.updates, update, next);
e0c64d08
GH		 601 *ext = update->ext;
602 ret = true;
a19cbfb3 603 }
e0c64d08 604 qemu_mutex_unlock(&qxl->ssd.lock);
212496c9 605 if (ret) {
c480bb7d 606 trace_qxl_ring_command_get(qxl->id, qxl_mode_to_string(qxl->mode));
212496c9
AL		 607 qxl_log_command(qxl, "vga", ext);
608 }
e0c64d08 609 return ret;
a19cbfb3
GH		 610 case QXL_MODE_COMPAT:
611 case QXL_MODE_NATIVE:
612 case QXL_MODE_UNDEFINED:
a19cbfb3 613 ring = &qxl->ram->cmd_ring;
087e6a42 614 if (qxl->guest_bug || SPICE_RING_IS_EMPTY(ring)) {
a19cbfb3
GH		 615 return false;
616 }
0b81c478
AL		 617 SPICE_RING_CONS_ITEM(qxl, ring, cmd);
618 if (!cmd) {
619 return false;
620 }
a19cbfb3
GH		 621 ext->cmd = *cmd;
622 ext->group_id = MEMSLOT_GROUP_GUEST;
623 ext->flags = qxl->cmdflags;
624 SPICE_RING_POP(ring, notify);
625 qxl_ring_set_dirty(qxl);
626 if (notify) {
627 qxl_send_events(qxl, QXL_INTERRUPT_DISPLAY);
628 }
629 qxl->guest_primary.commands++;
630 qxl_track_command(qxl, ext);
631 qxl_log_command(qxl, "cmd", ext);
0b81c478 632 trace_qxl_ring_command_get(qxl->id, qxl_mode_to_string(qxl->mode));
a19cbfb3
GH		 633 return true;
634 default:
635 return false;
636 }
637}
638
639/* called from spice server thread context only */
640static int interface_req_cmd_notification(QXLInstance *sin)
641{
642 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
643 int wait = 1;
644
c480bb7d 645 trace_qxl_ring_command_req_notification(qxl->id);
a19cbfb3
GH		 646 switch (qxl->mode) {
647 case QXL_MODE_COMPAT:
648 case QXL_MODE_NATIVE:
649 case QXL_MODE_UNDEFINED:
650 SPICE_RING_CONS_WAIT(&qxl->ram->cmd_ring, wait);
651 qxl_ring_set_dirty(qxl);
652 break;
653 default:
654 /* nothing */
655 break;
656 }
657 return wait;
658}
659
660/* called from spice server thread context only */
661static inline void qxl_push_free_res(PCIQXLDevice *d, int flush)
662{
663 QXLReleaseRing *ring = &d->ram->release_ring;
664 uint64_t *item;
665 int notify;
666
667#define QXL_FREE_BUNCH_SIZE 32
668
669 if (ring->prod - ring->cons + 1 == ring->num_items) {
670 /* ring full -- can't push */
671 return;
672 }
673 if (!flush && d->oom_running) {
674 /* collect everything from oom handler before pushing */
675 return;
676 }
677 if (!flush && d->num_free_res < QXL_FREE_BUNCH_SIZE) {
678 /* collect a bit more before pushing */
679 return;
680 }
681
682 SPICE_RING_PUSH(ring, notify);
c480bb7d
AL		 683 trace_qxl_ring_res_push(d->id, qxl_mode_to_string(d->mode),
684 d->guest_surfaces.count, d->num_free_res,
685 d->last_release, notify ? "yes" : "no");
686 trace_qxl_ring_res_push_rest(d->id, ring->prod - ring->cons,
687 ring->num_items, ring->prod, ring->cons);
a19cbfb3
GH		 688 if (notify) {
689 qxl_send_events(d, QXL_INTERRUPT_DISPLAY);
690 }
0b81c478
AL		 691 SPICE_RING_PROD_ITEM(d, ring, item);
692 if (!item) {
693 return;
694 }
a19cbfb3
GH		 695 *item = 0;
696 d->num_free_res = 0;
697 d->last_release = NULL;
698 qxl_ring_set_dirty(d);
699}
700
701/* called from spice server thread context only */
702static void interface_release_resource(QXLInstance *sin,
c9f88ce3 703 QXLReleaseInfoExt ext)
a19cbfb3
GH		 704{
705 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
706 QXLReleaseRing *ring;
707 uint64_t *item, id;
708
709 if (ext.group_id == MEMSLOT_GROUP_HOST) {
710 /* host group -> vga mode update request */
e8e23b7d 711 QXLCommandExt *cmdext = (void *)(intptr_t)(ext.info->id);
5643fc01
GH		 712 SimpleSpiceUpdate *update;
713 g_assert(cmdext->cmd.type == QXL_CMD_DRAW);
714 update = container_of(cmdext, SimpleSpiceUpdate, ext);
715 qemu_spice_destroy_update(&qxl->ssd, update);
a19cbfb3
GH		 716 return;
717 }
718
719 /*
720 * ext->info points into guest-visible memory
721 * pci bar 0, $command.release_info
722 */
723 ring = &qxl->ram->release_ring;
0b81c478
AL		 724 SPICE_RING_PROD_ITEM(qxl, ring, item);
725 if (!item) {
726 return;
727 }
a19cbfb3
GH		 728 if (*item == 0) {
729 /* stick head into the ring */
730 id = ext.info->id;
731 ext.info->next = 0;
732 qxl_ram_set_dirty(qxl, &ext.info->next);
733 *item = id;
734 qxl_ring_set_dirty(qxl);
735 } else {
736 /* append item to the list */
737 qxl->last_release->next = ext.info->id;
738 qxl_ram_set_dirty(qxl, &qxl->last_release->next);
739 ext.info->next = 0;
740 qxl_ram_set_dirty(qxl, &ext.info->next);
741 }
742 qxl->last_release = ext.info;
743 qxl->num_free_res++;
c480bb7d 744 trace_qxl_ring_res_put(qxl->id, qxl->num_free_res);
a19cbfb3
GH		 745 qxl_push_free_res(qxl, 0);
746}
747
748/* called from spice server thread context only */
749static int interface_get_cursor_command(QXLInstance *sin, struct QXLCommandExt *ext)
750{
751 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
752 QXLCursorRing *ring;
753 QXLCommand *cmd;
754 int notify;
755
c480bb7d
AL		 756 trace_qxl_ring_cursor_check(qxl->id, qxl_mode_to_string(qxl->mode));
757
a19cbfb3
GH		 758 switch (qxl->mode) {
759 case QXL_MODE_COMPAT:
760 case QXL_MODE_NATIVE:
761 case QXL_MODE_UNDEFINED:
762 ring = &qxl->ram->cursor_ring;
763 if (SPICE_RING_IS_EMPTY(ring)) {
764 return false;
765 }
0b81c478
AL		 766 SPICE_RING_CONS_ITEM(qxl, ring, cmd);
767 if (!cmd) {
768 return false;
769 }
a19cbfb3
GH		 770 ext->cmd = *cmd;
771 ext->group_id = MEMSLOT_GROUP_GUEST;
772 ext->flags = qxl->cmdflags;
773 SPICE_RING_POP(ring, notify);
774 qxl_ring_set_dirty(qxl);
775 if (notify) {
776 qxl_send_events(qxl, QXL_INTERRUPT_CURSOR);
777 }
778 qxl->guest_primary.commands++;
779 qxl_track_command(qxl, ext);
780 qxl_log_command(qxl, "csr", ext);
781 if (qxl->id == 0) {
782 qxl_render_cursor(qxl, ext);
783 }
c480bb7d 784 trace_qxl_ring_cursor_get(qxl->id, qxl_mode_to_string(qxl->mode));
a19cbfb3
GH		 785 return true;
786 default:
787 return false;
788 }
789}
790
791/* called from spice server thread context only */
792static int interface_req_cursor_notification(QXLInstance *sin)
793{
794 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
795 int wait = 1;
796
c480bb7d 797 trace_qxl_ring_cursor_req_notification(qxl->id);
a19cbfb3
GH		 798 switch (qxl->mode) {
799 case QXL_MODE_COMPAT:
800 case QXL_MODE_NATIVE:
801 case QXL_MODE_UNDEFINED:
802 SPICE_RING_CONS_WAIT(&qxl->ram->cursor_ring, wait);
803 qxl_ring_set_dirty(qxl);
804 break;
805 default:
806 /* nothing */
807 break;
808 }
809 return wait;
810}
811
812/* called from spice server thread context */
813static void interface_notify_update(QXLInstance *sin, uint32_t update_id)
814{
baeae407
AL		 815 /*
816 * Called by spice-server as a result of a QXL_CMD_UPDATE which is not in
817 * use by xf86-video-qxl and is defined out in the qxl windows driver.
818 * Probably was at some earlier version that is prior to git start (2009),
819 * and is still guest trigerrable.
820 */
821 fprintf(stderr, "%s: deprecated\n", __func__);
a19cbfb3
GH		 822}
823
824/* called from spice server thread context only */
825static int interface_flush_resources(QXLInstance *sin)
826{
827 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
828 int ret;
829
a19cbfb3
GH		 830 ret = qxl->num_free_res;
831 if (ret) {
832 qxl_push_free_res(qxl, 1);
833 }
834 return ret;
835}
836
5ff4e36c
AL		 837static void qxl_create_guest_primary_complete(PCIQXLDevice *d);
838
5ff4e36c 839/* called from spice server thread context only */
2e1a98c9 840static void interface_async_complete_io(PCIQXLDevice *qxl, QXLCookie *cookie)
5ff4e36c 841{
5ff4e36c
AL		 842 uint32_t current_async;
843
844 qemu_mutex_lock(&qxl->async_lock);
845 current_async = qxl->current_async;
846 qxl->current_async = QXL_UNDEFINED_IO;
847 qemu_mutex_unlock(&qxl->async_lock);
848
c480bb7d 849 trace_qxl_interface_async_complete_io(qxl->id, current_async, cookie);
2e1a98c9
AL		 850 if (!cookie) {
851 fprintf(stderr, "qxl: %s: error, cookie is NULL\n", __func__);
852 return;
853 }
854 if (cookie && current_async != cookie->io) {
855 fprintf(stderr,
2fce7edf
AL		 856 "qxl: %s: error: current_async = %d != %"
857 PRId64 " = cookie->io\n", __func__, current_async, cookie->io);
2e1a98c9 858 }
5ff4e36c 859 switch (current_async) {
81fb6f15
AL		 860 case QXL_IO_MEMSLOT_ADD_ASYNC:
861 case QXL_IO_DESTROY_PRIMARY_ASYNC:
862 case QXL_IO_UPDATE_AREA_ASYNC:
863 case QXL_IO_FLUSH_SURFACES_ASYNC:
020af1c4 864 case QXL_IO_MONITORS_CONFIG_ASYNC:
81fb6f15 865 break;
5ff4e36c
AL		 866 case QXL_IO_CREATE_PRIMARY_ASYNC:
867 qxl_create_guest_primary_complete(qxl);
868 break;
869 case QXL_IO_DESTROY_ALL_SURFACES_ASYNC:
870 qxl_spice_destroy_surfaces_complete(qxl);
871 break;
872 case QXL_IO_DESTROY_SURFACE_ASYNC:
2e1a98c9 873 qxl_spice_destroy_surface_wait_complete(qxl, cookie->u.surface_id);
5ff4e36c 874 break;
81fb6f15
AL		 875 default:
876 fprintf(stderr, "qxl: %s: unexpected current_async %d\n", __func__,
877 current_async);
5ff4e36c
AL		 878 }
879 qxl_send_events(qxl, QXL_INTERRUPT_IO_CMD);
880}
881
81fb6f15
AL		 882/* called from spice server thread context only */
883static void interface_update_area_complete(QXLInstance *sin,
884 uint32_t surface_id,
885 QXLRect *dirty, uint32_t num_updated_rects)
886{
887 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
888 int i;
889 int qxl_i;
890
891 qemu_mutex_lock(&qxl->ssd.lock);
892 if (surface_id != 0 || !qxl->render_update_cookie_num) {
893 qemu_mutex_unlock(&qxl->ssd.lock);
894 return;
895 }
c480bb7d
AL		 896 trace_qxl_interface_update_area_complete(qxl->id, surface_id, dirty->left,
897 dirty->right, dirty->top, dirty->bottom);
898 trace_qxl_interface_update_area_complete_rest(qxl->id, num_updated_rects);
81fb6f15
AL		 899 if (qxl->num_dirty_rects + num_updated_rects > QXL_NUM_DIRTY_RECTS) {
900 /*
901 * overflow - treat this as a full update. Not expected to be common.
902 */
c480bb7d
AL		 903 trace_qxl_interface_update_area_complete_overflow(qxl->id,
904 QXL_NUM_DIRTY_RECTS);
81fb6f15
AL		 905 qxl->guest_primary.resized = 1;
906 }
907 if (qxl->guest_primary.resized) {
908 /*
909 * Don't bother copying or scheduling the bh since we will flip
910 * the whole area anyway on completion of the update_area async call
911 */
912 qemu_mutex_unlock(&qxl->ssd.lock);
913 return;
914 }
915 qxl_i = qxl->num_dirty_rects;
916 for (i = 0; i < num_updated_rects; i++) {
917 qxl->dirty[qxl_i++] = dirty[i];
918 }
919 qxl->num_dirty_rects += num_updated_rects;
c480bb7d
AL		 920 trace_qxl_interface_update_area_complete_schedule_bh(qxl->id,
921 qxl->num_dirty_rects);
81fb6f15
AL		 922 qemu_bh_schedule(qxl->update_area_bh);
923 qemu_mutex_unlock(&qxl->ssd.lock);
924}
925
2e1a98c9
AL		 926/* called from spice server thread context only */
927static void interface_async_complete(QXLInstance *sin, uint64_t cookie_token)
928{
929 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
5dba0d45 930 QXLCookie *cookie = (QXLCookie *)(uintptr_t)cookie_token;
2e1a98c9
AL		 931
932 switch (cookie->type) {
933 case QXL_COOKIE_TYPE_IO:
934 interface_async_complete_io(qxl, cookie);
81fb6f15
AL		 935 g_free(cookie);
936 break;
937 case QXL_COOKIE_TYPE_RENDER_UPDATE_AREA:
938 qxl_render_update_area_done(qxl, cookie);
2e1a98c9 939 break;
020af1c4
AL		 940 case QXL_COOKIE_TYPE_POST_LOAD_MONITORS_CONFIG:
941 break;
2e1a98c9
AL		 942 default:
943 fprintf(stderr, "qxl: %s: unexpected cookie type %d\n",
944 __func__, cookie->type);
81fb6f15 945 g_free(cookie);
2e1a98c9 946 }
2e1a98c9
AL		 947}
948
c10018d6
SSP		 949/* called from spice server thread context only */
950static void interface_set_client_capabilities(QXLInstance *sin,
951 uint8_t client_present,
952 uint8_t caps[58])
953{
954 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
955
e0ac6097
AL		 956 if (qxl->revision < 4) {
957 trace_qxl_set_client_capabilities_unsupported_by_revision(qxl->id,
958 qxl->revision);
959 return;
960 }
961
ab902981
HG		 962 if (runstate_check(RUN_STATE_INMIGRATE) ||
963 runstate_check(RUN_STATE_POSTMIGRATE)) {
964 return;
965 }
966
c10018d6 967 qxl->shadow_rom.client_present = client_present;
08688af0
MA		 968 memcpy(qxl->shadow_rom.client_capabilities, caps,
969 sizeof(qxl->shadow_rom.client_capabilities));
c10018d6 970 qxl->rom->client_present = client_present;
08688af0
MA		 971 memcpy(qxl->rom->client_capabilities, caps,
972 sizeof(qxl->rom->client_capabilities));
c10018d6
SSP		 973 qxl_rom_set_dirty(qxl);
974
975 qxl_send_events(qxl, QXL_INTERRUPT_CLIENT);
976}
977
a639ab04
AL		 978static uint32_t qxl_crc32(const uint8_t *p, unsigned len)
979{
980 /*
981 * zlib xors the seed with 0xffffffff, and xors the result
982 * again with 0xffffffff; Both are not done with linux's crc32,
983 * which we want to be compatible with, so undo that.
984 */
985 return crc32(0xffffffff, p, len) ^ 0xffffffff;
986}
987
988/* called from main context only */
989static int interface_client_monitors_config(QXLInstance *sin,
990 VDAgentMonitorsConfig *monitors_config)
991{
992 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
993 QXLRom *rom = memory_region_get_ram_ptr(&qxl->rom_bar);
994 int i;
995
e0ac6097
AL		 996 if (qxl->revision < 4) {
997 trace_qxl_client_monitors_config_unsupported_by_device(qxl->id,
998 qxl->revision);
999 return 0;
1000 }
a639ab04
AL		 1001 /*
1002 * Older windows drivers set int_mask to 0 when their ISR is called,
1003 * then later set it to ~0. So it doesn't relate to the actual interrupts
1004 * handled. However, they are old, so clearly they don't support this
1005 * interrupt
1006 */
1007 if (qxl->ram->int_mask == 0 || qxl->ram->int_mask == ~0 ||
1008 !(qxl->ram->int_mask & QXL_INTERRUPT_CLIENT_MONITORS_CONFIG)) {
1009 trace_qxl_client_monitors_config_unsupported_by_guest(qxl->id,
1010 qxl->ram->int_mask,
1011 monitors_config);
1012 return 0;
1013 }
1014 if (!monitors_config) {
1015 return 1;
1016 }
1017 memset(&rom->client_monitors_config, 0,
1018 sizeof(rom->client_monitors_config));
1019 rom->client_monitors_config.count = monitors_config->num_of_monitors;
1020 /* monitors_config->flags ignored */
1021 if (rom->client_monitors_config.count >=
1022 ARRAY_SIZE(rom->client_monitors_config.heads)) {
1023 trace_qxl_client_monitors_config_capped(qxl->id,
1024 monitors_config->num_of_monitors,
1025 ARRAY_SIZE(rom->client_monitors_config.heads));
1026 rom->client_monitors_config.count =
1027 ARRAY_SIZE(rom->client_monitors_config.heads);
1028 }
1029 for (i = 0 ; i < rom->client_monitors_config.count ; ++i) {
1030 VDAgentMonConfig *monitor = &monitors_config->monitors[i];
1031 QXLURect *rect = &rom->client_monitors_config.heads[i];
1032 /* monitor->depth ignored */
1033 rect->left = monitor->x;
1034 rect->top = monitor->y;
1035 rect->right = monitor->x + monitor->width;
1036 rect->bottom = monitor->y + monitor->height;
1037 }
1038 rom->client_monitors_config_crc = qxl_crc32(
1039 (const uint8_t *)&rom->client_monitors_config,
1040 sizeof(rom->client_monitors_config));
1041 trace_qxl_client_monitors_config_crc(qxl->id,
1042 sizeof(rom->client_monitors_config),
1043 rom->client_monitors_config_crc);
1044
1045 trace_qxl_interrupt_client_monitors_config(qxl->id,
1046 rom->client_monitors_config.count,
1047 rom->client_monitors_config.heads);
1048 qxl_send_events(qxl, QXL_INTERRUPT_CLIENT_MONITORS_CONFIG);
1049 return 1;
1050}
a639ab04 1051
a19cbfb3
GH		 1052static const QXLInterface qxl_interface = {
1053 .base.type = SPICE_INTERFACE_QXL,
1054 .base.description = "qxl gpu",
1055 .base.major_version = SPICE_INTERFACE_QXL_MAJOR,
1056 .base.minor_version = SPICE_INTERFACE_QXL_MINOR,
1057
1058 .attache_worker = interface_attach_worker,
1059 .set_compression_level = interface_set_compression_level,
1060 .set_mm_time = interface_set_mm_time,
1061 .get_init_info = interface_get_init_info,
1062
1063 /* the callbacks below are called from spice server thread context */
1064 .get_command = interface_get_command,
1065 .req_cmd_notification = interface_req_cmd_notification,
1066 .release_resource = interface_release_resource,
1067 .get_cursor_command = interface_get_cursor_command,
1068 .req_cursor_notification = interface_req_cursor_notification,
1069 .notify_update = interface_notify_update,
1070 .flush_resources = interface_flush_resources,
5ff4e36c 1071 .async_complete = interface_async_complete,
81fb6f15 1072 .update_area_complete = interface_update_area_complete,
c10018d6 1073 .set_client_capabilities = interface_set_client_capabilities,
a639ab04 1074 .client_monitors_config = interface_client_monitors_config,
a19cbfb3
GH		 1075};
1076
15162335
GH		 1077static const GraphicHwOps qxl_ops = {
1078 .gfx_update = qxl_hw_update,
1079};
1080
a19cbfb3
GH		 1081static void qxl_enter_vga_mode(PCIQXLDevice *d)
1082{
1083 if (d->mode == QXL_MODE_VGA) {
1084 return;
1085 }
c480bb7d 1086 trace_qxl_enter_vga_mode(d->id);
0a2b5e3a
HG		 1087#if SPICE_SERVER_VERSION >= 0x000c03 /* release 0.12.3 */
1088 spice_qxl_driver_unload(&d->ssd.qxl);
1089#endif
15162335 1090 graphic_console_set_hwops(d->ssd.dcl.con, d->vga.hw_ops, &d->vga);
3dcadce5 1091 update_displaychangelistener(&d->ssd.dcl, GUI_REFRESH_INTERVAL_DEFAULT);
a19cbfb3
GH		 1092 qemu_spice_create_host_primary(&d->ssd);
1093 d->mode = QXL_MODE_VGA;
0f7bfd81 1094 vga_dirty_log_start(&d->vga);
1dbfa005 1095 graphic_hw_update(d->vga.con);
a19cbfb3
GH		 1096}
1097
1098static void qxl_exit_vga_mode(PCIQXLDevice *d)
1099{
1100 if (d->mode != QXL_MODE_VGA) {
1101 return;
1102 }
c480bb7d 1103 trace_qxl_exit_vga_mode(d->id);
15162335 1104 graphic_console_set_hwops(d->ssd.dcl.con, &qxl_ops, d);
3dcadce5 1105 update_displaychangelistener(&d->ssd.dcl, GUI_REFRESH_INTERVAL_IDLE);
0f7bfd81 1106 vga_dirty_log_stop(&d->vga);
5ff4e36c 1107 qxl_destroy_primary(d, QXL_SYNC);
a19cbfb3
GH		 1108}
1109
40010aea 1110static void qxl_update_irq(PCIQXLDevice *d)
a19cbfb3
GH		 1111{
1112 uint32_t pending = le32_to_cpu(d->ram->int_pending);
1113 uint32_t mask = le32_to_cpu(d->ram->int_mask);
1114 int level = !!(pending & mask);
9e64f8a3 1115 pci_set_irq(&d->pci, level);
a19cbfb3
GH		 1116 qxl_ring_set_dirty(d);
1117}
1118
a19cbfb3
GH		 1119static void qxl_check_state(PCIQXLDevice *d)
1120{
1121 QXLRam *ram = d->ram;
71d388d4 1122 int spice_display_running = qemu_spice_display_is_running(&d->ssd);
a19cbfb3 1123
71d388d4
YH		 1124 assert(!spice_display_running || SPICE_RING_IS_EMPTY(&ram->cmd_ring));
1125 assert(!spice_display_running || SPICE_RING_IS_EMPTY(&ram->cursor_ring));
a19cbfb3
GH		 1126}
1127
1128static void qxl_reset_state(PCIQXLDevice *d)
1129{
a19cbfb3
GH		 1130 QXLRom *rom = d->rom;
1131
be48e995 1132 qxl_check_state(d);
a19cbfb3
GH		 1133 d->shadow_rom.update_id = cpu_to_le32(0);
1134 *rom = d->shadow_rom;
1135 qxl_rom_set_dirty(d);
1136 init_qxl_ram(d);
1137 d->num_free_res = 0;
1138 d->last_release = NULL;
1139 memset(&d->ssd.dirty, 0, sizeof(d->ssd.dirty));
f06b8521 1140 qxl_update_irq(d);
a19cbfb3
GH		 1141}
1142
1143static void qxl_soft_reset(PCIQXLDevice *d)
1144{
c480bb7d 1145 trace_qxl_soft_reset(d->id);
a19cbfb3 1146 qxl_check_state(d);
087e6a42 1147 qxl_clear_guest_bug(d);
a5f68c22 1148 d->current_async = QXL_UNDEFINED_IO;
a19cbfb3
GH		 1149
1150 if (d->id == 0) {
1151 qxl_enter_vga_mode(d);
1152 } else {
1153 d->mode = QXL_MODE_UNDEFINED;
1154 }
1155}
1156
1157static void qxl_hard_reset(PCIQXLDevice *d, int loadvm)
1158{
75c70e37
GH		 1159 bool startstop = qemu_spice_display_is_running(&d->ssd);
1160
c480bb7d 1161 trace_qxl_hard_reset(d->id, loadvm);
a19cbfb3 1162
75c70e37
GH		 1163 if (startstop) {
1164 qemu_spice_display_stop();
1165 }
1166
aee32bf3
GH		 1167 qxl_spice_reset_cursor(d);
1168 qxl_spice_reset_image_cache(d);
a19cbfb3
GH		 1169 qxl_reset_surfaces(d);
1170 qxl_reset_memslots(d);
1171
1172 /* pre loadvm reset must not touch QXLRam. This lives in
1173 * device memory, is migrated together with RAM and thus
1174 * already loaded at this point */
1175 if (!loadvm) {
1176 qxl_reset_state(d);
1177 }
1178 qemu_spice_create_host_memslot(&d->ssd);
1179 qxl_soft_reset(d);
75c70e37
GH		 1180
1181 if (startstop) {
1182 qemu_spice_display_start();
1183 }
a19cbfb3
GH		 1184}
1185
1186static void qxl_reset_handler(DeviceState *dev)
1187{
c69f6c7d 1188 PCIQXLDevice *d = PCI_QXL(PCI_DEVICE(dev));
c480bb7d 1189
a19cbfb3
GH		 1190 qxl_hard_reset(d, 0);
1191}
1192
1193static void qxl_vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
1194{
1195 VGACommonState *vga = opaque;
1196 PCIQXLDevice *qxl = container_of(vga, PCIQXLDevice, vga);
1197
c480bb7d 1198 trace_qxl_io_write_vga(qxl->id, qxl_mode_to_string(qxl->mode), addr, val);
a19cbfb3 1199 if (qxl->mode != QXL_MODE_VGA) {
5ff4e36c 1200 qxl_destroy_primary(qxl, QXL_SYNC);
a19cbfb3
GH		 1201 qxl_soft_reset(qxl);
1202 }
1203 vga_ioport_write(opaque, addr, val);
1204}
1205
f67ab77a
GH		 1206static const MemoryRegionPortio qxl_vga_portio_list[] = {
1207 { 0x04, 2, 1, .read = vga_ioport_read,
1208 .write = qxl_vga_ioport_write }, /* 3b4 */
1209 { 0x0a, 1, 1, .read = vga_ioport_read,
1210 .write = qxl_vga_ioport_write }, /* 3ba */
1211 { 0x10, 16, 1, .read = vga_ioport_read,
1212 .write = qxl_vga_ioport_write }, /* 3c0 */
1213 { 0x24, 2, 1, .read = vga_ioport_read,
1214 .write = qxl_vga_ioport_write }, /* 3d4 */
1215 { 0x2a, 1, 1, .read = vga_ioport_read,
1216 .write = qxl_vga_ioport_write }, /* 3da */
1217 PORTIO_END_OF_LIST(),
1218};
1219
e954ea28
AL		 1220static int qxl_add_memslot(PCIQXLDevice *d, uint32_t slot_id, uint64_t delta,
1221 qxl_async_io async)
a19cbfb3
GH		 1222{
1223 static const int regions[] = {
1224 QXL_RAM_RANGE_INDEX,
1225 QXL_VRAM_RANGE_INDEX,
6f2b175a 1226 QXL_VRAM64_RANGE_INDEX,
a19cbfb3
GH		 1227 };
1228 uint64_t guest_start;
1229 uint64_t guest_end;
1230 int pci_region;
1231 pcibus_t pci_start;
1232 pcibus_t pci_end;
1233 intptr_t virt_start;
1234 QXLDevMemSlot memslot;
1235 int i;
1236
1237 guest_start = le64_to_cpu(d->guest_slots[slot_id].slot.mem_start);
1238 guest_end = le64_to_cpu(d->guest_slots[slot_id].slot.mem_end);
1239
c480bb7d 1240 trace_qxl_memslot_add_guest(d->id, slot_id, guest_start, guest_end);
a19cbfb3 1241
e954ea28 1242 if (slot_id >= NUM_MEMSLOTS) {
0a530548 1243 qxl_set_guest_bug(d, "%s: slot_id >= NUM_MEMSLOTS %d >= %d", __func__,
e954ea28
AL		 1244 slot_id, NUM_MEMSLOTS);
1245 return 1;
1246 }
1247 if (guest_start > guest_end) {
0a530548 1248 qxl_set_guest_bug(d, "%s: guest_start > guest_end 0x%" PRIx64
e954ea28
AL		 1249 " > 0x%" PRIx64, __func__, guest_start, guest_end);
1250 return 1;
1251 }
a19cbfb3
GH		 1252
1253 for (i = 0; i < ARRAY_SIZE(regions); i++) {
1254 pci_region = regions[i];
1255 pci_start = d->pci.io_regions[pci_region].addr;
1256 pci_end = pci_start + d->pci.io_regions[pci_region].size;
1257 /* mapped? */
1258 if (pci_start == -1) {
1259 continue;
1260 }
1261 /* start address in range ? */
1262 if (guest_start < pci_start || guest_start > pci_end) {
1263 continue;
1264 }
1265 /* end address in range ? */
1266 if (guest_end > pci_end) {
1267 continue;
1268 }
1269 /* passed */
1270 break;
1271 }
e954ea28 1272 if (i == ARRAY_SIZE(regions)) {
0a530548 1273 qxl_set_guest_bug(d, "%s: finished loop without match", __func__);
e954ea28
AL		 1274 return 1;
1275 }
a19cbfb3
GH		 1276
1277 switch (pci_region) {
1278 case QXL_RAM_RANGE_INDEX:
b1950430 1279 virt_start = (intptr_t)memory_region_get_ram_ptr(&d->vga.vram);
a19cbfb3
GH		 1280 break;
1281 case QXL_VRAM_RANGE_INDEX:
6f2b175a 1282 case 4 /* vram 64bit */:
b1950430 1283 virt_start = (intptr_t)memory_region_get_ram_ptr(&d->vram_bar);
a19cbfb3
GH		 1284 break;
1285 default:
1286 /* should not happen */
0a530548 1287 qxl_set_guest_bug(d, "%s: pci_region = %d", __func__, pci_region);
e954ea28 1288 return 1;
a19cbfb3
GH		 1289 }
1290
1291 memslot.slot_id = slot_id;
1292 memslot.slot_group_id = MEMSLOT_GROUP_GUEST; /* guest group */
1293 memslot.virt_start = virt_start + (guest_start - pci_start);
1294 memslot.virt_end = virt_start + (guest_end - pci_start);
1295 memslot.addr_delta = memslot.virt_start - delta;
1296 memslot.generation = d->rom->slot_generation = 0;
1297 qxl_rom_set_dirty(d);
1298
5ff4e36c 1299 qemu_spice_add_memslot(&d->ssd, &memslot, async);
a19cbfb3
GH		 1300 d->guest_slots[slot_id].ptr = (void*)memslot.virt_start;
1301 d->guest_slots[slot_id].size = memslot.virt_end - memslot.virt_start;
1302 d->guest_slots[slot_id].delta = delta;
1303 d->guest_slots[slot_id].active = 1;
e954ea28 1304 return 0;
a19cbfb3
GH		 1305}
1306
1307static void qxl_del_memslot(PCIQXLDevice *d, uint32_t slot_id)
1308{
5c59d118 1309 qemu_spice_del_memslot(&d->ssd, MEMSLOT_GROUP_HOST, slot_id);
a19cbfb3
GH		 1310 d->guest_slots[slot_id].active = 0;
1311}
1312
1313static void qxl_reset_memslots(PCIQXLDevice *d)
1314{
aee32bf3 1315 qxl_spice_reset_memslots(d);
a19cbfb3
GH		 1316 memset(&d->guest_slots, 0, sizeof(d->guest_slots));
1317}
1318
1319static void qxl_reset_surfaces(PCIQXLDevice *d)
1320{
c480bb7d 1321 trace_qxl_reset_surfaces(d->id);
a19cbfb3 1322 d->mode = QXL_MODE_UNDEFINED;
5ff4e36c 1323 qxl_spice_destroy_surfaces(d, QXL_SYNC);
a19cbfb3
GH		 1324}
1325
e25139b3 1326/* can be also called from spice server thread context */
a19cbfb3
GH		 1327void *qxl_phys2virt(PCIQXLDevice *qxl, QXLPHYSICAL pqxl, int group_id)
1328{
1329 uint64_t phys = le64_to_cpu(pqxl);
1330 uint32_t slot = (phys >> (64 - 8)) & 0xff;
1331 uint64_t offset = phys & 0xffffffffffff;
1332
1333 switch (group_id) {
1334 case MEMSLOT_GROUP_HOST:
f4a8a424 1335 return (void *)(intptr_t)offset;
a19cbfb3 1336 case MEMSLOT_GROUP_GUEST:
4b635c59 1337 if (slot >= NUM_MEMSLOTS) {
0a530548
AL		 1338 qxl_set_guest_bug(qxl, "slot too large %d >= %d", slot,
1339 NUM_MEMSLOTS);
4b635c59
AL		 1340 return NULL;
1341 }
1342 if (!qxl->guest_slots[slot].active) {
0a530548 1343 qxl_set_guest_bug(qxl, "inactive slot %d\n", slot);
4b635c59
AL		 1344 return NULL;
1345 }
1346 if (offset < qxl->guest_slots[slot].delta) {
0a530548
AL		 1347 qxl_set_guest_bug(qxl,
1348 "slot %d offset %"PRIu64" < delta %"PRIu64"\n",
4b635c59
AL		 1349 slot, offset, qxl->guest_slots[slot].delta);
1350 return NULL;
1351 }
a19cbfb3 1352 offset -= qxl->guest_slots[slot].delta;
4b635c59 1353 if (offset > qxl->guest_slots[slot].size) {
0a530548
AL		 1354 qxl_set_guest_bug(qxl,
1355 "slot %d offset %"PRIu64" > size %"PRIu64"\n",
4b635c59
AL		 1356 slot, offset, qxl->guest_slots[slot].size);
1357 return NULL;
1358 }
a19cbfb3 1359 return qxl->guest_slots[slot].ptr + offset;
a19cbfb3 1360 }
4b635c59 1361 return NULL;
a19cbfb3
GH		 1362}
1363
5ff4e36c
AL		 1364static void qxl_create_guest_primary_complete(PCIQXLDevice *qxl)
1365{
1366 /* for local rendering */
1367 qxl_render_resize(qxl);
1368}
1369
1370static void qxl_create_guest_primary(PCIQXLDevice *qxl, int loadvm,
1371 qxl_async_io async)
a19cbfb3
GH		 1372{
1373 QXLDevSurfaceCreate surface;
1374 QXLSurfaceCreate *sc = &qxl->guest_primary.surface;
3761abb1 1375 uint32_t requested_height = le32_to_cpu(sc->height);
13d1fd44
AL		 1376 int requested_stride = le32_to_cpu(sc->stride);
1377
3761abb1
AL		 1378 if (requested_stride == INT32_MIN ||
1379 abs(requested_stride) * (uint64_t)requested_height
1380 > qxl->vgamem_size) {
1381 qxl_set_guest_bug(qxl, "%s: requested primary larger than framebuffer"
1382 " stride %d x height %" PRIu32 " > %" PRIu32,
1383 __func__, requested_stride, requested_height,
1384 qxl->vgamem_size);
13d1fd44
AL		 1385 return;
1386 }
a19cbfb3 1387
ddf9f4b7 1388 if (qxl->mode == QXL_MODE_NATIVE) {
0a530548 1389 qxl_set_guest_bug(qxl, "%s: nop since already in QXL_MODE_NATIVE",
ddf9f4b7
AL		 1390 __func__);
1391 }
a19cbfb3
GH		 1392 qxl_exit_vga_mode(qxl);
1393
a19cbfb3
GH		 1394 surface.format = le32_to_cpu(sc->format);
1395 surface.height = le32_to_cpu(sc->height);
1396 surface.mem = le64_to_cpu(sc->mem);
1397 surface.position = le32_to_cpu(sc->position);
1398 surface.stride = le32_to_cpu(sc->stride);
1399 surface.width = le32_to_cpu(sc->width);
1400 surface.type = le32_to_cpu(sc->type);
1401 surface.flags = le32_to_cpu(sc->flags);
c480bb7d
AL		 1402 trace_qxl_create_guest_primary(qxl->id, sc->width, sc->height, sc->mem,
1403 sc->format, sc->position);
1404 trace_qxl_create_guest_primary_rest(qxl->id, sc->stride, sc->type,
1405 sc->flags);
a19cbfb3 1406
48f4ba67
AL		 1407 if ((surface.stride & 0x3) != 0) {
1408 qxl_set_guest_bug(qxl, "primary surface stride = %d %% 4 != 0",
1409 surface.stride);
1410 return;
1411 }
1412
a19cbfb3
GH		 1413 surface.mouse_mode = true;
1414 surface.group_id = MEMSLOT_GROUP_GUEST;
1415 if (loadvm) {
1416 surface.flags |= QXL_SURF_FLAG_KEEP_DATA;
1417 }
1418
1419 qxl->mode = QXL_MODE_NATIVE;
1420 qxl->cmdflags = 0;
5ff4e36c 1421 qemu_spice_create_primary_surface(&qxl->ssd, 0, &surface, async);
a19cbfb3 1422
5ff4e36c
AL		 1423 if (async == QXL_SYNC) {
1424 qxl_create_guest_primary_complete(qxl);
1425 }
a19cbfb3
GH		 1426}
1427
5ff4e36c
AL		 1428/* return 1 if surface destoy was initiated (in QXL_ASYNC case) or
1429 * done (in QXL_SYNC case), 0 otherwise. */
1430static int qxl_destroy_primary(PCIQXLDevice *d, qxl_async_io async)
a19cbfb3
GH		 1431{
1432 if (d->mode == QXL_MODE_UNDEFINED) {
5ff4e36c 1433 return 0;
a19cbfb3 1434 }
c480bb7d 1435 trace_qxl_destroy_primary(d->id);
a19cbfb3 1436 d->mode = QXL_MODE_UNDEFINED;
5ff4e36c 1437 qemu_spice_destroy_primary_surface(&d->ssd, 0, async);
30f6da66 1438 qxl_spice_reset_cursor(d);
5ff4e36c 1439 return 1;
a19cbfb3
GH		 1440}
1441
9c70434f 1442static void qxl_set_mode(PCIQXLDevice *d, unsigned int modenr, int loadvm)
a19cbfb3
GH		 1443{
1444 pcibus_t start = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr;
1445 pcibus_t end = d->pci.io_regions[QXL_RAM_RANGE_INDEX].size + start;
1446 QXLMode *mode = d->modes->modes + modenr;
1447 uint64_t devmem = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr;
1448 QXLMemSlot slot = {
1449 .mem_start = start,
1450 .mem_end = end
1451 };
9c70434f
GH		 1452
1453 if (modenr >= d->modes->n_modes) {
1454 qxl_set_guest_bug(d, "mode number out of range");
1455 return;
1456 }
1457
a19cbfb3
GH		 1458 QXLSurfaceCreate surface = {
1459 .width = mode->x_res,
1460 .height = mode->y_res,
1461 .stride = -mode->x_res * 4,
1462 .format = SPICE_SURFACE_FMT_32_xRGB,
1463 .flags = loadvm ? QXL_SURF_FLAG_KEEP_DATA : 0,
1464 .mouse_mode = true,
1465 .mem = devmem + d->shadow_rom.draw_area_offset,
1466 };
1467
c480bb7d
AL		 1468 trace_qxl_set_mode(d->id, modenr, mode->x_res, mode->y_res, mode->bits,
1469 devmem);
a19cbfb3
GH		 1470 if (!loadvm) {
1471 qxl_hard_reset(d, 0);
1472 }
1473
1474 d->guest_slots[0].slot = slot;
e954ea28 1475 assert(qxl_add_memslot(d, 0, devmem, QXL_SYNC) == 0);
a19cbfb3
GH		 1476
1477 d->guest_primary.surface = surface;
5ff4e36c 1478 qxl_create_guest_primary(d, 0, QXL_SYNC);
a19cbfb3
GH		 1479
1480 d->mode = QXL_MODE_COMPAT;
1481 d->cmdflags = QXL_COMMAND_FLAG_COMPAT;
a19cbfb3
GH		 1482 if (mode->bits == 16) {
1483 d->cmdflags |= QXL_COMMAND_FLAG_COMPAT_16BPP;
1484 }
a19cbfb3
GH		 1485 d->shadow_rom.mode = cpu_to_le32(modenr);
1486 d->rom->mode = cpu_to_le32(modenr);
1487 qxl_rom_set_dirty(d);
1488}
1489
a8170e5e 1490static void ioport_write(void *opaque, hwaddr addr,
b1950430 1491 uint64_t val, unsigned size)
a19cbfb3
GH		 1492{
1493 PCIQXLDevice *d = opaque;
b1950430 1494 uint32_t io_port = addr;
5ff4e36c 1495 qxl_async_io async = QXL_SYNC;
5ff4e36c 1496 uint32_t orig_io_port = io_port;
a19cbfb3 1497
d96aafca 1498 if (d->guest_bug && io_port != QXL_IO_RESET) {
087e6a42
AL		 1499 return;
1500 }
1501
020af1c4 1502 if (d->revision <= QXL_REVISION_STABLE_V10 &&
ffe01e59 1503 io_port > QXL_IO_FLUSH_RELEASE) {
020af1c4
AL		 1504 qxl_set_guest_bug(d, "unsupported io %d for revision %d\n",
1505 io_port, d->revision);
1506 return;
1507 }
1508
a19cbfb3
GH		 1509 switch (io_port) {
1510 case QXL_IO_RESET:
1511 case QXL_IO_SET_MODE:
1512 case QXL_IO_MEMSLOT_ADD:
1513 case QXL_IO_MEMSLOT_DEL:
1514 case QXL_IO_CREATE_PRIMARY:
81144d1a 1515 case QXL_IO_UPDATE_IRQ:
a3d14054 1516 case QXL_IO_LOG:
5ff4e36c
AL		 1517 case QXL_IO_MEMSLOT_ADD_ASYNC:
1518 case QXL_IO_CREATE_PRIMARY_ASYNC:
a19cbfb3
GH		 1519 break;
1520 default:
e21a298a 1521 if (d->mode != QXL_MODE_VGA) {
a19cbfb3 1522 break;
e21a298a 1523 }
c480bb7d 1524 trace_qxl_io_unexpected_vga_mode(d->id,
917ae08c 1525 addr, val, io_port_to_string(io_port));
5ff4e36c
AL		 1526 /* be nice to buggy guest drivers */
1527 if (io_port >= QXL_IO_UPDATE_AREA_ASYNC &&
020af1c4 1528 io_port < QXL_IO_RANGE_SIZE) {
5ff4e36c
AL		 1529 qxl_send_events(d, QXL_INTERRUPT_IO_CMD);
1530 }
a19cbfb3
GH		 1531 return;
1532 }
1533
5ff4e36c
AL		 1534 /* we change the io_port to avoid ifdeffery in the main switch */
1535 orig_io_port = io_port;
1536 switch (io_port) {
1537 case QXL_IO_UPDATE_AREA_ASYNC:
1538 io_port = QXL_IO_UPDATE_AREA;
1539 goto async_common;
1540 case QXL_IO_MEMSLOT_ADD_ASYNC:
1541 io_port = QXL_IO_MEMSLOT_ADD;
1542 goto async_common;
1543 case QXL_IO_CREATE_PRIMARY_ASYNC:
1544 io_port = QXL_IO_CREATE_PRIMARY;
1545 goto async_common;
1546 case QXL_IO_DESTROY_PRIMARY_ASYNC:
1547 io_port = QXL_IO_DESTROY_PRIMARY;
1548 goto async_common;
1549 case QXL_IO_DESTROY_SURFACE_ASYNC:
1550 io_port = QXL_IO_DESTROY_SURFACE_WAIT;
1551 goto async_common;
1552 case QXL_IO_DESTROY_ALL_SURFACES_ASYNC:
1553 io_port = QXL_IO_DESTROY_ALL_SURFACES;
3e16b9c5
AL		 1554 goto async_common;
1555 case QXL_IO_FLUSH_SURFACES_ASYNC:
020af1c4 1556 case QXL_IO_MONITORS_CONFIG_ASYNC:
5ff4e36c
AL		 1557async_common:
1558 async = QXL_ASYNC;
1559 qemu_mutex_lock(&d->async_lock);
1560 if (d->current_async != QXL_UNDEFINED_IO) {
0a530548 1561 qxl_set_guest_bug(d, "%d async started before last (%d) complete",
5ff4e36c
AL		 1562 io_port, d->current_async);
1563 qemu_mutex_unlock(&d->async_lock);
1564 return;
1565 }
1566 d->current_async = orig_io_port;
1567 qemu_mutex_unlock(&d->async_lock);
5ff4e36c
AL		 1568 break;
1569 default:
1570 break;
1571 }
18b20385
GH		 1572 trace_qxl_io_write(d->id, qxl_mode_to_string(d->mode),
1573 addr, io_port_to_string(addr),
1574 val, size, async);
5ff4e36c 1575
a19cbfb3
GH		 1576 switch (io_port) {
1577 case QXL_IO_UPDATE_AREA:
1578 {
81fb6f15 1579 QXLCookie *cookie = NULL;
a19cbfb3 1580 QXLRect update = d->ram->update_area;
81fb6f15 1581
ddd8fdc7 1582 if (d->ram->update_surface > d->ssd.num_surfaces) {
511b13e2
AL		 1583 qxl_set_guest_bug(d, "QXL_IO_UPDATE_AREA: invalid surface id %d\n",
1584 d->ram->update_surface);
36a03e0b 1585 break;
511b13e2 1586 }
36a03e0b
MT		 1587 if (update.left >= update.right || update.top >= update.bottom ||
1588 update.left < 0 || update.top < 0) {
511b13e2
AL		 1589 qxl_set_guest_bug(d,
1590 "QXL_IO_UPDATE_AREA: invalid area (%ux%u)x(%ux%u)\n",
1591 update.left, update.top, update.right, update.bottom);
9e5a25f1
MAL		 1592 if (update.left == update.right || update.top == update.bottom) {
1593 /* old drivers may provide empty area, keep going */
1594 qxl_clear_guest_bug(d);
1595 goto cancel_async;
1596 }
ccc2960d
DH		 1597 break;
1598 }
81fb6f15
AL		 1599 if (async == QXL_ASYNC) {
1600 cookie = qxl_cookie_new(QXL_COOKIE_TYPE_IO,
1601 QXL_IO_UPDATE_AREA_ASYNC);
1602 cookie->u.area = update;
1603 }
aee32bf3 1604 qxl_spice_update_area(d, d->ram->update_surface,
81fb6f15
AL		 1605 cookie ? &cookie->u.area : &update,
1606 NULL, 0, 0, async, cookie);
a19cbfb3
GH		 1607 break;
1608 }
1609 case QXL_IO_NOTIFY_CMD:
5c59d118 1610 qemu_spice_wakeup(&d->ssd);
a19cbfb3
GH		 1611 break;
1612 case QXL_IO_NOTIFY_CURSOR:
5c59d118 1613 qemu_spice_wakeup(&d->ssd);
a19cbfb3
GH		 1614 break;
1615 case QXL_IO_UPDATE_IRQ:
40010aea 1616 qxl_update_irq(d);
a19cbfb3
GH		 1617 break;
1618 case QXL_IO_NOTIFY_OOM:
a19cbfb3
GH		 1619 if (!SPICE_RING_IS_EMPTY(&d->ram->release_ring)) {
1620 break;
1621 }
1622 d->oom_running = 1;
aee32bf3 1623 qxl_spice_oom(d);
a19cbfb3
GH		 1624 d->oom_running = 0;
1625 break;
1626 case QXL_IO_SET_MODE:
a19cbfb3
GH		 1627 qxl_set_mode(d, val, 0);
1628 break;
1629 case QXL_IO_LOG:
1a1bc085 1630 trace_qxl_io_log(d->id, d->ram->log_buf);
a19cbfb3 1631 if (d->guestdebug) {
a680f7e7 1632 fprintf(stderr, "qxl/guest-%d: %" PRId64 ": %s", d->id,
bc72ad67 1633 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), d->ram->log_buf);
a19cbfb3
GH		 1634 }
1635 break;
1636 case QXL_IO_RESET:
a19cbfb3
GH		 1637 qxl_hard_reset(d, 0);
1638 break;
1639 case QXL_IO_MEMSLOT_ADD:
2bce0400 1640 if (val >= NUM_MEMSLOTS) {
0a530548 1641 qxl_set_guest_bug(d, "QXL_IO_MEMSLOT_ADD: val out of range");
2bce0400
GH		 1642 break;
1643 }
1644 if (d->guest_slots[val].active) {
0a530548
AL		 1645 qxl_set_guest_bug(d,
1646 "QXL_IO_MEMSLOT_ADD: memory slot already active");
2bce0400
GH		 1647 break;
1648 }
a19cbfb3 1649 d->guest_slots[val].slot = d->ram->mem_slot;
5ff4e36c 1650 qxl_add_memslot(d, val, 0, async);
a19cbfb3
GH		 1651 break;
1652 case QXL_IO_MEMSLOT_DEL:
2bce0400 1653 if (val >= NUM_MEMSLOTS) {
0a530548 1654 qxl_set_guest_bug(d, "QXL_IO_MEMSLOT_DEL: val out of range");
2bce0400
GH		 1655 break;
1656 }
a19cbfb3
GH		 1657 qxl_del_memslot(d, val);
1658 break;
1659 case QXL_IO_CREATE_PRIMARY:
2bce0400 1660 if (val != 0) {
0a530548 1661 qxl_set_guest_bug(d, "QXL_IO_CREATE_PRIMARY (async=%d): val != 0",
5ff4e36c
AL		 1662 async);
1663 goto cancel_async;
2bce0400 1664 }
a19cbfb3 1665 d->guest_primary.surface = d->ram->create_surface;
5ff4e36c 1666 qxl_create_guest_primary(d, 0, async);
a19cbfb3
GH		 1667 break;
1668 case QXL_IO_DESTROY_PRIMARY:
2bce0400 1669 if (val != 0) {
0a530548 1670 qxl_set_guest_bug(d, "QXL_IO_DESTROY_PRIMARY (async=%d): val != 0",
5ff4e36c
AL		 1671 async);
1672 goto cancel_async;
1673 }
5ff4e36c 1674 if (!qxl_destroy_primary(d, async)) {
c480bb7d
AL		 1675 trace_qxl_io_destroy_primary_ignored(d->id,
1676 qxl_mode_to_string(d->mode));
5ff4e36c 1677 goto cancel_async;
2bce0400 1678 }
a19cbfb3
GH		 1679 break;
1680 case QXL_IO_DESTROY_SURFACE_WAIT:
ddd8fdc7 1681 if (val >= d->ssd.num_surfaces) {
0a530548 1682 qxl_set_guest_bug(d, "QXL_IO_DESTROY_SURFACE (async=%d):"
5f8daf2e 1683 "%" PRIu64 " >= NUM_SURFACES", async, val);
5ff4e36c
AL		 1684 goto cancel_async;
1685 }
1686 qxl_spice_destroy_surface_wait(d, val, async);
a19cbfb3 1687 break;
3e16b9c5
AL		 1688 case QXL_IO_FLUSH_RELEASE: {
1689 QXLReleaseRing *ring = &d->ram->release_ring;
1690 if (ring->prod - ring->cons + 1 == ring->num_items) {
1691 fprintf(stderr,
1692 "ERROR: no flush, full release ring [p%d,%dc]\n",
1693 ring->prod, ring->cons);
1694 }
1695 qxl_push_free_res(d, 1 /* flush */);
3e16b9c5
AL		 1696 break;
1697 }
1698 case QXL_IO_FLUSH_SURFACES_ASYNC:
3e16b9c5
AL		 1699 qxl_spice_flush_surfaces_async(d);
1700 break;
a19cbfb3 1701 case QXL_IO_DESTROY_ALL_SURFACES:
5ff4e36c
AL		 1702 d->mode = QXL_MODE_UNDEFINED;
1703 qxl_spice_destroy_surfaces(d, async);
a19cbfb3 1704 break;
020af1c4
AL		 1705 case QXL_IO_MONITORS_CONFIG_ASYNC:
1706 qxl_spice_monitors_config_async(d, 0);
1707 break;
a19cbfb3 1708 default:
0a530548 1709 qxl_set_guest_bug(d, "%s: unexpected ioport=0x%x\n", __func__, io_port);
a19cbfb3 1710 }
5ff4e36c
AL		 1711 return;
1712cancel_async:
5ff4e36c
AL		 1713 if (async) {
1714 qxl_send_events(d, QXL_INTERRUPT_IO_CMD);
1715 qemu_mutex_lock(&d->async_lock);
1716 d->current_async = QXL_UNDEFINED_IO;
1717 qemu_mutex_unlock(&d->async_lock);
1718 }
a19cbfb3
GH		 1719}
1720
a8170e5e 1721static uint64_t ioport_read(void *opaque, hwaddr addr,
b1950430 1722 unsigned size)
a19cbfb3 1723{
917ae08c 1724 PCIQXLDevice *qxl = opaque;
a19cbfb3 1725
917ae08c 1726 trace_qxl_io_read_unexpected(qxl->id);
a19cbfb3
GH		 1727 return 0xff;
1728}
1729
b1950430
AK		 1730static const MemoryRegionOps qxl_io_ops = {
1731 .read = ioport_read,
1732 .write = ioport_write,
1733 .valid = {
1734 .min_access_size = 1,
1735 .max_access_size = 1,
1736 },
1737};
a19cbfb3 1738
4a46c99c 1739static void qxl_update_irq_bh(void *opaque)
a19cbfb3
GH		 1740{
1741 PCIQXLDevice *d = opaque;
40010aea 1742 qxl_update_irq(d);
a19cbfb3
GH		 1743}
1744
a19cbfb3
GH		 1745static void qxl_send_events(PCIQXLDevice *d, uint32_t events)
1746{
1747 uint32_t old_pending;
1748 uint32_t le_events = cpu_to_le32(events);
1749
917ae08c 1750 trace_qxl_send_events(d->id, events);
511aefb0
AL		 1751 if (!qemu_spice_display_is_running(&d->ssd)) {
1752 /* spice-server tracks guest running state and should not do this */
1753 fprintf(stderr, "%s: spice-server bug: guest stopped, ignoring\n",
1754 __func__);
1755 trace_qxl_send_events_vm_stopped(d->id, events);
1756 return;
1757 }
5444e768 1758 old_pending = atomic_fetch_or(&d->ram->int_pending, le_events);
a19cbfb3
GH		 1759 if ((old_pending & le_events) == le_events) {
1760 return;
1761 }
4a46c99c 1762 qemu_bh_schedule(d->update_irq);
a19cbfb3
GH		 1763}
1764
1765/* graphics console */
1766
1767static void qxl_hw_update(void *opaque)
1768{
1769 PCIQXLDevice *qxl = opaque;
a19cbfb3 1770
15162335 1771 qxl_render_update(qxl);
a19cbfb3
GH		 1772}
1773
e25139b3
YH		 1774static void qxl_dirty_surfaces(PCIQXLDevice *qxl)
1775{
c5825ac6 1776 uintptr_t vram_start;
e25139b3
YH		 1777 int i;
1778
2aa9e85c 1779 if (qxl->mode != QXL_MODE_NATIVE && qxl->mode != QXL_MODE_COMPAT) {
e25139b3
YH		 1780 return;
1781 }
1782
1783 /* dirty the primary surface */
1784 qxl_set_dirty(&qxl->vga.vram, qxl->shadow_rom.draw_area_offset,
1785 qxl->shadow_rom.surface0_area_size);
1786
c5825ac6 1787 vram_start = (uintptr_t)memory_region_get_ram_ptr(&qxl->vram_bar);
e25139b3
YH		 1788
1789 /* dirty the off-screen surfaces */
ddd8fdc7 1790 for (i = 0; i < qxl->ssd.num_surfaces; i++) {
e25139b3
YH		 1791 QXLSurfaceCmd *cmd;
1792 intptr_t surface_offset;
1793 int surface_size;
1794
1795 if (qxl->guest_surfaces.cmds[i] == 0) {
1796 continue;
1797 }
1798
1799 cmd = qxl_phys2virt(qxl, qxl->guest_surfaces.cmds[i],
1800 MEMSLOT_GROUP_GUEST);
fae2afb1 1801 assert(cmd);
e25139b3
YH		 1802 assert(cmd->type == QXL_SURFACE_CMD_CREATE);
1803 surface_offset = (intptr_t)qxl_phys2virt(qxl,
1804 cmd->u.surface_create.data,
1805 MEMSLOT_GROUP_GUEST);
fae2afb1 1806 assert(surface_offset);
e25139b3
YH		 1807 surface_offset -= vram_start;
1808 surface_size = cmd->u.surface_create.height *
1809 abs(cmd->u.surface_create.stride);
c480bb7d 1810 trace_qxl_surfaces_dirty(qxl->id, i, (int)surface_offset, surface_size);
e25139b3
YH		 1811 qxl_set_dirty(&qxl->vram_bar, surface_offset, surface_size);
1812 }
1813}
1814
1dfb4dd9
LC		 1815static void qxl_vm_change_state_handler(void *opaque, int running,
1816 RunState state)
a19cbfb3
GH		 1817{
1818 PCIQXLDevice *qxl = opaque;
a19cbfb3 1819
efbf2950
YH		 1820 if (running) {
1821 /*
1822 * if qxl_send_events was called from spice server context before
40010aea 1823 * migration ended, qxl_update_irq for these events might not have been
efbf2950
YH		 1824 * called
1825 */
40010aea 1826 qxl_update_irq(qxl);
e25139b3
YH		 1827 } else {
1828 /* make sure surfaces are saved before migration */
1829 qxl_dirty_surfaces(qxl);
a19cbfb3
GH		 1830 }
1831}
1832
1833/* display change listener */
1834
7c20b4a3 1835static void display_update(DisplayChangeListener *dcl,
7c20b4a3 1836 int x, int y, int w, int h)
a19cbfb3 1837{
c6c06853
GH		 1838 PCIQXLDevice *qxl = container_of(dcl, PCIQXLDevice, ssd.dcl);
1839
1840 if (qxl->mode == QXL_MODE_VGA) {
1841 qemu_spice_display_update(&qxl->ssd, x, y, w, h);
a19cbfb3
GH		 1842 }
1843}
1844
c12aeb86 1845static void display_switch(DisplayChangeListener *dcl,
c12aeb86 1846 struct DisplaySurface *surface)
a19cbfb3 1847{
c6c06853
GH		 1848 PCIQXLDevice *qxl = container_of(dcl, PCIQXLDevice, ssd.dcl);
1849
71874c17 1850 qxl->ssd.ds = surface;
c6c06853 1851 if (qxl->mode == QXL_MODE_VGA) {
c12aeb86 1852 qemu_spice_display_switch(&qxl->ssd, surface);
a19cbfb3
GH		 1853 }
1854}
1855
bc2ed970 1856static void display_refresh(DisplayChangeListener *dcl)
a19cbfb3 1857{
c6c06853
GH		 1858 PCIQXLDevice *qxl = container_of(dcl, PCIQXLDevice, ssd.dcl);
1859
1860 if (qxl->mode == QXL_MODE_VGA) {
1861 qemu_spice_display_refresh(&qxl->ssd);
a19cbfb3
GH		 1862 }
1863}
1864
7c20b4a3
GH		 1865static DisplayChangeListenerOps display_listener_ops = {
1866 .dpy_name = "spice/qxl",
a93a4a22 1867 .dpy_gfx_update = display_update,
c12aeb86 1868 .dpy_gfx_switch = display_switch,
7c20b4a3 1869 .dpy_refresh = display_refresh,
a19cbfb3
GH		 1870};
1871
13d1fd44 1872static void qxl_init_ramsize(PCIQXLDevice *qxl)
a974192c 1873{
13d1fd44
AL		 1874 /* vga mode framebuffer / primary surface (bar 0, first part) */
1875 if (qxl->vgamem_size_mb < 8) {
1876 qxl->vgamem_size_mb = 8;
1877 }
876d5163
RK		 1878 /* XXX: we round vgamem_size_mb up to a nearest power of two and it must be
1879 * less than vga_common_init()'s maximum on qxl->vga.vram_size (512 now).
1880 */
1881 if (qxl->vgamem_size_mb > 256) {
1882 qxl->vgamem_size_mb = 256;
1883 }
13d1fd44
AL		 1884 qxl->vgamem_size = qxl->vgamem_size_mb * 1024 * 1024;
1885
1886 /* vga ram (bar 0, total) */
017438ee
GH		 1887 if (qxl->ram_size_mb != -1) {
1888 qxl->vga.vram_size = qxl->ram_size_mb * 1024 * 1024;
1889 }
13d1fd44
AL		 1890 if (qxl->vga.vram_size < qxl->vgamem_size * 2) {
1891 qxl->vga.vram_size = qxl->vgamem_size * 2;
a974192c
GH		 1892 }
1893
6f2b175a
GH		 1894 /* vram32 (surfaces, 32bit, bar 1) */
1895 if (qxl->vram32_size_mb != -1) {
1896 qxl->vram32_size = qxl->vram32_size_mb * 1024 * 1024;
1897 }
1898 if (qxl->vram32_size < 4096) {
1899 qxl->vram32_size = 4096;
1900 }
1901
1902 /* vram (surfaces, 64bit, bar 4+5) */
017438ee
GH		 1903 if (qxl->vram_size_mb != -1) {
1904 qxl->vram_size = qxl->vram_size_mb * 1024 * 1024;
1905 }
6f2b175a
GH		 1906 if (qxl->vram_size < qxl->vram32_size) {
1907 qxl->vram_size = qxl->vram32_size;
a974192c 1908 }
6f2b175a 1909
a974192c 1910 if (qxl->revision == 1) {
6f2b175a 1911 qxl->vram32_size = 4096;
a974192c
GH		 1912 qxl->vram_size = 4096;
1913 }
bb7443f6
RK		 1914 qxl->vgamem_size = pow2ceil(qxl->vgamem_size);
1915 qxl->vga.vram_size = pow2ceil(qxl->vga.vram_size);
1916 qxl->vram32_size = pow2ceil(qxl->vram32_size);
1917 qxl->vram_size = pow2ceil(qxl->vram_size);
a974192c
GH		 1918}
1919
042a24db 1920static void qxl_realize_common(PCIQXLDevice *qxl, Error **errp)
a19cbfb3
GH		 1921{
1922 uint8_t* config = qxl->pci.config;
a19cbfb3
GH		 1923 uint32_t pci_device_rev;
1924 uint32_t io_size;
1925
1926 qxl->mode = QXL_MODE_UNDEFINED;
1927 qxl->generation = 1;
1928 qxl->num_memslots = NUM_MEMSLOTS;
14898cf6 1929 qemu_mutex_init(&qxl->track_lock);
5ff4e36c
AL		 1930 qemu_mutex_init(&qxl->async_lock);
1931 qxl->current_async = QXL_UNDEFINED_IO;
087e6a42 1932 qxl->guest_bug = 0;
a19cbfb3
GH		 1933
1934 switch (qxl->revision) {
1935 case 1: /* spice 0.4 -- qxl-1 */
a19cbfb3 1936 pci_device_rev = QXL_REVISION_STABLE_V04;
3f6297b9 1937 io_size = 8;
a19cbfb3
GH		 1938 break;
1939 case 2: /* spice 0.6 -- qxl-2 */
a19cbfb3 1940 pci_device_rev = QXL_REVISION_STABLE_V06;
3f6297b9 1941 io_size = 16;
a19cbfb3 1942 break;
9197a7c8 1943 case 3: /* qxl-3 */
020af1c4
AL		 1944 pci_device_rev = QXL_REVISION_STABLE_V10;
1945 io_size = 32; /* PCI region size must be pow2 */
1946 break;
020af1c4
AL		 1947 case 4: /* qxl-4 */
1948 pci_device_rev = QXL_REVISION_STABLE_V12;
bb7443f6 1949 io_size = pow2ceil(QXL_IO_RANGE_SIZE);
9197a7c8 1950 break;
36839d35 1951 default:
042a24db
MA		 1952 error_setg(errp, "Invalid revision %d for qxl device (max %d)",
1953 qxl->revision, QXL_DEFAULT_REVISION);
1954 return;
a19cbfb3
GH		 1955 }
1956
a19cbfb3
GH		 1957 pci_set_byte(&config[PCI_REVISION_ID], pci_device_rev);
1958 pci_set_byte(&config[PCI_INTERRUPT_PIN], 1);
1959
1960 qxl->rom_size = qxl_rom_size();
3eadad55 1961 memory_region_init_ram(&qxl->rom_bar, OBJECT(qxl), "qxl.vrom",
49946538 1962 qxl->rom_size, &error_abort);
c5705a77 1963 vmstate_register_ram(&qxl->rom_bar, &qxl->pci.qdev);
a19cbfb3
GH		 1964 init_qxl_rom(qxl);
1965 init_qxl_ram(qxl);
1966
ddd8fdc7 1967 qxl->guest_surfaces.cmds = g_new0(QXLPHYSICAL, qxl->ssd.num_surfaces);
3eadad55 1968 memory_region_init_ram(&qxl->vram_bar, OBJECT(qxl), "qxl.vram",
49946538 1969 qxl->vram_size, &error_abort);
c5705a77 1970 vmstate_register_ram(&qxl->vram_bar, &qxl->pci.qdev);
3eadad55
PB		 1971 memory_region_init_alias(&qxl->vram32_bar, OBJECT(qxl), "qxl.vram32",
1972 &qxl->vram_bar, 0, qxl->vram32_size);
a19cbfb3 1973
3eadad55 1974 memory_region_init_io(&qxl->io_bar, OBJECT(qxl), &qxl_io_ops, qxl,
b1950430
AK		 1975 "qxl-ioports", io_size);
1976 if (qxl->id == 0) {
1977 vga_dirty_log_start(&qxl->vga);
1978 }
bd8f2f5d 1979 memory_region_set_flush_coalesced(&qxl->io_bar);
b1950430
AK		 1980
1981
e824b2cc
AK		 1982 pci_register_bar(&qxl->pci, QXL_IO_RANGE_INDEX,
1983 PCI_BASE_ADDRESS_SPACE_IO, &qxl->io_bar);
a19cbfb3 1984
e824b2cc
AK		 1985 pci_register_bar(&qxl->pci, QXL_ROM_RANGE_INDEX,
1986 PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->rom_bar);
a19cbfb3 1987
e824b2cc
AK		 1988 pci_register_bar(&qxl->pci, QXL_RAM_RANGE_INDEX,
1989 PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->vga.vram);
a19cbfb3 1990
e824b2cc 1991 pci_register_bar(&qxl->pci, QXL_VRAM_RANGE_INDEX,
6f2b175a
GH		 1992 PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->vram32_bar);
1993
1994 if (qxl->vram32_size < qxl->vram_size) {
1995 /*
1996 * Make the 64bit vram bar show up only in case it is
1997 * configured to be larger than the 32bit vram bar.
1998 */
1999 pci_register_bar(&qxl->pci, QXL_VRAM64_RANGE_INDEX,
2000 PCI_BASE_ADDRESS_SPACE_MEMORY |
2001 PCI_BASE_ADDRESS_MEM_TYPE_64 |
2002 PCI_BASE_ADDRESS_MEM_PREFETCH,
2003 &qxl->vram_bar);
2004 }
2005
2006 /* print pci bar details */
2007 dprint(qxl, 1, "ram/%s: %d MB [region 0]\n",
2008 qxl->id == 0 ? "pri" : "sec",
2009 qxl->vga.vram_size / (1024*1024));
2010 dprint(qxl, 1, "vram/32: %d MB [region 1]\n",
2011 qxl->vram32_size / (1024*1024));
2012 dprint(qxl, 1, "vram/64: %d MB %s\n",
2013 qxl->vram_size / (1024*1024),
2014 qxl->vram32_size < qxl->vram_size ? "[region 4]" : "[unmapped]");
a19cbfb3
GH		 2015
2016 qxl->ssd.qxl.base.sif = &qxl_interface.base;
9fa03286 2017 if (qemu_spice_add_display_interface(&qxl->ssd.qxl, qxl->vga.con) != 0) {
042a24db
MA		 2018 error_setg(errp, "qxl interface %d.%d not supported by spice-server",
2019 SPICE_INTERFACE_QXL_MAJOR, SPICE_INTERFACE_QXL_MINOR);
2020 return;
e25a0651 2021 }
a19cbfb3
GH		 2022 qemu_add_vm_change_state_handler(qxl_vm_change_state_handler, qxl);
2023
4a46c99c 2024 qxl->update_irq = qemu_bh_new(qxl_update_irq_bh, qxl);
a19cbfb3
GH		 2025 qxl_reset_state(qxl);
2026
81fb6f15 2027 qxl->update_area_bh = qemu_bh_new(qxl_render_update_area_bh, qxl);
0b2824e5 2028 qxl->ssd.cursor_bh = qemu_bh_new(qemu_spice_cursor_refresh_bh, &qxl->ssd);
a19cbfb3
GH		 2029}
2030
042a24db 2031static void qxl_realize_primary(PCIDevice *dev, Error **errp)
a19cbfb3 2032{
c69f6c7d 2033 PCIQXLDevice *qxl = PCI_QXL(dev);
a19cbfb3 2034 VGACommonState *vga = &qxl->vga;
042a24db 2035 Error *local_err = NULL;
a19cbfb3
GH		 2036
2037 qxl->id = 0;
13d1fd44 2038 qxl_init_ramsize(qxl);
54a85d46 2039 vga->vbe_size = qxl->vgamem_size;
4a1e244e 2040 vga->vram_size_mb = qxl->vga.vram_size >> 20;
e2bbfc8e 2041 vga_common_init(vga, OBJECT(dev), true);
712f0cc7
PB		 2042 vga_init(vga, OBJECT(dev),
2043 pci_address_space(dev), pci_address_space_io(dev), false);
848696bf 2044 portio_list_init(&qxl->vga_port_list, OBJECT(dev), qxl_vga_portio_list,
db10ca90 2045 vga, "vga");
848696bf
KB		 2046 portio_list_set_flush_coalesced(&qxl->vga_port_list);
2047 portio_list_add(&qxl->vga_port_list, pci_address_space_io(dev), 0x3b0);
a19cbfb3 2048
5643706a 2049 vga->con = graphic_console_init(DEVICE(dev), 0, &qxl_ops, qxl);
c78f7137 2050 qemu_spice_display_init_common(&qxl->ssd);
a19cbfb3 2051
042a24db
MA		 2052 qxl_realize_common(qxl, &local_err);
2053 if (local_err) {
2054 error_propagate(errp, local_err);
2055 return;
bdd4df33
GH		 2056 }
2057
7c20b4a3 2058 qxl->ssd.dcl.ops = &display_listener_ops;
284d1c6b 2059 qxl->ssd.dcl.con = vga->con;
5209089f 2060 register_displaychangelistener(&qxl->ssd.dcl);
a19cbfb3
GH		 2061}
2062
042a24db 2063static void qxl_realize_secondary(PCIDevice *dev, Error **errp)
a19cbfb3
GH		 2064{
2065 static int device_id = 1;
c69f6c7d 2066 PCIQXLDevice *qxl = PCI_QXL(dev);
a19cbfb3
GH		 2067
2068 qxl->id = device_id++;
13d1fd44 2069 qxl_init_ramsize(qxl);
3eadad55 2070 memory_region_init_ram(&qxl->vga.vram, OBJECT(dev), "qxl.vgavram",
49946538 2071 qxl->vga.vram_size, &error_abort);
c5705a77 2072 vmstate_register_ram(&qxl->vga.vram, &qxl->pci.qdev);
b1950430 2073 qxl->vga.vram_ptr = memory_region_get_ram_ptr(&qxl->vga.vram);
5643706a 2074 qxl->vga.con = graphic_console_init(DEVICE(dev), 0, &qxl_ops, qxl);
a19cbfb3 2075
042a24db 2076 qxl_realize_common(qxl, errp);
a19cbfb3
GH		 2077}
2078
2079static void qxl_pre_save(void *opaque)
2080{
2081 PCIQXLDevice* d = opaque;
2082 uint8_t *ram_start = d->vga.vram_ptr;
2083
c480bb7d 2084 trace_qxl_pre_save(d->id);
a19cbfb3
GH		 2085 if (d->last_release == NULL) {
2086 d->last_release_offset = 0;
2087 } else {
2088 d->last_release_offset = (uint8_t *)d->last_release - ram_start;
2089 }
2090 assert(d->last_release_offset < d->vga.vram_size);
2091}
2092
2093static int qxl_pre_load(void *opaque)
2094{
2095 PCIQXLDevice* d = opaque;
2096
c480bb7d 2097 trace_qxl_pre_load(d->id);
a19cbfb3
GH		 2098 qxl_hard_reset(d, 1);
2099 qxl_exit_vga_mode(d);
a19cbfb3
GH		 2100 return 0;
2101}
2102
54825d2e
AL		 2103static void qxl_create_memslots(PCIQXLDevice *d)
2104{
2105 int i;
2106
2107 for (i = 0; i < NUM_MEMSLOTS; i++) {
2108 if (!d->guest_slots[i].active) {
2109 continue;
2110 }
54825d2e
AL		 2111 qxl_add_memslot(d, i, 0, QXL_SYNC);
2112 }
2113}
2114
a19cbfb3
GH		 2115static int qxl_post_load(void *opaque, int version)
2116{
2117 PCIQXLDevice* d = opaque;
2118 uint8_t *ram_start = d->vga.vram_ptr;
2119 QXLCommandExt *cmds;
54825d2e 2120 int in, out, newmode;
a19cbfb3 2121
a19cbfb3
GH		 2122 assert(d->last_release_offset < d->vga.vram_size);
2123 if (d->last_release_offset == 0) {
2124 d->last_release = NULL;
2125 } else {
2126 d->last_release = (QXLReleaseInfo *)(ram_start + d->last_release_offset);
2127 }
2128
2129 d->modes = (QXLModes*)((uint8_t*)d->rom + d->rom->modes_offset);
2130
c480bb7d 2131 trace_qxl_post_load(d->id, qxl_mode_to_string(d->mode));
a19cbfb3
GH		 2132 newmode = d->mode;
2133 d->mode = QXL_MODE_UNDEFINED;
54825d2e 2134
a19cbfb3
GH		 2135 switch (newmode) {
2136 case QXL_MODE_UNDEFINED:
fa98efe9 2137 qxl_create_memslots(d);
a19cbfb3
GH		 2138 break;
2139 case QXL_MODE_VGA:
54825d2e 2140 qxl_create_memslots(d);
a19cbfb3
GH		 2141 qxl_enter_vga_mode(d);
2142 break;
2143 case QXL_MODE_NATIVE:
54825d2e 2144 qxl_create_memslots(d);
5ff4e36c 2145 qxl_create_guest_primary(d, 1, QXL_SYNC);
a19cbfb3
GH		 2146
2147 /* replay surface-create and cursor-set commands */
ddd8fdc7
GH		 2148 cmds = g_malloc0(sizeof(QXLCommandExt) * (d->ssd.num_surfaces + 1));
2149 for (in = 0, out = 0; in < d->ssd.num_surfaces; in++) {
a19cbfb3
GH		 2150 if (d->guest_surfaces.cmds[in] == 0) {
2151 continue;
2152 }
2153 cmds[out].cmd.data = d->guest_surfaces.cmds[in];
2154 cmds[out].cmd.type = QXL_CMD_SURFACE;
2155 cmds[out].group_id = MEMSLOT_GROUP_GUEST;
2156 out++;
2157 }
30f6da66
YH		 2158 if (d->guest_cursor) {
2159 cmds[out].cmd.data = d->guest_cursor;
2160 cmds[out].cmd.type = QXL_CMD_CURSOR;
2161 cmds[out].group_id = MEMSLOT_GROUP_GUEST;
2162 out++;
2163 }
aee32bf3 2164 qxl_spice_loadvm_commands(d, cmds, out);
7267c094 2165 g_free(cmds);
020af1c4
AL		 2166 if (d->guest_monitors_config) {
2167 qxl_spice_monitors_config_async(d, 1);
2168 }
a19cbfb3
GH		 2169 break;
2170 case QXL_MODE_COMPAT:
54825d2e
AL		 2171 /* note: no need to call qxl_create_memslots, qxl_set_mode
2172 * creates the mem slot. */
a19cbfb3
GH		 2173 qxl_set_mode(d, d->shadow_rom.mode, 1);
2174 break;
2175 }
a19cbfb3
GH		 2176 return 0;
2177}
2178
b67737a6 2179#define QXL_SAVE_VERSION 21
a19cbfb3 2180
020af1c4
AL		 2181static bool qxl_monitors_config_needed(void *opaque)
2182{
2183 PCIQXLDevice *qxl = opaque;
2184
2185 return qxl->guest_monitors_config != 0;
2186}
2187
2188
a19cbfb3
GH		 2189static VMStateDescription qxl_memslot = {
2190 .name = "qxl-memslot",
2191 .version_id = QXL_SAVE_VERSION,
2192 .minimum_version_id = QXL_SAVE_VERSION,
2193 .fields = (VMStateField[]) {
2194 VMSTATE_UINT64(slot.mem_start, struct guest_slots),
2195 VMSTATE_UINT64(slot.mem_end, struct guest_slots),
2196 VMSTATE_UINT32(active, struct guest_slots),
2197 VMSTATE_END_OF_LIST()
2198 }
2199};
2200
2201static VMStateDescription qxl_surface = {
2202 .name = "qxl-surface",
2203 .version_id = QXL_SAVE_VERSION,
2204 .minimum_version_id = QXL_SAVE_VERSION,
2205 .fields = (VMStateField[]) {
2206 VMSTATE_UINT32(width, QXLSurfaceCreate),
2207 VMSTATE_UINT32(height, QXLSurfaceCreate),
2208 VMSTATE_INT32(stride, QXLSurfaceCreate),
2209 VMSTATE_UINT32(format, QXLSurfaceCreate),
2210 VMSTATE_UINT32(position, QXLSurfaceCreate),
2211 VMSTATE_UINT32(mouse_mode, QXLSurfaceCreate),
2212 VMSTATE_UINT32(flags, QXLSurfaceCreate),
2213 VMSTATE_UINT32(type, QXLSurfaceCreate),
2214 VMSTATE_UINT64(mem, QXLSurfaceCreate),
2215 VMSTATE_END_OF_LIST()
2216 }
2217};
2218
020af1c4
AL		 2219static VMStateDescription qxl_vmstate_monitors_config = {
2220 .name = "qxl/monitors-config",
2221 .version_id = 1,
2222 .minimum_version_id = 1,
5cd8cada 2223 .needed = qxl_monitors_config_needed,
020af1c4
AL		 2224 .fields = (VMStateField[]) {
2225 VMSTATE_UINT64(guest_monitors_config, PCIQXLDevice),
2226 VMSTATE_END_OF_LIST()
2227 },
2228};
2229
a19cbfb3
GH		 2230static VMStateDescription qxl_vmstate = {
2231 .name = "qxl",
2232 .version_id = QXL_SAVE_VERSION,
2233 .minimum_version_id = QXL_SAVE_VERSION,
2234 .pre_save = qxl_pre_save,
2235 .pre_load = qxl_pre_load,
2236 .post_load = qxl_post_load,
020af1c4 2237 .fields = (VMStateField[]) {
a19cbfb3
GH		 2238 VMSTATE_PCI_DEVICE(pci, PCIQXLDevice),
2239 VMSTATE_STRUCT(vga, PCIQXLDevice, 0, vmstate_vga_common, VGACommonState),
2240 VMSTATE_UINT32(shadow_rom.mode, PCIQXLDevice),
2241 VMSTATE_UINT32(num_free_res, PCIQXLDevice),
2242 VMSTATE_UINT32(last_release_offset, PCIQXLDevice),
2243 VMSTATE_UINT32(mode, PCIQXLDevice),
2244 VMSTATE_UINT32(ssd.unique, PCIQXLDevice),
b67737a6
GH		 2245 VMSTATE_INT32_EQUAL(num_memslots, PCIQXLDevice),
2246 VMSTATE_STRUCT_ARRAY(guest_slots, PCIQXLDevice, NUM_MEMSLOTS, 0,
2247 qxl_memslot, struct guest_slots),
2248 VMSTATE_STRUCT(guest_primary.surface, PCIQXLDevice, 0,
2249 qxl_surface, QXLSurfaceCreate),
ddd8fdc7
GH		 2250 VMSTATE_INT32_EQUAL(ssd.num_surfaces, PCIQXLDevice),
2251 VMSTATE_VARRAY_INT32(guest_surfaces.cmds, PCIQXLDevice,
2252 ssd.num_surfaces, 0,
2253 vmstate_info_uint64, uint64_t),
b67737a6 2254 VMSTATE_UINT64(guest_cursor, PCIQXLDevice),
a19cbfb3
GH		 2255 VMSTATE_END_OF_LIST()
2256 },
5cd8cada
JQ		 2257 .subsections = (const VMStateDescription*[]) {
2258 &qxl_vmstate_monitors_config,
2259 NULL
020af1c4 2260 }
a19cbfb3
GH		 2261};
2262
78e60ba5
GH		 2263static Property qxl_properties[] = {
2264 DEFINE_PROP_UINT32("ram_size", PCIQXLDevice, vga.vram_size,
2265 64 * 1024 * 1024),
6f2b175a 2266 DEFINE_PROP_UINT32("vram_size", PCIQXLDevice, vram32_size,
78e60ba5
GH		 2267 64 * 1024 * 1024),
2268 DEFINE_PROP_UINT32("revision", PCIQXLDevice, revision,
2269 QXL_DEFAULT_REVISION),
2270 DEFINE_PROP_UINT32("debug", PCIQXLDevice, debug, 0),
2271 DEFINE_PROP_UINT32("guestdebug", PCIQXLDevice, guestdebug, 0),
2272 DEFINE_PROP_UINT32("cmdlog", PCIQXLDevice, cmdlog, 0),
017438ee 2273 DEFINE_PROP_UINT32("ram_size_mb", PCIQXLDevice, ram_size_mb, -1),
79ce3567
AL		 2274 DEFINE_PROP_UINT32("vram_size_mb", PCIQXLDevice, vram32_size_mb, -1),
2275 DEFINE_PROP_UINT32("vram64_size_mb", PCIQXLDevice, vram_size_mb, -1),
9e56edcf 2276 DEFINE_PROP_UINT32("vgamem_mb", PCIQXLDevice, vgamem_size_mb, 16),
ddd8fdc7 2277 DEFINE_PROP_INT32("surfaces", PCIQXLDevice, ssd.num_surfaces, 1024),
78e60ba5
GH		 2278 DEFINE_PROP_END_OF_LIST(),
2279};
2280
c69f6c7d 2281static void qxl_pci_class_init(ObjectClass *klass, void *data)
40021f08 2282{
39bffca2 2283 DeviceClass *dc = DEVICE_CLASS(klass);
40021f08
AL		 2284 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
2285
40021f08
AL		 2286 k->vendor_id = REDHAT_PCI_VENDOR_ID;
2287 k->device_id = QXL_DEVICE_ID_STABLE;
125ee0ed 2288 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
39bffca2
AL		 2289 dc->reset = qxl_reset_handler;
2290 dc->vmsd = &qxl_vmstate;
2291 dc->props = qxl_properties;
c69f6c7d
GA		 2292}
2293
2294static const TypeInfo qxl_pci_type_info = {
2295 .name = TYPE_PCI_QXL,
2296 .parent = TYPE_PCI_DEVICE,
2297 .instance_size = sizeof(PCIQXLDevice),
2298 .abstract = true,
2299 .class_init = qxl_pci_class_init,
2300};
2301
2302static void qxl_primary_class_init(ObjectClass *klass, void *data)
2303{
2304 DeviceClass *dc = DEVICE_CLASS(klass);
2305 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
2306
2307 k->realize = qxl_realize_primary;
2308 k->romfile = "vgabios-qxl.bin";
2309 k->class_id = PCI_CLASS_DISPLAY_VGA;
2310 dc->desc = "Spice QXL GPU (primary, vga compatible)";
2897ae02 2311 dc->hotpluggable = false;
40021f08
AL		 2312}
2313
8c43a6f0 2314static const TypeInfo qxl_primary_info = {
39bffca2 2315 .name = "qxl-vga",
c69f6c7d 2316 .parent = TYPE_PCI_QXL,
39bffca2 2317 .class_init = qxl_primary_class_init,
a19cbfb3
GH		 2318};
2319
40021f08
AL		 2320static void qxl_secondary_class_init(ObjectClass *klass, void *data)
2321{
39bffca2 2322 DeviceClass *dc = DEVICE_CLASS(klass);
40021f08
AL		 2323 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
2324
042a24db 2325 k->realize = qxl_realize_secondary;
40021f08 2326 k->class_id = PCI_CLASS_DISPLAY_OTHER;
39bffca2 2327 dc->desc = "Spice QXL GPU (secondary)";
40021f08
AL		 2328}
2329
8c43a6f0 2330static const TypeInfo qxl_secondary_info = {
39bffca2 2331 .name = "qxl",
c69f6c7d 2332 .parent = TYPE_PCI_QXL,
39bffca2 2333 .class_init = qxl_secondary_class_init,
a19cbfb3
GH		 2334};
2335
83f7d43a 2336static void qxl_register_types(void)
a19cbfb3 2337{
c69f6c7d 2338 type_register_static(&qxl_pci_type_info);
39bffca2
AL		 2339 type_register_static(&qxl_primary_info);
2340 type_register_static(&qxl_secondary_info);
a19cbfb3
GH		 2341}
2342
83f7d43a 2343type_init(qxl_register_types)
Empty description
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