]> Git Repo - qemu.git/blame - hw/arm/virt.c
fw_cfg: Refactor extra pci roots addition
[qemu.git] / hw / arm / virt.c
CommitLineData
f5fdcd6e
PM
1/*
2 * ARM mach-virt emulation
3 *
4 * Copyright (c) 2013 Linaro Limited
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
17 *
18 * Emulate a virtual board which works by passing Linux all the information
19 * it needs about what devices are present via the device tree.
20 * There are some restrictions about what we can do here:
21 * + we can only present devices whose Linux drivers will work based
22 * purely on the device tree with no platform data at all
23 * + we want to present a very stripped-down minimalist platform,
24 * both because this reduces the security attack surface from the guest
25 * and also because it reduces our exposure to being broken when
26 * the kernel updates its device tree bindings and requires further
27 * information in a device binding that we aren't providing.
28 * This is essentially the same approach kvmtool uses.
29 */
30
12b16722 31#include "qemu/osdep.h"
a8d25326 32#include "qemu-common.h"
350a9c9e 33#include "qemu/units.h"
e0561e60 34#include "qemu/option.h"
70e89132 35#include "monitor/qdev.h"
da34e65c 36#include "qapi/error.h"
f5fdcd6e 37#include "hw/sysbus.h"
12e9493d 38#include "hw/boards.h"
12ec8bd5 39#include "hw/arm/boot.h"
f5fdcd6e 40#include "hw/arm/primecell.h"
afe0b380 41#include "hw/arm/virt.h"
81c7db72 42#include "hw/block/flash.h"
6f2062b9
EH
43#include "hw/vfio/vfio-calxeda-xgmac.h"
44#include "hw/vfio/vfio-amd-xgbe.h"
94692dcd 45#include "hw/display/ramfb.h"
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46#include "net/net.h"
47#include "sysemu/device_tree.h"
9695200a 48#include "sysemu/numa.h"
54d31236 49#include "sysemu/runstate.h"
f5fdcd6e 50#include "sysemu/sysemu.h"
c294ac32 51#include "sysemu/tpm.h"
f5fdcd6e 52#include "sysemu/kvm.h"
acf82361 53#include "hw/loader.h"
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PM
54#include "exec/address-spaces.h"
55#include "qemu/bitops.h"
56#include "qemu/error-report.h"
0b8fa32f 57#include "qemu/module.h"
4ab29b82 58#include "hw/pci-host/gpex.h"
70e89132 59#include "hw/virtio/virtio-pci.h"
5f7a5a0e
EA
60#include "hw/arm/sysbus-fdt.h"
61#include "hw/platform-bus.h"
a27bd6c7 62#include "hw/qdev-properties.h"
decf4f80 63#include "hw/arm/fdt.h"
95eb49c8
AJ
64#include "hw/intc/arm_gic.h"
65#include "hw/intc/arm_gicv3_common.h"
64552b6b 66#include "hw/irq.h"
e6fbcbc4 67#include "kvm_arm.h"
a2eb5c0c 68#include "hw/firmware/smbios.h"
b92ad394 69#include "qapi/visitor.h"
17e89077 70#include "qapi/qapi-visit-common.h"
3e6ebb64 71#include "standard-headers/linux/input.h"
584105ea 72#include "hw/arm/smmuv3.h"
957e32cf 73#include "hw/acpi/acpi.h"
2ba956cc 74#include "target/arm/internals.h"
1f283ae1
EA
75#include "hw/mem/pc-dimm.h"
76#include "hw/mem/nvdimm.h"
cff51ac9 77#include "hw/acpi/generic_event_device.h"
70e89132 78#include "hw/virtio/virtio-iommu.h"
d8f6d15f 79#include "hw/char/pl011.h"
60592cfe 80#include "qemu/guest-random.h"
f5fdcd6e 81
3356ebce 82#define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \
ab093c3c
AJ
83 static void virt_##major##_##minor##_class_init(ObjectClass *oc, \
84 void *data) \
85 { \
86 MachineClass *mc = MACHINE_CLASS(oc); \
87 virt_machine_##major##_##minor##_options(mc); \
88 mc->desc = "QEMU " # major "." # minor " ARM Virtual Machine"; \
3356ebce
AJ
89 if (latest) { \
90 mc->alias = "virt"; \
91 } \
ab093c3c
AJ
92 } \
93 static const TypeInfo machvirt_##major##_##minor##_info = { \
94 .name = MACHINE_TYPE_NAME("virt-" # major "." # minor), \
95 .parent = TYPE_VIRT_MACHINE, \
ab093c3c
AJ
96 .class_init = virt_##major##_##minor##_class_init, \
97 }; \
98 static void machvirt_machine_##major##_##minor##_init(void) \
99 { \
100 type_register_static(&machvirt_##major##_##minor##_info); \
101 } \
102 type_init(machvirt_machine_##major##_##minor##_init);
103
3356ebce
AJ
104#define DEFINE_VIRT_MACHINE_AS_LATEST(major, minor) \
105 DEFINE_VIRT_MACHINE_LATEST(major, minor, true)
106#define DEFINE_VIRT_MACHINE(major, minor) \
107 DEFINE_VIRT_MACHINE_LATEST(major, minor, false)
108
ab093c3c 109
a72d4363
AJ
110/* Number of external interrupt lines to configure the GIC with */
111#define NUM_IRQS 256
112
113#define PLATFORM_BUS_NUM_IRQS 64
114
50a17297 115/* Legacy RAM limit in GB (< version 4.0) */
957e32cf
EA
116#define LEGACY_RAMLIMIT_GB 255
117#define LEGACY_RAMLIMIT_BYTES (LEGACY_RAMLIMIT_GB * GiB)
71c27684 118
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119/* Addresses and sizes of our components.
120 * 0..128MB is space for a flash device so we can run bootrom code such as UEFI.
121 * 128MB..256MB is used for miscellaneous device I/O.
122 * 256MB..1GB is reserved for possible future PCI support (ie where the
123 * PCI memory window will go if we add a PCI host controller).
124 * 1GB and up is RAM (which may happily spill over into the
125 * high memory region beyond 4GB).
126 * This represents a compromise between how much RAM can be given to
127 * a 32 bit VM and leaving space for expansion and in particular for PCI.
6e411af9
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128 * Note that devices should generally be placed at multiples of 0x10000,
129 * to accommodate guests using 64K pages.
f5fdcd6e 130 */
350a9c9e 131static const MemMapEntry base_memmap[] = {
f5fdcd6e 132 /* Space up to 0x8000000 is reserved for a boot ROM */
94edf02c
EA
133 [VIRT_FLASH] = { 0, 0x08000000 },
134 [VIRT_CPUPERIPHS] = { 0x08000000, 0x00020000 },
f5fdcd6e 135 /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */
94edf02c
EA
136 [VIRT_GIC_DIST] = { 0x08000000, 0x00010000 },
137 [VIRT_GIC_CPU] = { 0x08010000, 0x00010000 },
138 [VIRT_GIC_V2M] = { 0x08020000, 0x00001000 },
55ef3233
LM
139 [VIRT_GIC_HYP] = { 0x08030000, 0x00010000 },
140 [VIRT_GIC_VCPU] = { 0x08040000, 0x00010000 },
b92ad394
PF
141 /* The space in between here is reserved for GICv3 CPU/vCPU/HYP */
142 [VIRT_GIC_ITS] = { 0x08080000, 0x00020000 },
143 /* This redistributor space allows up to 2*64kB*123 CPUs */
144 [VIRT_GIC_REDIST] = { 0x080A0000, 0x00F60000 },
94edf02c
EA
145 [VIRT_UART] = { 0x09000000, 0x00001000 },
146 [VIRT_RTC] = { 0x09010000, 0x00001000 },
0b341a85 147 [VIRT_FW_CFG] = { 0x09020000, 0x00000018 },
b0a3721e 148 [VIRT_GPIO] = { 0x09030000, 0x00001000 },
3df708eb 149 [VIRT_SECURE_UART] = { 0x09040000, 0x00001000 },
584105ea 150 [VIRT_SMMU] = { 0x09050000, 0x00020000 },
cff51ac9
SK
151 [VIRT_PCDIMM_ACPI] = { 0x09070000, MEMORY_HOTPLUG_IO_LEN },
152 [VIRT_ACPI_GED] = { 0x09080000, ACPI_GED_EVT_SEL_LEN },
b5a60bee 153 [VIRT_NVDIMM_ACPI] = { 0x09090000, NVDIMM_ACPI_IO_LEN},
68970d1e 154 [VIRT_PVTIME] = { 0x090a0000, 0x00010000 },
94edf02c 155 [VIRT_MMIO] = { 0x0a000000, 0x00000200 },
f5fdcd6e 156 /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */
94edf02c 157 [VIRT_PLATFORM_BUS] = { 0x0c000000, 0x02000000 },
83ec1923 158 [VIRT_SECURE_MEM] = { 0x0e000000, 0x01000000 },
94edf02c
EA
159 [VIRT_PCIE_MMIO] = { 0x10000000, 0x2eff0000 },
160 [VIRT_PCIE_PIO] = { 0x3eff0000, 0x00010000 },
161 [VIRT_PCIE_ECAM] = { 0x3f000000, 0x01000000 },
957e32cf
EA
162 /* Actual RAM size depends on initial RAM and device memory settings */
163 [VIRT_MEM] = { GiB, LEGACY_RAMLIMIT_BYTES },
350a9c9e
EA
164};
165
166/*
167 * Highmem IO Regions: This memory map is floating, located after the RAM.
168 * Each MemMapEntry base (GPA) will be dynamically computed, depending on the
169 * top of the RAM, so that its base get the same alignment as the size,
170 * ie. a 512GiB entry will be aligned on a 512GiB boundary. If there is
171 * less than 256GiB of RAM, the floating area starts at the 256GiB mark.
172 * Note the extended_memmap is sized so that it eventually also includes the
173 * base_memmap entries (VIRT_HIGH_GIC_REDIST2 index is greater than the last
174 * index of base_memmap).
175 */
176static MemMapEntry extended_memmap[] = {
f90747c4 177 /* Additional 64 MB redist region (can contain up to 512 redistributors) */
350a9c9e
EA
178 [VIRT_HIGH_GIC_REDIST2] = { 0x0, 64 * MiB },
179 [VIRT_HIGH_PCIE_ECAM] = { 0x0, 256 * MiB },
180 /* Second PCIe window */
181 [VIRT_HIGH_PCIE_MMIO] = { 0x0, 512 * GiB },
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PM
182};
183
184static const int a15irqmap[] = {
185 [VIRT_UART] = 1,
6e411af9 186 [VIRT_RTC] = 2,
4ab29b82 187 [VIRT_PCIE] = 3, /* ... to 6 */
b0a3721e 188 [VIRT_GPIO] = 7,
3df708eb 189 [VIRT_SECURE_UART] = 8,
cff51ac9 190 [VIRT_ACPI_GED] = 9,
f5fdcd6e 191 [VIRT_MMIO] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */
bd204e63 192 [VIRT_GIC_V2M] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */
584105ea 193 [VIRT_SMMU] = 74, /* ...to 74 + NUM_SMMU_IRQS - 1 */
5f7a5a0e 194 [VIRT_PLATFORM_BUS] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */
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195};
196
9ac4ef77 197static const char *valid_cpus[] = {
4414942e 198 ARM_CPU_TYPE_NAME("cortex-a7"),
ba1ba5cc
IM
199 ARM_CPU_TYPE_NAME("cortex-a15"),
200 ARM_CPU_TYPE_NAME("cortex-a53"),
201 ARM_CPU_TYPE_NAME("cortex-a57"),
2264faa5 202 ARM_CPU_TYPE_NAME("cortex-a72"),
ba1ba5cc 203 ARM_CPU_TYPE_NAME("host"),
9076ddb3 204 ARM_CPU_TYPE_NAME("max"),
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205};
206
ba1ba5cc 207static bool cpu_type_valid(const char *cpu)
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208{
209 int i;
210
9ac4ef77
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211 for (i = 0; i < ARRAY_SIZE(valid_cpus); i++) {
212 if (strcmp(cpu, valid_cpus[i]) == 0) {
213 return true;
f5fdcd6e
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214 }
215 }
9ac4ef77 216 return false;
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217}
218
60592cfe
JF
219static void create_kaslr_seed(VirtMachineState *vms, const char *node)
220{
60592cfe
JF
221 uint64_t seed;
222
9261ef5e 223 if (qemu_guest_getrandom(&seed, sizeof(seed), NULL)) {
60592cfe
JF
224 return;
225 }
226 qemu_fdt_setprop_u64(vms->fdt, node, "kaslr-seed", seed);
227}
228
c8ef2bda 229static void create_fdt(VirtMachineState *vms)
f5fdcd6e 230{
aa570207
TX
231 MachineState *ms = MACHINE(vms);
232 int nb_numa_nodes = ms->numa_state->num_nodes;
c8ef2bda 233 void *fdt = create_device_tree(&vms->fdt_size);
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234
235 if (!fdt) {
236 error_report("create_device_tree() failed");
237 exit(1);
238 }
239
c8ef2bda 240 vms->fdt = fdt;
f5fdcd6e
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241
242 /* Header */
5a4348d1
PC
243 qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,dummy-virt");
244 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
245 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
f5fdcd6e 246
e2eb3d29 247 /* /chosen must exist for load_dtb to fill in necessary properties later */
5a4348d1 248 qemu_fdt_add_subnode(fdt, "/chosen");
60592cfe 249 create_kaslr_seed(vms, "/chosen");
f5fdcd6e 250
ef6a5c71
JF
251 if (vms->secure) {
252 qemu_fdt_add_subnode(fdt, "/secure-chosen");
60592cfe 253 create_kaslr_seed(vms, "/secure-chosen");
ef6a5c71
JF
254 }
255
f5fdcd6e
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256 /* Clock node, for the benefit of the UART. The kernel device tree
257 * binding documentation claims the PL011 node clock properties are
258 * optional but in practice if you omit them the kernel refuses to
259 * probe for the device.
260 */
c8ef2bda 261 vms->clock_phandle = qemu_fdt_alloc_phandle(fdt);
5a4348d1
PC
262 qemu_fdt_add_subnode(fdt, "/apb-pclk");
263 qemu_fdt_setprop_string(fdt, "/apb-pclk", "compatible", "fixed-clock");
264 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "#clock-cells", 0x0);
265 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "clock-frequency", 24000000);
266 qemu_fdt_setprop_string(fdt, "/apb-pclk", "clock-output-names",
f5fdcd6e 267 "clk24mhz");
c8ef2bda 268 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "phandle", vms->clock_phandle);
f5fdcd6e 269
118154b7 270 if (nb_numa_nodes > 0 && ms->numa_state->have_numa_distance) {
c7637c04
AJ
271 int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t);
272 uint32_t *matrix = g_malloc0(size);
273 int idx, i, j;
274
275 for (i = 0; i < nb_numa_nodes; i++) {
276 for (j = 0; j < nb_numa_nodes; j++) {
277 idx = (i * nb_numa_nodes + j) * 3;
278 matrix[idx + 0] = cpu_to_be32(i);
279 matrix[idx + 1] = cpu_to_be32(j);
7e721e7b
TX
280 matrix[idx + 2] =
281 cpu_to_be32(ms->numa_state->nodes[i].distance[j]);
c7637c04
AJ
282 }
283 }
284
285 qemu_fdt_add_subnode(fdt, "/distance-map");
286 qemu_fdt_setprop_string(fdt, "/distance-map", "compatible",
287 "numa-distance-map-v1");
288 qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix",
289 matrix, size);
290 g_free(matrix);
291 }
06955739
PS
292}
293
055a7f2b 294static void fdt_add_timer_nodes(const VirtMachineState *vms)
f5fdcd6e 295{
156bc9a5
PM
296 /* On real hardware these interrupts are level-triggered.
297 * On KVM they were edge-triggered before host kernel version 4.4,
298 * and level-triggered afterwards.
299 * On emulated QEMU they are level-triggered.
300 *
301 * Getting the DTB info about them wrong is awkward for some
302 * guest kernels:
303 * pre-4.8 ignore the DT and leave the interrupt configured
304 * with whatever the GIC reset value (or the bootloader) left it at
305 * 4.8 before rc6 honour the incorrect data by programming it back
306 * into the GIC, causing problems
307 * 4.8rc6 and later ignore the DT and always write "level triggered"
308 * into the GIC
309 *
310 * For backwards-compatibility, virt-2.8 and earlier will continue
311 * to say these are edge-triggered, but later machines will report
312 * the correct information.
f5fdcd6e 313 */
b32a9509 314 ARMCPU *armcpu;
156bc9a5
PM
315 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
316 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI;
317
318 if (vmc->claim_edge_triggered_timers) {
319 irqflags = GIC_FDT_IRQ_FLAGS_EDGE_LO_HI;
320 }
f5fdcd6e 321
d04460e5 322 if (vms->gic_version == VIRT_GIC_VERSION_2) {
b92ad394
PF
323 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START,
324 GIC_FDT_IRQ_PPI_CPU_WIDTH,
c8ef2bda 325 (1 << vms->smp_cpus) - 1);
b92ad394 326 }
f5fdcd6e 327
c8ef2bda 328 qemu_fdt_add_subnode(vms->fdt, "/timer");
b32a9509
CF
329
330 armcpu = ARM_CPU(qemu_get_cpu(0));
331 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) {
332 const char compat[] = "arm,armv8-timer\0arm,armv7-timer";
c8ef2bda 333 qemu_fdt_setprop(vms->fdt, "/timer", "compatible",
b32a9509
CF
334 compat, sizeof(compat));
335 } else {
c8ef2bda 336 qemu_fdt_setprop_string(vms->fdt, "/timer", "compatible",
b32a9509
CF
337 "arm,armv7-timer");
338 }
c8ef2bda
PM
339 qemu_fdt_setprop(vms->fdt, "/timer", "always-on", NULL, 0);
340 qemu_fdt_setprop_cells(vms->fdt, "/timer", "interrupts",
ee246400
SZ
341 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_S_EL1_IRQ, irqflags,
342 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL1_IRQ, irqflags,
343 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_VIRT_IRQ, irqflags,
344 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL2_IRQ, irqflags);
f5fdcd6e
PM
345}
346
c8ef2bda 347static void fdt_add_cpu_nodes(const VirtMachineState *vms)
f5fdcd6e
PM
348{
349 int cpu;
8d45c54d 350 int addr_cells = 1;
4ccf5826 351 const MachineState *ms = MACHINE(vms);
8d45c54d
PF
352
353 /*
354 * From Documentation/devicetree/bindings/arm/cpus.txt
355 * On ARM v8 64-bit systems value should be set to 2,
356 * that corresponds to the MPIDR_EL1 register size.
357 * If MPIDR_EL1[63:32] value is equal to 0 on all CPUs
358 * in the system, #address-cells can be set to 1, since
359 * MPIDR_EL1[63:32] bits are not used for CPUs
360 * identification.
361 *
362 * Here we actually don't know whether our system is 32- or 64-bit one.
363 * The simplest way to go is to examine affinity IDs of all our CPUs. If
364 * at least one of them has Aff3 populated, we set #address-cells to 2.
365 */
c8ef2bda 366 for (cpu = 0; cpu < vms->smp_cpus; cpu++) {
8d45c54d
PF
367 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu));
368
369 if (armcpu->mp_affinity & ARM_AFF3_MASK) {
370 addr_cells = 2;
371 break;
372 }
373 }
f5fdcd6e 374
c8ef2bda
PM
375 qemu_fdt_add_subnode(vms->fdt, "/cpus");
376 qemu_fdt_setprop_cell(vms->fdt, "/cpus", "#address-cells", addr_cells);
377 qemu_fdt_setprop_cell(vms->fdt, "/cpus", "#size-cells", 0x0);
f5fdcd6e 378
c8ef2bda 379 for (cpu = vms->smp_cpus - 1; cpu >= 0; cpu--) {
f5fdcd6e
PM
380 char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
381 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu));
4ccf5826 382 CPUState *cs = CPU(armcpu);
f5fdcd6e 383
c8ef2bda
PM
384 qemu_fdt_add_subnode(vms->fdt, nodename);
385 qemu_fdt_setprop_string(vms->fdt, nodename, "device_type", "cpu");
386 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible",
f5fdcd6e
PM
387 armcpu->dtb_compatible);
388
2013c566
PM
389 if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED
390 && vms->smp_cpus > 1) {
c8ef2bda 391 qemu_fdt_setprop_string(vms->fdt, nodename,
f5fdcd6e
PM
392 "enable-method", "psci");
393 }
394
8d45c54d 395 if (addr_cells == 2) {
c8ef2bda 396 qemu_fdt_setprop_u64(vms->fdt, nodename, "reg",
8d45c54d
PF
397 armcpu->mp_affinity);
398 } else {
c8ef2bda 399 qemu_fdt_setprop_cell(vms->fdt, nodename, "reg",
8d45c54d
PF
400 armcpu->mp_affinity);
401 }
402
4ccf5826
IM
403 if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) {
404 qemu_fdt_setprop_cell(vms->fdt, nodename, "numa-node-id",
405 ms->possible_cpus->cpus[cs->cpu_index].props.node_id);
9695200a
SZ
406 }
407
f5fdcd6e
PM
408 g_free(nodename);
409 }
410}
411
c8ef2bda 412static void fdt_add_its_gic_node(VirtMachineState *vms)
02f98731 413{
bb2a3348
EA
414 char *nodename;
415
c8ef2bda 416 vms->msi_phandle = qemu_fdt_alloc_phandle(vms->fdt);
bb2a3348
EA
417 nodename = g_strdup_printf("/intc/its@%" PRIx64,
418 vms->memmap[VIRT_GIC_ITS].base);
419 qemu_fdt_add_subnode(vms->fdt, nodename);
420 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible",
02f98731 421 "arm,gic-v3-its");
bb2a3348
EA
422 qemu_fdt_setprop(vms->fdt, nodename, "msi-controller", NULL, 0);
423 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
c8ef2bda
PM
424 2, vms->memmap[VIRT_GIC_ITS].base,
425 2, vms->memmap[VIRT_GIC_ITS].size);
bb2a3348
EA
426 qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", vms->msi_phandle);
427 g_free(nodename);
02f98731
PF
428}
429
c8ef2bda 430static void fdt_add_v2m_gic_node(VirtMachineState *vms)
f5fdcd6e 431{
bb2a3348
EA
432 char *nodename;
433
434 nodename = g_strdup_printf("/intc/v2m@%" PRIx64,
435 vms->memmap[VIRT_GIC_V2M].base);
c8ef2bda 436 vms->msi_phandle = qemu_fdt_alloc_phandle(vms->fdt);
bb2a3348
EA
437 qemu_fdt_add_subnode(vms->fdt, nodename);
438 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible",
bd204e63 439 "arm,gic-v2m-frame");
bb2a3348
EA
440 qemu_fdt_setprop(vms->fdt, nodename, "msi-controller", NULL, 0);
441 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
c8ef2bda
PM
442 2, vms->memmap[VIRT_GIC_V2M].base,
443 2, vms->memmap[VIRT_GIC_V2M].size);
bb2a3348
EA
444 qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", vms->msi_phandle);
445 g_free(nodename);
bd204e63 446}
f5fdcd6e 447
055a7f2b 448static void fdt_add_gic_node(VirtMachineState *vms)
bd204e63 449{
bb2a3348
EA
450 char *nodename;
451
c8ef2bda
PM
452 vms->gic_phandle = qemu_fdt_alloc_phandle(vms->fdt);
453 qemu_fdt_setprop_cell(vms->fdt, "/", "interrupt-parent", vms->gic_phandle);
454
bb2a3348
EA
455 nodename = g_strdup_printf("/intc@%" PRIx64,
456 vms->memmap[VIRT_GIC_DIST].base);
457 qemu_fdt_add_subnode(vms->fdt, nodename);
458 qemu_fdt_setprop_cell(vms->fdt, nodename, "#interrupt-cells", 3);
459 qemu_fdt_setprop(vms->fdt, nodename, "interrupt-controller", NULL, 0);
460 qemu_fdt_setprop_cell(vms->fdt, nodename, "#address-cells", 0x2);
461 qemu_fdt_setprop_cell(vms->fdt, nodename, "#size-cells", 0x2);
462 qemu_fdt_setprop(vms->fdt, nodename, "ranges", NULL, 0);
d04460e5 463 if (vms->gic_version == VIRT_GIC_VERSION_3) {
f90747c4
EA
464 int nb_redist_regions = virt_gicv3_redist_region_count(vms);
465
bb2a3348 466 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible",
b92ad394 467 "arm,gic-v3");
f90747c4 468
bb2a3348 469 qemu_fdt_setprop_cell(vms->fdt, nodename,
f90747c4
EA
470 "#redistributor-regions", nb_redist_regions);
471
472 if (nb_redist_regions == 1) {
bb2a3348 473 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
f90747c4
EA
474 2, vms->memmap[VIRT_GIC_DIST].base,
475 2, vms->memmap[VIRT_GIC_DIST].size,
476 2, vms->memmap[VIRT_GIC_REDIST].base,
477 2, vms->memmap[VIRT_GIC_REDIST].size);
478 } else {
bb2a3348 479 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
bf424a12
EA
480 2, vms->memmap[VIRT_GIC_DIST].base,
481 2, vms->memmap[VIRT_GIC_DIST].size,
482 2, vms->memmap[VIRT_GIC_REDIST].base,
483 2, vms->memmap[VIRT_GIC_REDIST].size,
484 2, vms->memmap[VIRT_HIGH_GIC_REDIST2].base,
485 2, vms->memmap[VIRT_HIGH_GIC_REDIST2].size);
f90747c4
EA
486 }
487
f29cacfb 488 if (vms->virt) {
bb2a3348 489 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts",
55ef3233 490 GIC_FDT_IRQ_TYPE_PPI, ARCH_GIC_MAINT_IRQ,
f29cacfb
PM
491 GIC_FDT_IRQ_FLAGS_LEVEL_HI);
492 }
b92ad394
PF
493 } else {
494 /* 'cortex-a15-gic' means 'GIC v2' */
bb2a3348 495 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible",
b92ad394 496 "arm,cortex-a15-gic");
55ef3233
LM
497 if (!vms->virt) {
498 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
499 2, vms->memmap[VIRT_GIC_DIST].base,
500 2, vms->memmap[VIRT_GIC_DIST].size,
501 2, vms->memmap[VIRT_GIC_CPU].base,
502 2, vms->memmap[VIRT_GIC_CPU].size);
503 } else {
504 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
505 2, vms->memmap[VIRT_GIC_DIST].base,
506 2, vms->memmap[VIRT_GIC_DIST].size,
507 2, vms->memmap[VIRT_GIC_CPU].base,
508 2, vms->memmap[VIRT_GIC_CPU].size,
509 2, vms->memmap[VIRT_GIC_HYP].base,
510 2, vms->memmap[VIRT_GIC_HYP].size,
511 2, vms->memmap[VIRT_GIC_VCPU].base,
512 2, vms->memmap[VIRT_GIC_VCPU].size);
513 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts",
514 GIC_FDT_IRQ_TYPE_PPI, ARCH_GIC_MAINT_IRQ,
515 GIC_FDT_IRQ_FLAGS_LEVEL_HI);
516 }
b92ad394
PF
517 }
518
bb2a3348
EA
519 qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", vms->gic_phandle);
520 g_free(nodename);
f5fdcd6e
PM
521}
522
055a7f2b 523static void fdt_add_pmu_nodes(const VirtMachineState *vms)
01fe6b60 524{
946f1bb1 525 ARMCPU *armcpu = ARM_CPU(first_cpu);
01fe6b60
SZ
526 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI;
527
946f1bb1
AJ
528 if (!arm_feature(&armcpu->env, ARM_FEATURE_PMU)) {
529 assert(!object_property_get_bool(OBJECT(armcpu), "pmu", NULL));
530 return;
01fe6b60
SZ
531 }
532
d04460e5 533 if (vms->gic_version == VIRT_GIC_VERSION_2) {
01fe6b60
SZ
534 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START,
535 GIC_FDT_IRQ_PPI_CPU_WIDTH,
c8ef2bda 536 (1 << vms->smp_cpus) - 1);
01fe6b60
SZ
537 }
538
c8ef2bda 539 qemu_fdt_add_subnode(vms->fdt, "/pmu");
01fe6b60
SZ
540 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) {
541 const char compat[] = "arm,armv8-pmuv3";
c8ef2bda 542 qemu_fdt_setprop(vms->fdt, "/pmu", "compatible",
01fe6b60 543 compat, sizeof(compat));
c8ef2bda 544 qemu_fdt_setprop_cells(vms->fdt, "/pmu", "interrupts",
01fe6b60
SZ
545 GIC_FDT_IRQ_TYPE_PPI, VIRTUAL_PMU_IRQ, irqflags);
546 }
547}
548
b8b69f4c 549static inline DeviceState *create_acpi_ged(VirtMachineState *vms)
cff51ac9
SK
550{
551 DeviceState *dev;
552 MachineState *ms = MACHINE(vms);
553 int irq = vms->irqmap[VIRT_ACPI_GED];
1962f31b 554 uint32_t event = ACPI_GED_PWR_DOWN_EVT;
cff51ac9
SK
555
556 if (ms->ram_slots) {
1962f31b 557 event |= ACPI_GED_MEM_HOTPLUG_EVT;
cff51ac9
SK
558 }
559
c2505d1c
SK
560 if (ms->nvdimms_state->is_enabled) {
561 event |= ACPI_GED_NVDIMM_HOTPLUG_EVT;
562 }
563
3e80f690 564 dev = qdev_new(TYPE_ACPI_GED);
cff51ac9
SK
565 qdev_prop_set_uint32(dev, "ged-event", event);
566
567 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_ACPI_GED].base);
568 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, vms->memmap[VIRT_PCDIMM_ACPI].base);
b8b69f4c 569 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(vms->gic, irq));
cff51ac9 570
3c6ef471 571 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
cff51ac9
SK
572
573 return dev;
574}
575
b8b69f4c 576static void create_its(VirtMachineState *vms)
02f98731
PF
577{
578 const char *itsclass = its_class_name();
579 DeviceState *dev;
580
581 if (!itsclass) {
582 /* Do nothing if not supported */
583 return;
584 }
585
3e80f690 586 dev = qdev_new(itsclass);
02f98731 587
5325cc34 588 object_property_set_link(OBJECT(dev), "parent-gicv3", OBJECT(vms->gic),
02f98731 589 &error_abort);
3c6ef471 590 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
c8ef2bda 591 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_ITS].base);
02f98731 592
c8ef2bda 593 fdt_add_its_gic_node(vms);
1b6f99d8 594 vms->msi_controller = VIRT_MSI_CTRL_ITS;
02f98731
PF
595}
596
b8b69f4c 597static void create_v2m(VirtMachineState *vms)
bd204e63
CD
598{
599 int i;
c8ef2bda 600 int irq = vms->irqmap[VIRT_GIC_V2M];
bd204e63
CD
601 DeviceState *dev;
602
3e80f690 603 dev = qdev_new("arm-gicv2m");
c8ef2bda 604 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_V2M].base);
bd204e63
CD
605 qdev_prop_set_uint32(dev, "base-spi", irq);
606 qdev_prop_set_uint32(dev, "num-spi", NUM_GICV2M_SPIS);
3c6ef471 607 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
bd204e63
CD
608
609 for (i = 0; i < NUM_GICV2M_SPIS; i++) {
b8b69f4c
PMD
610 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
611 qdev_get_gpio_in(vms->gic, irq + i));
bd204e63
CD
612 }
613
c8ef2bda 614 fdt_add_v2m_gic_node(vms);
1b6f99d8 615 vms->msi_controller = VIRT_MSI_CTRL_GICV2M;
bd204e63
CD
616}
617
b8b69f4c 618static void create_gic(VirtMachineState *vms)
64204743 619{
cc7d44c2 620 MachineState *ms = MACHINE(vms);
b92ad394 621 /* We create a standalone GIC */
64204743 622 SysBusDevice *gicbusdev;
e6fbcbc4 623 const char *gictype;
055a7f2b 624 int type = vms->gic_version, i;
cc7d44c2 625 unsigned int smp_cpus = ms->smp.cpus;
03d72fa1 626 uint32_t nb_redist_regions = 0;
64204743 627
b92ad394 628 gictype = (type == 3) ? gicv3_class_name() : gic_class_name();
64204743 629
3e80f690 630 vms->gic = qdev_new(gictype);
b8b69f4c
PMD
631 qdev_prop_set_uint32(vms->gic, "revision", type);
632 qdev_prop_set_uint32(vms->gic, "num-cpu", smp_cpus);
64204743
PM
633 /* Note that the num-irq property counts both internal and external
634 * interrupts; there are always 32 of the former (mandated by GIC spec).
635 */
b8b69f4c 636 qdev_prop_set_uint32(vms->gic, "num-irq", NUM_IRQS + 32);
0e21f183 637 if (!kvm_irqchip_in_kernel()) {
b8b69f4c 638 qdev_prop_set_bit(vms->gic, "has-security-extensions", vms->secure);
0e21f183 639 }
1e575b66
EA
640
641 if (type == 3) {
642 uint32_t redist0_capacity =
643 vms->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE;
644 uint32_t redist0_count = MIN(smp_cpus, redist0_capacity);
645
03d72fa1
EA
646 nb_redist_regions = virt_gicv3_redist_region_count(vms);
647
b8b69f4c 648 qdev_prop_set_uint32(vms->gic, "len-redist-region-count",
03d72fa1 649 nb_redist_regions);
b8b69f4c 650 qdev_prop_set_uint32(vms->gic, "redist-region-count[0]", redist0_count);
03d72fa1
EA
651
652 if (nb_redist_regions == 2) {
653 uint32_t redist1_capacity =
bf424a12 654 vms->memmap[VIRT_HIGH_GIC_REDIST2].size / GICV3_REDIST_SIZE;
03d72fa1 655
b8b69f4c 656 qdev_prop_set_uint32(vms->gic, "redist-region-count[1]",
03d72fa1
EA
657 MIN(smp_cpus - redist0_count, redist1_capacity));
658 }
55ef3233
LM
659 } else {
660 if (!kvm_irqchip_in_kernel()) {
b8b69f4c 661 qdev_prop_set_bit(vms->gic, "has-virtualization-extensions",
55ef3233
LM
662 vms->virt);
663 }
1e575b66 664 }
b8b69f4c 665 gicbusdev = SYS_BUS_DEVICE(vms->gic);
3c6ef471 666 sysbus_realize_and_unref(gicbusdev, &error_fatal);
c8ef2bda 667 sysbus_mmio_map(gicbusdev, 0, vms->memmap[VIRT_GIC_DIST].base);
b92ad394 668 if (type == 3) {
c8ef2bda 669 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_REDIST].base);
03d72fa1 670 if (nb_redist_regions == 2) {
bf424a12
EA
671 sysbus_mmio_map(gicbusdev, 2,
672 vms->memmap[VIRT_HIGH_GIC_REDIST2].base);
03d72fa1 673 }
b92ad394 674 } else {
c8ef2bda 675 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_CPU].base);
55ef3233
LM
676 if (vms->virt) {
677 sysbus_mmio_map(gicbusdev, 2, vms->memmap[VIRT_GIC_HYP].base);
678 sysbus_mmio_map(gicbusdev, 3, vms->memmap[VIRT_GIC_VCPU].base);
679 }
b92ad394 680 }
64204743 681
5454006a
PM
682 /* Wire the outputs from each CPU's generic timer and the GICv3
683 * maintenance interrupt signal to the appropriate GIC PPI inputs,
684 * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs.
64204743
PM
685 */
686 for (i = 0; i < smp_cpus; i++) {
687 DeviceState *cpudev = DEVICE(qemu_get_cpu(i));
0e3e858f 688 int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS;
a007b1f8
PM
689 int irq;
690 /* Mapping from the output timer irq lines from the CPU to the
691 * GIC PPI inputs we use for the virt board.
64204743 692 */
a007b1f8
PM
693 const int timer_irq[] = {
694 [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ,
695 [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ,
696 [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ,
697 [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ,
698 };
699
700 for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
701 qdev_connect_gpio_out(cpudev, irq,
b8b69f4c 702 qdev_get_gpio_in(vms->gic,
a007b1f8
PM
703 ppibase + timer_irq[irq]));
704 }
64204743 705
55ef3233 706 if (type == 3) {
b8b69f4c 707 qemu_irq irq = qdev_get_gpio_in(vms->gic,
55ef3233
LM
708 ppibase + ARCH_GIC_MAINT_IRQ);
709 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt",
710 0, irq);
711 } else if (vms->virt) {
b8b69f4c 712 qemu_irq irq = qdev_get_gpio_in(vms->gic,
55ef3233
LM
713 ppibase + ARCH_GIC_MAINT_IRQ);
714 sysbus_connect_irq(gicbusdev, i + 4 * smp_cpus, irq);
715 }
716
07f48730 717 qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0,
b8b69f4c 718 qdev_get_gpio_in(vms->gic, ppibase
07f48730 719 + VIRTUAL_PMU_IRQ));
5454006a 720
64204743 721 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
8e7b4ca0
GB
722 sysbus_connect_irq(gicbusdev, i + smp_cpus,
723 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
5454006a
PM
724 sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus,
725 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ));
726 sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus,
727 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
64204743
PM
728 }
729
055a7f2b 730 fdt_add_gic_node(vms);
bd204e63 731
ccc11b02 732 if (type == 3 && vms->its) {
b8b69f4c 733 create_its(vms);
2231f69b 734 } else if (type == 2) {
b8b69f4c 735 create_v2m(vms);
b92ad394 736 }
64204743
PM
737}
738
b8b69f4c 739static void create_uart(const VirtMachineState *vms, int uart,
0ec7b3e7 740 MemoryRegion *mem, Chardev *chr)
f5fdcd6e
PM
741{
742 char *nodename;
c8ef2bda
PM
743 hwaddr base = vms->memmap[uart].base;
744 hwaddr size = vms->memmap[uart].size;
745 int irq = vms->irqmap[uart];
f5fdcd6e
PM
746 const char compat[] = "arm,pl011\0arm,primecell";
747 const char clocknames[] = "uartclk\0apb_pclk";
3e80f690 748 DeviceState *dev = qdev_new(TYPE_PL011);
3df708eb 749 SysBusDevice *s = SYS_BUS_DEVICE(dev);
f5fdcd6e 750
9bbbf649 751 qdev_prop_set_chr(dev, "chardev", chr);
3c6ef471 752 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
3df708eb
PM
753 memory_region_add_subregion(mem, base,
754 sysbus_mmio_get_region(s, 0));
b8b69f4c 755 sysbus_connect_irq(s, 0, qdev_get_gpio_in(vms->gic, irq));
f5fdcd6e
PM
756
757 nodename = g_strdup_printf("/pl011@%" PRIx64, base);
c8ef2bda 758 qemu_fdt_add_subnode(vms->fdt, nodename);
f5fdcd6e 759 /* Note that we can't use setprop_string because of the embedded NUL */
c8ef2bda 760 qemu_fdt_setprop(vms->fdt, nodename, "compatible",
f5fdcd6e 761 compat, sizeof(compat));
c8ef2bda 762 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
f5fdcd6e 763 2, base, 2, size);
c8ef2bda 764 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts",
f5fdcd6e 765 GIC_FDT_IRQ_TYPE_SPI, irq,
0be969a2 766 GIC_FDT_IRQ_FLAGS_LEVEL_HI);
c8ef2bda
PM
767 qemu_fdt_setprop_cells(vms->fdt, nodename, "clocks",
768 vms->clock_phandle, vms->clock_phandle);
769 qemu_fdt_setprop(vms->fdt, nodename, "clock-names",
f5fdcd6e 770 clocknames, sizeof(clocknames));
f022b8e9 771
3df708eb 772 if (uart == VIRT_UART) {
c8ef2bda 773 qemu_fdt_setprop_string(vms->fdt, "/chosen", "stdout-path", nodename);
3df708eb
PM
774 } else {
775 /* Mark as not usable by the normal world */
c8ef2bda
PM
776 qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled");
777 qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay");
fb23d693 778
fb23d693
JF
779 qemu_fdt_setprop_string(vms->fdt, "/secure-chosen", "stdout-path",
780 nodename);
3df708eb
PM
781 }
782
f5fdcd6e
PM
783 g_free(nodename);
784}
785
b8b69f4c 786static void create_rtc(const VirtMachineState *vms)
6e411af9
PM
787{
788 char *nodename;
c8ef2bda
PM
789 hwaddr base = vms->memmap[VIRT_RTC].base;
790 hwaddr size = vms->memmap[VIRT_RTC].size;
791 int irq = vms->irqmap[VIRT_RTC];
6e411af9
PM
792 const char compat[] = "arm,pl031\0arm,primecell";
793
b8b69f4c 794 sysbus_create_simple("pl031", base, qdev_get_gpio_in(vms->gic, irq));
6e411af9
PM
795
796 nodename = g_strdup_printf("/pl031@%" PRIx64, base);
c8ef2bda
PM
797 qemu_fdt_add_subnode(vms->fdt, nodename);
798 qemu_fdt_setprop(vms->fdt, nodename, "compatible", compat, sizeof(compat));
799 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
6e411af9 800 2, base, 2, size);
c8ef2bda 801 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts",
6e411af9 802 GIC_FDT_IRQ_TYPE_SPI, irq,
0be969a2 803 GIC_FDT_IRQ_FLAGS_LEVEL_HI);
c8ef2bda
PM
804 qemu_fdt_setprop_cell(vms->fdt, nodename, "clocks", vms->clock_phandle);
805 qemu_fdt_setprop_string(vms->fdt, nodename, "clock-names", "apb_pclk");
6e411af9
PM
806 g_free(nodename);
807}
808
94f02c5e 809static DeviceState *gpio_key_dev;
4bedd849
SZ
810static void virt_powerdown_req(Notifier *n, void *opaque)
811{
1962f31b
SK
812 VirtMachineState *s = container_of(n, VirtMachineState, powerdown_notifier);
813
814 if (s->acpi_dev) {
815 acpi_send_event(s->acpi_dev, ACPI_POWER_DOWN_STATUS);
816 } else {
817 /* use gpio Pin 3 for power button event */
818 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1);
819 }
4bedd849
SZ
820}
821
b8b69f4c 822static void create_gpio(const VirtMachineState *vms)
b0a3721e
SZ
823{
824 char *nodename;
94f02c5e 825 DeviceState *pl061_dev;
c8ef2bda
PM
826 hwaddr base = vms->memmap[VIRT_GPIO].base;
827 hwaddr size = vms->memmap[VIRT_GPIO].size;
828 int irq = vms->irqmap[VIRT_GPIO];
b0a3721e
SZ
829 const char compat[] = "arm,pl061\0arm,primecell";
830
b8b69f4c
PMD
831 pl061_dev = sysbus_create_simple("pl061", base,
832 qdev_get_gpio_in(vms->gic, irq));
b0a3721e 833
c8ef2bda 834 uint32_t phandle = qemu_fdt_alloc_phandle(vms->fdt);
b0a3721e 835 nodename = g_strdup_printf("/pl061@%" PRIx64, base);
c8ef2bda
PM
836 qemu_fdt_add_subnode(vms->fdt, nodename);
837 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
b0a3721e 838 2, base, 2, size);
c8ef2bda
PM
839 qemu_fdt_setprop(vms->fdt, nodename, "compatible", compat, sizeof(compat));
840 qemu_fdt_setprop_cell(vms->fdt, nodename, "#gpio-cells", 2);
841 qemu_fdt_setprop(vms->fdt, nodename, "gpio-controller", NULL, 0);
842 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts",
b0a3721e
SZ
843 GIC_FDT_IRQ_TYPE_SPI, irq,
844 GIC_FDT_IRQ_FLAGS_LEVEL_HI);
c8ef2bda
PM
845 qemu_fdt_setprop_cell(vms->fdt, nodename, "clocks", vms->clock_phandle);
846 qemu_fdt_setprop_string(vms->fdt, nodename, "clock-names", "apb_pclk");
847 qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", phandle);
3e6ebb64 848
94f02c5e
SZ
849 gpio_key_dev = sysbus_create_simple("gpio-key", -1,
850 qdev_get_gpio_in(pl061_dev, 3));
c8ef2bda
PM
851 qemu_fdt_add_subnode(vms->fdt, "/gpio-keys");
852 qemu_fdt_setprop_string(vms->fdt, "/gpio-keys", "compatible", "gpio-keys");
853 qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys", "#size-cells", 0);
854 qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys", "#address-cells", 1);
3e6ebb64 855
c8ef2bda
PM
856 qemu_fdt_add_subnode(vms->fdt, "/gpio-keys/poweroff");
857 qemu_fdt_setprop_string(vms->fdt, "/gpio-keys/poweroff",
3e6ebb64 858 "label", "GPIO Key Poweroff");
c8ef2bda 859 qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys/poweroff", "linux,code",
3e6ebb64 860 KEY_POWER);
c8ef2bda 861 qemu_fdt_setprop_cells(vms->fdt, "/gpio-keys/poweroff",
3e6ebb64 862 "gpios", phandle, 3, 0);
b0a3721e
SZ
863 g_free(nodename);
864}
865
b8b69f4c 866static void create_virtio_devices(const VirtMachineState *vms)
f5fdcd6e
PM
867{
868 int i;
c8ef2bda 869 hwaddr size = vms->memmap[VIRT_MMIO].size;
f5fdcd6e 870
587078f0
LE
871 /* We create the transports in forwards order. Since qbus_realize()
872 * prepends (not appends) new child buses, the incrementing loop below will
873 * create a list of virtio-mmio buses with decreasing base addresses.
874 *
875 * When a -device option is processed from the command line,
876 * qbus_find_recursive() picks the next free virtio-mmio bus in forwards
877 * order. The upshot is that -device options in increasing command line
878 * order are mapped to virtio-mmio buses with decreasing base addresses.
879 *
880 * When this code was originally written, that arrangement ensured that the
881 * guest Linux kernel would give the lowest "name" (/dev/vda, eth0, etc) to
882 * the first -device on the command line. (The end-to-end order is a
883 * function of this loop, qbus_realize(), qbus_find_recursive(), and the
884 * guest kernel's name-to-address assignment strategy.)
885 *
886 * Meanwhile, the kernel's traversal seems to have been reversed; see eg.
887 * the message, if not necessarily the code, of commit 70161ff336.
888 * Therefore the loop now establishes the inverse of the original intent.
889 *
890 * Unfortunately, we can't counteract the kernel change by reversing the
891 * loop; it would break existing command lines.
892 *
893 * In any case, the kernel makes no guarantee about the stability of
894 * enumeration order of virtio devices (as demonstrated by it changing
895 * between kernel versions). For reliable and stable identification
896 * of disks users must use UUIDs or similar mechanisms.
f5fdcd6e
PM
897 */
898 for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) {
c8ef2bda
PM
899 int irq = vms->irqmap[VIRT_MMIO] + i;
900 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size;
f5fdcd6e 901
b8b69f4c
PMD
902 sysbus_create_simple("virtio-mmio", base,
903 qdev_get_gpio_in(vms->gic, irq));
f5fdcd6e
PM
904 }
905
587078f0
LE
906 /* We add dtb nodes in reverse order so that they appear in the finished
907 * device tree lowest address first.
908 *
909 * Note that this mapping is independent of the loop above. The previous
910 * loop influences virtio device to virtio transport assignment, whereas
911 * this loop controls how virtio transports are laid out in the dtb.
912 */
f5fdcd6e
PM
913 for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) {
914 char *nodename;
c8ef2bda
PM
915 int irq = vms->irqmap[VIRT_MMIO] + i;
916 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size;
f5fdcd6e
PM
917
918 nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, base);
c8ef2bda
PM
919 qemu_fdt_add_subnode(vms->fdt, nodename);
920 qemu_fdt_setprop_string(vms->fdt, nodename,
5a4348d1 921 "compatible", "virtio,mmio");
c8ef2bda 922 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
5a4348d1 923 2, base, 2, size);
c8ef2bda 924 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts",
5a4348d1
PC
925 GIC_FDT_IRQ_TYPE_SPI, irq,
926 GIC_FDT_IRQ_FLAGS_EDGE_LO_HI);
054bb7b2 927 qemu_fdt_setprop(vms->fdt, nodename, "dma-coherent", NULL, 0);
f5fdcd6e
PM
928 g_free(nodename);
929 }
930}
931
e0561e60
MA
932#define VIRT_FLASH_SECTOR_SIZE (256 * KiB)
933
934static PFlashCFI01 *virt_flash_create1(VirtMachineState *vms,
935 const char *name,
936 const char *alias_prop_name)
acf82361 937{
e0561e60
MA
938 /*
939 * Create a single flash device. We use the same parameters as
940 * the flash devices on the Versatile Express board.
acf82361 941 */
df707969 942 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01);
acf82361 943
e0561e60 944 qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE);
acf82361
PM
945 qdev_prop_set_uint8(dev, "width", 4);
946 qdev_prop_set_uint8(dev, "device-width", 2);
e9809422 947 qdev_prop_set_bit(dev, "big-endian", false);
acf82361
PM
948 qdev_prop_set_uint16(dev, "id0", 0x89);
949 qdev_prop_set_uint16(dev, "id1", 0x18);
950 qdev_prop_set_uint16(dev, "id2", 0x00);
951 qdev_prop_set_uint16(dev, "id3", 0x00);
952 qdev_prop_set_string(dev, "name", name);
d2623129 953 object_property_add_child(OBJECT(vms), name, OBJECT(dev));
e0561e60 954 object_property_add_alias(OBJECT(vms), alias_prop_name,
d2623129 955 OBJECT(dev), "drive");
e0561e60
MA
956 return PFLASH_CFI01(dev);
957}
acf82361 958
e0561e60
MA
959static void virt_flash_create(VirtMachineState *vms)
960{
961 vms->flash[0] = virt_flash_create1(vms, "virt.flash0", "pflash0");
962 vms->flash[1] = virt_flash_create1(vms, "virt.flash1", "pflash1");
963}
acf82361 964
e0561e60
MA
965static void virt_flash_map1(PFlashCFI01 *flash,
966 hwaddr base, hwaddr size,
967 MemoryRegion *sysmem)
968{
969 DeviceState *dev = DEVICE(flash);
acf82361 970
4cdd0a77 971 assert(QEMU_IS_ALIGNED(size, VIRT_FLASH_SECTOR_SIZE));
e0561e60
MA
972 assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX);
973 qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE);
3c6ef471 974 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
e0561e60
MA
975
976 memory_region_add_subregion(sysmem, base,
977 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev),
978 0));
16f4a8dc
PM
979}
980
e0561e60
MA
981static void virt_flash_map(VirtMachineState *vms,
982 MemoryRegion *sysmem,
983 MemoryRegion *secure_sysmem)
16f4a8dc 984{
e0561e60
MA
985 /*
986 * Map two flash devices to fill the VIRT_FLASH space in the memmap.
738a5d9f
PM
987 * sysmem is the system memory space. secure_sysmem is the secure view
988 * of the system, and the first flash device should be made visible only
989 * there. The second flash device is visible to both secure and nonsecure.
990 * If sysmem == secure_sysmem this means there is no separate Secure
991 * address space and both flash devices are generally visible.
16f4a8dc 992 */
c8ef2bda
PM
993 hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2;
994 hwaddr flashbase = vms->memmap[VIRT_FLASH].base;
acf82361 995
e0561e60
MA
996 virt_flash_map1(vms->flash[0], flashbase, flashsize,
997 secure_sysmem);
998 virt_flash_map1(vms->flash[1], flashbase + flashsize, flashsize,
999 sysmem);
1000}
1001
1002static void virt_flash_fdt(VirtMachineState *vms,
1003 MemoryRegion *sysmem,
1004 MemoryRegion *secure_sysmem)
1005{
1006 hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2;
1007 hwaddr flashbase = vms->memmap[VIRT_FLASH].base;
1008 char *nodename;
acf82361 1009
738a5d9f
PM
1010 if (sysmem == secure_sysmem) {
1011 /* Report both flash devices as a single node in the DT */
1012 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase);
c8ef2bda
PM
1013 qemu_fdt_add_subnode(vms->fdt, nodename);
1014 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", "cfi-flash");
1015 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
738a5d9f
PM
1016 2, flashbase, 2, flashsize,
1017 2, flashbase + flashsize, 2, flashsize);
c8ef2bda 1018 qemu_fdt_setprop_cell(vms->fdt, nodename, "bank-width", 4);
738a5d9f
PM
1019 g_free(nodename);
1020 } else {
e0561e60
MA
1021 /*
1022 * Report the devices as separate nodes so we can mark one as
738a5d9f
PM
1023 * only visible to the secure world.
1024 */
1025 nodename = g_strdup_printf("/secflash@%" PRIx64, flashbase);
c8ef2bda
PM
1026 qemu_fdt_add_subnode(vms->fdt, nodename);
1027 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", "cfi-flash");
1028 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
738a5d9f 1029 2, flashbase, 2, flashsize);
c8ef2bda
PM
1030 qemu_fdt_setprop_cell(vms->fdt, nodename, "bank-width", 4);
1031 qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled");
1032 qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay");
738a5d9f
PM
1033 g_free(nodename);
1034
1035 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase);
c8ef2bda
PM
1036 qemu_fdt_add_subnode(vms->fdt, nodename);
1037 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", "cfi-flash");
1038 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
738a5d9f 1039 2, flashbase + flashsize, 2, flashsize);
c8ef2bda 1040 qemu_fdt_setprop_cell(vms->fdt, nodename, "bank-width", 4);
738a5d9f
PM
1041 g_free(nodename);
1042 }
acf82361
PM
1043}
1044
e0561e60
MA
1045static bool virt_firmware_init(VirtMachineState *vms,
1046 MemoryRegion *sysmem,
1047 MemoryRegion *secure_sysmem)
1048{
1049 int i;
1050 BlockBackend *pflash_blk0;
1051
1052 /* Map legacy -drive if=pflash to machine properties */
1053 for (i = 0; i < ARRAY_SIZE(vms->flash); i++) {
1054 pflash_cfi01_legacy_drive(vms->flash[i],
1055 drive_get(IF_PFLASH, 0, i));
1056 }
1057
1058 virt_flash_map(vms, sysmem, secure_sysmem);
1059
1060 pflash_blk0 = pflash_cfi01_get_blk(vms->flash[0]);
1061
1062 if (bios_name) {
1063 char *fname;
1064 MemoryRegion *mr;
1065 int image_size;
1066
1067 if (pflash_blk0) {
1068 error_report("The contents of the first flash device may be "
1069 "specified with -bios or with -drive if=pflash... "
1070 "but you cannot use both options at once");
1071 exit(1);
1072 }
1073
1074 /* Fall back to -bios */
1075
1076 fname = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
1077 if (!fname) {
1078 error_report("Could not find ROM image '%s'", bios_name);
1079 exit(1);
1080 }
1081 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(vms->flash[0]), 0);
1082 image_size = load_image_mr(fname, mr);
1083 g_free(fname);
1084 if (image_size < 0) {
1085 error_report("Could not load ROM image '%s'", bios_name);
1086 exit(1);
1087 }
1088 }
1089
1090 return pflash_blk0 || bios_name;
1091}
1092
af1f60a4 1093static FWCfgState *create_fw_cfg(const VirtMachineState *vms, AddressSpace *as)
578f3c7b 1094{
cc7d44c2 1095 MachineState *ms = MACHINE(vms);
c8ef2bda
PM
1096 hwaddr base = vms->memmap[VIRT_FW_CFG].base;
1097 hwaddr size = vms->memmap[VIRT_FW_CFG].size;
5836d168 1098 FWCfgState *fw_cfg;
578f3c7b
LE
1099 char *nodename;
1100
5836d168 1101 fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, as);
cc7d44c2 1102 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)ms->smp.cpus);
578f3c7b
LE
1103
1104 nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base);
c8ef2bda
PM
1105 qemu_fdt_add_subnode(vms->fdt, nodename);
1106 qemu_fdt_setprop_string(vms->fdt, nodename,
578f3c7b 1107 "compatible", "qemu,fw-cfg-mmio");
c8ef2bda 1108 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
578f3c7b 1109 2, base, 2, size);
14efdb5c 1110 qemu_fdt_setprop(vms->fdt, nodename, "dma-coherent", NULL, 0);
578f3c7b 1111 g_free(nodename);
af1f60a4 1112 return fw_cfg;
578f3c7b
LE
1113}
1114
c8ef2bda 1115static void create_pcie_irq_map(const VirtMachineState *vms,
9ac4ef77 1116 uint32_t gic_phandle,
4ab29b82
AG
1117 int first_irq, const char *nodename)
1118{
1119 int devfn, pin;
dfd90a87 1120 uint32_t full_irq_map[4 * 4 * 10] = { 0 };
4ab29b82
AG
1121 uint32_t *irq_map = full_irq_map;
1122
1123 for (devfn = 0; devfn <= 0x18; devfn += 0x8) {
1124 for (pin = 0; pin < 4; pin++) {
1125 int irq_type = GIC_FDT_IRQ_TYPE_SPI;
1126 int irq_nr = first_irq + ((pin + PCI_SLOT(devfn)) % PCI_NUM_PINS);
1127 int irq_level = GIC_FDT_IRQ_FLAGS_LEVEL_HI;
1128 int i;
1129
1130 uint32_t map[] = {
1131 devfn << 8, 0, 0, /* devfn */
1132 pin + 1, /* PCI pin */
dfd90a87 1133 gic_phandle, 0, 0, irq_type, irq_nr, irq_level }; /* GIC irq */
4ab29b82
AG
1134
1135 /* Convert map to big endian */
dfd90a87 1136 for (i = 0; i < 10; i++) {
4ab29b82
AG
1137 irq_map[i] = cpu_to_be32(map[i]);
1138 }
dfd90a87 1139 irq_map += 10;
4ab29b82
AG
1140 }
1141 }
1142
c8ef2bda 1143 qemu_fdt_setprop(vms->fdt, nodename, "interrupt-map",
4ab29b82
AG
1144 full_irq_map, sizeof(full_irq_map));
1145
c8ef2bda 1146 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupt-map-mask",
4ab29b82
AG
1147 0x1800, 0, 0, /* devfn (PCI_SLOT(3)) */
1148 0x7 /* PCI irq */);
1149}
1150
b8b69f4c 1151static void create_smmu(const VirtMachineState *vms,
584105ea
PM
1152 PCIBus *bus)
1153{
1154 char *node;
1155 const char compat[] = "arm,smmu-v3";
1156 int irq = vms->irqmap[VIRT_SMMU];
1157 int i;
1158 hwaddr base = vms->memmap[VIRT_SMMU].base;
1159 hwaddr size = vms->memmap[VIRT_SMMU].size;
1160 const char irq_names[] = "eventq\0priq\0cmdq-sync\0gerror";
1161 DeviceState *dev;
1162
1163 if (vms->iommu != VIRT_IOMMU_SMMUV3 || !vms->iommu_phandle) {
1164 return;
1165 }
1166
3e80f690 1167 dev = qdev_new("arm-smmuv3");
584105ea 1168
5325cc34 1169 object_property_set_link(OBJECT(dev), "primary-bus", OBJECT(bus),
584105ea 1170 &error_abort);
3c6ef471 1171 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
584105ea
PM
1172 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
1173 for (i = 0; i < NUM_SMMU_IRQS; i++) {
b8b69f4c
PMD
1174 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
1175 qdev_get_gpio_in(vms->gic, irq + i));
584105ea
PM
1176 }
1177
1178 node = g_strdup_printf("/smmuv3@%" PRIx64, base);
1179 qemu_fdt_add_subnode(vms->fdt, node);
1180 qemu_fdt_setprop(vms->fdt, node, "compatible", compat, sizeof(compat));
1181 qemu_fdt_setprop_sized_cells(vms->fdt, node, "reg", 2, base, 2, size);
1182
1183 qemu_fdt_setprop_cells(vms->fdt, node, "interrupts",
1184 GIC_FDT_IRQ_TYPE_SPI, irq , GIC_FDT_IRQ_FLAGS_EDGE_LO_HI,
1185 GIC_FDT_IRQ_TYPE_SPI, irq + 1, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI,
1186 GIC_FDT_IRQ_TYPE_SPI, irq + 2, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI,
1187 GIC_FDT_IRQ_TYPE_SPI, irq + 3, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI);
1188
1189 qemu_fdt_setprop(vms->fdt, node, "interrupt-names", irq_names,
1190 sizeof(irq_names));
1191
1192 qemu_fdt_setprop_cell(vms->fdt, node, "clocks", vms->clock_phandle);
1193 qemu_fdt_setprop_string(vms->fdt, node, "clock-names", "apb_pclk");
1194 qemu_fdt_setprop(vms->fdt, node, "dma-coherent", NULL, 0);
1195
1196 qemu_fdt_setprop_cell(vms->fdt, node, "#iommu-cells", 1);
1197
1198 qemu_fdt_setprop_cell(vms->fdt, node, "phandle", vms->iommu_phandle);
1199 g_free(node);
1200}
1201
0fbddcec 1202static void create_virtio_iommu_dt_bindings(VirtMachineState *vms)
70e89132
EA
1203{
1204 const char compat[] = "virtio,pci-iommu";
1205 uint16_t bdf = vms->virtio_iommu_bdf;
1206 char *node;
1207
1208 vms->iommu_phandle = qemu_fdt_alloc_phandle(vms->fdt);
1209
1210 node = g_strdup_printf("%s/virtio_iommu@%d", vms->pciehb_nodename, bdf);
1211 qemu_fdt_add_subnode(vms->fdt, node);
1212 qemu_fdt_setprop(vms->fdt, node, "compatible", compat, sizeof(compat));
1213 qemu_fdt_setprop_sized_cells(vms->fdt, node, "reg",
1214 1, bdf << 8, 1, 0, 1, 0,
1215 1, 0, 1, 0);
1216
1217 qemu_fdt_setprop_cell(vms->fdt, node, "#iommu-cells", 1);
1218 qemu_fdt_setprop_cell(vms->fdt, node, "phandle", vms->iommu_phandle);
1219 g_free(node);
1220
1221 qemu_fdt_setprop_cells(vms->fdt, vms->pciehb_nodename, "iommu-map",
1222 0x0, vms->iommu_phandle, 0x0, bdf,
1223 bdf + 1, vms->iommu_phandle, bdf + 1, 0xffff - bdf);
1224}
1225
b8b69f4c 1226static void create_pcie(VirtMachineState *vms)
4ab29b82 1227{
c8ef2bda
PM
1228 hwaddr base_mmio = vms->memmap[VIRT_PCIE_MMIO].base;
1229 hwaddr size_mmio = vms->memmap[VIRT_PCIE_MMIO].size;
bf424a12
EA
1230 hwaddr base_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].base;
1231 hwaddr size_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].size;
c8ef2bda
PM
1232 hwaddr base_pio = vms->memmap[VIRT_PCIE_PIO].base;
1233 hwaddr size_pio = vms->memmap[VIRT_PCIE_PIO].size;
601d626d 1234 hwaddr base_ecam, size_ecam;
6a1f001b 1235 hwaddr base = base_mmio;
601d626d 1236 int nr_pcie_buses;
c8ef2bda 1237 int irq = vms->irqmap[VIRT_PCIE];
4ab29b82
AG
1238 MemoryRegion *mmio_alias;
1239 MemoryRegion *mmio_reg;
1240 MemoryRegion *ecam_alias;
1241 MemoryRegion *ecam_reg;
1242 DeviceState *dev;
1243 char *nodename;
601d626d 1244 int i, ecam_id;
fea9b3ca 1245 PCIHostState *pci;
4ab29b82 1246
3e80f690 1247 dev = qdev_new(TYPE_GPEX_HOST);
3c6ef471 1248 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
4ab29b82 1249
601d626d
EA
1250 ecam_id = VIRT_ECAM_ID(vms->highmem_ecam);
1251 base_ecam = vms->memmap[ecam_id].base;
1252 size_ecam = vms->memmap[ecam_id].size;
1253 nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN;
4ab29b82
AG
1254 /* Map only the first size_ecam bytes of ECAM space */
1255 ecam_alias = g_new0(MemoryRegion, 1);
1256 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
1257 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam",
1258 ecam_reg, 0, size_ecam);
1259 memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias);
1260
1261 /* Map the MMIO window into system address space so as to expose
1262 * the section of PCI MMIO space which starts at the same base address
1263 * (ie 1:1 mapping for that part of PCI MMIO space visible through
1264 * the window).
1265 */
1266 mmio_alias = g_new0(MemoryRegion, 1);
1267 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);
1268 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio",
1269 mmio_reg, base_mmio, size_mmio);
1270 memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias);
1271
0127937b 1272 if (vms->highmem) {
5125f9cd
PF
1273 /* Map high MMIO space */
1274 MemoryRegion *high_mmio_alias = g_new0(MemoryRegion, 1);
1275
1276 memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high",
1277 mmio_reg, base_mmio_high, size_mmio_high);
1278 memory_region_add_subregion(get_system_memory(), base_mmio_high,
1279 high_mmio_alias);
1280 }
1281
4ab29b82 1282 /* Map IO port space */
6a1f001b 1283 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio);
4ab29b82
AG
1284
1285 for (i = 0; i < GPEX_NUM_IRQS; i++) {
b8b69f4c
PMD
1286 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
1287 qdev_get_gpio_in(vms->gic, irq + i));
c9bb8e16 1288 gpex_set_irq_num(GPEX_HOST(dev), i, irq + i);
4ab29b82
AG
1289 }
1290
fea9b3ca
AK
1291 pci = PCI_HOST_BRIDGE(dev);
1292 if (pci->bus) {
1293 for (i = 0; i < nb_nics; i++) {
1294 NICInfo *nd = &nd_table[i];
1295
1296 if (!nd->model) {
1297 nd->model = g_strdup("virtio");
1298 }
1299
1300 pci_nic_init_nofail(nd, pci->bus, nd->model, NULL);
1301 }
1302 }
1303
70e89132 1304 nodename = vms->pciehb_nodename = g_strdup_printf("/pcie@%" PRIx64, base);
c8ef2bda
PM
1305 qemu_fdt_add_subnode(vms->fdt, nodename);
1306 qemu_fdt_setprop_string(vms->fdt, nodename,
4ab29b82 1307 "compatible", "pci-host-ecam-generic");
c8ef2bda
PM
1308 qemu_fdt_setprop_string(vms->fdt, nodename, "device_type", "pci");
1309 qemu_fdt_setprop_cell(vms->fdt, nodename, "#address-cells", 3);
1310 qemu_fdt_setprop_cell(vms->fdt, nodename, "#size-cells", 2);
6d9c1b8d 1311 qemu_fdt_setprop_cell(vms->fdt, nodename, "linux,pci-domain", 0);
c8ef2bda 1312 qemu_fdt_setprop_cells(vms->fdt, nodename, "bus-range", 0,
4ab29b82 1313 nr_pcie_buses - 1);
c8ef2bda 1314 qemu_fdt_setprop(vms->fdt, nodename, "dma-coherent", NULL, 0);
4ab29b82 1315
c8ef2bda
PM
1316 if (vms->msi_phandle) {
1317 qemu_fdt_setprop_cells(vms->fdt, nodename, "msi-parent",
1318 vms->msi_phandle);
b92ad394 1319 }
bd204e63 1320
c8ef2bda 1321 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
4ab29b82 1322 2, base_ecam, 2, size_ecam);
5125f9cd 1323
0127937b 1324 if (vms->highmem) {
c8ef2bda 1325 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "ranges",
5125f9cd
PF
1326 1, FDT_PCI_RANGE_IOPORT, 2, 0,
1327 2, base_pio, 2, size_pio,
1328 1, FDT_PCI_RANGE_MMIO, 2, base_mmio,
1329 2, base_mmio, 2, size_mmio,
1330 1, FDT_PCI_RANGE_MMIO_64BIT,
1331 2, base_mmio_high,
1332 2, base_mmio_high, 2, size_mmio_high);
1333 } else {
c8ef2bda 1334 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "ranges",
5125f9cd
PF
1335 1, FDT_PCI_RANGE_IOPORT, 2, 0,
1336 2, base_pio, 2, size_pio,
1337 1, FDT_PCI_RANGE_MMIO, 2, base_mmio,
1338 2, base_mmio, 2, size_mmio);
1339 }
4ab29b82 1340
c8ef2bda
PM
1341 qemu_fdt_setprop_cell(vms->fdt, nodename, "#interrupt-cells", 1);
1342 create_pcie_irq_map(vms, vms->gic_phandle, irq, nodename);
4ab29b82 1343
584105ea
PM
1344 if (vms->iommu) {
1345 vms->iommu_phandle = qemu_fdt_alloc_phandle(vms->fdt);
1346
70e89132
EA
1347 switch (vms->iommu) {
1348 case VIRT_IOMMU_SMMUV3:
1349 create_smmu(vms, pci->bus);
1350 qemu_fdt_setprop_cells(vms->fdt, nodename, "iommu-map",
1351 0x0, vms->iommu_phandle, 0x0, 0x10000);
1352 break;
1353 default:
1354 g_assert_not_reached();
1355 }
584105ea 1356 }
4ab29b82
AG
1357}
1358
b8b69f4c 1359static void create_platform_bus(VirtMachineState *vms)
5f7a5a0e
EA
1360{
1361 DeviceState *dev;
1362 SysBusDevice *s;
1363 int i;
5f7a5a0e
EA
1364 MemoryRegion *sysmem = get_system_memory();
1365
3e80f690 1366 dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE);
5f7a5a0e 1367 dev->id = TYPE_PLATFORM_BUS_DEVICE;
3b77f6c3
IM
1368 qdev_prop_set_uint32(dev, "num_irqs", PLATFORM_BUS_NUM_IRQS);
1369 qdev_prop_set_uint32(dev, "mmio_size", vms->memmap[VIRT_PLATFORM_BUS].size);
3c6ef471 1370 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
a3fc8396 1371 vms->platform_bus_dev = dev;
5f7a5a0e 1372
3b77f6c3
IM
1373 s = SYS_BUS_DEVICE(dev);
1374 for (i = 0; i < PLATFORM_BUS_NUM_IRQS; i++) {
b8b69f4c
PMD
1375 int irq = vms->irqmap[VIRT_PLATFORM_BUS] + i;
1376 sysbus_connect_irq(s, i, qdev_get_gpio_in(vms->gic, irq));
5f7a5a0e
EA
1377 }
1378
1379 memory_region_add_subregion(sysmem,
3b77f6c3 1380 vms->memmap[VIRT_PLATFORM_BUS].base,
5f7a5a0e
EA
1381 sysbus_mmio_get_region(s, 0));
1382}
1383
8bce44a2
RH
1384static void create_tag_ram(MemoryRegion *tag_sysmem,
1385 hwaddr base, hwaddr size,
1386 const char *name)
1387{
1388 MemoryRegion *tagram = g_new(MemoryRegion, 1);
1389
1390 memory_region_init_ram(tagram, NULL, name, size / 32, &error_fatal);
1391 memory_region_add_subregion(tag_sysmem, base / 32, tagram);
1392}
1393
c8ef2bda 1394static void create_secure_ram(VirtMachineState *vms,
8bce44a2
RH
1395 MemoryRegion *secure_sysmem,
1396 MemoryRegion *secure_tag_sysmem)
83ec1923
PM
1397{
1398 MemoryRegion *secram = g_new(MemoryRegion, 1);
1399 char *nodename;
c8ef2bda
PM
1400 hwaddr base = vms->memmap[VIRT_SECURE_MEM].base;
1401 hwaddr size = vms->memmap[VIRT_SECURE_MEM].size;
83ec1923 1402
98a99ce0
PM
1403 memory_region_init_ram(secram, NULL, "virt.secure-ram", size,
1404 &error_fatal);
83ec1923
PM
1405 memory_region_add_subregion(secure_sysmem, base, secram);
1406
1407 nodename = g_strdup_printf("/secram@%" PRIx64, base);
c8ef2bda
PM
1408 qemu_fdt_add_subnode(vms->fdt, nodename);
1409 qemu_fdt_setprop_string(vms->fdt, nodename, "device_type", "memory");
1410 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 2, base, 2, size);
1411 qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled");
1412 qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay");
83ec1923 1413
8bce44a2
RH
1414 if (secure_tag_sysmem) {
1415 create_tag_ram(secure_tag_sysmem, base, size, "mach-virt.secure-tag");
1416 }
1417
83ec1923
PM
1418 g_free(nodename);
1419}
1420
f5fdcd6e
PM
1421static void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size)
1422{
9ac4ef77
PM
1423 const VirtMachineState *board = container_of(binfo, VirtMachineState,
1424 bootinfo);
f5fdcd6e
PM
1425
1426 *fdt_size = board->fdt_size;
1427 return board->fdt;
1428}
1429
e9a8e474 1430static void virt_build_smbios(VirtMachineState *vms)
c30e1565 1431{
dfadc3bf
WH
1432 MachineClass *mc = MACHINE_GET_CLASS(vms);
1433 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
c30e1565
WH
1434 uint8_t *smbios_tables, *smbios_anchor;
1435 size_t smbios_tables_len, smbios_anchor_len;
bab27ea2 1436 const char *product = "QEMU Virtual Machine";
c30e1565 1437
bab27ea2
AJ
1438 if (kvm_enabled()) {
1439 product = "KVM Virtual Machine";
1440 }
1441
1442 smbios_set_defaults("QEMU", product,
dfadc3bf
WH
1443 vmc->smbios_old_sys_ver ? "1.0" : mc->name, false,
1444 true, SMBIOS_ENTRY_POINT_30);
c30e1565 1445
a0628599 1446 smbios_get_tables(MACHINE(vms), NULL, 0, &smbios_tables, &smbios_tables_len,
c30e1565
WH
1447 &smbios_anchor, &smbios_anchor_len);
1448
1449 if (smbios_anchor) {
af1f60a4 1450 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-tables",
c30e1565 1451 smbios_tables, smbios_tables_len);
af1f60a4 1452 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-anchor",
c30e1565
WH
1453 smbios_anchor, smbios_anchor_len);
1454 }
1455}
1456
d7c2e2db 1457static
054f4dc9 1458void virt_machine_done(Notifier *notifier, void *data)
d7c2e2db 1459{
054f4dc9
AJ
1460 VirtMachineState *vms = container_of(notifier, VirtMachineState,
1461 machine_done);
2744ece8 1462 MachineState *ms = MACHINE(vms);
3b77f6c3
IM
1463 ARMCPU *cpu = ARM_CPU(first_cpu);
1464 struct arm_boot_info *info = &vms->bootinfo;
1465 AddressSpace *as = arm_boot_address_space(cpu, info);
1466
1467 /*
1468 * If the user provided a dtb, we assume the dynamic sysbus nodes
1469 * already are integrated there. This corresponds to a use case where
1470 * the dynamic sysbus nodes are complex and their generation is not yet
1471 * supported. In that case the user can take charge of the guest dt
1472 * while qemu takes charge of the qom stuff.
1473 */
1474 if (info->dtb_filename == NULL) {
1475 platform_bus_add_all_fdt_nodes(vms->fdt, "/intc",
1476 vms->memmap[VIRT_PLATFORM_BUS].base,
1477 vms->memmap[VIRT_PLATFORM_BUS].size,
1478 vms->irqmap[VIRT_PLATFORM_BUS]);
1479 }
2744ece8 1480 if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as, ms) < 0) {
3b77f6c3
IM
1481 exit(1);
1482 }
054f4dc9 1483
e9a8e474
AJ
1484 virt_acpi_setup(vms);
1485 virt_build_smbios(vms);
d7c2e2db
SZ
1486}
1487
46de5913
IM
1488static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx)
1489{
1490 uint8_t clustersz = ARM_DEFAULT_CPUS_PER_CLUSTER;
1491 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
1492
1493 if (!vmc->disallow_affinity_adjustment) {
1494 /* Adjust MPIDR like 64-bit KVM hosts, which incorporate the
1495 * GIC's target-list limitations. 32-bit KVM hosts currently
1496 * always create clusters of 4 CPUs, but that is expected to
1497 * change when they gain support for gicv3. When KVM is enabled
1498 * it will override the changes we make here, therefore our
1499 * purposes are to make TCG consistent (with 64-bit KVM hosts)
1500 * and to improve SGI efficiency.
1501 */
d04460e5 1502 if (vms->gic_version == VIRT_GIC_VERSION_3) {
46de5913
IM
1503 clustersz = GICV3_TARGETLIST_BITS;
1504 } else {
1505 clustersz = GIC_TARGETLIST_BITS;
1506 }
1507 }
1508 return arm_cpu_mp_affinity(idx, clustersz);
1509}
1510
350a9c9e
EA
1511static void virt_set_memmap(VirtMachineState *vms)
1512{
957e32cf
EA
1513 MachineState *ms = MACHINE(vms);
1514 hwaddr base, device_memory_base, device_memory_size;
350a9c9e
EA
1515 int i;
1516
1517 vms->memmap = extended_memmap;
1518
1519 for (i = 0; i < ARRAY_SIZE(base_memmap); i++) {
1520 vms->memmap[i] = base_memmap[i];
1521 }
1522
957e32cf
EA
1523 if (ms->ram_slots > ACPI_MAX_RAM_SLOTS) {
1524 error_report("unsupported number of memory slots: %"PRIu64,
1525 ms->ram_slots);
1526 exit(EXIT_FAILURE);
1527 }
1528
1529 /*
1530 * We compute the base of the high IO region depending on the
1531 * amount of initial and device memory. The device memory start/size
1532 * is aligned on 1GiB. We never put the high IO region below 256GiB
1533 * so that if maxram_size is < 255GiB we keep the legacy memory map.
1534 * The device region size assumes 1GiB page max alignment per slot.
1535 */
1536 device_memory_base =
1537 ROUND_UP(vms->memmap[VIRT_MEM].base + ms->ram_size, GiB);
1538 device_memory_size = ms->maxram_size - ms->ram_size + ms->ram_slots * GiB;
1539
1540 /* Base address of the high IO region */
1541 base = device_memory_base + ROUND_UP(device_memory_size, GiB);
1542 if (base < device_memory_base) {
1543 error_report("maxmem/slots too huge");
1544 exit(EXIT_FAILURE);
1545 }
1546 if (base < vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES) {
1547 base = vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES;
1548 }
350a9c9e
EA
1549
1550 for (i = VIRT_LOWMEMMAP_LAST; i < ARRAY_SIZE(extended_memmap); i++) {
1551 hwaddr size = extended_memmap[i].size;
1552
1553 base = ROUND_UP(base, size);
1554 vms->memmap[i].base = base;
1555 vms->memmap[i].size = size;
1556 base += size;
1557 }
957e32cf
EA
1558 vms->highest_gpa = base - 1;
1559 if (device_memory_size > 0) {
1560 ms->device_memory = g_malloc0(sizeof(*ms->device_memory));
1561 ms->device_memory->base = device_memory_base;
1562 memory_region_init(&ms->device_memory->mr, OBJECT(vms),
1563 "device-memory", device_memory_size);
1564 }
350a9c9e
EA
1565}
1566
36bf4ec8
EA
1567/*
1568 * finalize_gic_version - Determines the final gic_version
1569 * according to the gic-version property
1570 *
1571 * Default GIC type is v2
1572 */
1573static void finalize_gic_version(VirtMachineState *vms)
1574{
6785aee0
EA
1575 unsigned int max_cpus = MACHINE(vms)->smp.max_cpus;
1576
97b4c918
EA
1577 if (kvm_enabled()) {
1578 int probe_bitmap;
d45efe47 1579
97b4c918
EA
1580 if (!kvm_irqchip_in_kernel()) {
1581 switch (vms->gic_version) {
1582 case VIRT_GIC_VERSION_HOST:
1583 warn_report(
1584 "gic-version=host not relevant with kernel-irqchip=off "
1585 "as only userspace GICv2 is supported. Using v2 ...");
1586 return;
1587 case VIRT_GIC_VERSION_MAX:
1588 case VIRT_GIC_VERSION_NOSEL:
1589 vms->gic_version = VIRT_GIC_VERSION_2;
1590 return;
1591 case VIRT_GIC_VERSION_2:
1592 return;
1593 case VIRT_GIC_VERSION_3:
36bf4ec8 1594 error_report(
97b4c918 1595 "gic-version=3 is not supported with kernel-irqchip=off");
36bf4ec8 1596 exit(1);
97b4c918
EA
1597 }
1598 }
1599
1600 probe_bitmap = kvm_arm_vgic_probe();
1601 if (!probe_bitmap) {
1602 error_report("Unable to determine GIC version supported by host");
1603 exit(1);
1604 }
1605
1606 switch (vms->gic_version) {
1607 case VIRT_GIC_VERSION_HOST:
1608 case VIRT_GIC_VERSION_MAX:
1609 if (probe_bitmap & KVM_ARM_VGIC_V3) {
1610 vms->gic_version = VIRT_GIC_VERSION_3;
d45efe47 1611 } else {
97b4c918 1612 vms->gic_version = VIRT_GIC_VERSION_2;
36bf4ec8 1613 }
97b4c918
EA
1614 return;
1615 case VIRT_GIC_VERSION_NOSEL:
6785aee0
EA
1616 if ((probe_bitmap & KVM_ARM_VGIC_V2) && max_cpus <= GIC_NCPU) {
1617 vms->gic_version = VIRT_GIC_VERSION_2;
1618 } else if (probe_bitmap & KVM_ARM_VGIC_V3) {
1619 /*
1620 * in case the host does not support v2 in-kernel emulation or
1621 * the end-user requested more than 8 VCPUs we now default
1622 * to v3. In any case defaulting to v2 would be broken.
1623 */
1624 vms->gic_version = VIRT_GIC_VERSION_3;
1625 } else if (max_cpus > GIC_NCPU) {
1626 error_report("host only supports in-kernel GICv2 emulation "
1627 "but more than 8 vcpus are requested");
1628 exit(1);
1629 }
97b4c918
EA
1630 break;
1631 case VIRT_GIC_VERSION_2:
1632 case VIRT_GIC_VERSION_3:
1633 break;
1634 }
1635
1636 /* Check chosen version is effectively supported by the host */
1637 if (vms->gic_version == VIRT_GIC_VERSION_2 &&
1638 !(probe_bitmap & KVM_ARM_VGIC_V2)) {
1639 error_report("host does not support in-kernel GICv2 emulation");
1640 exit(1);
1641 } else if (vms->gic_version == VIRT_GIC_VERSION_3 &&
1642 !(probe_bitmap & KVM_ARM_VGIC_V3)) {
1643 error_report("host does not support in-kernel GICv3 emulation");
1644 exit(1);
36bf4ec8 1645 }
97b4c918
EA
1646 return;
1647 }
1648
1649 /* TCG mode */
1650 switch (vms->gic_version) {
1651 case VIRT_GIC_VERSION_NOSEL:
36bf4ec8 1652 vms->gic_version = VIRT_GIC_VERSION_2;
97b4c918
EA
1653 break;
1654 case VIRT_GIC_VERSION_MAX:
1655 vms->gic_version = VIRT_GIC_VERSION_3;
1656 break;
1657 case VIRT_GIC_VERSION_HOST:
1658 error_report("gic-version=host requires KVM");
1659 exit(1);
1660 case VIRT_GIC_VERSION_2:
1661 case VIRT_GIC_VERSION_3:
1662 break;
36bf4ec8
EA
1663 }
1664}
1665
fe11f058
AJ
1666/*
1667 * virt_cpu_post_init() must be called after the CPUs have
1668 * been realized and the GIC has been created.
1669 */
68970d1e
AJ
1670static void virt_cpu_post_init(VirtMachineState *vms, int max_cpus,
1671 MemoryRegion *sysmem)
fe11f058 1672{
68970d1e 1673 bool aarch64, pmu, steal_time;
946f1bb1 1674 CPUState *cpu;
fe11f058
AJ
1675
1676 aarch64 = object_property_get_bool(OBJECT(first_cpu), "aarch64", NULL);
946f1bb1 1677 pmu = object_property_get_bool(OBJECT(first_cpu), "pmu", NULL);
68970d1e
AJ
1678 steal_time = object_property_get_bool(OBJECT(first_cpu),
1679 "kvm-steal-time", NULL);
fe11f058 1680
946f1bb1 1681 if (kvm_enabled()) {
68970d1e
AJ
1682 hwaddr pvtime_reg_base = vms->memmap[VIRT_PVTIME].base;
1683 hwaddr pvtime_reg_size = vms->memmap[VIRT_PVTIME].size;
1684
1685 if (steal_time) {
1686 MemoryRegion *pvtime = g_new(MemoryRegion, 1);
1687 hwaddr pvtime_size = max_cpus * PVTIME_SIZE_PER_CPU;
1688
1689 /* The memory region size must be a multiple of host page size. */
1690 pvtime_size = REAL_HOST_PAGE_ALIGN(pvtime_size);
1691
1692 if (pvtime_size > pvtime_reg_size) {
1693 error_report("pvtime requires a %" HWADDR_PRId
1694 " byte memory region for %d CPUs,"
1695 " but only %" HWADDR_PRId " has been reserved",
1696 pvtime_size, max_cpus, pvtime_reg_size);
1697 exit(1);
1698 }
1699
1700 memory_region_init_ram(pvtime, NULL, "pvtime", pvtime_size, NULL);
1701 memory_region_add_subregion(sysmem, pvtime_reg_base, pvtime);
1702 }
1703
946f1bb1
AJ
1704 CPU_FOREACH(cpu) {
1705 if (pmu) {
1706 assert(arm_feature(&ARM_CPU(cpu)->env, ARM_FEATURE_PMU));
1707 if (kvm_irqchip_in_kernel()) {
1708 kvm_arm_pmu_set_irq(cpu, PPI(VIRTUAL_PMU_IRQ));
1709 }
1710 kvm_arm_pmu_init(cpu);
1711 }
68970d1e
AJ
1712 if (steal_time) {
1713 kvm_arm_pvtime_init(cpu, pvtime_reg_base +
1714 cpu->cpu_index * PVTIME_SIZE_PER_CPU);
1715 }
946f1bb1
AJ
1716 }
1717 } else {
fe11f058
AJ
1718 if (aarch64 && vms->highmem) {
1719 int requested_pa_size = 64 - clz64(vms->highest_gpa);
1720 int pamax = arm_pamax(ARM_CPU(first_cpu));
1721
1722 if (pamax < requested_pa_size) {
1723 error_report("VCPU supports less PA bits (%d) than "
1724 "requested by the memory map (%d)",
1725 pamax, requested_pa_size);
1726 exit(1);
1727 }
1728 }
1729 }
1730}
1731
3ef96221 1732static void machvirt_init(MachineState *machine)
f5fdcd6e 1733{
e5a5604f 1734 VirtMachineState *vms = VIRT_MACHINE(machine);
95eb49c8 1735 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(machine);
17d3d0e2
IM
1736 MachineClass *mc = MACHINE_GET_CLASS(machine);
1737 const CPUArchIdList *possible_cpus;
f5fdcd6e 1738 MemoryRegion *sysmem = get_system_memory();
3df708eb 1739 MemoryRegion *secure_sysmem = NULL;
8bce44a2
RH
1740 MemoryRegion *tag_sysmem = NULL;
1741 MemoryRegion *secure_tag_sysmem = NULL;
7ea686f5 1742 int n, virt_max_cpus;
e0561e60 1743 bool firmware_loaded;
17ec075a 1744 bool aarch64 = true;
cff51ac9 1745 bool has_ged = !vmc->no_ged;
cc7d44c2
LX
1746 unsigned int smp_cpus = machine->smp.cpus;
1747 unsigned int max_cpus = machine->smp.max_cpus;
f5fdcd6e 1748
c9650222
EA
1749 /*
1750 * In accelerated mode, the memory map is computed earlier in kvm_type()
1751 * to create a VM with the right number of IPA bits.
1752 */
1753 if (!vms->memmap) {
1754 virt_set_memmap(vms);
1755 }
350a9c9e 1756
b92ad394
PF
1757 /* We can probe only here because during property set
1758 * KVM is not available yet
1759 */
36bf4ec8 1760 finalize_gic_version(vms);
b92ad394 1761
ba1ba5cc
IM
1762 if (!cpu_type_valid(machine->cpu_type)) {
1763 error_report("mach-virt: CPU type %s not supported", machine->cpu_type);
f5fdcd6e
PM
1764 exit(1);
1765 }
1766
e0561e60
MA
1767 if (vms->secure) {
1768 if (kvm_enabled()) {
1769 error_report("mach-virt: KVM does not support Security extensions");
1770 exit(1);
1771 }
1772
1773 /*
1774 * The Secure view of the world is the same as the NonSecure,
1775 * but with a few extra devices. Create it as a container region
1776 * containing the system memory at low priority; any secure-only
1777 * devices go in at higher priority and take precedence.
1778 */
1779 secure_sysmem = g_new(MemoryRegion, 1);
1780 memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory",
1781 UINT64_MAX);
1782 memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1);
1783 }
1784
1785 firmware_loaded = virt_firmware_init(vms, sysmem,
1786 secure_sysmem ?: sysmem);
1787
4824a61a
PM
1788 /* If we have an EL3 boot ROM then the assumption is that it will
1789 * implement PSCI itself, so disable QEMU's internal implementation
1790 * so it doesn't get in the way. Instead of starting secondary
1791 * CPUs in PSCI powerdown state we will start them all running and
1792 * let the boot ROM sort them out.
f29cacfb
PM
1793 * The usual case is that we do use QEMU's PSCI implementation;
1794 * if the guest has EL2 then we will use SMC as the conduit,
1795 * and otherwise we will use HVC (for backwards compatibility and
1796 * because if we're using KVM then we must use HVC).
4824a61a 1797 */
2013c566
PM
1798 if (vms->secure && firmware_loaded) {
1799 vms->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED;
f29cacfb
PM
1800 } else if (vms->virt) {
1801 vms->psci_conduit = QEMU_PSCI_CONDUIT_SMC;
2013c566
PM
1802 } else {
1803 vms->psci_conduit = QEMU_PSCI_CONDUIT_HVC;
1804 }
4824a61a 1805
4b280b72
AJ
1806 /* The maximum number of CPUs depends on the GIC version, or on how
1807 * many redistributors we can fit into the memory map.
1808 */
d04460e5 1809 if (vms->gic_version == VIRT_GIC_VERSION_3) {
bf424a12
EA
1810 virt_max_cpus =
1811 vms->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE;
1812 virt_max_cpus +=
1813 vms->memmap[VIRT_HIGH_GIC_REDIST2].size / GICV3_REDIST_SIZE;
4b280b72 1814 } else {
7ea686f5 1815 virt_max_cpus = GIC_NCPU;
4b280b72
AJ
1816 }
1817
7ea686f5 1818 if (max_cpus > virt_max_cpus) {
4b280b72
AJ
1819 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs "
1820 "supported by machine 'mach-virt' (%d)",
7ea686f5 1821 max_cpus, virt_max_cpus);
4b280b72
AJ
1822 exit(1);
1823 }
1824
c8ef2bda 1825 vms->smp_cpus = smp_cpus;
f5fdcd6e 1826
f29cacfb
PM
1827 if (vms->virt && kvm_enabled()) {
1828 error_report("mach-virt: KVM does not support providing "
1829 "Virtualization extensions to the guest CPU");
1830 exit(1);
1831 }
1832
7f6185ed
RH
1833 if (vms->mte && kvm_enabled()) {
1834 error_report("mach-virt: KVM does not support providing "
1835 "MTE to the guest CPU");
1836 exit(1);
1837 }
1838
c8ef2bda 1839 create_fdt(vms);
f5fdcd6e 1840
17d3d0e2
IM
1841 possible_cpus = mc->possible_cpu_arch_ids(machine);
1842 for (n = 0; n < possible_cpus->len; n++) {
1843 Object *cpuobj;
d9c34f9c 1844 CPUState *cs;
46de5913 1845
17d3d0e2
IM
1846 if (n >= smp_cpus) {
1847 break;
1848 }
1849
d342eb76 1850 cpuobj = object_new(possible_cpus->cpus[n].type);
5325cc34
MA
1851 object_property_set_int(cpuobj, "mp-affinity",
1852 possible_cpus->cpus[n].arch_id, NULL);
f313369f 1853
d9c34f9c
IM
1854 cs = CPU(cpuobj);
1855 cs->cpu_index = n;
1856
a0ceb640
IM
1857 numa_cpu_pre_plug(&possible_cpus->cpus[cs->cpu_index], DEVICE(cpuobj),
1858 &error_fatal);
bd4c1bfe 1859
17ec075a
EA
1860 aarch64 &= object_property_get_bool(cpuobj, "aarch64", NULL);
1861
e5a5604f 1862 if (!vms->secure) {
5325cc34 1863 object_property_set_bool(cpuobj, "has_el3", false, NULL);
e5a5604f
GB
1864 }
1865
efba1595 1866 if (!vms->virt && object_property_find(cpuobj, "has_el2")) {
5325cc34 1867 object_property_set_bool(cpuobj, "has_el2", false, NULL);
c25bd18a
PM
1868 }
1869
2013c566 1870 if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED) {
5325cc34
MA
1871 object_property_set_int(cpuobj, "psci-conduit", vms->psci_conduit,
1872 NULL);
211b0169 1873
4824a61a
PM
1874 /* Secondary CPUs start in PSCI powered-down state */
1875 if (n > 0) {
5325cc34
MA
1876 object_property_set_bool(cpuobj, "start-powered-off", true,
1877 NULL);
4824a61a 1878 }
f5fdcd6e 1879 }
ba750085 1880
dea101a1 1881 if (vmc->kvm_no_adjvtime &&
efba1595 1882 object_property_find(cpuobj, "kvm-no-adjvtime")) {
5325cc34 1883 object_property_set_bool(cpuobj, "kvm-no-adjvtime", true, NULL);
dea101a1
AJ
1884 }
1885
68970d1e
AJ
1886 if (vmc->no_kvm_steal_time &&
1887 object_property_find(cpuobj, "kvm-steal-time")) {
1888 object_property_set_bool(cpuobj, "kvm-steal-time", false, NULL);
1889 }
1890
efba1595 1891 if (vmc->no_pmu && object_property_find(cpuobj, "pmu")) {
5325cc34 1892 object_property_set_bool(cpuobj, "pmu", false, NULL);
1141d1eb
WH
1893 }
1894
efba1595 1895 if (object_property_find(cpuobj, "reset-cbar")) {
5325cc34
MA
1896 object_property_set_int(cpuobj, "reset-cbar",
1897 vms->memmap[VIRT_CPUPERIPHS].base,
1898 &error_abort);
ba750085
PM
1899 }
1900
5325cc34 1901 object_property_set_link(cpuobj, "memory", OBJECT(sysmem),
1d939a68 1902 &error_abort);
3df708eb 1903 if (vms->secure) {
5325cc34
MA
1904 object_property_set_link(cpuobj, "secure-memory",
1905 OBJECT(secure_sysmem), &error_abort);
3df708eb 1906 }
1d939a68 1907
6f4e1405
RH
1908 if (vms->mte) {
1909 /* Create the memory region only once, but link to all cpus. */
8bce44a2 1910 if (!tag_sysmem) {
6f4e1405
RH
1911 /*
1912 * The property exists only if MemTag is supported.
1913 * If it is, we must allocate the ram to back that up.
1914 */
efba1595 1915 if (!object_property_find(cpuobj, "tag-memory")) {
6f4e1405
RH
1916 error_report("MTE requested, but not supported "
1917 "by the guest CPU");
1918 exit(1);
1919 }
1920
8bce44a2
RH
1921 tag_sysmem = g_new(MemoryRegion, 1);
1922 memory_region_init(tag_sysmem, OBJECT(machine),
1923 "tag-memory", UINT64_MAX / 32);
1924
1925 if (vms->secure) {
1926 secure_tag_sysmem = g_new(MemoryRegion, 1);
1927 memory_region_init(secure_tag_sysmem, OBJECT(machine),
1928 "secure-tag-memory", UINT64_MAX / 32);
1929
1930 /* As with ram, secure-tag takes precedence over tag. */
1931 memory_region_add_subregion_overlap(secure_tag_sysmem, 0,
1932 tag_sysmem, -1);
1933 }
1934 }
1935
5325cc34
MA
1936 object_property_set_link(cpuobj, "tag-memory", OBJECT(tag_sysmem),
1937 &error_abort);
8bce44a2 1938 if (vms->secure) {
5325cc34
MA
1939 object_property_set_link(cpuobj, "secure-tag-memory",
1940 OBJECT(secure_tag_sysmem),
1941 &error_abort);
8bce44a2
RH
1942 }
1943 }
1944
ce189ab2 1945 qdev_realize(DEVICE(cpuobj), NULL, &error_fatal);
dbb74759 1946 object_unref(cpuobj);
f5fdcd6e 1947 }
055a7f2b 1948 fdt_add_timer_nodes(vms);
c8ef2bda 1949 fdt_add_cpu_nodes(vms);
f5fdcd6e 1950
a72f6805
IM
1951 memory_region_add_subregion(sysmem, vms->memmap[VIRT_MEM].base,
1952 machine->ram);
957e32cf
EA
1953 if (machine->device_memory) {
1954 memory_region_add_subregion(sysmem, machine->device_memory->base,
1955 &machine->device_memory->mr);
1956 }
f5fdcd6e 1957
80734cbd 1958 virt_flash_fdt(vms, sysmem, secure_sysmem ?: sysmem);
acf82361 1959
b8b69f4c 1960 create_gic(vms);
f5fdcd6e 1961
68970d1e 1962 virt_cpu_post_init(vms, possible_cpus->len, sysmem);
fe11f058 1963
055a7f2b 1964 fdt_add_pmu_nodes(vms);
01fe6b60 1965
b8b69f4c 1966 create_uart(vms, VIRT_UART, sysmem, serial_hd(0));
3df708eb
PM
1967
1968 if (vms->secure) {
8bce44a2 1969 create_secure_ram(vms, secure_sysmem, secure_tag_sysmem);
b8b69f4c 1970 create_uart(vms, VIRT_SECURE_UART, secure_sysmem, serial_hd(1));
3df708eb 1971 }
f5fdcd6e 1972
8bce44a2
RH
1973 if (tag_sysmem) {
1974 create_tag_ram(tag_sysmem, vms->memmap[VIRT_MEM].base,
1975 machine->ram_size, "mach-virt.tag");
1976 }
1977
17ec075a
EA
1978 vms->highmem_ecam &= vms->highmem && (!firmware_loaded || aarch64);
1979
b8b69f4c 1980 create_rtc(vms);
6e411af9 1981
b8b69f4c 1982 create_pcie(vms);
4ab29b82 1983
17e89077 1984 if (has_ged && aarch64 && firmware_loaded && virt_is_acpi_enabled(vms)) {
b8b69f4c 1985 vms->acpi_dev = create_acpi_ged(vms);
1962f31b 1986 } else {
b8b69f4c 1987 create_gpio(vms);
cff51ac9
SK
1988 }
1989
c345680c
SK
1990 /* connect powerdown request */
1991 vms->powerdown_notifier.notify = virt_powerdown_req;
1992 qemu_register_powerdown_notifier(&vms->powerdown_notifier);
1993
f5fdcd6e
PM
1994 /* Create mmio transports, so the user can create virtio backends
1995 * (which will be automatically plugged in to the transports). If
1996 * no backend is created the transport will just sit harmlessly idle.
1997 */
b8b69f4c 1998 create_virtio_devices(vms);
f5fdcd6e 1999
af1f60a4
AJ
2000 vms->fw_cfg = create_fw_cfg(vms, &address_space_memory);
2001 rom_set_fw(vms->fw_cfg);
d7c2e2db 2002
b8b69f4c 2003 create_platform_bus(vms);
578f3c7b 2004
b5a60bee
KL
2005 if (machine->nvdimms_state->is_enabled) {
2006 const struct AcpiGenericAddress arm_virt_nvdimm_acpi_dsmio = {
2007 .space_id = AML_AS_SYSTEM_MEMORY,
2008 .address = vms->memmap[VIRT_NVDIMM_ACPI].base,
2009 .bit_width = NVDIMM_ACPI_IO_LEN << 3
2010 };
2011
2012 nvdimm_init_acpi_state(machine->nvdimms_state, sysmem,
2013 arm_virt_nvdimm_acpi_dsmio,
2014 vms->fw_cfg, OBJECT(vms));
2015 }
2016
c8ef2bda 2017 vms->bootinfo.ram_size = machine->ram_size;
c8ef2bda
PM
2018 vms->bootinfo.nb_cpus = smp_cpus;
2019 vms->bootinfo.board_id = -1;
2020 vms->bootinfo.loader_start = vms->memmap[VIRT_MEM].base;
2021 vms->bootinfo.get_dtb = machvirt_dtb;
3b77f6c3 2022 vms->bootinfo.skip_dtb_autoload = true;
c8ef2bda 2023 vms->bootinfo.firmware_loaded = firmware_loaded;
2744ece8 2024 arm_load_kernel(ARM_CPU(first_cpu), machine, &vms->bootinfo);
5f7a5a0e 2025
3b77f6c3
IM
2026 vms->machine_done.notify = virt_machine_done;
2027 qemu_add_machine_init_done_notifier(&vms->machine_done);
f5fdcd6e
PM
2028}
2029
083a5890
GB
2030static bool virt_get_secure(Object *obj, Error **errp)
2031{
2032 VirtMachineState *vms = VIRT_MACHINE(obj);
2033
2034 return vms->secure;
2035}
2036
2037static void virt_set_secure(Object *obj, bool value, Error **errp)
2038{
2039 VirtMachineState *vms = VIRT_MACHINE(obj);
2040
2041 vms->secure = value;
2042}
2043
f29cacfb
PM
2044static bool virt_get_virt(Object *obj, Error **errp)
2045{
2046 VirtMachineState *vms = VIRT_MACHINE(obj);
2047
2048 return vms->virt;
2049}
2050
2051static void virt_set_virt(Object *obj, bool value, Error **errp)
2052{
2053 VirtMachineState *vms = VIRT_MACHINE(obj);
2054
2055 vms->virt = value;
2056}
2057
5125f9cd
PF
2058static bool virt_get_highmem(Object *obj, Error **errp)
2059{
2060 VirtMachineState *vms = VIRT_MACHINE(obj);
2061
2062 return vms->highmem;
2063}
2064
2065static void virt_set_highmem(Object *obj, bool value, Error **errp)
2066{
2067 VirtMachineState *vms = VIRT_MACHINE(obj);
2068
2069 vms->highmem = value;
2070}
2071
ccc11b02
EA
2072static bool virt_get_its(Object *obj, Error **errp)
2073{
2074 VirtMachineState *vms = VIRT_MACHINE(obj);
2075
2076 return vms->its;
2077}
2078
2079static void virt_set_its(Object *obj, bool value, Error **errp)
2080{
2081 VirtMachineState *vms = VIRT_MACHINE(obj);
2082
2083 vms->its = value;
2084}
2085
17e89077
GH
2086bool virt_is_acpi_enabled(VirtMachineState *vms)
2087{
2088 if (vms->acpi == ON_OFF_AUTO_OFF) {
2089 return false;
2090 }
2091 return true;
2092}
2093
2094static void virt_get_acpi(Object *obj, Visitor *v, const char *name,
2095 void *opaque, Error **errp)
2096{
2097 VirtMachineState *vms = VIRT_MACHINE(obj);
2098 OnOffAuto acpi = vms->acpi;
2099
2100 visit_type_OnOffAuto(v, name, &acpi, errp);
2101}
2102
2103static void virt_set_acpi(Object *obj, Visitor *v, const char *name,
2104 void *opaque, Error **errp)
2105{
2106 VirtMachineState *vms = VIRT_MACHINE(obj);
2107
2108 visit_type_OnOffAuto(v, name, &vms->acpi, errp);
2109}
2110
2afa8c85
DG
2111static bool virt_get_ras(Object *obj, Error **errp)
2112{
2113 VirtMachineState *vms = VIRT_MACHINE(obj);
2114
2115 return vms->ras;
2116}
2117
2118static void virt_set_ras(Object *obj, bool value, Error **errp)
2119{
2120 VirtMachineState *vms = VIRT_MACHINE(obj);
2121
2122 vms->ras = value;
2123}
2124
6f4e1405
RH
2125static bool virt_get_mte(Object *obj, Error **errp)
2126{
2127 VirtMachineState *vms = VIRT_MACHINE(obj);
2128
2129 return vms->mte;
2130}
2131
2132static void virt_set_mte(Object *obj, bool value, Error **errp)
2133{
2134 VirtMachineState *vms = VIRT_MACHINE(obj);
2135
2136 vms->mte = value;
2137}
2138
b92ad394
PF
2139static char *virt_get_gic_version(Object *obj, Error **errp)
2140{
2141 VirtMachineState *vms = VIRT_MACHINE(obj);
d04460e5 2142 const char *val = vms->gic_version == VIRT_GIC_VERSION_3 ? "3" : "2";
b92ad394
PF
2143
2144 return g_strdup(val);
2145}
2146
2147static void virt_set_gic_version(Object *obj, const char *value, Error **errp)
2148{
2149 VirtMachineState *vms = VIRT_MACHINE(obj);
2150
2151 if (!strcmp(value, "3")) {
d04460e5 2152 vms->gic_version = VIRT_GIC_VERSION_3;
b92ad394 2153 } else if (!strcmp(value, "2")) {
d04460e5 2154 vms->gic_version = VIRT_GIC_VERSION_2;
b92ad394 2155 } else if (!strcmp(value, "host")) {
d04460e5 2156 vms->gic_version = VIRT_GIC_VERSION_HOST; /* Will probe later */
dc16538a 2157 } else if (!strcmp(value, "max")) {
d04460e5 2158 vms->gic_version = VIRT_GIC_VERSION_MAX; /* Will probe later */
b92ad394 2159 } else {
7b55044f 2160 error_setg(errp, "Invalid gic-version value");
dc16538a 2161 error_append_hint(errp, "Valid values are 3, 2, host, max.\n");
b92ad394
PF
2162 }
2163}
2164
e24e3454
EA
2165static char *virt_get_iommu(Object *obj, Error **errp)
2166{
2167 VirtMachineState *vms = VIRT_MACHINE(obj);
2168
2169 switch (vms->iommu) {
2170 case VIRT_IOMMU_NONE:
2171 return g_strdup("none");
2172 case VIRT_IOMMU_SMMUV3:
2173 return g_strdup("smmuv3");
2174 default:
2175 g_assert_not_reached();
2176 }
2177}
2178
2179static void virt_set_iommu(Object *obj, const char *value, Error **errp)
2180{
2181 VirtMachineState *vms = VIRT_MACHINE(obj);
2182
2183 if (!strcmp(value, "smmuv3")) {
2184 vms->iommu = VIRT_IOMMU_SMMUV3;
2185 } else if (!strcmp(value, "none")) {
2186 vms->iommu = VIRT_IOMMU_NONE;
2187 } else {
2188 error_setg(errp, "Invalid iommu value");
2189 error_append_hint(errp, "Valid values are none, smmuv3.\n");
2190 }
2191}
2192
ea089eeb
IM
2193static CpuInstanceProperties
2194virt_cpu_index_to_props(MachineState *ms, unsigned cpu_index)
2195{
2196 MachineClass *mc = MACHINE_GET_CLASS(ms);
2197 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms);
2198
2199 assert(cpu_index < possible_cpus->len);
2200 return possible_cpus->cpus[cpu_index].props;
2201}
2202
79e07936
IM
2203static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx)
2204{
aa570207 2205 return idx % ms->numa_state->num_nodes;
79e07936
IM
2206}
2207
17d3d0e2
IM
2208static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms)
2209{
2210 int n;
cc7d44c2 2211 unsigned int max_cpus = ms->smp.max_cpus;
17d3d0e2
IM
2212 VirtMachineState *vms = VIRT_MACHINE(ms);
2213
2214 if (ms->possible_cpus) {
2215 assert(ms->possible_cpus->len == max_cpus);
2216 return ms->possible_cpus;
2217 }
2218
2219 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
2220 sizeof(CPUArchId) * max_cpus);
2221 ms->possible_cpus->len = max_cpus;
2222 for (n = 0; n < ms->possible_cpus->len; n++) {
d342eb76 2223 ms->possible_cpus->cpus[n].type = ms->cpu_type;
17d3d0e2
IM
2224 ms->possible_cpus->cpus[n].arch_id =
2225 virt_cpu_mp_affinity(vms, n);
2226 ms->possible_cpus->cpus[n].props.has_thread_id = true;
2227 ms->possible_cpus->cpus[n].props.thread_id = n;
17d3d0e2
IM
2228 }
2229 return ms->possible_cpus;
2230}
2231
1f283ae1
EA
2232static void virt_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
2233 Error **errp)
2234{
cff51ac9 2235 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
c2505d1c 2236 const MachineState *ms = MACHINE(hotplug_dev);
cff51ac9 2237 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
1f283ae1 2238
cff51ac9
SK
2239 if (!vms->acpi_dev) {
2240 error_setg(errp,
2241 "memory hotplug is not enabled: missing acpi-ged device");
1f283ae1
EA
2242 return;
2243 }
2244
19bd6aaf
RH
2245 if (vms->mte) {
2246 error_setg(errp, "memory hotplug is not enabled: MTE is enabled");
2247 return;
2248 }
2249
c2505d1c
SK
2250 if (is_nvdimm && !ms->nvdimms_state->is_enabled) {
2251 error_setg(errp, "nvdimm is not enabled: add 'nvdimm=on' to '-M'");
2252 return;
2253 }
2254
1f283ae1
EA
2255 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), NULL, errp);
2256}
2257
2258static void virt_memory_plug(HotplugHandler *hotplug_dev,
2259 DeviceState *dev, Error **errp)
2260{
2261 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
b5a60bee
KL
2262 MachineState *ms = MACHINE(hotplug_dev);
2263 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
1f283ae1 2264
84fd5496 2265 pc_dimm_plug(PC_DIMM(dev), MACHINE(vms));
1f283ae1 2266
b5a60bee
KL
2267 if (is_nvdimm) {
2268 nvdimm_plug(ms->nvdimms_state);
2269 }
2270
53eccc70
KZ
2271 hotplug_handler_plug(HOTPLUG_HANDLER(vms->acpi_dev),
2272 dev, &error_abort);
1f283ae1
EA
2273}
2274
2275static void virt_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev,
2276 DeviceState *dev, Error **errp)
2277{
1b6f99d8
EA
2278 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
2279
1f283ae1
EA
2280 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2281 virt_memory_pre_plug(hotplug_dev, dev, errp);
1b6f99d8
EA
2282 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
2283 hwaddr db_start = 0, db_end = 0;
2284 char *resv_prop_str;
2285
2286 switch (vms->msi_controller) {
2287 case VIRT_MSI_CTRL_NONE:
2288 return;
2289 case VIRT_MSI_CTRL_ITS:
2290 /* GITS_TRANSLATER page */
2291 db_start = base_memmap[VIRT_GIC_ITS].base + 0x10000;
2292 db_end = base_memmap[VIRT_GIC_ITS].base +
2293 base_memmap[VIRT_GIC_ITS].size - 1;
2294 break;
2295 case VIRT_MSI_CTRL_GICV2M:
2296 /* MSI_SETSPI_NS page */
2297 db_start = base_memmap[VIRT_GIC_V2M].base;
2298 db_end = db_start + base_memmap[VIRT_GIC_V2M].size - 1;
2299 break;
2300 }
2301 resv_prop_str = g_strdup_printf("0x%"PRIx64":0x%"PRIx64":%u",
2302 db_start, db_end,
2303 VIRTIO_IOMMU_RESV_MEM_T_MSI);
2304
2305 qdev_prop_set_uint32(dev, "len-reserved-regions", 1);
2306 qdev_prop_set_string(dev, "reserved-regions[0]", resv_prop_str);
2307 g_free(resv_prop_str);
1f283ae1
EA
2308 }
2309}
2310
a3fc8396
IM
2311static void virt_machine_device_plug_cb(HotplugHandler *hotplug_dev,
2312 DeviceState *dev, Error **errp)
2313{
2314 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
2315
2316 if (vms->platform_bus_dev) {
2317 if (object_dynamic_cast(OBJECT(dev), TYPE_SYS_BUS_DEVICE)) {
2318 platform_bus_link_device(PLATFORM_BUS_DEVICE(vms->platform_bus_dev),
2319 SYS_BUS_DEVICE(dev));
2320 }
2321 }
1f283ae1
EA
2322 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2323 virt_memory_plug(hotplug_dev, dev, errp);
2324 }
70e89132
EA
2325 if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
2326 PCIDevice *pdev = PCI_DEVICE(dev);
2327
2328 vms->iommu = VIRT_IOMMU_VIRTIO;
2329 vms->virtio_iommu_bdf = pci_get_bdf(pdev);
0fbddcec 2330 create_virtio_iommu_dt_bindings(vms);
70e89132 2331 }
1f283ae1
EA
2332}
2333
539533b8
SK
2334static void virt_dimm_unplug_request(HotplugHandler *hotplug_dev,
2335 DeviceState *dev, Error **errp)
2336{
2337 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
2338 Error *local_err = NULL;
2339
2340 if (!vms->acpi_dev) {
2341 error_setg(&local_err,
2342 "memory hotplug is not enabled: missing acpi-ged device");
2343 goto out;
2344 }
2345
2346 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) {
2347 error_setg(&local_err,
2348 "nvdimm device hot unplug is not supported yet.");
2349 goto out;
2350 }
2351
2352 hotplug_handler_unplug_request(HOTPLUG_HANDLER(vms->acpi_dev), dev,
2353 &local_err);
2354out:
2355 error_propagate(errp, local_err);
2356}
2357
2358static void virt_dimm_unplug(HotplugHandler *hotplug_dev,
2359 DeviceState *dev, Error **errp)
2360{
2361 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
2362 Error *local_err = NULL;
2363
2364 hotplug_handler_unplug(HOTPLUG_HANDLER(vms->acpi_dev), dev, &local_err);
2365 if (local_err) {
2366 goto out;
2367 }
2368
2369 pc_dimm_unplug(PC_DIMM(dev), MACHINE(vms));
2370 qdev_unrealize(dev);
2371
2372out:
2373 error_propagate(errp, local_err);
2374}
2375
1f283ae1
EA
2376static void virt_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev,
2377 DeviceState *dev, Error **errp)
2378{
539533b8
SK
2379 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2380 virt_dimm_unplug_request(hotplug_dev, dev, errp);
2381 } else {
2382 error_setg(errp, "device unplug request for unsupported device"
2383 " type: %s", object_get_typename(OBJECT(dev)));
2384 }
2385}
2386
2387static void virt_machine_device_unplug_cb(HotplugHandler *hotplug_dev,
2388 DeviceState *dev, Error **errp)
2389{
2390 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2391 virt_dimm_unplug(hotplug_dev, dev, errp);
2392 } else {
2393 error_setg(errp, "virt: device unplug for unsupported device"
2394 " type: %s", object_get_typename(OBJECT(dev)));
2395 }
a3fc8396
IM
2396}
2397
2398static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine,
2399 DeviceState *dev)
2400{
1f283ae1
EA
2401 if (object_dynamic_cast(OBJECT(dev), TYPE_SYS_BUS_DEVICE) ||
2402 (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM))) {
a3fc8396
IM
2403 return HOTPLUG_HANDLER(machine);
2404 }
70e89132
EA
2405 if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
2406 VirtMachineState *vms = VIRT_MACHINE(machine);
a3fc8396 2407
17e89077 2408 if (!vms->bootinfo.firmware_loaded || !virt_is_acpi_enabled(vms)) {
70e89132
EA
2409 return HOTPLUG_HANDLER(machine);
2410 }
2411 }
a3fc8396
IM
2412 return NULL;
2413}
2414
c9650222
EA
2415/*
2416 * for arm64 kvm_type [7-0] encodes the requested number of bits
2417 * in the IPA address space
2418 */
2419static int virt_kvm_type(MachineState *ms, const char *type_str)
2420{
2421 VirtMachineState *vms = VIRT_MACHINE(ms);
2422 int max_vm_pa_size = kvm_arm_get_max_vm_ipa_size(ms);
2423 int requested_pa_size;
2424
2425 /* we freeze the memory map to compute the highest gpa */
2426 virt_set_memmap(vms);
2427
2428 requested_pa_size = 64 - clz64(vms->highest_gpa);
2429
2430 if (requested_pa_size > max_vm_pa_size) {
2431 error_report("-m and ,maxmem option values "
2432 "require an IPA range (%d bits) larger than "
2433 "the one supported by the host (%d bits)",
2434 requested_pa_size, max_vm_pa_size);
2435 exit(1);
2436 }
2437 /*
2438 * By default we return 0 which corresponds to an implicit legacy
2439 * 40b IPA setting. Otherwise we return the actual requested PA
2440 * logsize
2441 */
2442 return requested_pa_size > 40 ? requested_pa_size : 0;
2443}
2444
ed796373
WH
2445static void virt_machine_class_init(ObjectClass *oc, void *data)
2446{
9c94d8e6 2447 MachineClass *mc = MACHINE_CLASS(oc);
a3fc8396 2448 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
9c94d8e6
WH
2449
2450 mc->init = machvirt_init;
b10fbd53
EA
2451 /* Start with max_cpus set to 512, which is the maximum supported by KVM.
2452 * The value may be reduced later when we have more information about the
9c94d8e6
WH
2453 * configuration of the particular instance.
2454 */
b10fbd53 2455 mc->max_cpus = 512;
6f2062b9
EH
2456 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_CALXEDA_XGMAC);
2457 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_AMD_XGBE);
94692dcd 2458 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE);
4ebc0b61 2459 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_PLATFORM);
c294ac32 2460 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS);
9c94d8e6
WH
2461 mc->block_default_type = IF_VIRTIO;
2462 mc->no_cdrom = 1;
2463 mc->pci_allow_0_address = true;
a2519ad1
PM
2464 /* We know we will never create a pre-ARMv7 CPU which needs 1K pages */
2465 mc->minimum_page_bits = 12;
17d3d0e2 2466 mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids;
ea089eeb 2467 mc->cpu_index_to_instance_props = virt_cpu_index_to_props;
ba1ba5cc 2468 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15");
79e07936 2469 mc->get_default_cpu_node_id = virt_get_default_cpu_node_id;
c9650222 2470 mc->kvm_type = virt_kvm_type;
debbdc00 2471 assert(!mc->get_hotplug_handler);
a3fc8396 2472 mc->get_hotplug_handler = virt_machine_get_hotplug_handler;
1f283ae1 2473 hc->pre_plug = virt_machine_device_pre_plug_cb;
a3fc8396 2474 hc->plug = virt_machine_device_plug_cb;
1f283ae1 2475 hc->unplug_request = virt_machine_device_unplug_request_cb;
539533b8 2476 hc->unplug = virt_machine_device_unplug_cb;
c2505d1c 2477 mc->nvdimm_supported = true;
442da7dc 2478 mc->auto_enable_numa_with_memhp = true;
195784a0 2479 mc->auto_enable_numa_with_memdev = true;
a72f6805 2480 mc->default_ram_id = "mach-virt.ram";
17e89077
GH
2481
2482 object_class_property_add(oc, "acpi", "OnOffAuto",
2483 virt_get_acpi, virt_set_acpi,
d2623129 2484 NULL, NULL);
17e89077 2485 object_class_property_set_description(oc, "acpi",
7eecec7d 2486 "Enable ACPI");
ed796373
WH
2487}
2488
95159760 2489static void virt_instance_init(Object *obj)
083a5890
GB
2490{
2491 VirtMachineState *vms = VIRT_MACHINE(obj);
ccc11b02 2492 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
083a5890 2493
2d710006
PM
2494 /* EL3 is disabled by default on virt: this makes us consistent
2495 * between KVM and TCG for this board, and it also allows us to
2496 * boot UEFI blobs which assume no TrustZone support.
2497 */
2498 vms->secure = false;
083a5890 2499 object_property_add_bool(obj, "secure", virt_get_secure,
d2623129 2500 virt_set_secure);
083a5890
GB
2501 object_property_set_description(obj, "secure",
2502 "Set on/off to enable/disable the ARM "
7eecec7d 2503 "Security Extensions (TrustZone)");
5125f9cd 2504
f29cacfb
PM
2505 /* EL2 is also disabled by default, for similar reasons */
2506 vms->virt = false;
2507 object_property_add_bool(obj, "virtualization", virt_get_virt,
d2623129 2508 virt_set_virt);
f29cacfb
PM
2509 object_property_set_description(obj, "virtualization",
2510 "Set on/off to enable/disable emulating a "
2511 "guest CPU which implements the ARM "
7eecec7d 2512 "Virtualization Extensions");
f29cacfb 2513
5125f9cd
PF
2514 /* High memory is enabled by default */
2515 vms->highmem = true;
2516 object_property_add_bool(obj, "highmem", virt_get_highmem,
d2623129 2517 virt_set_highmem);
5125f9cd
PF
2518 object_property_set_description(obj, "highmem",
2519 "Set on/off to enable/disable using "
7eecec7d 2520 "physical address space above 32 bits");
36bf4ec8 2521 vms->gic_version = VIRT_GIC_VERSION_NOSEL;
b92ad394 2522 object_property_add_str(obj, "gic-version", virt_get_gic_version,
d2623129 2523 virt_set_gic_version);
b92ad394
PF
2524 object_property_set_description(obj, "gic-version",
2525 "Set GIC version. "
7eecec7d 2526 "Valid values are 2, 3, host and max");
9ac4ef77 2527
17ec075a
EA
2528 vms->highmem_ecam = !vmc->no_highmem_ecam;
2529
ccc11b02
EA
2530 if (vmc->no_its) {
2531 vms->its = false;
2532 } else {
2533 /* Default allows ITS instantiation */
2534 vms->its = true;
2535 object_property_add_bool(obj, "its", virt_get_its,
d2623129 2536 virt_set_its);
ccc11b02
EA
2537 object_property_set_description(obj, "its",
2538 "Set on/off to enable/disable "
7eecec7d 2539 "ITS instantiation");
ccc11b02
EA
2540 }
2541
e24e3454
EA
2542 /* Default disallows iommu instantiation */
2543 vms->iommu = VIRT_IOMMU_NONE;
d2623129 2544 object_property_add_str(obj, "iommu", virt_get_iommu, virt_set_iommu);
e24e3454
EA
2545 object_property_set_description(obj, "iommu",
2546 "Set the IOMMU type. "
7eecec7d 2547 "Valid values are none and smmuv3");
e24e3454 2548
2afa8c85
DG
2549 /* Default disallows RAS instantiation */
2550 vms->ras = false;
2551 object_property_add_bool(obj, "ras", virt_get_ras,
d2623129 2552 virt_set_ras);
2afa8c85
DG
2553 object_property_set_description(obj, "ras",
2554 "Set on/off to enable/disable reporting host memory errors "
7eecec7d 2555 "to a KVM guest using ACPI and guest external abort exceptions");
2afa8c85 2556
6f4e1405
RH
2557 /* MTE is disabled by default. */
2558 vms->mte = false;
2559 object_property_add_bool(obj, "mte", virt_get_mte, virt_set_mte);
2560 object_property_set_description(obj, "mte",
2561 "Set on/off to enable/disable emulating a "
2562 "guest CPU which implements the ARM "
2563 "Memory Tagging Extension");
2564
9ac4ef77 2565 vms->irqmap = a15irqmap;
e0561e60
MA
2566
2567 virt_flash_create(vms);
083a5890
GB
2568}
2569
95159760
EH
2570static const TypeInfo virt_machine_info = {
2571 .name = TYPE_VIRT_MACHINE,
2572 .parent = TYPE_MACHINE,
2573 .abstract = true,
2574 .instance_size = sizeof(VirtMachineState),
2575 .class_size = sizeof(VirtMachineClass),
2576 .class_init = virt_machine_class_init,
bbac02f1 2577 .instance_init = virt_instance_init,
95159760
EH
2578 .interfaces = (InterfaceInfo[]) {
2579 { TYPE_HOTPLUG_HANDLER },
2580 { }
2581 },
2582};
2583
2584static void machvirt_machine_init(void)
2585{
2586 type_register_static(&virt_machine_info);
2587}
2588type_init(machvirt_machine_init);
2589
3ff3c5d3
CH
2590static void virt_machine_5_2_options(MachineClass *mc)
2591{
2592}
2593DEFINE_VIRT_MACHINE_AS_LATEST(5, 2)
2594
541aaa1d
CH
2595static void virt_machine_5_1_options(MachineClass *mc)
2596{
68970d1e
AJ
2597 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
2598
3ff3c5d3
CH
2599 virt_machine_5_2_options(mc);
2600 compat_props_add(mc->compat_props, hw_compat_5_1, hw_compat_5_1_len);
68970d1e 2601 vmc->no_kvm_steal_time = true;
541aaa1d 2602}
3ff3c5d3 2603DEFINE_VIRT_MACHINE(5, 1)
541aaa1d 2604
3eb74d20
CH
2605static void virt_machine_5_0_options(MachineClass *mc)
2606{
2c1fb4d5
AJ
2607 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
2608
541aaa1d 2609 virt_machine_5_1_options(mc);
c6228807 2610 compat_props_add(mc->compat_props, hw_compat_5_0, hw_compat_5_0_len);
32a354dc 2611 mc->numa_mem_supported = true;
2c1fb4d5 2612 vmc->acpi_expose_flash = true;
195784a0 2613 mc->auto_enable_numa_with_memdev = false;
3eb74d20 2614}
541aaa1d 2615DEFINE_VIRT_MACHINE(5, 0)
3eb74d20 2616
9aec2e52
CH
2617static void virt_machine_4_2_options(MachineClass *mc)
2618{
dea101a1
AJ
2619 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
2620
fa7c8e92 2621 virt_machine_5_0_options(mc);
5f258577 2622 compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len);
dea101a1 2623 vmc->kvm_no_adjvtime = true;
9aec2e52 2624}
3eb74d20 2625DEFINE_VIRT_MACHINE(4, 2)
9aec2e52 2626
9bf2650b
CH
2627static void virt_machine_4_1_options(MachineClass *mc)
2628{
cff51ac9
SK
2629 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
2630
9aec2e52
CH
2631 virt_machine_4_2_options(mc);
2632 compat_props_add(mc->compat_props, hw_compat_4_1, hw_compat_4_1_len);
cff51ac9 2633 vmc->no_ged = true;
442da7dc 2634 mc->auto_enable_numa_with_memhp = false;
9bf2650b 2635}
9aec2e52 2636DEFINE_VIRT_MACHINE(4, 1)
9bf2650b 2637
84e060bf
AW
2638static void virt_machine_4_0_options(MachineClass *mc)
2639{
9bf2650b
CH
2640 virt_machine_4_1_options(mc);
2641 compat_props_add(mc->compat_props, hw_compat_4_0, hw_compat_4_0_len);
84e060bf 2642}
9bf2650b 2643DEFINE_VIRT_MACHINE(4, 0)
84e060bf 2644
22907d2b
AJ
2645static void virt_machine_3_1_options(MachineClass *mc)
2646{
84e060bf 2647 virt_machine_4_0_options(mc);
abd93cc7 2648 compat_props_add(mc->compat_props, hw_compat_3_1, hw_compat_3_1_len);
22907d2b 2649}
84e060bf 2650DEFINE_VIRT_MACHINE(3, 1)
22907d2b 2651
8ae9a1ca
EA
2652static void virt_machine_3_0_options(MachineClass *mc)
2653{
22907d2b 2654 virt_machine_3_1_options(mc);
ddb3235d 2655 compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len);
8ae9a1ca 2656}
22907d2b
AJ
2657DEFINE_VIRT_MACHINE(3, 0)
2658
a2a05159
PM
2659static void virt_machine_2_12_options(MachineClass *mc)
2660{
17ec075a
EA
2661 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
2662
8ae9a1ca 2663 virt_machine_3_0_options(mc);
0d47310b 2664 compat_props_add(mc->compat_props, hw_compat_2_12, hw_compat_2_12_len);
17ec075a 2665 vmc->no_highmem_ecam = true;
b10fbd53 2666 mc->max_cpus = 255;
a2a05159 2667}
8ae9a1ca 2668DEFINE_VIRT_MACHINE(2, 12)
a2a05159 2669
79283dda
EA
2670static void virt_machine_2_11_options(MachineClass *mc)
2671{
dfadc3bf
WH
2672 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
2673
a2a05159 2674 virt_machine_2_12_options(mc);
43df70a9 2675 compat_props_add(mc->compat_props, hw_compat_2_11, hw_compat_2_11_len);
dfadc3bf 2676 vmc->smbios_old_sys_ver = true;
79283dda 2677}
a2a05159 2678DEFINE_VIRT_MACHINE(2, 11)
79283dda 2679
f22ab6cb
EA
2680static void virt_machine_2_10_options(MachineClass *mc)
2681{
79283dda 2682 virt_machine_2_11_options(mc);
503224f4 2683 compat_props_add(mc->compat_props, hw_compat_2_10, hw_compat_2_10_len);
846690de
PM
2684 /* before 2.11 we never faulted accesses to bad addresses */
2685 mc->ignore_memory_transaction_failures = true;
f22ab6cb 2686}
79283dda 2687DEFINE_VIRT_MACHINE(2, 10)
f22ab6cb 2688
e353aac5
PM
2689static void virt_machine_2_9_options(MachineClass *mc)
2690{
f22ab6cb 2691 virt_machine_2_10_options(mc);
3e803152 2692 compat_props_add(mc->compat_props, hw_compat_2_9, hw_compat_2_9_len);
e353aac5 2693}
f22ab6cb 2694DEFINE_VIRT_MACHINE(2, 9)
e353aac5 2695
96b0439b
AJ
2696static void virt_machine_2_8_options(MachineClass *mc)
2697{
156bc9a5
PM
2698 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
2699
e353aac5 2700 virt_machine_2_9_options(mc);
edc24ccd 2701 compat_props_add(mc->compat_props, hw_compat_2_8, hw_compat_2_8_len);
156bc9a5
PM
2702 /* For 2.8 and earlier we falsely claimed in the DT that
2703 * our timers were edge-triggered, not level-triggered.
2704 */
2705 vmc->claim_edge_triggered_timers = true;
96b0439b 2706}
e353aac5 2707DEFINE_VIRT_MACHINE(2, 8)
96b0439b 2708
1287f2b3
AJ
2709static void virt_machine_2_7_options(MachineClass *mc)
2710{
2231f69b
AJ
2711 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
2712
96b0439b 2713 virt_machine_2_8_options(mc);
5a995064 2714 compat_props_add(mc->compat_props, hw_compat_2_7, hw_compat_2_7_len);
2231f69b
AJ
2715 /* ITS was introduced with 2.8 */
2716 vmc->no_its = true;
a2519ad1
PM
2717 /* Stick with 1K pages for migration compatibility */
2718 mc->minimum_page_bits = 0;
1287f2b3 2719}
96b0439b 2720DEFINE_VIRT_MACHINE(2, 7)
1287f2b3 2721
ab093c3c 2722static void virt_machine_2_6_options(MachineClass *mc)
c2919690 2723{
95eb49c8
AJ
2724 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
2725
1287f2b3 2726 virt_machine_2_7_options(mc);
ff8f261f 2727 compat_props_add(mc->compat_props, hw_compat_2_6, hw_compat_2_6_len);
95eb49c8 2728 vmc->disallow_affinity_adjustment = true;
1141d1eb
WH
2729 /* Disable PMU for 2.6 as PMU support was first introduced in 2.7 */
2730 vmc->no_pmu = true;
c2919690 2731}
1287f2b3 2732DEFINE_VIRT_MACHINE(2, 6)
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