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[linux.git] / drivers / char / rocket.c
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1da177e4
LT		 1/*
2 * RocketPort device driver for Linux
3 *
4 * Written by Theodore Ts'o, 1995, 1996, 1997, 1998, 1999, 2000.
5 *
6 * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2000, 2003 by Comtrol, Inc.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of the
11 * License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23/*
24 * Kernel Synchronization:
25 *
26 * This driver has 2 kernel control paths - exception handlers (calls into the driver
27 * from user mode) and the timer bottom half (tasklet). This is a polled driver, interrupts
28 * are not used.
29 *
30 * Critical data:
31 * - rp_table[], accessed through passed "info" pointers, is a global (static) array of
32 * serial port state information and the xmit_buf circular buffer. Protected by
33 * a per port spinlock.
34 * - xmit_flags[], an array of ints indexed by line (port) number, indicating that there
35 * is data to be transmitted. Protected by atomic bit operations.
36 * - rp_num_ports, int indicating number of open ports, protected by atomic operations.
37 *
38 * rp_write() and rp_write_char() functions use a per port semaphore to protect against
39 * simultaneous access to the same port by more than one process.
40 */
41
42/****** Defines ******/
1da177e4
LT		 43#define ROCKET_PARANOIA_CHECK
44#define ROCKET_DISABLE_SIMUSAGE
45
46#undef ROCKET_SOFT_FLOW
47#undef ROCKET_DEBUG_OPEN
48#undef ROCKET_DEBUG_INTR
49#undef ROCKET_DEBUG_WRITE
50#undef ROCKET_DEBUG_FLOW
51#undef ROCKET_DEBUG_THROTTLE
52#undef ROCKET_DEBUG_WAIT_UNTIL_SENT
53#undef ROCKET_DEBUG_RECEIVE
54#undef ROCKET_DEBUG_HANGUP
55#undef REV_PCI_ORDER
56#undef ROCKET_DEBUG_IO
57
58#define POLL_PERIOD HZ/100 /* Polling period .01 seconds (10ms) */
59
60/****** Kernel includes ******/
61
1da177e4
LT		 62#include <linux/module.h>
63#include <linux/errno.h>
64#include <linux/major.h>
65#include <linux/kernel.h>
66#include <linux/signal.h>
67#include <linux/slab.h>
68#include <linux/mm.h>
69#include <linux/sched.h>
70#include <linux/timer.h>
71#include <linux/interrupt.h>
72#include <linux/tty.h>
73#include <linux/tty_driver.h>
74#include <linux/tty_flip.h>
44b7d1b3 75#include <linux/serial.h>
1da177e4
LT		 76#include <linux/string.h>
77#include <linux/fcntl.h>
78#include <linux/ptrace.h>
69f545ea 79#include <linux/mutex.h>
1da177e4
LT		 80#include <linux/ioport.h>
81#include <linux/delay.h>
8cf5a8c5 82#include <linux/completion.h>
1da177e4
LT		 83#include <linux/wait.h>
84#include <linux/pci.h>
44b7d1b3 85#include <linux/uaccess.h>
1da177e4 86#include <asm/atomic.h>
457fb605 87#include <asm/unaligned.h>
1da177e4
LT		 88#include <linux/bitops.h>
89#include <linux/spinlock.h>
1da177e4
LT		 90#include <linux/init.h>
91
92/****** RocketPort includes ******/
93
94#include "rocket_int.h"
95#include "rocket.h"
96
97#define ROCKET_VERSION "2.09"
98#define ROCKET_DATE "12-June-2003"
99
100/****** RocketPort Local Variables ******/
101
40565f19
JS		 102static void rp_do_poll(unsigned long dummy);
103
1da177e4
LT		 104static struct tty_driver *rocket_driver;
105
106static struct rocket_version driver_version = {
107 ROCKET_VERSION, ROCKET_DATE
108};
109
110static struct r_port *rp_table[MAX_RP_PORTS]; /* The main repository of serial port state information. */
111static unsigned int xmit_flags[NUM_BOARDS]; /* Bit significant, indicates port had data to transmit. */
112 /* eg. Bit 0 indicates port 0 has xmit data, ... */
113static atomic_t rp_num_ports_open; /* Number of serial ports open */
40565f19 114static DEFINE_TIMER(rocket_timer, rp_do_poll, 0, 0);
1da177e4
LT		 115
116static unsigned long board1; /* ISA addresses, retrieved from rocketport.conf */
117static unsigned long board2;
118static unsigned long board3;
119static unsigned long board4;
120static unsigned long controller;
121static int support_low_speed;
122static unsigned long modem1;
123static unsigned long modem2;
124static unsigned long modem3;
125static unsigned long modem4;
126static unsigned long pc104_1[8];
127static unsigned long pc104_2[8];
128static unsigned long pc104_3[8];
129static unsigned long pc104_4[8];
130static unsigned long *pc104[4] = { pc104_1, pc104_2, pc104_3, pc104_4 };
131
132static int rp_baud_base[NUM_BOARDS]; /* Board config info (Someday make a per-board structure) */
133static unsigned long rcktpt_io_addr[NUM_BOARDS];
134static int rcktpt_type[NUM_BOARDS];
135static int is_PCI[NUM_BOARDS];
136static rocketModel_t rocketModel[NUM_BOARDS];
137static int max_board;
31f35939 138static const struct tty_port_operations rocket_port_ops;
1da177e4
LT		 139
140/*
141 * The following arrays define the interrupt bits corresponding to each AIOP.
142 * These bits are different between the ISA and regular PCI boards and the
143 * Universal PCI boards.
144 */
145
146static Word_t aiop_intr_bits[AIOP_CTL_SIZE] = {
147 AIOP_INTR_BIT_0,
148 AIOP_INTR_BIT_1,
149 AIOP_INTR_BIT_2,
150 AIOP_INTR_BIT_3
151};
152
153static Word_t upci_aiop_intr_bits[AIOP_CTL_SIZE] = {
154 UPCI_AIOP_INTR_BIT_0,
155 UPCI_AIOP_INTR_BIT_1,
156 UPCI_AIOP_INTR_BIT_2,
157 UPCI_AIOP_INTR_BIT_3
158};
159
f15313bf
AB		 160static Byte_t RData[RDATASIZE] = {
161 0x00, 0x09, 0xf6, 0x82,
162 0x02, 0x09, 0x86, 0xfb,
163 0x04, 0x09, 0x00, 0x0a,
164 0x06, 0x09, 0x01, 0x0a,
165 0x08, 0x09, 0x8a, 0x13,
166 0x0a, 0x09, 0xc5, 0x11,
167 0x0c, 0x09, 0x86, 0x85,
168 0x0e, 0x09, 0x20, 0x0a,
169 0x10, 0x09, 0x21, 0x0a,
170 0x12, 0x09, 0x41, 0xff,
171 0x14, 0x09, 0x82, 0x00,
172 0x16, 0x09, 0x82, 0x7b,
173 0x18, 0x09, 0x8a, 0x7d,
174 0x1a, 0x09, 0x88, 0x81,
175 0x1c, 0x09, 0x86, 0x7a,
176 0x1e, 0x09, 0x84, 0x81,
177 0x20, 0x09, 0x82, 0x7c,
178 0x22, 0x09, 0x0a, 0x0a
179};
180
181static Byte_t RRegData[RREGDATASIZE] = {
182 0x00, 0x09, 0xf6, 0x82, /* 00: Stop Rx processor */
183 0x08, 0x09, 0x8a, 0x13, /* 04: Tx software flow control */
184 0x0a, 0x09, 0xc5, 0x11, /* 08: XON char */
185 0x0c, 0x09, 0x86, 0x85, /* 0c: XANY */
186 0x12, 0x09, 0x41, 0xff, /* 10: Rx mask char */
187 0x14, 0x09, 0x82, 0x00, /* 14: Compare/Ignore #0 */
188 0x16, 0x09, 0x82, 0x7b, /* 18: Compare #1 */
189 0x18, 0x09, 0x8a, 0x7d, /* 1c: Compare #2 */
190 0x1a, 0x09, 0x88, 0x81, /* 20: Interrupt #1 */
191 0x1c, 0x09, 0x86, 0x7a, /* 24: Ignore/Replace #1 */
192 0x1e, 0x09, 0x84, 0x81, /* 28: Interrupt #2 */
193 0x20, 0x09, 0x82, 0x7c, /* 2c: Ignore/Replace #2 */
194 0x22, 0x09, 0x0a, 0x0a /* 30: Rx FIFO Enable */
195};
196
197static CONTROLLER_T sController[CTL_SIZE] = {
198 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
199 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
200 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
201 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
202 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
203 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
204 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
205 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}}
206};
207
208static Byte_t sBitMapClrTbl[8] = {
209 0xfe, 0xfd, 0xfb, 0xf7, 0xef, 0xdf, 0xbf, 0x7f
210};
211
212static Byte_t sBitMapSetTbl[8] = {
213 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80
214};
215
216static int sClockPrescale = 0x14;
217
1da177e4
LT		 218/*
219 * Line number is the ttySIx number (x), the Minor number. We
220 * assign them sequentially, starting at zero. The following
221 * array keeps track of the line number assigned to a given board/aiop/channel.
222 */
223static unsigned char lineNumbers[MAX_RP_PORTS];
224static unsigned long nextLineNumber;
225
226/***** RocketPort Static Prototypes *********/
227static int __init init_ISA(int i);
228static void rp_wait_until_sent(struct tty_struct *tty, int timeout);
229static void rp_flush_buffer(struct tty_struct *tty);
230static void rmSpeakerReset(CONTROLLER_T * CtlP, unsigned long model);
231static unsigned char GetLineNumber(int ctrl, int aiop, int ch);
232static unsigned char SetLineNumber(int ctrl, int aiop, int ch);
233static void rp_start(struct tty_struct *tty);
f15313bf
AB		 234static int sInitChan(CONTROLLER_T * CtlP, CHANNEL_T * ChP, int AiopNum,
235 int ChanNum);
236static void sSetInterfaceMode(CHANNEL_T * ChP, Byte_t mode);
237static void sFlushRxFIFO(CHANNEL_T * ChP);
238static void sFlushTxFIFO(CHANNEL_T * ChP);
239static void sEnInterrupts(CHANNEL_T * ChP, Word_t Flags);
240static void sDisInterrupts(CHANNEL_T * ChP, Word_t Flags);
241static void sModemReset(CONTROLLER_T * CtlP, int chan, int on);
242static void sPCIModemReset(CONTROLLER_T * CtlP, int chan, int on);
243static int sWriteTxPrioByte(CHANNEL_T * ChP, Byte_t Data);
244static int sPCIInitController(CONTROLLER_T * CtlP, int CtlNum,
245 ByteIO_t * AiopIOList, int AiopIOListSize,
246 WordIO_t ConfigIO, int IRQNum, Byte_t Frequency,
247 int PeriodicOnly, int altChanRingIndicator,
248 int UPCIRingInd);
249static int sInitController(CONTROLLER_T * CtlP, int CtlNum, ByteIO_t MudbacIO,
250 ByteIO_t * AiopIOList, int AiopIOListSize,
251 int IRQNum, Byte_t Frequency, int PeriodicOnly);
252static int sReadAiopID(ByteIO_t io);
253static int sReadAiopNumChan(WordIO_t io);
1da177e4 254
1da177e4
LT		 255MODULE_AUTHOR("Theodore Ts'o");
256MODULE_DESCRIPTION("Comtrol RocketPort driver");
257module_param(board1, ulong, 0);
258MODULE_PARM_DESC(board1, "I/O port for (ISA) board #1");
259module_param(board2, ulong, 0);
260MODULE_PARM_DESC(board2, "I/O port for (ISA) board #2");
261module_param(board3, ulong, 0);
262MODULE_PARM_DESC(board3, "I/O port for (ISA) board #3");
263module_param(board4, ulong, 0);
264MODULE_PARM_DESC(board4, "I/O port for (ISA) board #4");
265module_param(controller, ulong, 0);
266MODULE_PARM_DESC(controller, "I/O port for (ISA) rocketport controller");
267module_param(support_low_speed, bool, 0);
268MODULE_PARM_DESC(support_low_speed, "1 means support 50 baud, 0 means support 460400 baud");
269module_param(modem1, ulong, 0);
270MODULE_PARM_DESC(modem1, "1 means (ISA) board #1 is a RocketModem");
271module_param(modem2, ulong, 0);
272MODULE_PARM_DESC(modem2, "1 means (ISA) board #2 is a RocketModem");
273module_param(modem3, ulong, 0);
274MODULE_PARM_DESC(modem3, "1 means (ISA) board #3 is a RocketModem");
275module_param(modem4, ulong, 0);
276MODULE_PARM_DESC(modem4, "1 means (ISA) board #4 is a RocketModem");
277module_param_array(pc104_1, ulong, NULL, 0);
278MODULE_PARM_DESC(pc104_1, "set interface types for ISA(PC104) board #1 (e.g. pc104_1=232,232,485,485,...");
279module_param_array(pc104_2, ulong, NULL, 0);
280MODULE_PARM_DESC(pc104_2, "set interface types for ISA(PC104) board #2 (e.g. pc104_2=232,232,485,485,...");
281module_param_array(pc104_3, ulong, NULL, 0);
282MODULE_PARM_DESC(pc104_3, "set interface types for ISA(PC104) board #3 (e.g. pc104_3=232,232,485,485,...");
283module_param_array(pc104_4, ulong, NULL, 0);
284MODULE_PARM_DESC(pc104_4, "set interface types for ISA(PC104) board #4 (e.g. pc104_4=232,232,485,485,...");
285
d269cdd0 286static int rp_init(void);
1da177e4
LT		 287static void rp_cleanup_module(void);
288
289module_init(rp_init);
290module_exit(rp_cleanup_module);
291
1da177e4 292
1da177e4 293MODULE_LICENSE("Dual BSD/GPL");
1da177e4
LT		 294
295/*************************************************************************/
296/* Module code starts here */
297
298static inline int rocket_paranoia_check(struct r_port *info,
299 const char *routine)
300{
301#ifdef ROCKET_PARANOIA_CHECK
302 if (!info)
303 return 1;
304 if (info->magic != RPORT_MAGIC) {
68562b79
JS		 305 printk(KERN_WARNING "Warning: bad magic number for rocketport "
306 "struct in %s\n", routine);
1da177e4
LT		 307 return 1;
308 }
309#endif
310 return 0;
311}
312
313
314/* Serial port receive data function. Called (from timer poll) when an AIOPIC signals
315 * that receive data is present on a serial port. Pulls data from FIFO, moves it into the
316 * tty layer.
317 */
318static void rp_do_receive(struct r_port *info,
319 struct tty_struct *tty,
320 CHANNEL_t * cp, unsigned int ChanStatus)
321{
322 unsigned int CharNStat;
cc44a817
PF		 323 int ToRecv, wRecv, space;
324 unsigned char *cbuf;
1da177e4
LT		 325
326 ToRecv = sGetRxCnt(cp);
1da177e4 327#ifdef ROCKET_DEBUG_INTR
68562b79 328 printk(KERN_INFO "rp_do_receive(%d)...\n", ToRecv);
1da177e4 329#endif
cc44a817
PF		 330 if (ToRecv == 0)
331 return;
33f0f88f 332
1da177e4
LT		 333 /*
334 * if status indicates there are errored characters in the
335 * FIFO, then enter status mode (a word in FIFO holds
336 * character and status).
337 */
338 if (ChanStatus & (RXFOVERFL | RXBREAK | RXFRAME | RXPARITY)) {
339 if (!(ChanStatus & STATMODE)) {
340#ifdef ROCKET_DEBUG_RECEIVE
68562b79 341 printk(KERN_INFO "Entering STATMODE...\n");
1da177e4
LT		 342#endif
343 ChanStatus |= STATMODE;
344 sEnRxStatusMode(cp);
345 }
346 }
347
348 /*
349 * if we previously entered status mode, then read down the
350 * FIFO one word at a time, pulling apart the character and
351 * the status. Update error counters depending on status
352 */
353 if (ChanStatus & STATMODE) {
354#ifdef ROCKET_DEBUG_RECEIVE
68562b79
JS		 355 printk(KERN_INFO "Ignore %x, read %x...\n",
356 info->ignore_status_mask, info->read_status_mask);
1da177e4
LT		 357#endif
358 while (ToRecv) {
cc44a817
PF		 359 char flag;
360
1da177e4
LT		 361 CharNStat = sInW(sGetTxRxDataIO(cp));
362#ifdef ROCKET_DEBUG_RECEIVE
68562b79 363 printk(KERN_INFO "%x...\n", CharNStat);
1da177e4
LT		 364#endif
365 if (CharNStat & STMBREAKH)
366 CharNStat &= ~(STMFRAMEH | STMPARITYH);
367 if (CharNStat & info->ignore_status_mask) {
368 ToRecv--;
369 continue;
370 }
371 CharNStat &= info->read_status_mask;
372 if (CharNStat & STMBREAKH)
cc44a817 373 flag = TTY_BREAK;
1da177e4 374 else if (CharNStat & STMPARITYH)
cc44a817 375 flag = TTY_PARITY;
1da177e4 376 else if (CharNStat & STMFRAMEH)
cc44a817 377 flag = TTY_FRAME;
1da177e4 378 else if (CharNStat & STMRCVROVRH)
cc44a817 379 flag = TTY_OVERRUN;
1da177e4 380 else
cc44a817
PF		 381 flag = TTY_NORMAL;
382 tty_insert_flip_char(tty, CharNStat & 0xff, flag);
1da177e4
LT		 383 ToRecv--;
384 }
385
386 /*
387 * after we've emptied the FIFO in status mode, turn
388 * status mode back off
389 */
390 if (sGetRxCnt(cp) == 0) {
391#ifdef ROCKET_DEBUG_RECEIVE
392 printk(KERN_INFO "Status mode off.\n");
393#endif
394 sDisRxStatusMode(cp);
395 }
396 } else {
397 /*
398 * we aren't in status mode, so read down the FIFO two
399 * characters at time by doing repeated word IO
400 * transfer.
401 */
cc44a817
PF		 402 space = tty_prepare_flip_string(tty, &cbuf, ToRecv);
403 if (space < ToRecv) {
404#ifdef ROCKET_DEBUG_RECEIVE
405 printk(KERN_INFO "rp_do_receive:insufficient space ToRecv=%d space=%d\n", ToRecv, space);
406#endif
407 if (space <= 0)
408 return;
409 ToRecv = space;
410 }
1da177e4
LT		 411 wRecv = ToRecv >> 1;
412 if (wRecv)
413 sInStrW(sGetTxRxDataIO(cp), (unsigned short *) cbuf, wRecv);
414 if (ToRecv & 1)
415 cbuf[ToRecv - 1] = sInB(sGetTxRxDataIO(cp));
1da177e4
LT		 416 }
417 /* Push the data up to the tty layer */
cc44a817 418 tty_flip_buffer_push(tty);
1da177e4
LT		 419}
420
421/*
422 * Serial port transmit data function. Called from the timer polling loop as a
423 * result of a bit set in xmit_flags[], indicating data (from the tty layer) is ready
424 * to be sent out the serial port. Data is buffered in rp_table[line].xmit_buf, it is
425 * moved to the port's xmit FIFO. *info is critical data, protected by spinlocks.
426 */
427static void rp_do_transmit(struct r_port *info)
428{
429 int c;
430 CHANNEL_t *cp = &info->channel;
431 struct tty_struct *tty;
432 unsigned long flags;
433
434#ifdef ROCKET_DEBUG_INTR
68562b79 435 printk(KERN_DEBUG "%s\n", __func__);
1da177e4
LT		 436#endif
437 if (!info)
438 return;
47b01b3a
AC		 439 tty = tty_port_tty_get(&info->port);
440
441 if (tty == NULL) {
442 printk(KERN_WARNING "rp: WARNING %s called with tty==NULL\n", __func__);
1da177e4
LT		 443 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
444 return;
445 }
446
447 spin_lock_irqsave(&info->slock, flags);
1da177e4
LT		 448 info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
449
450 /* Loop sending data to FIFO until done or FIFO full */
451 while (1) {
452 if (tty->stopped || tty->hw_stopped)
453 break;
709107fc
HH		 454 c = min(info->xmit_fifo_room, info->xmit_cnt);
455 c = min(c, XMIT_BUF_SIZE - info->xmit_tail);
1da177e4
LT		 456 if (c <= 0 || info->xmit_fifo_room <= 0)
457 break;
458 sOutStrW(sGetTxRxDataIO(cp), (unsigned short *) (info->xmit_buf + info->xmit_tail), c / 2);
459 if (c & 1)
460 sOutB(sGetTxRxDataIO(cp), info->xmit_buf[info->xmit_tail + c - 1]);
461 info->xmit_tail += c;
462 info->xmit_tail &= XMIT_BUF_SIZE - 1;
463 info->xmit_cnt -= c;
464 info->xmit_fifo_room -= c;
465#ifdef ROCKET_DEBUG_INTR
68562b79 466 printk(KERN_INFO "tx %d chars...\n", c);
1da177e4
LT		 467#endif
468 }
469
470 if (info->xmit_cnt == 0)
471 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
472
473 if (info->xmit_cnt < WAKEUP_CHARS) {
474 tty_wakeup(tty);
1da177e4
LT		 475#ifdef ROCKETPORT_HAVE_POLL_WAIT
476 wake_up_interruptible(&tty->poll_wait);
477#endif
478 }
479
480 spin_unlock_irqrestore(&info->slock, flags);
47b01b3a 481 tty_kref_put(tty);
1da177e4
LT		 482
483#ifdef ROCKET_DEBUG_INTR
68562b79 484 printk(KERN_DEBUG "(%d,%d,%d,%d)...\n", info->xmit_cnt, info->xmit_head,
1da177e4
LT		 485 info->xmit_tail, info->xmit_fifo_room);
486#endif
487}
488
489/*
490 * Called when a serial port signals it has read data in it's RX FIFO.
491 * It checks what interrupts are pending and services them, including
492 * receiving serial data.
493 */
494static void rp_handle_port(struct r_port *info)
495{
496 CHANNEL_t *cp;
497 struct tty_struct *tty;
498 unsigned int IntMask, ChanStatus;
499
500 if (!info)
501 return;
502
21bed701 503 if ((info->port.flags & ASYNC_INITIALIZED) == 0) {
68562b79
JS		 504 printk(KERN_WARNING "rp: WARNING: rp_handle_port called with "
505 "info->flags & NOT_INIT\n");
1da177e4
LT		 506 return;
507 }
47b01b3a
AC		 508 tty = tty_port_tty_get(&info->port);
509 if (!tty) {
68562b79 510 printk(KERN_WARNING "rp: WARNING: rp_handle_port called with "
47b01b3a 511 "tty==NULL\n");
1da177e4
LT		 512 return;
513 }
514 cp = &info->channel;
1da177e4
LT		 515
516 IntMask = sGetChanIntID(cp) & info->intmask;
517#ifdef ROCKET_DEBUG_INTR
68562b79 518 printk(KERN_INFO "rp_interrupt %02x...\n", IntMask);
1da177e4
LT		 519#endif
520 ChanStatus = sGetChanStatus(cp);
521 if (IntMask & RXF_TRIG) { /* Rx FIFO trigger level */
522 rp_do_receive(info, tty, cp, ChanStatus);
523 }
524 if (IntMask & DELTA_CD) { /* CD change */
525#if (defined(ROCKET_DEBUG_OPEN) || defined(ROCKET_DEBUG_INTR) || defined(ROCKET_DEBUG_HANGUP))
68562b79 526 printk(KERN_INFO "ttyR%d CD now %s...\n", info->line,
1da177e4
LT		 527 (ChanStatus & CD_ACT) ? "on" : "off");
528#endif
529 if (!(ChanStatus & CD_ACT) && info->cd_status) {
530#ifdef ROCKET_DEBUG_HANGUP
531 printk(KERN_INFO "CD drop, calling hangup.\n");
532#endif
533 tty_hangup(tty);
534 }
535 info->cd_status = (ChanStatus & CD_ACT) ? 1 : 0;
e60a1084 536 wake_up_interruptible(&info->port.open_wait);
1da177e4
LT		 537 }
538#ifdef ROCKET_DEBUG_INTR
539 if (IntMask & DELTA_CTS) { /* CTS change */
540 printk(KERN_INFO "CTS change...\n");
541 }
542 if (IntMask & DELTA_DSR) { /* DSR change */
543 printk(KERN_INFO "DSR change...\n");
544 }
545#endif
47b01b3a 546 tty_kref_put(tty);
1da177e4
LT		 547}
548
549/*
550 * The top level polling routine. Repeats every 1/100 HZ (10ms).
551 */
552static void rp_do_poll(unsigned long dummy)
553{
554 CONTROLLER_t *ctlp;
6c0286b1
JS		 555 int ctrl, aiop, ch, line;
556 unsigned int xmitmask, i;
1da177e4
LT		 557 unsigned int CtlMask;
558 unsigned char AiopMask;
559 Word_t bit;
560
561 /* Walk through all the boards (ctrl's) */
562 for (ctrl = 0; ctrl < max_board; ctrl++) {
563 if (rcktpt_io_addr[ctrl] <= 0)
564 continue;
565
566 /* Get a ptr to the board's control struct */
567 ctlp = sCtlNumToCtlPtr(ctrl);
568
3a4fa0a2 569 /* Get the interrupt status from the board */
1da177e4
LT		 570#ifdef CONFIG_PCI
571 if (ctlp->BusType == isPCI)
572 CtlMask = sPCIGetControllerIntStatus(ctlp);
573 else
574#endif
575 CtlMask = sGetControllerIntStatus(ctlp);
576
577 /* Check if any AIOP read bits are set */
578 for (aiop = 0; CtlMask; aiop++) {
579 bit = ctlp->AiopIntrBits[aiop];
580 if (CtlMask & bit) {
581 CtlMask &= ~bit;
582 AiopMask = sGetAiopIntStatus(ctlp, aiop);
583
584 /* Check if any port read bits are set */
585 for (ch = 0; AiopMask; AiopMask >>= 1, ch++) {
586 if (AiopMask & 1) {
587
588 /* Get the line number (/dev/ttyRx number). */
589 /* Read the data from the port. */
590 line = GetLineNumber(ctrl, aiop, ch);
591 rp_handle_port(rp_table[line]);
592 }
593 }
594 }
595 }
596
597 xmitmask = xmit_flags[ctrl];
598
599 /*
600 * xmit_flags contains bit-significant flags, indicating there is data
601 * to xmit on the port. Bit 0 is port 0 on this board, bit 1 is port
602 * 1, ... (32 total possible). The variable i has the aiop and ch
603 * numbers encoded in it (port 0-7 are aiop0, 8-15 are aiop1, etc).
604 */
605 if (xmitmask) {
606 for (i = 0; i < rocketModel[ctrl].numPorts; i++) {
607 if (xmitmask & (1 << i)) {
608 aiop = (i & 0x18) >> 3;
609 ch = i & 0x07;
610 line = GetLineNumber(ctrl, aiop, ch);
611 rp_do_transmit(rp_table[line]);
612 }
613 }
614 }
615 }
616
617 /*
618 * Reset the timer so we get called at the next clock tick (10ms).
619 */
620 if (atomic_read(&rp_num_ports_open))
621 mod_timer(&rocket_timer, jiffies + POLL_PERIOD);
622}
623
624/*
625 * Initializes the r_port structure for a port, as well as enabling the port on
626 * the board.
627 * Inputs: board, aiop, chan numbers
628 */
629static void init_r_port(int board, int aiop, int chan, struct pci_dev *pci_dev)
630{
631 unsigned rocketMode;
632 struct r_port *info;
633 int line;
634 CONTROLLER_T *ctlp;
635
636 /* Get the next available line number */
637 line = SetLineNumber(board, aiop, chan);
638
639 ctlp = sCtlNumToCtlPtr(board);
640
641 /* Get a r_port struct for the port, fill it in and save it globally, indexed by line number */
dd00cc48 642 info = kzalloc(sizeof (struct r_port), GFP_KERNEL);
1da177e4 643 if (!info) {
68562b79
JS		 644 printk(KERN_ERR "Couldn't allocate info struct for line #%d\n",
645 line);
1da177e4
LT		 646 return;
647 }
1da177e4
LT		 648
649 info->magic = RPORT_MAGIC;
650 info->line = line;
651 info->ctlp = ctlp;
652 info->board = board;
653 info->aiop = aiop;
654 info->chan = chan;
31f35939
AC		 655 tty_port_init(&info->port);
656 info->port.ops = &rocket_port_ops;
8cf5a8c5 657 init_completion(&info->close_wait);
1da177e4
LT		 658 info->flags &= ~ROCKET_MODE_MASK;
659 switch (pc104[board][line]) {
660 case 422:
661 info->flags |= ROCKET_MODE_RS422;
662 break;
663 case 485:
664 info->flags |= ROCKET_MODE_RS485;
665 break;
666 case 232:
667 default:
668 info->flags |= ROCKET_MODE_RS232;
669 break;
670 }
671
672 info->intmask = RXF_TRIG | TXFIFO_MT | SRC_INT | DELTA_CD | DELTA_CTS | DELTA_DSR;
673 if (sInitChan(ctlp, &info->channel, aiop, chan) == 0) {
68562b79
JS		 674 printk(KERN_ERR "RocketPort sInitChan(%d, %d, %d) failed!\n",
675 board, aiop, chan);
1da177e4
LT		 676 kfree(info);
677 return;
678 }
679
680 rocketMode = info->flags & ROCKET_MODE_MASK;
681
682 if ((info->flags & ROCKET_RTS_TOGGLE) || (rocketMode == ROCKET_MODE_RS485))
683 sEnRTSToggle(&info->channel);
684 else
685 sDisRTSToggle(&info->channel);
686
687 if (ctlp->boardType == ROCKET_TYPE_PC104) {
688 switch (rocketMode) {
689 case ROCKET_MODE_RS485:
690 sSetInterfaceMode(&info->channel, InterfaceModeRS485);
691 break;
692 case ROCKET_MODE_RS422:
693 sSetInterfaceMode(&info->channel, InterfaceModeRS422);
694 break;
695 case ROCKET_MODE_RS232:
696 default:
697 if (info->flags & ROCKET_RTS_TOGGLE)
698 sSetInterfaceMode(&info->channel, InterfaceModeRS232T);
699 else
700 sSetInterfaceMode(&info->channel, InterfaceModeRS232);
701 break;
702 }
703 }
704 spin_lock_init(&info->slock);
69f545ea 705 mutex_init(&info->write_mtx);
1da177e4 706 rp_table[line] = info;
ac6aec2f
JS		 707 tty_register_device(rocket_driver, line, pci_dev ? &pci_dev->dev :
708 NULL);
1da177e4
LT		 709}
710
711/*
712 * Configures a rocketport port according to its termio settings. Called from
713 * user mode into the driver (exception handler). *info CD manipulation is spinlock protected.
714 */
47b01b3a 715static void configure_r_port(struct tty_struct *tty, struct r_port *info,
606d099c 716 struct ktermios *old_termios)
1da177e4
LT		 717{
718 unsigned cflag;
719 unsigned long flags;
720 unsigned rocketMode;
721 int bits, baud, divisor;
722 CHANNEL_t *cp;
47b01b3a 723 struct ktermios *t = tty->termios;
1da177e4 724
1da177e4 725 cp = &info->channel;
6df3526b 726 cflag = t->c_cflag;
1da177e4
LT		 727
728 /* Byte size and parity */
729 if ((cflag & CSIZE) == CS8) {
730 sSetData8(cp);
731 bits = 10;
732 } else {
733 sSetData7(cp);
734 bits = 9;
735 }
736 if (cflag & CSTOPB) {
737 sSetStop2(cp);
738 bits++;
739 } else {
740 sSetStop1(cp);
741 }
742
743 if (cflag & PARENB) {
744 sEnParity(cp);
745 bits++;
746 if (cflag & PARODD) {
747 sSetOddParity(cp);
748 } else {
749 sSetEvenParity(cp);
750 }
751 } else {
752 sDisParity(cp);
753 }
754
755 /* baud rate */
47b01b3a 756 baud = tty_get_baud_rate(tty);
1da177e4
LT		 757 if (!baud)
758 baud = 9600;
759 divisor = ((rp_baud_base[info->board] + (baud >> 1)) / baud) - 1;
760 if ((divisor >= 8192 || divisor < 0) && old_termios) {
6df3526b 761 baud = tty_termios_baud_rate(old_termios);
1da177e4
LT		 762 if (!baud)
763 baud = 9600;
764 divisor = (rp_baud_base[info->board] / baud) - 1;
765 }
766 if (divisor >= 8192 || divisor < 0) {
767 baud = 9600;
768 divisor = (rp_baud_base[info->board] / baud) - 1;
769 }
770 info->cps = baud / bits;
771 sSetBaud(cp, divisor);
772
6df3526b 773 /* FIXME: Should really back compute a baud rate from the divisor */
47b01b3a 774 tty_encode_baud_rate(tty, baud, baud);
6df3526b 775
1da177e4
LT		 776 if (cflag & CRTSCTS) {
777 info->intmask |= DELTA_CTS;
778 sEnCTSFlowCtl(cp);
779 } else {
780 info->intmask &= ~DELTA_CTS;
781 sDisCTSFlowCtl(cp);
782 }
783 if (cflag & CLOCAL) {
784 info->intmask &= ~DELTA_CD;
785 } else {
786 spin_lock_irqsave(&info->slock, flags);
787 if (sGetChanStatus(cp) & CD_ACT)
788 info->cd_status = 1;
789 else
790 info->cd_status = 0;
791 info->intmask |= DELTA_CD;
792 spin_unlock_irqrestore(&info->slock, flags);
793 }
794
795 /*
796 * Handle software flow control in the board
797 */
798#ifdef ROCKET_SOFT_FLOW
47b01b3a 799 if (I_IXON(tty)) {
1da177e4 800 sEnTxSoftFlowCtl(cp);
47b01b3a 801 if (I_IXANY(tty)) {
1da177e4
LT		 802 sEnIXANY(cp);
803 } else {
804 sDisIXANY(cp);
805 }
47b01b3a
AC		 806 sSetTxXONChar(cp, START_CHAR(tty));
807 sSetTxXOFFChar(cp, STOP_CHAR(tty));
1da177e4
LT		 808 } else {
809 sDisTxSoftFlowCtl(cp);
810 sDisIXANY(cp);
811 sClrTxXOFF(cp);
812 }
813#endif
814
815 /*
816 * Set up ignore/read mask words
817 */
818 info->read_status_mask = STMRCVROVRH | 0xFF;
47b01b3a 819 if (I_INPCK(tty))
1da177e4 820 info->read_status_mask |= STMFRAMEH | STMPARITYH;
47b01b3a 821 if (I_BRKINT(tty) || I_PARMRK(tty))
1da177e4
LT		 822 info->read_status_mask |= STMBREAKH;
823
824 /*
825 * Characters to ignore
826 */
827 info->ignore_status_mask = 0;
47b01b3a 828 if (I_IGNPAR(tty))
1da177e4 829 info->ignore_status_mask |= STMFRAMEH | STMPARITYH;
47b01b3a 830 if (I_IGNBRK(tty)) {
1da177e4
LT		 831 info->ignore_status_mask |= STMBREAKH;
832 /*
833 * If we're ignoring parity and break indicators,
834 * ignore overruns too. (For real raw support).
835 */
47b01b3a 836 if (I_IGNPAR(tty))
1da177e4
LT		 837 info->ignore_status_mask |= STMRCVROVRH;
838 }
839
840 rocketMode = info->flags & ROCKET_MODE_MASK;
841
842 if ((info->flags & ROCKET_RTS_TOGGLE)
843 || (rocketMode == ROCKET_MODE_RS485))
844 sEnRTSToggle(cp);
845 else
846 sDisRTSToggle(cp);
847
848 sSetRTS(&info->channel);
849
850 if (cp->CtlP->boardType == ROCKET_TYPE_PC104) {
851 switch (rocketMode) {
852 case ROCKET_MODE_RS485:
853 sSetInterfaceMode(cp, InterfaceModeRS485);
854 break;
855 case ROCKET_MODE_RS422:
856 sSetInterfaceMode(cp, InterfaceModeRS422);
857 break;
858 case ROCKET_MODE_RS232:
859 default:
860 if (info->flags & ROCKET_RTS_TOGGLE)
861 sSetInterfaceMode(cp, InterfaceModeRS232T);
862 else
863 sSetInterfaceMode(cp, InterfaceModeRS232);
864 break;
865 }
866 }
867}
868
31f35939
AC		 869static int carrier_raised(struct tty_port *port)
870{
871 struct r_port *info = container_of(port, struct r_port, port);
872 return (sGetChanStatusLo(&info->channel) & CD_ACT) ? 1 : 0;
873}
874
5d951fb4
AC		 875static void raise_dtr_rts(struct tty_port *port)
876{
877 struct r_port *info = container_of(port, struct r_port, port);
878 sSetDTR(&info->channel);
879 sSetRTS(&info->channel);
880}
881
e60a1084 882/* info->port.count is considered critical, protected by spinlocks. */
1da177e4
LT		 883static int block_til_ready(struct tty_struct *tty, struct file *filp,
884 struct r_port *info)
885{
886 DECLARE_WAITQUEUE(wait, current);
31f35939 887 struct tty_port *port = &info->port;
1da177e4
LT		 888 int retval;
889 int do_clocal = 0, extra_count = 0;
890 unsigned long flags;
891
892 /*
893 * If the device is in the middle of being closed, then block
894 * until it's done, and then try again.
895 */
896 if (tty_hung_up_p(filp))
21bed701 897 return ((info->port.flags & ASYNC_HUP_NOTIFY) ? -EAGAIN : -ERESTARTSYS);
a129909c 898 if (info->flags & ASYNC_CLOSING) {
8cf5a8c5
JS		 899 if (wait_for_completion_interruptible(&info->close_wait))
900 return -ERESTARTSYS;
21bed701 901 return ((info->port.flags & ASYNC_HUP_NOTIFY) ? -EAGAIN : -ERESTARTSYS);
1da177e4
LT		 902 }
903
904 /*
905 * If non-blocking mode is set, or the port is not enabled,
906 * then make the check up front and then exit.
907 */
908 if ((filp->f_flags & O_NONBLOCK) || (tty->flags & (1 << TTY_IO_ERROR))) {
21bed701 909 info->port.flags |= ASYNC_NORMAL_ACTIVE;
1da177e4
LT		 910 return 0;
911 }
912 if (tty->termios->c_cflag & CLOCAL)
913 do_clocal = 1;
914
915 /*
916 * Block waiting for the carrier detect and the line to become free. While we are in
31f35939 917 * this loop, port->count is dropped by one, so that rp_close() knows when to free things.
1da177e4
LT		 918 * We restore it upon exit, either normal or abnormal.
919 */
920 retval = 0;
31f35939 921 add_wait_queue(&port->open_wait, &wait);
1da177e4 922#ifdef ROCKET_DEBUG_OPEN
31f35939 923 printk(KERN_INFO "block_til_ready before block: ttyR%d, count = %d\n", info->line, port->count);
1da177e4 924#endif
c1314a49 925 spin_lock_irqsave(&port->lock, flags);
1da177e4
LT		 926
927#ifdef ROCKET_DISABLE_SIMUSAGE
21bed701 928 info->port.flags |= ASYNC_NORMAL_ACTIVE;
1da177e4
LT		 929#else
930 if (!tty_hung_up_p(filp)) {
931 extra_count = 1;
31f35939 932 port->count--;
1da177e4
LT		 933 }
934#endif
31f35939 935 port->blocked_open++;
1da177e4 936
c1314a49 937 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 938
939 while (1) {
5d951fb4
AC		 940 if (tty->termios->c_cflag & CBAUD)
941 tty_port_raise_dtr_rts(port);
1da177e4 942 set_current_state(TASK_INTERRUPTIBLE);
21bed701
AC		 943 if (tty_hung_up_p(filp) || !(info->port.flags & ASYNC_INITIALIZED)) {
944 if (info->port.flags & ASYNC_HUP_NOTIFY)
1da177e4
LT		 945 retval = -EAGAIN;
946 else
947 retval = -ERESTARTSYS;
948 break;
949 }
21bed701 950 if (!(info->port.flags & ASYNC_CLOSING) &&
31f35939 951 (do_clocal || tty_port_carrier_raised(port)))
1da177e4
LT		 952 break;
953 if (signal_pending(current)) {
954 retval = -ERESTARTSYS;
955 break;
956 }
957#ifdef ROCKET_DEBUG_OPEN
958 printk(KERN_INFO "block_til_ready blocking: ttyR%d, count = %d, flags=0x%0x\n",
21bed701 959 info->line, port->count, info->port.flags);
1da177e4
LT		 960#endif
961 schedule(); /* Don't hold spinlock here, will hang PC */
962 }
cc0a8fbb 963 __set_current_state(TASK_RUNNING);
31f35939 964 remove_wait_queue(&port->open_wait, &wait);
1da177e4 965
c1314a49 966 spin_lock_irqsave(&port->lock, flags);
1da177e4
LT		 967
968 if (extra_count)
31f35939
AC		 969 port->count++;
970 port->blocked_open--;
1da177e4 971
c1314a49 972 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 973
974#ifdef ROCKET_DEBUG_OPEN
975 printk(KERN_INFO "block_til_ready after blocking: ttyR%d, count = %d\n",
31f35939 976 info->line, port->count);
1da177e4
LT		 977#endif
978 if (retval)
979 return retval;
21bed701 980 info->port.flags |= ASYNC_NORMAL_ACTIVE;
1da177e4
LT		 981 return 0;
982}
983
984/*
985 * Exception handler that opens a serial port. Creates xmit_buf storage, fills in
986 * port's r_port struct. Initializes the port hardware.
987 */
988static int rp_open(struct tty_struct *tty, struct file *filp)
989{
990 struct r_port *info;
991 int line = 0, retval;
992 CHANNEL_t *cp;
993 unsigned long page;
994
f6de0c98 995 line = tty->index;
1da177e4
LT		 996 if ((line < 0) || (line >= MAX_RP_PORTS) || ((info = rp_table[line]) == NULL))
997 return -ENXIO;
998
999 page = __get_free_page(GFP_KERNEL);
1000 if (!page)
1001 return -ENOMEM;
1002
21bed701 1003 if (info->port.flags & ASYNC_CLOSING) {
8cf5a8c5 1004 retval = wait_for_completion_interruptible(&info->close_wait);
1da177e4 1005 free_page(page);
8cf5a8c5
JS		 1006 if (retval)
1007 return retval;
21bed701 1008 return ((info->port.flags & ASYNC_HUP_NOTIFY) ? -EAGAIN : -ERESTARTSYS);
1da177e4
LT		 1009 }
1010
1011 /*
1012 * We must not sleep from here until the port is marked fully in use.
1013 */
1014 if (info->xmit_buf)
1015 free_page(page);
1016 else
1017 info->xmit_buf = (unsigned char *) page;
1018
1019 tty->driver_data = info;
47b01b3a 1020 tty_port_tty_set(&info->port, tty);
1da177e4 1021
e60a1084 1022 if (info->port.count++ == 0) {
1da177e4
LT		 1023 atomic_inc(&rp_num_ports_open);
1024
1025#ifdef ROCKET_DEBUG_OPEN
68562b79
JS		 1026 printk(KERN_INFO "rocket mod++ = %d...\n",
1027 atomic_read(&rp_num_ports_open));
1da177e4
LT		 1028#endif
1029 }
1030#ifdef ROCKET_DEBUG_OPEN
e60a1084 1031 printk(KERN_INFO "rp_open ttyR%d, count=%d\n", info->line, info->port.count);
1da177e4
LT		 1032#endif
1033
1034 /*
1035 * Info->count is now 1; so it's safe to sleep now.
1036 */
21bed701 1037 if ((info->port.flags & ASYNC_INITIALIZED) == 0) {
1da177e4
LT		 1038 cp = &info->channel;
1039 sSetRxTrigger(cp, TRIG_1);
1040 if (sGetChanStatus(cp) & CD_ACT)
1041 info->cd_status = 1;
1042 else
1043 info->cd_status = 0;
1044 sDisRxStatusMode(cp);
1045 sFlushRxFIFO(cp);
1046 sFlushTxFIFO(cp);
1047
1048 sEnInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
1049 sSetRxTrigger(cp, TRIG_1);
1050
1051 sGetChanStatus(cp);
1052 sDisRxStatusMode(cp);
1053 sClrTxXOFF(cp);
1054
1055 sDisCTSFlowCtl(cp);
1056 sDisTxSoftFlowCtl(cp);
1057
1058 sEnRxFIFO(cp);
1059 sEnTransmit(cp);
1060
21bed701 1061 info->port.flags |= ASYNC_INITIALIZED;
1da177e4
LT		 1062
1063 /*
1064 * Set up the tty->alt_speed kludge
1065 */
1066 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_HI)
47b01b3a 1067 tty->alt_speed = 57600;
1da177e4 1068 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_VHI)
47b01b3a 1069 tty->alt_speed = 115200;
1da177e4 1070 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_SHI)
47b01b3a 1071 tty->alt_speed = 230400;
1da177e4 1072 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_WARP)
47b01b3a 1073 tty->alt_speed = 460800;
1da177e4 1074
47b01b3a 1075 configure_r_port(tty, info, NULL);
1da177e4
LT		 1076 if (tty->termios->c_cflag & CBAUD) {
1077 sSetDTR(cp);
1078 sSetRTS(cp);
1079 }
1080 }
1081 /* Starts (or resets) the maint polling loop */
1082 mod_timer(&rocket_timer, jiffies + POLL_PERIOD);
1083
1084 retval = block_til_ready(tty, filp, info);
1085 if (retval) {
1086#ifdef ROCKET_DEBUG_OPEN
1087 printk(KERN_INFO "rp_open returning after block_til_ready with %d\n", retval);
1088#endif
1089 return retval;
1090 }
1091 return 0;
1092}
1093
1094/*
e60a1084 1095 * Exception handler that closes a serial port. info->port.count is considered critical.
1da177e4
LT		 1096 */
1097static void rp_close(struct tty_struct *tty, struct file *filp)
1098{
c9f19e96 1099 struct r_port *info = tty->driver_data;
c1314a49 1100 struct tty_port *port = &info->port;
1da177e4
LT		 1101 unsigned long flags;
1102 int timeout;
1103 CHANNEL_t *cp;
1104
1105 if (rocket_paranoia_check(info, "rp_close"))
1106 return;
1107
1108#ifdef ROCKET_DEBUG_OPEN
e60a1084 1109 printk(KERN_INFO "rp_close ttyR%d, count = %d\n", info->line, info->port.count);
1da177e4
LT		 1110#endif
1111
1112 if (tty_hung_up_p(filp))
1113 return;
c1314a49 1114 spin_lock_irqsave(&port->lock, flags);
1da177e4 1115
c1314a49 1116 if (tty->count == 1 && port->count != 1) {
1da177e4
LT		 1117 /*
1118 * Uh, oh. tty->count is 1, which means that the tty
1119 * structure will be freed. Info->count should always
1120 * be one in these conditions. If it's greater than
1121 * one, we've got real problems, since it means the
1122 * serial port won't be shutdown.
1123 */
68562b79 1124 printk(KERN_WARNING "rp_close: bad serial port count; "
e60a1084 1125 "tty->count is 1, info->port.count is %d\n", info->port.count);
c1314a49 1126 port->count = 1;
1da177e4 1127 }
c1314a49 1128 if (--port->count < 0) {
68562b79 1129 printk(KERN_WARNING "rp_close: bad serial port count for "
e60a1084 1130 "ttyR%d: %d\n", info->line, info->port.count);
c1314a49 1131 port->count = 0;
1da177e4 1132 }
c1314a49
AC		 1133 if (port->count) {
1134 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 1135 return;
1136 }
21bed701 1137 info->port.flags |= ASYNC_CLOSING;
c1314a49 1138 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 1139
1140 cp = &info->channel;
1141
1142 /*
1143 * Notify the line discpline to only process XON/XOFF characters
1144 */
1145 tty->closing = 1;
1146
1147 /*
1148 * If transmission was throttled by the application request,
1149 * just flush the xmit buffer.
1150 */
1151 if (tty->flow_stopped)
1152 rp_flush_buffer(tty);
1153
1154 /*
1155 * Wait for the transmit buffer to clear
1156 */
a129909c 1157 if (info->port.closing_wait != ASYNC_CLOSING_WAIT_NONE)
c1314a49 1158 tty_wait_until_sent(tty, port->closing_wait);
1da177e4
LT		 1159 /*
1160 * Before we drop DTR, make sure the UART transmitter
1161 * has completely drained; this is especially
1162 * important if there is a transmit FIFO!
1163 */
1164 timeout = (sGetTxCnt(cp) + 1) * HZ / info->cps;
1165 if (timeout == 0)
1166 timeout = 1;
1167 rp_wait_until_sent(tty, timeout);
1168 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1169
1170 sDisTransmit(cp);
1171 sDisInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
1172 sDisCTSFlowCtl(cp);
1173 sDisTxSoftFlowCtl(cp);
1174 sClrTxXOFF(cp);
1175 sFlushRxFIFO(cp);
1176 sFlushTxFIFO(cp);
1177 sClrRTS(cp);
1178 if (C_HUPCL(tty))
1179 sClrDTR(cp);
1180
f6de0c98 1181 rp_flush_buffer(tty);
1da177e4
LT		 1182
1183 tty_ldisc_flush(tty);
1184
1185 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1186
c1314a49
AC		 1187 if (port->blocked_open) {
1188 if (port->close_delay) {
1189 msleep_interruptible(jiffies_to_msecs(port->close_delay));
1da177e4 1190 }
c1314a49 1191 wake_up_interruptible(&port->open_wait);
1da177e4
LT		 1192 } else {
1193 if (info->xmit_buf) {
1194 free_page((unsigned long) info->xmit_buf);
1195 info->xmit_buf = NULL;
1196 }
1197 }
21bed701 1198 info->port.flags &= ~(ASYNC_INITIALIZED | ASYNC_CLOSING | ASYNC_NORMAL_ACTIVE);
1da177e4 1199 tty->closing = 0;
8cf5a8c5 1200 complete_all(&info->close_wait);
1da177e4
LT		 1201 atomic_dec(&rp_num_ports_open);
1202
1203#ifdef ROCKET_DEBUG_OPEN
68562b79
JS		 1204 printk(KERN_INFO "rocket mod-- = %d...\n",
1205 atomic_read(&rp_num_ports_open));
1da177e4
LT		 1206 printk(KERN_INFO "rp_close ttyR%d complete shutdown\n", info->line);
1207#endif
1208
1209}
1210
1211static void rp_set_termios(struct tty_struct *tty,
606d099c 1212 struct ktermios *old_termios)
1da177e4 1213{
c9f19e96 1214 struct r_port *info = tty->driver_data;
1da177e4
LT		 1215 CHANNEL_t *cp;
1216 unsigned cflag;
1217
1218 if (rocket_paranoia_check(info, "rp_set_termios"))
1219 return;
1220
1221 cflag = tty->termios->c_cflag;
1222
1da177e4
LT		 1223 /*
1224 * This driver doesn't support CS5 or CS6
1225 */
1226 if (((cflag & CSIZE) == CS5) || ((cflag & CSIZE) == CS6))
1227 tty->termios->c_cflag =
1228 ((cflag & ~CSIZE) | (old_termios->c_cflag & CSIZE));
6df3526b
AC		 1229 /* Or CMSPAR */
1230 tty->termios->c_cflag &= ~CMSPAR;
1da177e4 1231
47b01b3a 1232 configure_r_port(tty, info, old_termios);
1da177e4
LT		 1233
1234 cp = &info->channel;
1235
1236 /* Handle transition to B0 status */
1237 if ((old_termios->c_cflag & CBAUD) && !(tty->termios->c_cflag & CBAUD)) {
1238 sClrDTR(cp);
1239 sClrRTS(cp);
1240 }
1241
1242 /* Handle transition away from B0 status */
1243 if (!(old_termios->c_cflag & CBAUD) && (tty->termios->c_cflag & CBAUD)) {
1244 if (!tty->hw_stopped || !(tty->termios->c_cflag & CRTSCTS))
1245 sSetRTS(cp);
1246 sSetDTR(cp);
1247 }
1248
1249 if ((old_termios->c_cflag & CRTSCTS) && !(tty->termios->c_cflag & CRTSCTS)) {
1250 tty->hw_stopped = 0;
1251 rp_start(tty);
1252 }
1253}
1254
9e98966c 1255static int rp_break(struct tty_struct *tty, int break_state)
1da177e4 1256{
c9f19e96 1257 struct r_port *info = tty->driver_data;
1da177e4
LT		 1258 unsigned long flags;
1259
1260 if (rocket_paranoia_check(info, "rp_break"))
9e98966c 1261 return -EINVAL;
1da177e4
LT		 1262
1263 spin_lock_irqsave(&info->slock, flags);
1264 if (break_state == -1)
1265 sSendBreak(&info->channel);
1266 else
1267 sClrBreak(&info->channel);
1268 spin_unlock_irqrestore(&info->slock, flags);
9e98966c 1269 return 0;
1da177e4
LT		 1270}
1271
1272/*
1273 * sGetChanRI used to be a macro in rocket_int.h. When the functionality for
1274 * the UPCI boards was added, it was decided to make this a function because
1275 * the macro was getting too complicated. All cases except the first one
1276 * (UPCIRingInd) are taken directly from the original macro.
1277 */
1278static int sGetChanRI(CHANNEL_T * ChP)
1279{
1280 CONTROLLER_t *CtlP = ChP->CtlP;
1281 int ChanNum = ChP->ChanNum;
1282 int RingInd = 0;
1283
1284 if (CtlP->UPCIRingInd)
1285 RingInd = !(sInB(CtlP->UPCIRingInd) & sBitMapSetTbl[ChanNum]);
1286 else if (CtlP->AltChanRingIndicator)
1287 RingInd = sInB((ByteIO_t) (ChP->ChanStat + 8)) & DSR_ACT;
1288 else if (CtlP->boardType == ROCKET_TYPE_PC104)
1289 RingInd = !(sInB(CtlP->AiopIO[3]) & sBitMapSetTbl[ChanNum]);
1290
1291 return RingInd;
1292}
1293
1294/********************************************************************************************/
1295/* Here are the routines used by rp_ioctl. These are all called from exception handlers. */
1296
1297/*
1298 * Returns the state of the serial modem control lines. These next 2 functions
1299 * are the way kernel versions > 2.5 handle modem control lines rather than IOCTLs.
1300 */
1301static int rp_tiocmget(struct tty_struct *tty, struct file *file)
1302{
c9f19e96 1303 struct r_port *info = tty->driver_data;
1da177e4
LT		 1304 unsigned int control, result, ChanStatus;
1305
1306 ChanStatus = sGetChanStatusLo(&info->channel);
1307 control = info->channel.TxControl[3];
1308 result = ((control & SET_RTS) ? TIOCM_RTS : 0) |
1309 ((control & SET_DTR) ? TIOCM_DTR : 0) |
1310 ((ChanStatus & CD_ACT) ? TIOCM_CAR : 0) |
1311 (sGetChanRI(&info->channel) ? TIOCM_RNG : 0) |
1312 ((ChanStatus & DSR_ACT) ? TIOCM_DSR : 0) |
1313 ((ChanStatus & CTS_ACT) ? TIOCM_CTS : 0);
1314
1315 return result;
1316}
1317
1318/*
1319 * Sets the modem control lines
1320 */
1321static int rp_tiocmset(struct tty_struct *tty, struct file *file,
1322 unsigned int set, unsigned int clear)
1323{
c9f19e96 1324 struct r_port *info = tty->driver_data;
1da177e4
LT		 1325
1326 if (set & TIOCM_RTS)
1327 info->channel.TxControl[3] |= SET_RTS;
1328 if (set & TIOCM_DTR)
1329 info->channel.TxControl[3] |= SET_DTR;
1330 if (clear & TIOCM_RTS)
1331 info->channel.TxControl[3] &= ~SET_RTS;
1332 if (clear & TIOCM_DTR)
1333 info->channel.TxControl[3] &= ~SET_DTR;
1334
457fb605 1335 out32(info->channel.IndexAddr, info->channel.TxControl);
1da177e4
LT		 1336 return 0;
1337}
1338
1339static int get_config(struct r_port *info, struct rocket_config __user *retinfo)
1340{
1341 struct rocket_config tmp;
1342
1343 if (!retinfo)
1344 return -EFAULT;
1345 memset(&tmp, 0, sizeof (tmp));
1346 tmp.line = info->line;
1347 tmp.flags = info->flags;
44b7d1b3
AC		 1348 tmp.close_delay = info->port.close_delay;
1349 tmp.closing_wait = info->port.closing_wait;
1da177e4
LT		 1350 tmp.port = rcktpt_io_addr[(info->line >> 5) & 3];
1351
1352 if (copy_to_user(retinfo, &tmp, sizeof (*retinfo)))
1353 return -EFAULT;
1354 return 0;
1355}
1356
47b01b3a
AC		 1357static int set_config(struct tty_struct *tty, struct r_port *info,
1358 struct rocket_config __user *new_info)
1da177e4
LT		 1359{
1360 struct rocket_config new_serial;
1361
1362 if (copy_from_user(&new_serial, new_info, sizeof (new_serial)))
1363 return -EFAULT;
1364
1365 if (!capable(CAP_SYS_ADMIN))
1366 {
1367 if ((new_serial.flags & ~ROCKET_USR_MASK) != (info->flags & ~ROCKET_USR_MASK))
1368 return -EPERM;
1369 info->flags = ((info->flags & ~ROCKET_USR_MASK) | (new_serial.flags & ROCKET_USR_MASK));
47b01b3a 1370 configure_r_port(tty, info, NULL);
1da177e4
LT		 1371 return 0;
1372 }
1373
1374 info->flags = ((info->flags & ~ROCKET_FLAGS) | (new_serial.flags & ROCKET_FLAGS));
44b7d1b3
AC		 1375 info->port.close_delay = new_serial.close_delay;
1376 info->port.closing_wait = new_serial.closing_wait;
1da177e4
LT		 1377
1378 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_HI)
47b01b3a 1379 tty->alt_speed = 57600;
1da177e4 1380 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_VHI)
47b01b3a 1381 tty->alt_speed = 115200;
1da177e4 1382 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_SHI)
47b01b3a 1383 tty->alt_speed = 230400;
1da177e4 1384 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_WARP)
47b01b3a 1385 tty->alt_speed = 460800;
1da177e4 1386
47b01b3a 1387 configure_r_port(tty, info, NULL);
1da177e4
LT		 1388 return 0;
1389}
1390
1391/*
1392 * This function fills in a rocket_ports struct with information
1393 * about what boards/ports are in the system. This info is passed
1394 * to user space. See setrocket.c where the info is used to create
1395 * the /dev/ttyRx ports.
1396 */
1397static int get_ports(struct r_port *info, struct rocket_ports __user *retports)
1398{
1399 struct rocket_ports tmp;
1400 int board;
1401
1402 if (!retports)
1403 return -EFAULT;
1404 memset(&tmp, 0, sizeof (tmp));
1405 tmp.tty_major = rocket_driver->major;
1406
1407 for (board = 0; board < 4; board++) {
1408 tmp.rocketModel[board].model = rocketModel[board].model;
1409 strcpy(tmp.rocketModel[board].modelString, rocketModel[board].modelString);
1410 tmp.rocketModel[board].numPorts = rocketModel[board].numPorts;
1411 tmp.rocketModel[board].loadrm2 = rocketModel[board].loadrm2;
1412 tmp.rocketModel[board].startingPortNumber = rocketModel[board].startingPortNumber;
1413 }
1414 if (copy_to_user(retports, &tmp, sizeof (*retports)))
1415 return -EFAULT;
1416 return 0;
1417}
1418
1419static int reset_rm2(struct r_port *info, void __user *arg)
1420{
1421 int reset;
1422
4129a645
AC		 1423 if (!capable(CAP_SYS_ADMIN))
1424 return -EPERM;
1425
1da177e4
LT		 1426 if (copy_from_user(&reset, arg, sizeof (int)))
1427 return -EFAULT;
1428 if (reset)
1429 reset = 1;
1430
1431 if (rcktpt_type[info->board] != ROCKET_TYPE_MODEMII &&
1432 rcktpt_type[info->board] != ROCKET_TYPE_MODEMIII)
1433 return -EINVAL;
1434
1435 if (info->ctlp->BusType == isISA)
1436 sModemReset(info->ctlp, info->chan, reset);
1437 else
1438 sPCIModemReset(info->ctlp, info->chan, reset);
1439
1440 return 0;
1441}
1442
1443static int get_version(struct r_port *info, struct rocket_version __user *retvers)
1444{
1445 if (copy_to_user(retvers, &driver_version, sizeof (*retvers)))
1446 return -EFAULT;
1447 return 0;
1448}
1449
1450/* IOCTL call handler into the driver */
1451static int rp_ioctl(struct tty_struct *tty, struct file *file,
1452 unsigned int cmd, unsigned long arg)
1453{
c9f19e96 1454 struct r_port *info = tty->driver_data;
1da177e4 1455 void __user *argp = (void __user *)arg;
bdf183aa 1456 int ret = 0;
1da177e4
LT		 1457
1458 if (cmd != RCKP_GET_PORTS && rocket_paranoia_check(info, "rp_ioctl"))
1459 return -ENXIO;
1460
bdf183aa
AC		 1461 lock_kernel();
1462
1da177e4
LT		 1463 switch (cmd) {
1464 case RCKP_GET_STRUCT:
1465 if (copy_to_user(argp, info, sizeof (struct r_port)))
bdf183aa
AC		 1466 ret = -EFAULT;
1467 break;
1da177e4 1468 case RCKP_GET_CONFIG:
bdf183aa
AC		 1469 ret = get_config(info, argp);
1470 break;
1da177e4 1471 case RCKP_SET_CONFIG:
47b01b3a 1472 ret = set_config(tty, info, argp);
bdf183aa 1473 break;
1da177e4 1474 case RCKP_GET_PORTS:
bdf183aa
AC		 1475 ret = get_ports(info, argp);
1476 break;
1da177e4 1477 case RCKP_RESET_RM2:
bdf183aa
AC		 1478 ret = reset_rm2(info, argp);
1479 break;
1da177e4 1480 case RCKP_GET_VERSION:
bdf183aa
AC		 1481 ret = get_version(info, argp);
1482 break;
1da177e4 1483 default:
bdf183aa 1484 ret = -ENOIOCTLCMD;
1da177e4 1485 }
bdf183aa
AC		 1486 unlock_kernel();
1487 return ret;
1da177e4
LT		 1488}
1489
1490static void rp_send_xchar(struct tty_struct *tty, char ch)
1491{
c9f19e96 1492 struct r_port *info = tty->driver_data;
1da177e4
LT		 1493 CHANNEL_t *cp;
1494
1495 if (rocket_paranoia_check(info, "rp_send_xchar"))
1496 return;
1497
1498 cp = &info->channel;
1499 if (sGetTxCnt(cp))
1500 sWriteTxPrioByte(cp, ch);
1501 else
1502 sWriteTxByte(sGetTxRxDataIO(cp), ch);
1503}
1504
1505static void rp_throttle(struct tty_struct *tty)
1506{
c9f19e96 1507 struct r_port *info = tty->driver_data;
1da177e4
LT		 1508 CHANNEL_t *cp;
1509
1510#ifdef ROCKET_DEBUG_THROTTLE
1511 printk(KERN_INFO "throttle %s: %d....\n", tty->name,
1512 tty->ldisc.chars_in_buffer(tty));
1513#endif
1514
1515 if (rocket_paranoia_check(info, "rp_throttle"))
1516 return;
1517
1518 cp = &info->channel;
1519 if (I_IXOFF(tty))
1520 rp_send_xchar(tty, STOP_CHAR(tty));
1521
1522 sClrRTS(&info->channel);
1523}
1524
1525static void rp_unthrottle(struct tty_struct *tty)
1526{
c9f19e96 1527 struct r_port *info = tty->driver_data;
1da177e4
LT		 1528 CHANNEL_t *cp;
1529#ifdef ROCKET_DEBUG_THROTTLE
1530 printk(KERN_INFO "unthrottle %s: %d....\n", tty->name,
1531 tty->ldisc.chars_in_buffer(tty));
1532#endif
1533
1534 if (rocket_paranoia_check(info, "rp_throttle"))
1535 return;
1536
1537 cp = &info->channel;
1538 if (I_IXOFF(tty))
1539 rp_send_xchar(tty, START_CHAR(tty));
1540
1541 sSetRTS(&info->channel);
1542}
1543
1544/*
1545 * ------------------------------------------------------------
1546 * rp_stop() and rp_start()
1547 *
1548 * This routines are called before setting or resetting tty->stopped.
1549 * They enable or disable transmitter interrupts, as necessary.
1550 * ------------------------------------------------------------
1551 */
1552static void rp_stop(struct tty_struct *tty)
1553{
c9f19e96 1554 struct r_port *info = tty->driver_data;
1da177e4
LT		 1555
1556#ifdef ROCKET_DEBUG_FLOW
1557 printk(KERN_INFO "stop %s: %d %d....\n", tty->name,
1558 info->xmit_cnt, info->xmit_fifo_room);
1559#endif
1560
1561 if (rocket_paranoia_check(info, "rp_stop"))
1562 return;
1563
1564 if (sGetTxCnt(&info->channel))
1565 sDisTransmit(&info->channel);
1566}
1567
1568static void rp_start(struct tty_struct *tty)
1569{
c9f19e96 1570 struct r_port *info = tty->driver_data;
1da177e4
LT		 1571
1572#ifdef ROCKET_DEBUG_FLOW
1573 printk(KERN_INFO "start %s: %d %d....\n", tty->name,
1574 info->xmit_cnt, info->xmit_fifo_room);
1575#endif
1576
1577 if (rocket_paranoia_check(info, "rp_stop"))
1578 return;
1579
1580 sEnTransmit(&info->channel);
1581 set_bit((info->aiop * 8) + info->chan,
1582 (void *) &xmit_flags[info->board]);
1583}
1584
1585/*
1586 * rp_wait_until_sent() --- wait until the transmitter is empty
1587 */
1588static void rp_wait_until_sent(struct tty_struct *tty, int timeout)
1589{
c9f19e96 1590 struct r_port *info = tty->driver_data;
1da177e4
LT		 1591 CHANNEL_t *cp;
1592 unsigned long orig_jiffies;
1593 int check_time, exit_time;
1594 int txcnt;
1595
1596 if (rocket_paranoia_check(info, "rp_wait_until_sent"))
1597 return;
1598
1599 cp = &info->channel;
1600
1601 orig_jiffies = jiffies;
1602#ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
68562b79 1603 printk(KERN_INFO "In RP_wait_until_sent(%d) (jiff=%lu)...\n", timeout,
1da177e4 1604 jiffies);
68562b79 1605 printk(KERN_INFO "cps=%d...\n", info->cps);
1da177e4 1606#endif
978e595f 1607 lock_kernel();
1da177e4
LT		 1608 while (1) {
1609 txcnt = sGetTxCnt(cp);
1610 if (!txcnt) {
1611 if (sGetChanStatusLo(cp) & TXSHRMT)
1612 break;
1613 check_time = (HZ / info->cps) / 5;
1614 } else {
1615 check_time = HZ * txcnt / info->cps;
1616 }
1617 if (timeout) {
1618 exit_time = orig_jiffies + timeout - jiffies;
1619 if (exit_time <= 0)
1620 break;
1621 if (exit_time < check_time)
1622 check_time = exit_time;
1623 }
1624 if (check_time == 0)
1625 check_time = 1;
1626#ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
68562b79
JS		 1627 printk(KERN_INFO "txcnt = %d (jiff=%lu,check=%d)...\n", txcnt,
1628 jiffies, check_time);
1da177e4
LT		 1629#endif
1630 msleep_interruptible(jiffies_to_msecs(check_time));
1631 if (signal_pending(current))
1632 break;
1633 }
cc0a8fbb 1634 __set_current_state(TASK_RUNNING);
978e595f 1635 unlock_kernel();
1da177e4
LT		 1636#ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
1637 printk(KERN_INFO "txcnt = %d (jiff=%lu)...done\n", txcnt, jiffies);
1638#endif
1639}
1640
1641/*
1642 * rp_hangup() --- called by tty_hangup() when a hangup is signaled.
1643 */
1644static void rp_hangup(struct tty_struct *tty)
1645{
1646 CHANNEL_t *cp;
c9f19e96 1647 struct r_port *info = tty->driver_data;
1da177e4
LT		 1648
1649 if (rocket_paranoia_check(info, "rp_hangup"))
1650 return;
1651
1652#if (defined(ROCKET_DEBUG_OPEN) || defined(ROCKET_DEBUG_HANGUP))
68562b79 1653 printk(KERN_INFO "rp_hangup of ttyR%d...\n", info->line);
1da177e4
LT		 1654#endif
1655 rp_flush_buffer(tty);
21bed701 1656 if (info->port.flags & ASYNC_CLOSING)
1da177e4 1657 return;
e60a1084 1658 if (info->port.count)
1da177e4
LT		 1659 atomic_dec(&rp_num_ports_open);
1660 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1661
e60a1084 1662 info->port.count = 0;
21bed701 1663 info->port.flags &= ~ASYNC_NORMAL_ACTIVE;
47b01b3a 1664 tty_port_tty_set(&info->port, NULL);
1da177e4
LT		 1665
1666 cp = &info->channel;
1667 sDisRxFIFO(cp);
1668 sDisTransmit(cp);
1669 sDisInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
1670 sDisCTSFlowCtl(cp);
1671 sDisTxSoftFlowCtl(cp);
1672 sClrTxXOFF(cp);
21bed701 1673 info->port.flags &= ~ASYNC_INITIALIZED;
1da177e4 1674
e60a1084 1675 wake_up_interruptible(&info->port.open_wait);
1da177e4
LT		 1676}
1677
1678/*
1679 * Exception handler - write char routine. The RocketPort driver uses a
1680 * double-buffering strategy, with the twist that if the in-memory CPU
1681 * buffer is empty, and there's space in the transmit FIFO, the
1682 * writing routines will write directly to transmit FIFO.
1683 * Write buffer and counters protected by spinlocks
1684 */
bbbbb96f 1685static int rp_put_char(struct tty_struct *tty, unsigned char ch)
1da177e4 1686{
c9f19e96 1687 struct r_port *info = tty->driver_data;
1da177e4
LT		 1688 CHANNEL_t *cp;
1689 unsigned long flags;
1690
1691 if (rocket_paranoia_check(info, "rp_put_char"))
bbbbb96f 1692 return 0;
1da177e4 1693
69f545ea
MK		 1694 /*
1695 * Grab the port write mutex, locking out other processes that try to
1696 * write to this port
1697 */
1698 mutex_lock(&info->write_mtx);
1da177e4
LT		 1699
1700#ifdef ROCKET_DEBUG_WRITE
68562b79 1701 printk(KERN_INFO "rp_put_char %c...\n", ch);
1da177e4
LT		 1702#endif
1703
1704 spin_lock_irqsave(&info->slock, flags);
1705 cp = &info->channel;
1706
1707 if (!tty->stopped && !tty->hw_stopped && info->xmit_fifo_room == 0)
1708 info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
1709
1710 if (tty->stopped || tty->hw_stopped || info->xmit_fifo_room == 0 || info->xmit_cnt != 0) {
1711 info->xmit_buf[info->xmit_head++] = ch;
1712 info->xmit_head &= XMIT_BUF_SIZE - 1;
1713 info->xmit_cnt++;
1714 set_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1715 } else {
1716 sOutB(sGetTxRxDataIO(cp), ch);
1717 info->xmit_fifo_room--;
1718 }
1719 spin_unlock_irqrestore(&info->slock, flags);
69f545ea 1720 mutex_unlock(&info->write_mtx);
bbbbb96f 1721 return 1;
1da177e4
LT		 1722}
1723
1724/*
1725 * Exception handler - write routine, called when user app writes to the device.
69f545ea 1726 * A per port write mutex is used to protect from another process writing to
1da177e4
LT		 1727 * this port at the same time. This other process could be running on the other CPU
1728 * or get control of the CPU if the copy_from_user() blocks due to a page fault (swapped out).
1729 * Spinlocks protect the info xmit members.
1730 */
1731static int rp_write(struct tty_struct *tty,
1732 const unsigned char *buf, int count)
1733{
c9f19e96 1734 struct r_port *info = tty->driver_data;
1da177e4
LT		 1735 CHANNEL_t *cp;
1736 const unsigned char *b;
1737 int c, retval = 0;
1738 unsigned long flags;
1739
1740 if (count <= 0 || rocket_paranoia_check(info, "rp_write"))
1741 return 0;
1742
1e3e8d91
SS		 1743 if (mutex_lock_interruptible(&info->write_mtx))
1744 return -ERESTARTSYS;
1da177e4
LT		 1745
1746#ifdef ROCKET_DEBUG_WRITE
68562b79 1747 printk(KERN_INFO "rp_write %d chars...\n", count);
1da177e4
LT		 1748#endif
1749 cp = &info->channel;
1750
1751 if (!tty->stopped && !tty->hw_stopped && info->xmit_fifo_room < count)
1752 info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
1753
1754 /*
1755 * If the write queue for the port is empty, and there is FIFO space, stuff bytes
1756 * into FIFO. Use the write queue for temp storage.
1757 */
1758 if (!tty->stopped && !tty->hw_stopped && info->xmit_cnt == 0 && info->xmit_fifo_room > 0) {
1759 c = min(count, info->xmit_fifo_room);
1760 b = buf;
1761
1762 /* Push data into FIFO, 2 bytes at a time */
1763 sOutStrW(sGetTxRxDataIO(cp), (unsigned short *) b, c / 2);
1764
1765 /* If there is a byte remaining, write it */
1766 if (c & 1)
1767 sOutB(sGetTxRxDataIO(cp), b[c - 1]);
1768
1769 retval += c;
1770 buf += c;
1771 count -= c;
1772
1773 spin_lock_irqsave(&info->slock, flags);
1774 info->xmit_fifo_room -= c;
1775 spin_unlock_irqrestore(&info->slock, flags);
1776 }
1777
1778 /* If count is zero, we wrote it all and are done */
1779 if (!count)
1780 goto end;
1781
1782 /* Write remaining data into the port's xmit_buf */
1783 while (1) {
47b01b3a
AC		 1784 /* Hung up ? */
1785 if (!test_bit(ASYNC_NORMAL_ACTIVE, &info->port.flags))
1da177e4 1786 goto end;
709107fc
HH		 1787 c = min(count, XMIT_BUF_SIZE - info->xmit_cnt - 1);
1788 c = min(c, XMIT_BUF_SIZE - info->xmit_head);
1da177e4
LT		 1789 if (c <= 0)
1790 break;
1791
1792 b = buf;
1793 memcpy(info->xmit_buf + info->xmit_head, b, c);
1794
1795 spin_lock_irqsave(&info->slock, flags);
1796 info->xmit_head =
1797 (info->xmit_head + c) & (XMIT_BUF_SIZE - 1);
1798 info->xmit_cnt += c;
1799 spin_unlock_irqrestore(&info->slock, flags);
1800
1801 buf += c;
1802 count -= c;
1803 retval += c;
1804 }
1805
1806 if ((retval > 0) && !tty->stopped && !tty->hw_stopped)
1807 set_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1808
1809end:
1810 if (info->xmit_cnt < WAKEUP_CHARS) {
1811 tty_wakeup(tty);
1da177e4
LT		 1812#ifdef ROCKETPORT_HAVE_POLL_WAIT
1813 wake_up_interruptible(&tty->poll_wait);
1814#endif
1815 }
69f545ea 1816 mutex_unlock(&info->write_mtx);
1da177e4
LT		 1817 return retval;
1818}
1819
1820/*
1821 * Return the number of characters that can be sent. We estimate
1822 * only using the in-memory transmit buffer only, and ignore the
1823 * potential space in the transmit FIFO.
1824 */
1825static int rp_write_room(struct tty_struct *tty)
1826{
c9f19e96 1827 struct r_port *info = tty->driver_data;
1da177e4
LT		 1828 int ret;
1829
1830 if (rocket_paranoia_check(info, "rp_write_room"))
1831 return 0;
1832
1833 ret = XMIT_BUF_SIZE - info->xmit_cnt - 1;
1834 if (ret < 0)
1835 ret = 0;
1836#ifdef ROCKET_DEBUG_WRITE
68562b79 1837 printk(KERN_INFO "rp_write_room returns %d...\n", ret);
1da177e4
LT		 1838#endif
1839 return ret;
1840}
1841
1842/*
1843 * Return the number of characters in the buffer. Again, this only
1844 * counts those characters in the in-memory transmit buffer.
1845 */
1846static int rp_chars_in_buffer(struct tty_struct *tty)
1847{
c9f19e96 1848 struct r_port *info = tty->driver_data;
1da177e4
LT		 1849 CHANNEL_t *cp;
1850
1851 if (rocket_paranoia_check(info, "rp_chars_in_buffer"))
1852 return 0;
1853
1854 cp = &info->channel;
1855
1856#ifdef ROCKET_DEBUG_WRITE
68562b79 1857 printk(KERN_INFO "rp_chars_in_buffer returns %d...\n", info->xmit_cnt);
1da177e4
LT		 1858#endif
1859 return info->xmit_cnt;
1860}
1861
1862/*
1863 * Flushes the TX fifo for a port, deletes data in the xmit_buf stored in the
1864 * r_port struct for the port. Note that spinlock are used to protect info members,
1865 * do not call this function if the spinlock is already held.
1866 */
1867static void rp_flush_buffer(struct tty_struct *tty)
1868{
c9f19e96 1869 struct r_port *info = tty->driver_data;
1da177e4
LT		 1870 CHANNEL_t *cp;
1871 unsigned long flags;
1872
1873 if (rocket_paranoia_check(info, "rp_flush_buffer"))
1874 return;
1875
1876 spin_lock_irqsave(&info->slock, flags);
1877 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
1878 spin_unlock_irqrestore(&info->slock, flags);
1879
1da177e4
LT		 1880#ifdef ROCKETPORT_HAVE_POLL_WAIT
1881 wake_up_interruptible(&tty->poll_wait);
1882#endif
1883 tty_wakeup(tty);
1884
1885 cp = &info->channel;
1886 sFlushTxFIFO(cp);
1887}
1888
1889#ifdef CONFIG_PCI
1890
8d5916d3
JS		 1891static struct pci_device_id __devinitdata rocket_pci_ids[] = {
1892 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_ANY_ID) },
1893 { }
1894};
1895MODULE_DEVICE_TABLE(pci, rocket_pci_ids);
1896
1da177e4
LT		 1897/*
1898 * Called when a PCI card is found. Retrieves and stores model information,
1899 * init's aiopic and serial port hardware.
1900 * Inputs: i is the board number (0-n)
1901 */
f15313bf 1902static __init int register_PCI(int i, struct pci_dev *dev)
1da177e4
LT		 1903{
1904 int num_aiops, aiop, max_num_aiops, num_chan, chan;
1905 unsigned int aiopio[MAX_AIOPS_PER_BOARD];
1906 char *str, *board_type;
1907 CONTROLLER_t *ctlp;
1908
1909 int fast_clock = 0;
1910 int altChanRingIndicator = 0;
1911 int ports_per_aiop = 8;
1da177e4
LT		 1912 WordIO_t ConfigIO = 0;
1913 ByteIO_t UPCIRingInd = 0;
1914
1915 if (!dev || pci_enable_device(dev))
1916 return 0;
1917
1918 rcktpt_io_addr[i] = pci_resource_start(dev, 0);
1da177e4
LT		 1919
1920 rcktpt_type[i] = ROCKET_TYPE_NORMAL;
1921 rocketModel[i].loadrm2 = 0;
1922 rocketModel[i].startingPortNumber = nextLineNumber;
1923
1924 /* Depending on the model, set up some config variables */
1925 switch (dev->device) {
1926 case PCI_DEVICE_ID_RP4QUAD:
1927 str = "Quadcable";
1928 max_num_aiops = 1;
1929 ports_per_aiop = 4;
1930 rocketModel[i].model = MODEL_RP4QUAD;
1931 strcpy(rocketModel[i].modelString, "RocketPort 4 port w/quad cable");
1932 rocketModel[i].numPorts = 4;
1933 break;
1934 case PCI_DEVICE_ID_RP8OCTA:
1935 str = "Octacable";
1936 max_num_aiops = 1;
1937 rocketModel[i].model = MODEL_RP8OCTA;
1938 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/octa cable");
1939 rocketModel[i].numPorts = 8;
1940 break;
1941 case PCI_DEVICE_ID_URP8OCTA:
1942 str = "Octacable";
1943 max_num_aiops = 1;
1944 rocketModel[i].model = MODEL_UPCI_RP8OCTA;
1945 strcpy(rocketModel[i].modelString, "RocketPort UPCI 8 port w/octa cable");
1946 rocketModel[i].numPorts = 8;
1947 break;
1948 case PCI_DEVICE_ID_RP8INTF:
1949 str = "8";
1950 max_num_aiops = 1;
1951 rocketModel[i].model = MODEL_RP8INTF;
1952 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/external I/F");
1953 rocketModel[i].numPorts = 8;
1954 break;
1955 case PCI_DEVICE_ID_URP8INTF:
1956 str = "8";
1957 max_num_aiops = 1;
1958 rocketModel[i].model = MODEL_UPCI_RP8INTF;
1959 strcpy(rocketModel[i].modelString, "RocketPort UPCI 8 port w/external I/F");
1960 rocketModel[i].numPorts = 8;
1961 break;
1962 case PCI_DEVICE_ID_RP8J:
1963 str = "8J";
1964 max_num_aiops = 1;
1965 rocketModel[i].model = MODEL_RP8J;
1966 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/RJ11 connectors");
1967 rocketModel[i].numPorts = 8;
1968 break;
1969 case PCI_DEVICE_ID_RP4J:
1970 str = "4J";
1971 max_num_aiops = 1;
1972 ports_per_aiop = 4;
1973 rocketModel[i].model = MODEL_RP4J;
1974 strcpy(rocketModel[i].modelString, "RocketPort 4 port w/RJ45 connectors");
1975 rocketModel[i].numPorts = 4;
1976 break;
1977 case PCI_DEVICE_ID_RP8SNI:
1978 str = "8 (DB78 Custom)";
1979 max_num_aiops = 1;
1980 rocketModel[i].model = MODEL_RP8SNI;
1981 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/ custom DB78");
1982 rocketModel[i].numPorts = 8;
1983 break;
1984 case PCI_DEVICE_ID_RP16SNI:
1985 str = "16 (DB78 Custom)";
1986 max_num_aiops = 2;
1987 rocketModel[i].model = MODEL_RP16SNI;
1988 strcpy(rocketModel[i].modelString, "RocketPort 16 port w/ custom DB78");
1989 rocketModel[i].numPorts = 16;
1990 break;
1991 case PCI_DEVICE_ID_RP16INTF:
1992 str = "16";
1993 max_num_aiops = 2;
1994 rocketModel[i].model = MODEL_RP16INTF;
1995 strcpy(rocketModel[i].modelString, "RocketPort 16 port w/external I/F");
1996 rocketModel[i].numPorts = 16;
1997 break;
1998 case PCI_DEVICE_ID_URP16INTF:
1999 str = "16";
2000 max_num_aiops = 2;
2001 rocketModel[i].model = MODEL_UPCI_RP16INTF;
2002 strcpy(rocketModel[i].modelString, "RocketPort UPCI 16 port w/external I/F");
2003 rocketModel[i].numPorts = 16;
2004 break;
2005 case PCI_DEVICE_ID_CRP16INTF:
2006 str = "16";
2007 max_num_aiops = 2;
2008 rocketModel[i].model = MODEL_CPCI_RP16INTF;
2009 strcpy(rocketModel[i].modelString, "RocketPort Compact PCI 16 port w/external I/F");
2010 rocketModel[i].numPorts = 16;
2011 break;
2012 case PCI_DEVICE_ID_RP32INTF:
2013 str = "32";
2014 max_num_aiops = 4;
2015 rocketModel[i].model = MODEL_RP32INTF;
2016 strcpy(rocketModel[i].modelString, "RocketPort 32 port w/external I/F");
2017 rocketModel[i].numPorts = 32;
2018 break;
2019 case PCI_DEVICE_ID_URP32INTF:
2020 str = "32";
2021 max_num_aiops = 4;
2022 rocketModel[i].model = MODEL_UPCI_RP32INTF;
2023 strcpy(rocketModel[i].modelString, "RocketPort UPCI 32 port w/external I/F");
2024 rocketModel[i].numPorts = 32;
2025 break;
2026 case PCI_DEVICE_ID_RPP4:
2027 str = "Plus Quadcable";
2028 max_num_aiops = 1;
2029 ports_per_aiop = 4;
2030 altChanRingIndicator++;
2031 fast_clock++;
2032 rocketModel[i].model = MODEL_RPP4;
2033 strcpy(rocketModel[i].modelString, "RocketPort Plus 4 port");
2034 rocketModel[i].numPorts = 4;
2035 break;
2036 case PCI_DEVICE_ID_RPP8:
2037 str = "Plus Octacable";
2038 max_num_aiops = 2;
2039 ports_per_aiop = 4;
2040 altChanRingIndicator++;
2041 fast_clock++;
2042 rocketModel[i].model = MODEL_RPP8;
2043 strcpy(rocketModel[i].modelString, "RocketPort Plus 8 port");
2044 rocketModel[i].numPorts = 8;
2045 break;
2046 case PCI_DEVICE_ID_RP2_232:
2047 str = "Plus 2 (RS-232)";
2048 max_num_aiops = 1;
2049 ports_per_aiop = 2;
2050 altChanRingIndicator++;
2051 fast_clock++;
2052 rocketModel[i].model = MODEL_RP2_232;
2053 strcpy(rocketModel[i].modelString, "RocketPort Plus 2 port RS232");
2054 rocketModel[i].numPorts = 2;
2055 break;
2056 case PCI_DEVICE_ID_RP2_422:
2057 str = "Plus 2 (RS-422)";
2058 max_num_aiops = 1;
2059 ports_per_aiop = 2;
2060 altChanRingIndicator++;
2061 fast_clock++;
2062 rocketModel[i].model = MODEL_RP2_422;
2063 strcpy(rocketModel[i].modelString, "RocketPort Plus 2 port RS422");
2064 rocketModel[i].numPorts = 2;
2065 break;
2066 case PCI_DEVICE_ID_RP6M:
2067
2068 max_num_aiops = 1;
2069 ports_per_aiop = 6;
2070 str = "6-port";
2071
57fedc7a
JS		 2072 /* If revision is 1, the rocketmodem flash must be loaded.
2073 * If it is 2 it is a "socketed" version. */
2074 if (dev->revision == 1) {
1da177e4
LT		 2075 rcktpt_type[i] = ROCKET_TYPE_MODEMII;
2076 rocketModel[i].loadrm2 = 1;
2077 } else {
2078 rcktpt_type[i] = ROCKET_TYPE_MODEM;
2079 }
2080
2081 rocketModel[i].model = MODEL_RP6M;
2082 strcpy(rocketModel[i].modelString, "RocketModem 6 port");
2083 rocketModel[i].numPorts = 6;
2084 break;
2085 case PCI_DEVICE_ID_RP4M:
2086 max_num_aiops = 1;
2087 ports_per_aiop = 4;
2088 str = "4-port";
57fedc7a 2089 if (dev->revision == 1) {
1da177e4
LT		 2090 rcktpt_type[i] = ROCKET_TYPE_MODEMII;
2091 rocketModel[i].loadrm2 = 1;
2092 } else {
2093 rcktpt_type[i] = ROCKET_TYPE_MODEM;
2094 }
2095
2096 rocketModel[i].model = MODEL_RP4M;
2097 strcpy(rocketModel[i].modelString, "RocketModem 4 port");
2098 rocketModel[i].numPorts = 4;
2099 break;
2100 default:
2101 str = "(unknown/unsupported)";
2102 max_num_aiops = 0;
2103 break;
2104 }
2105
2106 /*
2107 * Check for UPCI boards.
2108 */
2109
2110 switch (dev->device) {
2111 case PCI_DEVICE_ID_URP32INTF:
2112 case PCI_DEVICE_ID_URP8INTF:
2113 case PCI_DEVICE_ID_URP16INTF:
2114 case PCI_DEVICE_ID_CRP16INTF:
2115 case PCI_DEVICE_ID_URP8OCTA:
2116 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
2117 ConfigIO = pci_resource_start(dev, 1);
2118 if (dev->device == PCI_DEVICE_ID_URP8OCTA) {
2119 UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
2120
2121 /*
2122 * Check for octa or quad cable.
2123 */
2124 if (!
2125 (sInW(ConfigIO + _PCI_9030_GPIO_CTRL) &
2126 PCI_GPIO_CTRL_8PORT)) {
2127 str = "Quadcable";
2128 ports_per_aiop = 4;
2129 rocketModel[i].numPorts = 4;
2130 }
2131 }
2132 break;
2133 case PCI_DEVICE_ID_UPCI_RM3_8PORT:
2134 str = "8 ports";
2135 max_num_aiops = 1;
2136 rocketModel[i].model = MODEL_UPCI_RM3_8PORT;
2137 strcpy(rocketModel[i].modelString, "RocketModem III 8 port");
2138 rocketModel[i].numPorts = 8;
2139 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
2140 UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
2141 ConfigIO = pci_resource_start(dev, 1);
2142 rcktpt_type[i] = ROCKET_TYPE_MODEMIII;
2143 break;
2144 case PCI_DEVICE_ID_UPCI_RM3_4PORT:
2145 str = "4 ports";
2146 max_num_aiops = 1;
2147 rocketModel[i].model = MODEL_UPCI_RM3_4PORT;
2148 strcpy(rocketModel[i].modelString, "RocketModem III 4 port");
2149 rocketModel[i].numPorts = 4;
2150 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
2151 UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
2152 ConfigIO = pci_resource_start(dev, 1);
2153 rcktpt_type[i] = ROCKET_TYPE_MODEMIII;
2154 break;
2155 default:
2156 break;
2157 }
2158
2159 switch (rcktpt_type[i]) {
2160 case ROCKET_TYPE_MODEM:
2161 board_type = "RocketModem";
2162 break;
2163 case ROCKET_TYPE_MODEMII:
2164 board_type = "RocketModem II";
2165 break;
2166 case ROCKET_TYPE_MODEMIII:
2167 board_type = "RocketModem III";
2168 break;
2169 default:
2170 board_type = "RocketPort";
2171 break;
2172 }
2173
2174 if (fast_clock) {
2175 sClockPrescale = 0x12; /* mod 2 (divide by 3) */
2176 rp_baud_base[i] = 921600;
2177 } else {
2178 /*
2179 * If support_low_speed is set, use the slow clock
2180 * prescale, which supports 50 bps
2181 */
2182 if (support_low_speed) {
2183 /* mod 9 (divide by 10) prescale */
2184 sClockPrescale = 0x19;
2185 rp_baud_base[i] = 230400;
2186 } else {
2187 /* mod 4 (devide by 5) prescale */
2188 sClockPrescale = 0x14;
2189 rp_baud_base[i] = 460800;
2190 }
2191 }
2192
2193 for (aiop = 0; aiop < max_num_aiops; aiop++)
2194 aiopio[aiop] = rcktpt_io_addr[i] + (aiop * 0x40);
2195 ctlp = sCtlNumToCtlPtr(i);
2196 num_aiops = sPCIInitController(ctlp, i, aiopio, max_num_aiops, ConfigIO, 0, FREQ_DIS, 0, altChanRingIndicator, UPCIRingInd);
2197 for (aiop = 0; aiop < max_num_aiops; aiop++)
2198 ctlp->AiopNumChan[aiop] = ports_per_aiop;
2199
68562b79
JS		 2200 dev_info(&dev->dev, "comtrol PCI controller #%d found at "
2201 "address %04lx, %d AIOP(s) (%s), creating ttyR%d - %ld\n",
2202 i, rcktpt_io_addr[i], num_aiops, rocketModel[i].modelString,
2203 rocketModel[i].startingPortNumber,
2204 rocketModel[i].startingPortNumber + rocketModel[i].numPorts-1);
1da177e4
LT		 2205
2206 if (num_aiops <= 0) {
2207 rcktpt_io_addr[i] = 0;
2208 return (0);
2209 }
2210 is_PCI[i] = 1;
2211
2212 /* Reset the AIOPIC, init the serial ports */
2213 for (aiop = 0; aiop < num_aiops; aiop++) {
2214 sResetAiopByNum(ctlp, aiop);
2215 num_chan = ports_per_aiop;
2216 for (chan = 0; chan < num_chan; chan++)
2217 init_r_port(i, aiop, chan, dev);
2218 }
2219
2220 /* Rocket modems must be reset */
2221 if ((rcktpt_type[i] == ROCKET_TYPE_MODEM) ||
2222 (rcktpt_type[i] == ROCKET_TYPE_MODEMII) ||
2223 (rcktpt_type[i] == ROCKET_TYPE_MODEMIII)) {
2224 num_chan = ports_per_aiop;
2225 for (chan = 0; chan < num_chan; chan++)
2226 sPCIModemReset(ctlp, chan, 1);
48a67f5d 2227 msleep(500);
1da177e4
LT		 2228 for (chan = 0; chan < num_chan; chan++)
2229 sPCIModemReset(ctlp, chan, 0);
48a67f5d 2230 msleep(500);
1da177e4
LT		 2231 rmSpeakerReset(ctlp, rocketModel[i].model);
2232 }
2233 return (1);
2234}
2235
2236/*
2237 * Probes for PCI cards, inits them if found
2238 * Input: board_found = number of ISA boards already found, or the
2239 * starting board number
2240 * Returns: Number of PCI boards found
2241 */
2242static int __init init_PCI(int boards_found)
2243{
2244 struct pci_dev *dev = NULL;
2245 int count = 0;
2246
2247 /* Work through the PCI device list, pulling out ours */
606d099c 2248 while ((dev = pci_get_device(PCI_VENDOR_ID_RP, PCI_ANY_ID, dev))) {
1da177e4
LT		 2249 if (register_PCI(count + boards_found, dev))
2250 count++;
2251 }
2252 return (count);
2253}
2254
2255#endif /* CONFIG_PCI */
2256
2257/*
2258 * Probes for ISA cards
2259 * Input: i = the board number to look for
2260 * Returns: 1 if board found, 0 else
2261 */
2262static int __init init_ISA(int i)
2263{
2264 int num_aiops, num_chan = 0, total_num_chan = 0;
2265 int aiop, chan;
2266 unsigned int aiopio[MAX_AIOPS_PER_BOARD];
2267 CONTROLLER_t *ctlp;
2268 char *type_string;
2269
2270 /* If io_addr is zero, no board configured */
2271 if (rcktpt_io_addr[i] == 0)
2272 return (0);
2273
2274 /* Reserve the IO region */
2275 if (!request_region(rcktpt_io_addr[i], 64, "Comtrol RocketPort")) {
68562b79
JS		 2276 printk(KERN_ERR "Unable to reserve IO region for configured "
2277 "ISA RocketPort at address 0x%lx, board not "
2278 "installed...\n", rcktpt_io_addr[i]);
1da177e4
LT		 2279 rcktpt_io_addr[i] = 0;
2280 return (0);
2281 }
2282
2283 ctlp = sCtlNumToCtlPtr(i);
2284
2285 ctlp->boardType = rcktpt_type[i];
2286
2287 switch (rcktpt_type[i]) {
2288 case ROCKET_TYPE_PC104:
2289 type_string = "(PC104)";
2290 break;
2291 case ROCKET_TYPE_MODEM:
2292 type_string = "(RocketModem)";
2293 break;
2294 case ROCKET_TYPE_MODEMII:
2295 type_string = "(RocketModem II)";
2296 break;
2297 default:
2298 type_string = "";
2299 break;
2300 }
2301
2302 /*
2303 * If support_low_speed is set, use the slow clock prescale,
2304 * which supports 50 bps
2305 */
2306 if (support_low_speed) {
2307 sClockPrescale = 0x19; /* mod 9 (divide by 10) prescale */
2308 rp_baud_base[i] = 230400;
2309 } else {
2310 sClockPrescale = 0x14; /* mod 4 (devide by 5) prescale */
2311 rp_baud_base[i] = 460800;
2312 }
2313
2314 for (aiop = 0; aiop < MAX_AIOPS_PER_BOARD; aiop++)
2315 aiopio[aiop] = rcktpt_io_addr[i] + (aiop * 0x400);
2316
2317 num_aiops = sInitController(ctlp, i, controller + (i * 0x400), aiopio, MAX_AIOPS_PER_BOARD, 0, FREQ_DIS, 0);
2318
2319 if (ctlp->boardType == ROCKET_TYPE_PC104) {
2320 sEnAiop(ctlp, 2); /* only one AIOPIC, but these */
2321 sEnAiop(ctlp, 3); /* CSels used for other stuff */
2322 }
2323
2324 /* If something went wrong initing the AIOP's release the ISA IO memory */
2325 if (num_aiops <= 0) {
2326 release_region(rcktpt_io_addr[i], 64);
2327 rcktpt_io_addr[i] = 0;
2328 return (0);
2329 }
2330
2331 rocketModel[i].startingPortNumber = nextLineNumber;
2332
2333 for (aiop = 0; aiop < num_aiops; aiop++) {
2334 sResetAiopByNum(ctlp, aiop);
2335 sEnAiop(ctlp, aiop);
2336 num_chan = sGetAiopNumChan(ctlp, aiop);
2337 total_num_chan += num_chan;
2338 for (chan = 0; chan < num_chan; chan++)
2339 init_r_port(i, aiop, chan, NULL);
2340 }
2341 is_PCI[i] = 0;
2342 if ((rcktpt_type[i] == ROCKET_TYPE_MODEM) || (rcktpt_type[i] == ROCKET_TYPE_MODEMII)) {
2343 num_chan = sGetAiopNumChan(ctlp, 0);
2344 total_num_chan = num_chan;
2345 for (chan = 0; chan < num_chan; chan++)
2346 sModemReset(ctlp, chan, 1);
48a67f5d 2347 msleep(500);
1da177e4
LT		 2348 for (chan = 0; chan < num_chan; chan++)
2349 sModemReset(ctlp, chan, 0);
48a67f5d 2350 msleep(500);
1da177e4
LT		 2351 strcpy(rocketModel[i].modelString, "RocketModem ISA");
2352 } else {
2353 strcpy(rocketModel[i].modelString, "RocketPort ISA");
2354 }
2355 rocketModel[i].numPorts = total_num_chan;
2356 rocketModel[i].model = MODEL_ISA;
2357
2358 printk(KERN_INFO "RocketPort ISA card #%d found at 0x%lx - %d AIOPs %s\n",
2359 i, rcktpt_io_addr[i], num_aiops, type_string);
2360
2361 printk(KERN_INFO "Installing %s, creating /dev/ttyR%d - %ld\n",
2362 rocketModel[i].modelString,
2363 rocketModel[i].startingPortNumber,
2364 rocketModel[i].startingPortNumber +
2365 rocketModel[i].numPorts - 1);
2366
2367 return (1);
2368}
2369
b68e31d0 2370static const struct tty_operations rocket_ops = {
1da177e4
LT		 2371 .open = rp_open,
2372 .close = rp_close,
2373 .write = rp_write,
2374 .put_char = rp_put_char,
2375 .write_room = rp_write_room,
2376 .chars_in_buffer = rp_chars_in_buffer,
2377 .flush_buffer = rp_flush_buffer,
2378 .ioctl = rp_ioctl,
2379 .throttle = rp_throttle,
2380 .unthrottle = rp_unthrottle,
2381 .set_termios = rp_set_termios,
2382 .stop = rp_stop,
2383 .start = rp_start,
2384 .hangup = rp_hangup,
2385 .break_ctl = rp_break,
2386 .send_xchar = rp_send_xchar,
2387 .wait_until_sent = rp_wait_until_sent,
2388 .tiocmget = rp_tiocmget,
2389 .tiocmset = rp_tiocmset,
2390};
2391
31f35939
AC		 2392static const struct tty_port_operations rocket_port_ops = {
2393 .carrier_raised = carrier_raised,
5d951fb4 2394 .raise_dtr_rts = raise_dtr_rts,
31f35939
AC		 2395};
2396
1da177e4
LT		 2397/*
2398 * The module "startup" routine; it's run when the module is loaded.
2399 */
d269cdd0 2400static int __init rp_init(void)
1da177e4 2401{
4384a3fa 2402 int ret = -ENOMEM, pci_boards_found, isa_boards_found, i;
1da177e4
LT		 2403
2404 printk(KERN_INFO "RocketPort device driver module, version %s, %s\n",
2405 ROCKET_VERSION, ROCKET_DATE);
2406
2407 rocket_driver = alloc_tty_driver(MAX_RP_PORTS);
2408 if (!rocket_driver)
4384a3fa 2409 goto err;
1da177e4 2410
1da177e4
LT		 2411 /*
2412 * If board 1 is non-zero, there is at least one ISA configured. If controller is
2413 * zero, use the default controller IO address of board1 + 0x40.
2414 */
2415 if (board1) {
2416 if (controller == 0)
2417 controller = board1 + 0x40;
2418 } else {
2419 controller = 0; /* Used as a flag, meaning no ISA boards */
2420 }
2421
2422 /* If an ISA card is configured, reserve the 4 byte IO space for the Mudbac controller */
2423 if (controller && (!request_region(controller, 4, "Comtrol RocketPort"))) {
4384a3fa
JS		 2424 printk(KERN_ERR "Unable to reserve IO region for first "
2425 "configured ISA RocketPort controller 0x%lx. "
2426 "Driver exiting\n", controller);
2427 ret = -EBUSY;
2428 goto err_tty;
1da177e4
LT		 2429 }
2430
2431 /* Store ISA variable retrieved from command line or .conf file. */
2432 rcktpt_io_addr[0] = board1;
2433 rcktpt_io_addr[1] = board2;
2434 rcktpt_io_addr[2] = board3;
2435 rcktpt_io_addr[3] = board4;
2436
2437 rcktpt_type[0] = modem1 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2438 rcktpt_type[0] = pc104_1[0] ? ROCKET_TYPE_PC104 : rcktpt_type[0];
2439 rcktpt_type[1] = modem2 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2440 rcktpt_type[1] = pc104_2[0] ? ROCKET_TYPE_PC104 : rcktpt_type[1];
2441 rcktpt_type[2] = modem3 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2442 rcktpt_type[2] = pc104_3[0] ? ROCKET_TYPE_PC104 : rcktpt_type[2];
2443 rcktpt_type[3] = modem4 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2444 rcktpt_type[3] = pc104_4[0] ? ROCKET_TYPE_PC104 : rcktpt_type[3];
2445
2446 /*
2447 * Set up the tty driver structure and then register this
2448 * driver with the tty layer.
2449 */
2450
2451 rocket_driver->owner = THIS_MODULE;
331b8319 2452 rocket_driver->flags = TTY_DRIVER_DYNAMIC_DEV;
1da177e4
LT		 2453 rocket_driver->name = "ttyR";
2454 rocket_driver->driver_name = "Comtrol RocketPort";
2455 rocket_driver->major = TTY_ROCKET_MAJOR;
2456 rocket_driver->minor_start = 0;
2457 rocket_driver->type = TTY_DRIVER_TYPE_SERIAL;
2458 rocket_driver->subtype = SERIAL_TYPE_NORMAL;
2459 rocket_driver->init_termios = tty_std_termios;
2460 rocket_driver->init_termios.c_cflag =
2461 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
606d099c
AC		 2462 rocket_driver->init_termios.c_ispeed = 9600;
2463 rocket_driver->init_termios.c_ospeed = 9600;
1da177e4 2464#ifdef ROCKET_SOFT_FLOW
ac6aec2f 2465 rocket_driver->flags |= TTY_DRIVER_REAL_RAW;
1da177e4
LT		 2466#endif
2467 tty_set_operations(rocket_driver, &rocket_ops);
2468
4384a3fa
JS		 2469 ret = tty_register_driver(rocket_driver);
2470 if (ret < 0) {
2471 printk(KERN_ERR "Couldn't install tty RocketPort driver\n");
2472 goto err_tty;
1da177e4
LT		 2473 }
2474
2475#ifdef ROCKET_DEBUG_OPEN
2476 printk(KERN_INFO "RocketPort driver is major %d\n", rocket_driver.major);
2477#endif
2478
2479 /*
2480 * OK, let's probe each of the controllers looking for boards. Any boards found
2481 * will be initialized here.
2482 */
2483 isa_boards_found = 0;
2484 pci_boards_found = 0;
2485
2486 for (i = 0; i < NUM_BOARDS; i++) {
2487 if (init_ISA(i))
2488 isa_boards_found++;
2489 }
2490
2491#ifdef CONFIG_PCI
2492 if (isa_boards_found < NUM_BOARDS)
2493 pci_boards_found = init_PCI(isa_boards_found);
2494#endif
2495
2496 max_board = pci_boards_found + isa_boards_found;
2497
2498 if (max_board == 0) {
4384a3fa
JS		 2499 printk(KERN_ERR "No rocketport ports found; unloading driver\n");
2500 ret = -ENXIO;
2501 goto err_ttyu;
1da177e4
LT		 2502 }
2503
2504 return 0;
4384a3fa
JS		 2505err_ttyu:
2506 tty_unregister_driver(rocket_driver);
2507err_tty:
2508 put_tty_driver(rocket_driver);
2509err:
2510 return ret;
1da177e4
LT		 2511}
2512
1da177e4
LT		 2513
2514static void rp_cleanup_module(void)
2515{
2516 int retval;
2517 int i;
2518
2519 del_timer_sync(&rocket_timer);
2520
2521 retval = tty_unregister_driver(rocket_driver);
2522 if (retval)
68562b79 2523 printk(KERN_ERR "Error %d while trying to unregister "
1da177e4 2524 "rocketport driver\n", -retval);
1da177e4 2525
735d5661 2526 for (i = 0; i < MAX_RP_PORTS; i++)
ac6aec2f
JS		 2527 if (rp_table[i]) {
2528 tty_unregister_device(rocket_driver, i);
2529 kfree(rp_table[i]);
2530 }
2531
2532 put_tty_driver(rocket_driver);
1da177e4
LT		 2533
2534 for (i = 0; i < NUM_BOARDS; i++) {
2535 if (rcktpt_io_addr[i] <= 0 || is_PCI[i])
2536 continue;
2537 release_region(rcktpt_io_addr[i], 64);
2538 }
2539 if (controller)
2540 release_region(controller, 4);
2541}
1da177e4 2542
1da177e4
LT		 2543/***************************************************************************
2544Function: sInitController
2545Purpose: Initialization of controller global registers and controller
2546 structure.
2547Call: sInitController(CtlP,CtlNum,MudbacIO,AiopIOList,AiopIOListSize,
2548 IRQNum,Frequency,PeriodicOnly)
2549 CONTROLLER_T *CtlP; Ptr to controller structure
2550 int CtlNum; Controller number
2551 ByteIO_t MudbacIO; Mudbac base I/O address.
2552 ByteIO_t *AiopIOList; List of I/O addresses for each AIOP.
2553 This list must be in the order the AIOPs will be found on the
2554 controller. Once an AIOP in the list is not found, it is
2555 assumed that there are no more AIOPs on the controller.
2556 int AiopIOListSize; Number of addresses in AiopIOList
2557 int IRQNum; Interrupt Request number. Can be any of the following:
2558 0: Disable global interrupts
2559 3: IRQ 3
2560 4: IRQ 4
2561 5: IRQ 5
2562 9: IRQ 9
2563 10: IRQ 10
2564 11: IRQ 11
2565 12: IRQ 12
2566 15: IRQ 15
2567 Byte_t Frequency: A flag identifying the frequency
2568 of the periodic interrupt, can be any one of the following:
2569 FREQ_DIS - periodic interrupt disabled
2570 FREQ_137HZ - 137 Hertz
2571 FREQ_69HZ - 69 Hertz
2572 FREQ_34HZ - 34 Hertz
2573 FREQ_17HZ - 17 Hertz
2574 FREQ_9HZ - 9 Hertz
2575 FREQ_4HZ - 4 Hertz
2576 If IRQNum is set to 0 the Frequency parameter is
2577 overidden, it is forced to a value of FREQ_DIS.
f15313bf 2578 int PeriodicOnly: 1 if all interrupts except the periodic
1da177e4 2579 interrupt are to be blocked.
f15313bf 2580 0 is both the periodic interrupt and
1da177e4
LT		 2581 other channel interrupts are allowed.
2582 If IRQNum is set to 0 the PeriodicOnly parameter is
f15313bf 2583 overidden, it is forced to a value of 0.
1da177e4
LT		 2584Return: int: Number of AIOPs on the controller, or CTLID_NULL if controller
2585 initialization failed.
2586
2587Comments:
2588 If periodic interrupts are to be disabled but AIOP interrupts
f15313bf 2589 are allowed, set Frequency to FREQ_DIS and PeriodicOnly to 0.
1da177e4
LT		 2590
2591 If interrupts are to be completely disabled set IRQNum to 0.
2592
f15313bf 2593 Setting Frequency to FREQ_DIS and PeriodicOnly to 1 is an
1da177e4
LT		 2594 invalid combination.
2595
2596 This function performs initialization of global interrupt modes,
2597 but it does not actually enable global interrupts. To enable
2598 and disable global interrupts use functions sEnGlobalInt() and
2599 sDisGlobalInt(). Enabling of global interrupts is normally not
2600 done until all other initializations are complete.
2601
2602 Even if interrupts are globally enabled, they must also be
2603 individually enabled for each channel that is to generate
2604 interrupts.
2605
2606Warnings: No range checking on any of the parameters is done.
2607
2608 No context switches are allowed while executing this function.
2609
2610 After this function all AIOPs on the controller are disabled,
2611 they can be enabled with sEnAiop().
2612*/
f15313bf
AB		 2613static int sInitController(CONTROLLER_T * CtlP, int CtlNum, ByteIO_t MudbacIO,
2614 ByteIO_t * AiopIOList, int AiopIOListSize,
2615 int IRQNum, Byte_t Frequency, int PeriodicOnly)
1da177e4
LT		 2616{
2617 int i;
2618 ByteIO_t io;
2619 int done;
2620
2621 CtlP->AiopIntrBits = aiop_intr_bits;
2622 CtlP->AltChanRingIndicator = 0;
2623 CtlP->CtlNum = CtlNum;
2624 CtlP->CtlID = CTLID_0001; /* controller release 1 */
2625 CtlP->BusType = isISA;
2626 CtlP->MBaseIO = MudbacIO;
2627 CtlP->MReg1IO = MudbacIO + 1;
2628 CtlP->MReg2IO = MudbacIO + 2;
2629 CtlP->MReg3IO = MudbacIO + 3;
2630#if 1
2631 CtlP->MReg2 = 0; /* interrupt disable */
2632 CtlP->MReg3 = 0; /* no periodic interrupts */
2633#else
2634 if (sIRQMap[IRQNum] == 0) { /* interrupts globally disabled */
2635 CtlP->MReg2 = 0; /* interrupt disable */
2636 CtlP->MReg3 = 0; /* no periodic interrupts */
2637 } else {
2638 CtlP->MReg2 = sIRQMap[IRQNum]; /* set IRQ number */
2639 CtlP->MReg3 = Frequency; /* set frequency */
2640 if (PeriodicOnly) { /* periodic interrupt only */
2641 CtlP->MReg3 |= PERIODIC_ONLY;
2642 }
2643 }
2644#endif
2645 sOutB(CtlP->MReg2IO, CtlP->MReg2);
2646 sOutB(CtlP->MReg3IO, CtlP->MReg3);
2647 sControllerEOI(CtlP); /* clear EOI if warm init */
2648 /* Init AIOPs */
2649 CtlP->NumAiop = 0;
2650 for (i = done = 0; i < AiopIOListSize; i++) {
2651 io = AiopIOList[i];
2652 CtlP->AiopIO[i] = (WordIO_t) io;
2653 CtlP->AiopIntChanIO[i] = io + _INT_CHAN;
2654 sOutB(CtlP->MReg2IO, CtlP->MReg2 | (i & 0x03)); /* AIOP index */
2655 sOutB(MudbacIO, (Byte_t) (io >> 6)); /* set up AIOP I/O in MUDBAC */
2656 if (done)
2657 continue;
2658 sEnAiop(CtlP, i); /* enable the AIOP */
2659 CtlP->AiopID[i] = sReadAiopID(io); /* read AIOP ID */
2660 if (CtlP->AiopID[i] == AIOPID_NULL) /* if AIOP does not exist */
2661 done = 1; /* done looking for AIOPs */
2662 else {
2663 CtlP->AiopNumChan[i] = sReadAiopNumChan((WordIO_t) io); /* num channels in AIOP */
2664 sOutW((WordIO_t) io + _INDX_ADDR, _CLK_PRE); /* clock prescaler */
2665 sOutB(io + _INDX_DATA, sClockPrescale);
2666 CtlP->NumAiop++; /* bump count of AIOPs */
2667 }
2668 sDisAiop(CtlP, i); /* disable AIOP */
2669 }
2670
2671 if (CtlP->NumAiop == 0)
2672 return (-1);
2673 else
2674 return (CtlP->NumAiop);
2675}
2676
2677/***************************************************************************
2678Function: sPCIInitController
2679Purpose: Initialization of controller global registers and controller
2680 structure.
2681Call: sPCIInitController(CtlP,CtlNum,AiopIOList,AiopIOListSize,
2682 IRQNum,Frequency,PeriodicOnly)
2683 CONTROLLER_T *CtlP; Ptr to controller structure
2684 int CtlNum; Controller number
2685 ByteIO_t *AiopIOList; List of I/O addresses for each AIOP.
2686 This list must be in the order the AIOPs will be found on the
2687 controller. Once an AIOP in the list is not found, it is
2688 assumed that there are no more AIOPs on the controller.
2689 int AiopIOListSize; Number of addresses in AiopIOList
2690 int IRQNum; Interrupt Request number. Can be any of the following:
2691 0: Disable global interrupts
2692 3: IRQ 3
2693 4: IRQ 4
2694 5: IRQ 5
2695 9: IRQ 9
2696 10: IRQ 10
2697 11: IRQ 11
2698 12: IRQ 12
2699 15: IRQ 15
2700 Byte_t Frequency: A flag identifying the frequency
2701 of the periodic interrupt, can be any one of the following:
2702 FREQ_DIS - periodic interrupt disabled
2703 FREQ_137HZ - 137 Hertz
2704 FREQ_69HZ - 69 Hertz
2705 FREQ_34HZ - 34 Hertz
2706 FREQ_17HZ - 17 Hertz
2707 FREQ_9HZ - 9 Hertz
2708 FREQ_4HZ - 4 Hertz
2709 If IRQNum is set to 0 the Frequency parameter is
2710 overidden, it is forced to a value of FREQ_DIS.
f15313bf 2711 int PeriodicOnly: 1 if all interrupts except the periodic
1da177e4 2712 interrupt are to be blocked.
f15313bf 2713 0 is both the periodic interrupt and
1da177e4
LT		 2714 other channel interrupts are allowed.
2715 If IRQNum is set to 0 the PeriodicOnly parameter is
f15313bf 2716 overidden, it is forced to a value of 0.
1da177e4
LT		 2717Return: int: Number of AIOPs on the controller, or CTLID_NULL if controller
2718 initialization failed.
2719
2720Comments:
2721 If periodic interrupts are to be disabled but AIOP interrupts
f15313bf 2722 are allowed, set Frequency to FREQ_DIS and PeriodicOnly to 0.
1da177e4
LT		 2723
2724 If interrupts are to be completely disabled set IRQNum to 0.
2725
f15313bf 2726 Setting Frequency to FREQ_DIS and PeriodicOnly to 1 is an
1da177e4
LT		 2727 invalid combination.
2728
2729 This function performs initialization of global interrupt modes,
2730 but it does not actually enable global interrupts. To enable
2731 and disable global interrupts use functions sEnGlobalInt() and
2732 sDisGlobalInt(). Enabling of global interrupts is normally not
2733 done until all other initializations are complete.
2734
2735 Even if interrupts are globally enabled, they must also be
2736 individually enabled for each channel that is to generate
2737 interrupts.
2738
2739Warnings: No range checking on any of the parameters is done.
2740
2741 No context switches are allowed while executing this function.
2742
2743 After this function all AIOPs on the controller are disabled,
2744 they can be enabled with sEnAiop().
2745*/
f15313bf
AB		 2746static int sPCIInitController(CONTROLLER_T * CtlP, int CtlNum,
2747 ByteIO_t * AiopIOList, int AiopIOListSize,
2748 WordIO_t ConfigIO, int IRQNum, Byte_t Frequency,
2749 int PeriodicOnly, int altChanRingIndicator,
2750 int UPCIRingInd)
1da177e4
LT		 2751{
2752 int i;
2753 ByteIO_t io;
2754
2755 CtlP->AltChanRingIndicator = altChanRingIndicator;
2756 CtlP->UPCIRingInd = UPCIRingInd;
2757 CtlP->CtlNum = CtlNum;
2758 CtlP->CtlID = CTLID_0001; /* controller release 1 */
2759 CtlP->BusType = isPCI; /* controller release 1 */
2760
2761 if (ConfigIO) {
2762 CtlP->isUPCI = 1;
2763 CtlP->PCIIO = ConfigIO + _PCI_9030_INT_CTRL;
2764 CtlP->PCIIO2 = ConfigIO + _PCI_9030_GPIO_CTRL;
2765 CtlP->AiopIntrBits = upci_aiop_intr_bits;
2766 } else {
2767 CtlP->isUPCI = 0;
2768 CtlP->PCIIO =
2769 (WordIO_t) ((ByteIO_t) AiopIOList[0] + _PCI_INT_FUNC);
2770 CtlP->AiopIntrBits = aiop_intr_bits;
2771 }
2772
2773 sPCIControllerEOI(CtlP); /* clear EOI if warm init */
2774 /* Init AIOPs */
2775 CtlP->NumAiop = 0;
2776 for (i = 0; i < AiopIOListSize; i++) {
2777 io = AiopIOList[i];
2778 CtlP->AiopIO[i] = (WordIO_t) io;
2779 CtlP->AiopIntChanIO[i] = io + _INT_CHAN;
2780
2781 CtlP->AiopID[i] = sReadAiopID(io); /* read AIOP ID */
2782 if (CtlP->AiopID[i] == AIOPID_NULL) /* if AIOP does not exist */
2783 break; /* done looking for AIOPs */
2784
2785 CtlP->AiopNumChan[i] = sReadAiopNumChan((WordIO_t) io); /* num channels in AIOP */
2786 sOutW((WordIO_t) io + _INDX_ADDR, _CLK_PRE); /* clock prescaler */
2787 sOutB(io + _INDX_DATA, sClockPrescale);
2788 CtlP->NumAiop++; /* bump count of AIOPs */
2789 }
2790
2791 if (CtlP->NumAiop == 0)
2792 return (-1);
2793 else
2794 return (CtlP->NumAiop);
2795}
2796
2797/***************************************************************************
2798Function: sReadAiopID
2799Purpose: Read the AIOP idenfication number directly from an AIOP.
2800Call: sReadAiopID(io)
2801 ByteIO_t io: AIOP base I/O address
2802Return: int: Flag AIOPID_XXXX if a valid AIOP is found, where X
2803 is replace by an identifying number.
2804 Flag AIOPID_NULL if no valid AIOP is found
2805Warnings: No context switches are allowed while executing this function.
2806
2807*/
f15313bf 2808static int sReadAiopID(ByteIO_t io)
1da177e4
LT		 2809{
2810 Byte_t AiopID; /* ID byte from AIOP */
2811
2812 sOutB(io + _CMD_REG, RESET_ALL); /* reset AIOP */
2813 sOutB(io + _CMD_REG, 0x0);
2814 AiopID = sInW(io + _CHN_STAT0) & 0x07;
2815 if (AiopID == 0x06)
2816 return (1);
2817 else /* AIOP does not exist */
2818 return (-1);
2819}
2820
2821/***************************************************************************
2822Function: sReadAiopNumChan
2823Purpose: Read the number of channels available in an AIOP directly from
2824 an AIOP.
2825Call: sReadAiopNumChan(io)
2826 WordIO_t io: AIOP base I/O address
2827Return: int: The number of channels available
2828Comments: The number of channels is determined by write/reads from identical
2829 offsets within the SRAM address spaces for channels 0 and 4.
2830 If the channel 4 space is mirrored to channel 0 it is a 4 channel
2831 AIOP, otherwise it is an 8 channel.
2832Warnings: No context switches are allowed while executing this function.
2833*/
f15313bf 2834static int sReadAiopNumChan(WordIO_t io)
1da177e4
LT		 2835{
2836 Word_t x;
2837 static Byte_t R[4] = { 0x00, 0x00, 0x34, 0x12 };
2838
2839 /* write to chan 0 SRAM */
457fb605 2840 out32((DWordIO_t) io + _INDX_ADDR, R);
1da177e4
LT		 2841 sOutW(io + _INDX_ADDR, 0); /* read from SRAM, chan 0 */
2842 x = sInW(io + _INDX_DATA);
2843 sOutW(io + _INDX_ADDR, 0x4000); /* read from SRAM, chan 4 */
2844 if (x != sInW(io + _INDX_DATA)) /* if different must be 8 chan */
2845 return (8);
2846 else
2847 return (4);
2848}
2849
2850/***************************************************************************
2851Function: sInitChan
2852Purpose: Initialization of a channel and channel structure
2853Call: sInitChan(CtlP,ChP,AiopNum,ChanNum)
2854 CONTROLLER_T *CtlP; Ptr to controller structure
2855 CHANNEL_T *ChP; Ptr to channel structure
2856 int AiopNum; AIOP number within controller
2857 int ChanNum; Channel number within AIOP
f15313bf 2858Return: int: 1 if initialization succeeded, 0 if it fails because channel
1da177e4
LT		 2859 number exceeds number of channels available in AIOP.
2860Comments: This function must be called before a channel can be used.
2861Warnings: No range checking on any of the parameters is done.
2862
2863 No context switches are allowed while executing this function.
2864*/
f15313bf
AB		 2865static int sInitChan(CONTROLLER_T * CtlP, CHANNEL_T * ChP, int AiopNum,
2866 int ChanNum)
1da177e4
LT		 2867{
2868 int i;
2869 WordIO_t AiopIO;
2870 WordIO_t ChIOOff;
2871 Byte_t *ChR;
2872 Word_t ChOff;
2873 static Byte_t R[4];
2874 int brd9600;
2875
2876 if (ChanNum >= CtlP->AiopNumChan[AiopNum])
f15313bf 2877 return 0; /* exceeds num chans in AIOP */
1da177e4
LT		 2878
2879 /* Channel, AIOP, and controller identifiers */
2880 ChP->CtlP = CtlP;
2881 ChP->ChanID = CtlP->AiopID[AiopNum];
2882 ChP->AiopNum = AiopNum;
2883 ChP->ChanNum = ChanNum;
2884
2885 /* Global direct addresses */
2886 AiopIO = CtlP->AiopIO[AiopNum];
2887 ChP->Cmd = (ByteIO_t) AiopIO + _CMD_REG;
2888 ChP->IntChan = (ByteIO_t) AiopIO + _INT_CHAN;
2889 ChP->IntMask = (ByteIO_t) AiopIO + _INT_MASK;
2890 ChP->IndexAddr = (DWordIO_t) AiopIO + _INDX_ADDR;
2891 ChP->IndexData = AiopIO + _INDX_DATA;
2892
2893 /* Channel direct addresses */
2894 ChIOOff = AiopIO + ChP->ChanNum * 2;
2895 ChP->TxRxData = ChIOOff + _TD0;
2896 ChP->ChanStat = ChIOOff + _CHN_STAT0;
2897 ChP->TxRxCount = ChIOOff + _FIFO_CNT0;
2898 ChP->IntID = (ByteIO_t) AiopIO + ChP->ChanNum + _INT_ID0;
2899
2900 /* Initialize the channel from the RData array */
2901 for (i = 0; i < RDATASIZE; i += 4) {
2902 R[0] = RData[i];
2903 R[1] = RData[i + 1] + 0x10 * ChanNum;
2904 R[2] = RData[i + 2];
2905 R[3] = RData[i + 3];
457fb605 2906 out32(ChP->IndexAddr, R);
1da177e4
LT		 2907 }
2908
2909 ChR = ChP->R;
2910 for (i = 0; i < RREGDATASIZE; i += 4) {
2911 ChR[i] = RRegData[i];
2912 ChR[i + 1] = RRegData[i + 1] + 0x10 * ChanNum;
2913 ChR[i + 2] = RRegData[i + 2];
2914 ChR[i + 3] = RRegData[i + 3];
2915 }
2916
2917 /* Indexed registers */
2918 ChOff = (Word_t) ChanNum *0x1000;
2919
2920 if (sClockPrescale == 0x14)
2921 brd9600 = 47;
2922 else
2923 brd9600 = 23;
2924
2925 ChP->BaudDiv[0] = (Byte_t) (ChOff + _BAUD);
2926 ChP->BaudDiv[1] = (Byte_t) ((ChOff + _BAUD) >> 8);
2927 ChP->BaudDiv[2] = (Byte_t) brd9600;
2928 ChP->BaudDiv[3] = (Byte_t) (brd9600 >> 8);
457fb605 2929 out32(ChP->IndexAddr, ChP->BaudDiv);
1da177e4
LT		 2930
2931 ChP->TxControl[0] = (Byte_t) (ChOff + _TX_CTRL);
2932 ChP->TxControl[1] = (Byte_t) ((ChOff + _TX_CTRL) >> 8);
2933 ChP->TxControl[2] = 0;
2934 ChP->TxControl[3] = 0;
457fb605 2935 out32(ChP->IndexAddr, ChP->TxControl);
1da177e4
LT		 2936
2937 ChP->RxControl[0] = (Byte_t) (ChOff + _RX_CTRL);
2938 ChP->RxControl[1] = (Byte_t) ((ChOff + _RX_CTRL) >> 8);
2939 ChP->RxControl[2] = 0;
2940 ChP->RxControl[3] = 0;
457fb605 2941 out32(ChP->IndexAddr, ChP->RxControl);
1da177e4
LT		 2942
2943 ChP->TxEnables[0] = (Byte_t) (ChOff + _TX_ENBLS);
2944 ChP->TxEnables[1] = (Byte_t) ((ChOff + _TX_ENBLS) >> 8);
2945 ChP->TxEnables[2] = 0;
2946 ChP->TxEnables[3] = 0;
457fb605 2947 out32(ChP->IndexAddr, ChP->TxEnables);
1da177e4
LT		 2948
2949 ChP->TxCompare[0] = (Byte_t) (ChOff + _TXCMP1);
2950 ChP->TxCompare[1] = (Byte_t) ((ChOff + _TXCMP1) >> 8);
2951 ChP->TxCompare[2] = 0;
2952 ChP->TxCompare[3] = 0;
457fb605 2953 out32(ChP->IndexAddr, ChP->TxCompare);
1da177e4
LT		 2954
2955 ChP->TxReplace1[0] = (Byte_t) (ChOff + _TXREP1B1);
2956 ChP->TxReplace1[1] = (Byte_t) ((ChOff + _TXREP1B1) >> 8);
2957 ChP->TxReplace1[2] = 0;
2958 ChP->TxReplace1[3] = 0;
457fb605 2959 out32(ChP->IndexAddr, ChP->TxReplace1);
1da177e4
LT		 2960
2961 ChP->TxReplace2[0] = (Byte_t) (ChOff + _TXREP2);
2962 ChP->TxReplace2[1] = (Byte_t) ((ChOff + _TXREP2) >> 8);
2963 ChP->TxReplace2[2] = 0;
2964 ChP->TxReplace2[3] = 0;
457fb605 2965 out32(ChP->IndexAddr, ChP->TxReplace2);
1da177e4
LT		 2966
2967 ChP->TxFIFOPtrs = ChOff + _TXF_OUTP;
2968 ChP->TxFIFO = ChOff + _TX_FIFO;
2969
2970 sOutB(ChP->Cmd, (Byte_t) ChanNum | RESTXFCNT); /* apply reset Tx FIFO count */
2971 sOutB(ChP->Cmd, (Byte_t) ChanNum); /* remove reset Tx FIFO count */
2972 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxFIFOPtrs); /* clear Tx in/out ptrs */
2973 sOutW(ChP->IndexData, 0);
2974 ChP->RxFIFOPtrs = ChOff + _RXF_OUTP;
2975 ChP->RxFIFO = ChOff + _RX_FIFO;
2976
2977 sOutB(ChP->Cmd, (Byte_t) ChanNum | RESRXFCNT); /* apply reset Rx FIFO count */
2978 sOutB(ChP->Cmd, (Byte_t) ChanNum); /* remove reset Rx FIFO count */
2979 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs); /* clear Rx out ptr */
2980 sOutW(ChP->IndexData, 0);
2981 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs + 2); /* clear Rx in ptr */
2982 sOutW(ChP->IndexData, 0);
2983 ChP->TxPrioCnt = ChOff + _TXP_CNT;
2984 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxPrioCnt);
2985 sOutB(ChP->IndexData, 0);
2986 ChP->TxPrioPtr = ChOff + _TXP_PNTR;
2987 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxPrioPtr);
2988 sOutB(ChP->IndexData, 0);
2989 ChP->TxPrioBuf = ChOff + _TXP_BUF;
2990 sEnRxProcessor(ChP); /* start the Rx processor */
2991
f15313bf 2992 return 1;
1da177e4
LT		 2993}
2994
2995/***************************************************************************
2996Function: sStopRxProcessor
2997Purpose: Stop the receive processor from processing a channel.
2998Call: sStopRxProcessor(ChP)
2999 CHANNEL_T *ChP; Ptr to channel structure
3000
3001Comments: The receive processor can be started again with sStartRxProcessor().
3002 This function causes the receive processor to skip over the
3003 stopped channel. It does not stop it from processing other channels.
3004
3005Warnings: No context switches are allowed while executing this function.
3006
3007 Do not leave the receive processor stopped for more than one
3008 character time.
3009
3010 After calling this function a delay of 4 uS is required to ensure
3011 that the receive processor is no longer processing this channel.
3012*/
f15313bf 3013static void sStopRxProcessor(CHANNEL_T * ChP)
1da177e4
LT		 3014{
3015 Byte_t R[4];
3016
3017 R[0] = ChP->R[0];
3018 R[1] = ChP->R[1];
3019 R[2] = 0x0a;
3020 R[3] = ChP->R[3];
457fb605 3021 out32(ChP->IndexAddr, R);
1da177e4
LT		 3022}
3023
3024/***************************************************************************
3025Function: sFlushRxFIFO
3026Purpose: Flush the Rx FIFO
3027Call: sFlushRxFIFO(ChP)
3028 CHANNEL_T *ChP; Ptr to channel structure
3029Return: void
3030Comments: To prevent data from being enqueued or dequeued in the Tx FIFO
3031 while it is being flushed the receive processor is stopped
3032 and the transmitter is disabled. After these operations a
3033 4 uS delay is done before clearing the pointers to allow
3034 the receive processor to stop. These items are handled inside
3035 this function.
3036Warnings: No context switches are allowed while executing this function.
3037*/
f15313bf 3038static void sFlushRxFIFO(CHANNEL_T * ChP)
1da177e4
LT		 3039{
3040 int i;
3041 Byte_t Ch; /* channel number within AIOP */
f15313bf 3042 int RxFIFOEnabled; /* 1 if Rx FIFO enabled */
1da177e4
LT		 3043
3044 if (sGetRxCnt(ChP) == 0) /* Rx FIFO empty */
3045 return; /* don't need to flush */
3046
f15313bf 3047 RxFIFOEnabled = 0;
1da177e4 3048 if (ChP->R[0x32] == 0x08) { /* Rx FIFO is enabled */
f15313bf 3049 RxFIFOEnabled = 1;
1da177e4
LT		 3050 sDisRxFIFO(ChP); /* disable it */
3051 for (i = 0; i < 2000 / 200; i++) /* delay 2 uS to allow proc to disable FIFO */
3052 sInB(ChP->IntChan); /* depends on bus i/o timing */
3053 }
3054 sGetChanStatus(ChP); /* clear any pending Rx errors in chan stat */
3055 Ch = (Byte_t) sGetChanNum(ChP);
3056 sOutB(ChP->Cmd, Ch | RESRXFCNT); /* apply reset Rx FIFO count */
3057 sOutB(ChP->Cmd, Ch); /* remove reset Rx FIFO count */
3058 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs); /* clear Rx out ptr */
3059 sOutW(ChP->IndexData, 0);
3060 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs + 2); /* clear Rx in ptr */
3061 sOutW(ChP->IndexData, 0);
3062 if (RxFIFOEnabled)
3063 sEnRxFIFO(ChP); /* enable Rx FIFO */
3064}
3065
3066/***************************************************************************
3067Function: sFlushTxFIFO
3068Purpose: Flush the Tx FIFO
3069Call: sFlushTxFIFO(ChP)
3070 CHANNEL_T *ChP; Ptr to channel structure
3071Return: void
3072Comments: To prevent data from being enqueued or dequeued in the Tx FIFO
3073 while it is being flushed the receive processor is stopped
3074 and the transmitter is disabled. After these operations a
3075 4 uS delay is done before clearing the pointers to allow
3076 the receive processor to stop. These items are handled inside
3077 this function.
3078Warnings: No context switches are allowed while executing this function.
3079*/
f15313bf 3080static void sFlushTxFIFO(CHANNEL_T * ChP)
1da177e4
LT		 3081{
3082 int i;
3083 Byte_t Ch; /* channel number within AIOP */
f15313bf 3084 int TxEnabled; /* 1 if transmitter enabled */
1da177e4
LT		 3085
3086 if (sGetTxCnt(ChP) == 0) /* Tx FIFO empty */
3087 return; /* don't need to flush */
3088
f15313bf 3089 TxEnabled = 0;
1da177e4 3090 if (ChP->TxControl[3] & TX_ENABLE) {
f15313bf 3091 TxEnabled = 1;
1da177e4
LT		 3092 sDisTransmit(ChP); /* disable transmitter */
3093 }
3094 sStopRxProcessor(ChP); /* stop Rx processor */
3095 for (i = 0; i < 4000 / 200; i++) /* delay 4 uS to allow proc to stop */
3096 sInB(ChP->IntChan); /* depends on bus i/o timing */
3097 Ch = (Byte_t) sGetChanNum(ChP);
3098 sOutB(ChP->Cmd, Ch | RESTXFCNT); /* apply reset Tx FIFO count */
3099 sOutB(ChP->Cmd, Ch); /* remove reset Tx FIFO count */
3100 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxFIFOPtrs); /* clear Tx in/out ptrs */
3101 sOutW(ChP->IndexData, 0);
3102 if (TxEnabled)
3103 sEnTransmit(ChP); /* enable transmitter */
3104 sStartRxProcessor(ChP); /* restart Rx processor */
3105}
3106
3107/***************************************************************************
3108Function: sWriteTxPrioByte
3109Purpose: Write a byte of priority transmit data to a channel
3110Call: sWriteTxPrioByte(ChP,Data)
3111 CHANNEL_T *ChP; Ptr to channel structure
3112 Byte_t Data; The transmit data byte
3113
3114Return: int: 1 if the bytes is successfully written, otherwise 0.
3115
3116Comments: The priority byte is transmitted before any data in the Tx FIFO.
3117
3118Warnings: No context switches are allowed while executing this function.
3119*/
f15313bf 3120static int sWriteTxPrioByte(CHANNEL_T * ChP, Byte_t Data)
1da177e4
LT		 3121{
3122 Byte_t DWBuf[4]; /* buffer for double word writes */
3123 Word_t *WordPtr; /* must be far because Win SS != DS */
3124 register DWordIO_t IndexAddr;
3125
3126 if (sGetTxCnt(ChP) > 1) { /* write it to Tx priority buffer */
3127 IndexAddr = ChP->IndexAddr;
3128 sOutW((WordIO_t) IndexAddr, ChP->TxPrioCnt); /* get priority buffer status */
3129 if (sInB((ByteIO_t) ChP->IndexData) & PRI_PEND) /* priority buffer busy */
3130 return (0); /* nothing sent */
3131
3132 WordPtr = (Word_t *) (&DWBuf[0]);
3133 *WordPtr = ChP->TxPrioBuf; /* data byte address */
3134
3135 DWBuf[2] = Data; /* data byte value */
457fb605 3136 out32(IndexAddr, DWBuf); /* write it out */
1da177e4
LT		 3137
3138 *WordPtr = ChP->TxPrioCnt; /* Tx priority count address */
3139
3140 DWBuf[2] = PRI_PEND + 1; /* indicate 1 byte pending */
3141 DWBuf[3] = 0; /* priority buffer pointer */
457fb605 3142 out32(IndexAddr, DWBuf); /* write it out */
1da177e4
LT		 3143 } else { /* write it to Tx FIFO */
3144
3145 sWriteTxByte(sGetTxRxDataIO(ChP), Data);
3146 }
3147 return (1); /* 1 byte sent */
3148}
3149
3150/***************************************************************************
3151Function: sEnInterrupts
3152Purpose: Enable one or more interrupts for a channel
3153Call: sEnInterrupts(ChP,Flags)
3154 CHANNEL_T *ChP; Ptr to channel structure
3155 Word_t Flags: Interrupt enable flags, can be any combination
3156 of the following flags:
3157 TXINT_EN: Interrupt on Tx FIFO empty
3158 RXINT_EN: Interrupt on Rx FIFO at trigger level (see
3159 sSetRxTrigger())
3160 SRCINT_EN: Interrupt on SRC (Special Rx Condition)
3161 MCINT_EN: Interrupt on modem input change
3162 CHANINT_EN: Allow channel interrupt signal to the AIOP's
3163 Interrupt Channel Register.
3164Return: void
3165Comments: If an interrupt enable flag is set in Flags, that interrupt will be
3166 enabled. If an interrupt enable flag is not set in Flags, that
3167 interrupt will not be changed. Interrupts can be disabled with
3168 function sDisInterrupts().
3169
3170 This function sets the appropriate bit for the channel in the AIOP's
3171 Interrupt Mask Register if the CHANINT_EN flag is set. This allows
3172 this channel's bit to be set in the AIOP's Interrupt Channel Register.
3173
3174 Interrupts must also be globally enabled before channel interrupts
3175 will be passed on to the host. This is done with function
3176 sEnGlobalInt().
3177
3178 In some cases it may be desirable to disable interrupts globally but
3179 enable channel interrupts. This would allow the global interrupt
3180 status register to be used to determine which AIOPs need service.
3181*/
f15313bf 3182static void sEnInterrupts(CHANNEL_T * ChP, Word_t Flags)
1da177e4
LT		 3183{
3184 Byte_t Mask; /* Interrupt Mask Register */
3185
3186 ChP->RxControl[2] |=
3187 ((Byte_t) Flags & (RXINT_EN | SRCINT_EN | MCINT_EN));
3188
457fb605 3189 out32(ChP->IndexAddr, ChP->RxControl);
1da177e4
LT		 3190
3191 ChP->TxControl[2] |= ((Byte_t) Flags & TXINT_EN);
3192
457fb605 3193 out32(ChP->IndexAddr, ChP->TxControl);
1da177e4
LT		 3194
3195 if (Flags & CHANINT_EN) {
3196 Mask = sInB(ChP->IntMask) | sBitMapSetTbl[ChP->ChanNum];
3197 sOutB(ChP->IntMask, Mask);
3198 }
3199}
3200
3201/***************************************************************************
3202Function: sDisInterrupts
3203Purpose: Disable one or more interrupts for a channel
3204Call: sDisInterrupts(ChP,Flags)
3205 CHANNEL_T *ChP; Ptr to channel structure
3206 Word_t Flags: Interrupt flags, can be any combination
3207 of the following flags:
3208 TXINT_EN: Interrupt on Tx FIFO empty
3209 RXINT_EN: Interrupt on Rx FIFO at trigger level (see
3210 sSetRxTrigger())
3211 SRCINT_EN: Interrupt on SRC (Special Rx Condition)
3212 MCINT_EN: Interrupt on modem input change
3213 CHANINT_EN: Disable channel interrupt signal to the
3214 AIOP's Interrupt Channel Register.
3215Return: void
3216Comments: If an interrupt flag is set in Flags, that interrupt will be
3217 disabled. If an interrupt flag is not set in Flags, that
3218 interrupt will not be changed. Interrupts can be enabled with
3219 function sEnInterrupts().
3220
3221 This function clears the appropriate bit for the channel in the AIOP's
3222 Interrupt Mask Register if the CHANINT_EN flag is set. This blocks
3223 this channel's bit from being set in the AIOP's Interrupt Channel
3224 Register.
3225*/
f15313bf 3226static void sDisInterrupts(CHANNEL_T * ChP, Word_t Flags)
1da177e4
LT		 3227{
3228 Byte_t Mask; /* Interrupt Mask Register */
3229
3230 ChP->RxControl[2] &=
3231 ~((Byte_t) Flags & (RXINT_EN | SRCINT_EN | MCINT_EN));
457fb605 3232 out32(ChP->IndexAddr, ChP->RxControl);
1da177e4 3233 ChP->TxControl[2] &= ~((Byte_t) Flags & TXINT_EN);
457fb605 3234 out32(ChP->IndexAddr, ChP->TxControl);
1da177e4
LT		 3235
3236 if (Flags & CHANINT_EN) {
3237 Mask = sInB(ChP->IntMask) & sBitMapClrTbl[ChP->ChanNum];
3238 sOutB(ChP->IntMask, Mask);
3239 }
3240}
3241
f15313bf 3242static void sSetInterfaceMode(CHANNEL_T * ChP, Byte_t mode)
1da177e4
LT		 3243{
3244 sOutB(ChP->CtlP->AiopIO[2], (mode & 0x18) | ChP->ChanNum);
3245}
3246
3247/*
3248 * Not an official SSCI function, but how to reset RocketModems.
3249 * ISA bus version
3250 */
f15313bf 3251static void sModemReset(CONTROLLER_T * CtlP, int chan, int on)
1da177e4
LT		 3252{
3253 ByteIO_t addr;
3254 Byte_t val;
3255
3256 addr = CtlP->AiopIO[0] + 0x400;
3257 val = sInB(CtlP->MReg3IO);
3258 /* if AIOP[1] is not enabled, enable it */
3259 if ((val & 2) == 0) {
3260 val = sInB(CtlP->MReg2IO);
3261 sOutB(CtlP->MReg2IO, (val & 0xfc) | (1 & 0x03));
3262 sOutB(CtlP->MBaseIO, (unsigned char) (addr >> 6));
3263 }
3264
3265 sEnAiop(CtlP, 1);
3266 if (!on)
3267 addr += 8;
3268 sOutB(addr + chan, 0); /* apply or remove reset */
3269 sDisAiop(CtlP, 1);
3270}
3271
3272/*
3273 * Not an official SSCI function, but how to reset RocketModems.
3274 * PCI bus version
3275 */
f15313bf 3276static void sPCIModemReset(CONTROLLER_T * CtlP, int chan, int on)
1da177e4
LT		 3277{
3278 ByteIO_t addr;
3279
3280 addr = CtlP->AiopIO[0] + 0x40; /* 2nd AIOP */
3281 if (!on)
3282 addr += 8;
3283 sOutB(addr + chan, 0); /* apply or remove reset */
3284}
3285
3286/* Resets the speaker controller on RocketModem II and III devices */
3287static void rmSpeakerReset(CONTROLLER_T * CtlP, unsigned long model)
3288{
3289 ByteIO_t addr;
3290
3291 /* RocketModem II speaker control is at the 8th port location of offset 0x40 */
3292 if ((model == MODEL_RP4M) || (model == MODEL_RP6M)) {
3293 addr = CtlP->AiopIO[0] + 0x4F;
3294 sOutB(addr, 0);
3295 }
3296
3297 /* RocketModem III speaker control is at the 1st port location of offset 0x80 */
3298 if ((model == MODEL_UPCI_RM3_8PORT)
3299 || (model == MODEL_UPCI_RM3_4PORT)) {
3300 addr = CtlP->AiopIO[0] + 0x88;
3301 sOutB(addr, 0);
3302 }
3303}
3304
3305/* Returns the line number given the controller (board), aiop and channel number */
3306static unsigned char GetLineNumber(int ctrl, int aiop, int ch)
3307{
3308 return lineNumbers[(ctrl << 5) | (aiop << 3) | ch];
3309}
3310
3311/*
3312 * Stores the line number associated with a given controller (board), aiop
3313 * and channel number.
3314 * Returns: The line number assigned
3315 */
3316static unsigned char SetLineNumber(int ctrl, int aiop, int ch)
3317{
3318 lineNumbers[(ctrl << 5) | (aiop << 3) | ch] = nextLineNumber++;
3319 return (nextLineNumber - 1);
3320}
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